From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id 578342EBAB for ; Thu, 16 Oct 2025 17:37:52 +0200 (CEST) Received: (qmail 17693 invoked by uid 550); 16 Oct 2025 15:37:49 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com x-ms-reactions: disallow Received: (qmail 17615 invoked from network); 16 Oct 2025 15:37:48 -0000 Message-ID: Date: Thu, 16 Oct 2025 23:37:36 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird To: musl@lists.openwall.com References: <20250918164720.337994-1-pincheng.plct@isrc.iscas.ac.cn> From: Pincheng Wang In-Reply-To: <20250918164720.337994-1-pincheng.plct@isrc.iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CM-TRANSID:zQCowAD3mBJAEfFolfN0Dw--.54691S2 X-Coremail-Antispam: 1UD129KBjvJXoWxJrWDZFyUAr15GF1xGw1xXwb_yoW8CF43pF W29w15GFWqgasrCas3Xwn7u3WrX3WFg3y3GF17t3s7Z34akF13KF18Kw1Yyas8Jr13CFW2 gr4UKr18GF1UArJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyjb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4 A2jsIEc7CjxVAFwI0_Jr0_Gr1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IE w4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMc vjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCF04k20xvY0x0EwIxGrwCFx2IqxVCF s4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r 1rMI8E67AF67kF1VAFwI0_Jr0_JrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWU JVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r 1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUv cSsGvfC2KfnxnUUI43ZEXa7IU5PpnJUUUUU== X-Originating-IP: [120.227.57.86] X-CM-SenderInfo: pslquxhhqjh1xofwqxxvufhxpvfd2hldfou0/ Subject: Re: [musl] [PATCH 0/1] riscv: Add support for Zacas in atomic operations On 2025/9/19 00:47, Pincheng Wang wrote: > Hi all, > > This patch adds support for the RISC-V Zacas (Atomic Compare-and-Swap) > extension in musl's atomic operations for both riscv64 and riscv32. > > Currently, musl implements a_cas using a > Load-Reserved/Store-Conditional (lr/sc) loop that: > - Requires at least four instructions (lr+bne+sc+bnez) per CAS > operation, > - Contains a retry loop under contention, > - Incurs branch penalties that may cause pipeline stalls. > > Zacas introduces amocas.w.aqrl/amocas.d.aqrl instructions that perform > CAS atomically in a single instruction, eliminating retry loops and > conditional branches. > > Due to hardware limitations, we evaluated this change under QEMU using > both mcycle and minstret counters. The results show clear benefits: > > Metric lr/sc Zacas Improvement > Instr. per CAS (50k ops average) 15.04 8.36 -44.4% > Instr. per op (single-thread) 23.61 14.25 -39.6% > Instr. per op (multi-thread, high contention) 528.24 251.14 -52.5% > > In addition, libc.a size is reduced by ~1.2% due to removal of loop > code. > > The patch automatically falls back to the lr/sc implementation on > systems where Zacas is not available, preserving full backward > compatibility. > > This work provides a measurable reduction in instruction count, > execution cycles and binary size, improving scalability of > synchronization primitives under load. > > Thanks for reviewing! > > Best regards, > Pincheng Wang > > > Pincheng Wang (1): > riscv: add Zacas extension support for atomic CAS > > arch/riscv32/atomic_arch.h | 17 +++++++++++++++++ > arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++ > 2 files changed, 47 insertions(+) > Hi all, Friendly ping regarding my earlier patch on enabling the RISC-V Zacas (amocas.{w,d}) path for a_cas()/a_cas_p(). Best regards, Pincheng Wang