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Designed by David Anto\v s, 2003]

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{\tfd\bf Project of IPv6 Router with FPGA Hardware Accelerator}
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{\bf Ji\v r\'{\i} Novotn\'y}\crlf
Institute of Computer Science\crlf
Masaryk University Brno\crlf
Botanick\'a~68a, Brno 602\thinspace00\crlf
Czech Republic\crlf
\type{novotny@liberouter.org}
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{\bf Otto Fu\v c\'{\i}k}\crlf
Faculty of Information Technology\crlf
Brno University of Technology\crlf
Bo\v{z}et\v{e}chova~2, Brno 612\thinspace66\crlf
Czech Republic\crlf
\type{fucik@liberouter.org}
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{\bf David Anto\v{s}}\crlf
Faculty of Informatics\crlf
Masaryk University Brno\crlf
Botanick\'a~68a, Brno 602\thinspace00\crlf
Czech Republic\crlf 
\type{antos@liberouter.org}

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\chapter{Introduction}

Personal Computer (PC) as a router is
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\item Reliable and highly functional
\item Comparable to middle-class routers (e.g., CISCO~7500)
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But\dots
\startitemize
\item Configurable with difficulties (via \type{/etc} files)
\item Limited mainly by PCI system bus (up to 2~Gbps with 64bit/66MHz bus)
\stopitemize

The goal of the \externalfigure[liberouter][height=0.5\baselineskip]{}
project: IPv6 router solving
those limitations. How?
\startitemize
\item Hardware accelerator {\em Combo6}
\item XML based configuration system {\em Netopeer}
\stopitemize

\chapter{Router Architecture}

Combo6 is a PCI card containing FPGA, memories (SSRAMs and DRAM), expansion
connectors, and supporting logic. Network interfaces are mounted on an
expansion daughter card for interfaces to be changed easily.

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Design rules (just pure instance of {\em hardware/software codesign}
principles):
\startitemize
\item Packet switching and filtering will be performed by Combo6
\item PC can do the rest; routing path calculations, configuration,
statistics computation
\item Communication through PCI is limited to configuration, routing table
updates, statistics collection, and exception handling
\item Usual Operating System tools can be used, like \type{ifconfig} and
routing daemons
\stopitemize

\chapter{Packet Processing in Hardware}

Key idea: Packet processing in FPGA is done by a chain of dedicated
processors with simple, specialized instruction sets designed for their
particular purposes. We call them {\em nanoprocessors}---they are
interpreted by FPGA's microcode. Instruction sets are \quotation{between
FSMs and RISC processors.}

\startitemize
\item Changing nanoprograms in runtime is possible (with no need of VHDL
compilation)---this differs from Partial Reconfiguration
\item VHDL tools are not needed to change nanoprograms, our free
development environment can be employed
\item New features can be added step-by-step
\item On the contrary, Partial Reconfiguration may produce more efficient
designs
\stopitemize

Packet processing is pipelined. A packet flows through the FPGA and
memories. An incoming packet is received by the Input Packet Buffer and
passed to the Header Field Extractor. The HFE pushes the body of the packet
into the dynamic memory. Meanwhile, it parses its headers and creates a
{\em Unified-header} and a structure reflecting actual arrangement of the
headers. The Unified-header is a fixed structure containing information
relevant for routing and filtering decisions.

The Lookup Processor (LUP) processes the Unified-header performing a lookup
nanoprogram. The lookup nanoprogram is kept in CAM and SRAM. Using CAM is
fast, unfortunately, IPv6 requires nearly 600~bits to check. Widest
available CAMs have less than 300~bits, therefore a combination of CAM
search and lookup instructions (conditional jumps) is used.

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Packet Replicator and Block of Output Queues (RQU) replicates the packet ID
to queues computed by LUP. Output Packet Editor modifies headers of the
packet before it is sent out. Operating system is one of the output
interfaces. It allows to deliver packets to the host computer as well as
handling packets hardware is not able to process.

\chapter{Software Support}

Software drivers are developed for NetBSD (and FreeBSD) and ported to
Linux. Driver operations include FPGA chip configuration, accessing
memories in the card, and hardware/software interface operations.

Other part of router software {\em hides presence of Combo6 in the host
computer}. The card should perform the same routing and filtering
functionality as the host computer itself, only faster. Host computer uses
routing table, configuration of interfaces, and firewall setting, Combo6
has to run the LUP nanoprocessor just once to make a decision how to handle
a packet.

To be able to combine routing table and firewall setting into one lookup
operation, we developed a concept of {\em routing/firewalling
table}---firewall rules are applied on routing table rows a-priori.

\chapter{Netopeer Configuration System}

PC based routers are running under various operating systems with various
configuration files causing problems to network administrators. To
overcome this we are working on a unified configuration environment {\em
Netopeer}. The primary configuration is kept in an XML repository. User
interfaces implement Command Line Interface, web interface, and SNMP.
Configurations for several operating systems and commercial routers can be
generated from the XML, also allowing to convert among the representations.

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\chapter{Acknowledgements}

This research is supported by the FP5 project {\em 6NET} (IST-2001-32603)
and CESNET project {\em IPv6 implementation in the CESNET2 network}
(02/2003).

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