PDP-11 Processor features/options (was HELP PDP-11 instruction)

PDP-11 Processor features/options (was HELP PDP-11 instruction)

[johnh]

I have updated my web page, fixing a few typos, and made more distinctions
between various processors, along with a table of 'obscure instructions'.

	http://www.psych.usyd.edu.au/pdp-11/table.html

Does anyone out there know the internal implementation details of the J11
chip. I assume it's micro sequenced, but what is the micro word length?


PS

I have found the 'PDP-11 Family Differences Table' (in the PDP-11 Architecture
Handbook and others) to be wrong in several places.

						Regards John


Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id PAA82835
	for pups-liszt; Thu, 11 May 2000 15:56:31 +1000 (EST)
Received: from Zeke.Update.UU.SE (IDENT:2026 at Zeke.Update.UU.SE [130.238.11.14])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with ESMTP id PAA82831
	for <PUPS at minnie.cs.adfa.edu.au>; Thu, 11 May 2000 15:56:18 +1000 (EST)
Received: from localhost (bqt at localhost)
	by Zeke.Update.UU.SE (8.8.8/8.8.8) with SMTP id HAA06288;
	Thu, 11 May 2000 07:56:03 +0200
Date: Thu, 11 May 2000 07:56:02 +0200 (MET DST)
From: Johnny Billquist <bqt@Update.UU.SE>
To: Tim Shoppa <SHOPPA at trailing-edge.com>
cc: PUPS at minnie.cs.adfa.edu.au
Subject: Re: Help: PDP-11 instruction classification (again!)
In-Reply-To: <000510130612.202009f2 at trailing-edge.com>
Message-ID: <Pine.VUL.3.93.1000511075207.6110D-100000 at Zeke.Update.UU.SE>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

On Wed, 10 May 2000, Tim Shoppa wrote:

> >J11 = KDJ-11A or KDJ-11B
> 
> And lots of other systems.  Some DEC peripherals (most noticably the
> early HSC storage controllers for VAXclusters) have J11's, several Xerox
> laserprinters used J11's, DEC PRO380's used J11's.  Many third-party
> CPU boards use J11's, it's not unusual to see them scrounging the used
> market for HSC's to strip the J11 from, as the HSC's generally had late-rev
> J11's.  (And Harris hasn't made the J11 chips for many years now.)

Actually, the first HSCs (HSC-50 and HSC-70) have an F11. Hmmm, a bit
unsure about the HSC-70 come to think of it. The HSC-50 is definitely F-11
anyway, and that's the oldest one. Boots of DECtape II. Slow as hell
because of it. :-)

> You can find T11 chips in several Q-bus and Unibus peripherals, most notably
> the RQDX1, 2, and 3 (the chip labeled "27-17311-01").

What cpu is in the DEUNA and DEQNA? I think those also have a T11.

> The CPU chipset used in the LSI-11/02 and /03 is a Western Digital chipset,
> and the same set was used (with different microcode) by other CPU makers.
> In particular, the Alpha Micro two-board S-100 set.

And I think DEC even supported the possibility of writing your own
microcode for this one.

	Johnny

Johnny Billquist                  || "I'm on a bus
                                  ||  on a psychedelic trip
email: bqt at update.uu.se           ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol


Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id QAA82993
	for pups-liszt; Thu, 11 May 2000 16:21:04 +1000 (EST)
Received: from junk.nocrew.org (mail@[212.73.17.42])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with ESMTP id QAA82989
	for <pups at minnie.cs.adfa.edu.au>; Thu, 11 May 2000 16:20:57 +1000 (EST)
Received: from lars by junk.nocrew.org with local (Exim 3.03 #1 (Debian))
	for pups at minnie.cs.adfa.edu.au
	id 12pmL6-0000Jw-00; Thu, 11 May 2000 08:20:52 +0200
To: pups at minnie.cs.adfa.edu.au
Subject: Obscure opcodes
From: lars brinkhoff <lars@nocrew.org>
Date: 11 May 2000 08:20:51 +0200
In-Reply-To: johnh at psych.usyd.edu.au's message of "Thu, 11 May 2000 09:23:18 +1000 (EST)"
Message-ID: <85vh0lwqt8.fsf at junk.nocrew.org>
Lines: 5
User-Agent: Gnus/5.0803 (Gnus v5.8.3) Emacs/20.5
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

Does anyone know that bit patterns these instructions use:
        commercial instruction set,
        FADD, FDIV, FMUL, FDIV, (and any other FIS instructions if any),
        LDUB, MED, XFC
?

Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id WAA84068
	for pups-liszt; Thu, 11 May 2000 22:04:37 +1000 (EST)
Received: from ns1.teraglobal.com (ns1.teraglobal.com [63.210.171.3])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with ESMTP id WAA84064
	for <pups at minnie.cs.adfa.edu.au>; Thu, 11 May 2000 22:04:29 +1000 (EST)
Received: from [10.10.50.26] (208.186.13.23) by ns1.teraglobal.com with ESMTP
 (Eudora Internet Mail Server 2.2.2); Thu, 11 May 2000 05:03:38 -0700
Mime-Version: 1.0
X-Sender: rivie at ns1.teraglobal.com
Message-Id: <v04210103b5404dc720f4@[10.10.50.26]>
In-Reply-To: <85vh0lwqt8.fsf at junk.nocrew.org>
References: <85vh0lwqt8.fsf at junk.nocrew.org>
Date: Thu, 11 May 2000 06:03:35 -0600
To: pups at minnie.cs.adfa.edu.au
From: Roger Ivie <rivie@teraglobal.com>
Subject: Re: Obscure opcodes
Content-Type: text/plain; charset="us-ascii" ; format="flowed"
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

>Does anyone know that bit patterns these instructions use:
>        commercial instruction set,

According to the PDP11/04/34a/44/60/70 processor handbook
(1979-1980),

addn 076050
addp 076070
addni 076150
addpi 076170

ashn 076056
ashp 076076
ashni 076156
ashpi 076176

cmpc 076044
cmpci 076144

cmpn 076052
cmpp 076072
cmpni 076152
cmppi 076172

cvtln 076057
cvtlp 076077
cvtlni 076157
cvtlpi 076177

cvtnl 076053
cvtpl 076073
cvtnli 076153
cvtpli 076173

cvtnp 076055
cvtpn 076054
cvtnpi 076155
cvtpni 076154

divp 076075
divpi 076175

locc 076040
locci 076140

l2dr 07602r

l3dr 07606r

matc 076045
matci 076145

movc 076030
movci 076130

movrc 076031
movrci 076131

movtc 076032
movtci 076132

mulp 076074
mulpi 076174

scanc 076042
scanci 076142

skpc 076041
skpci 076141

spanc 076043
spanci 076143

subn 076051
subp 076071
subni 076151
subpi 076171

>        FADD, FDIV, FMUL, FDIV, (and any other FIS instructions if any),

According to Microcomputer Handbook (1977-1978):

fadd 07500r
fsub 07501r
fmul 07502r
fdiv 07503r

and those are the only instructions listed under FIS.

>        LDUB, MED, XFC
>?

Back to 11/04/34a/44/60/70:

med 076600
ldub 170003
xfc 0767xy
  - x = "used for initial instruction group determination",
  - y = "further instruction determination"
     (this is a user-defined instruction via writable microcode in the 11/60).

-- 
Roger Ivie
TeraGlobal Communications Corporation
1750 North Research Park Way
North Logan, UT 84341
Phone: (435)787-0555
Fax: (435)787-0516

Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id WAA84207
	for pups-liszt; Thu, 11 May 2000 22:38:09 +1000 (EST)
Received: from timaxp.trailing-edge.com (timaxp.trailing-edge.com [63.73.218.130])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with SMTP id WAA84199
	for <PUPS at MINNIE.CS.ADFA.EDU.AU>; Thu, 11 May 2000 22:37:56 +1000 (EST)
Received: by timaxp.trailing-edge.com for PUPS at MINNIE.CS.ADFA.EDU.AU;
          Thu, 11 May 2000 8:37:50 -0400
Date: Thu, 11 May 2000 8:37:50 -0400
From: Tim Shoppa <SHOPPA@trailing-edge.com>
To: PUPS at minnie.cs.adfa.edu.au
Message-Id: <000511083750.20203768 at trailing-edge.com>
Subject: Re: Obscure opcodes
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

>>        LDUB, MED, XFC
>>?

>Back to 11/04/34a/44/60/70:
>
>med 076600

The MED instruction is used in RT-11 to determine if the machine is an
11/60.  It's probably also used in the 11/60-specific XXDP diagnostics.
I don't think that it's used in any of the -11 Unices.

Note that MED is really a two-word-long instruction.

>ldub 170003

My 11/60 Processor Handbook also lists MNS (170004), MNP (170005), and
MAS (170006).  These are "11/60 FP11-E Maintenance Instructions" and
"This set together with the LDUB instruction should be used for diagnostic
purposes only" according to the 11/60 book.

Note that no version of DEC MACRO-11 recognizes MNS, MNP, MAS, or LDUB.

The MED instruction is recognized in MACRO-11 only as MED6X.  The "6X"
jibes with the rumored existence of experimental variants on the 11/60
processor, one of which is the multi-processor 11/64.

-- 
 Tim Shoppa                        Email: shoppa at trailing-edge.com
 Trailing Edge Technology          WWW:   http://www.trailing-edge.com/
 7328 Bradley Blvd		   Voice: 301-767-5917
 Bethesda, MD, USA 20817           Fax:   301-767-5927


Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id WAA84206
	for pups-liszt; Thu, 11 May 2000 22:38:07 +1000 (EST)
Received: from junk.nocrew.org (mail@[212.73.17.42])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with ESMTP id WAA84198
	for <pups at minnie.cs.adfa.edu.au>; Thu, 11 May 2000 22:37:55 +1000 (EST)
Received: from lars by junk.nocrew.org with local (Exim 3.03 #1 (Debian))
	for pups at minnie.cs.adfa.edu.au
	id 12psDu-0001Yf-00; Thu, 11 May 2000 14:37:50 +0200
To: pups at minnie.cs.adfa.edu.au
Subject: Re: Obscure opcodes
References: <85vh0lwqt8.fsf at junk.nocrew.org> <v04210103b5404dc720f4@[10.10.50.26]>
From: lars brinkhoff <lars@nocrew.org>
Date: 11 May 2000 14:37:48 +0200
In-Reply-To: Roger Ivie's message of "Thu, 11 May 2000 06:03:35 -0600"
Message-ID: <857ld1w9cz.fsf at junk.nocrew.org>
Lines: 1
User-Agent: Gnus/5.0803 (Gnus v5.8.3) Emacs/20.5
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

Thank you all, now I have all the opcode information I need!

Received: (from major at localhost)
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) id XAA84380
	for pups-liszt; Thu, 11 May 2000 23:26:07 +1000 (EST)
Received: from europe.std.com (europe.std.com [199.172.62.20])
	by minnie.cs.adfa.edu.au (8.9.3/8.9.3) with ESMTP id XAA84376
	for <PUPS at minnie.cs.adfa.edu.au>; Thu, 11 May 2000 23:25:58 +1000 (EST)
From: allisonp@world.std.com
Received: from world.std.com (allisonp at world-f.std.com [199.172.62.5])
	by europe.std.com (8.9.3/8.9.3) with ESMTP id JAA16612;
	Thu, 11 May 2000 09:25:47 -0400 (EDT)
Received: from localhost (allisonp at localhost)
	by world.std.com (8.9.3/8.9.3) with SMTP id JAA01132;
	Thu, 11 May 2000 09:25:46 -0400 (EDT)
Date: Thu, 11 May 2000 09:25:45 -0400 (EDT)
To: Johnny Billquist <bqt at Update.UU.SE>
cc: Tim Shoppa <SHOPPA at trailing-edge.com>, PUPS at minnie.cs.adfa.edu.au
Subject: Re: Help: PDP-11 instruction classification (again!)
In-Reply-To: <Pine.VUL.3.93.1000511075207.6110D-100000 at Zeke.Update.UU.SE>
Message-ID: <Pine.SGI.3.95.1000511092245.25873A-100000 at world.std.com>
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
Sender: owner-pups at minnie.cs.adfa.edu.au
Precedence: bulk

> > You can find T11 chips in several Q-bus and Unibus peripherals, most notably
> > the RQDX1, 2, and 3 (the chip labeled "27-17311-01").
> 
> What cpu is in the DEUNA and DEQNA? I think those also have a T11.

I thought DEUNA was 68k and DEQNA is definatly state machines and random
logic no t11.  DELQA is 68k.

> > and the same set was used (with different microcode) by other CPU makers.
> > In particular, the Alpha Micro two-board S-100 set.
> 
> And I think DEC even supported the possibility of writing your own
> microcode for this one.

Yes there was a WCS that filled the FIS microm spot (and a full board
under it).

Allison