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[68.12.97.90]) by smtp.gmail.com with ESMTPSA id u186-20020aca60c3000000b0035bce2a39c7sm4881377oib.21.2022.12.13.10.51.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Dec 2022 10:51:10 -0800 (PST) Date: Tue, 13 Dec 2022 12:51:09 -0600 From: "G. Branden Robinson" To: tuhs@tuhs.org Message-ID: <20221213185109.663zv3usi5ey5jx6@illithid> References: <20221213175811.C1E8118C098@mercury.lcs.mit.edu> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="mlcfwozegydp5mx4" Content-Disposition: inline In-Reply-To: <20221213175811.C1E8118C098@mercury.lcs.mit.edu> Message-ID-Hash: K7AP65BAWHWEEICIEXGQRCJMM2PPUSQT X-Message-ID-Hash: K7AP65BAWHWEEICIEXGQRCJMM2PPUSQT X-MailFrom: g.branden.robinson@gmail.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-tuhs.tuhs.org-0; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [TUHS] Re: Clever code List-Id: The Unix Heritage Society mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: --mlcfwozegydp5mx4 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline At 2022-12-13T12:58:11-0500, Noel Chiappa wrote: > ... registers used to have two aspects - one now gone (and maybe > the second too). The first was that the _technology_ used to implement > them (latches built out of tubes, then transistors) was faster than > main memory - a distinction now mostly gone, especially since caches > blur the speed distinction between today's main memory and registers. > The second was that registers, being smaller in numbers, could be > named with a few bits, allowing them to be named with a small share of > the bits in an instruction. (This one still remains, although > instructions are now so long it's probably less important.) Maybe less important on x86, but the amount of space in the instruction for encoding registers seems to me to have played a major role in the design of the RV32I/E and C (compressed) extension instruction formats of RISC-V. https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf Regards, Branden --mlcfwozegydp5mx4 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEh3PWHWjjDgcrENwa0Z6cfXEmbc4FAmOYyZUACgkQ0Z6cfXEm bc7Pmg//YkXq9WwU7+au4w+vucwcU2RIHvgVK1DbwO0Tnf/C5Cd6BgFxFu02rvuQ 5dsrPZ60q2scXt49iuPBGLU8RVK8xTOn9Qk0OlCWrw0Jzj9A3eYSJCYAwAK/LW4R dAPo1zntbYWyeGXhYCQ3vEsjSo2dhtv71ustETL4AqOMfD1JJ0gSTXsqloOr1AL4 AjI4CW+MM+vY26KyICussTe08yTqYZ73kjBjl3GheMKjDnxbP7AGnhqwpxTNCddV hnKkjRDPIhQBxThv1ZUwjCqU0LUylWO80f4RgbzrTTNhBeQh7IQUCMmoqenX8xUx f7mIgb8O6UB7Hoo0nu4RU7YjxIn7AhYwxSLeWcmUDbLGu5UYl/vU2tZnoopSW+EI Tj9at2aSW15pybcpj+n6XKY1MNKoT98Tv1gvDE1dQ6vnWM+DfFKbP/g7wWLNgjyR WnjqcYvoLq6iFHGwenKrQzTVRJNcUEmbl/vkGt6NAwrWjJ8H/10rHjg1qhG2BmDo MXADMDKlyQ+aLkFg4wBqmNsOGlLvH3pFqCUh7H/VTqmQ89/9bOvZfvgNnt478WRw BDpTbUul/FvMcE44ZnP+Cq8t6ovrGU2C/5CWZ/fsr5z1Co52agVo6OIUcLIR93kT DuBv3QxesSsfKM74UQwGZ7FgFdYqvTiLyVGQsUf2H07HclCmfKA= =VJ0A -----END PGP SIGNATURE----- --mlcfwozegydp5mx4--