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From: Paul Ruizendaal <pnr@planet.nl>
To: TUHS main list <tuhs@minnie.tuhs.org>
Subject: [TUHS] Encoding an ISA: Random Logic vs. Control Stores
Date: Wed, 1 Dec 2021 14:59:45 +0100	[thread overview]
Message-ID: <219A3DE7-3DA1-4618-82B2-9354D63F93DF@planet.nl> (raw)

For DEC memo’s on designing the PDP-11 see bitsavers:

http://www.bitsavers.org/pdf/dec/pdp11/memos/

(thank you Bitsavers! I love that archive)

Ad van de Goor (author of a few of the memo’s) was my MSc thesis professor. I recall him saying in the early 80’s that in his view the PDP-11 should have been an 18-bit machine; he reasoned that even in the late 60’s it was obvious that 16-bits of address space was not enough for the lifespan of the design.

---

For those who want to experiment with FPGA’s and ancient ISA’s, here is my plain Verilog code for the TI 9995 chip, which has an instruction set that is highly reminiscent of the PDP-11:
https://gitlab.com/pnru/cortex/-/tree/master

The actual CPU code (TMS99095.v) is less than 1000 lines of code.

Paul


             reply	other threads:[~2021-12-01 14:02 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-01 13:59 Paul Ruizendaal [this message]
  -- strict thread matches above, loose matches on Subject: below --
2021-12-01 14:55 Douglas McIlroy
2021-12-01 20:27 ` Jon Steinhart
2021-12-01 21:14 ` Lawrence Stewart
2021-12-01 22:09   ` Jon Steinhart
2021-11-30  8:07 pbirkel
2021-11-30 15:19 ` Ron Natalie
2021-11-30 15:30   ` arnold
2021-11-30 15:39     ` Ralph Corderoy
2021-11-30 18:50     ` Jon Steinhart
2021-11-30 21:45       ` Humm
2021-11-30 23:07         ` Jon Steinhart
2021-11-30 23:18           ` Henry Bent
2021-12-01  5:00             ` Jon Steinhart
2021-12-01  6:27               ` pbirkel
2021-12-01 16:42                 ` ron minnich
2021-12-01 17:08                   ` Ron Natalie

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