From: Bakul Shah <bakul@iitbombay.org>
To: Will Senn <will.senn@gmail.com>
Cc: TUHS main list <tuhs@minnie.tuhs.org>
Subject: Re: [TUHS] Memory on Lion's v6
Date: Mon, 28 Feb 2022 17:25:09 -0800 [thread overview]
Message-ID: <85538B2F-7FDF-4D97-B7F0-F71977408D8F@iitbombay.org> (raw)
In-Reply-To: <4e3c05d2-2496-b917-f1f4-1c6cba9ef58a@gmail.com>
On Feb 27, 2022, at 9:48 PM, Will Senn <will.senn@gmail.com> wrote:
>
> It seems like he must have had an MMU and 128k memory,
This is covered in the Lions book. For instance
On the PDP11/40 the memory management unit consists of two
sets of registers for mapping virtual addresses to physical
addresses. These are known as “active page registers” or
“segmentation registers”. One set is used when the
processor is in user mode and the other set, in kernel
mode. Changing the contents of these registers changes the
details of these mappings. The ability to make these
changes is a privilege that the operating system keeps
firmly to itself.
Also see section 7 and in particular 7.9. And may be more!
next prev parent reply other threads:[~2022-03-01 1:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-28 5:48 Will Senn
2022-02-28 6:09 ` Warner Losh
2022-02-28 15:48 ` Clem Cole
2022-02-28 23:27 ` Andrew Hume
2022-03-01 15:31 ` Andrew Hume
2022-03-01 1:25 ` Bakul Shah [this message]
2022-03-01 0:44 Noel Chiappa
2022-03-02 1:19 Noel Chiappa
2022-03-02 2:15 ` Warner Losh
2022-03-02 2:26 Noel Chiappa
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