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From: Ronald Natalie <ron@ronnatalie.com>
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Date: Mon, 18 Jun 2018 08:39:29 -0400
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 <de343543-a222-e490-1cb0-cf59242a2684@update.uu.se>
To: Johnny Billquist <bqt@update.uu.se>
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Subject: Re: [TUHS] core
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> On Jun 18, 2018, at 1:58 AM, Johnny Billquist <bqt@update.uu.se> =
wrote:
>=20
> On 2018-06-18 04:00, Ronald Natalie <ron@ronnatalie.com> wrote:
>>> Well, it is an easy observable fact that before the PDP-11/70, all =
PDP-11 models had their memory on the Unibus. So it was not only "an =
ability at the lower end", b
>> That=E2=80=99s not quite true.   While the 18 bit addressed machines =
all had their memory directly accessible from the Unibus, the 45/50/55 =
had a separate bus for the (then new) semiconductor (bipolar or MOS) =
memory.
>=20
> Eh... Yes... But...
> The "separate" bus for the semiconductor memory is just a second =
Unibus, so the statement is still true. All (earlier) PDP-11 models had =
their memory on the Unibus. Including the 11/45,50,55.
> It's just that those models have two Unibuses.

No, you are confusing different things I think.   The fastbus (where the =
memory was) is a distinct bus.    The fastbus was dual ported with the =
CPU in one port and a second UNIBUS could be connected to the other =
port.