From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: tuhs-bounces@minnie.tuhs.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from minnie.tuhs.org (minnie.tuhs.org [45.79.103.53]) by inbox.vuxu.org (OpenSMTPD) with ESMTP id c705ffb0 for ; Sun, 23 Sep 2018 21:18:09 +0000 (UTC) Received: by minnie.tuhs.org (Postfix, from userid 112) id 2905AA1DE7; Mon, 24 Sep 2018 07:18:08 +1000 (AEST) Received: from minnie.tuhs.org (localhost [127.0.0.1]) by minnie.tuhs.org (Postfix) with ESMTP id 336A894119; Mon, 24 Sep 2018 07:17:41 +1000 (AEST) Authentication-Results: minnie.tuhs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=Cs0dwtvS; dkim-atps=neutral Received: by minnie.tuhs.org (Postfix, from userid 112) id DE785A1DCC; Mon, 24 Sep 2018 07:17:38 +1000 (AEST) Received: from mail-lj1-f195.google.com (mail-lj1-f195.google.com [209.85.208.195]) by minnie.tuhs.org (Postfix) with ESMTPS id 27AA494119 for ; Mon, 24 Sep 2018 07:17:38 +1000 (AEST) Received: by mail-lj1-f195.google.com with SMTP id f8-v6so16488216ljk.1 for ; Sun, 23 Sep 2018 14:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=jZjElxNX+v1BCQQTgLA9ji9YifJ57J+MI1fVc0xVse0=; b=Cs0dwtvS5gNDD9PHLQ/AJPAHsuzUc9NzGiy9Q0q/X8EF4MVcZdJ+fxvhc+I8G45f5Z Sdg5nZU0xajHG7+uzSCQKLf3SrYqlPnqZOiSF6sPIlSVNi8rdkJ5rCVsk30OObC5f0tW pbTu71SR3lUtiN8orW3G0JmV+cXrtBDXrpapQPPqthR8ck+gpc98n9P7ineApMC8YOCH 4kiA2JfyXL5vUewsiiEQdpE9cB4cFSuoP0eICCIE5eufTGAMcNpSa9/nuq8vPaM/PPTF 64wxX5WA4N4Vtys+GnAAo69Xu7h/YzH8hYGXbTvTHSkkSGESVq3nN6I4Ly8VbV+TecxZ lyfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=jZjElxNX+v1BCQQTgLA9ji9YifJ57J+MI1fVc0xVse0=; b=uDqG5DJgGqYIw6OuJz8VGi0NI0A86h+jNdX7NWhNxfikACMP3rJdO6P1cRhStg8sMK josnP+AzZiWiB1TnMTq2d31I7SrzgT/zXai7C5KUai13sb8h03d/1GSMLaMb3yVx0+Uf KRgMgMWgVn+w1CckMBK0GoB190SsGCrAqfogsyTHrZ1yUVDg1IkxMS0RUGYN/Xi/2P6A /KogxrbZYP8eK9c+mjYDhiJ4ztLlGT4IU/m9H/XlpEQfznE3VNqG7Hu6SUjBTTrmpxih DvybNN7F8Q6khPrPcvEbPDjXQ6+B/+q5rQyi2oeTlQOu+d9eYBjMkwNRhVYIcMrff6O2 kwJQ== X-Gm-Message-State: APzg51BNFWo0XOZVfaLzbDMlQQhSBuRfjYUz2WKt8YwfrDpAUQ81d/PM v3+nefyHoKO4movyLmlrB8DImonVzcMSYxqlh/k= X-Google-Smtp-Source: ANB0VdYh0+OvXaTUDtQEtleTjLaeCk0rQC7Y8zkKOj6BE//ryK72z7oTcV+lEWpPYmSaVZl5JqlYtJQMdXirln/yp4s= X-Received: by 2002:a2e:7d10:: with SMTP id y16-v6mr8224434ljc.29.1537737456371; Sun, 23 Sep 2018 14:17:36 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a2e:82cb:0:0:0:0:0 with HTTP; Sun, 23 Sep 2018 14:17:35 -0700 (PDT) In-Reply-To: References: <1686170E-4323-4BDF-B95C-8A6B3FFD5288@gmail.com> From: Paul Winalski Date: Sun, 23 Sep 2018 17:17:35 -0400 Message-ID: To: "A. P. Garcia" Content-Type: text/plain; charset="UTF-8" Subject: Re: [TUHS] SPARC is CRAPS spelled backwards. X-BeenThere: tuhs@minnie.tuhs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: The Unix Heritage Society mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tuhs@minnie.tuhs.org Errors-To: tuhs-bounces@minnie.tuhs.org Sender: "TUHS" On 9/23/18, A. P. Garcia wrote: > > In trying to steer this word salad towards some semblance of meaningful > discussion, is SPARC dead? Practically, yes, I would say so. Or at least it > seems to be heading in that direction. Is RISC dead? Not at all. ARM is > doing quite well, and the old "CISC vs RISC" thing seems to be a non-issue > now, as even the current x86 processors have adopted many design features > that originated in RISC research. In general, a CISC instruction set encoding can express the same algorithm more compactly than a RISC instruction set. Once CISC technology solved the instruction pipelining and decoding problem, it gained an advantage over RISC architectures such as Alpha because the instruction set stream was less verbose. Modern x86 designs have a bit of logic stuck in one corner that translates the x86 instruction stream into a string of RISC-style micro-operations. The cores execute the micro-ops. Micro-op sequences can be cached, so the translation is done only once for loops. The result is, as it were, the best of both worlds--the compactness of a CISC instruction stream and the simpler and faster circuitry of RISC. -Paul W.