From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FROM,HTML_MESSAGE,MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 26527 invoked from network); 26 Aug 2020 16:15:18 -0000 Received: from minnie.tuhs.org (45.79.103.53) by inbox.vuxu.org with ESMTPUTF8; 26 Aug 2020 16:15:18 -0000 Received: by minnie.tuhs.org (Postfix, from userid 112) id 61C1C9DF4E; Thu, 27 Aug 2020 02:15:13 +1000 (AEST) Received: from minnie.tuhs.org (localhost [127.0.0.1]) by minnie.tuhs.org (Postfix) with ESMTP id 4580293D54; Thu, 27 Aug 2020 02:14:48 +1000 (AEST) Authentication-Results: minnie.tuhs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mPvIMtZC"; dkim-atps=neutral Received: by minnie.tuhs.org (Postfix, from userid 112) id DE40193D54; Thu, 27 Aug 2020 02:14:44 +1000 (AEST) Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by minnie.tuhs.org (Postfix) with ESMTPS id C419C93D49 for ; Thu, 27 Aug 2020 02:14:43 +1000 (AEST) Received: by mail-wm1-f46.google.com with SMTP id b79so1757570wmb.4 for ; Wed, 26 Aug 2020 09:14:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fUC8u8FGxPS1PdBte9p7kQXKrLUpxwCKJtkUu0aTNo8=; b=mPvIMtZCmGZZJMDvcTZ8LeIDncU8GzhqGf5KgH6rRT6xHQOOfBl1i8AgnTUqWZ5pn3 v8TYssUyep+6d/hRx1PqrcZZTyFUmldg/G2+ujewWct94HlxWX+MEmmcAtWWRc85MPz7 VA/rkU+5jN2VSPSsI4LWstvnVKx+7DrJgA8IlF+20d5F0E2AEvNR9o1A9kL0j9PTMjlz ohb2zN/Kfiygw2yI0bGaBSzpKIlo1FHGdjOK+QPuytj7GiVcx3PDgG+HHQi73avHo4pe XrLSDCPCiiFJ3IZeYE+Lu1JxN+KmMJ7H0TNaFjwvSo2dbq8zab8zxf58fqhp6w7r34sZ jNzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fUC8u8FGxPS1PdBte9p7kQXKrLUpxwCKJtkUu0aTNo8=; b=f3u6qul/WeAXD8w/r3oriIKlwe9sy5/O6M6U/3E6PDkzzO/IMzDgOEJLnWoI0vOMMF xafNBUdbeMgApFRNdn9E4bhFdohD3XTBoaDYKDH2gp27kiZV8otixR7yVKobU1xK+jFj g99hRN43QsbftoxjMHINfMvMcK2iwZ0S6suIVJWaN7sVmODXmawqJH3uyX49svQE3y1u MnZLQLpxTmSX3O+4NxbDS4IwZzxf/F44t00JB9jC9vtR7nRDPB4c2L1P77qxrbNKtofw X2Vvct3sK5jXRMbA9MG2h7Da8T8SWRExijRK2RnZgKCSfeHQIybvkVcJRK3KgC82uTbH nMrw== X-Gm-Message-State: AOAM5313PseLGyBgKIEfg5uva3DbBuZhpeAfaiAUmgwuBrJp676eimbm RMBh8Qla0k6V1F+qy5SH0BqMi9HSrwCOwjhhnBKmXcPJwiw= X-Google-Smtp-Source: ABdhPJyl81YVLOweZzGPGL4C6B5z46hWXqu+lfawRse8xrxeCdjhK/UWCx7ow8Vevtj6MvBVorHCM5Ck5H7Ak9k119k= X-Received: by 2002:a1c:5a87:: with SMTP id o129mr4788283wmb.145.1598458482308; Wed, 26 Aug 2020 09:14:42 -0700 (PDT) MIME-Version: 1.0 References: <20200826155908.674C418C0CD@mercury.lcs.mit.edu> In-Reply-To: <20200826155908.674C418C0CD@mercury.lcs.mit.edu> From: Jim Geist Date: Wed, 26 Aug 2020 12:14:29 -0400 Message-ID: To: Noel Chiappa Content-Type: multipart/alternative; boundary="00000000000006c1fc05adca1e6c" Subject: Re: [TUHS] Memory management in Dennis Ritchie's C Compiler X-BeenThere: tuhs@minnie.tuhs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: The Unix Heritage Society mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: The Eunuchs Hysterical Society Errors-To: tuhs-bounces@minnie.tuhs.org Sender: "TUHS" --00000000000006c1fc05adca1e6c Content-Type: text/plain; charset="UTF-8" You're right. Modes 2 and 3 are post-increment and post-increment deferred. 4 and 5 are pre-decrement and pre-decrement deferred. On Wed, Aug 26, 2020 at 12:00 PM Noel Chiappa wrote: > > From: John Cowan > > > That's always true on the PDP-11 and Vax ... because the processor > > architecture (which has pre-increment and post-decrement > instructions, > > but not their counterparts) > > After Doug's message, I carefull re-read this, and I'm not sure it's > correct? > The PDP-11 has pre-decrement and post-increment, not the other way around > (as > above) - unless I'm misunderstanding what you meant by those terms? > > That's why: > > *p++ = 0; > > turns (if p is in R2) into > > CLR (R2)+ > > R2 is used, and then incremented after it has been used. > > Noel > --00000000000006c1fc05adca1e6c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
You're right. Modes 2 and 3 are post-increment and pos= t-increment deferred. 4 and 5 are pre-decrement and pre-decrement deferred.=

= On Wed, Aug 26, 2020 at 12:00 PM Noel Chiappa <jnc@mercury.lcs.mit.edu> wrote:
=C2=A0 =C2=A0 > From: John Cowa= n

=C2=A0 =C2=A0 > That's always true on the PDP-11 and Vax ... because= the processor
=C2=A0 =C2=A0 > architecture (which has pre-increment and post-decrement= instructions,
=C2=A0 =C2=A0 > but not their counterparts)

After Doug's message, I carefull re-read this, and I'm not sure it&= #39;s correct?
The PDP-11 has pre-decrement and post-increment, not the other way around (= as
above) - unless I'm misunderstanding what you meant by those terms?

That's why:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 *p++ =3D 0;

turns (if p is in R2) into

=C2=A0 =C2=A0 =C2=A0 =C2=A0 CLR=C2=A0 =C2=A0 =C2=A0(R2)+

R2 is used, and then incremented after it has been used.

=C2=A0 =C2=A0Noel
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