From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HTML_MESSAGE,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 25814 invoked from network); 26 Aug 2020 16:09:43 -0000 Received: from minnie.tuhs.org (45.79.103.53) by inbox.vuxu.org with ESMTPUTF8; 26 Aug 2020 16:09:43 -0000 Received: by minnie.tuhs.org (Postfix, from userid 112) id CF2479CAC3; Thu, 27 Aug 2020 02:09:41 +1000 (AEST) Received: from minnie.tuhs.org (localhost [127.0.0.1]) by minnie.tuhs.org (Postfix) with ESMTP id D3B1193D54; Thu, 27 Aug 2020 02:09:20 +1000 (AEST) Authentication-Results: minnie.tuhs.org; dkim=pass (2048-bit key; unprotected) header.d=bsdimp-com.20150623.gappssmtp.com header.i=@bsdimp-com.20150623.gappssmtp.com header.b="e2/yxlBq"; dkim-atps=neutral Received: by minnie.tuhs.org (Postfix, from userid 112) id A832793D54; Thu, 27 Aug 2020 02:09:19 +1000 (AEST) Received: from mail-qt1-f182.google.com (mail-qt1-f182.google.com [209.85.160.182]) by minnie.tuhs.org (Postfix) with ESMTPS id F14B393D49 for ; Thu, 27 Aug 2020 02:09:18 +1000 (AEST) Received: by mail-qt1-f182.google.com with SMTP id t20so1775196qtr.8 for ; Wed, 26 Aug 2020 09:09:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bsdimp-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vXPGqERyY2rRBfJsH/urWooSd9wutGH3CBctgeWb3vw=; b=e2/yxlBqjb9OH//3OfLdHM5HZMpz5m/M14GdFuW2mI5yFOJI0hWQM2z/aL1IAMX9CF EXngIRm6gGZTvU1s0Oikn35UUPTvICd/PmUXv6b+57UEpJHIcTB+z8rh7isgYrLawZxu E9kiQZuubEzBaxIsocZCvByr31kvIEGpki3MSV2mybWntwSqd9j0nSj8ijK6noZYU902 tSOmQVPMenyKhRvmqSNcQPgyZXnZ/T2QmIdpxKwsyv6432AOY2O7jfRhOqP5hIdzokGi pwAXvQ+lAu/7XFwWhMQ2G0XbwIsqoDlXyf9drW76xrlk/MgLRqLVyhHRhCTju+qaDxee QClA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vXPGqERyY2rRBfJsH/urWooSd9wutGH3CBctgeWb3vw=; b=sNqYUXPVGtsFqjK67kpz/86lgHpAmKj6+GyVOhAquwq4qKNzcnD7BmIwCdMpgVQYJV VxNckw4QOZLzbu6HZXpZJdK2Lu2GjYDyNrEYwdO38F6idPBjbN2gV5mUkGA24Ph3+C2h Kjw3JNAQylXLVo2rxcl+Ok8gGLjjMVLB9RCpMf/WFZzafETG93TMqEpfho4K0eCYTfJY 72tOqtTWbHqRihLEmi4zJVyNqmNADgkSrgH9pt2IYvhwbmmOhRKGp8Vc3AL9ZebsT8Xc zzLCwKW4PDIMILEk24Ku+vLe2Iy9dp+WcxmeDHBwGw6LgfHCkDeCt8C/H9vgEJaXe7lF HQvA== X-Gm-Message-State: AOAM5331LF+rZiJlftFlv8YbU22ulGjb1RYOW1r4HsqpkGId8Gj4rPtb J+pBpGgByUxLDx7NdCEFt73Cf6NuXQne2MPdBLxn5iKDsAk= X-Google-Smtp-Source: ABdhPJxriGOAsyfDnPFLT0MwcTFdi+UGiAEi0c4Oc8lWt6yhjyTzMAEHpdT6HTA9bKW2KcP5JNvUjaIuThPMyfAypL8= X-Received: by 2002:ac8:4719:: with SMTP id f25mr15024351qtp.291.1598458158024; Wed, 26 Aug 2020 09:09:18 -0700 (PDT) MIME-Version: 1.0 References: <20200826155908.674C418C0CD@mercury.lcs.mit.edu> In-Reply-To: <20200826155908.674C418C0CD@mercury.lcs.mit.edu> From: Warner Losh Date: Wed, 26 Aug 2020 10:09:06 -0600 Message-ID: To: Noel Chiappa Content-Type: multipart/alternative; boundary="000000000000b2a14005adca0a6c" Subject: Re: [TUHS] Memory management in Dennis Ritchie's C Compiler X-BeenThere: tuhs@minnie.tuhs.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: The Unix Heritage Society mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: The Eunuchs Hysterical Society Errors-To: tuhs-bounces@minnie.tuhs.org Sender: "TUHS" --000000000000b2a14005adca0a6c Content-Type: text/plain; charset="UTF-8" On Wed, Aug 26, 2020 at 9:59 AM Noel Chiappa wrote: > > From: John Cowan > > > That's always true on the PDP-11 and Vax ... because the processor > > architecture (which has pre-increment and post-decrement > instructions, > > but not their counterparts) > > After Doug's message, I carefull re-read this, and I'm not sure it's > correct? > The PDP-11 has pre-decrement and post-increment, not the other way around > (as > above) - unless I'm misunderstanding what you meant by those terms? > > That's why: > > *p++ = 0; > > turns (if p is in R2) into > > CLR (R2)+ > > R2 is used, and then incremented after it has been used. > This quirk of the PDP-11 is why I still prefer post-increment and pre-decrement in my code... even though there's no chance in hades that my code will ever run there... Warner --000000000000b2a14005adca0a6c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Wed, Aug 26, 2020 at 9:59 AM Noel = Chiappa <jnc@mercury.lcs.mit.= edu> wrote:
=C2=A0 =C2=A0 > From: John Cowan

=C2=A0 =C2=A0 > That's always true on the PDP-11 and Vax ... because= the processor
=C2=A0 =C2=A0 > architecture (which has pre-increment and post-decrement= instructions,
=C2=A0 =C2=A0 > but not their counterparts)

After Doug's message, I carefull re-read this, and I'm not sure it&= #39;s correct?
The PDP-11 has pre-decrement and post-increment, not the other way around (= as
above) - unless I'm misunderstanding what you meant by those terms?

That's why:

=C2=A0 =C2=A0 =C2=A0 =C2=A0 *p++ =3D 0;

turns (if p is in R2) into

=C2=A0 =C2=A0 =C2=A0 =C2=A0 CLR=C2=A0 =C2=A0 =C2=A0(R2)+

R2 is used, and then incremented after it has been used.

This quirk of the PDP-11 is why I still prefer post-incre= ment and pre-decrement in my code... even though there's no chance in h= ades that my code will ever run there...

Warner
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