[TUHS] Irix on MIPS -- was kernel mode paged

[TUHS] Irix on MIPS -- was kernel mode paged

[ron minnich]

I'm looking for a reference to any Unix ports where the kernel ran in
a non-paged address space and  user mode was paged. I could swear this
was done at some point, and memory says it was on a soft-TLB system
like the MIPS, to avoid TLB pollution and TLB fault overhead.

But maybe I'm nuts. I am happy to hear either answer.

Re: [TUHS] Irix on MIPS -- was kernel mode paged

[Warner Losh]

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On Thu, Nov 21, 2019, 2:12 PM ron minnich <rminnich@gmail.com> wrote:

> I'm looking for a reference to any Unix ports where the kernel ran in
> a non-paged address space and  user mode was paged. I could swear this
> was done at some point, and memory says it was on a soft-TLB system
> like the MIPS, to avoid TLB pollution and TLB fault overhead.
>
> But maybe I'm nuts. I am happy to hear either answer.
>

Mips had KSEG0 which didn't go through TLB and was mapped to physical
memory.  Some MIPS kernels ran in this space to avoid TLB issues...

Warner

>

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Re: [TUHS] Irix on MIPS -- was kernel mode paged

[ron minnich]

Ah thinks Warner, that was exactly what I was trying to recall.

And I am reminded as well how overloaded the term 'paged' is ... but
yeah, in this case, I was looking for examples where the kernel ran
with essentially no mmu but user programs did.

Note that on Alpha there was an identity mapped space with no MMU as
well but that was only for PAL mode and firmware that used PAL mode
(like LinuxBIOS).

On modern systems we have RISC-V with the no MMU M mode, and I just
got to thinking that running a kernel in M mode would be "what's old
is new again" :-)

Thanks


On Thu, Nov 21, 2019 at 7:24 PM Warner Losh <imp@bsdimp.com> wrote:
>
>
>
> On Thu, Nov 21, 2019, 2:12 PM ron minnich <rminnich@gmail.com> wrote:
>>
>> I'm looking for a reference to any Unix ports where the kernel ran in
>> a non-paged address space and  user mode was paged. I could swear this
>> was done at some point, and memory says it was on a soft-TLB system
>> like the MIPS, to avoid TLB pollution and TLB fault overhead.
>>
>> But maybe I'm nuts. I am happy to hear either answer.
>
>
> Mips had KSEG0 which didn't go through TLB and was mapped to physical memory.  Some MIPS kernels ran in this space to avoid TLB issues...
>
> Warner