From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: tuhs-bounces@minnie.tuhs.org X-Spam-Checker-Version: SpamAssassin 3.4.1 (2015-04-28) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham autolearn_force=no version=3.4.1 Received: from minnie.tuhs.org (minnie.tuhs.org [45.79.103.53]) by inbox.vuxu.org (OpenSMTPD) with ESMTP id e549efc1 for ; Tue, 26 Jun 2018 23:53:27 +0000 (UTC) Received: by minnie.tuhs.org (Postfix, from userid 112) id 70563A18AE; Wed, 27 Jun 2018 09:53:26 +1000 (AEST) Received: from minnie.tuhs.org (localhost [127.0.0.1]) by minnie.tuhs.org (Postfix) with ESMTP id 45F6FA183A; Wed, 27 Jun 2018 09:53:18 +1000 (AEST) Received: by minnie.tuhs.org (Postfix, from userid 112) id BEA75A183A; Wed, 27 Jun 2018 09:53:15 +1000 (AEST) Received: from mail.bitblocks.com (ns1.bitblocks.com [173.228.5.8]) by minnie.tuhs.org (Postfix) with ESMTP id 77F2EA181A for ; Wed, 27 Jun 2018 09:53:15 +1000 (AEST) Received: from mob.bitblocks.com (mob.bitblocks.com [192.168.125.11]) by mail.bitblocks.com (Postfix) with ESMTP id 2A126156E517; Tue, 26 Jun 2018 16:53:01 -0700 (PDT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.4 \(3445.8.2\)) From: Bakul Shah In-Reply-To: <769e0f86-eb90-0ec5-e744-319ab74dbd85@kilonet.net> Date: Tue, 26 Jun 2018 16:53:00 -0700 Content-Transfer-Encoding: quoted-printable Message-Id: References: <1f8043fd-e8d6-a5e6-5849-022d1a41f5bf@kilonet.net> <20180626215012.GE8150@mcvoy.com> <20180626215905.GH8150@mcvoy.com> <117BE24B-C768-43ED-A470-40FCD1662ECD@bitblocks.com> <769e0f86-eb90-0ec5-e744-319ab74dbd85@kilonet.net> To: Arthur Krewat X-Mailer: Apple Mail (2.3445.8.2) Subject: Re: [TUHS] PDP-11 legacy, C, and modern architectures X-BeenThere: tuhs@minnie.tuhs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: The Unix Heritage Society mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tuhs@minnie.tuhs.org Errors-To: tuhs-bounces@minnie.tuhs.org Sender: "TUHS" On Jun 26, 2018, at 3:33 PM, Arthur Krewat wrote: >=20 > On 6/26/2018 6:20 PM, Bakul Shah wrote: >> it is becoming increasingly clear that >> caching (hidden memory to continue with the illusion of a simple = memory >> model) itself is a potential security issue. >=20 > Then let's discuss why caching is the problem. If thread X reads = memory location A, why is thread Y able to access that cached value? = Shouldn't that cached value be associated with memory location A which I = would assume would be in a protected space that thread Y shouldn't be = able to access? >=20 > I know the nuts and bolts of how this cache exploit works, that's not = what I'm asking. >=20 > What I'm asking is, why is cache accessible in the first place? Any = cache offset should have the same memory protection as the value it = represents. Isn't this the CPU manufacturer's fault? As I understand it, the difference in cache access vs other caches/memory access times allows for timing attacks. By its nature a cache is much smaller than the next level cache or memory so there will have to be a way to evict stale data from it and there will be (false) sharing and consequent access time difference. Knowledge of specific attacks can help devise specific fixes but I don't think we can say unequivocally we have seen the worst of it.=20