[TUHS] Kartus's Software Demand Paging System?

[TUHS] Kartus's Software Demand Paging System?

[segaloco via TUHS]

I'm having trouble turning up info on something I recently read about.
For background, Basic-16 was the 8086 SGS developed in BTL for various
UNIX and telco experiments on Intel 8086 systems.  Like other SGSs, this
one includes a simulator, b16sim.  This simulator includes a "-p" option
to request that a "paged" version of the simulator be used.  This then
references a subsystem by J. S. Kartus:

> B16sim can be invoked in two versions.  There is an "incore" version which can
> address programs up to 32K bytes in length and a paged version which can
> address up to 1M bytes.  The paged version is implemented using the
> "Software Demand Paging" system of J. S. Kartus (see REFERENCES).

With the REFERENCES entry given as:

> J. S. Kartus, "Software Demand Paging User's Manual," 2523-781228.02MF.

Does anyone have any recollection of what precisely this subsystem
entailed and if it had any influence on later hardware demand paging
efforts inside BTL?  Thanks for any insights!

- Matt G.

[TUHS] Re: Kartus's Software Demand Paging System?

[Clem Cole via TUHS]

On Fri, Feb 13, 2026 at 2:44 PM segaloco via TUHS <tuhs@tuhs.org> wrote:

> I'm having trouble turning up info on something I recently read about.
> For background, Basic-16 was the 8086 SGS developed in BTL for various
> UNIX and telco experiments on Intel 8086 systems.  Like other SGSs, this
> one includes a simulator, b16sim.  This simulator includes a "-p" option
> to request that a "paged" version of the simulator be used.  This then
> references a subsystem by J. S. Kartus:
>

I remember reading a little about B16sim in a technical paper
published in October
1984 in the *AT&T Bell Laboratories Technical Journal* (Volume 63, Issue 8,
p. 1791). You can download a PDF of that paperat:
https://www.nokia.com/bell-labs/about/dennis-m-ritchie/otherports/newp.pdf

IIRC, the authors were using an 8086 and built their own base-limit
register MMU to get 2M into the system.  I wonder if they were using the
"pages" similarly to how DEC did in the PDP-11 databooks, which were 4096
bytes in size.  I'm referring to Chapter 6, Memory Management [Pages
135-169], in the 1981 Version of the PDP-11 Processor Handbook (the one
with a green cover with white letters). In fact, if you read the sections
about memory management, two of the most important registers are the PAR —
Page Address Register and the PDR — Page Descriptor Register

If you do turn up sources, that would be wonderful to add to the TUSH
archive.

Clem