From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: tuhs-bounces@minnie.tuhs.org X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from minnie.tuhs.org (minnie.tuhs.org [45.79.103.53]) by inbox.vuxu.org (OpenSMTPD) with ESMTP id d343c6b1 for ; Mon, 24 Sep 2018 11:26:22 +0000 (UTC) Received: by minnie.tuhs.org (Postfix, from userid 112) id B2E72A1DE9; Mon, 24 Sep 2018 21:26:21 +1000 (AEST) Received: from minnie.tuhs.org (localhost [127.0.0.1]) by minnie.tuhs.org (Postfix) with ESMTP id 0C940A1DCC; Mon, 24 Sep 2018 21:25:52 +1000 (AEST) Received: by minnie.tuhs.org (Postfix, from userid 112) id 5F3C7A1DCC; Mon, 24 Sep 2018 21:25:49 +1000 (AEST) Received: from ppsw-33.csi.cam.ac.uk (ppsw-33.csi.cam.ac.uk [131.111.8.133]) by minnie.tuhs.org (Postfix) with ESMTPS id 924C594119 for ; Mon, 24 Sep 2018 21:25:48 +1000 (AEST) X-Cam-AntiVirus: no malware found X-Cam-ScannerInfo: http://help.uis.cam.ac.uk/email-scanner-virus Received: from grey.csi.cam.ac.uk ([131.111.57.57]:40260) by ppsw-33.csi.cam.ac.uk (ppsw.cam.ac.uk [131.111.8.139]:25) with esmtps (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) id 1g4Ozq-000k8H-i4 (Exim 4.91) (return-path ); Mon, 24 Sep 2018 12:25:46 +0100 Date: Mon, 24 Sep 2018 12:25:46 +0100 From: Tony Finch To: Paul Winalski In-Reply-To: Message-ID: References: <1686170E-4323-4BDF-B95C-8A6B3FFD5288@gmail.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Subject: Re: [TUHS] SPARC is CRAPS spelled backwards. X-BeenThere: tuhs@minnie.tuhs.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: The Unix Heritage Society mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tuhs@minnie.tuhs.org Errors-To: tuhs-bounces@minnie.tuhs.org Sender: "TUHS" Paul Winalski wrote: > > In general, a CISC instruction set encoding can express the same > algorithm more compactly than a RISC instruction set. Once CISC > technology solved the instruction pipelining and decoding problem, it > gained an advantage over RISC architectures such as Alpha because the > instruction set stream was less verbose. It's more subtle than that, I think. One of the best contributions to this discussion was John Mashey's classic comp.arch article (which I originally read in 1994, I think) - https://yarchive.net/comp/risc_definition.html What is striking about it is that the two dominant architectures now are (very roughly) the least CISCy CISC and the least RISCy RISC. In particular x86 did not go in for elaborate addressing modes and highly orthogonal instruction sets that allow you to use the elaborate addressing modes multiple times in one instruction. (Compare it with later 68Ks, for contrast.) So the translation to RISC-style micro-ops does not end up with ridiculously long dependency chains within most instructions. Tony. -- f.anthony.n.finch http://dotat.at/ Shannon: South 3 or 4, increasing 5 to 7, perhaps gale 8 later. Moderate, becoming rough, then very rough later in far northwest. Fair then occasional rain. Good, becoming moderate, occasionally poor.