From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,MAILING_LIST_MULTI autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 8597 invoked from network); 13 Dec 2022 20:14:31 -0000 Received: from minnie.tuhs.org (50.116.15.146) by inbox.vuxu.org with ESMTPUTF8; 13 Dec 2022 20:14:31 -0000 Received: from minnie.tuhs.org (localhost [IPv6:::1]) by minnie.tuhs.org (Postfix) with ESMTP id 3BDFC42445; Wed, 14 Dec 2022 06:14:25 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuhs.org; s=dkim; t=1670962465; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:list-id:list-help: list-owner:list-unsubscribe:list-subscribe:list-post; bh=X0Wco0NS9B9t62BMSr5oP4V2FIvO9d9iw2g42WlAUUg=; b=K3YcRNhg6pXcBS1askjNDOSSDFPeeb+HwPEfg50n9/pgUVJOANTWbhgNOKiviNuqCrPdg0 IiV2fwPy44DTSfw+HBsPx7vOn39ZwyE+Lw97cW/qrwqD2hNlA4p+nogZMAnKnvyhz7k4fj R8rkqOFozP3qWEUKYdkrHud9YETd6Vk= Received: from mail-4027.protonmail.ch (mail-4027.protonmail.ch [185.70.40.27]) by minnie.tuhs.org (Postfix) with ESMTPS id E55BE4243D for ; Wed, 14 Dec 2022 06:14:20 +1000 (AEST) Date: Tue, 13 Dec 2022 20:14:07 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=protonmail.com; s=protonmail3; t=1670962458; x=1671221658; bh=X0Wco0NS9B9t62BMSr5oP4V2FIvO9d9iw2g42WlAUUg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Bmz+HqAJHMx5mgPV3PYoxboIW8B535ZE78imyPt33Ee1ru2i/STd6bBp1+0cd8QBd 0fkh08LJTCMD45LvgRnoPHUNt7hUjK02ZD8SsZS2xlMOohpvUkvtkXXs1hx9L6r5j+ M23WoI2QXhwyVCGp6oxmDD1Cu608DJLVdGCIjHczEdgjLAdEn5PMg1IqU9JCJry3dE 8ZdDnGzMXJw8gAN1S0yDFA6EbweqDo55BePtoh3J5Ol7pCsEF1E6DvpH+PNWubnjpR IFVElUhgS0drCWiaZKaBllCF5JcSk8GLWXBo4ONmVEMqR5aebPsnnxD9C9lZ956ARY 32kiEuzvwYsBg== To: "G. Branden Robinson" Message-ID: In-Reply-To: <20221213185109.663zv3usi5ey5jx6@illithid> References: <20221213175811.C1E8118C098@mercury.lcs.mit.edu> <20221213185109.663zv3usi5ey5jx6@illithid> Feedback-ID: 35591162:user:proton MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Message-ID-Hash: JH37WBIIZVU72R25OPBUS6RO2RH5ZEJH X-Message-ID-Hash: JH37WBIIZVU72R25OPBUS6RO2RH5ZEJH X-MailFrom: segaloco@protonmail.com X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-tuhs.tuhs.org-0; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header CC: tuhs@tuhs.org X-Mailman-Version: 3.3.6b1 Precedence: list Subject: [TUHS] Re: Clever code List-Id: The Unix Heritage Society mailing list Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: From: segaloco via TUHS Reply-To: segaloco Where RISC-V is very intentional on this, my reading has lead me to underst= and that many previous CPU architectures simply passed pieces of the opcode= to further hardware in the microarchitecture, so it wasn't so much of a de= sign a register system to fit in a specific bit width but rather a matter o= f bits 3-5 and 7-9 are connected directly to the two inputs of the ALU inte= rnally or something to that effect. Hearsay of course, I wasn't there, but= that's the explanation I've heard in the past. Now how much settling on a bit width for the register field of opcodes infl= uences the number of registers or vice versa, hard to say. Did Motorola wa= nt a 3 bit register field in opcodes or a resolution of 8 registers per add= ressing mode in the 68k first for instance, and which decision then followe= d? I don't know, maybe someone does? In fact, that makes me now wonder if= there are CPUs with non-power-of-two register counts outside of the early = days. Anything else would waste values in a bitfield. - Matt G. ------- Original Message ------- On Tuesday, December 13th, 2022 at 10:51 AM, G. Branden Robinson wrote: > At 2022-12-13T12:58:11-0500, Noel Chiappa wrote: >=20 > > ... registers used to have two aspects - one now gone (and maybe > > the second too). The first was that the technology used to implement > > them (latches built out of tubes, then transistors) was faster than > > main memory - a distinction now mostly gone, especially since caches > > blur the speed distinction between today's main memory and registers. > > The second was that registers, being smaller in numbers, could be > > named with a few bits, allowing them to be named with a small share of > > the bits in an instruction. (This one still remains, although > > instructions are now so long it's probably less important.) >=20 >=20 > Maybe less important on x86, but the amount of space in the instruction > for encoding registers seems to me to have played a major role in the > design of the RV32I/E and C (compressed) extension instruction formats > of RISC-V. >=20 > https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf >=20 > Regards, > Branden