* [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts
@ 2022-10-22 13:46 paper42
2022-11-20 18:48 ` [PR PATCH] [Updated] " paper42
` (19 more replies)
0 siblings, 20 replies; 21+ messages in thread
From: paper42 @ 2022-10-22 13:46 UTC (permalink / raw)
To: ml
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There is a new pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: update to 16.18.0, merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
This is a draft for now for comments and for checking if every package that used nodejs-lts still builds with nodejs 16.
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#### Testing the changes
- I tested the changes in this PR: **NO**
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A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
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From a09ff142795d0a6a693aac00c2e8fb752642d27a Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 16 Oct 2022 11:56:51 +0200
Subject: [PATCH 1/2] nodejs: update to 16.18.0
* merge with nodejs-lts, version 16 is the latest LTS version and
nodejs-lts contains an EOL LTS version 12
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ---------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 105 --
srcpkgs/nodejs-lts/update | 2 -
.../patches/ppc-fixes-for-older-models.patch | 972 ------------------
srcpkgs/nodejs/template | 22 +-
10 files changed, 19 insertions(+), 2001 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
delete mode 100644 srcpkgs/nodejs/patches/ppc-fixes-for-older-models.patch
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index 8a57b3958db8..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,105 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=2
-wrksrc="node-v${version}"
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 1d93341e8729..000000000000
--- a/srcpkgs/nodejs/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,972 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Use the current PPC_5_PLUS CPU feature to determine whether to generate
-FP round to int, and use the PPC_7_PLUS feature to determine whether
-to use the v2.06 ISA instructions or whether to generate an alternate
-generic PPC sequence to handle the cases of 64-bit unsigned integer
-to/from floating point, integers to single-precision floating point,
-and loading and storing 64-bit integers with byte reversal.
-
-Add a new PPC_7_PLUS_NXP feature for the popcnt and ldbrx/stdbrx
-opcodes added in Power ISA v2.06, which are also present in the NXP
-e5500 and e6500 cores, which are otherwise missing many of the
-features added since v2.01. This enables NXP cores to use a few
-more features. Additionally, bring back the ISELECT feature flag,
-which is also supported by NXP cores, including older ones, and
-has its own AT_HWCAP2 feature flag in Linux.
-
-By defining a new ICACHE_SNOOP feature bit to replace the use of
-PPC_6_PLUS, the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, is more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-08 04:37:48.000000000 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-19 14:38:37.997161835 -0800
-@@ -14,15 +14,13 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || \
-+ (V8_OS_LINUX && (V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64))
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
- #include <sys/syspage.h> // cpuinfo
- #endif
--#if V8_OS_LINUX && (V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64)
--#include <elf.h>
--#endif
- #if V8_OS_AIX
- #include <sys/systemcfg.h> // _system_configuration
- #ifndef POWER_8
-@@ -772,56 +770,55 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = base::Fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- base::Fclose(fp);
-- }
--
-- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = kPPCPower10;
-- } else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = kPPCPower9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = kPPCPower8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = kPPCPower7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = kPPCPower6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = kPPCPower5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = kPPCG5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = kPPCG4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = kPPCPA6T;
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-+
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = kPPCPower10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = kPPCPower9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = kPPCPower8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = kPPCPower7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = kPPCPower6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = kPPCPower5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = kPPCPA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = kPPCE6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = kPPCE5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = kPPCG5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = kPPCG4;
-+ } else {
-+ part_ = kPPCG3;
- }
-
- #elif V8_OS_AIX
-@@ -842,9 +839,13 @@
- part_ = kPPCPower6;
- break;
- case POWER_5:
-+ default:
- part_ = kPPCPower5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != kPPCPower5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
---- a/deps/v8/src/base/cpu.h 2022-02-08 04:37:48.000000000 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-19 14:32:09.831579133 -0800
-@@ -71,9 +71,12 @@
- kPPCPower8,
- kPPCPower9,
- kPPCPower10,
-+ kPPCG3,
- kPPCG4,
- kPPCG5,
-- kPPCPA6T
-+ kPPCPA6T,
-+ kPPCE5500,
-+ kPPCE6500
- };
-
- // General features
-@@ -119,6 +122,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- #if defined(V8_OS_STARBOARD)
- bool StarboardDetectCPU();
-@@ -166,6 +173,8 @@
- bool has_non_stop_time_stamp_counter_;
- bool is_running_in_vm_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/builtins/ppc/builtins-ppc.cc 2022-02-08 04:37:48.000000000 -0800
-+++ b/deps/v8/src/builtins/ppc/builtins-ppc.cc 2022-02-19 15:18:36.373031457 -0800
-@@ -2823,7 +2823,7 @@
- __ lbz(scratch, MemOperand(scratch, 0));
- __ cmpi(scratch, Operand::Zero());
-
-- if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (CpuFeatures::IsSupported(ISELECT)) {
- __ Move(scratch, thunk_ref);
- __ isel(eq, scratch, function_address, scratch);
- } else {
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-19 18:45:44.687593194 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-19 18:33:15.060674389 -0800
-@@ -925,13 +925,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -943,20 +955,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -986,15 +1030,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ orx(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2459,19 +2544,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2485,18 +2568,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2510,18 +2591,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2536,16 +2615,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2560,12 +2637,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2580,12 +2655,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2599,12 +2672,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2615,11 +2686,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2631,11 +2700,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2650,32 +2717,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::AddS64(Register dst, Register src, Register value, OEBit s,
-@@ -3189,10 +3250,8 @@
- }
-
- #define MEM_LE_OP_LIST(V) \
-- V(LoadU64, ldbrx) \
- V(LoadU32, lwbrx) \
- V(LoadU16, lhbrx) \
-- V(StoreU64, stdbrx) \
- V(StoreU32, stwbrx) \
- V(StoreU16, sthbrx)
-
-@@ -3214,6 +3273,37 @@
- #undef MEM_LE_OP_FUNCTION
- #undef MEM_LE_OP_LIST
-
-+void TurboAssembler::LoadU64LE(Register dst, const MemOperand& mem,
-+ Register scratch) {
-+#ifdef V8_TARGET_BIG_ENDIAN
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS_NXP)) {
-+ GenerateMemoryLEOperation(dst, mem, ldbrx);
-+ } else {
-+ lwbrx(dst, mem);
-+ lwbrx(scratch, MemOperand(mem.ra(), mem.rb(), mem.offset() + 4));
-+ rldicr(scratch, scratch, 32, 31);
-+ orx(dst, dst, scratch);
-+ }
-+#else
-+ LoadU64(dst, mem, scratch);
-+#endif
-+}
-+
-+void TurboAssembler::StoreU64LE(Register src, const MemOperand& mem,
-+ Register scratch) {
-+#ifdef V8_TARGET_BIG_ENDIAN
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS_NXP)) {
-+ GenerateMemoryLEOperation(src, mem, stdbrx);
-+ } else {
-+ stwbrx(src, mem);
-+ rldicl(scratch, src, 32, 32);
-+ stwbrx(scratch, MemOperand(mem.ra(), mem.rb(), mem.offset() + 4));
-+ }
-+#else
-+ StoreU64(src, mem, scratch);
-+#endif
-+}
-+
- void TurboAssembler::LoadS32LE(Register dst, const MemOperand& mem,
- Register scratch) {
- #ifdef V8_TARGET_BIG_ENDIAN
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-19 21:19:15.982288690 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-19 21:22:43.071487369 -0800
-@@ -52,11 +52,15 @@
- MIPS_SIMD, // MSA instructions
-
- #elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
-+ PPC_5_PLUS,
- PPC_6_PLUS,
- PPC_7_PLUS,
- PPC_8_PLUS,
- PPC_9_PLUS,
- PPC_10_PLUS,
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS_NXP, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-
- #elif V8_TARGET_ARCH_S390X
- FPU,
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-20 23:35:21.212337639 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-20 23:36:20.925858840 -0800
-@@ -2702,16 +2702,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(PPC_5_PLUS)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS_NXP)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
---- a/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc 2022-02-20 23:35:21.216337741 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/code-generator-ppc.cc 2022-02-20 23:39:56.479351482 -0800
-@@ -785,6 +785,7 @@
- // Calculate a mask which has all bits set in the normal case, but has all
- // bits cleared if we are speculatively executing the wrong PC.
- __ CmpS64(kJavaScriptCallCodeStartRegister, scratch);
-+ // TODO: is alternate sequence needed for CPUs without isel?
- __ li(scratch, Operand::Zero());
- __ notx(kSpeculationPoisonRegister, scratch);
- __ isel(eq, kSpeculationPoisonRegister, kSpeculationPoisonRegister, scratch);
-@@ -1823,6 +1824,7 @@
- int crbit = v8::internal::Assembler::encode_crbit(
- cr, static_cast<CRBit>(VXCVI % CRWIDTH));
- __ mcrfs(cr, VXCVI); // extract FPSCR field containing VXCVI into cr7
-+ // TODO: is alternate sequence needed for CPUs without isel?
- __ li(kScratchReg, Operand(1));
- __ ShiftLeftU64(kScratchReg, kScratchReg,
- Operand(31)); // generate INT32_MIN.
-@@ -1844,6 +1846,7 @@
- int crbit = v8::internal::Assembler::encode_crbit(
- cr, static_cast<CRBit>(VXCVI % CRWIDTH));
- __ mcrfs(cr, VXCVI); // extract FPSCR field containing VXCVI into cr7
-+ // TODO: is alternate sequence needed for CPUs without isel?
- __ li(kScratchReg, Operand::Zero());
- __ isel(i.OutputRegister(0), kScratchReg, i.OutputRegister(0), crbit);
- }
-@@ -1868,7 +1871,7 @@
- cr, static_cast<CRBit>(VXCVI % CRWIDTH));
- __ mcrfs(cr, VXCVI); // extract FPSCR field containing VXCVI into cr7
- // Handle conversion failures (such as overflow).
-- if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (CpuFeatures::IsSupported(ISELECT)) {
- if (check_conversion) {
- __ li(i.OutputRegister(1), Operand(1));
- __ isel(i.OutputRegister(1), r0, i.OutputRegister(1), crbit);
-@@ -1905,7 +1908,7 @@
- int crbit = v8::internal::Assembler::encode_crbit(
- cr, static_cast<CRBit>(VXCVI % CRWIDTH));
- __ mcrfs(cr, VXCVI); // extract FPSCR field containing VXCVI into cr7
-- if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (CpuFeatures::IsSupported(ISELECT)) {
- __ li(i.OutputRegister(1), Operand(1));
- __ isel(i.OutputRegister(1), r0, i.OutputRegister(1), crbit);
- } else {
-@@ -2168,12 +2171,67 @@
- break;
- }
- case kPPC_LoadByteRev64: {
-- ASSEMBLE_LOAD_INTEGER_RR(ldbrx);
-+ // inlined version of ASSEMBLE_LOAD_INTEGER_RR()
-+ Register result = i.OutputRegister();
-+ AddressingMode mode = kMode_None;
-+ MemOperand operand = i.MemoryOperand(&mode);
-+ DCHECK_EQ(mode, kMode_MRR);
-+ bool is_atomic = i.InputInt32(2);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS_NXP)) {
-+ __ ldbrx(result, operand);
-+ } else {
-+#ifdef V8_TARGET_BIG_ENDIAN
-+ // low and high words from reversed perspective
-+ MemOperand op_low = operand;
-+ MemOperand op_high = MemOperand(operand.ra(), operand.rb(),
-+ operand.offset() + 4);
-+#else
-+ // low and high words from reversed perspective
-+ MemOperand op_high = operand;
-+ MemOperand op_low = MemOperand(operand.ra(), operand.rb(),
-+ operand.offset() + 4);
-+#endif
-+ Register temp1 = r0;
-+ __ lwbrx(result, op_low);
-+ __ lwbrx(temp1, op_high);
-+ __ rldicr(temp1, temp1, 32, 31);
-+ __ orx(result, result, temp1);
-+ }
-+ if (is_atomic) __ lwsync();
-+ DCHECK_EQ(LeaveRC, i.OutputRCBit());
- EmitWordLoadPoisoningIfNeeded(this, instr, i);
- break;
- }
- case kPPC_StoreByteRev64: {
-- ASSEMBLE_STORE_INTEGER_RR(stdbrx);
-+ // inlined version of ASSEMBLE_STORE_INTEGER_RR()
-+ size_t index = 0;
-+ AddressingMode mode = kMode_None;
-+ MemOperand operand = i.MemoryOperand(&mode, &index);
-+ DCHECK_EQ(mode, kMode_MRR);
-+ Register value = i.InputRegister(index);
-+ bool is_atomic = i.InputInt32(3);
-+ if (is_atomic) __ lwsync();
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS_NXP)) {
-+ __ stdbrx(value, operand);
-+ } else {
-+#ifdef V8_TARGET_BIG_ENDIAN
-+ // low and high words from reversed perspective
-+ MemOperand op_low = operand;
-+ MemOperand op_high = MemOperand(operand.ra(), operand.rb(),
-+ operand.offset() + 4);
-+#else
-+ // low and high words from reversed perspective
-+ MemOperand op_high = operand;
-+ MemOperand op_low = MemOperand(operand.ra(), operand.rb(),
-+ operand.offset() + 4);
-+#endif
-+ Register temp1 = r0;
-+ __ stwbrx(value, op_low);
-+ __ rldicl(temp1, value, 32, 32);
-+ __ stwbrx(temp1, op_high);
-+ }
-+ if (is_atomic) __ sync();
-+ DCHECK_EQ(LeaveRC, i.OutputRCBit());
- break;
- }
- case kPPC_F64x2Splat: {
-@@ -2911,11 +2969,13 @@
- __ li(ip, Operand(1));
- // Check if both lanes are 0, if so then return false.
- __ vxor(kScratchSimd128Reg, kScratchSimd128Reg, kScratchSimd128Reg);
-+ // TODO: is alternate sequence needed for CPUs without isel?
- __ mtcrf(r0, fxm); // Clear cr6.
- __ vcmpequd(kScratchSimd128Reg, src, kScratchSimd128Reg, SetRC);
- __ isel(dst, r0, ip, bit_number);
- break;
- }
-+// TODO: is alternate sequence needed for CPUs without isel?
- #define SIMD_ALL_TRUE(opcode) \
- Simd128Register src = i.InputSimd128Register(0); \
- Register dst = i.OutputRegister(); \
-@@ -3809,6 +3869,7 @@
-
- ArchOpcode op = instr->arch_opcode();
- condition = NegateFlagsCondition(condition);
-+ // TODO: is alternate sequence needed for CPUs without isel?
- __ li(kScratchReg, Operand::Zero());
- __ isel(FlagsConditionToCondition(condition, op), kSpeculationPoisonRegister,
- kScratchReg, kSpeculationPoisonRegister, cr0);
-@@ -3922,7 +3983,7 @@
- // Unnecessary for eq/lt & ne/ge since only FU bit will be set.
- }
-
-- if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (CpuFeatures::IsSupported(ISELECT)) {
- switch (cond) {
- case eq:
- case lt:
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-08 04:37:48.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-20 17:02:17.900000785 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY PPC_6_PLUS
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
---- ./deps/v8/src/codegen/ppc/assembler-ppc.cc.orig 2022-02-08 04:37:48.000000000 -0800
-+++ ./deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-20 17:20:25.019591225 -0800
-@@ -65,6 +65,7 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-@@ -73,6 +74,8 @@
- #ifdef USE_SIMULATOR
- // Simulator
- supported_ |= (1u << PPC_10_PLUS);
-+ supported_ |= (1u << ICACHE_SNOOP);
-+ supported_ |= (1u << ISELECT);
- #else
- base::CPU cpu;
- if (cpu.part() == base::CPU::kPPCPower10) {
-@@ -85,17 +88,37 @@
- supported_ |= (1u << PPC_7_PLUS);
- } else if (cpu.part() == base::CPU::kPPCPower6) {
- supported_ |= (1u << PPC_6_PLUS);
-+ } else if (cpu.part() == base::CPU::kPPCPower5 ||
-+ cpu.part() == base::CPU::kPPCPA6T) {
-+ supported_ |= (1u << PPC_5_PLUS);
-+ } else if (cpu.part() == base::CPU::kPPCE6500 ||
-+ cpu.part() == base::CPU::kPPCE5500) {
-+ supported_ |= (1u << PPC_7_PLUS_NXP); // NXP-supported v2.06 features
-+ }
-+
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP);
-+ }
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT);
- }
- #if V8_OS_LINUX
- if (cpu.icache_line_size() != base::CPU::kUnknownCacheLineSize) {
- icache_line_size_ = cpu.icache_line_size();
- }
-+ if (cpu.dcache_line_size() != base::CPU::kUnknownCacheLineSize) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #endif
- #endif
- if (supported_ & (1u << PPC_10_PLUS)) supported_ |= (1u << PPC_9_PLUS);
- if (supported_ & (1u << PPC_9_PLUS)) supported_ |= (1u << PPC_8_PLUS);
- if (supported_ & (1u << PPC_8_PLUS)) supported_ |= (1u << PPC_7_PLUS);
-- if (supported_ & (1u << PPC_7_PLUS)) supported_ |= (1u << PPC_6_PLUS);
-+ if (supported_ & (1u << PPC_7_PLUS)) {
-+ supported_ |= (1u << PPC_7_PLUS_NXP); // NXP-supported v2.06 features
-+ supported_ |= (1u << PPC_6_PLUS);
-+ }
-+ if (supported_ & (1u << PPC_6_PLUS)) supported_ |= (1u << PPC_5_PLUS);
-
- // Set a static value on whether Simd is supported.
- // This variable is only used for certain archs to query SupportWasmSimd128()
-@@ -117,11 +140,15 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-+ printf("PPC_5_PLUS=%d\n", CpuFeatures::IsSupported(PPC_5_PLUS));
- printf("PPC_6_PLUS=%d\n", CpuFeatures::IsSupported(PPC_6_PLUS));
- printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
- printf("PPC_8_PLUS=%d\n", CpuFeatures::IsSupported(PPC_8_PLUS));
- printf("PPC_9_PLUS=%d\n", CpuFeatures::IsSupported(PPC_9_PLUS));
- printf("PPC_10_PLUS=%d\n", CpuFeatures::IsSupported(PPC_10_PLUS));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("PPC_7_PLUS_NXP=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS_NXP));
- }
-
- Register ToRegister(int num) {
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index 1e636ca21c46..851523278bcc 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
-version=16.15.1
-revision=2
+version=16.18.0
+revision=1
wrksrc="node-v${version}"
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
@@ -16,7 +16,7 @@ maintainer="Enno Boland <gottox@voidlinux.org>"
license="MIT"
homepage="https://nodejs.org/"
distfiles="https://nodejs.org/dist/v${version}/node-v${version}.tar.gz"
-checksum=308aee7149c4092a53c87c28ef49e23a8d1606119e79ae68333062e2a1f94208
+checksum=276c8a469bd4013c5842ee4166fb9b0087e5ee252a7c932d97e274b77ba73e70
python_version=3
build_options="ssl libuv icu nghttp2 cares"
@@ -28,7 +28,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -101,8 +101,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From f855f8a25de9a3ca13c9f3a57539f4a3d81c9e21 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 16 Oct 2022 13:04:29 +0200
Subject: [PATCH 2/2] chronograf: update to 1.10.0.
---
srcpkgs/chronograf/template | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/srcpkgs/chronograf/template b/srcpkgs/chronograf/template
index 5dfcc1c3ef7c..f0093b5a8508 100644
--- a/srcpkgs/chronograf/template
+++ b/srcpkgs/chronograf/template
@@ -1,18 +1,18 @@
# Template file for 'chronograf'
pkgname=chronograf
-version=1.9.4
+version=1.10.0
revision=1
build_style=go
go_import_path="github.com/influxdata/${pkgname}"
go_package="${go_import_path}/cmd/chronograf"
go_ldflags="-X main.version=${version}"
-hostmakedepends="dep go-bindata nodejs-lts yarn"
+hostmakedepends="dep go-bindata nodejs yarn python3"
short_desc="Open source monitoring and visualization UI for the TICK stack"
maintainer="Michael Aldridge <maldridge@voidlinux.org>"
license="AGPL-3.0-or-later"
homepage="https://www.influxdata.com/time-series-platform/chronograf/"
distfiles="https://github.com/influxdata/${pkgname}/archive/${version}.tar.gz"
-checksum=ff294f25a9de57140024b9953992c1a4d79ec88167ad28435645d888a0096c27
+checksum=4c9ec541a77314b11f23f2eff1394568ea9180f1f3cc3f098cb3e7977dbfd7a5
system_accounts="_chronograf"
_chronograf_homedir="/var/lib/${pkgname}"
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: update to 16.18.0, merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
@ 2022-11-20 18:48 ` paper42
2022-11-25 20:21 ` nodejs: " leahneukirchen
` (18 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2022-11-20 18:48 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 2004 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: update to 16.18.0, merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
This is a draft for now for comments and for checking if every package that used nodejs-lts still builds with nodejs 16.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 39938 bytes --]
From 3ff7554b45c938922f555cf810fce513374b6512 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 18 +-
9 files changed, 17 insertions(+), 1026 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index 5420e8524442..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=2
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index c2f4d4eb340f..19a5befed667 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
version=16.15.1
-revision=2
+revision=3
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
$(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
2022-11-20 18:48 ` [PR PATCH] [Updated] " paper42
@ 2022-11-25 20:21 ` leahneukirchen
2022-12-07 8:02 ` [PR PATCH] [Updated] " paper42
` (17 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: leahneukirchen @ 2022-11-25 20:21 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 310 bytes --]
New comment by leahneukirchen on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1327865721
Comment:
Hmm, I think we had the `-lts` because some packages needed a really old Node (but I thought, like, Node 8). If that's not the case anymore, we can just drop it.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
2022-11-20 18:48 ` [PR PATCH] [Updated] " paper42
2022-11-25 20:21 ` nodejs: " leahneukirchen
@ 2022-12-07 8:02 ` paper42
2022-12-15 17:12 ` akierig
` (16 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2022-12-07 8:02 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1985 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
This is a draft for now for comments and for checking if every package that used nodejs-lts still builds with nodejs 16.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 53998 bytes --]
From 41be3b48bbc1a435e8204b1dfa594a5f9b5b97fa Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH 1/6] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 18 +-
9 files changed, 17 insertions(+), 1026 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index 5420e8524442..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=2
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index c2f4d4eb340f..19a5befed667 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
version=16.15.1
-revision=2
+revision=3
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
$(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From 5f1096582322c2a95d7208f0503a90420e46aba2 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 15:59:49 +0100
Subject: [PATCH 2/6] rstudio: don't use very old nodejs for build
---
srcpkgs/rstudio/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/rstudio/template b/srcpkgs/rstudio/template
index f260b6fe2de4..a07748db9e4e 100644
--- a/srcpkgs/rstudio/template
+++ b/srcpkgs/rstudio/template
@@ -11,7 +11,7 @@ configure_args="-DRSTUDIO_TARGET=Desktop
-DQT_QMAKE_EXECUTABLE=/usr/lib/qt5/bin/qmake
-DCMAKE_INSTALL_PREFIX=/usr/lib/rstudio"
hostmakedepends="unzip pandoc openjdk apache-ant R qt5-qmake
- qt5-host-tools which nodejs-lts"
+ qt5-host-tools which nodejs"
makedepends="zlib-devel libuuid-devel openssl-devel pam-devel R mathjax
boost-devel pango-devel hunspell-devel qt5-devel qt5-webkit-devel
qt5-declarative-devel qt5-location-devel qt5-sensors-devel qt5-svg-devel
From 3c1c84b395254eaa86cf8f1ae012b48815004ab3 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:11:24 +0100
Subject: [PATCH 3/6] llhttp: remove nodejs-lts comment
nodejs-lts is now merged to nodejs
---
srcpkgs/llhttp/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/llhttp/template b/srcpkgs/llhttp/template
index 7c367836045b..b2fbc9dd7932 100644
--- a/srcpkgs/llhttp/template
+++ b/srcpkgs/llhttp/template
@@ -1,6 +1,6 @@
# Template file for 'llhttp'
-# When this package is updated, nodejs and nodejs-lts may need to be updated
+# When this package is updated, nodejs may need to be updated
# or at least a revbump in the same pull request since they work in-sync.
pkgname=llhttp
From a2e068621cea59627267d0bd309dcaf8e6bcc557 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:14:18 +0100
Subject: [PATCH 4/6] thunderbird: fix build with python 3.11
---
srcpkgs/thunderbird/patches/python3.11.patch | 238 +++++++++++++++++++
1 file changed, 238 insertions(+)
create mode 100644 srcpkgs/thunderbird/patches/python3.11.patch
diff --git a/srcpkgs/thunderbird/patches/python3.11.patch b/srcpkgs/thunderbird/patches/python3.11.patch
new file mode 100644
index 000000000000..2facee5ebb2b
--- /dev/null
+++ b/srcpkgs/thunderbird/patches/python3.11.patch
@@ -0,0 +1,238 @@
+Patch-Source: https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=267709
+Patch-Source: https://hg.mozilla.org/mozilla-central/rev/f54162b2c1f2fe52c6137ab2c3469a1944f58b27
+--- a/xpcom/idl-parser/xpidl/xpidl.py
++++ b/xpcom/idl-parser/xpidl/xpidl.py
+@@ -1633,13 +1633,13 @@ class IDLParser(object):
+ t_ignore = " \t"
+
+ def t_multilinecomment(self, t):
+- r"/\*(?s).*?\*/"
++ r"/\*(\n|.)*?\*/"
+ t.lexer.lineno += t.value.count("\n")
+ if t.value.startswith("/**"):
+ self._doccomments.append(t.value)
+
+ def t_singlelinecomment(self, t):
+- r"(?m)//.*?$"
++ r"//[^\n]*"
+
+ def t_IID(self, t):
+ return t
+@@ -1652,7 +1652,7 @@ class IDLParser(object):
+ return t
+
+ def t_LCDATA(self, t):
+- r"(?s)%\{[ ]*C\+\+[ ]*\n(?P<cdata>.*?\n?)%\}[ ]*(C\+\+)?"
++ r"%\{[ ]*C\+\+[ ]*\n(?P<cdata>(\n|.)*?\n?)%\}[ ]*(C\+\+)?"
+ t.type = "CDATA"
+ t.value = t.lexer.lexmatch.group("cdata")
+ t.lexer.lineno += t.value.count("\n")
+
+
+# HG changeset patch
+# User ahochheiden <ahochheiden@mozilla.com>
+# Date 1654151264 0
+# Node ID f54162b2c1f2fe52c6137ab2c3469a1944f58b27
+# Parent 6e7776492240c27732840d65a33dcc440fa1aba0
+Bug 1769631 - Remove 'U' from 'mode' parameters for various 'open' calls to ensure Python3.11 compatibility r=firefox-build-system-reviewers,glandium
+
+The 'U' flag represents "universal newline". It has been deprecated
+since Python3.3. Since then "universal newline" is the default when a
+file is opened in text mode (not bytes). In Python3.11 using the 'U'
+flag throws errors. There should be no harm in removing 'U' from 'open'
+everywhere it is used, and doing allows the use of Python3.11.
+
+For more reading see: https://docs.python.org/3.11/whatsnew/3.11.html#changes-in-the-python-api
+
+Differential Revision: https://phabricator.services.mozilla.com/D147721
+
+diff --git a/dom/base/usecounters.py b/dom/base/usecounters.py
+--- a/dom/base/usecounters.py
++++ b/dom/base/usecounters.py
+@@ -3,17 +3,17 @@
+ # file, You can obtain one at http://mozilla.org/MPL/2.0/.
+
+ import collections
+ import re
+
+
+ def read_conf(conf_filename):
+ # Can't read/write from a single StringIO, so make a new one for reading.
+- stream = open(conf_filename, "rU")
++ stream = open(conf_filename, "r")
+
+ def parse_counters(stream):
+ for line_num, line in enumerate(stream):
+ line = line.rstrip("\n")
+ if not line or line.startswith("//"):
+ # empty line or comment
+ continue
+ m = re.match(r"method ([A-Za-z0-9]+)\.([A-Za-z0-9]+)$", line)
+diff --git a/python/mozbuild/mozbuild/action/process_define_files.py b/python/mozbuild/mozbuild/action/process_define_files.py
+--- a/python/mozbuild/mozbuild/action/process_define_files.py
++++ b/python/mozbuild/mozbuild/action/process_define_files.py
+@@ -31,17 +31,17 @@ def process_define_file(output, input):
+
+ config = PartialConfigEnvironment(topobjdir)
+
+ if mozpath.basedir(
+ path, [mozpath.join(topsrcdir, "js/src")]
+ ) and not config.substs.get("JS_STANDALONE"):
+ config = PartialConfigEnvironment(mozpath.join(topobjdir, "js", "src"))
+
+- with open(path, "rU") as input:
++ with open(path, "r") as input:
+ r = re.compile(
+ "^\s*#\s*(?P<cmd>[a-z]+)(?:\s+(?P<name>\S+)(?:\s+(?P<value>\S+))?)?", re.U
+ )
+ for l in input:
+ m = r.match(l)
+ if m:
+ cmd = m.group("cmd")
+ name = m.group("name")
+diff --git a/python/mozbuild/mozbuild/backend/base.py b/python/mozbuild/mozbuild/backend/base.py
+--- a/python/mozbuild/mozbuild/backend/base.py
++++ b/python/mozbuild/mozbuild/backend/base.py
+@@ -267,17 +267,17 @@ class BuildBackend(LoggingMixin):
+ If an exception is raised, |mach build| will fail with a
+ non-zero exit code.
+ """
+ self._write_purgecaches(config)
+
+ return status
+
+ @contextmanager
+- def _write_file(self, path=None, fh=None, readmode="rU"):
++ def _write_file(self, path=None, fh=None, readmode="r"):
+ """Context manager to write a file.
+
+ This is a glorified wrapper around FileAvoidWrite with integration to
+ update the summary data on this instance.
+
+ Example usage:
+
+ with self._write_file('foo.txt') as fh:
+diff --git a/python/mozbuild/mozbuild/preprocessor.py b/python/mozbuild/mozbuild/preprocessor.py
+--- a/python/mozbuild/mozbuild/preprocessor.py
++++ b/python/mozbuild/mozbuild/preprocessor.py
+@@ -526,17 +526,17 @@ class Preprocessor:
+ if not options.output:
+ raise Preprocessor.Error(
+ self, "--depend doesn't work with stdout", None
+ )
+ depfile = get_output_file(options.depend)
+
+ if args:
+ for f in args:
+- with io.open(f, "rU", encoding="utf-8") as input:
++ with io.open(f, "r", encoding="utf-8") as input:
+ self.processFile(input=input, output=out)
+ if depfile:
+ mk = Makefile()
+ mk.create_rule([six.ensure_text(options.output)]).add_dependencies(
+ self.includes
+ )
+ mk.dump(depfile)
+ depfile.close()
+@@ -855,17 +855,17 @@ class Preprocessor:
+ self.checkLineNumbers = False
+ if isName:
+ try:
+ args = _to_text(args)
+ if filters:
+ args = self.applyFilters(args)
+ if not os.path.isabs(args):
+ args = os.path.join(self.curdir, args)
+- args = io.open(args, "rU", encoding="utf-8")
++ args = io.open(args, "r", encoding="utf-8")
+ except Preprocessor.Error:
+ raise
+ except Exception:
+ raise Preprocessor.Error(self, "FILE_NOT_FOUND", _to_text(args))
+ self.checkLineNumbers = bool(
+ re.search("\.(js|jsm|java|webidl)(?:\.in)?$", args.name)
+ )
+ oldFile = self.context["FILE"]
+@@ -909,17 +909,17 @@ class Preprocessor:
+
+ def do_error(self, args):
+ raise Preprocessor.Error(self, "Error: ", _to_text(args))
+
+
+ def preprocess(includes=[sys.stdin], defines={}, output=sys.stdout, marker="#"):
+ pp = Preprocessor(defines=defines, marker=marker)
+ for f in includes:
+- with io.open(f, "rU", encoding="utf-8") as input:
++ with io.open(f, "r", encoding="utf-8") as input:
+ pp.processFile(input=input, output=output)
+ return pp.includes
+
+
+ # Keep this module independently executable.
+ if __name__ == "__main__":
+ pp = Preprocessor()
+ pp.handleCommandLine(None, True)
+diff --git a/python/mozbuild/mozbuild/util.py b/python/mozbuild/mozbuild/util.py
+--- a/python/mozbuild/mozbuild/util.py
++++ b/python/mozbuild/mozbuild/util.py
+@@ -231,17 +231,17 @@ class FileAvoidWrite(BytesIO):
+ enabled by default because it a) doesn't make sense for binary files b)
+ could add unwanted overhead to calls.
+
+ Additionally, there is dry run mode where the file is not actually written
+ out, but reports whether the file was existing and would have been updated
+ still occur, as well as diff capture if requested.
+ """
+
+- def __init__(self, filename, capture_diff=False, dry_run=False, readmode="rU"):
++ def __init__(self, filename, capture_diff=False, dry_run=False, readmode="r"):
+ BytesIO.__init__(self)
+ self.name = filename
+ assert type(capture_diff) == bool
+ assert type(dry_run) == bool
+ assert "r" in readmode
+ self._capture_diff = capture_diff
+ self._write_to_file = not dry_run
+ self.diff = None
+diff --git a/python/mozbuild/mozpack/files.py b/python/mozbuild/mozpack/files.py
+--- a/python/mozbuild/mozpack/files.py
++++ b/python/mozbuild/mozpack/files.py
+@@ -549,17 +549,17 @@ class PreprocessedFile(BaseFile):
+ self.defines = defines
+ self.extra_depends = list(extra_depends or [])
+ self.silence_missing_directive_warnings = silence_missing_directive_warnings
+
+ def inputs(self):
+ pp = Preprocessor(defines=self.defines, marker=self.marker)
+ pp.setSilenceDirectiveWarnings(self.silence_missing_directive_warnings)
+
+- with _open(self.path, "rU") as input:
++ with _open(self.path, "r") as input:
+ with _open(os.devnull, "w") as output:
+ pp.processFile(input=input, output=output)
+
+ # This always yields at least self.path.
+ return pp.includes
+
+ def copy(self, dest, skip_if_older=True):
+ """
+@@ -606,17 +606,17 @@ class PreprocessedFile(BaseFile):
+ return False
+
+ deps_out = None
+ if self.depfile:
+ deps_out = FileAvoidWrite(self.depfile)
+ pp = Preprocessor(defines=self.defines, marker=self.marker)
+ pp.setSilenceDirectiveWarnings(self.silence_missing_directive_warnings)
+
+- with _open(self.path, "rU") as input:
++ with _open(self.path, "r") as input:
+ pp.processFile(input=input, output=dest, depfile=deps_out)
+
+ dest.close()
+ if self.depfile:
+ deps_out.close()
+
+ return True
+
+
From 09c032fc51c012449a0c9e717cba85fd71a75a49 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:20:26 +0100
Subject: [PATCH 5/6] thunderbird: use new node for build
---
srcpkgs/thunderbird/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/thunderbird/template b/srcpkgs/thunderbird/template
index 022d585cee84..29e88efee0d8 100644
--- a/srcpkgs/thunderbird/template
+++ b/srcpkgs/thunderbird/template
@@ -16,7 +16,7 @@ checksum=c4bec51c09d216b4ba03210c6ef3b7eef4e76f1fa4957e9d11f79d3e5825164e
lib32disabled=yes
hostmakedepends="autoconf unzip zip pkg-config perl python3 yasm rust cargo
- llvm clang nodejs-lts cbindgen nasm which tar"
+ llvm clang nodejs cbindgen nasm which tar"
makedepends="nss-devel libjpeg-turbo-devel gtk+3-devel icu-devel
pixman-devel libevent-devel libnotify-devel libvpx-devel
libXrender-devel libXcomposite-devel libSM-devel libXt-devel rust-std
From 9004779abd2c3d078f4bf73a91c8d19d19caf26b Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 19:57:15 +0100
Subject: [PATCH 6/6] keybase-desktop: update to 6.0.2.
---
srcpkgs/keybase-desktop/template | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/srcpkgs/keybase-desktop/template b/srcpkgs/keybase-desktop/template
index 86dcf893c775..2b97c4e45b38 100644
--- a/srcpkgs/keybase-desktop/template
+++ b/srcpkgs/keybase-desktop/template
@@ -1,15 +1,15 @@
# Template file for 'keybase-desktop'
pkgname=keybase-desktop
-version=5.8.1
+version=6.0.2
revision=1
-hostmakedepends="git nodejs-lts yarn unzip"
+hostmakedepends="git nodejs yarn unzip"
depends="keybase kbfs"
short_desc="Keybase desktop client"
maintainer="Dominic Monroe <monroef4@googlemail.com>"
license="BSD-3-Clause"
homepage="https://keybase.io"
distfiles="https://github.com/keybase/client/archive/v${version}.tar.gz"
-checksum=25539ff5b3bad939c9a481ccae89913c1d14aab7f2ac9756a4c231b01ce3fc61
+checksum=bdc42b44727614d92768aaaf1ea4e0f01c6b24d5a478bb4b89e0abc93bc67ed5
nostrip_files="Keybase"
case "${XBPS_TARGET_MACHINE}" in
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (2 preceding siblings ...)
2022-12-07 8:02 ` [PR PATCH] [Updated] " paper42
@ 2022-12-15 17:12 ` akierig
2022-12-15 17:14 ` akierig
` (15 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: akierig @ 2022-12-15 17:12 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 293 bytes --]
New comment by akierig on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1353422874
Comment:
all in favor of updating node. I can't update `Signal-Desktop`'s latest version because it requires node ≥ 16.16.0. Happy to help if I can, @paper42.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (3 preceding siblings ...)
2022-12-15 17:12 ` akierig
@ 2022-12-15 17:14 ` akierig
2022-12-15 19:11 ` [PR PATCH] [Updated] " paper42
` (14 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: akierig @ 2022-12-15 17:14 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 404 bytes --]
New comment by akierig on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1353422874
Comment:
all in favor of updating node. I can't update `Signal-Desktop`'s latest version because it [requires node ≥ 16.16.0](https://github.com/signalapp/Signal-Desktop/blob/854ac9edb3c8a183ee7ba3f98112680e9e423fa4/package.json#L321). Happy to help if I can, @paper42.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (4 preceding siblings ...)
2022-12-15 17:14 ` akierig
@ 2022-12-15 19:11 ` paper42
2022-12-18 11:08 ` paper42
` (13 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2022-12-15 19:11 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1985 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
This is a draft for now for comments and for checking if every package that used nodejs-lts still builds with nodejs 16.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 40712 bytes --]
From e06bfc81edfe76c7c3caaee25579c3428e67cb02 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH 1/2] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 18 +-
9 files changed, 17 insertions(+), 1026 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index 5420e8524442..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=2
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index c2f4d4eb340f..19a5befed667 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
version=16.15.1
-revision=2
+revision=3
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
$(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From 3b5abe041d35a694912d25edcddc12a9276bfda3 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:11:24 +0100
Subject: [PATCH 2/2] llhttp: remove nodejs-lts comment
nodejs-lts is now merged to nodejs
---
srcpkgs/llhttp/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/llhttp/template b/srcpkgs/llhttp/template
index 7c367836045b..b2fbc9dd7932 100644
--- a/srcpkgs/llhttp/template
+++ b/srcpkgs/llhttp/template
@@ -1,6 +1,6 @@
# Template file for 'llhttp'
-# When this package is updated, nodejs and nodejs-lts may need to be updated
+# When this package is updated, nodejs may need to be updated
# or at least a revbump in the same pull request since they work in-sync.
pkgname=llhttp
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (5 preceding siblings ...)
2022-12-15 19:11 ` [PR PATCH] [Updated] " paper42
@ 2022-12-18 11:08 ` paper42
2023-02-04 16:36 ` dkwo
` (12 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2022-12-18 11:08 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1985 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
This is a draft for now for comments and for checking if every package that used nodejs-lts still builds with nodejs 16.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 40712 bytes --]
From cf91d12162ae87fe57d72f8905c29d595d177d5e Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH 1/2] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 18 +-
9 files changed, 17 insertions(+), 1026 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index 5420e8524442..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=2
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index 0fee0a8ec725..f09b47a03b15 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
version=16.19.0
-revision=1
+revision=2
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
$(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From 62e73e5045e95f1bb4f00c06e061670e157ffd77 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:11:24 +0100
Subject: [PATCH 2/2] llhttp: remove nodejs-lts comment
nodejs-lts is now merged to nodejs
---
srcpkgs/llhttp/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/llhttp/template b/srcpkgs/llhttp/template
index 7c367836045b..b2fbc9dd7932 100644
--- a/srcpkgs/llhttp/template
+++ b/srcpkgs/llhttp/template
@@ -1,6 +1,6 @@
# Template file for 'llhttp'
-# When this package is updated, nodejs and nodejs-lts may need to be updated
+# When this package is updated, nodejs may need to be updated
# or at least a revbump in the same pull request since they work in-sync.
pkgname=llhttp
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (6 preceding siblings ...)
2022-12-18 11:08 ` paper42
@ 2023-02-04 16:36 ` dkwo
2023-02-04 17:07 ` paper42
` (11 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: dkwo @ 2023-02-04 16:36 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 261 bytes --]
New comment by dkwo on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1416795928
Comment:
Can I rely on this PR for openssl3 update #37681 ? `nodejs-lts` was failing to build with openssl3, perhaps being too old.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (7 preceding siblings ...)
2023-02-04 16:36 ` dkwo
@ 2023-02-04 17:07 ` paper42
2023-02-04 17:08 ` paper42
` (10 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-02-04 17:07 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 192 bytes --]
New comment by paper42 on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1416802219
Comment:
No, chronograf still doesn't build with nodejs 16.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (8 preceding siblings ...)
2023-02-04 17:07 ` paper42
@ 2023-02-04 17:08 ` paper42
2023-02-04 17:43 ` dkwo
` (9 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-02-04 17:08 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 269 bytes --]
New comment by paper42 on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1416802219
Comment:
No, chronograf still doesn't build with nodejs 16, this will be merged when it does, but I have not been able to fix it so far.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (9 preceding siblings ...)
2023-02-04 17:08 ` paper42
@ 2023-02-04 17:43 ` dkwo
2023-03-01 20:22 ` paper42
` (8 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: dkwo @ 2023-02-04 17:43 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 177 bytes --]
New comment by dkwo on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1416809967
Comment:
Have you tried updating it to 1.10.0 ?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (10 preceding siblings ...)
2023-02-04 17:43 ` dkwo
@ 2023-03-01 20:22 ` paper42
2023-03-07 0:16 ` dkwo
` (7 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-03-01 20:22 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 300 bytes --]
New comment by paper42 on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1450797367
Comment:
> Have you tried updating it to 1.10.0 ?
I did, but there was an error and since I don't know nodejs, I ended there. 1.10.0 should support nodejs 16 though
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (11 preceding siblings ...)
2023-03-01 20:22 ` paper42
@ 2023-03-07 0:16 ` dkwo
2023-03-07 6:40 ` paper42
` (6 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: dkwo @ 2023-03-07 0:16 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1996 bytes --]
New comment by dkwo on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1457255826
Comment:
@paper42 I was able to build it with
```
diff --git a/srcpkgs/chronograf/template b/srcpkgs/chronograf/template
index 5dfcc1c3ef..087208b040 100644
--- a/srcpkgs/chronograf/template
+++ b/srcpkgs/chronograf/template
@@ -1,18 +1,18 @@
# Template file for 'chronograf'
pkgname=chronograf
-version=1.9.4
+version=1.10.0
revision=1
build_style=go
go_import_path="github.com/influxdata/${pkgname}"
go_package="${go_import_path}/cmd/chronograf"
go_ldflags="-X main.version=${version}"
-hostmakedepends="dep go-bindata nodejs-lts yarn"
+hostmakedepends="dep go-bindata nodejs yarn python3"
short_desc="Open source monitoring and visualization UI for the TICK stack"
maintainer="Michael Aldridge <maldridge@voidlinux.org>"
license="AGPL-3.0-or-later"
homepage="https://www.influxdata.com/time-series-platform/chronograf/"
distfiles="https://github.com/influxdata/${pkgname}/archive/${version}.tar.gz"
-checksum=ff294f25a9de57140024b9953992c1a4d79ec88167ad28435645d888a0096c27
+checksum=4c9ec541a77314b11f23f2eff1394568ea9180f1f3cc3f098cb3e7977dbfd7a5
system_accounts="_chronograf"
_chronograf_homedir="/var/lib/${pkgname}"
@@ -23,13 +23,13 @@ case "$XBPS_TARGET_MACHINE" in
ppc*) broken="ftbfs in some js module" ;;
esac
-pre_build() {
- cd $wrksrc/ui
- yarn install
- export PATH=$PATH:${wrksrc}/ui/node_modules/.bin
+do_build() {
+ go get -p "$XBPS_MAKEJOBS" -x -tags "${go_build_tags}" -ldflags "${go_ldflags}" github.com/influxdata/chronograf
+ CFLAGS="$CFLAGS -fPIC" CXXFLAGS="$CXXFLAGS -fPIC" make
+}
- cd $wrksrc
- make assets
+do_install() {
+ go install github.com/influxdata/chronograf/cmd/chronograf
}
post_install() {
```
cc mantainer @the-maldridge
it may even build with nodejs 18 from #41239 , but I have not checked.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (12 preceding siblings ...)
2023-03-07 0:16 ` dkwo
@ 2023-03-07 6:40 ` paper42
2023-03-07 16:50 ` dkwo
` (5 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-03-07 6:40 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 192 bytes --]
New comment by paper42 on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1457626466
Comment:
@dkwo great, could you open a PR with that change?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (13 preceding siblings ...)
2023-03-07 6:40 ` paper42
@ 2023-03-07 16:50 ` dkwo
2023-05-16 14:41 ` dkwo
` (4 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: dkwo @ 2023-03-07 16:50 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 150 bytes --]
New comment by dkwo on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1458501063
Comment:
done #42644
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (14 preceding siblings ...)
2023-03-07 16:50 ` dkwo
@ 2023-05-16 14:41 ` dkwo
2023-06-02 19:18 ` [PR PATCH] [Updated] " paper42
` (3 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: dkwo @ 2023-05-16 14:41 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 197 bytes --]
New comment by dkwo on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1549812833
Comment:
@paper42 can this be merged, now that chronograf is fixed?
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (15 preceding siblings ...)
2023-05-16 14:41 ` dkwo
@ 2023-06-02 19:18 ` paper42
2023-06-02 19:20 ` paper42
` (2 subsequent siblings)
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-06-02 19:18 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1966 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
TODO:
- [ ] fix chronograf build with nodejs 16 (probably with an update)
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
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A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 40370 bytes --]
From e9b7dc5e8bef29f13eabcc779f02eff9124e3786 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH 1/2] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 16 +-
9 files changed, 16 insertions(+), 1025 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index d88dca8e6ee5..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=3
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index a53792a6544f..f09b47a03b15 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From 4125d64e7d0d75e779f812790f5718c2f7d4cc58 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:11:24 +0100
Subject: [PATCH 2/2] llhttp: remove nodejs-lts comment
nodejs-lts is now merged to nodejs
---
srcpkgs/llhttp/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/llhttp/template b/srcpkgs/llhttp/template
index 7c367836045b..b2fbc9dd7932 100644
--- a/srcpkgs/llhttp/template
+++ b/srcpkgs/llhttp/template
@@ -1,6 +1,6 @@
# Template file for 'llhttp'
-# When this package is updated, nodejs and nodejs-lts may need to be updated
+# When this package is updated, nodejs may need to be updated
# or at least a revbump in the same pull request since they work in-sync.
pkgname=llhttp
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Updated] nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (16 preceding siblings ...)
2023-06-02 19:18 ` [PR PATCH] [Updated] " paper42
@ 2023-06-02 19:20 ` paper42
2023-06-03 19:47 ` [PR PATCH] [Closed]: " paper42
2023-06-03 19:47 ` paper42
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-06-02 19:20 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1966 bytes --]
There is an updated pull request by paper42 against master on the void-packages repository
https://github.com/paper42/void-packages node-lts-16
https://github.com/void-linux/void-packages/pull/40106
nodejs: merge with nodejs-lts
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
TODO:
- [ ] fix chronograf build with nodejs 16 (probably with an update)
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **NO**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/40106.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-node-lts-16-40106.patch --]
[-- Type: text/x-diff, Size: 40712 bytes --]
From 3ebf7ef87f15a74ff2c8eca3956b2901234f8b6b Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Sun, 20 Nov 2022 19:47:36 +0100
Subject: [PATCH 1/2] nodejs: merge with nodejs-lts
nodejs 16 is an LTS version and nodejs-lts version 12 is EOL
---
srcpkgs/nodejs-lts | 1 +
srcpkgs/nodejs-lts-devel | 2 +-
.../patches/ppc-fixes-for-older-models.patch | 847 ------------------
srcpkgs/nodejs-lts/patches/ppc32.patch | 20 -
srcpkgs/nodejs-lts/patches/shared-uv.patch | 25 -
.../patches/xxx-ppc-hwcap-musl.patch | 24 -
srcpkgs/nodejs-lts/template | 104 ---
srcpkgs/nodejs-lts/update | 2 -
srcpkgs/nodejs/template | 18 +-
9 files changed, 17 insertions(+), 1026 deletions(-)
create mode 120000 srcpkgs/nodejs-lts
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/ppc32.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/shared-uv.patch
delete mode 100644 srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
delete mode 100644 srcpkgs/nodejs-lts/template
delete mode 100644 srcpkgs/nodejs-lts/update
diff --git a/srcpkgs/nodejs-lts b/srcpkgs/nodejs-lts
new file mode 120000
index 000000000000..0c524b775308
--- /dev/null
+++ b/srcpkgs/nodejs-lts
@@ -0,0 +1 @@
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts-devel b/srcpkgs/nodejs-lts-devel
index c9a495a2e35b..0c524b775308 120000
--- a/srcpkgs/nodejs-lts-devel
+++ b/srcpkgs/nodejs-lts-devel
@@ -1 +1 @@
-nodejs-lts
\ No newline at end of file
+nodejs
\ No newline at end of file
diff --git a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch b/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
deleted file mode 100644
index 3a3630f1ad4d..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc-fixes-for-older-models.patch
+++ /dev/null
@@ -1,847 +0,0 @@
-Fix PowerPC CPU detection and codegen to work with more processors.
-
-This patch defines the correct optional Power ISA features that the
-PPC code generator needs in order to run without crashing on v2.01
-and older CPUs such as PPC 970 (G5) or NXP e6500, and to run more
-efficiently on CPUs with features that weren't being used before.
-
-PowerPC ISA v2.01 and older CPUs don't have FP round to int instructions,
-and PowerPC ISA v2.06 and older are missing support for unsigned 64-bit
-to/from double, as well as integer to/from single-precision float.
-
-Add a new FP_ROUND_TO_INT CPU feature to determine whether to generate
-FP round to int, and add a new PPC_7_PLUS feature to determine whether
-to use the v2.06 FPR conversion instructions or generate an alternate
-sequence to handle large 64-bit unsigned ints, and single-precision
-using the v2.01 instructions with handling for large uint64_t values
-as well as rounding results from double to single-precision.
-
-Also add a new POP_COUNT feature for the popcnt opcodes added in v2.06,
-which are also present in the NXP e5500 and e6500 cores, which are
-otherwise missing many of the features added since v2.01.
-
-By defining an ICACHE_SNOOP feature bit to replace the poorly-named
-"LWSYNC", the meaning of the instruction cache flushing fast path,
-and the CPUs that can use it, are more clearly defined. In addition,
-for the other PowerPC chips, the loop to flush the data and instruction
-cache blocks has been split into two loops, with a single "sync" and
-"isync" after each loop, which should be more efficient, and also handles
-the few CPUs with differing data and instruction cache line sizes.
-
-In the macro assembler methods, in addition to providing an alternate
-path for FP conversion opcodes added in POWER7 (ISA v2.06), unnecessary
-instructions to move sp down and then immediately back up were replaced
-with negative offsets from the current sp. This should be faster, and also
-sp is supposed to point to a back chain at all times (V8 may not do this).
-
-This patch also fixes ppc64 big-endian ELFv1 builds (not needed for Void).
-
---- a/deps/v8/src/base/cpu.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.cc 2022-02-17 23:01:40.624597523 -0800
-@@ -10,7 +10,7 @@
- #if V8_OS_LINUX
- #include <linux/auxvec.h> // AT_HWCAP
- #endif
--#if V8_GLIBC_PREREQ(2, 16)
-+#if V8_GLIBC_PREREQ(2, 16) || (V8_OS_LINUX && V8_HOST_ARCH_PPC)
- #include <sys/auxv.h> // getauxval()
- #endif
- #if V8_OS_QNX
-@@ -611,57 +611,56 @@
-
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
-- // Read processor info from /proc/self/auxv.
-- char* auxv_cpu_type = nullptr;
-- FILE* fp = fopen("/proc/self/auxv", "r");
-- if (fp != nullptr) {
--#if V8_TARGET_ARCH_PPC64
-- Elf64_auxv_t entry;
--#else
-- Elf32_auxv_t entry;
--#endif
-- for (;;) {
-- size_t n = fread(&entry, sizeof(entry), 1, fp);
-- if (n == 0 || entry.a_type == AT_NULL) {
-- break;
-- }
-- switch (entry.a_type) {
-- case AT_PLATFORM:
-- auxv_cpu_type = reinterpret_cast<char*>(entry.a_un.a_val);
-- break;
-- case AT_ICACHEBSIZE:
-- icache_line_size_ = entry.a_un.a_val;
-- break;
-- case AT_DCACHEBSIZE:
-- dcache_line_size_ = entry.a_un.a_val;
-- break;
-- }
-- }
-- fclose(fp);
-- }
-+ // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
-+ icache_line_size_ = static_cast<int>(getauxval(AT_ICACHEBSIZE));
-+ dcache_line_size_ = static_cast<int>(getauxval(AT_DCACHEBSIZE));
-+ const unsigned long hwcap = getauxval(AT_HWCAP);
-+ const unsigned long hwcap2 = getauxval(AT_HWCAP2);
-+ const char* platform = reinterpret_cast<const char*>(getauxval(AT_PLATFORM));
-+
-+ // NOTE: AT_HWCAP ISA version bits aren't cumulative, so it's necessary
-+ // to compare against a mask of all supported versions and CPUs, up to
-+ // ISA v2.06, which *is* set for later CPUs. In contrast, the AT_HWCAP2
-+ // ISA version bits from v2.07 onward are set cumulatively, so POWER10
-+ // will set the ISA version bits from v2.06 (in AT_HWCAP) through v3.1.
-+
-+ // i-cache coherency requires Power ISA v2.02 or later; has its own flag.
-+ has_icache_snoop_ = (hwcap & PPC_FEATURE_ICACHE_SNOOP);
-+
-+ // requires Power ISA v2.03 or later, or the HAS_ISEL bit (e.g. e6500).
-+ has_isel_ = (hwcap & (PPC_FEATURE_POWER5_PLUS | PPC_FEATURE_ARCH_2_05 |
-+ PPC_FEATURE_PA6T | PPC_FEATURE_POWER6_EXT | PPC_FEATURE_ARCH_2_06)) ||
-+ (hwcap2 & PPC_FEATURE2_HAS_ISEL);
-+
-+ // hwcap mask for older 64-bit PPC CPUs with Altivec, e.g. G5, Cell.
-+ static const unsigned long kHwcapMaskPPCG5 =
-+ (PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC);
-
- part_ = -1;
-- if (auxv_cpu_type) {
-- if (strcmp(auxv_cpu_type, "power10") == 0) {
-- part_ = PPC_POWER10;
-- }
-- else if (strcmp(auxv_cpu_type, "power9") == 0) {
-- part_ = PPC_POWER9;
-- } else if (strcmp(auxv_cpu_type, "power8") == 0) {
-- part_ = PPC_POWER8;
-- } else if (strcmp(auxv_cpu_type, "power7") == 0) {
-- part_ = PPC_POWER7;
-- } else if (strcmp(auxv_cpu_type, "power6") == 0) {
-- part_ = PPC_POWER6;
-- } else if (strcmp(auxv_cpu_type, "power5") == 0) {
-- part_ = PPC_POWER5;
-- } else if (strcmp(auxv_cpu_type, "ppc970") == 0) {
-- part_ = PPC_G5;
-- } else if (strcmp(auxv_cpu_type, "ppc7450") == 0) {
-- part_ = PPC_G4;
-- } else if (strcmp(auxv_cpu_type, "pa6t") == 0) {
-- part_ = PPC_PA6T;
-- }
-+ if (hwcap2 & PPC_FEATURE2_ARCH_3_1) {
-+ part_ = PPC_POWER10;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
-+ part_ = PPC_POWER9;
-+ } else if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
-+ part_ = PPC_POWER8;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_06) {
-+ part_ = PPC_POWER7;
-+ } else if (hwcap & PPC_FEATURE_ARCH_2_05) {
-+ part_ = PPC_POWER6;
-+ } else if (hwcap & (PPC_FEATURE_POWER5 | PPC_FEATURE_POWER5_PLUS)) {
-+ part_ = PPC_POWER5;
-+ } else if (hwcap & PPC_FEATURE_PA6T) {
-+ part_ = PPC_PA6T;
-+ } else if (strcmp(platform, "ppce6500") == 0) {
-+ part_ = PPC_E6500;
-+ } else if (strcmp(platform, "ppce5500") == 0) {
-+ part_ = PPC_E5500;
-+ } else if ((hwcap & kHwcapMaskPPCG5) == kHwcapMaskPPCG5) {
-+ part_ = PPC_G5;
-+ } else if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
-+ part_ = PPC_G4;
-+ } else {
-+ part_ = PPC_G3;
- }
-
- #elif V8_OS_AIX
-@@ -682,9 +681,13 @@
- part_ = PPC_POWER6;
- break;
- case POWER_5:
-+ default:
- part_ = PPC_POWER5;
- break;
- }
-+
-+ has_icache_snoop_ = true;
-+ has_isel_ = (part_ != PPC_POWER5); // isel was added in POWER5+ (v2.03)
- #endif // V8_OS_AIX
- #endif // !USE_SIMULATOR
- #endif // V8_HOST_ARCH_PPC
---- a/deps/v8/src/base/cpu.h 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/base/cpu.h 2022-02-17 19:54:08.768614805 -0800
-@@ -71,9 +71,12 @@
- PPC_POWER8,
- PPC_POWER9,
- PPC_POWER10,
-+ PPC_G3,
- PPC_G4,
- PPC_G5,
-- PPC_PA6T
-+ PPC_PA6T,
-+ PPC_E5500,
-+ PPC_E6500
- };
-
- // General features
-@@ -116,6 +119,10 @@
- bool is_fp64_mode() const { return is_fp64_mode_; }
- bool has_msa() const { return has_msa_; }
-
-+ // PowerPC features
-+ bool has_icache_snoop() const { return has_icache_snoop_; }
-+ bool has_isel() const { return has_isel_; }
-+
- private:
- char vendor_[13];
- int stepping_;
-@@ -157,6 +164,8 @@
- bool is_fp64_mode_;
- bool has_non_stop_time_stamp_counter_;
- bool has_msa_;
-+ bool has_icache_snoop_;
-+ bool has_isel_;
- };
-
- } // namespace base
---- a/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-01 10:53:09.000000000 -0800
-+++ b/deps/v8/src/codegen/ppc/macro-assembler-ppc.cc 2022-02-18 22:55:36.676461343 -0800
-@@ -706,13 +706,25 @@
-
- void TurboAssembler::ConvertIntToFloat(Register src, DoubleRegister dst) {
- MovIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedIntToFloat(Register src,
- DoubleRegister dst) {
- MovUnsignedIntToDouble(dst, src, r0);
-- fcfids(dst, dst);
-+
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(dst, dst);
-+ } else {
-+ fcfid(dst, dst);
-+ frsp(dst, dst);
-+ }
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -724,20 +736,52 @@
-
- void TurboAssembler::ConvertUnsignedInt64ToFloat(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidus(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidus(double_dst, double_dst);
-+ } else {
-+ ConvertUnsignedInt64ToDouble(src, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
-
- void TurboAssembler::ConvertUnsignedInt64ToDouble(Register src,
- DoubleRegister double_dst) {
-- MovInt64ToDouble(double_dst, src);
-- fcfidu(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ MovInt64ToDouble(double_dst, src);
-+ fcfidu(double_dst, double_dst);
-+ } else {
-+ Label negative;
-+ Label done;
-+ cmpi(src, Operand::Zero());
-+ blt(&negative);
-+ std(src, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ b(&done);
-+ bind(&negative);
-+ // Note: GCC saves the lowest bit, then ORs it after shifting right 1 bit,
-+ // presumably for better rounding. This version only shifts right 1 bit.
-+ srdi(r0, src, Operand(1));
-+ std(r0, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ fcfid(double_dst, double_dst);
-+ fadd(double_dst, double_dst, double_dst);
-+ bind(&done);
-+ }
- }
-
- void TurboAssembler::ConvertInt64ToFloat(Register src,
- DoubleRegister double_dst) {
- MovInt64ToDouble(double_dst, src);
-- fcfids(double_dst, double_dst);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ fcfids(double_dst, double_dst);
-+ } else {
-+ fcfid(double_dst, double_dst);
-+ frsp(double_dst, double_dst);
-+ }
- }
- #endif
-
-@@ -767,15 +811,56 @@
- void TurboAssembler::ConvertDoubleToUnsignedInt64(
- const DoubleRegister double_input, const Register dst,
- const DoubleRegister double_dst, FPRoundingMode rounding_mode) {
-- if (rounding_mode == kRoundToZero) {
-- fctiduz(double_dst, double_input);
-+ if (CpuFeatures::IsSupported(PPC_7_PLUS)) {
-+ if (rounding_mode == kRoundToZero) {
-+ fctiduz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctidu(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+
-+ MovDoubleToInt64(dst, double_dst);
- } else {
-- SetRoundingMode(rounding_mode);
-- fctidu(double_dst, double_input);
-- ResetRoundingMode();
-+ Label safe_size;
-+ Label done;
-+ mov(dst, Operand(1593835520)); // bit pattern for 2^63 as a float
-+ stw(dst, MemOperand(sp, -kFloatSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ lfs(double_dst, MemOperand(sp, -kFloatSize));
-+ fcmpu(double_input, double_dst);
-+ blt(&safe_size);
-+ // Subtract 2^63, then OR the top bit of the uint64 to add back
-+ fsub(double_dst, double_input, double_dst);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_dst);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_dst);
-+ ResetRoundingMode();
-+ }
-+ // set r0 to -1, then clear all but the MSB.
-+ mov(r0, Operand(-1));
-+ rldicr(r0, r0, 0, 0);
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ xor_(dst, dst, r0);
-+ b(&done);
-+ // Handling for values smaller than 2^63.
-+ bind(&safe_size);
-+ if (rounding_mode == kRoundToZero) {
-+ fctidz(double_dst, double_input);
-+ } else {
-+ SetRoundingMode(rounding_mode);
-+ fctid(double_dst, double_input);
-+ ResetRoundingMode();
-+ }
-+ stfd(double_dst, MemOperand(sp, -kDoubleSize));
-+ nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-+ ld(dst, MemOperand(sp, -kDoubleSize));
-+ bind(&done);
- }
--
-- MovDoubleToInt64(dst, double_dst);
- }
- #endif
-
-@@ -2097,19 +2182,17 @@
- }
- #endif
-
-- addi(sp, sp, Operand(-kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- mov(scratch, Operand(litVal.ival));
-- std(scratch, MemOperand(sp));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- LoadIntLiteral(scratch, litVal.ival[0]);
-- stw(scratch, MemOperand(sp, 0));
-+ stw(scratch, MemOperand(sp, -kDoubleSize));
- LoadIntLiteral(scratch, litVal.ival[1]);
-- stw(scratch, MemOperand(sp, 4));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + 4));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(result, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(result, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovIntToDouble(DoubleRegister dst, Register src,
-@@ -2123,18 +2206,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- extsw(scratch, src);
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- srawi(scratch, src, 31);
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovUnsignedIntToDouble(DoubleRegister dst, Register src,
-@@ -2148,18 +2229,16 @@
- #endif
-
- DCHECK(src != scratch);
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
- clrldi(scratch, src, Operand(32));
-- std(scratch, MemOperand(sp, 0));
-+ std(scratch, MemOperand(sp, -kDoubleSize));
- #else
- li(scratch, Operand::Zero());
-- stw(scratch, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(scratch, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovInt64ToDouble(DoubleRegister dst,
-@@ -2174,16 +2253,14 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
- #if V8_TARGET_ARCH_PPC64
-- std(src, MemOperand(sp, 0));
-+ std(src, MemOperand(sp, -kDoubleSize));
- #else
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- #if V8_TARGET_ARCH_PPC64
-@@ -2198,12 +2275,10 @@
- return;
- }
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stw(src_hi, MemOperand(sp, Register::kExponentOffset));
-- stw(src_lo, MemOperand(sp, Register::kMantissaOffset));
-+ stw(src_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ stw(src_lo, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
- #endif
-
-@@ -2218,12 +2293,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kMantissaOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::InsertDoubleHigh(DoubleRegister dst, Register src,
-@@ -2237,12 +2310,10 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(dst, MemOperand(sp));
-- stw(src, MemOperand(sp, Register::kExponentOffset));
-+ stfd(dst, MemOperand(sp, -kDoubleSize));
-+ stw(src, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfd(dst, MemOperand(sp));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lfd(dst, MemOperand(sp, -kDoubleSize));
- }
-
- void TurboAssembler::MovDoubleLowToInt(Register dst, DoubleRegister src) {
-@@ -2253,11 +2324,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- }
-
- void TurboAssembler::MovDoubleHighToInt(Register dst, DoubleRegister src) {
-@@ -2269,11 +2338,9 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, Register::kExponentOffset));
-- addi(sp, sp, Operand(kDoubleSize));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
- }
-
- void TurboAssembler::MovDoubleToInt64(
-@@ -2288,32 +2355,26 @@
- }
- #endif
-
-- subi(sp, sp, Operand(kDoubleSize));
-- stfd(src, MemOperand(sp));
-+ stfd(src, MemOperand(sp, -kDoubleSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
- #if V8_TARGET_ARCH_PPC64
-- ld(dst, MemOperand(sp, 0));
-+ ld(dst, MemOperand(sp, -kDoubleSize));
- #else
-- lwz(dst_hi, MemOperand(sp, Register::kExponentOffset));
-- lwz(dst, MemOperand(sp, Register::kMantissaOffset));
-+ lwz(dst_hi, MemOperand(sp, -kDoubleSize + Register::kExponentOffset));
-+ lwz(dst, MemOperand(sp, -kDoubleSize + Register::kMantissaOffset));
- #endif
-- addi(sp, sp, Operand(kDoubleSize));
- }
-
- void TurboAssembler::MovIntToFloat(DoubleRegister dst, Register src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stw(src, MemOperand(sp, 0));
-+ stw(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lfs(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lfs(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::MovFloatToInt(Register dst, DoubleRegister src) {
-- subi(sp, sp, Operand(kFloatSize));
-- stfs(src, MemOperand(sp, 0));
-+ stfs(src, MemOperand(sp, -kFloatSize));
- nop(GROUP_ENDING_NOP); // LHS/RAW optimization
-- lwz(dst, MemOperand(sp, 0));
-- addi(sp, sp, Operand(kFloatSize));
-+ lwz(dst, MemOperand(sp, -kFloatSize));
- }
-
- void TurboAssembler::Add(Register dst, Register src, intptr_t value,
---- a/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-15 21:11:46.291387457 -0800
-+++ b/deps/v8/src/codegen/ppc/cpu-ppc.cc 2022-02-17 20:38:08.816098185 -0800
-@@ -8,14 +8,12 @@
-
- #include "src/codegen/cpu-features.h"
-
--#define INSTR_AND_DATA_CACHE_COHERENCY LWSYNC
--
- namespace v8 {
- namespace internal {
-
- void CpuFeatures::FlushICache(void* buffer, size_t size) {
- #if !defined(USE_SIMULATOR)
-- if (CpuFeatures::IsSupported(INSTR_AND_DATA_CACHE_COHERENCY)) {
-+ if (CpuFeatures::IsSupported(ICACHE_SNOOP)) {
- __asm__ __volatile__(
- "sync \n"
- "icbi 0, %0 \n"
-@@ -26,25 +24,33 @@
- return;
- }
-
-- const int kCacheLineSize = CpuFeatures::icache_line_size();
-- intptr_t mask = kCacheLineSize - 1;
-+ const int kInstrCacheLineSize = CpuFeatures::icache_line_size();
-+ const int kDataCacheLineSize = CpuFeatures::dcache_line_size();
-+ intptr_t ic_mask = kInstrCacheLineSize - 1;
-+ intptr_t dc_mask = kDataCacheLineSize - 1;
- byte* start =
-- reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~mask);
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~dc_mask);
- byte* end = static_cast<byte*>(buffer) + size;
-- for (byte* pointer = start; pointer < end; pointer += kCacheLineSize) {
-- __asm__(
-+ for (byte* pointer = start; pointer < end; pointer += kDataCacheLineSize) {
-+ __asm__ __volatile__(
- "dcbf 0, %0 \n"
-- "sync \n"
-- "icbi 0, %0 \n"
-- "isync \n"
- : /* no output */
- : "r"(pointer));
- }
-+ __asm__ __volatile__("sync");
-
-+ start =
-+ reinterpret_cast<byte*>(reinterpret_cast<intptr_t>(buffer) & ~ic_mask);
-+ for (byte* pointer = start; pointer < end; pointer += kInstrCacheLineSize) {
-+ __asm__ __volatile__(
-+ "icbi 0, %0 \n"
-+ : /* no output */
-+ : "r"(pointer));
-+ }
-+ __asm__ __volatile__("isync");
- #endif // !USE_SIMULATOR
- }
- } // namespace internal
- } // namespace v8
-
--#undef INSTR_AND_DATA_CACHE_COHERENCY
- #endif // V8_TARGET_ARCH_PPC
---- a/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/ppc/assembler-ppc.cc 2022-02-18 00:11:07.887257174 -0800
-@@ -57,58 +57,62 @@
- void CpuFeatures::ProbeImpl(bool cross_compile) {
- supported_ |= CpuFeaturesImpliedByCompiler();
- icache_line_size_ = 128;
-+ dcache_line_size_ = 128;
-
- // Only use statically determined features for cross compile (snapshot).
- if (cross_compile) return;
-
--// Detect whether frim instruction is supported (POWER5+)
--// For now we will just check for processors we know do not
--// support it
- #ifndef USE_SIMULATOR
- // Probe for additional features at runtime.
- base::CPU cpu;
-- if (cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << MODULO);
-- }
-+ switch (cpu.part()) {
-+ case base::CPU::PPC_POWER10:
-+ case base::CPU::PPC_POWER9:
-+ supported_ |= (1u << MODULO);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER8:
- #if V8_TARGET_ARCH_PPC64
-- if (cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << FPR_GPR_MOV);
-- }
-+ supported_ |= (1u << FPR_GPR_MOV);
- #endif
-- if (cpu.part() == base::CPU::PPC_POWER6 ||
-- cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << LWSYNC);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER7:
-+ supported_ |= (1u << PPC_7_PLUS);
-+ supported_ |= (1u << POP_COUNT);
-+ // fallthrough
-+
-+ case base::CPU::PPC_POWER6:
-+ case base::CPU::PPC_POWER5:
-+ case base::CPU::PPC_PA6T:
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ break;
-+
-+ // Special cases below. Otherwise, assume no special features.
-+ // NXP e5500/e6500 have popcnt but not much else since ISA v2.01.
-+ case base::CPU::PPC_E5500:
-+ case base::CPU::PPC_E6500:
-+ supported_ |= (1u << POP_COUNT);
-+ break;
- }
-- if (cpu.part() == base::CPU::PPC_POWER7 ||
-- cpu.part() == base::CPU::PPC_POWER8 ||
-- cpu.part() == base::CPU::PPC_POWER9 ||
-- cpu.part() == base::CPU::PPC_POWER10) {
-- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ if (cpu.has_isel()) {
-+ supported_ |= (1u << ISELECT); // ISA v2.03, plus some NXP CPUs
- }
--#if V8_OS_LINUX
-- if (!(cpu.part() == base::CPU::PPC_G5 || cpu.part() == base::CPU::PPC_G4)) {
-- // Assume support
-- supported_ |= (1u << FPU);
-+ if (cpu.has_icache_snoop()) {
-+ supported_ |= (1u << ICACHE_SNOOP); // ISA v2.02; has its own hwcap flag
- }
- if (cpu.icache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
- icache_line_size_ = cpu.icache_line_size();
- }
--#elif V8_OS_AIX
-- // Assume support FP support and default cache line size
-- supported_ |= (1u << FPU);
--#endif
-+ if (cpu.dcache_line_size() != base::CPU::UNKNOWN_CACHE_LINE_SIZE) {
-+ dcache_line_size_ = cpu.dcache_line_size();
-+ }
- #else // Simulator
-- supported_ |= (1u << FPU);
-- supported_ |= (1u << LWSYNC);
-+ supported_ |= (1u << FP_ROUND_TO_INT);
-+ supported_ |= (1u << ICACHE_SNOOP);
- supported_ |= (1u << ISELECT);
-- supported_ |= (1u << VSX);
-+ supported_ |= (1u << POP_COUNT);
-+ supported_ |= (1u << PPC_7_PLUS);
- supported_ |= (1u << MODULO);
- #if V8_TARGET_ARCH_PPC64
- supported_ |= (1u << FPR_GPR_MOV);
-@@ -129,7 +133,13 @@
- }
-
- void CpuFeatures::PrintFeatures() {
-- printf("FPU=%d\n", CpuFeatures::IsSupported(FPU));
-+ printf("FP_ROUND_TO_INT=%d\n", CpuFeatures::IsSupported(FP_ROUND_TO_INT));
-+ printf("ICACHE_SNOOP=%d\n", CpuFeatures::IsSupported(ICACHE_SNOOP));
-+ printf("ISELECT=%d\n", CpuFeatures::IsSupported(ISELECT));
-+ printf("POP_COUNT=%d\n", CpuFeatures::IsSupported(POP_COUNT));
-+ printf("PPC_7_PLUS=%d\n", CpuFeatures::IsSupported(PPC_7_PLUS));
-+ printf("FPR_GPR_MOV=%d\n", CpuFeatures::IsSupported(FPR_GPR_MOV));
-+ printf("MODULO=%d\n", CpuFeatures::IsSupported(MODULO));
- }
-
- Register ToRegister(int num) {
---- a/deps/v8/src/codegen/cpu-features.h 2022-02-15 21:11:46.295387559 -0800
-+++ b/deps/v8/src/codegen/cpu-features.h 2022-02-17 21:10:09.853266061 -0800
-@@ -13,6 +13,7 @@
-
- // CPU feature flags.
- enum CpuFeature {
-+#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
- // x86
- SSE4_2,
- SSE4_1,
-@@ -26,11 +27,15 @@
- LZCNT,
- POPCNT,
- ATOM,
-+
-+#elif V8_TARGET_ARCH_ARM
- // ARM
- // - Standard configurations. The baseline is ARMv6+VFPv2.
- ARMv7, // ARMv7-A + VFPv3-D32 + NEON
- ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
- ARMv8, // ARMv8-A (+ all of the above)
-+
-+#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
- // MIPS, MIPS64
- FPU,
- FP64FPU,
-@@ -38,12 +43,18 @@
- MIPSr2,
- MIPSr6,
- MIPS_SIMD, // MSA instructions
-+
-+#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
- // PPC
-- FPR_GPR_MOV,
-- LWSYNC,
-- ISELECT,
-- VSX,
-- MODULO,
-+ FP_ROUND_TO_INT, // ISA v2.02 (POWER5)
-+ ICACHE_SNOOP, // ISA v2.02 (POWER5)
-+ ISELECT, // ISA v2.03 (POWER5+ and some NXP cores)
-+ PPC_7_PLUS, // ISA v2.06 (POWER7)
-+ POP_COUNT, // ISA v2.06 (POWER7 and NXP e5500/e6500)
-+ FPR_GPR_MOV, // ISA v2.07 (POWER8)
-+ MODULO, // ISA v3.0 (POWER9)
-+
-+#elif V8_TARGET_ARCH_S390X
- // S390
- DISTINCT_OPS,
- GENERAL_INSTR_EXT,
-@@ -51,14 +62,17 @@
- VECTOR_FACILITY,
- VECTOR_ENHANCE_FACILITY_1,
- MISC_INSTR_EXT2,
-+#endif
-
- NUMBER_OF_CPU_FEATURES,
-
-+#if V8_TARGET_ARCH_ARM
- // ARM feature aliases (based on the standard configurations above).
- VFPv3 = ARMv7,
- NEON = ARMv7,
- VFP32DREGS = ARMv7,
- SUDIV = ARMv7_SUDIV
-+#endif
- };
-
- // CpuFeatures keeps track of which features are supported by the target CPU.
---- a/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:46.299387660 -0800
-+++ b/deps/v8/src/compiler/backend/ppc/instruction-selector-ppc.cc 2022-02-15 21:11:49.123459271 -0800
-@@ -2393,16 +2393,26 @@
- // static
- MachineOperatorBuilder::Flags
- InstructionSelector::SupportedMachineOperatorFlags() {
-- return MachineOperatorBuilder::kFloat32RoundDown |
-- MachineOperatorBuilder::kFloat64RoundDown |
-- MachineOperatorBuilder::kFloat32RoundUp |
-- MachineOperatorBuilder::kFloat64RoundUp |
-- MachineOperatorBuilder::kFloat32RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTruncate |
-- MachineOperatorBuilder::kFloat64RoundTiesAway |
-- MachineOperatorBuilder::kWord32Popcnt |
-- MachineOperatorBuilder::kWord64Popcnt;
-+ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::Flag::kNoFlags;
-+ // FP rounding to integer instructions require Power ISA v2.02 or later.
-+ if (CpuFeatures::IsSupported(FP_ROUND_TO_INT)) {
-+ flags |= MachineOperatorBuilder::kFloat32RoundDown |
-+ MachineOperatorBuilder::kFloat64RoundDown |
-+ MachineOperatorBuilder::kFloat32RoundUp |
-+ MachineOperatorBuilder::kFloat64RoundUp |
-+ MachineOperatorBuilder::kFloat32RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTruncate |
-+ MachineOperatorBuilder::kFloat64RoundTiesAway;
-+ }
-+ // Population count requires Power ISA v2.06, or NXP e5500/e6500.
-+ if (CpuFeatures::IsSupported(POP_COUNT)) {
-+ flags |= MachineOperatorBuilder::kWord32Popcnt;
-+#if V8_TARGET_ARCH_PPC64
-+ flags |= MachineOperatorBuilder::kWord64Popcnt;
-+#endif
-+ }
- // We omit kWord32ShiftIsSafe as s[rl]w use 0x3F as a mask rather than 0x1F.
-+ return flags;
- }
-
- // static
diff --git a/srcpkgs/nodejs-lts/patches/ppc32.patch b/srcpkgs/nodejs-lts/patches/ppc32.patch
deleted file mode 100644
index ddfceb2f2179..000000000000
--- a/srcpkgs/nodejs-lts/patches/ppc32.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/deps/v8/src/libsampler/sampler.cc
-+++ b/deps/v8/src/libsampler/sampler.cc
-@@ -423,10 +423,17 @@
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.regs->link);
- #else
- // Some C libraries, notably Musl, define the regs member as a void pointer
-+ #if !V8_TARGET_ARCH_32_BIT
- state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[32]);
- state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[1]);
- state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[31]);
- state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gp_regs[36]);
-+ #else
-+ state->pc = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[32]);
-+ state->sp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[1]);
-+ state->fp = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[31]);
-+ state->lr = reinterpret_cast<void*>(ucontext->uc_mcontext.gregs[36]);
-+ #endif
- #endif
- #elif V8_HOST_ARCH_S390
- #if V8_TARGET_ARCH_32_BIT
diff --git a/srcpkgs/nodejs-lts/patches/shared-uv.patch b/srcpkgs/nodejs-lts/patches/shared-uv.patch
deleted file mode 100644
index 01e95f15b477..000000000000
--- a/srcpkgs/nodejs-lts/patches/shared-uv.patch
+++ /dev/null
@@ -1,25 +0,0 @@
---- a/deps/uvwasi/uvwasi.gyp
-+++ b/deps/uvwasi/uvwasi.gyp
-@@ -18,9 +18,6 @@
- 'src/wasi_rights.c',
- 'src/wasi_serdes.c',
- ],
-- 'dependencies': [
-- '../uv/uv.gyp:libuv',
-- ],
- 'direct_dependent_settings': {
- 'include_dirs': ['include']
- },
-@@ -31,6 +28,12 @@
- '_POSIX_C_SOURCE=200112',
- ],
- }],
-+ [ 'node_shared_libuv=="false"', {
-+ 'dependencies': [ '../uv/uv.gyp:libuv' ],
-+ }],
-+ [ 'node_shared_libuv=="true"', {
-+ 'libraries': [ '-luv' ],
-+ }]
- ],
- }
- ]
diff --git a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch b/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
deleted file mode 100644
index 952892caed38..000000000000
--- a/srcpkgs/nodejs-lts/patches/xxx-ppc-hwcap-musl.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-commit 558ab896cbdd90259950c631ba29a1c66bf4c2d3
-Author: q66 <daniel@octaforge.org>
-Date: Mon Feb 28 23:53:22 2022 +0100
-
- add some hwcap bits fallbacks
-
-diff --git a/deps/v8/src/base/cpu.cc b/deps/v8/src/base/cpu.cc
-index a1b21d2..8e52802 100644
---- a/deps/v8/src/base/cpu.cc
-+++ b/deps/v8/src/base/cpu.cc
-@@ -768,6 +768,13 @@ CPU::CPU()
-
- #elif V8_HOST_ARCH_PPC || V8_HOST_ARCH_PPC64
-
-+#ifndef PPC_FEATURE2_HAS_ISEL
-+#define PPC_FEATURE2_HAS_ISEL 0x08000000
-+#endif
-+#ifndef PPC_FEATURE2_ARCH_3_1
-+#define PPC_FEATURE2_ARCH_3_1 0x00040000
-+#endif
-+
- #ifndef USE_SIMULATOR
- #if V8_OS_LINUX
- // Read processor info from getauxval() (needs at least glibc 2.18 or musl).
diff --git a/srcpkgs/nodejs-lts/template b/srcpkgs/nodejs-lts/template
deleted file mode 100644
index d88dca8e6ee5..000000000000
--- a/srcpkgs/nodejs-lts/template
+++ /dev/null
@@ -1,104 +0,0 @@
-# Template file for 'nodejs-lts'
-pkgname=nodejs-lts
-version=12.22.10
-revision=3
-# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
-hostmakedepends="pkg-config python libatomic-devel zlib-devel which
- $(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-makedepends="libatomic-devel zlib-devel python-devel $(vopt_if icu icu-devel)
- $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
- $(vopt_if http_parser http-parser-devel) $(vopt_if nghttp2 nghttp2-devel)
- $(vopt_if cares c-ares-devel) $(vopt_if http_parser llhttp-devel)"
-checkdepends="procps-ng"
-short_desc="Evented I/O for V8 javascript"
-maintainer="Enno Boland <gottox@voidlinux.org>"
-license="MIT"
-homepage="https://nodejs.org/"
-distfiles="${homepage}/dist/v${version}/node-v${version}.tar.gz"
-checksum=1eeec68b530da4aced730e2af9e07a1ced8148337708f37fc8b4eddc3b6dc9e9
-python_version=3
-
-build_options="ssl libuv http_parser icu nghttp2 cares"
-desc_option_ssl="Enable shared openssl"
-desc_option_libuv="Enable shared libuv"
-desc_option_http_parser="Enable shared http-parser and llhttp"
-desc_option_icu="Enable shared icu"
-desc_option_nghttp2="Enable shared nghttp2"
-desc_option_cares="Enable shared c-ares"
-build_options_default="ssl libuv http_parser icu nghttp2 cares"
-
-replaces="iojs>=0"
-conflicts="nodejs nodejs-lts-10"
-provides="nodejs-runtime-0_1"
-
-if [ "$XBPS_WORDSIZE" -ne "$XBPS_TARGET_WORDSIZE" ]; then
- nocross="host and target must have the same pointer size"
-fi
-
-case "$XBPS_TARGET_MACHINE" in
- ppc64*) ;;
- ppc*) broken="Node 12.x does not support 32-bit ppc" ;;
-esac
-
-CFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-CXXFLAGS="-D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64"
-
-do_configure() {
- local _args
-
- export LD="$CXX"
- if [ "$CROSS_BUILD" ]; then
- case "$XBPS_TARGET_MACHINE" in
- arm*) _args="--dest-cpu=arm" ;;
- aarch64*) _args="--dest-cpu=arm64" ;;
- ppc64*) _args="--dest-cpu=ppc64" ;;
- ppc*) _args="--dest-cpu=ppc" ;;
- mipsel*) _args="--dest-cpu=mipsel" ;;
- mips*) _args="--dest-cpu=mips" ;;
- i686*) _args="--dest-cpu=x86" ;;
- x86_64*) _args="--dest-cpu=x86_64" ;;
- *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;;
- esac
- _args+=" --cross-compiling"
- fi
- ./configure --prefix=/usr --shared-zlib \
- $(vopt_if icu --with-intl=system-icu) \
- $(vopt_if http_parser --shared-http-parser) \
- $(vopt_if ssl --shared-openssl) \
- $(vopt_if libuv --shared-libuv) \
- $(vopt_if nghttp2 --shared-nghttp2) \
- $(vopt_if cares --shared-cares) ${_args}
-}
-
-post_configure() {
- # Fix linking against llhttp
- sed 's/-lhttp_parser/& -lllhttp/' -i out/*.target.mk
-}
-
-do_build() {
- if [ "$CROSS_BUILD" ]; then
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} PORTABLE=1 V=1
- else
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1
- fi
-}
-
-do_check() {
- make LD="$CXX" LDFLAGS+=-ldl ${makejobs} V=1 test-only
-}
-
-do_install() {
- make LD="$CXX" LDFLAGS+=-ldl DESTDIR="$DESTDIR" install
- rm $DESTDIR/usr/include/node/openssl -rf
- vlicense LICENSE
-}
-
-nodejs-lts-devel_package() {
- short_desc+=" (development files)"
- conflicts="nodejs-devel nodejs-lts-10-devel"
- pkg_install() {
- vmove usr/include
- }
-}
diff --git a/srcpkgs/nodejs-lts/update b/srcpkgs/nodejs-lts/update
deleted file mode 100644
index 537f8229dab9..000000000000
--- a/srcpkgs/nodejs-lts/update
+++ /dev/null
@@ -1,2 +0,0 @@
-site=https://nodejs.org/dist
-pattern='v\K12[\d.]+(?=\/)'
diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template
index a53792a6544f..d4e821e86bcd 100644
--- a/srcpkgs/nodejs/template
+++ b/srcpkgs/nodejs/template
@@ -1,7 +1,7 @@
# Template file for 'nodejs'
pkgname=nodejs
version=16.19.0
-revision=2
+revision=3
# Need these for host v8 for torque, see https://github.com/nodejs/node/pull/21079
hostmakedepends="which pkg-config python3 libatomic-devel zlib-devel
$(vopt_if icu icu-devel) $(vopt_if ssl openssl-devel) $(vopt_if libuv libuv-devel)
@@ -27,7 +27,7 @@ desc_option_cares="Enable shared c-ares"
build_options_default="ssl libuv icu nghttp2 cares"
replaces="iojs>=0"
-conflicts="nodejs-lts nodejs-lts-10"
+conflicts="nodejs-lts-10"
provides="nodejs-runtime-0_1"
# https://build.voidlinux.org/builders/i686_builder/builds/27325/steps/shell_3/logs/stdio
@@ -100,8 +100,20 @@ do_install() {
nodejs-devel_package() {
short_desc+=" (development files)"
- conflicts="nodejs-lts-devel nodejs-lts-10-devel"
+ conflicts="nodejs-lts-10-devel"
pkg_install() {
vmove usr/include
}
}
+
+nodejs-lts_package() {
+ depends="${sourcepkg}>=${version}_${revision}"
+ short_desc+=" LTS"
+ build_style=meta
+}
+
+nodejs-lts-devel_package() {
+ depends="${sourcepkg}-devel>=${version}_${revision}"
+ short_desc+=" LTS (development files)"
+ build_style=meta
+}
From 678946ee257c92aba9c17087c6d091c1a01f0006 Mon Sep 17 00:00:00 2001
From: Michal Vasilek <michal@vasilek.cz>
Date: Tue, 6 Dec 2022 16:11:24 +0100
Subject: [PATCH 2/2] llhttp: remove nodejs-lts comment
nodejs-lts is now merged to nodejs
---
srcpkgs/llhttp/template | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/srcpkgs/llhttp/template b/srcpkgs/llhttp/template
index 7c367836045b..b2fbc9dd7932 100644
--- a/srcpkgs/llhttp/template
+++ b/srcpkgs/llhttp/template
@@ -1,6 +1,6 @@
# Template file for 'llhttp'
-# When this package is updated, nodejs and nodejs-lts may need to be updated
+# When this package is updated, nodejs may need to be updated
# or at least a revbump in the same pull request since they work in-sync.
pkgname=llhttp
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PR PATCH] [Closed]: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (17 preceding siblings ...)
2023-06-02 19:20 ` paper42
@ 2023-06-03 19:47 ` paper42
2023-06-03 19:47 ` paper42
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-06-03 19:47 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1811 bytes --]
There's a closed pull request on the void-packages repository
nodejs: merge with nodejs-lts
https://github.com/void-linux/void-packages/pull/40106
Description:
Nodejs versioning says that every even release (12, 14, 16, 18) is an LTS release. The `nodejs` package currently uses version 16 which is a supported LTS version, `nodejs-lts` uses version 12 which is EOL and very old. Many packages use nodejs-lts for building, but then depend on the nodejs virtual package which defaults to nodejs, many packages don't work with old nodejs-lts and people couldn't have both installed. If we need to, we can always split nodejs-lts again, but right now I don't see a reason to do so. Alpine merged their nodejs-lts package to nodejs and provides nodejs-current for the latest version for development.
TODO:
- [x] fix chronograf build with nodejs 16 (probably with an update)
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
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and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: nodejs: merge with nodejs-lts
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
` (18 preceding siblings ...)
2023-06-03 19:47 ` [PR PATCH] [Closed]: " paper42
@ 2023-06-03 19:47 ` paper42
19 siblings, 0 replies; 21+ messages in thread
From: paper42 @ 2023-06-03 19:47 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 237 bytes --]
New comment by paper42 on void-packages repository
https://github.com/void-linux/void-packages/pull/40106#issuecomment-1575159072
Comment:
merged in 0fbf636fd59f00b77976ef802ce65aa468a16bbf and 78574d756c6495767f0e443a04d4e7e2e0976114
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2023-06-03 19:47 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-22 13:46 [PR PATCH] nodejs: update to 16.18.0, merge with nodejs-lts paper42
2022-11-20 18:48 ` [PR PATCH] [Updated] " paper42
2022-11-25 20:21 ` nodejs: " leahneukirchen
2022-12-07 8:02 ` [PR PATCH] [Updated] " paper42
2022-12-15 17:12 ` akierig
2022-12-15 17:14 ` akierig
2022-12-15 19:11 ` [PR PATCH] [Updated] " paper42
2022-12-18 11:08 ` paper42
2023-02-04 16:36 ` dkwo
2023-02-04 17:07 ` paper42
2023-02-04 17:08 ` paper42
2023-02-04 17:43 ` dkwo
2023-03-01 20:22 ` paper42
2023-03-07 0:16 ` dkwo
2023-03-07 6:40 ` paper42
2023-03-07 16:50 ` dkwo
2023-05-16 14:41 ` dkwo
2023-06-02 19:18 ` [PR PATCH] [Updated] " paper42
2023-06-02 19:20 ` paper42
2023-06-03 19:47 ` [PR PATCH] [Closed]: " paper42
2023-06-03 19:47 ` paper42
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