From b5a1450724eda606163e05837b9ec028e9a833a3 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 00:10:22 +0100 Subject: [PATCH 001/189] go: add riscv64 --- common/environment/build-style/go.sh | 5 +++-- srcpkgs/go/template | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common/environment/build-style/go.sh b/common/environment/build-style/go.sh index 74db82b2a1ce5..223bba83ff11b 100644 --- a/common/environment/build-style/go.sh +++ b/common/environment/build-style/go.sh @@ -1,7 +1,7 @@ if [ -z "$hostmakedepends" -o "${hostmakedepends##*gcc-go-tools*}" ]; then # gc compiler if [ -z "$archs" ]; then - archs="aarch64* armv[567]* i686* x86_64* ppc64le*" + archs="aarch64* armv[567]* i686* x86_64* ppc64le* riscv64*" fi hostmakedepends+=" go" nopie=yes @@ -9,7 +9,7 @@ else # gccgo compiler if [ -z "$archs" ]; then # we have support for these in our gcc - archs="aarch64* armv[567]* i686* x86_64* ppc64*" + archs="aarch64* armv[567]* i686* x86_64* ppc64* riscv64*" fi if [ "$CROSS_BUILD" ]; then # target compiler to use; otherwise it'll just call gccgo @@ -29,6 +29,7 @@ case "$XBPS_TARGET_MACHINE" in ppc*) export GOARCH=ppc;; mipsel*) export GOARCH=mipsle;; mips*) export GOARCH=mips;; + riscv64*) export GOARCH=riscv64;; esac export GOPATH="${wrksrc}/_build-${pkgname}-xbps" diff --git a/srcpkgs/go/template b/srcpkgs/go/template index dea0969cdb051..d077161ff441f 100644 --- a/srcpkgs/go/template +++ b/srcpkgs/go/template @@ -25,6 +25,7 @@ case "${XBPS_TARGET_MACHINE}" in x86_64*) _goarch=amd64 ;; ppc64le*) _goarch=ppc64le ;; mips*) _goarch=mips ;; + riscv64*) _goarch=riscv64 ;; *) broken="Unsupported architecture ${XBPS_TARGET_MACHINE}" ;; esac From 2b84e29f8ee28587f397f7bd3722e7d17e9b2555 Mon Sep 17 00:00:00 2001 From: John Date: Mon, 16 Jan 2023 22:15:02 +0100 Subject: [PATCH 002/189] build-style/cmake.sh: add riscv64 arch --- common/build-style/cmake.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/common/build-style/cmake.sh b/common/build-style/cmake.sh index a38c3413f62ca..36331635ddd62 100644 --- a/common/build-style/cmake.sh +++ b/common/build-style/cmake.sh @@ -31,6 +31,7 @@ _EOF ppc64*) _CMAKE_SYSTEM_PROCESSOR=ppc64 ;; ppcle*) _CMAKE_SYSTEM_PROCESSOR=ppcle ;; ppc*) _CMAKE_SYSTEM_PROCESSOR=ppc ;; + riscv64*) _CMAKE_SYSTEM_PROCESSOR=riscv64 ;; *) _CMAKE_SYSTEM_PROCESSOR=generic ;; esac cat > cross_${XBPS_CROSS_TRIPLET}.cmake <<_EOF From 61214344a63509fcef77592b17eac03bba66f6d5 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Thu, 18 Jul 2019 11:07:04 +0200 Subject: [PATCH 003/189] add configure/autoconf_cache/riscv64-linux --- .../configure/autoconf_cache/riscv64-linux | 148 ++++++++++++++++++ .../configure/gnu-configure-args.sh | 4 + 2 files changed, 152 insertions(+) create mode 100644 common/environment/configure/autoconf_cache/riscv64-linux diff --git a/common/environment/configure/autoconf_cache/riscv64-linux b/common/environment/configure/autoconf_cache/riscv64-linux new file mode 100644 index 0000000000000..2b0d518d10b46 --- /dev/null +++ b/common/environment/configure/autoconf_cache/riscv64-linux @@ -0,0 +1,148 @@ + +## # general +#ac_cv_va_val_copy=${ac_cv_va_val_copy=yes} +#ac_cv_func_lstat_dereferences_slashed_symlink=${ac_cv_func_lstat_dereferences_slashed_symlink=yes} +## ac_cv_func_lstat_empty_string_bug=${ac_cv_func_lstat_empty_string_bug=no} +## ac_cv_func_posix_getpwnam_r=${ac_cv_func_posix_getpwnam_r=yes} +## ac_cv_func_setvbuf_reversed=${ac_cv_func_setvbuf_reversed=no} +## ac_cv_func_stat_empty_string_bug=${ac_cv_func_stat_empty_string_bug=no} +## ac_cv_func_stat_ignores_trailing_slash=${ac_cv_func_stat_ignores_trailing_slash=no} +## ac_libnet_have_packet_socket=${ac_libnet_have_packet_socket=yes} +## ac_cv_linux_vers=${ac_cv_linux_vers=2} +## ac_cv_need_trio=${ac_cv_need_trio=no} +#ac_cv_sizeof___int64=0 +#ac_cv_sizeof_char=1 +c_cv_sizeof_int=${ac_cv_sizeof_int=4} +ac_cv_sizeof_long=${ac_cv_sizeof_long=8} +ac_cv_sizeof_off_t=${ac_cv_sizeof_off_t=8} +ac_cv_sizeof_long_int=${ac_cv_sizeof_long_int=8} +#ac_cv_sizeof_long_long=8 +#ac_cv_sizeof_short=2 +#ac_cv_sizeof_size_t=8 +#ac_cv_sizeof_ssize_t=8 +#ac_cv_sizeof_void_p=8 +#ac_cv_sizeof_unsigned_int=4 +#ac_cv_sizeof_unsigned_long=8 +ac_cv_sizeof_bool=1 +## ac_cv_sizeof_long_double=${ac_cv_sizeof_long_double=16} +## ac_cv_sizeof_long_long=${ac_cv_sizeof_long_long=8} +#ac_cv_sizeof_unsigned_short=2 +## ac_cv_sizeof_short_int=${ac_cv_sizeof_short_int=2} +## ac_cv_sizeof_size_t=${ac_cv_sizeof_size_t=8} +## ac_cv_sizeof_uid_t=${ac_cv_sizeof_uid_t=4} +## ac_cv_sizeof_gid_t=${ac_cv_sizeof_gid_t=4} +## ac_cv_sizeof_ino_t=${ac_cv_sizeof_ino_t=8} +## ac_cv_sizeof_dev_t=${ac_cv_sizeof_dev_t=8} +## ac_cv_sizeof_void_p=${ac_cv_sizeof_void_p=8} +## ac_cv_strerror_r_SUSv3=${ac_cv_strerror_r_SUSv3=no} +## db_cv_alignp_t=${db_cv_alignp_t='unsigned long long'} +## db_cv_align_t=${db_cv_align_t='unsigned long long'} +## db_cv_fcntl_f_setfd=${db_cv_fcntl_f_setfd=yes} +## db_cv_sprintf_count=${db_cv_sprintf_count=yes} +## ac_cv_sizeof_struct_iovec=16 + +# glib +#glib_cv_hasinline=${glib_cv_hasinline=yes} +#glib_cv_has__inline=${glib_cv_has__inline=yes} +#glib_cv_has__inline__=${glib_cv_has__inline__=yes} +#glib_cv_long_long_format=${glib_cv_long_long_format=ll} +#glib_cv_rtldglobal_broken=${glib_cv_rtldglobal_broken=no} +glib_cv_stack_grows=${glib_cv_stack_grows=no} +glib_cv_uscore=${glib_cv_uscore=no} +#glib_cv_va_val_copy=${glib_cv_va_val_copy=yes} +#ac_cv_alignof_guint32=4 +#ac_cv_alignof_guint64=8 +#ac_cv_alignof_unsigned_long=8 +#ac_cv_alignof_char=1 +#ac_cv_alignof_double=8 + +## nano_cv_func_regexec_segv_emptystr=${nano_cv_func_regexec_segv_emptystr=no} +## samba_cv_HAVE_VA_COPY=${samba_cv_HAVE_VA_COPY=yes} +## utils_cv_sys_open_max=${utils_cv_sys_open_max=1015} + +# gettext +am_cv_func_working_getline=${am_cv_func_working_getline=yes} + +#gcc +#ac_cv_lib_m_sin=${ac_cv_lib_m_sin=yes} + +#orbit +#libIDL_cv_long_long_format=ll + +## # ORBit2 +## ac_cv_alignof_CORBA_boolean=1 +## ac_cv_alignof_CORBA_char=1 +## ac_cv_alignof_CORBA_double=8 +## ac_cv_alignof_CORBA_float=4 +## ac_cv_alignof_CORBA_long=4 +## ac_cv_alignof_CORBA_long_double=8 +## ac_cv_alignof_CORBA_long_long=8 +## ac_cv_alignof_CORBA_octet=1 +## ac_cv_alignof_CORBA_pointer=8 +## ac_cv_alignof_CORBA_short=2 +## ac_cv_alignof_CORBA_struct=1 +## ac_cv_alignof_CORBA_wchar=2 +## +## lf_cv_sane_realloc=yes +as_cv_unaligned_access=${as_cv_unaligned_access=no} +## +## #unfs3 +## nfsd_cv_broken_setfsuid=${nfsd_cv_broken_setfsuid=0} +## nfsd_cv_func_statfs=${nfsd_cv_func_statfs=statfs2_bsize} +## nfsd_cv_bsd_signals=${nfsd_cv_bsd_signals=yes} + +#apr +apr_cv_tcp_nodelay_with_cork=${apr_cv_tcp_nodelay_with_cork=yes} + +# lftp +lftp_cv_va_val_copy=${lftp_cv_va_val_copy=yes} + +# slrn +slrn_cv_va_val_copy=${slrn_cv_va_val_copy=yes} + +# cvs +cvs_cv_func_printf_ptr=${cvs_cv_func_printf_ptr=yes} + +## # at-spi2-core +#ac_cv_alignof_dbind_pointer=8 +#ac_cv_alignof_dbind_struct=1 +#ac_cv_alignof_dbus_bool_t=4 +#ac_cv_alignof_dbus_int16_t=2 +#ac_cv_alignof_dbus_int32_t=4 +#ac_cv_alignof_dbus_int64_t=8 + +## # socat +#sc_cv_type_dev_basic='6 /* unsigned long */' +#sc_cv_type_gidt_basic='4 /* unsigned int */' +#sc_cv_type_longlong=yes +#sc_cv_type_modet_basic='4 /* unsigned int */' +#sc_cv_type_off64=yes +#sc_cv_type_off64_basic='5 /* long */' +#sc_cv_type_off_basic='5 /* long */' +#sc_cv_type_pidt_basic='3 /* int */' +#sc_cv_type_rlimit_rlimmax_basic='6 /* unsigned long */' +#sc_cv_type_sa_family_t=yes +#sc_cv_type_sighandler=yes +#sc_cv_type_sizet_basic='6 /* unsigned long */' +#sc_cv_type_socklen=yes +#sc_cv_type_socklent_basic='4 /* unsigned int */' +#sc_cv_type_stat64=yes +#sc_cv_type_stat64_stblksize_basic='3 /* int */' +#sc_cv_type_stat64_stblocks_basic='5 /* long */' +#sc_cv_type_stat64_stdev_basic='6 /* unsigned long */' +#sc_cv_type_stat64_stino_basic='6 /* unsigned long */' +#sc_cv_type_stat64_stnlink_basic='4 /* unsigned int */' +#sc_cv_type_stat64_stsize_basic='5 /* long */' +#sc_cv_type_stat_stblksize_basic='3 /* int */' +#sc_cv_type_stat_stblocks_basic='5 /* long */' +#sc_cv_type_stat_stino_basic='6 /* unsigned long */' +#sc_cv_type_stat_stnlink_basic='4 /* unsigned int */' +#sc_cv_type_stat_stsize_basic='5 /* long */' +#sc_cv_type_struct_timeval_tv_usec='5 /* long */' +#sc_cv_type_timet_basic='5 /* long */' +#sc_cv_type_uidt_basic='4 /* unsigned int */' +#sc_cv_type_uint16=yes +#sc_cv_type_uint32=yes +#sc_cv_type_uint64=yes +#sc_cv_type_uint8=yes +#sc_cv_typeof_struct_cmsghdr_cmsg_len='6 /* unsigned long */' diff --git a/common/environment/configure/gnu-configure-args.sh b/common/environment/configure/gnu-configure-args.sh index dafbf5dc110c8..1a552b5074a07 100644 --- a/common/environment/configure/gnu-configure-args.sh +++ b/common/environment/configure/gnu-configure-args.sh @@ -123,6 +123,10 @@ case "$XBPS_TARGET_MACHINE" in . ${_AUTOCONFCACHEDIR}/powerpc-linux . ${_AUTOCONFCACHEDIR}/powerpc32-linux ;; + riscv*) + . ${_AUTOCONFCACHEDIR}/endian-little + . ${_AUTOCONFCACHEDIR}/riscv64-linux + ;; *) ;; esac From 8cae638ea712f59866ed9517bcc911c18e1bdd80 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Wed, 17 Jul 2019 16:55:24 +0200 Subject: [PATCH 004/189] add riscv64 profiles --- common/build-profiles/riscv64-musl.sh | 7 +++++++ common/cross-profiles/riscv64-musl.sh | 12 ++++++++++++ common/xbps-src/shutils/common.sh | 2 ++ 3 files changed, 21 insertions(+) create mode 100644 common/build-profiles/riscv64-musl.sh create mode 100644 common/cross-profiles/riscv64-musl.sh diff --git a/common/build-profiles/riscv64-musl.sh b/common/build-profiles/riscv64-musl.sh new file mode 100644 index 0000000000000..4d31a667d84dd --- /dev/null +++ b/common/build-profiles/riscv64-musl.sh @@ -0,0 +1,7 @@ +XBPS_TARGET_CFLAGS="-march=rv64imafdc" +XBPS_TARGET_CXXFLAGS="$XBPS_TARGET_CFLAGS" +XBPS_TARGET_FFLAGS="$XBPS_TARGET_CFLAGS" +XBPS_TRIPLET="riscv64-unknown-linux-musl" +XBPS_RUST_TARGET="riscv64gc-unknown-linux-musl" +XBPS_ZIG_TARGET="riscv64-linux-musl" +XBPS_ZIG_CPU="baseline" diff --git a/common/cross-profiles/riscv64-musl.sh b/common/cross-profiles/riscv64-musl.sh new file mode 100644 index 0000000000000..e3f30cdca0a4b --- /dev/null +++ b/common/cross-profiles/riscv64-musl.sh @@ -0,0 +1,12 @@ +# Cross build profile for riscv64 and Musl libc. + +XBPS_TARGET_MACHINE="riscv64-musl" +XBPS_TARGET_QEMU_MACHINE="riscv64" +XBPS_CROSS_TRIPLET="riscv64-linux-musl" +XBPS_CROSS_CFLAGS="-march=rv64imafdc" +XBPS_CROSS_CXXFLAGS="$XBPS_CROSS_CFLAGS" +XBPS_CROSS_FFLAGS="$XBPS_CROSS_CFLAGS" +XBPS_CROSS_RUSTFLAGS="--sysroot=${XBPS_CROSS_BASE}/usr" +XBPS_CROSS_RUST_TARGET="riscv64gc-unknown-linux-musl" +XBPS_CROSS_ZIG_TARGET="riscv64-linux-musl" +XBPS_CROSS_ZIG_CPU="baseline" diff --git a/common/xbps-src/shutils/common.sh b/common/xbps-src/shutils/common.sh index 2218d34ce30b5..fec84c8f85e0d 100644 --- a/common/xbps-src/shutils/common.sh +++ b/common/xbps-src/shutils/common.sh @@ -289,6 +289,7 @@ get_endian() { ppc*le) echo "le";; ppc*) echo "be";; x86_64) echo "le";; + riscv64) echo "le";; esac } @@ -316,6 +317,7 @@ get_wordsize() { ppc64*) echo "64";; ppc*) echo "32";; x86_64) echo "64";; + riscv64) echo "64";; esac } From bc21e0c26cf5be336a38ec55286b6678754cbf06 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:09 +0200 Subject: [PATCH 005/189] bluedevil: update to 5.27.7. --- srcpkgs/bluedevil/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/bluedevil/template b/srcpkgs/bluedevil/template index 91af92c573f78..1bc3fcd94d8c2 100644 --- a/srcpkgs/bluedevil/template +++ b/srcpkgs/bluedevil/template @@ -1,6 +1,6 @@ # Template file for 'bluedevil' pkgname=bluedevil -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -14,4 +14,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/bluedevil" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=7ceff877200edd7043a57aeba3bf54828b2d96501b4e58497b6f0ec01b73df74 +checksum=cbc1aea8cceefd68a015098101de669df9a4d619a7a7baeb823b1b60b362bf35 From e6e71a5256f1bdf492cc130363fb4463dcb6a147 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:11 +0200 Subject: [PATCH 006/189] breeze-gtk: update to 5.27.7. --- srcpkgs/breeze-gtk/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/breeze-gtk/template b/srcpkgs/breeze-gtk/template index f5b66efa76336..4f862119300b2 100644 --- a/srcpkgs/breeze-gtk/template +++ b/srcpkgs/breeze-gtk/template @@ -1,6 +1,6 @@ # Template file for 'breeze-gtk' pkgname=breeze-gtk -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules sassc python3 python3-cairo qt5-devel" @@ -10,4 +10,4 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/breeze-gtk" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=ac2aab13b9224ddea6560fdbac9fe9d93a08a86787f95b95c43a95b134836bda +checksum=293294ed0b51c07496fe8c2ede841eb6e2ef41926725e11658c7208543d958e8 From 1584380c08738bd7301e62a5288d5118715d3001 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:24 +0200 Subject: [PATCH 007/189] breeze: update to 5.27.7. --- srcpkgs/breeze/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/breeze/template b/srcpkgs/breeze/template index 598469f2b1202..fe8e7854ada10 100644 --- a/srcpkgs/breeze/template +++ b/srcpkgs/breeze/template @@ -1,6 +1,6 @@ # Template file for 'breeze' pkgname=breeze -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -14,7 +14,7 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/breeze" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=5d9a8d7e5b061ce4183c4f842b0e82e6132b6c8e7ebc2c1d579baa066ffa6c6c +checksum=bffdcf314009b6fcb0202a58e48b3e62a4cbf741f5f299c257998f46dea4ccf1 if [ "$CROSS_BUILD" ]; then configure_args+=" -DKF5_HOST_TOOLING=/usr/lib/cmake" From f3b6ca9b08b99d22796003347dded64e7d32510a Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:25 +0200 Subject: [PATCH 008/189] flatpak-kcm: update to 5.27.7. --- srcpkgs/flatpak-kcm/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/flatpak-kcm/template b/srcpkgs/flatpak-kcm/template index cf5fba05e127b..cb6c1818b4a3f 100644 --- a/srcpkgs/flatpak-kcm/template +++ b/srcpkgs/flatpak-kcm/template @@ -1,6 +1,6 @@ # Template file for 'flatpak-kcm' pkgname=flatpak-kcm -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/flatpak-kcm" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=fcee94bb9eeb58db5b304e16b5db060d8f559e1b10b202e83ab8e342be927f7a +checksum=a2ec35e31524c21f377a3687bd8c419765570e35299ecb3f5351a26eddee32b3 From 088b0a4ba9a9196004eab819a87f5815da105b94 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:25 +0200 Subject: [PATCH 009/189] kactivitymanagerd: update to 5.27.7. --- srcpkgs/kactivitymanagerd/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kactivitymanagerd/template b/srcpkgs/kactivitymanagerd/template index 2c98ca84032a9..abd4e1849c44b 100644 --- a/srcpkgs/kactivitymanagerd/template +++ b/srcpkgs/kactivitymanagerd/template @@ -1,6 +1,6 @@ # Template file for 'kactivitymanagerd' pkgname=kactivitymanagerd -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake build_helper="qemu" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kactivitymanagerd" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=06180b32ad64f88e2f3ea598e887c42cf68189dba14b220dceafcb0490c5b02d +checksum=2df245330612d79090980269ad7c4e776150598e583761ac83f628cc1ffafbb4 From 39a747ab33e9aaee04f3e297006952d3b9c28b3e Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:26 +0200 Subject: [PATCH 010/189] kde-cli-tools: update to 5.27.7. --- srcpkgs/kde-cli-tools/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kde-cli-tools/template b/srcpkgs/kde-cli-tools/template index f8b1d7f7fc91a..eb6fc7acdb60c 100644 --- a/srcpkgs/kde-cli-tools/template +++ b/srcpkgs/kde-cli-tools/template @@ -1,6 +1,6 @@ # Template file for 'kde-cli-tools' pkgname=kde-cli-tools -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -14,7 +14,7 @@ maintainer="John " license="LGPL-2.1-or-later, GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kde-cli-tools" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=b5e2b1c3bf82c112c8488aea73dca11a49963ea66e66db8f358f8e0394ba0faa +checksum=aadb24e6153451111c22574ee27b1e562ba5e923f0a260a817ed58a2168a21af post_install() { ln -sf ../libexec/kf5/kdesu ${DESTDIR}/usr/bin From f46748b7721c4612226703b728b12c76989dd379 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:27 +0200 Subject: [PATCH 011/189] kde-gtk-config5: update to 5.27.7. --- srcpkgs/kde-gtk-config5/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kde-gtk-config5/template b/srcpkgs/kde-gtk-config5/template index 4a47776d0c872..d7107da10c95e 100644 --- a/srcpkgs/kde-gtk-config5/template +++ b/srcpkgs/kde-gtk-config5/template @@ -1,6 +1,6 @@ # Template file for 'kde-gtk-config5' pkgname=kde-gtk-config5 -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -14,7 +14,7 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kde-gtk-config" distfiles="${KDE_SITE}/plasma/${version}/${pkgname%5}-${version}.tar.xz" -checksum=b3f23a5602530b77d55ff08e108692576740de056edb01f7b1bc3843d890f820 +checksum=ae2a1e468f4132a8efcf61818847d453e73f8b7010d900a6a1406fd7de901c8f if [ "$CROSS_BUILD" ]; then hostmakedepends+=" kcoreaddons" From 2b351c0626b44db25cde980512aec29e76411a30 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:28 +0200 Subject: [PATCH 012/189] kdecoration: update to 5.27.7. --- srcpkgs/kdecoration/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kdecoration/template b/srcpkgs/kdecoration/template index 1ec3497326ff2..d3a56905bf361 100644 --- a/srcpkgs/kdecoration/template +++ b/srcpkgs/kdecoration/template @@ -1,6 +1,6 @@ # Template file for 'kdecoration' pkgname=kdecoration -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -12,7 +12,7 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kdecoration" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=9db69b439a9a6c863c5be74ba380964087c83b0f438aeaf6d0a97f5fd05294e6 +checksum=ef26a499d51f4da9e6c25a0209d08b5e8dcedddc86e066537f46f20f001f7294 kdecoration-devel_package() { short_desc+=" - development" From 1519f94f61e36d26386a41e734b71a323153d7bc Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:29 +0200 Subject: [PATCH 013/189] kdeplasma-addons5: update to 5.27.7. --- srcpkgs/kdeplasma-addons5/template | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/srcpkgs/kdeplasma-addons5/template b/srcpkgs/kdeplasma-addons5/template index b3ce923df439a..17ecf3474d8ad 100644 --- a/srcpkgs/kdeplasma-addons5/template +++ b/srcpkgs/kdeplasma-addons5/template @@ -1,7 +1,7 @@ # Template file for 'kdeplasma-addons5' pkgname=kdeplasma-addons5 -version=5.27.6 -revision=2 +version=5.27.7 +revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" hostmakedepends="extra-cmake-modules qt5-qmake qt5-host-tools pkg-config @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kdeplasma-addons" distfiles="${KDE_SITE}/plasma/${version}/${pkgname%5}-${version}.tar.xz" -checksum=343b0d40a81bf498633c71a138902b43e61461fcae2209b6f09e7cf6c8baf087 +checksum=51c73d8872fce7f3bc54a8fbf480a40c0178d63f703fe696721d046f3a25ef50 From e408f9ceff76a79022b93d25e03bf8210b171444 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:29 +0200 Subject: [PATCH 014/189] kgamma5: update to 5.27.7. --- srcpkgs/kgamma5/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kgamma5/template b/srcpkgs/kgamma5/template index 8ff8cdf39889e..e29cf6f72459e 100644 --- a/srcpkgs/kgamma5/template +++ b/srcpkgs/kgamma5/template @@ -1,6 +1,6 @@ # Template file for 'kgamma5' pkgname=kgamma5 -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kgamma5" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=61f111ecccd2fae7f46a1c7ef80d49a21bd80d8aadb65541453df134351fd692 +checksum=d45e88d4ee1c6cffa0b5ef085c4a7d028ade37e2daa72253e74941d9bcf5ae6c From f77dd0673875effb72578db2d6847566a7bf02f2 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:30 +0200 Subject: [PATCH 015/189] khotkeys: update to 5.27.7. --- srcpkgs/khotkeys/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/khotkeys/template b/srcpkgs/khotkeys/template index 979bf131d8256..3a1d3b9ef094f 100644 --- a/srcpkgs/khotkeys/template +++ b/srcpkgs/khotkeys/template @@ -1,6 +1,6 @@ # Template file for 'khotkeys' pkgname=khotkeys -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -12,7 +12,7 @@ maintainer="John " license="GPL-2.0-only, LGPL-2.0-or-later" homepage="https://invent.kde.org/plasma/khotkeys" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=dbc7ec600e0450901648e6513f25f7c1ccad6798ce38b70437258daa6d833d7e +checksum=6d85041dc59a4e0c6726c97c3f30caf6d22b8f960bcfc39fcdd294f16538efc6 if [ "$CROSS_BUILD" ]; then configure_args+=" -DDESKTOPTOJSON_EXECUTABLE=/usr/bin/desktoptojson" From dea229ec0bfceacc0a4ec30c985892e74459744e Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:31 +0200 Subject: [PATCH 016/189] kinfocenter: update to 5.27.7. --- srcpkgs/kinfocenter/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kinfocenter/template b/srcpkgs/kinfocenter/template index 937d78309c506..4a12714c50b84 100644 --- a/srcpkgs/kinfocenter/template +++ b/srcpkgs/kinfocenter/template @@ -1,6 +1,6 @@ # Template file for 'kinfocenter' pkgname=kinfocenter -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -16,4 +16,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later, GFDL-1.2-only" homepage="https://invent.kde.org/plasma/kinfocenter" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=cd96e9952cc8c73337dda0786d45f3f381ca5137f8eca5feee2209f63981901b +checksum=72ee8872213f08c2d910e82712db2d24773c28701cdbb9e7d23f671791401596 From 2d4e93f8fce1a38a1db542d03484b61832f2212f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:32 +0200 Subject: [PATCH 017/189] kmenuedit: update to 5.27.7. --- srcpkgs/kmenuedit/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kmenuedit/template b/srcpkgs/kmenuedit/template index 15080cf358a34..51053197878d8 100644 --- a/srcpkgs/kmenuedit/template +++ b/srcpkgs/kmenuedit/template @@ -1,6 +1,6 @@ # Template file for 'kmenuedit' pkgname=kmenuedit -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kmenuedit" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=89144ffa83855627506cae2c10e5e646f3f1efd839121b1d7eb595b7c51a4696 +checksum=67abf2bf9166c0c7797442edcfc5d6f7eba4a575ac689859b651eac509f9c058 From a4d784a2df0359fad1fd637bf3a834ae7265abf8 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:33 +0200 Subject: [PATCH 018/189] kpipewire: update to 5.27.7. --- srcpkgs/kpipewire/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kpipewire/template b/srcpkgs/kpipewire/template index db4e42f0d456a..c9132e561ae49 100644 --- a/srcpkgs/kpipewire/template +++ b/srcpkgs/kpipewire/template @@ -1,6 +1,6 @@ # Template file for 'kpipewire' pkgname=kpipewire -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules plasma-wayland-protocols gettext @@ -13,7 +13,7 @@ maintainer="John " license="GPL-3.0-or-later" homepage="https://invent.kde.org/plasma/kpipewire" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=7ed653bfc0e82aa32e05766def3466937a5b2e31abbf3d50c9298b23e6e4328b +checksum=0ad273b8875c0472e0b4f4332c9f1a5d93dca6533f978fd0606094bd91d24782 kpipewire-devel_package() { depends="${sourcepkg}>=${version}_${revision}" From 868b02d962c252a9cba75b5cf19b05ace0ad03f6 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:34 +0200 Subject: [PATCH 019/189] kscreen: update to 5.27.7. --- srcpkgs/kscreen/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kscreen/template b/srcpkgs/kscreen/template index 4fc07d033b23f..47af27ed4a6e5 100644 --- a/srcpkgs/kscreen/template +++ b/srcpkgs/kscreen/template @@ -1,6 +1,6 @@ # Template file for 'kscreen' pkgname=kscreen -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -14,4 +14,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kscreen" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=ded0651eec67e22f22fa3d6b0dbb03e81bfb2d4e5a7468e9efc5f5a4598bf254 +checksum=38d755e1b01584e1c21a925b2ab046c0f8f977bb1c4e75d436ebc9c633160a0f From dbce48ba078e42d7434dd842c2a9f1762d221364 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:35 +0200 Subject: [PATCH 020/189] kscreenlocker: update to 5.27.7. --- srcpkgs/kscreenlocker/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kscreenlocker/template b/srcpkgs/kscreenlocker/template index c4c134123d911..762fd6480bb7b 100644 --- a/srcpkgs/kscreenlocker/template +++ b/srcpkgs/kscreenlocker/template @@ -1,6 +1,6 @@ # Template file for 'kscreenlocker' pkgname=kscreenlocker -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -14,7 +14,7 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kscreenlocker" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=5d04960f82895a15e51ad07238a394e347f28815ab93e9f5a97106c21bf1f55d +checksum=c2013b510ed714b0f2544b37393b82cb1d6699dec829c8906d10dd249a9ec387 kscreenlocker-devel_package() { short_desc+=" - development" From d8e2a799f6d1f1a98abd9600e14ecdc6d05da8cf Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:35 +0200 Subject: [PATCH 021/189] ksshaskpass: update to 5.27.7. --- srcpkgs/ksshaskpass/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/ksshaskpass/template b/srcpkgs/ksshaskpass/template index 117ee058efa97..ff5af28f4a70b 100644 --- a/srcpkgs/ksshaskpass/template +++ b/srcpkgs/ksshaskpass/template @@ -1,6 +1,6 @@ # Template file for 'ksshaskpass' pkgname=ksshaskpass -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -12,5 +12,5 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/ksshaskpass" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=854cad79eb8b27685e97c4f62fd96e97744fc6a38491f156c047d0bce5c6e8c5 +checksum=e13175acf1ac1eb95a2454ab30b57e1e829a32145a7acf931f892546e46ebe6e alternatives="ssh-askpass:/usr/libexec/ssh-askpass:/usr/bin/ksshaskpass" From f64764f23b4af624ac0de51a545954bb6f109280 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:36 +0200 Subject: [PATCH 022/189] ksystemstats: update to 5.27.7. --- srcpkgs/ksystemstats/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/ksystemstats/template b/srcpkgs/ksystemstats/template index d503471bdc570..4d762de8fa8e6 100644 --- a/srcpkgs/ksystemstats/template +++ b/srcpkgs/ksystemstats/template @@ -1,6 +1,6 @@ # Template file for 'ksystemstats' pkgname=ksystemstats -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules qt5-qmake gettext @@ -12,4 +12,4 @@ maintainer="John " license="GPL-2.0-only OR GPL-3.0-only, LGPL-2.1-only OR LGPL-3-only" homepage="https://invent.kde.org/plasma/ksystemstats" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=f1810ac6641bb17c42a90f643ef0fb45226e9b155601dd1827ccaf302ffa2376 +checksum=7c3f8998e6f5abd1adfd22fe6272b9f178bb4db716a3d8dfc162f46e4c59a5bb From 61d006b2c409bc2358e0e61a5606305fdc367d7a Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:37 +0200 Subject: [PATCH 023/189] kwallet-pam: update to 5.27.7. --- srcpkgs/kwallet-pam/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kwallet-pam/template b/srcpkgs/kwallet-pam/template index 6b8834e7d388b..717c6fe6641a4 100644 --- a/srcpkgs/kwallet-pam/template +++ b/srcpkgs/kwallet-pam/template @@ -1,6 +1,6 @@ # Template file for 'kwallet-pam' pkgname=kwallet-pam -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="qt5-qmake qt5-host-tools extra-cmake-modules" @@ -11,4 +11,4 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kwallet-pam" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=b7adf0065f20855edc18959f5fa661f79fe53081cc35d4c4df242988e3d16830 +checksum=2b3bf57d4d1108c64fdaee7b3b14008636ff8316d9dd8325206f47fc2f8680a9 From e263147e9b2fd6764c6e121865e496f8c03660bd Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:38 +0200 Subject: [PATCH 024/189] kwayland-integration: update to 5.27.7. --- srcpkgs/kwayland-integration/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kwayland-integration/template b/srcpkgs/kwayland-integration/template index e2395bb392d94..d8ebaf6b84b6a 100644 --- a/srcpkgs/kwayland-integration/template +++ b/srcpkgs/kwayland-integration/template @@ -1,6 +1,6 @@ # Template file for 'kwayland-integration' pkgname=kwayland-integration -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,4 +13,4 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/kwayland-integration" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=10b7db4dfa276fe4e2398f742f60459367c5db1c91f8a9015e06e9f51e092c83 +checksum=1e7997688a329563f62ce7534e82326a4317d9ecf12403d12e70d4d237316ebb From 1a9cfcf69bfa209622876606f7d94fec6ab71c50 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:40 +0200 Subject: [PATCH 025/189] kwin: update to 5.27.7. --- srcpkgs/kwin/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kwin/template b/srcpkgs/kwin/template index 91a1176995720..8fb205e8adcbe 100644 --- a/srcpkgs/kwin/template +++ b/srcpkgs/kwin/template @@ -1,6 +1,6 @@ # Template file for 'kwin' pkgname=kwin -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake build_helper=qemu @@ -21,7 +21,7 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kwin" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=62d5bd5e91e951c9ad8c2fc49c29485feca78db985731f0779cdaaf5052499ec +checksum=cbff55ba018463bc05ba286663aea1d7b0f48993dc3c778b5514e34fcdb95a2f replaces="kwayland-server>=0" kwin-devel_package() { From 8c288481fda753340eadfdc5d2801a69a0d5e8e6 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:40 +0200 Subject: [PATCH 026/189] kwrited: update to 5.27.7. --- srcpkgs/kwrited/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/kwrited/template b/srcpkgs/kwrited/template index 106bfabc1b529..fbdfcf7c52ef6 100644 --- a/srcpkgs/kwrited/template +++ b/srcpkgs/kwrited/template @@ -1,6 +1,6 @@ # Template file for 'kwrited' pkgname=kwrited -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -11,4 +11,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/kwrited" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=0665240812594b9c5ec20b24dde1734bedc33f1440eb8591e72429ab2b1a7894 +checksum=16ec41745cbbe5c162d5808ab24663dc74248c719d324c81047fd1657d018fa8 From f2c885c23a8a9337a48ab427101d8e4583e47adc Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:41 +0200 Subject: [PATCH 027/189] layer-shell-qt: update to 5.27.7. --- srcpkgs/layer-shell-qt/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/layer-shell-qt/template b/srcpkgs/layer-shell-qt/template index 6f6e1735ca6dc..0e8ea322d8884 100644 --- a/srcpkgs/layer-shell-qt/template +++ b/srcpkgs/layer-shell-qt/template @@ -1,6 +1,6 @@ # Template file for 'layer-shell-qt' pkgname=layer-shell-qt -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake confiugre_args="-DWaylandScanner_EXECUTABLE=/usr/bin/wayland-scanner" @@ -13,7 +13,7 @@ maintainer="John " license="GPL-3.0-or-later" homepage="https://invent.kde.org/plasma/layer-shell-qt" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=e65c29ca65bf945da4f53bce9eb3614eb1105e57652e3fb1782ee9d24a9e8793 +checksum=27c44e7db73bf2aa6728719e8bb848c1b0c1c7a704c86349a419577920c6f421 layer-shell-qt-devel_package() { depends="${sourcepkg}>=${version}_${revision}" From 90f778760354ebc5cb60efd4dfab17638aba6b77 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:42 +0200 Subject: [PATCH 028/189] libkscreen: update to 5.27.7. --- srcpkgs/libkscreen/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/libkscreen/template b/srcpkgs/libkscreen/template index d15037a28a7b6..27c3c14593b42 100644 --- a/srcpkgs/libkscreen/template +++ b/srcpkgs/libkscreen/template @@ -1,6 +1,6 @@ # Template file for 'libkscreen' pkgname=libkscreen -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,7 +13,7 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/libkscreen" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=c1a9373faab5a7ec77980a696a7599583b4fda8e1f12da2c5716bc9562789efb +checksum=86b51bf3406c353afd7a2e1f47e2511d060313d8bd8a2ef7fa73a3bf153e3eab libkscreen-devel_package() { short_desc+=" - development" From e529e69b66094d8558b7858fccbd5782398acc29 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:43 +0200 Subject: [PATCH 029/189] libksysguard: update to 5.27.7. --- srcpkgs/libksysguard/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/libksysguard/template b/srcpkgs/libksysguard/template index 9ca1ac1dd256d..ad183e28bdfeb 100644 --- a/srcpkgs/libksysguard/template +++ b/srcpkgs/libksysguard/template @@ -1,6 +1,6 @@ # Template file for 'libksysguard' pkgname=libksysguard -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules gettext kauth qt5-host-tools qt5-qmake @@ -13,7 +13,7 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/libksysguard" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=9ecb2cb4aab6ba8f0b790267f22aab48244a78c6370b86eb662a0480fb031bdb +checksum=682a939252e35a52b7f95a6f5bfcc7cb983fa3b5275ae3b377ab8040b292cb18 build_options="webengine" From 53635de8c80050db3318858ac6125f0bfcaeb858 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:43 +0200 Subject: [PATCH 030/189] milou: update to 5.27.7. --- srcpkgs/milou/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/milou/template b/srcpkgs/milou/template index ea8e16b85ef97..fd2e6db0c82f6 100644 --- a/srcpkgs/milou/template +++ b/srcpkgs/milou/template @@ -1,6 +1,6 @@ # Template file for 'milou' pkgname=milou -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -12,7 +12,7 @@ maintainer="John " license="GPL-2.0-or-later, LPGL-2.1-or-later" homepage="https://invent.kde.org/plasma/milou" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=feaea739bc100f313d098a13614b16c01bdafc7dbe0e9ebed5e7a6d8cfd381c6 +checksum=81690bffc9d58445c09af64670d80cd53735db2f0da36a4847d3466ec5a90853 if [ "$CROSS_BUILD" ]; then hostmakedepends+=" kpackage-devel kconfig-devel kcoreaddons-devel plasma-framework" From 82cee0ce0aa0972fc8b2268112f916e3eea63cd2 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:44 +0200 Subject: [PATCH 031/189] oxygen-sounds: update to 5.27.7. --- srcpkgs/oxygen-sounds/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/oxygen-sounds/template b/srcpkgs/oxygen-sounds/template index d631f4127513d..b602687ddbef4 100644 --- a/srcpkgs/oxygen-sounds/template +++ b/srcpkgs/oxygen-sounds/template @@ -1,6 +1,6 @@ # Template file for 'oxygen-sounds' pkgname=oxygen-sounds -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules" @@ -9,4 +9,4 @@ maintainer="John " license="LGPL-3.0-or-later" homepage="https://invent.kde.org/plasma/oxygen-sounds" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=afeaf30c41d191e43582d41601102b17effa2b9c2e65c61ca6a3e36ef2fc327e +checksum=f8897cfd85fe1e7c6a0d8b9ce9fdafe1cb878112e30467663713c9eb9652528c From ecc50178bece5a46232888c7fb451e02e0a2a68b Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:45 +0200 Subject: [PATCH 032/189] oxygen: update to 5.27.7. --- srcpkgs/oxygen/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/oxygen/template b/srcpkgs/oxygen/template index a1f2b850c247b..db955b2997c87 100644 --- a/srcpkgs/oxygen/template +++ b/srcpkgs/oxygen/template @@ -1,6 +1,6 @@ # Template file for 'oxygen' pkgname=oxygen -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,4 +13,4 @@ maintainer="John " license="LGPL-2.1-or-later, GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/oxygen" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=a9063912e238fcd113f719c01d100028545373d1b7881b147fcc92f910dc0906 +checksum=a218fc2f2f7b297de56b75f413c5acab0398f8c4a7a043a1b99b99d15256398d From 9f3d56415297b66b37934465179aa18f3c383ed3 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:46 +0200 Subject: [PATCH 033/189] plasma-browser-integration: update to 5.27.7. --- srcpkgs/plasma-browser-integration/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-browser-integration/template b/srcpkgs/plasma-browser-integration/template index c6427418751eb..c7d583907be1f 100644 --- a/srcpkgs/plasma-browser-integration/template +++ b/srcpkgs/plasma-browser-integration/template @@ -1,6 +1,6 @@ # Template file for 'plasma-browser-integration' pkgname=plasma-browser-integration -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF @@ -14,4 +14,4 @@ maintainer="John " license="GPL-3.0-or-later" homepage="https://invent.kde.org/plasma/plasma-browser-integration" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=72f86d1ee1b6474921ed102439dabf4c3813c2ae3731496c222656b8ab69198a +checksum=3ee5b893a210f84849612c48c03c544b611800edbc1ed6ae5ca2100a69bb6030 From d0884f1c6425a18f39c8777d64d6df8846c46e30 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:49 +0200 Subject: [PATCH 034/189] plasma-desktop: update to 5.27.7. --- srcpkgs/plasma-desktop/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-desktop/template b/srcpkgs/plasma-desktop/template index c7740e305b6b7..b037782c2468f 100644 --- a/srcpkgs/plasma-desktop/template +++ b/srcpkgs/plasma-desktop/template @@ -1,6 +1,6 @@ # Template file for 'plasma-desktop' pkgname=plasma-desktop -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF @@ -20,6 +20,6 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.0-or-later, LGPL-2.1-or-later, GFDL-1.2-or-later" homepage="https://invent.kde.org/plasma/plasma-desktop" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=e2485ea25d695ba22c1f14957abe14af658741a5e788269543ab7ff33045a683 +checksum=229aa838869a05e351db5f2d81608c9dce216cfeb85f1fb7e7d575e8869353da replaces="user-manager>=0" python_version=3 From 9cff187d51234e46c70c52fb81bc381d97f86bdb Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:50 +0200 Subject: [PATCH 035/189] plasma-disks: update to 5.27.7. --- srcpkgs/plasma-disks/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-disks/template b/srcpkgs/plasma-disks/template index 4dffe8008ef78..c5fd5c7dd4282 100644 --- a/srcpkgs/plasma-disks/template +++ b/srcpkgs/plasma-disks/template @@ -1,6 +1,6 @@ # Template file for 'plasma-disks' pkgname=plasma-disks -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/plasma-disks" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=3cc04456b7c16c5bb78c0e89f9a864cc48ec6d571d4d85c9025f232c3a876427 +checksum=3ba9b69e269420f73fecf894e65061b36a75d197a29fca04e5b0069581d8924b From 1577abfe22d9c6600b263841c3418868689d4308 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:51 +0200 Subject: [PATCH 036/189] plasma-firewall: update to 5.27.7. --- srcpkgs/plasma-firewall/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-firewall/template b/srcpkgs/plasma-firewall/template index ab17632b74d4e..7afb06c8c48f3 100644 --- a/srcpkgs/plasma-firewall/template +++ b/srcpkgs/plasma-firewall/template @@ -1,6 +1,6 @@ # Template file for 'plasma-firewall' pkgname=plasma-firewall -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -12,4 +12,4 @@ maintainer="John " license="GPL-2.0-only OR GPL-3.0-only" homepage="https://invent.kde.org/network/plasma-firewall" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=c8623cdfed38cd886153c51a1f6bda4af6709d237ae70963806f182cd2f76cc9 +checksum=cdc6c3b422def13de2df5f5cad9f004efd3210a61aeaccafc2a633d8fc94b4d8 From fe3445991233c996effc4fb4a347d2e020a68d56 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:51 +0200 Subject: [PATCH 037/189] plasma-integration: update to 5.27.7. --- srcpkgs/plasma-integration/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-integration/template b/srcpkgs/plasma-integration/template index 7fda166d22aa1..985c10decdc45 100644 --- a/srcpkgs/plasma-integration/template +++ b/srcpkgs/plasma-integration/template @@ -1,6 +1,6 @@ # Template file for 'plasma-integration' pkgname=plasma-integration -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -14,4 +14,4 @@ maintainer="John " license="LGPL-2.0-or-later" homepage="https://invent.kde.org/plasma/plasma-integration" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=a5fd5df218788b44c0bb2a437db1cad11917d4ebe6acefd89abd3f72104d8dab +checksum=e3f266c60efb3d96f3a22782ba81b7c7071b010484ea717a169327c3f6641faa From ea92df5752da9e37ffb9192168e7e946d58ac552 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:52 +0200 Subject: [PATCH 038/189] plasma-nm: update to 5.27.7. --- srcpkgs/plasma-nm/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-nm/template b/srcpkgs/plasma-nm/template index 75e85a94a9ecb..ab7a00068aa2c 100644 --- a/srcpkgs/plasma-nm/template +++ b/srcpkgs/plasma-nm/template @@ -1,6 +1,6 @@ # Template file for 'plasma-nm' pkgname=plasma-nm -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -16,4 +16,4 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/plasma-nm" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=0a649ee81433340eb106889d06a3b6592b99dc41dab898f9dcd14312fb68d9c9 +checksum=488a34118e6070fab5005cf092d9332bbc6c415dab6aa8387e08560123653ff1 From d53f94a5100d787134323f6676f17ef14ef6715f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:53 +0200 Subject: [PATCH 039/189] plasma-pa: update to 5.27.7. --- srcpkgs/plasma-pa/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-pa/template b/srcpkgs/plasma-pa/template index 294f5605c0135..f4803ead60308 100644 --- a/srcpkgs/plasma-pa/template +++ b/srcpkgs/plasma-pa/template @@ -1,6 +1,6 @@ # Template file for 'plasma-pa' pkgname=plasma-pa -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -15,4 +15,4 @@ maintainer="John " license="LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/plasma-pa" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=4e7608ba32a47affe64bb77ec30bc3ed977a4ca7577399238dd3821df5856e4f +checksum=4c73fb72af73a5258fb7d384eea65084b76341ae9c55652a491e1163cb46e2ed From b77465f78cd2fc619fde359ce9542bd2ac60117c Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:54 +0200 Subject: [PATCH 040/189] plasma-sdk: update to 5.27.7. --- srcpkgs/plasma-sdk/template | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/srcpkgs/plasma-sdk/template b/srcpkgs/plasma-sdk/template index c9c0a5844f2b4..ea0a664b2c8fc 100644 --- a/srcpkgs/plasma-sdk/template +++ b/srcpkgs/plasma-sdk/template @@ -1,11 +1,11 @@ # Template file for 'plasma-sdk' pkgname=plasma-sdk -version=5.27.6.1 +version=5.27.7.1 revision=1 build_style=cmake -configure_args="-DBUILD_TESTING=OFF" -hostmakedepends="extra-cmake-modules qt5-qmake qt5-host-tools kcoreaddons - gettext" +configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" +hostmakedepends="extra-cmake-modules qt5-qmake qt5-host-tools + gettext kpackage-devel kconfig-devel kcoreaddons-devel plasma-framework" makedepends="plasma-framework-devel kdelibs4support-devel kdesignerplugin-devel kitemmodels-devel knewstuff-devel ktexteditor-devel kdoctools-devel" short_desc="Plasma development applications" @@ -13,9 +13,4 @@ maintainer="John " license="GPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/plasma-sdk" distfiles="${KDE_SITE}/plasma/${version%.*}/${pkgname}-${version}.tar.xz" -checksum=2e4b0e466fced4345ecbd9c3b208bd334793762b02ae18bc54904860a69dceaf - -if [ "$CROSS_BUILD" ]; then - hostmakedepends+=" kpackage-devel kconfig-devel kcoreaddons-devel plasma-framework" - configure_args+=" -DKF5_HOST_TOOLING=/usr/lib/cmake" -fi +checksum=d310a81eed68334886a7e7767bce9066c6ccb07087aa77d04b73acf41a5426a4 From 8bf9d93e56f65fd2ae44ac592ca23b47e2d5b406 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:54 +0200 Subject: [PATCH 041/189] plasma-systemmonitor: update to 5.27.7. --- srcpkgs/plasma-systemmonitor/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-systemmonitor/template b/srcpkgs/plasma-systemmonitor/template index bcfa7e9ad0707..b4f1fc50828fe 100644 --- a/srcpkgs/plasma-systemmonitor/template +++ b/srcpkgs/plasma-systemmonitor/template @@ -1,6 +1,6 @@ # Template file for 'plasma-systemmonitor' pkgname=plasma-systemmonitor -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake hostmakedepends="extra-cmake-modules gettext qt5-host-tools qt5-qmake @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-only OR GPL-3.0-only, LGPL-2.1-only OR LGPL-3.0-only" homepage="https://invent.kde.org/plasma/plasma-systemmonitor" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=796eb25f061f05cd4e59019cfe902cb61d53be60904bec69366b347c3cfb9c1d +checksum=14611b425b1817743acaf594005f16a6ae347b063182fec0ee1f8676589e28e3 From 1c76857c29740aafdef5af06c0dabfa5b7079287 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:55 +0200 Subject: [PATCH 042/189] plasma-thunderbolt: update to 5.27.7. --- srcpkgs/plasma-thunderbolt/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-thunderbolt/template b/srcpkgs/plasma-thunderbolt/template index 07d8ff6a90e64..b9255cb61337a 100644 --- a/srcpkgs/plasma-thunderbolt/template +++ b/srcpkgs/plasma-thunderbolt/template @@ -1,6 +1,6 @@ # Template file for 'plasma-thunderbolt' pkgname=plasma-thunderbolt -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -13,7 +13,7 @@ maintainer="John " license="GPL-3.0-or-later" homepage="https://invent.kde.org/plasma/plasma-thunderbolt" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=669fee26f59bb2c9122b9a9286a45f0808de42d47ed4b66382bf40ae925d6cc6 +checksum=d60ac7888f5b11e53573c41617588bbc5120bc23ac4377265c20a6ebd42df069 do_check() { : # Requires running dbus and bolt services From 8a46199a36af345ff644719287e69247c2fd0785 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:55:56 +0200 Subject: [PATCH 043/189] plasma-vault: update to 5.27.7. --- srcpkgs/plasma-vault/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-vault/template b/srcpkgs/plasma-vault/template index 340117f4ed115..ffb989d30fa58 100644 --- a/srcpkgs/plasma-vault/template +++ b/srcpkgs/plasma-vault/template @@ -1,6 +1,6 @@ # Template file for 'plasma-vault' pkgname=plasma-vault -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args=" -DKF5_HOST_TOOLING=/usr/lib/cmake @@ -14,4 +14,4 @@ maintainer="Giuseppe Fierro " license="GPL-2.0-or-later, LGPL-2.0-or-later, LGPL-2.1-or-later" homepage="https://github.com/KDE/plasma-vault" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=245f5f4dac9934c2491fc9369feacb4002d16bde8c4366114557de2b2a40aa73 +checksum=181aba6b37ee065f7354c5df2963db68eb01400da8531cda62a0acaa682eb5dc From c4adf6f914a6b295bea21ac5f203f2d69f59d348 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:10 +0200 Subject: [PATCH 044/189] plasma-workspace-wallpapers: update to 5.27.7. --- srcpkgs/plasma-workspace-wallpapers/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/plasma-workspace-wallpapers/template b/srcpkgs/plasma-workspace-wallpapers/template index 1fedd14d10934..ef1a1ea34771e 100644 --- a/srcpkgs/plasma-workspace-wallpapers/template +++ b/srcpkgs/plasma-workspace-wallpapers/template @@ -1,6 +1,6 @@ # Template file for 'plasma-workspace-wallpapers' pkgname=plasma-workspace-wallpapers -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -10,4 +10,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/plasma-workspace-wallpapers" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=1303557516376eac7759c7aff796f2815a65e6874ecdd260118c66a061df1b05 +checksum=dec571ce370ea344a70d82f16af82e8197c8afc098c0e7d47fbe8d5b6b0538a0 From 50c414e224228356b7927e8c20afe846f65e6567 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:14 +0200 Subject: [PATCH 045/189] plasma-workspace: update to 5.27.7. --- srcpkgs/plasma-workspace/template | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/srcpkgs/plasma-workspace/template b/srcpkgs/plasma-workspace/template index 9033ad55ac17e..4b7bc217f7b83 100644 --- a/srcpkgs/plasma-workspace/template +++ b/srcpkgs/plasma-workspace/template @@ -1,7 +1,7 @@ # Template file for 'plasma-workspace' pkgname=plasma-workspace -version=5.27.6 -revision=2 +version=5.27.7 +revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DWaylandScanner_EXECUTABLE=/usr/bin/wayland-scanner @@ -23,7 +23,7 @@ maintainer="John " license="GPL-2.0-or-later, GFDL-1.2-or-later, LGPL-2.1-or-later" homepage="https://invent.kde.org/plasma/plasma-workspace" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=1ce6f70f7bb909b9ed9c213bc5528a4e7c264f570a9c94f2f4fb25c1528f8883 +checksum=0642941dcdf513ac201494897e2c5097a2f2db8be6dcdb597cae1a43d82ece5f build_options="pipewire" build_options_default="pipewire" From 707d5b751fa9229100d87192c82cf6a0cde2e5ac Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:14 +0200 Subject: [PATCH 046/189] polkit-kde-agent: update to 5.27.7. --- srcpkgs/polkit-kde-agent/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/polkit-kde-agent/template b/srcpkgs/polkit-kde-agent/template index 6d0641de9dbe3..58917e5003433 100644 --- a/srcpkgs/polkit-kde-agent/template +++ b/srcpkgs/polkit-kde-agent/template @@ -1,6 +1,6 @@ # Template file for 'polkit-kde-agent' pkgname=polkit-kde-agent -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -12,4 +12,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://commits.kde.org/polkit-kde-agent" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-1-${version}.tar.xz" -checksum=df737ae267ffab5abe460624c325daad176882ac1a4fd5df81e4ba44be4ced4c +checksum=8c4906f13f0a8b31423f6e2eb42163fea3a9517adec518b3f165d99acab6cf5c From 5e3b4531ff616c6c60996d55876ed24aeaed9ce7 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:15 +0200 Subject: [PATCH 047/189] powerdevil: update to 5.27.7. --- srcpkgs/powerdevil/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/powerdevil/template b/srcpkgs/powerdevil/template index e1c6ad4f3de9f..8b22710652ff0 100644 --- a/srcpkgs/powerdevil/template +++ b/srcpkgs/powerdevil/template @@ -1,6 +1,6 @@ # Template file for 'powerdevil' pkgname=powerdevil -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/powerdevil" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=6b230fabf2738455e3dfc3ab15e70b942ec827dc3080434774c6cb19d3217fb5 +checksum=c08084238b8e2225dcaf36226e69476e7ce0d427597708e598720c59dc853894 From 1c16d336bb219f2062feead6a799eba75abc74cf Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:16 +0200 Subject: [PATCH 048/189] sddm-kcm: update to 5.27.7. --- srcpkgs/sddm-kcm/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/sddm-kcm/template b/srcpkgs/sddm-kcm/template index b09bc794b21f1..865dada9a4411 100644 --- a/srcpkgs/sddm-kcm/template +++ b/srcpkgs/sddm-kcm/template @@ -1,6 +1,6 @@ # Template file for 'sddm-kcm' pkgname=sddm-kcm -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF -DKF5_HOST_TOOLING=/usr/lib/cmake" @@ -14,4 +14,4 @@ maintainer="John " license="GPL-2.0-or-later" homepage="https://invent.kde.org/plasma/sddm-kcm" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=dc70ab178f6954a6aaf7862440a64742c0c600c48f454462e97e09a1ddd6b5e2 +checksum=0645f5511c99cd2f01963cf0e01ccfe248bbca33daf349c729f0fe0ca3103c43 From d29fc3051ebcf27b4a5cf49ac6223f86e941120f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:17 +0200 Subject: [PATCH 049/189] systemsettings: update to 5.27.7. --- srcpkgs/systemsettings/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/systemsettings/template b/srcpkgs/systemsettings/template index c4d9dc209e26b..a4c174e2bba8b 100644 --- a/srcpkgs/systemsettings/template +++ b/srcpkgs/systemsettings/template @@ -1,6 +1,6 @@ # Template file for 'systemsettings' pkgname=systemsettings -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DBUILD_TESTING=OFF" @@ -14,4 +14,4 @@ maintainer="John " license="GPL-2.0-or-later, GFDL-1.2-only" homepage="https://invent.kde.org/plasma/systemsettings" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=bc2c471f1e13e9d063b616552bdc0d831c430338f3e3b32bbb3c0418956e789d +checksum=7c1dda144c7bcd6468331895a37df19d352cc84732a3d60bd62741a6c9aa6c6e From 7dfb339307422901399a013a169af77b95ca0b13 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 1 Aug 2023 14:56:17 +0200 Subject: [PATCH 050/189] xdg-desktop-portal-kde: update to 5.27.7. --- srcpkgs/xdg-desktop-portal-kde/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/xdg-desktop-portal-kde/template b/srcpkgs/xdg-desktop-portal-kde/template index 94cc75f56e13e..9c640c9528de0 100644 --- a/srcpkgs/xdg-desktop-portal-kde/template +++ b/srcpkgs/xdg-desktop-portal-kde/template @@ -1,6 +1,6 @@ # Template file for 'xdg-desktop-portal-kde' pkgname=xdg-desktop-portal-kde -version=5.27.6 +version=5.27.7 revision=1 build_style=cmake configure_args="-DWaylandScanner_EXECUTABLE=/usr/bin/wayland-scanner" @@ -13,4 +13,4 @@ maintainer="John " license="GPL-3.0-or-later" homepage="https://phabricator.kde.org/source/xdg-desktop-portal-kde/" distfiles="${KDE_SITE}/plasma/${version}/${pkgname}-${version}.tar.xz" -checksum=aed5e49660a47c86f26df67bf80ac3e55d2ce9bf2a3e676bfaa905516810f773 +checksum=ccdbf9bad6465de934c4dc30a6fb4d4376872caf0014b91c3749e27140fe08cd From 8f004e60f8a8fb93e5564070066bf92f34c4bd0f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 27 Jun 2023 12:02:59 +0200 Subject: [PATCH 051/189] astroid: rebuild against protobuf-23.3_1 --- srcpkgs/astroid/patches/protobuf-23.patch | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 srcpkgs/astroid/patches/protobuf-23.patch diff --git a/srcpkgs/astroid/patches/protobuf-23.patch b/srcpkgs/astroid/patches/protobuf-23.patch new file mode 100644 index 0000000000000..00a8e7442fdb3 --- /dev/null +++ b/srcpkgs/astroid/patches/protobuf-23.patch @@ -0,0 +1,14 @@ +diff --git a/CMakeLists.txt b/CMakeLists.txt +index 6eb00cf..10296e8 100644 +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -117,7 +117,9 @@ find_package ( Boost REQUIRED + system + ) + ++find_package (Protobuf CONFIG REQUIRED) + find_package (Protobuf 3.0 REQUIRED) ++set (PROTOBUF_LIBRARIES protobuf::libprotobuf) + set (PROTO_FILES + src/modes/thread_view/webextension/messages.proto + ) From 5fe7693f69d68c11eefdc3e4b9f968a6425cb2e6 Mon Sep 17 00:00:00 2001 From: John Date: Mon, 3 Apr 2023 19:37:44 +0200 Subject: [PATCH 053/189] qt6-webengine: update to 6.5.0. --- .../0108-chromium-cursed^Uscoped_file.patch | 18 ------------------ 1 file changed, 18 deletions(-) delete mode 100644 srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch diff --git a/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch b/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch deleted file mode 100644 index dd31da9790adc..0000000000000 --- a/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- qt6-webengine-6.4.2.orig/src/3rdparty/chromium/base/files/scoped_file_linux.cc -+++ qt6-webengine-6.4.2/src/3rdparty/chromium/base/files/scoped_file_linux.cc -@@ -77,15 +77,3 @@ bool IsFDOwned(int fd) { - } - - } // namespace base -- --extern "C" { -- --int __close(int); -- --__attribute__((visibility("default"), noinline)) int close(int fd) { -- if (base::IsFDOwned(fd) && g_is_ownership_enforced) -- CrashOnFdOwnershipViolation(); -- return __close(fd); --} -- --} // extern "C" From 1c5e70129b6c00649c733acd01f1b64c8a6eddb3 Mon Sep 17 00:00:00 2001 From: Marcin Puc Date: Thu, 5 Jan 2023 15:11:06 +0100 Subject: [PATCH 054/189] SPIRV-LLVM-Translator: update to 15.0.0 --- common/shlibs | 1 + 1 file changed, 1 insertion(+) diff --git a/common/shlibs b/common/shlibs index 144eac95bae58..ec408d357e5b1 100644 --- a/common/shlibs +++ b/common/shlibs @@ -997,6 +997,7 @@ libclang.so.15 libclang-15.0.7_1 libclang-cpp.so.15 libclang-cpp-15.0.7_1 libLLVM-11.so libllvm11-11.0.0_1 libLLVM-12.so libllvm12-12.0.0_1 +libLLVMSPIRVLib.so.15 SPIRV-LLVM-Translator-15.0.0_1 libLLVM-15.so libllvm15-15.0.7_1 libLLVMSPIRVLib.so.15 SPIRV-LLVM-Translator-15.0.0_1 libomp.so.5 libomp-15.0.7_1 From 65a9adab2141702de0ed65b8226bb3a6f3726f0a Mon Sep 17 00:00:00 2001 From: Duncaen Date: Wed, 15 Feb 2023 16:49:11 +0100 Subject: [PATCH 055/189] icu: update to 72.1. --- srcpkgs/icu/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/icu/template b/srcpkgs/icu/template index 271f7ea4fc944..4b2e7856448e6 100644 --- a/srcpkgs/icu/template +++ b/srcpkgs/icu/template @@ -11,7 +11,7 @@ configure_args="--with-data-packaging=archive --enable-static" hostmakedepends="pkg-config" checkdepends="diffutils python3" short_desc="Robust and fully-featured Unicode libraries" -maintainer="Randy McCaskill " +maintainer="Duncaen " license="ICU" homepage="https://home.unicode.org/" distfiles="https://github.com/unicode-org/icu/releases/download/release-${version//./-}/icu4c-${version//./_}-src.tgz" From e0e4a45bc03cca04d78f04cc3a84d3367a893c79 Mon Sep 17 00:00:00 2001 From: Duncaen Date: Wed, 15 Feb 2023 15:24:25 +0100 Subject: [PATCH 056/189] firefox: add riscv64 patches --- srcpkgs/firefox/patches/ppc32-fix-build.patch | 36 ------------ .../patches/riscv64-reduce-debug.patch | 23 ++++++++ srcpkgs/firefox/patches/sqlite-ppc.patch | 55 ------------------- srcpkgs/firefox/template | 9 ++- 4 files changed, 31 insertions(+), 92 deletions(-) delete mode 100644 srcpkgs/firefox/patches/ppc32-fix-build.patch create mode 100644 srcpkgs/firefox/patches/riscv64-reduce-debug.patch delete mode 100644 srcpkgs/firefox/patches/sqlite-ppc.patch diff --git a/srcpkgs/firefox/patches/ppc32-fix-build.patch b/srcpkgs/firefox/patches/ppc32-fix-build.patch deleted file mode 100644 index b26a46cfe835a..0000000000000 --- a/srcpkgs/firefox/patches/ppc32-fix-build.patch +++ /dev/null @@ -1,36 +0,0 @@ -This is not a complete/correct patch, but it makes firefox build. For now -mostly for tracking, so a real fix can be made, but right now it still -segfaults on start. - -Ref: https://hg.mozilla.org/mozilla-central/rev/08339a56f3ae -Ref: https://hg.mozilla.org/mozilla-central/rev/d16fcad6aa60 -Ref: https://hg.mozilla.org/mozilla-central/rev/ab87611d012e -Ref: https://hg.mozilla.org/mozilla-central/file/tip/xpcom/reflect/xptcall/md/unix/xptcinvoke_ppc_linux.cpp - ---- a/xpcom/reflect/xptcall/xptcall.h -+++ b/xpcom/reflect/xptcall/xptcall.h -@@ -71,6 +71,11 @@ struct nsXPTCVariant { - ExtendedVal ext; - }; - -+#if defined(__powerpc__) && !defined(__powerpc64__) -+ // this field is still necessary on ppc32, as an address -+ // to it is taken certain places in xptcall -+ void *ptr; -+#endif - nsXPTType type; - uint8_t flags; - -@@ -91,7 +96,12 @@ struct nsXPTCVariant { - }; - - void ClearFlags() { flags = 0; } -+#if defined(__powerpc__) && !defined(__powerpc64__) -+ void SetIndirect() { ptr = &val; flags |= IS_INDIRECT; } -+ bool IsPtrData() const { return IsIndirect(); } -+#else - void SetIndirect() { flags |= IS_INDIRECT; } -+#endif - - bool IsIndirect() const { return 0 != (flags & IS_INDIRECT); } - diff --git a/srcpkgs/firefox/patches/riscv64-reduce-debug.patch b/srcpkgs/firefox/patches/riscv64-reduce-debug.patch new file mode 100644 index 0000000000000..e1f780d73a4f7 --- /dev/null +++ b/srcpkgs/firefox/patches/riscv64-reduce-debug.patch @@ -0,0 +1,23 @@ +commit 29ff842dfe33d172d115a90ab69cc240426dad04 +Author: q66 +Date: Tue Oct 4 10:45:28 2022 +0200 + + reduce debug_info on riscv + +diff --git a/build/moz.configure/rust.configure b/build/moz.configure/rust.configure +index e64dc5d..e3e1fbd 100644 +--- a/build/moz.configure/rust.configure ++++ b/build/moz.configure/rust.configure +@@ -653,7 +653,11 @@ def rust_compile_flags( + debug_assertions = False + + if debug_symbols: +- debug_info = "2" ++ # linking fails with full debug info on riscv ++ if target.cpu == "riscv64": ++ debug_info = "1" ++ else: ++ debug_info = "2" + + opts = [] + diff --git a/srcpkgs/firefox/patches/sqlite-ppc.patch b/srcpkgs/firefox/patches/sqlite-ppc.patch deleted file mode 100644 index 51f7faa618dda..0000000000000 --- a/srcpkgs/firefox/patches/sqlite-ppc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 67157b1aa7da0a146b7d2d5abb9237eea1f434ec Mon Sep 17 00:00:00 2001 -From: Daniel Kolesa -Date: Fri, 23 Sep 2022 02:38:29 +0200 -Subject: [PATCH] fix sqlite3 on ppc with clang - -The __ppc__ macro is always defined on clang but not gcc, which -results in sqlite mistakenly thinking that ppc64le with clang -is big endian. - -Also disable some inline assembly stuff on ppc that is never used -with gcc and probably was never tested with modern machines. ---- - third_party/sqlite3/src/sqlite3.c | 10 +++++----- - 1 file changed, 5 insertions(+), 5 deletions(-) - -diff --git a/third_party/sqlite3/src/sqlite3.c b/third_party/sqlite3/src/sqlite3.c -index 4f3dc68..9017062 100644 ---- a/third_party/sqlite3/src/sqlite3.c -+++ b/third_party/sqlite3/src/sqlite3.c -@@ -14317,9 +14317,9 @@ typedef INT16_TYPE LogEst; - # if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) -+ defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) || defined(__LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 --# elif defined(sparc) || defined(__ppc__) || \ -+# elif defined(sparc) || defined(__BIG_ENDIAN__) || \ - defined(__ARMEB__) || defined(__AARCH64EB__) - # define SQLITE_BYTEORDER 4321 - # else -@@ -20713,7 +20713,7 @@ SQLITE_PRIVATE const char **sqlite3CompileOptions(int *pnOpt); - return val; - } - --#elif !defined(__STRICT_ANSI__) && (defined(__GNUC__) && defined(__ppc__)) -+#elif 0 - - __inline__ sqlite_uint64 sqlite3Hwtime(void){ - unsigned long long retval; -@@ -196385,9 +196385,9 @@ struct RtreeMatchArg { - #if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__arm__) -+ defined(__arm__) || defined(__LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 --#elif defined(sparc) || defined(__ppc__) -+#elif defined(sparc) || defined(__BIG_ENDIAN__) - # define SQLITE_BYTEORDER 4321 - #else - # define SQLITE_BYTEORDER 0 /* 0 means "unknown at compile-time" */ --- -2.37.3 - diff --git a/srcpkgs/firefox/template b/srcpkgs/firefox/template index 2b6f276b9addc..c62214d2ec47d 100644 --- a/srcpkgs/firefox/template +++ b/srcpkgs/firefox/template @@ -61,6 +61,8 @@ post_extract() { post_patch() { : # _clear_vendor_checksums num-traits + _clear_vendor_checksums nix + _clear_vendor_checksums bindgen } do_build() { @@ -156,12 +158,17 @@ do_build() { fi } + case "$XBPS_TARGET_MACHINE" in + riscv64*) _linker=bfd;; + *) _linker=$(vopt_if clang lld bfd);; + esac + cat <<-! >.mozconfig ac_add_options --prefix=/usr ac_add_options --libdir=/usr/lib ac_add_options --host=${XBPS_TRIPLET} ac_add_options --target=${XBPS_CROSS_TRIPLET:-${XBPS_TRIPLET}} - ac_add_options --enable-linker=$(vopt_if clang lld bfd) + ac_add_options --enable-linker=$_linker $(vopt_if lto 'ac_add_options --enable-lto=cross') $(vopt_if clang 'ac_add_options --with-libclang-path=/usr/lib') From 76c0af1fd9d4b4758bc94d95abb9bb555359c487 Mon Sep 17 00:00:00 2001 From: Marcin Puc Date: Sun, 18 Dec 2022 12:20:08 +0100 Subject: [PATCH 057/189] llvm12: remove bumped subpackages --- srcpkgs/llvm12/template | 3 --- 1 file changed, 3 deletions(-) diff --git a/srcpkgs/llvm12/template b/srcpkgs/llvm12/template index 86e86bb96c63f..1f998f5b9c4ae 100644 --- a/srcpkgs/llvm12/template +++ b/srcpkgs/llvm12/template @@ -108,10 +108,7 @@ pre_configure() { CXXFLAGS="$BUILD_CXXFLAGS" LDFLAGS="$BUILD_LDFLAGS" \ cmake ../.. -DCMAKE_BUILD_TYPE=Release make ${makejobs} -C utils/TableGen - make ${makejobs} -C tools/clang/utils/TableGen - [ "$_lldb_enable" = "yes" ] && make ${makejobs} -C tools/lldb/utils/TableGen configure_args+=" -DLLVM_TABLEGEN=${wrksrc}/llvm/build/HOST/bin/llvm-tblgen" - configure_args+=" -DCLANG_TABLEGEN=${wrksrc}/llvm/build/HOST/bin/clang-tblgen" cd ../.. fi From bdb7e4dbfca90e9824e873fc684f41556ed017ef Mon Sep 17 00:00:00 2001 From: Marcin Puc Date: Sun, 18 Dec 2022 00:40:18 +0100 Subject: [PATCH 058/189] llvm: update to 15 --- common/shlibs | 3 +++ 1 file changed, 3 insertions(+) diff --git a/common/shlibs b/common/shlibs index ec408d357e5b1..338e5f132503c 100644 --- a/common/shlibs +++ b/common/shlibs @@ -995,6 +995,9 @@ libconfuse.so.2 confuse-3.2.1_1 liblldb.so.15 lldb-15.0.7_1 libclang.so.15 libclang-15.0.7_1 libclang-cpp.so.15 libclang-cpp-15.0.7_1 +liblldb.so.15 lldb-15.0.6_1 +libclang.so.15 libclang-15.0.6_1 +libclang-cpp.so.15 libclang-cpp-15.0.6_1 libLLVM-11.so libllvm11-11.0.0_1 libLLVM-12.so libllvm12-12.0.0_1 libLLVMSPIRVLib.so.15 SPIRV-LLVM-Translator-15.0.0_1 From 3d2f1991659d273386866ed16778f3eb97c1ebd5 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Thu, 18 Jul 2019 12:23:44 +0200 Subject: [PATCH 059/189] kernel-libc-headers: add riscv. --- srcpkgs/kernel-libc-headers/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/kernel-libc-headers/template b/srcpkgs/kernel-libc-headers/template index 61d118a2cfdf1..9e2fc50ed3294 100644 --- a/srcpkgs/kernel-libc-headers/template +++ b/srcpkgs/kernel-libc-headers/template @@ -20,6 +20,7 @@ case "$XBPS_TARGET_MACHINE" in aarch64*) _arch="arm64";; mips*) _arch="mips";; ppc*) _arch="powerpc";; + riscv*) _arch="riscv";; *) msg_error "$pkgname: unknown architecture.\n";; esac From bb466ed43f045fc9485ac376cc8b614cbdf2fe4d Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Wed, 17 Jul 2019 17:06:00 +0200 Subject: [PATCH 060/189] pcre: disable JIT on riscv --- srcpkgs/pcre/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/pcre/template b/srcpkgs/pcre/template index 3f29793d9dc37..6834aa777bf67 100644 --- a/srcpkgs/pcre/template +++ b/srcpkgs/pcre/template @@ -16,6 +16,7 @@ checksum=4dae6fdcd2bb0bb6c37b5f97c33c2be954da743985369cddac3546e3218bffb8 case "$XBPS_TARGET_MACHINE" in mips*) ;; # Without stack for recursion the mips builds fail + riscv*) configure_args+=" --disable-jit" ;; *) configure_args+=" --disable-stack-for-recursion" ;; esac From d5251648cc63320ed8c8eb58d10a1a97f0ba88bc Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Thu, 18 Jul 2019 11:30:41 +0200 Subject: [PATCH 061/189] gdb: disable gdbserver on riscv (nyi) --- srcpkgs/gdb/template | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/srcpkgs/gdb/template b/srcpkgs/gdb/template index 0712062a82dc6..3bf9b59ec3ccd 100644 --- a/srcpkgs/gdb/template +++ b/srcpkgs/gdb/template @@ -43,7 +43,9 @@ build_options="debuginfod gdbserver guile multiarch python static" desc_option_gdbserver="Enable support for building GDB server" desc_option_debuginfod="Enable support for libdebuginfod" desc_option_multiarch="Enable support for all architectures" -build_options_default="debuginfod gdbserver python" +case "$XBPS_TARGET_MACHINE" in + *) build_options_default="debuginfod gdbserver python";; +esac vopt_conflict gdbserver static vopt_conflict debuginfod static From 5251c30920071daf49373bb02c2b9fb762f558c5 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Thu, 18 Jul 2019 14:28:48 +0200 Subject: [PATCH 062/189] pcre2: disable JIT on riscv --- srcpkgs/pcre2/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/pcre2/template b/srcpkgs/pcre2/template index 24677648eb602..bdea7048e9ea1 100644 --- a/srcpkgs/pcre2/template +++ b/srcpkgs/pcre2/template @@ -15,6 +15,10 @@ changelog="https://raw.githubusercontent.com/PCRE2Project/pcre2/master/NEWS" distfiles="https://github.com/PhilipHazel/pcre2/releases/download/pcre2-${version}/pcre2-${version}.tar.bz2" checksum=8d36cd8cb6ea2a4c2bb358ff6411b0c788633a2a45dabbf1aeb4b701d1b5e840 +case "$XBPS_TARGET_MACHINE" in + riscv*) configure_args+=" --disable-jit" ;; +esac + post_install() { vlicense LICENCE } From 8a3c6c4a58e6b16f4db3ccf349ffdbe48907e4e2 Mon Sep 17 00:00:00 2001 From: John Date: Thu, 12 Jan 2023 21:54:49 +0100 Subject: [PATCH 063/189] openssl: add riscv64 arch --- srcpkgs/openssl/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/openssl/template b/srcpkgs/openssl/template index fe6ac906c6495..2bcede50be165 100644 --- a/srcpkgs/openssl/template +++ b/srcpkgs/openssl/template @@ -43,6 +43,7 @@ case $XBPS_TARGET_MACHINE in ppc*) configure_args+=" linux-ppc";; arm*) configure_args+=" linux-armv4";; mips*) configure_args+=" linux-mips32 -mips32";; + riscv64*) configure_args+=" linux64-riscv64";; *) broken="$XBPS_TARGET_MACHINE";; esac From 8038eb9fb21d5e933b1b4e0d6a51d1cae179c682 Mon Sep 17 00:00:00 2001 From: John Date: Thu, 12 Jan 2023 22:09:15 +0100 Subject: [PATCH 064/189] musl: update to 1.2.3. --- ...ist_unlink_in_pthread_exit_after_all.patch | 56 ----- ...hreads_minus_1_as_relaxed_atomic_for.patch | 78 ------- ...own_size_of_some_libc_struct_members.patch | 30 --- ...pping_for_processes_that_return_to_s.patch | 102 -------- ...88a9da5e7b2925dda17a2d6820dddf1fb287.patch | 139 ----------- ...098a885feae3ae8c32b407350d8ca85dd178.patch | 113 --------- srcpkgs/musl/patches/CVE-2020-28928.patch | 64 ----- srcpkgs/musl/patches/aarch64-fregs.patch | 37 --- srcpkgs/musl/patches/add-qsort_r.patch | 201 ---------------- ...d-support-for-SIGEV_THREAD_ID-timers.patch | 74 ------ ...rlimit-misbehavior-and-hang-in-vfork.patch | 49 ---- srcpkgs/musl/patches/epoll_cp.patch | 28 --- .../musl/patches/fix-pi-mutex-cond-1.patch | 56 ----- .../musl/patches/fix-pi-mutex-cond-2.patch | 48 ---- .../musl/patches/fix-pi-mutex-cond-3.patch | 28 --- srcpkgs/musl/patches/gettid.patch | 49 ---- ...tly_instead_of_using_procfs_readlink.patch | 219 ------------------ srcpkgs/musl/patches/isascii.patch | 21 -- srcpkgs/musl/patches/mo_lookup.patch | 19 -- srcpkgs/musl/patches/ppc-pt_regs.patch | 38 --- srcpkgs/musl/patches/ppc64-fpregset_t.patch | 31 --- srcpkgs/musl/patches/ppcle.patch | 24 -- ...in_readlink_syscall_with_zero_buffer.patch | 59 ----- srcpkgs/musl/template | 11 +- 24 files changed, 5 insertions(+), 1569 deletions(-) delete mode 100644 srcpkgs/musl/patches/0001_reorder_thread_list_unlink_in_pthread_exit_after_all.patch delete mode 100644 srcpkgs/musl/patches/0002_don_t_use_libc_threads_minus_1_as_relaxed_atomic_for.patch delete mode 100644 srcpkgs/musl/patches/0003_cut_down_size_of_some_libc_struct_members.patch delete mode 100644 srcpkgs/musl/patches/0004_restore_lock_skipping_for_processes_that_return_to_s.patch delete mode 100644 srcpkgs/musl/patches/98e688a9da5e7b2925dda17a2d6820dddf1fb287.patch delete mode 100644 srcpkgs/musl/patches/99d5098a885feae3ae8c32b407350d8ca85dd178.patch delete mode 100644 srcpkgs/musl/patches/CVE-2020-28928.patch delete mode 100644 srcpkgs/musl/patches/aarch64-fregs.patch delete mode 100644 srcpkgs/musl/patches/add-qsort_r.patch delete mode 100644 srcpkgs/musl/patches/add-support-for-SIGEV_THREAD_ID-timers.patch delete mode 100644 srcpkgs/musl/patches/avoid-set-id-setrlimit-misbehavior-and-hang-in-vfork.patch delete mode 100644 srcpkgs/musl/patches/epoll_cp.patch delete mode 100644 srcpkgs/musl/patches/fix-pi-mutex-cond-1.patch delete mode 100644 srcpkgs/musl/patches/fix-pi-mutex-cond-2.patch delete mode 100644 srcpkgs/musl/patches/fix-pi-mutex-cond-3.patch delete mode 100644 srcpkgs/musl/patches/gettid.patch delete mode 100644 srcpkgs/musl/patches/implement_realpath_directly_instead_of_using_procfs_readlink.patch delete mode 100644 srcpkgs/musl/patches/isascii.patch delete mode 100644 srcpkgs/musl/patches/mo_lookup.patch delete mode 100644 srcpkgs/musl/patches/ppc-pt_regs.patch delete mode 100644 srcpkgs/musl/patches/ppc64-fpregset_t.patch delete mode 100644 srcpkgs/musl/patches/ppcle.patch delete mode 100644 srcpkgs/musl/patches/work_around_linux_bug_in_readlink_syscall_with_zero_buffer.patch diff --git a/srcpkgs/musl/patches/0001_reorder_thread_list_unlink_in_pthread_exit_after_all.patch b/srcpkgs/musl/patches/0001_reorder_thread_list_unlink_in_pthread_exit_after_all.patch deleted file mode 100644 index 7c1a55bc85e30..0000000000000 --- a/srcpkgs/musl/patches/0001_reorder_thread_list_unlink_in_pthread_exit_after_all.patch +++ /dev/null @@ -1,56 +0,0 @@ ->From 4d5aa20a94a2d3fae3e69289dc23ecafbd0c16c4 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Fri, 22 May 2020 17:35:14 -0400 -Subject: [PATCH 1/4] reorder thread list unlink in pthread_exit after all - locks - -since the backend for LOCK() skips locking if single-threaded, it's -unsafe to make the process appear single-threaded before the last use -of lock. - -this fixes potential unsynchronized access to a linked list via -__dl_thread_cleanup. ---- - src/thread/pthread_create.c | 19 +++++++++++-------- - 1 file changed, 11 insertions(+), 8 deletions(-) - -diff --git a/src/thread/pthread_create.c b/src/thread/pthread_create.c -index 5f491092..6a3b0c21 100644 ---- a/src/thread/pthread_create.c -+++ b/src/thread/pthread_create.c -@@ -90,14 +90,7 @@ _Noreturn void __pthread_exit(void *result) - exit(0); - } - -- /* At this point we are committed to thread termination. Unlink -- * the thread from the list. This change will not be visible -- * until the lock is released, which only happens after SYS_exit -- * has been called, via the exit futex address pointing at the lock. */ -- libc.threads_minus_1--; -- self->next->prev = self->prev; -- self->prev->next = self->next; -- self->prev = self->next = self; -+ /* At this point we are committed to thread termination. */ - - /* Process robust list in userspace to handle non-pshared mutexes - * and the detached thread case where the robust list head will -@@ -121,6 +114,16 @@ _Noreturn void __pthread_exit(void *result) - __do_orphaned_stdio_locks(); - __dl_thread_cleanup(); - -+ /* Last, unlink thread from the list. This change will not be visible -+ * until the lock is released, which only happens after SYS_exit -+ * has been called, via the exit futex address pointing at the lock. -+ * This needs to happen after any possible calls to LOCK() that might -+ * skip locking if libc.threads_minus_1 is zero. */ -+ libc.threads_minus_1--; -+ self->next->prev = self->prev; -+ self->prev->next = self->next; -+ self->prev = self->next = self; -+ - /* This atomic potentially competes with a concurrent pthread_detach - * call; the loser is responsible for freeing thread resources. */ - int state = a_cas(&self->detach_state, DT_JOINABLE, DT_EXITING); --- -2.21.0 - diff --git a/srcpkgs/musl/patches/0002_don_t_use_libc_threads_minus_1_as_relaxed_atomic_for.patch b/srcpkgs/musl/patches/0002_don_t_use_libc_threads_minus_1_as_relaxed_atomic_for.patch deleted file mode 100644 index e060762e99a62..0000000000000 --- a/srcpkgs/musl/patches/0002_don_t_use_libc_threads_minus_1_as_relaxed_atomic_for.patch +++ /dev/null @@ -1,78 +0,0 @@ ->From e01b5939b38aea5ecbe41670643199825874b26c Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Thu, 21 May 2020 23:32:45 -0400 -Subject: [PATCH 2/4] don't use libc.threads_minus_1 as relaxed atomic for - skipping locks - -after all but the last thread exits, the next thread to observe -libc.threads_minus_1==0 and conclude that it can skip locking fails to -synchronize with any changes to memory that were made by the -last-exiting thread. this can produce data races. - -on some archs, at least x86, memory synchronization is unlikely to be -a problem; however, with the inline locks in malloc, skipping the lock -also eliminated the compiler barrier, and caused code that needed to -re-check chunk in-use bits after obtaining the lock to reuse a stale -value, possibly from before the process became single-threaded. this -in turn produced corruption of the heap state. - -some uses of libc.threads_minus_1 remain, especially for allocation of -new TLS in the dynamic linker; otherwise, it could be removed -entirely. it's made non-volatile to reflect that the remaining -accesses are only made under lock on the thread list. - -instead of libc.threads_minus_1, libc.threaded is now used for -skipping locks. the difference is that libc.threaded is permanently -true once an additional thread has been created. this will produce -some performance regression in processes that are mostly -single-threaded but occasionally creating threads. in the future it -may be possible to bring back the full lock-skipping, but more care -needs to be taken to produce a safe design. ---- - src/internal/libc.h | 2 +- - src/malloc/malloc.c | 2 +- - src/thread/__lock.c | 2 +- - 3 files changed, 3 insertions(+), 3 deletions(-) - -diff --git a/src/internal/libc.h b/src/internal/libc.h -index ac97dc7e..c0614852 100644 ---- a/src/internal/libc.h -+++ b/src/internal/libc.h -@@ -21,7 +21,7 @@ struct __libc { - int can_do_threads; - int threaded; - int secure; -- volatile int threads_minus_1; -+ int threads_minus_1; - size_t *auxv; - struct tls_module *tls_head; - size_t tls_size, tls_align, tls_cnt; -diff --git a/src/malloc/malloc.c b/src/malloc/malloc.c -index 96982596..2553a62e 100644 ---- a/src/malloc/malloc.c -+++ b/src/malloc/malloc.c -@@ -26,7 +26,7 @@ int __malloc_replaced; - - static inline void lock(volatile int *lk) - { -- if (libc.threads_minus_1) -+ if (libc.threaded) - while(a_swap(lk, 1)) __wait(lk, lk+1, 1, 1); - } - -diff --git a/src/thread/__lock.c b/src/thread/__lock.c -index 45557c88..5b9b144e 100644 ---- a/src/thread/__lock.c -+++ b/src/thread/__lock.c -@@ -18,7 +18,7 @@ - - void __lock(volatile int *l) - { -- if (!libc.threads_minus_1) return; -+ if (!libc.threaded) return; - /* fast path: INT_MIN for the lock, +1 for the congestion */ - int current = a_cas(l, 0, INT_MIN + 1); - if (!current) return; --- -2.21.0 - diff --git a/srcpkgs/musl/patches/0003_cut_down_size_of_some_libc_struct_members.patch b/srcpkgs/musl/patches/0003_cut_down_size_of_some_libc_struct_members.patch deleted file mode 100644 index 540c5d9501957..0000000000000 --- a/srcpkgs/musl/patches/0003_cut_down_size_of_some_libc_struct_members.patch +++ /dev/null @@ -1,30 +0,0 @@ ->From f12888e9eb9eed60cc266b899dcafecb4752964a Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Fri, 22 May 2020 17:25:38 -0400 -Subject: [PATCH 3/4] cut down size of some libc struct members - -these are all flags that can be single-byte values. ---- - src/internal/libc.h | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/src/internal/libc.h b/src/internal/libc.h -index c0614852..d47f58e0 100644 ---- a/src/internal/libc.h -+++ b/src/internal/libc.h -@@ -18,9 +18,9 @@ struct tls_module { - }; - - struct __libc { -- int can_do_threads; -- int threaded; -- int secure; -+ char can_do_threads; -+ char threaded; -+ char secure; - int threads_minus_1; - size_t *auxv; - struct tls_module *tls_head; --- -2.21.0 - diff --git a/srcpkgs/musl/patches/0004_restore_lock_skipping_for_processes_that_return_to_s.patch b/srcpkgs/musl/patches/0004_restore_lock_skipping_for_processes_that_return_to_s.patch deleted file mode 100644 index e703c1f403c59..0000000000000 --- a/srcpkgs/musl/patches/0004_restore_lock_skipping_for_processes_that_return_to_s.patch +++ /dev/null @@ -1,102 +0,0 @@ ->From 8d81ba8c0bc6fe31136cb15c9c82ef4c24965040 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Fri, 22 May 2020 17:45:47 -0400 -Subject: [PATCH 4/4] restore lock-skipping for processes that return to - single-threaded state - -the design used here relies on the barrier provided by the first lock -operation after the process returns to single-threaded state to -synchronize with actions by the last thread that exited. by storing -the intent to change modes in the same object used to detect whether -locking is needed, it's possible to avoid an extra (possibly costly) -memory load after the lock is taken. ---- - src/internal/libc.h | 1 + - src/malloc/malloc.c | 5 ++++- - src/thread/__lock.c | 4 +++- - src/thread/pthread_create.c | 8 ++++---- - 4 files changed, 12 insertions(+), 6 deletions(-) - -diff --git a/src/internal/libc.h b/src/internal/libc.h -index d47f58e0..619bba86 100644 ---- a/src/internal/libc.h -+++ b/src/internal/libc.h -@@ -21,6 +21,7 @@ struct __libc { - char can_do_threads; - char threaded; - char secure; -+ volatile signed char need_locks; - int threads_minus_1; - size_t *auxv; - struct tls_module *tls_head; -diff --git a/src/malloc/malloc.c b/src/malloc/malloc.c -index 2553a62e..a803d4c9 100644 ---- a/src/malloc/malloc.c -+++ b/src/malloc/malloc.c -@@ -26,8 +26,11 @@ int __malloc_replaced; - - static inline void lock(volatile int *lk) - { -- if (libc.threaded) -+ int need_locks = libc.need_locks; -+ if (need_locks) { - while(a_swap(lk, 1)) __wait(lk, lk+1, 1, 1); -+ if (need_locks < 0) libc.need_locks = 0; -+ } - } - - static inline void unlock(volatile int *lk) -diff --git a/src/thread/__lock.c b/src/thread/__lock.c -index 5b9b144e..60eece49 100644 ---- a/src/thread/__lock.c -+++ b/src/thread/__lock.c -@@ -18,9 +18,11 @@ - - void __lock(volatile int *l) - { -- if (!libc.threaded) return; -+ int need_locks = libc.need_locks; -+ if (!need_locks) return; - /* fast path: INT_MIN for the lock, +1 for the congestion */ - int current = a_cas(l, 0, INT_MIN + 1); -+ if (need_locks < 0) libc.need_locks = 0; - if (!current) return; - /* A first spin loop, for medium congestion. */ - for (unsigned i = 0; i < 10; ++i) { -diff --git a/src/thread/pthread_create.c b/src/thread/pthread_create.c -index 6a3b0c21..6bdfb44f 100644 ---- a/src/thread/pthread_create.c -+++ b/src/thread/pthread_create.c -@@ -118,8 +118,8 @@ _Noreturn void __pthread_exit(void *result) - * until the lock is released, which only happens after SYS_exit - * has been called, via the exit futex address pointing at the lock. - * This needs to happen after any possible calls to LOCK() that might -- * skip locking if libc.threads_minus_1 is zero. */ -- libc.threads_minus_1--; -+ * skip locking if process appears single-threaded. */ -+ if (!--libc.threads_minus_1) libc.need_locks = -1; - self->next->prev = self->prev; - self->prev->next = self->next; - self->prev = self->next = self; -@@ -339,7 +339,7 @@ int __pthread_create(pthread_t *restrict res, const pthread_attr_t *restrict att - ~(1UL<<((SIGCANCEL-1)%(8*sizeof(long)))); - - __tl_lock(); -- libc.threads_minus_1++; -+ if (!libc.threads_minus_1++) libc.need_locks = 1; - ret = __clone((c11 ? start_c11 : start), stack, flags, args, &new->tid, TP_ADJ(new), &__thread_list_lock); - - /* All clone failures translate to EAGAIN. If explicit scheduling -@@ -363,7 +363,7 @@ int __pthread_create(pthread_t *restrict res, const pthread_attr_t *restrict att - new->next->prev = new; - new->prev->next = new; - } else { -- libc.threads_minus_1--; -+ if (!--libc.threads_minus_1) libc.need_locks = 0; - } - __tl_unlock(); - __restore_sigs(&set); --- -2.21.0 - - diff --git a/srcpkgs/musl/patches/98e688a9da5e7b2925dda17a2d6820dddf1fb287.patch b/srcpkgs/musl/patches/98e688a9da5e7b2925dda17a2d6820dddf1fb287.patch deleted file mode 100644 index a8bfa66d6c47d..0000000000000 --- a/srcpkgs/musl/patches/98e688a9da5e7b2925dda17a2d6820dddf1fb287.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 98e688a9da5e7b2925dda17a2d6820dddf1fb287 Mon Sep 17 00:00:00 2001 -From: Ismael Luceno -Date: Sun, 15 Aug 2021 17:51:57 +0200 -Subject: [PATCH] define NULL as nullptr when used in C++11 or later - -This should be safer for casting and more compatible with existing code -bases that wrongly assume it must be defined as a pointer. ---- - include/locale.h | 4 +++- - include/stddef.h | 4 +++- - include/stdio.h | 4 +++- - include/stdlib.h | 4 +++- - include/string.h | 4 +++- - include/time.h | 4 +++- - include/unistd.h | 4 +++- - include/wchar.h | 4 +++- - 8 files changed, 24 insertions(+), 8 deletions(-) - -diff --git a/include/locale.h b/include/locale.h -index ce384381c..11106fea8 100644 ---- a/include/locale.h -+++ b/include/locale.h -@@ -7,7 +7,9 @@ extern "C" { - - #include - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/stddef.h b/include/stddef.h -index bd7538535..f25b86396 100644 ---- a/include/stddef.h -+++ b/include/stddef.h -@@ -1,7 +1,9 @@ - #ifndef _STDDEF_H - #define _STDDEF_H - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/stdio.h b/include/stdio.h -index 3604198c3..d1ed01f03 100644 ---- a/include/stdio.h -+++ b/include/stdio.h -@@ -25,7 +25,9 @@ extern "C" { - - #include - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/stdlib.h b/include/stdlib.h -index 7af86e3bc..b507ca33b 100644 ---- a/include/stdlib.h -+++ b/include/stdlib.h -@@ -7,7 +7,9 @@ extern "C" { - - #include - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/string.h b/include/string.h -index 795a2abcd..43ad0942e 100644 ---- a/include/string.h -+++ b/include/string.h -@@ -7,7 +7,9 @@ extern "C" { - - #include - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/time.h b/include/time.h -index 5494df183..3d9483720 100644 ---- a/include/time.h -+++ b/include/time.h -@@ -7,7 +7,9 @@ extern "C" { - - #include - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/unistd.h b/include/unistd.h -index 130640260..ee2dbe8af 100644 ---- a/include/unistd.h -+++ b/include/unistd.h -@@ -15,7 +15,9 @@ extern "C" { - #define SEEK_CUR 1 - #define SEEK_END 2 - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) -diff --git a/include/wchar.h b/include/wchar.h -index 88eb55b18..ed5d774df 100644 ---- a/include/wchar.h -+++ b/include/wchar.h -@@ -38,7 +38,9 @@ extern "C" { - #define WCHAR_MIN (-1-0x7fffffff+L'\0') - #endif - --#ifdef __cplusplus -+#if __cplusplus >= 201103L -+#define NULL nullptr -+#elif defined(__cplusplus) - #define NULL 0L - #else - #define NULL ((void*)0) - diff --git a/srcpkgs/musl/patches/99d5098a885feae3ae8c32b407350d8ca85dd178.patch b/srcpkgs/musl/patches/99d5098a885feae3ae8c32b407350d8ca85dd178.patch deleted file mode 100644 index 4e03ad1607ce9..0000000000000 --- a/srcpkgs/musl/patches/99d5098a885feae3ae8c32b407350d8ca85dd178.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 99d5098a885feae3ae8c32b407350d8ca85dd178 Mon Sep 17 00:00:00 2001 -From: Julien Ramseier -Date: Sun, 18 Oct 2020 12:15:06 -0400 -Subject: update crypt_blowfish to support $2b$ prefix - -Merge changes from Solar Designer's crypt_blowfish v1.3. This makes -crypt_blowfish fully compatible with OpenBSD's bcrypt by adding -support for the $2b$ prefix (which behaves the same as -crypt_blowfish's $2y$). ---- - src/crypt/crypt_blowfish.c | 38 +++++++++++++++++++++++--------------- - 1 file changed, 23 insertions(+), 15 deletions(-) - -(limited to 'src/crypt/crypt_blowfish.c') - -diff --git a/src/crypt/crypt_blowfish.c b/src/crypt/crypt_blowfish.c -index d3f79851..d722607b 100644 ---- a/src/crypt/crypt_blowfish.c -+++ b/src/crypt/crypt_blowfish.c -@@ -15,7 +15,7 @@ - * No copyright is claimed, and the software is hereby placed in the public - * domain. In case this attempt to disclaim copyright and place the software - * in the public domain is deemed null and void, then the software is -- * Copyright (c) 1998-2012 Solar Designer and it is hereby released to the -+ * Copyright (c) 1998-2014 Solar Designer and it is hereby released to the - * general public under the following terms: - * - * Redistribution and use in source and binary forms, with or without -@@ -31,12 +31,12 @@ - * you place this code and any modifications you make under a license - * of your choice. - * -- * This implementation is mostly compatible with OpenBSD's bcrypt.c (prefix -- * "$2a$") by Niels Provos , and uses some of his -- * ideas. The password hashing algorithm was designed by David Mazieres -- * . For more information on the level of compatibility, -- * please refer to the comments in BF_set_key() below and to the included -- * crypt(3) man page. -+ * This implementation is fully compatible with OpenBSD's bcrypt.c for prefix -+ * "$2b$", originally by Niels Provos , and it uses -+ * some of his ideas. The password hashing algorithm was designed by David -+ * Mazieres . For information on the level of -+ * compatibility for bcrypt hash prefixes other than "$2b$", please refer to -+ * the comments in BF_set_key() below and to the included crypt(3) man page. - * - * There's a paper on the algorithm that explains its design decisions: - * -@@ -533,6 +533,7 @@ static void BF_set_key(const char *key, BF_key expanded, BF_key initial, - * Valid combinations of settings are: - * - * Prefix "$2a$": bug = 0, safety = 0x10000 -+ * Prefix "$2b$": bug = 0, safety = 0 - * Prefix "$2x$": bug = 1, safety = 0 - * Prefix "$2y$": bug = 0, safety = 0 - */ -@@ -596,12 +597,14 @@ static void BF_set_key(const char *key, BF_key expanded, BF_key initial, - initial[0] ^= sign; - } - -+static const unsigned char flags_by_subtype[26] = { -+ 2, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0 -+}; -+ - static char *BF_crypt(const char *key, const char *setting, - char *output, BF_word min) - { -- static const unsigned char flags_by_subtype[26] = -- {2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0}; - struct { - BF_ctx ctx; - BF_key expanded_key; -@@ -746,9 +749,11 @@ char *__crypt_blowfish(const char *key, const char *setting, char *output) - { - const char *test_key = "8b \xd0\xc1\xd2\xcf\xcc\xd8"; - const char *test_setting = "$2a$00$abcdefghijklmnopqrstuu"; -- static const char test_hash[2][34] = -- {"VUrPmXD6q/nVSSp7pNDhCR9071IfIRe\0\x55", /* $2x$ */ -- "i1D709vfamulimlGcq0qq3UvuUasvEa\0\x55"}; /* $2a$, $2y$ */ -+ static const char test_hashes[2][34] = { -+ "i1D709vfamulimlGcq0qq3UvuUasvEa\0\x55", /* 'a', 'b', 'y' */ -+ "VUrPmXD6q/nVSSp7pNDhCR9071IfIRe\0\x55", /* 'x' */ -+ }; -+ const char *test_hash = test_hashes[0]; - char *retval; - const char *p; - int ok; -@@ -768,8 +773,11 @@ char *__crypt_blowfish(const char *key, const char *setting, char *output) - * detected by the self-test. - */ - memcpy(buf.s, test_setting, sizeof(buf.s)); -- if (retval) -+ if (retval) { -+ unsigned int flags = flags_by_subtype[setting[2] - 'a']; -+ test_hash = test_hashes[flags & 1]; - buf.s[2] = setting[2]; -+ } - memset(buf.o, 0x55, sizeof(buf.o)); - buf.o[sizeof(buf.o) - 1] = 0; - p = BF_crypt(test_key, buf.s, buf.o, 1); -@@ -777,7 +785,7 @@ char *__crypt_blowfish(const char *key, const char *setting, char *output) - ok = (p == buf.o && - !memcmp(p, buf.s, 7 + 22) && - !memcmp(p + (7 + 22), -- test_hash[buf.s[2] & 1], -+ test_hash, - 31 + 1 + 1 + 1)); - - { --- -cgit v1.2.1 - diff --git a/srcpkgs/musl/patches/CVE-2020-28928.patch b/srcpkgs/musl/patches/CVE-2020-28928.patch deleted file mode 100644 index b3ff3b4ee08f0..0000000000000 --- a/srcpkgs/musl/patches/CVE-2020-28928.patch +++ /dev/null @@ -1,64 +0,0 @@ ---- a/src/multibyte/wcsnrtombs.c -+++ b/src/multibyte/wcsnrtombs.c -@@ -1,41 +1,33 @@ - #include -+#include -+#include - - size_t wcsnrtombs(char *restrict dst, const wchar_t **restrict wcs, size_t wn, size_t n, mbstate_t *restrict st) - { -- size_t l, cnt=0, n2; -- char *s, buf[256]; - const wchar_t *ws = *wcs; -- const wchar_t *tmp_ws; -- -- if (!dst) s = buf, n = sizeof buf; -- else s = dst; -- -- while ( ws && n && ( (n2=wn)>=n || n2>32 ) ) { -- if (n2>=n) n2=n; -- tmp_ws = ws; -- l = wcsrtombs(s, &ws, n2, 0); -- if (!(l+1)) { -- cnt = l; -- n = 0; -+ size_t cnt = 0; -+ if (!dst) n=0; -+ while (ws && wn) { -+ char tmp[MB_LEN_MAX]; -+ size_t l = wcrtomb(nn) break; -+ memcpy(dst, tmp, l); -+ } -+ dst += l; - n -= l; - } -- wn = ws ? wn - (ws - tmp_ws) : 0; -- cnt += l; -- } -- if (ws) while (n && wn) { -- l = wcrtomb(s, *ws, 0); -- if ((l+1)<=1) { -- if (!l) ws = 0; -- else cnt = l; -+ if (!*ws) { -+ ws = 0; - break; - } -- ws++; wn--; -- /* safe - this loop runs fewer than sizeof(buf) times */ -- s+=l; n-=l; -+ ws++; -+ wn--; - cnt += l; - } - if (dst) *wcs = ws; - diff --git a/srcpkgs/musl/patches/aarch64-fregs.patch b/srcpkgs/musl/patches/aarch64-fregs.patch deleted file mode 100644 index 024eed11a8e53..0000000000000 --- a/srcpkgs/musl/patches/aarch64-fregs.patch +++ /dev/null @@ -1,37 +0,0 @@ -Use types compatible with glibc/kernel headers. - -diff --git a/arch/aarch64/bits/signal.h b/arch/aarch64/bits/signal.h -index b71261f5..5098c734 100644 ---- a/arch/aarch64/bits/signal.h -+++ b/arch/aarch64/bits/signal.h -@@ -11,7 +11,7 @@ typedef unsigned long greg_t; - typedef unsigned long gregset_t[34]; - - typedef struct { -- long double vregs[32]; -+ __uint128_t vregs[32]; - unsigned int fpsr; - unsigned int fpcr; - } fpregset_t; -@@ -34,7 +34,7 @@ struct fpsimd_context { - struct _aarch64_ctx head; - unsigned int fpsr; - unsigned int fpcr; -- long double vregs[32]; -+ __uint128_t vregs[32]; - }; - struct esr_context { - struct _aarch64_ctx head; -diff --git a/arch/aarch64/bits/user.h b/arch/aarch64/bits/user.h -index d12cdf7f..8a1002aa 100644 ---- a/arch/aarch64/bits/user.h -+++ b/arch/aarch64/bits/user.h -@@ -6,7 +6,7 @@ struct user_regs_struct { - }; - - struct user_fpsimd_struct { -- long double vregs[32]; -+ __uint128_t vregs[32]; - unsigned int fpsr; - unsigned int fpcr; - }; diff --git a/srcpkgs/musl/patches/add-qsort_r.patch b/srcpkgs/musl/patches/add-qsort_r.patch deleted file mode 100644 index 3d85496afb69f..0000000000000 --- a/srcpkgs/musl/patches/add-qsort_r.patch +++ /dev/null @@ -1,201 +0,0 @@ -From b76f37fd5625d038141b52184956fb4b7838e9a5 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=89rico=20Nogueira?= -Date: Tue, 9 Mar 2021 18:02:13 -0300 -Subject: [PATCH] add qsort_r and make qsort a wrapper around it - -we make qsort a wrapper by providing a wrapper_cmp function that uses -the extra argument as a function pointer. should be optimized to a tail -call on most architectures, as long as it's built with --fomit-frame-pointer, so the performance impact should be minimal. - -to keep the git history clean, for now qsort_r is implemented in qsort.c -and qsort is implemented in qsort_nr.c. qsort.c also received a few -trivial cleanups, including replacing (*cmp)() calls with cmp(). -qsort_nr.c contains only wrapper_cmp and qsort as a qsort_r wrapper -itself. ---- - include/stdlib.h | 1 + - src/include/stdlib.h | 1 + - src/stdlib/qsort.c | 37 ++++++++++++++++++++----------------- - src/stdlib/qsort_nr.c | 14 ++++++++++++++ - 4 files changed, 36 insertions(+), 17 deletions(-) - create mode 100644 src/stdlib/qsort_nr.c - -diff --git a/include/stdlib.h b/include/stdlib.h -index b54a051fe..7af86e3bc 100644 ---- a/include/stdlib.h -+++ b/include/stdlib.h -@@ -146,6 +146,7 @@ int clearenv(void); - #define WCOREDUMP(s) ((s) & 0x80) - #define WIFCONTINUED(s) ((s) == 0xffff) - void *reallocarray (void *, size_t, size_t); -+void qsort_r (void *, size_t, size_t, int (*)(const void *, const void *, void *), void *); - #endif - - #ifdef _GNU_SOURCE -diff --git a/src/include/stdlib.h b/src/include/stdlib.h -index e9da20158..812b04de2 100644 ---- a/src/include/stdlib.h -+++ b/src/include/stdlib.h -@@ -8,6 +8,7 @@ hidden void __env_rm_add(char *, char *); - hidden int __mkostemps(char *, int, int); - hidden int __ptsname_r(int, char *, size_t); - hidden char *__randname(char *); -+hidden void __qsort_r (void *, size_t, size_t, int (*)(const void *, const void *, void *), void *); - - hidden void *__libc_malloc(size_t); - hidden void *__libc_malloc_impl(size_t); -diff --git a/src/stdlib/qsort.c b/src/stdlib/qsort.c -index da58fd317..314ddc29d 100644 ---- a/src/stdlib/qsort.c -+++ b/src/stdlib/qsort.c -@@ -24,6 +24,7 @@ - /* Smoothsort, an adaptive variant of Heapsort. Memory usage: O(1). - Run time: Worst case O(n log n), close to O(n) in the mostly-sorted case. */ - -+#define _BSD_SOURCE - #include - #include - #include -@@ -31,7 +32,7 @@ - #include "atomic.h" - #define ntz(x) a_ctz_l((x)) - --typedef int (*cmpfun)(const void *, const void *); -+typedef int (*cmpfun)(const void *, const void *, void *); - - static inline int pntz(size_t p[2]) { - int r = ntz(p[0] - 1); -@@ -88,7 +89,7 @@ static inline void shr(size_t p[2], int n) - p[1] >>= n; - } - --static void sift(unsigned char *head, size_t width, cmpfun cmp, int pshift, size_t lp[]) -+static void sift(unsigned char *head, size_t width, cmpfun cmp, void *arg, int pshift, size_t lp[]) - { - unsigned char *rt, *lf; - unsigned char *ar[14 * sizeof(size_t) + 1]; -@@ -99,10 +100,10 @@ static void sift(unsigned char *head, size_t width, cmpfun cmp, int pshift, size - rt = head - width; - lf = head - width - lp[pshift - 2]; - -- if((*cmp)(ar[0], lf) >= 0 && (*cmp)(ar[0], rt) >= 0) { -+ if(cmp(ar[0], lf, arg) >= 0 && cmp(ar[0], rt, arg) >= 0) { - break; - } -- if((*cmp)(lf, rt) >= 0) { -+ if(cmp(lf, rt, arg) >= 0) { - ar[i++] = lf; - head = lf; - pshift -= 1; -@@ -115,7 +116,7 @@ static void sift(unsigned char *head, size_t width, cmpfun cmp, int pshift, size - cycle(width, ar, i); - } - --static void trinkle(unsigned char *head, size_t width, cmpfun cmp, size_t pp[2], int pshift, int trusty, size_t lp[]) -+static void trinkle(unsigned char *head, size_t width, cmpfun cmp, void *arg, size_t pp[2], int pshift, int trusty, size_t lp[]) - { - unsigned char *stepson, - *rt, *lf; -@@ -130,13 +131,13 @@ static void trinkle(unsigned char *head, size_t width, cmpfun cmp, size_t pp[2], - ar[0] = head; - while(p[0] != 1 || p[1] != 0) { - stepson = head - lp[pshift]; -- if((*cmp)(stepson, ar[0]) <= 0) { -+ if(cmp(stepson, ar[0], arg) <= 0) { - break; - } - if(!trusty && pshift > 1) { - rt = head - width; - lf = head - width - lp[pshift - 2]; -- if((*cmp)(rt, stepson) >= 0 || (*cmp)(lf, stepson) >= 0) { -+ if(cmp(rt, stepson, arg) >= 0 || cmp(lf, stepson, arg) >= 0) { - break; - } - } -@@ -150,11 +151,11 @@ static void trinkle(unsigned char *head, size_t width, cmpfun cmp, size_t pp[2], - } - if(!trusty) { - cycle(width, ar, i); -- sift(head, width, cmp, pshift, lp); -+ sift(head, width, cmp, arg, pshift, lp); - } - } - --void qsort(void *base, size_t nel, size_t width, cmpfun cmp) -+void __qsort_r(void *base, size_t nel, size_t width, cmpfun cmp, void *arg) - { - size_t lp[12*sizeof(size_t)]; - size_t i, size = width * nel; -@@ -173,16 +174,16 @@ void qsort(void *base, size_t nel, size_t width, cmpfun cmp) - - while(head < high) { - if((p[0] & 3) == 3) { -- sift(head, width, cmp, pshift, lp); -+ sift(head, width, cmp, arg, pshift, lp); - shr(p, 2); - pshift += 2; - } else { - if(lp[pshift - 1] >= high - head) { -- trinkle(head, width, cmp, p, pshift, 0, lp); -+ trinkle(head, width, cmp, arg, p, pshift, 0, lp); - } else { -- sift(head, width, cmp, pshift, lp); -+ sift(head, width, cmp, arg, pshift, lp); - } -- -+ - if(pshift == 1) { - shl(p, 1); - pshift = 0; -@@ -191,12 +192,12 @@ void qsort(void *base, size_t nel, size_t width, cmpfun cmp) - pshift = 1; - } - } -- -+ - p[0] |= 1; - head += width; - } - -- trinkle(head, width, cmp, p, pshift, 0, lp); -+ trinkle(head, width, cmp, arg, p, pshift, 0, lp); - - while(pshift != 1 || p[0] != 1 || p[1] != 0) { - if(pshift <= 1) { -@@ -208,11 +209,13 @@ void qsort(void *base, size_t nel, size_t width, cmpfun cmp) - pshift -= 2; - p[0] ^= 7; - shr(p, 1); -- trinkle(head - lp[pshift] - width, width, cmp, p, pshift + 1, 1, lp); -+ trinkle(head - lp[pshift] - width, width, cmp, arg, p, pshift + 1, 1, lp); - shl(p, 1); - p[0] |= 1; -- trinkle(head - width, width, cmp, p, pshift, 1, lp); -+ trinkle(head - width, width, cmp, arg, p, pshift, 1, lp); - } - head -= width; - } - } -+ -+weak_alias(__qsort_r, qsort_r); -diff --git a/src/stdlib/qsort_nr.c b/src/stdlib/qsort_nr.c -new file mode 100644 -index 000000000..efe7ccecd ---- /dev/null -+++ b/src/stdlib/qsort_nr.c -@@ -0,0 +1,14 @@ -+#define _BSD_SOURCE -+#include -+ -+typedef int (*cmpfun)(const void *, const void *); -+ -+static int wrapper_cmp(const void *v1, const void *v2, void *cmp) -+{ -+ return ((cmpfun)cmp)(v1, v2); -+} -+ -+void qsort(void *base, size_t nel, size_t width, cmpfun cmp) -+{ -+ __qsort_r(base, nel, width, wrapper_cmp, cmp); -+} diff --git a/srcpkgs/musl/patches/add-support-for-SIGEV_THREAD_ID-timers.patch b/srcpkgs/musl/patches/add-support-for-SIGEV_THREAD_ID-timers.patch deleted file mode 100644 index e20dff5ba0d45..0000000000000 --- a/srcpkgs/musl/patches/add-support-for-SIGEV_THREAD_ID-timers.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 7c71792e87691451f2a6b76348e83ad1889f1dcb Mon Sep 17 00:00:00 2001 -From: James Y Knight -Date: Sun, 30 Jun 2019 21:55:20 -0400 -Subject: [PATCH] add support for SIGEV_THREAD_ID timers - -This is like SIGEV_SIGNAL, but targeted to a particular thread's -tid, rather than the process. ---- - include/signal.h | 16 +++++++++++++--- - src/time/timer_create.c | 8 ++++++-- - 2 files changed, 19 insertions(+), 5 deletions(-) - -diff --git a/include/signal.h b/include/signal.h -index fbdf667b2..9ed929e4f 100644 ---- a/include/signal.h -+++ b/include/signal.h -@@ -180,14 +180,24 @@ struct sigevent { - union sigval sigev_value; - int sigev_signo; - int sigev_notify; -- void (*sigev_notify_function)(union sigval); -- pthread_attr_t *sigev_notify_attributes; -- char __pad[56-3*sizeof(long)]; -+ union { -+ char __pad[64 - 2*sizeof(int) - sizeof(union sigval)]; -+ pid_t sigev_notify_thread_id; -+ struct { -+ void (*sigev_notify_function)(union sigval); -+ pthread_attr_t *sigev_notify_attributes; -+ } __sev_thread; -+ } __sev_fields; - }; - -+#define sigev_notify_thread_id __sev_fields.sigev_notify_thread_id -+#define sigev_notify_function __sev_fields.__sev_thread.sigev_notify_function -+#define sigev_notify_attributes __sev_fields.__sev_thread.sigev_notify_attributes -+ - #define SIGEV_SIGNAL 0 - #define SIGEV_NONE 1 - #define SIGEV_THREAD 2 -+#define SIGEV_THREAD_ID 4 - - int __libc_current_sigrtmin(void); - int __libc_current_sigrtmax(void); -diff --git a/src/time/timer_create.c b/src/time/timer_create.c -index 5ddfda278..4bef23905 100644 ---- a/src/time/timer_create.c -+++ b/src/time/timer_create.c -@@ -71,11 +71,15 @@ int timer_create(clockid_t clk, struct sigevent *restrict evp, timer_t *restrict - switch (evp ? evp->sigev_notify : SIGEV_SIGNAL) { - case SIGEV_NONE: - case SIGEV_SIGNAL: -+ case SIGEV_THREAD_ID: - if (evp) { - ksev.sigev_value = evp->sigev_value; - ksev.sigev_signo = evp->sigev_signo; - ksev.sigev_notify = evp->sigev_notify; -- ksev.sigev_tid = 0; -+ if (evp->sigev_notify == SIGEV_THREAD_ID) -+ ksev.sigev_tid = evp->sigev_notify_thread_id; -+ else -+ ksev.sigev_tid = 0; - ksevp = &ksev; - } - if (syscall(SYS_timer_create, clk, ksevp, &timerid) < 0) -@@ -107,7 +111,7 @@ int timer_create(clockid_t clk, struct sigevent *restrict evp, timer_t *restrict - - ksev.sigev_value.sival_ptr = 0; - ksev.sigev_signo = SIGTIMER; -- ksev.sigev_notify = 4; /* SIGEV_THREAD_ID */ -+ ksev.sigev_notify = SIGEV_THREAD_ID; - ksev.sigev_tid = td->tid; - if (syscall(SYS_timer_create, clk, &ksev, &timerid) < 0) - timerid = -1; diff --git a/srcpkgs/musl/patches/avoid-set-id-setrlimit-misbehavior-and-hang-in-vfork.patch b/srcpkgs/musl/patches/avoid-set-id-setrlimit-misbehavior-and-hang-in-vfork.patch deleted file mode 100644 index 21f236b3a6cd1..0000000000000 --- a/srcpkgs/musl/patches/avoid-set-id-setrlimit-misbehavior-and-hang-in-vfork.patch +++ /dev/null @@ -1,49 +0,0 @@ -From a5aff1972c9e3981566414b09a28e331ccd2be5d Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Thu, 17 Sep 2020 15:09:46 -0400 -Subject: [PATCH 237/513] avoid set*id/setrlimit misbehavior and hang in - vforked/cloned child - -taking the deprecated/dropped vfork spec strictly, doing pretty much -anything but execve in the child is wrong and undefined. however, -these are commonly needed operations to setup the child state before -exec, and historical implementations tolerated them. - -for single-threaded parents, these operations already worked as -expected in the vforked child. however, due to the need for __synccall -to synchronize id/resource limit changes among all threads, calling -these functions in the vforked child of a multithreaded parent caused -a misdirected broadcast signaling of all threads in the parent. these -signals could kill the parent entirely if the synccall signal handler -had never been installed in the parent, or could be ignored if it had, -or could signal/kill one or more utterly wrong processes if the parent -already terminated (due to vfork semantics, only possible via fatal -signal) and the parent tids were recycled. in any case, the expected -number of semaphore posts would never happen, so the child would -permanently hang (with all signals blocked) waiting for them. - -to mitigate this, and also make the normal usage case work as -intended, treat the condition where the caller's actual tid does not -match the tid in its thread structure as single-threaded, and bypass -the entire synccall broadcast operation. ---- - src/thread/synccall.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/src/thread/synccall.c b/src/thread/synccall.c -index 648a6ad4..d58c851f 100644 ---- a/src/thread/synccall.c -+++ b/src/thread/synccall.c -@@ -63,7 +63,8 @@ void __synccall(void (*func)(void *), void *ctx) - sem_init(&target_sem, 0, 0); - sem_init(&caller_sem, 0, 0); - -- if (!libc.threads_minus_1) goto single_threaded; -+ if (!libc.threads_minus_1 || __syscall(SYS_gettid) != self->tid) -+ goto single_threaded; - - callback = func; - context = ctx; --- -2.41.0 - diff --git a/srcpkgs/musl/patches/epoll_cp.patch b/srcpkgs/musl/patches/epoll_cp.patch deleted file mode 100644 index 92f47551ad8eb..0000000000000 --- a/srcpkgs/musl/patches/epoll_cp.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 2c00f95c1ac7dd50f53d9e361847ebd2513c8da0 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Sat, 3 Apr 2021 21:16:41 -0400 -Subject: [PATCH] make epoll_[p]wait a cancellation point - -this is a Linux-specific function and not covered by POSIX's -requirements for which interfaces are cancellation points, but glibc -makes it one and existing software relies on it being one. - -at some point a review for similar functions that should be made -cancellation points should be done. - -diff --git src/linux/epoll.c src/linux/epoll.c -index deff5b10..93baa814 100644 ---- a/src/linux/epoll.c -+++ b/src/linux/epoll.c -@@ -24,9 +24,9 @@ int epoll_ctl(int fd, int op, int fd2, struct epoll_event *ev) - - int epoll_pwait(int fd, struct epoll_event *ev, int cnt, int to, const sigset_t *sigs) - { -- int r = __syscall(SYS_epoll_pwait, fd, ev, cnt, to, sigs, _NSIG/8); -+ int r = __syscall_cp(SYS_epoll_pwait, fd, ev, cnt, to, sigs, _NSIG/8); - #ifdef SYS_epoll_wait -- if (r==-ENOSYS && !sigs) r = __syscall(SYS_epoll_wait, fd, ev, cnt, to); -+ if (r==-ENOSYS && !sigs) r = __syscall_cp(SYS_epoll_wait, fd, ev, cnt, to); - #endif - return __syscall_ret(r); - } diff --git a/srcpkgs/musl/patches/fix-pi-mutex-cond-1.patch b/srcpkgs/musl/patches/fix-pi-mutex-cond-1.patch deleted file mode 100644 index 39af72b0c5f91..0000000000000 --- a/srcpkgs/musl/patches/fix-pi-mutex-cond-1.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 2d0bbe6c788938d1332609c014eeebc1dff966ac Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Mon, 26 Oct 2020 15:56:25 -0400 -Subject: fix pthread_cond_wait paired with with priority-inheritance mutex - -pthread_cond_wait arranged for requeued waiters to wake when the mutex -is unlocked by temporarily adjusting the mutex's waiter count. commit -54ca677983d47529bab8752315ac1a2b49888870 broke this when introducing -PI mutexes by repurposing the waiter count field of the mutex -structure. since then, for PI mutexes, the waiter count adjustment was -misinterpreted by the mutex locking code as indicating that the mutex -is non a non-recoverable state. - -it would be possible to special-case PI mutexes here, but instead just -drop all adjustment of the waiters count, and instead use the lock -word waiters bit for all mutex types. since the mutex is either held -by the caller or in unrecoverable state at the time the bit is set, it -will necessarily still be set at the time of any subsequent valid -unlock operation, and this will produce the desired effect of waking -the next waiter. - -if waiter counts are entirely dropped at some point in the future this -code should still work without modification. ---- - src/thread/pthread_cond_timedwait.c | 11 +++++------ - 1 file changed, 5 insertions(+), 6 deletions(-) - -(limited to 'src/thread/pthread_cond_timedwait.c') - -diff --git a/src/thread/pthread_cond_timedwait.c b/src/thread/pthread_cond_timedwait.c -index d1501240..f5f37af1 100644 ---- a/src/thread/pthread_cond_timedwait.c -+++ b/src/thread/pthread_cond_timedwait.c -@@ -146,14 +146,13 @@ relock: - - if (oldstate == WAITING) goto done; - -- if (!node.next) a_inc(&m->_m_waiters); -- - /* Unlock the barrier that's holding back the next waiter, and - * either wake it or requeue it to the mutex. */ -- if (node.prev) -- unlock_requeue(&node.prev->barrier, &m->_m_lock, m->_m_type & 128); -- else -- a_dec(&m->_m_waiters); -+ if (node.prev) { -+ int val = m->_m_lock; -+ if (val>0) a_cas(&m->_m_lock, val, val|0x80000000); -+ unlock_requeue(&node.prev->barrier, &m->_m_lock, m->_m_type & (8|128)); -+ } - - /* Since a signal was consumed, cancellation is not permitted. */ - if (e == ECANCELED) e = 0; --- -cgit v1.2.1 - diff --git a/srcpkgs/musl/patches/fix-pi-mutex-cond-2.patch b/srcpkgs/musl/patches/fix-pi-mutex-cond-2.patch deleted file mode 100644 index b356e38b61f83..0000000000000 --- a/srcpkgs/musl/patches/fix-pi-mutex-cond-2.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 27b2fc9d6db956359727a66c262f1e69995660aa Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Fri, 30 Oct 2020 11:21:06 -0400 -Subject: fix missing-wake regression in pthread_cond_wait - -the reasoning in commit 2d0bbe6c788938d1332609c014eeebc1dff966ac was -not entirely correct. while it's true that setting the waiters flag -ensures that the next unlock will perform a wake, it's possible that -the wake is consumed by a mutex waiter that has no relationship with -the condvar wait queue being processed, which then takes the mutex. -when that thread subsequently unlocks, it sees no waiters, and leaves -the rest of the condvar queue stuck. - -bring back the waiter count adjustment, but skip it for PI mutexes, -for which a successful lock-after-waiting always sets the waiters bit. -if future changes are made to bring this same waiters-bit contract to -all lock types, this can be reverted. ---- - src/thread/pthread_cond_timedwait.c | 5 +++++ - 1 file changed, 5 insertions(+) - -(limited to 'src/thread/pthread_cond_timedwait.c') - -diff --git a/src/thread/pthread_cond_timedwait.c b/src/thread/pthread_cond_timedwait.c -index f5f37af1..a0cd4904 100644 ---- a/src/thread/pthread_cond_timedwait.c -+++ b/src/thread/pthread_cond_timedwait.c -@@ -146,12 +146,17 @@ relock: - - if (oldstate == WAITING) goto done; - -+ if (!node.next && !(m->_m_type & 8)) -+ a_inc(&m->_m_waiters); -+ - /* Unlock the barrier that's holding back the next waiter, and - * either wake it or requeue it to the mutex. */ - if (node.prev) { - int val = m->_m_lock; - if (val>0) a_cas(&m->_m_lock, val, val|0x80000000); - unlock_requeue(&node.prev->barrier, &m->_m_lock, m->_m_type & (8|128)); -+ } else if (!!(m->_m_type & 8)) { -+ a_dec(&m->_m_waiters); - } - - /* Since a signal was consumed, cancellation is not permitted. */ --- -cgit v1.2.1 - diff --git a/srcpkgs/musl/patches/fix-pi-mutex-cond-3.patch b/srcpkgs/musl/patches/fix-pi-mutex-cond-3.patch deleted file mode 100644 index 2cc943f26f6a6..0000000000000 --- a/srcpkgs/musl/patches/fix-pi-mutex-cond-3.patch +++ /dev/null @@ -1,28 +0,0 @@ -From d91a6cf6e369a79587c5665fce9635e5634ca201 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Fri, 30 Oct 2020 16:50:08 -0400 -Subject: fix erroneous pthread_cond_wait mutex waiter count logic due to typo - -introduced in commit 27b2fc9d6db956359727a66c262f1e69995660aa. ---- - src/thread/pthread_cond_timedwait.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -(limited to 'src/thread/pthread_cond_timedwait.c') - -diff --git a/src/thread/pthread_cond_timedwait.c b/src/thread/pthread_cond_timedwait.c -index a0cd4904..6b761455 100644 ---- a/src/thread/pthread_cond_timedwait.c -+++ b/src/thread/pthread_cond_timedwait.c -@@ -155,7 +155,7 @@ relock: - int val = m->_m_lock; - if (val>0) a_cas(&m->_m_lock, val, val|0x80000000); - unlock_requeue(&node.prev->barrier, &m->_m_lock, m->_m_type & (8|128)); -- } else if (!!(m->_m_type & 8)) { -+ } else if (!(m->_m_type & 8)) { - a_dec(&m->_m_waiters); - } - --- -cgit v1.2.1 - diff --git a/srcpkgs/musl/patches/gettid.patch b/srcpkgs/musl/patches/gettid.patch deleted file mode 100644 index bb8bf5905b880..0000000000000 --- a/srcpkgs/musl/patches/gettid.patch +++ /dev/null @@ -1,49 +0,0 @@ -From d49cf07541bb54a5ac7aec1feec8514db33db8ea Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Mon, 17 Aug 2020 20:12:53 -0400 -Subject: [PATCH] add gettid function - -this is a prerequisite for addition of other interfaces that use -kernel tids, including futex and SIGEV_THREAD_ID. - -there is some ambiguity as to whether the semantic return type should -be int or pid_t. either way, futex API imposes a contract that the -values fit in int (excluding some upper reserved bits). glibc used -pid_t, so in the interest of not having gratuitous mismatch (the -underlying types are the same anyway), pid_t is used here as well. - -while conceptually this is a syscall, the copy stored in the thread -structure is always valid in all contexts where it's valid to call -libc functions, so it's used to avoid the syscall. ---- - include/unistd.h | 1 + - src/linux/gettid.c | 8 ++++++++ - 2 files changed, 9 insertions(+) - create mode 100644 src/linux/gettid.c - -diff --git a/include/unistd.h b/include/unistd.h -index 7bcbff943..07584a23e 100644 ---- a/include/unistd.h -+++ b/include/unistd.h -@@ -190,6 +190,7 @@ int syncfs(int); - int euidaccess(const char *, int); - int eaccess(const char *, int); - ssize_t copy_file_range(int, off_t *, int, off_t *, size_t, unsigned); -+pid_t gettid(void); - #endif - - #if defined(_LARGEFILE64_SOURCE) || defined(_GNU_SOURCE) -diff --git a/src/linux/gettid.c b/src/linux/gettid.c -new file mode 100644 -index 000000000..70767137e ---- /dev/null -+++ b/src/linux/gettid.c -@@ -0,0 +1,8 @@ -+#define _GNU_SOURCE -+#include -+#include "pthread_impl.h" -+ -+pid_t gettid(void) -+{ -+ return __pthread_self()->tid; -+} diff --git a/srcpkgs/musl/patches/implement_realpath_directly_instead_of_using_procfs_readlink.patch b/srcpkgs/musl/patches/implement_realpath_directly_instead_of_using_procfs_readlink.patch deleted file mode 100644 index 569a1f52c7cd9..0000000000000 --- a/srcpkgs/musl/patches/implement_realpath_directly_instead_of_using_procfs_readlink.patch +++ /dev/null @@ -1,219 +0,0 @@ -From 29ff7599a448232f2527841c2362643d246cee36 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Mon, 30 Nov 2020 12:14:47 -0500 -Subject: [PATCH] implement realpath directly instead of using procfs readlink - -inability to use realpath in chroot/container without procfs access -and at early boot prior to mount of /proc has been an ongoing issue, -and it turns out realpath was one of the last remaining interfaces -that needed procfs for its core functionality. during investigation -while reimplementing, it was determined that there were also serious -problems with the procfs-based implementation. most seriously it was -unsafe on pre-O_PATH kernels, and unlike other places where O_PATH was -used, the unsafety was hard or impossible to fix because O_NOFOLLOW -can't be used (since the whole purpose was to follow symlinks). - -the new implementation is a direct one, performing readlink on each -path component to resolve it. an explicit stack, as opposed to -recursion, is used to represent the remaining components to be -processed. the stack starts out holding just the input string, and -reading a link pushes the link contents onto the stack. - -unlike many other implementations, this one does not call getcwd -initially for relative pathnames. instead it accumulates initial .. -components to be applied to the working directory if the result is -still a relative path. this avoids calling getcwd (which may fail) at -all when symlink traversal will eventually yield an absolute path. it -also doesn't use any form of stat operation; instead it arranges for -readlink to tell it when a non-directory is used in a context where a -directory is needed. this minimizes the number of syscalls needed, -avoids accessing inodes when the directory table suffices, and reduces -the amount of code pulled in for static linking. ---- - src/misc/realpath.c | 159 +++++++++++++++++++++++++++++++++++++------- - 1 file changed, 136 insertions(+), 23 deletions(-) - -diff --git a/src/misc/realpath.c b/src/misc/realpath.c -index d2708e59d..db8b74dc8 100644 ---- a/src/misc/realpath.c -+++ b/src/misc/realpath.c -@@ -1,43 +1,156 @@ - #include - #include --#include --#include - #include - #include - #include --#include "syscall.h" -+ -+static size_t slash_len(const char *s) -+{ -+ const char *s0 = s; -+ while (*s == '/') s++; -+ return s-s0; -+} - - char *realpath(const char *restrict filename, char *restrict resolved) - { -- int fd; -- ssize_t r; -- struct stat st1, st2; -- char buf[15+3*sizeof(int)]; -- char tmp[PATH_MAX]; -+ char stack[PATH_MAX+1]; -+ char output[PATH_MAX]; -+ size_t p, q, l, l0, cnt=0, nup=0; -+ int check_dir=0; - - if (!filename) { - errno = EINVAL; - return 0; - } -+ l = strnlen(filename, sizeof stack); -+ if (!l) { -+ errno = ENOENT; -+ return 0; -+ } -+ if (l >= PATH_MAX) goto toolong; -+ p = sizeof stack - l - 1; -+ q = 0; -+ memcpy(stack+p, filename, l+1); -+ -+ /* Main loop. Each iteration pops the next part from stack of -+ * remaining path components and consumes any slashes that follow. -+ * If not a link, it's moved to output; if a link, contents are -+ * pushed to the stack. */ -+restart: -+ for (; ; p+=slash_len(stack+p)) { -+ /* If stack starts with /, the whole component is / or // -+ * and the output state must be reset. */ -+ if (stack[p] == '/') { -+ check_dir=0; -+ nup=0; -+ q=0; -+ output[q++] = '/'; -+ p++; -+ /* Initial // is special. */ -+ if (stack[p] == '/' && stack[p+1] != '/') -+ output[q++] = '/'; -+ continue; -+ } -+ -+ char *z = __strchrnul(stack+p, '/'); -+ l0 = l = z-(stack+p); - -- fd = sys_open(filename, O_PATH|O_NONBLOCK|O_CLOEXEC); -- if (fd < 0) return 0; -- __procfdname(buf, fd); -+ if (!l && !check_dir) break; - -- r = readlink(buf, tmp, sizeof tmp - 1); -- if (r < 0) goto err; -- tmp[r] = 0; -+ /* Skip any . component but preserve check_dir status. */ -+ if (l==1 && stack[p]=='.') { -+ p += l; -+ continue; -+ } - -- fstat(fd, &st1); -- r = stat(tmp, &st2); -- if (r<0 || st1.st_dev != st2.st_dev || st1.st_ino != st2.st_ino) { -- if (!r) errno = ELOOP; -- goto err; -+ /* Copy next component onto output at least temporarily, to -+ * call readlink, but wait to advance output position until -+ * determining it's not a link. */ -+ if (q && output[q-1] != '/') { -+ if (!p) goto toolong; -+ stack[--p] = '/'; -+ l++; -+ } -+ if (q+l >= PATH_MAX) goto toolong; -+ memcpy(output+q, stack+p, l); -+ output[q+l] = 0; -+ p += l; -+ -+ int up = 0; -+ if (l0==2 && stack[p-2]=='.' && stack[p-1]=='.') { -+ up = 1; -+ /* Any non-.. path components we could cancel start -+ * after nup repetitions of the 3-byte string "../"; -+ * if there are none, accumulate .. components to -+ * later apply to cwd, if needed. */ -+ if (q <= 3*nup) { -+ nup++; -+ q += l; -+ continue; -+ } -+ /* When previous components are already known to be -+ * directories, processing .. can skip readlink. */ -+ if (!check_dir) goto skip_readlink; -+ } -+ ssize_t k = readlink(output, stack, p); -+ if (k==p) goto toolong; -+ if (!k) { -+ errno = ENOENT; -+ return 0; -+ } -+ if (k<0) { -+ if (errno != EINVAL) return 0; -+skip_readlink: -+ check_dir = 0; -+ if (up) { -+ while(q && output[q-1]!='/') q--; -+ if (q>1 && (q>2 || output[0]!='/')) q--; -+ continue; -+ } -+ if (l0) q += l; -+ check_dir = stack[p]; -+ continue; -+ } -+ if (++cnt == SYMLOOP_MAX) { -+ errno = ELOOP; -+ return 0; -+ } -+ -+ /* If link contents end in /, strip any slashes already on -+ * stack to avoid /->// or //->/// or spurious toolong. */ -+ if (stack[k-1]=='/') while (stack[p]=='/') p++; -+ p -= k; -+ memmove(stack+p, stack, k); -+ -+ /* Skip the stack advancement in case we have a new -+ * absolute base path. */ -+ goto restart; - } - -- __syscall(SYS_close, fd); -- return resolved ? strcpy(resolved, tmp) : strdup(tmp); --err: -- __syscall(SYS_close, fd); -+ output[q] = 0; -+ -+ if (output[0] != '/') { -+ if (!getcwd(stack, sizeof stack)) return 0; -+ l = strlen(stack); -+ /* Cancel any initial .. components. */ -+ p = 0; -+ while (nup--) { -+ while(l>1 && stack[l-1]!='/') l--; -+ if (l>1) l--; -+ p += 2; -+ if (p= PATH_MAX) goto toolong; -+ memmove(output + l, output + p, q - p + 1); -+ memcpy(output, stack, l); -+ q = l + q-p; -+ } -+ -+ if (resolved) return memcpy(resolved, output, q+1); -+ else return strdup(output); -+ -+toolong: -+ errno = ENAMETOOLONG; - return 0; - } diff --git a/srcpkgs/musl/patches/isascii.patch b/srcpkgs/musl/patches/isascii.patch deleted file mode 100644 index 6719d2ee188fa..0000000000000 --- a/srcpkgs/musl/patches/isascii.patch +++ /dev/null @@ -1,21 +0,0 @@ -From e48e99c112246fb580596404074445cb25d7858d Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C3=89rico=20Rolim?= -Date: Mon, 4 Jan 2021 22:48:34 -0300 -Subject: [PATCH] suppress isascii() macro for C++ - -analogous to commit a60457c84a4b59ab564d7f4abb660a70283ba98d. - -diff --git include/ctype.h include/ctype.h -index 7936536f..32bcef4d 100644 ---- a/include/ctype.h -+++ b/include/ctype.h -@@ -64,7 +64,9 @@ int isascii(int); - int toascii(int); - #define _tolower(a) ((a)|0x20) - #define _toupper(a) ((a)&0x5f) -+#ifndef __cplusplus - #define isascii(a) (0 ? isascii(a) : (unsigned)(a) < 128) -+#endif - - #endif - diff --git a/srcpkgs/musl/patches/mo_lookup.patch b/srcpkgs/musl/patches/mo_lookup.patch deleted file mode 100644 index ae86e33c9c700..0000000000000 --- a/srcpkgs/musl/patches/mo_lookup.patch +++ /dev/null @@ -1,19 +0,0 @@ -Do not crash with a NULL pointer dereference when dcngettext() -is called with NULL msgid[12] arguments. - -Fix for https://github.com/void-linux/void-packages/issues/12042 -and probably others. - - --xtraeme - ---- a/src/locale/__mo_lookup.c.orig 2019-06-26 09:55:36.843012674 +0200 -+++ b/src/locale/__mo_lookup.c 2019-06-26 09:56:11.529443955 +0200 -@@ -13,7 +13,7 @@ const char *__mo_lookup(const void *p, s - uint32_t b = 0, n = swapc(mo[2], sw); - uint32_t o = swapc(mo[3], sw); - uint32_t t = swapc(mo[4], sw); -- if (n>=size/4 || o>=size-4*n || t>=size-4*n || ((o|t)%4)) -+ if (!s || n>=size/4 || o>=size-4*n || t>=size-4*n || ((o|t)%4)) - return 0; - o/=4; - t/=4; diff --git a/srcpkgs/musl/patches/ppc-pt_regs.patch b/srcpkgs/musl/patches/ppc-pt_regs.patch deleted file mode 100644 index 45815321bf0f1..0000000000000 --- a/srcpkgs/musl/patches/ppc-pt_regs.patch +++ /dev/null @@ -1,38 +0,0 @@ -commit c2518a8efb6507f1b41c3b12e03b06f8f2317a1f -Author: Rich Felker -Date: Sat Oct 19 15:53:43 2019 -0400 - - use struct pt_regs * rather than void * for powerpc[64] sigcontext regs - - this is to match the kernel and glibc interfaces. here, struct pt_regs - is an incomplete type, but that's harmless, and if it's completed by - inclusion of another header then members of the struct pointed to by - the regs member can be accessed directly without going through a cast - or intermediate pointer object. - -diff --git a/arch/powerpc/bits/signal.h b/arch/powerpc/bits/signal.h -index 06efb11c..c1bf3caf 100644 ---- a/arch/powerpc/bits/signal.h -+++ b/arch/powerpc/bits/signal.h -@@ -28,7 +28,7 @@ struct sigcontext { - int signal; - unsigned long handler; - unsigned long oldmask; -- void *regs; -+ struct pt_regs *regs; - }; - - typedef struct { -diff --git a/arch/powerpc64/bits/signal.h b/arch/powerpc64/bits/signal.h -index 4dec22a5..d5493b18 100644 ---- a/arch/powerpc64/bits/signal.h -+++ b/arch/powerpc64/bits/signal.h -@@ -32,7 +32,7 @@ typedef struct sigcontext { - int _pad0; - unsigned long handler; - unsigned long oldmask; -- void *regs; -+ struct pt_regs *regs; - gregset_t gp_regs; - fpregset_t fp_regs; - vrregset_t *v_regs; diff --git a/srcpkgs/musl/patches/ppc64-fpregset_t.patch b/srcpkgs/musl/patches/ppc64-fpregset_t.patch deleted file mode 100644 index 12617ba0ef7d5..0000000000000 --- a/srcpkgs/musl/patches/ppc64-fpregset_t.patch +++ /dev/null @@ -1,31 +0,0 @@ -commit c9f48cde0a22641ce3daf54596a9ecebdab91435 -Author: Rich Felker -Date: Sat Oct 19 15:39:45 2019 -0400 - - fix fpregset_t type on powerpc64 - - the userspace ucontext API has this as an array rather than a - structure. - - commit 3c59a868956636bc8adafb1b168d090897692532 fixed the - corresponding mistake for vrregset_t, namely that the original - powerpc64 port used a mix of types from 32-bit powerpc and powerpc64 - rather than matching the 64-bit types. - -diff --git a/arch/powerpc64/bits/signal.h b/arch/powerpc64/bits/signal.h -index 2cc0604c..4dec22a5 100644 ---- a/arch/powerpc64/bits/signal.h -+++ b/arch/powerpc64/bits/signal.h -@@ -9,11 +9,7 @@ - #if defined(_GNU_SOURCE) || defined(_BSD_SOURCE) - - typedef unsigned long greg_t, gregset_t[48]; -- --typedef struct { -- double fpregs[32]; -- double fpscr; --} fpregset_t; -+typedef double fpregset_t[33]; - - typedef struct { - #ifdef __GNUC__ diff --git a/srcpkgs/musl/patches/ppcle.patch b/srcpkgs/musl/patches/ppcle.patch deleted file mode 100644 index 7d49338a5a0f1..0000000000000 --- a/srcpkgs/musl/patches/ppcle.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 20dfc2002482a21b955b710af119a01aecee784b Mon Sep 17 00:00:00 2001 -From: Daniel Kolesa -Date: Tue, 15 Dec 2020 20:42:17 +0100 -Subject: [PATCH] add ppc32 le subarch - ---- - configure | 1 + - 1 file changed, 1 insertion(+) - -diff --git configure configure -index 8680128..f1ca58e 100755 ---- a/configure -+++ b/configure -@@ -645,6 +645,7 @@ fi - if test "$ARCH" = "powerpc" ; then - trycppif "__NO_FPRS__ && !_SOFT_FLOAT" "$t" && fail \ - "$0: error: compiler's floating point configuration is unsupported" -+trycppif __LITTLE_ENDIAN__ "$t" && SUBARCH=${SUBARCH}le - trycppif _SOFT_FLOAT "$t" && SUBARCH=${SUBARCH}-sf - fi - --- -2.29.2 - diff --git a/srcpkgs/musl/patches/work_around_linux_bug_in_readlink_syscall_with_zero_buffer.patch b/srcpkgs/musl/patches/work_around_linux_bug_in_readlink_syscall_with_zero_buffer.patch deleted file mode 100644 index 3286432ebea23..0000000000000 --- a/srcpkgs/musl/patches/work_around_linux_bug_in_readlink_syscall_with_zero_buffer.patch +++ /dev/null @@ -1,59 +0,0 @@ -From e2fa720be7024cce4fc489f3877476d35da48ee2 Mon Sep 17 00:00:00 2001 -From: Rich Felker -Date: Mon, 23 Nov 2020 19:44:19 -0500 -Subject: [PATCH] work around linux bug in readlink syscall with zero buffer - size - -linux fails with EINVAL when a zero buffer size is passed to the -syscall. this is non-conforming because POSIX already defines EINVAL -with a significantly different meaning: the target is not a symlink. - -since the request is semantically valid, patch it up by using a dummy -buffer of length one, and truncating the return value to zero if it -succeeds. ---- - src/unistd/readlink.c | 11 +++++++++-- - src/unistd/readlinkat.c | 9 ++++++++- - 2 files changed, 17 insertions(+), 3 deletions(-) - -diff --git a/src/unistd/readlink.c b/src/unistd/readlink.c -index a152d5249..32f4537f9 100644 ---- a/src/unistd/readlink.c -+++ b/src/unistd/readlink.c -@@ -4,9 +4,16 @@ - - ssize_t readlink(const char *restrict path, char *restrict buf, size_t bufsize) - { -+ char dummy[1]; -+ if (!bufsize) { -+ buf = dummy; -+ bufsize = 1; -+ } - #ifdef SYS_readlink -- return syscall(SYS_readlink, path, buf, bufsize); -+ int r = __syscall(SYS_readlink, path, buf, bufsize); - #else -- return syscall(SYS_readlinkat, AT_FDCWD, path, buf, bufsize); -+ int r = __syscall(SYS_readlinkat, AT_FDCWD, path, buf, bufsize); - #endif -+ if (buf == dummy && r > 0) r = 0; -+ return __syscall_ret(r); - } -diff --git a/src/unistd/readlinkat.c b/src/unistd/readlinkat.c -index 9af45cd5a..f79d3d142 100644 ---- a/src/unistd/readlinkat.c -+++ b/src/unistd/readlinkat.c -@@ -3,5 +3,12 @@ - - ssize_t readlinkat(int fd, const char *restrict path, char *restrict buf, size_t bufsize) - { -- return syscall(SYS_readlinkat, fd, path, buf, bufsize); -+ char dummy[1]; -+ if (!bufsize) { -+ buf = dummy; -+ bufsize = 1; -+ } -+ int r = __syscall(SYS_readlinkat, fd, path, buf, bufsize); -+ if (buf == dummy && r > 0) r = 0; -+ return __syscall_ret(r); - } diff --git a/srcpkgs/musl/template b/srcpkgs/musl/template index e0e05c2df0995..a025e874623f2 100644 --- a/srcpkgs/musl/template +++ b/srcpkgs/musl/template @@ -1,8 +1,7 @@ # Template file for 'musl' pkgname=musl -reverts="1.2.0_1" -version=1.1.24 -revision=17 +version=1.2.4 +revision=1 archs="*-musl" bootstrap=yes build_style=gnu-configure @@ -10,9 +9,9 @@ configure_args="--prefix=/usr --disable-gcc-wrapper" short_desc="Musl C library" maintainer="Enno Boland " license="MIT" -homepage="https://musl.libc.org/" -distfiles="https://musl.libc.org/releases/musl-${version}.tar.gz" -checksum=1370c9a812b2cf2a7d92802510cca0058cc37e66a7bedd70051f0a34015022a3 +homepage="https://www.musl-libc.org/" +distfiles="https://www.musl-libc.org/releases/musl-${version}.tar.gz" +checksum=7a35eae33d5372a7c0da1188de798726f68825513b7ae3ebe97aaaa52114f039 nostrip_files="libc.so" shlib_provides="libc.so" From e2e360a7baeae5e47f1bc9ff5a88a8e41a1f0d9f Mon Sep 17 00:00:00 2001 From: John Date: Sun, 15 Jan 2023 13:11:12 +0100 Subject: [PATCH 065/189] nginx: add riscv64 cross profile --- srcpkgs/nginx/files/ngx_auto_config.h.riscv64 | 629 ++++++++++++++++++ srcpkgs/nginx/files/njs_auto_config.h.riscv64 | 163 +++++ srcpkgs/nginx/template | 4 + 3 files changed, 796 insertions(+) create mode 100644 srcpkgs/nginx/files/ngx_auto_config.h.riscv64 create mode 100644 srcpkgs/nginx/files/njs_auto_config.h.riscv64 diff --git a/srcpkgs/nginx/files/ngx_auto_config.h.riscv64 b/srcpkgs/nginx/files/ngx_auto_config.h.riscv64 new file mode 100644 index 0000000000000..fb49c8d012aff --- /dev/null +++ b/srcpkgs/nginx/files/ngx_auto_config.h.riscv64 @@ -0,0 +1,629 @@ +#define NGX_CONFIGURE " --prefix=/etc/nginx --conf-path=/etc/nginx/nginx.conf --sbin-path=/usr/bin/nginx --modules-path=/usr/lib/nginx/modules --pid-path=/run/nginx.pid --lock-path=/var/lock/nginx.lock --user=nginx --group=nginx --http-log-path=/var/log/nginx/access.log --error-log-path=/var/log/nginx/error.log --http-client-body-temp-path=/var/lib/nginx/tmp/client-body --http-proxy-temp-path=/var/lib/nginx/tmp/proxy --http-fastcgi-temp-path=/var/lib/nginx/tmp/fastcgi --http-scgi-temp-path=/var/lib/nginx/tmp/scgi --http-uwsgi-temp-path=/var/lib/nginx/tmp/uwsgi --with-compat --with-file-aio --with-http_dav_module --with-http_gunzip_module --with-http_gzip_static_module --with-http_realip_module --with-http_ssl_module --with-http_slice_module --with-http_stub_status_module --with-http_sub_module --with-http_v2_module --with-http_xslt_module=dynamic --with-http_geoip_module=dynamic --with-http_perl_module=dynamic --with-stream=dynamic --with-stream_geoip_module=dynamic --with-stream_realip_module --with-stream_ssl_module --with-stream_ssl_preread_module --with-mail --with-mail_ssl_module --with-pcre-jit --with-threads --add-dynamic-module=../njs-0.7.7/nginx" + +#ifndef NGX_HAVE_GCC_ATOMIC +#define NGX_HAVE_GCC_ATOMIC 1 +#endif + + +#ifndef NGX_HAVE_C99_VARIADIC_MACROS +#define NGX_HAVE_C99_VARIADIC_MACROS 1 +#endif + + +#ifndef NGX_HAVE_GCC_VARIADIC_MACROS +#define NGX_HAVE_GCC_VARIADIC_MACROS 1 +#endif + + +#ifndef NGX_HAVE_GCC_BSWAP64 +#define NGX_HAVE_GCC_BSWAP64 1 +#endif + + +#ifndef NGX_HAVE_EPOLL +#define NGX_HAVE_EPOLL 1 +#endif + + +#ifndef NGX_HAVE_CLEAR_EVENT +#define NGX_HAVE_CLEAR_EVENT 1 +#endif + + +#ifndef NGX_HAVE_EPOLLRDHUP +#define NGX_HAVE_EPOLLRDHUP 1 +#endif + + +#ifndef NGX_HAVE_EPOLLEXCLUSIVE +#define NGX_HAVE_EPOLLEXCLUSIVE 1 +#endif + + +#ifndef NGX_HAVE_EVENTFD +#define NGX_HAVE_EVENTFD 1 +#endif + + +#ifndef NGX_HAVE_SYS_EVENTFD_H +#define NGX_HAVE_SYS_EVENTFD_H 1 +#endif + + +#ifndef NGX_HAVE_O_PATH +#define NGX_HAVE_O_PATH 1 +#endif + + +#ifndef NGX_HAVE_SENDFILE +#define NGX_HAVE_SENDFILE 1 +#endif + + +#ifndef NGX_HAVE_SENDFILE64 +#define NGX_HAVE_SENDFILE64 1 +#endif + + +#ifndef NGX_HAVE_PR_SET_DUMPABLE +#define NGX_HAVE_PR_SET_DUMPABLE 1 +#endif + + +#ifndef NGX_HAVE_PR_SET_KEEPCAPS +#define NGX_HAVE_PR_SET_KEEPCAPS 1 +#endif + + +#ifndef NGX_HAVE_CAPABILITIES +#define NGX_HAVE_CAPABILITIES 1 +#endif + + +#ifndef NGX_HAVE_GNU_CRYPT_R +#define NGX_HAVE_GNU_CRYPT_R 1 +#endif + + +#ifndef NGX_ALIGNMENT +#define NGX_ALIGNMENT 16 +#endif + + +#ifndef NGX_CPU_CACHE_LINE +#define NGX_CPU_CACHE_LINE 32 +#endif + + +#define NGX_KQUEUE_UDATA_T (void *) + + +#ifndef NGX_HAVE_POSIX_FADVISE +#define NGX_HAVE_POSIX_FADVISE 1 +#endif + + +#ifndef NGX_HAVE_O_DIRECT +#define NGX_HAVE_O_DIRECT 1 +#endif + + +#ifndef NGX_HAVE_ALIGNED_DIRECTIO +#define NGX_HAVE_ALIGNED_DIRECTIO 1 +#endif + + +#ifndef NGX_HAVE_STATFS +#define NGX_HAVE_STATFS 1 +#endif + + +#ifndef NGX_HAVE_STATVFS +#define NGX_HAVE_STATVFS 1 +#endif + + +#ifndef NGX_HAVE_DLOPEN +#define NGX_HAVE_DLOPEN 1 +#endif + + +#ifndef NGX_HAVE_SCHED_YIELD +#define NGX_HAVE_SCHED_YIELD 1 +#endif + + +#ifndef NGX_HAVE_SCHED_SETAFFINITY +#define NGX_HAVE_SCHED_SETAFFINITY 1 +#endif + + +#ifndef NGX_HAVE_REUSEPORT +#define NGX_HAVE_REUSEPORT 1 +#endif + + +#ifndef NGX_HAVE_TRANSPARENT_PROXY +#define NGX_HAVE_TRANSPARENT_PROXY 1 +#endif + + +#ifndef NGX_HAVE_IP_BIND_ADDRESS_NO_PORT +#define NGX_HAVE_IP_BIND_ADDRESS_NO_PORT 1 +#endif + + +#ifndef NGX_HAVE_IP_PKTINFO +#define NGX_HAVE_IP_PKTINFO 1 +#endif + + +#ifndef NGX_HAVE_IPV6_RECVPKTINFO +#define NGX_HAVE_IPV6_RECVPKTINFO 1 +#endif + + +#ifndef NGX_HAVE_DEFERRED_ACCEPT +#define NGX_HAVE_DEFERRED_ACCEPT 1 +#endif + + +#ifndef NGX_HAVE_KEEPALIVE_TUNABLE +#define NGX_HAVE_KEEPALIVE_TUNABLE 1 +#endif + + +#ifndef NGX_HAVE_TCP_FASTOPEN +#define NGX_HAVE_TCP_FASTOPEN 1 +#endif + + +#ifndef NGX_HAVE_TCP_INFO +#define NGX_HAVE_TCP_INFO 1 +#endif + + +#ifndef NGX_HAVE_ACCEPT4 +#define NGX_HAVE_ACCEPT4 1 +#endif + + +#ifndef NGX_HAVE_FILE_AIO +#define NGX_HAVE_FILE_AIO 1 +#endif + + +#ifndef NGX_HAVE_EVENTFD +#define NGX_HAVE_EVENTFD 1 +#endif + + +#ifndef NGX_HAVE_SYS_EVENTFD_H +#define NGX_HAVE_SYS_EVENTFD_H 1 +#endif + + +#ifndef NGX_HAVE_UNIX_DOMAIN +#define NGX_HAVE_UNIX_DOMAIN 1 +#endif + + +#ifndef NGX_PTR_SIZE +#define NGX_PTR_SIZE 8 +#endif + + +#ifndef NGX_SIG_ATOMIC_T_SIZE +#define NGX_SIG_ATOMIC_T_SIZE 4 +#endif + + +#ifndef NGX_HAVE_LITTLE_ENDIAN +#define NGX_HAVE_LITTLE_ENDIAN 1 +#endif + + +#ifndef NGX_MAX_SIZE_T_VALUE +#define NGX_MAX_SIZE_T_VALUE 9223372036854775807LL +#endif + + +#ifndef NGX_SIZE_T_LEN +#define NGX_SIZE_T_LEN (sizeof("-9223372036854775808") - 1) +#endif + + +#ifndef NGX_MAX_OFF_T_VALUE +#define NGX_MAX_OFF_T_VALUE 9223372036854775807LL +#endif + + +#ifndef NGX_OFF_T_LEN +#define NGX_OFF_T_LEN (sizeof("-9223372036854775808") - 1) +#endif + + +#ifndef NGX_TIME_T_SIZE +#define NGX_TIME_T_SIZE 8 +#endif + + +#ifndef NGX_TIME_T_LEN +#define NGX_TIME_T_LEN (sizeof("-9223372036854775808") - 1) +#endif + + +#ifndef NGX_MAX_TIME_T_VALUE +#define NGX_MAX_TIME_T_VALUE 9223372036854775807LL +#endif + + +#ifndef NGX_HAVE_INET6 +#define NGX_HAVE_INET6 1 +#endif + + +#ifndef NGX_HAVE_PREAD +#define NGX_HAVE_PREAD 1 +#endif + + +#ifndef NGX_HAVE_PWRITE +#define NGX_HAVE_PWRITE 1 +#endif + + +#ifndef NGX_HAVE_PWRITEV +#define NGX_HAVE_PWRITEV 1 +#endif + + +#ifndef NGX_HAVE_LOCALTIME_R +#define NGX_HAVE_LOCALTIME_R 1 +#endif + + +#ifndef NGX_HAVE_CLOCK_MONOTONIC +#define NGX_HAVE_CLOCK_MONOTONIC 1 +#endif + + +#ifndef NGX_HAVE_POSIX_MEMALIGN +#define NGX_HAVE_POSIX_MEMALIGN 1 +#endif + + +#ifndef NGX_HAVE_MEMALIGN +#define NGX_HAVE_MEMALIGN 1 +#endif + + +#ifndef NGX_HAVE_MAP_ANON +#define NGX_HAVE_MAP_ANON 1 +#endif + + +#ifndef NGX_HAVE_MAP_DEVZERO +#define NGX_HAVE_MAP_DEVZERO 1 +#endif + + +#ifndef NGX_HAVE_SYSVSHM +#define NGX_HAVE_SYSVSHM 1 +#endif + + +#ifndef NGX_HAVE_POSIX_SEM +#define NGX_HAVE_POSIX_SEM 1 +#endif + + +#ifndef NGX_HAVE_MSGHDR_MSG_CONTROL +#define NGX_HAVE_MSGHDR_MSG_CONTROL 1 +#endif + + +#ifndef NGX_HAVE_FIONBIO +#define NGX_HAVE_FIONBIO 1 +#endif + + +#ifndef NGX_HAVE_FIONREAD +#define NGX_HAVE_FIONREAD 1 +#endif + + +#ifndef NGX_HAVE_GMTOFF +#define NGX_HAVE_GMTOFF 1 +#endif + + +#ifndef NGX_HAVE_D_TYPE +#define NGX_HAVE_D_TYPE 1 +#endif + + +#ifndef NGX_HAVE_SC_NPROCESSORS_ONLN +#define NGX_HAVE_SC_NPROCESSORS_ONLN 1 +#endif + + +#ifndef NGX_HAVE_OPENAT +#define NGX_HAVE_OPENAT 1 +#endif + + +#ifndef NGX_HAVE_GETADDRINFO +#define NGX_HAVE_GETADDRINFO 1 +#endif + + +#ifndef NGX_THREADS +#define NGX_THREADS 1 +#endif + + +#ifndef NGX_HTTP_CACHE +#define NGX_HTTP_CACHE 1 +#endif + + +#ifndef NGX_HTTP_GZIP +#define NGX_HTTP_GZIP 1 +#endif + + +#ifndef NGX_HTTP_SSI +#define NGX_HTTP_SSI 1 +#endif + + +#ifndef NGX_HTTP_GZIP +#define NGX_HTTP_GZIP 1 +#endif + + +#ifndef NGX_HTTP_V2 +#define NGX_HTTP_V2 1 +#endif + + +#ifndef NGX_HTTP_HEADERS +#define NGX_HTTP_HEADERS 1 +#endif + + +#ifndef NGX_HTTP_GZIP +#define NGX_HTTP_GZIP 1 +#endif + + +#ifndef NGX_HTTP_DAV +#define NGX_HTTP_DAV 1 +#endif + + +#ifndef NGX_CRYPT +#define NGX_CRYPT 1 +#endif + + +#ifndef NGX_HTTP_REALIP +#define NGX_HTTP_REALIP 1 +#endif + + +#ifndef NGX_HTTP_X_FORWARDED_FOR +#define NGX_HTTP_X_FORWARDED_FOR 1 +#endif + + +#ifndef NGX_HTTP_X_FORWARDED_FOR +#define NGX_HTTP_X_FORWARDED_FOR 1 +#endif + + +#ifndef NGX_HTTP_X_FORWARDED_FOR +#define NGX_HTTP_X_FORWARDED_FOR 1 +#endif + + +#ifndef NGX_HTTP_SSL +#define NGX_HTTP_SSL 1 +#endif + + +#ifndef NGX_HTTP_X_FORWARDED_FOR +#define NGX_HTTP_X_FORWARDED_FOR 1 +#endif + + +#ifndef NGX_HTTP_UPSTREAM_ZONE +#define NGX_HTTP_UPSTREAM_ZONE 1 +#endif + + +#ifndef NGX_STAT_STUB +#define NGX_STAT_STUB 1 +#endif + + +#ifndef NGX_MAIL_SSL +#define NGX_MAIL_SSL 1 +#endif + + +#ifndef NGX_STREAM_SSL +#define NGX_STREAM_SSL 1 +#endif + + +#ifndef NGX_STREAM_UPSTREAM_ZONE +#define NGX_STREAM_UPSTREAM_ZONE 1 +#endif + + +#ifndef NGX_COMPAT +#define NGX_COMPAT 1 +#endif + + +#ifndef NGX_HTTP_GZIP +#define NGX_HTTP_GZIP 1 +#endif + + +#ifndef NGX_HTTP_DAV +#define NGX_HTTP_DAV 1 +#endif + + +#ifndef NGX_HTTP_REALIP +#define NGX_HTTP_REALIP 1 +#endif + + +#ifndef NGX_HTTP_X_FORWARDED_FOR +#define NGX_HTTP_X_FORWARDED_FOR 1 +#endif + + +#ifndef NGX_HTTP_HEADERS +#define NGX_HTTP_HEADERS 1 +#endif + + +#ifndef NGX_HTTP_UPSTREAM_ZONE +#define NGX_HTTP_UPSTREAM_ZONE 1 +#endif + + +#ifndef NGX_STREAM_UPSTREAM_ZONE +#define NGX_STREAM_UPSTREAM_ZONE 1 +#endif + + +#ifndef NGX_PCRE2 +#define NGX_PCRE2 1 +#endif + + +#ifndef NGX_PCRE +#define NGX_PCRE 1 +#endif + + +#ifndef NGX_OPENSSL +#define NGX_OPENSSL 1 +#endif + + +#ifndef NGX_SSL +#define NGX_SSL 1 +#endif + + +#ifndef NGX_ZLIB +#define NGX_ZLIB 1 +#endif + + +#ifndef NGX_HAVE_EXSLT +#define NGX_HAVE_EXSLT 1 +#endif + + +#ifndef NGX_HAVE_PERL_MULTIPLICITY +#define NGX_HAVE_PERL_MULTIPLICITY 1 +#endif + + +#ifndef NGX_HAVE_GEOIP_V6 +#define NGX_HAVE_GEOIP_V6 1 +#endif + + +#ifndef NGX_PREFIX +#define NGX_PREFIX "/etc/nginx/" +#endif + + +#ifndef NGX_CONF_PREFIX +#define NGX_CONF_PREFIX "/etc/nginx/" +#endif + + +#ifndef NGX_SBIN_PATH +#define NGX_SBIN_PATH "/usr/bin/nginx" +#endif + + +#ifndef NGX_CONF_PATH +#define NGX_CONF_PATH "/etc/nginx/nginx.conf" +#endif + + +#ifndef NGX_PID_PATH +#define NGX_PID_PATH "/run/nginx.pid" +#endif + + +#ifndef NGX_LOCK_PATH +#define NGX_LOCK_PATH "/var/lock/nginx.lock" +#endif + + +#ifndef NGX_ERROR_LOG_PATH +#define NGX_ERROR_LOG_PATH "/var/log/nginx/error.log" +#endif + + +#ifndef NGX_HTTP_LOG_PATH +#define NGX_HTTP_LOG_PATH "/var/log/nginx/access.log" +#endif + + +#ifndef NGX_HTTP_CLIENT_TEMP_PATH +#define NGX_HTTP_CLIENT_TEMP_PATH "/var/lib/nginx/tmp/client-body" +#endif + + +#ifndef NGX_HTTP_PROXY_TEMP_PATH +#define NGX_HTTP_PROXY_TEMP_PATH "/var/lib/nginx/tmp/proxy" +#endif + + +#ifndef NGX_HTTP_FASTCGI_TEMP_PATH +#define NGX_HTTP_FASTCGI_TEMP_PATH "/var/lib/nginx/tmp/fastcgi" +#endif + + +#ifndef NGX_HTTP_UWSGI_TEMP_PATH +#define NGX_HTTP_UWSGI_TEMP_PATH "/var/lib/nginx/tmp/uwsgi" +#endif + + +#ifndef NGX_HTTP_SCGI_TEMP_PATH +#define NGX_HTTP_SCGI_TEMP_PATH "/var/lib/nginx/tmp/scgi" +#endif + + +#ifndef NGX_SUPPRESS_WARN +#define NGX_SUPPRESS_WARN 1 +#endif + + +#ifndef NGX_SMP +#define NGX_SMP 1 +#endif + + +#ifndef NGX_USER +#define NGX_USER "nginx" +#endif + + +#ifndef NGX_GROUP +#define NGX_GROUP "nginx" +#endif + diff --git a/srcpkgs/nginx/files/njs_auto_config.h.riscv64 b/srcpkgs/nginx/files/njs_auto_config.h.riscv64 new file mode 100644 index 0000000000000..6460d00be3b22 --- /dev/null +++ b/srcpkgs/nginx/files/njs_auto_config.h.riscv64 @@ -0,0 +1,163 @@ + +/* This file is auto-generated by configure */ + + +#ifndef NJS_LINUX +#define NJS_LINUX 1 +#endif + + +#ifndef NJS_GCC +#define NJS_GCC 1 +#endif + + +#ifndef NJS_TEST262 +#define NJS_TEST262 1 +#endif + + +#ifndef NJS_INT_SIZE +#define NJS_INT_SIZE 4 +#endif + + +#ifndef NJS_UINT_SIZE +#define NJS_UINT_SIZE 4 +#endif + + +#ifndef NJS_PTR_SIZE +#define NJS_PTR_SIZE 8 +#endif + + +#ifndef NJS_UINTPTR_T_SIZE +#define NJS_UINTPTR_T_SIZE 8 +#endif + + +#ifndef NJS_SIZE_T_SIZE +#define NJS_SIZE_T_SIZE 8 +#endif + + +#ifndef NJS_OFF_T_SIZE +#define NJS_OFF_T_SIZE 8 +#endif + + +#ifndef NJS_TIME_T_SIZE +#define NJS_TIME_T_SIZE 8 +#endif + + +#ifndef NJS_BYTE_ORDER +#define NJS_BYTE_ORDER little +#endif + + +#ifndef NJS_HAVE_LITTLE_ENDIAN +#define NJS_HAVE_LITTLE_ENDIAN 1 +#endif + + +#ifndef NJS_HAVE_UNSIGNED_INT128 +#define NJS_HAVE_UNSIGNED_INT128 1 +#endif + + +#ifndef NJS_HAVE_BUILTIN_EXPECT +#define NJS_HAVE_BUILTIN_EXPECT 1 +#endif + + +#ifndef NJS_HAVE_BUILTIN_UNREACHABLE +#define NJS_HAVE_BUILTIN_UNREACHABLE 1 +#endif + + +#ifndef NJS_HAVE_BUILTIN_PREFETCH +#define NJS_HAVE_BUILTIN_PREFETCH 1 +#endif + + +#ifndef NJS_HAVE_BUILTIN_CLZ +#define NJS_HAVE_BUILTIN_CLZ 1 +#endif + + +#ifndef NJS_HAVE_BUILTIN_CLZLL +#define NJS_HAVE_BUILTIN_CLZLL 1 +#endif + + +#ifndef NJS_HAVE_GCC_ATTRIBUTE_VISIBILITY +#define NJS_HAVE_GCC_ATTRIBUTE_VISIBILITY 1 +#endif + + +#ifndef NJS_HAVE_GCC_ATTRIBUTE_MALLOC +#define NJS_HAVE_GCC_ATTRIBUTE_MALLOC 1 +#endif + + +#ifndef NJS_HAVE_GCC_ATTRIBUTE_ALIGNED +#define NJS_HAVE_GCC_ATTRIBUTE_ALIGNED 1 +#endif + + +#ifndef NJS_HAVE_GCC_ATTRIBUTE_PACKED +#define NJS_HAVE_GCC_ATTRIBUTE_PACKED 1 +#endif + + +#ifndef NJS_HAVE_CLOCK_MONOTONIC +#define NJS_HAVE_CLOCK_MONOTONIC 1 +#endif + + +#ifndef NJS_HAVE_TM_GMTOFF +#define NJS_HAVE_TM_GMTOFF 1 +#endif + + +#ifndef NJS_HAVE_POSIX_MEMALIGN +#define NJS_HAVE_POSIX_MEMALIGN 1 +#endif + + +#ifndef NJS_HAVE_GETRANDOM +#define NJS_HAVE_GETRANDOM 1 +#endif + + +#ifndef NJS_HAVE_STAT_ATIM +#define NJS_HAVE_STAT_ATIM 1 +#endif + + +#ifndef NJS_HAVE_EXPLICIT_BZERO +#define NJS_HAVE_EXPLICIT_BZERO 1 +#endif + + +#ifndef NJS_HAVE_PCRE2 +#define NJS_HAVE_PCRE2 1 +#endif + + +#ifndef NJS_PCRE2_VERSION +#define NJS_PCRE2_VERSION 10.39 +#endif + + +#ifndef NJS_HAVE_OPENSSL +#define NJS_HAVE_OPENSSL 1 +#endif + + +#ifndef NJS_OPENSSL_VERSION +#define NJS_OPENSSL_VERSION "OpenSSL 1.1.1s 1 Nov 2022" +#endif + diff --git a/srcpkgs/nginx/template b/srcpkgs/nginx/template index 174b57623603f..ba1a237a34b4b 100644 --- a/srcpkgs/nginx/template +++ b/srcpkgs/nginx/template @@ -126,6 +126,10 @@ pre_build() { cp "${FILESDIR}/ngx_auto_config.h.aarch64" objs/ngx_auto_config.h cp "${FILESDIR}/njs_auto_config.h.aarch64" ../njs-${_njs_version}/build/njs_auto_config.h ;; + riscv64*) + cp "${FILESDIR}/ngx_auto_config.h.riscv64" objs/ngx_auto_config.h + cp "${FILESDIR}/njs_auto_config.h.riscv64" ../njs-${_njs_version}/build/njs_auto_config.h + ;; esac sed -i "s:-I/usr:-I${XBPS_CROSS_BASE}/usr:" objs/Makefile From 7d3ef5fbd139b35d1924b44ae4214f9a1b38f30d Mon Sep 17 00:00:00 2001 From: John Date: Sun, 15 Jan 2023 13:56:49 +0100 Subject: [PATCH 066/189] boost: add riscv64 support --- srcpkgs/boost/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/boost/template b/srcpkgs/boost/template index 1f6abd4fcab19..b86ce95156071 100644 --- a/srcpkgs/boost/template +++ b/srcpkgs/boost/template @@ -86,6 +86,7 @@ case "$XBPS_TARGET_MACHINE" in aarch64*) _arch=arm; _abi=aapcs ;; mips*) _arch=mips32r2; _abi=o32 ;; ppc*) _arch=power; _abi=sysv ;; + riscv64*) _arch=riscv; _abi=sysv ;; esac do_build() { From 3f9b0199b9b157d7cb2e10765a293737b18e8b4e Mon Sep 17 00:00:00 2001 From: John Date: Sun, 15 Jan 2023 14:01:11 +0100 Subject: [PATCH 067/189] LuaJIT: mark as unsupported on riscv64 --- srcpkgs/LuaJIT/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/LuaJIT/template b/srcpkgs/LuaJIT/template index 85449ac3d6f73..15644ddfa6ff0 100644 --- a/srcpkgs/LuaJIT/template +++ b/srcpkgs/LuaJIT/template @@ -4,6 +4,7 @@ version=2.1.0beta3 revision=2 _so_version=2.1.0 _dist_version=${_so_version}-beta3 +archs="~riscv64*" hostmakedepends="lua52-BitOp" short_desc="Just-In-Time Compiler for Lua" maintainer="Orphaned " From 82acab8c7c63b55bf11a7d5a243d0f910a43de02 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 15 Jan 2023 16:20:39 +0100 Subject: [PATCH 068/189] libcec: add patch to skip ptr -> bool conversion --- srcpkgs/libcec/patches/bool.patch | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 srcpkgs/libcec/patches/bool.patch diff --git a/srcpkgs/libcec/patches/bool.patch b/srcpkgs/libcec/patches/bool.patch new file mode 100644 index 0000000000000..d57714a1594ea --- /dev/null +++ b/srcpkgs/libcec/patches/bool.patch @@ -0,0 +1,20 @@ +--- a/include/cecloader.h 2020-07-13 12:18:33.000000000 +0200 ++++ - 2023-01-15 16:19:43.758391565 +0100 +@@ -172,7 +172,7 @@ + if (!g_libCEC) + { + std::cout << dlerror() << std::endl; +- return NULL; ++ return false; + } + } + +@@ -181,7 +181,7 @@ + if (!LibCecBootloader) + { + std::cout << "cannot find CECStartBootloader" << std::endl; +- return NULL; ++ return false; + } + + bool bReturn = LibCecBootloader(); From 6e9a0221e2c5f14bbe6ff25355c2dd757277d997 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 15 Jan 2023 16:22:08 +0100 Subject: [PATCH 069/189] kodi: enable on riscv64 --- srcpkgs/kodi/template | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/srcpkgs/kodi/template b/srcpkgs/kodi/template index bd5433969db64..7efb35c5ae1b3 100644 --- a/srcpkgs/kodi/template +++ b/srcpkgs/kodi/template @@ -39,8 +39,7 @@ if [ "$XBPS_WORDSIZE" = 32 ]; then fi lib32disabled=yes -archs="i686* x86_64* aarch64* - ppc64* armv6l* armv7l*" +archs="i686* x86_64* aarch64* ppc64* armv6l* armv7l* riscv64*" hostmakedepends=" automake libtool pkg-config gperf cmake gettext zip unzip nasm yasm python3-devel From e2e0a925719e8a18e70b1d1e4cf781ed5912a563 Mon Sep 17 00:00:00 2001 From: John Date: Mon, 16 Jan 2023 22:05:51 +0100 Subject: [PATCH 070/189] nss: add riscv64 arch --- srcpkgs/nss/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/nss/template b/srcpkgs/nss/template index 7f5eae8fd3d96..42c9d9c82908b 100644 --- a/srcpkgs/nss/template +++ b/srcpkgs/nss/template @@ -49,7 +49,7 @@ do_build() { fi case "$XBPS_TARGET_MACHINE" in - aarch64*|ppc*|x86_64*|i?86*) + aarch64*|ppc*|x86_64*|i?86*|riscv64*) _ARCH="${XBPS_TARGET_MACHINE%-*}" ;; arm*) _ARCH="arm";; From 638fb89fbcd444f58c3cc19c6a0c0d4d0be42c6b Mon Sep 17 00:00:00 2001 From: John Date: Mon, 16 Jan 2023 22:05:59 +0100 Subject: [PATCH 071/189] libunwind: update to 1.6.2. --- common/shlibs | 1 + srcpkgs/libunwind/template | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/common/shlibs b/common/shlibs index 338e5f132503c..8c8e4c58e75a4 100644 --- a/common/shlibs +++ b/common/shlibs @@ -1358,6 +1358,7 @@ libunwind-aarch64.so.8 libunwind-1.5.0_3 libunwind-ppc32.so.8 libunwind-1.5.0_3 libunwind-ppc64.so.8 libunwind-1.5.0_3 libunwind-setjmp.so.0 libunwind-1.5.0_3 +libunwind-riscv.so.8 libunwind-1.6.2_1 libmicrohttpd.so.12 libmicrohttpd-0.9.73_1 libmicrodns.so.1 libmicrodns-0.2.0_1 libgit2.so.1.6 libgit2-1.6.4_1 diff --git a/srcpkgs/libunwind/template b/srcpkgs/libunwind/template index d4819ce54acd0..d6c3b739f7c68 100644 --- a/srcpkgs/libunwind/template +++ b/srcpkgs/libunwind/template @@ -1,7 +1,7 @@ # Template file for 'libunwind' pkgname=libunwind -version=1.5.0 -revision=3 +version=1.6.2 +revision=1 build_style=gnu-configure hostmakedepends="libtool automake" makedepends="liblzma-devel" @@ -10,7 +10,7 @@ maintainer="Orphaned " license="MIT" homepage="https://www.nongnu.org/libunwind/" distfiles="${NONGNU_SITE}/${pkgname}/${pkgname}-${version/rc/-rc}.tar.gz" -checksum=90337653d92d4a13de590781371c604f9031cdb50520366aa1e3a91e1efb1017 +checksum=4a6aec666991fb45d0889c44aede8ad6eb108071c3554fcdff671f9c94794976 CFLAGS="-fcommon" From e796fe345178757906c51256d1761fbfcf1f205e Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 00:03:31 +0100 Subject: [PATCH 072/189] chromium: prepare some riscv64 things --- srcpkgs/chromium/patches/riscv-angle.patch | 27 + .../chromium/patches/riscv-breakpad.patch.old | 569 +++++ srcpkgs/chromium/patches/riscv-crashpad.patch | 777 +++++++ srcpkgs/chromium/patches/riscv-dav1d.patch | 43 + .../chromium/patches/riscv-sandbox.patch.old | 1942 +++++++++++++++++ srcpkgs/chromium/patches/riscv-v8.patch.old | 176 ++ srcpkgs/chromium/patches/riscv.patch.old | 118 + srcpkgs/chromium/template | 4 +- 8 files changed, 3655 insertions(+), 1 deletion(-) create mode 100644 srcpkgs/chromium/patches/riscv-angle.patch create mode 100644 srcpkgs/chromium/patches/riscv-breakpad.patch.old create mode 100644 srcpkgs/chromium/patches/riscv-crashpad.patch create mode 100644 srcpkgs/chromium/patches/riscv-dav1d.patch create mode 100644 srcpkgs/chromium/patches/riscv-sandbox.patch.old create mode 100644 srcpkgs/chromium/patches/riscv-v8.patch.old create mode 100644 srcpkgs/chromium/patches/riscv.patch.old diff --git a/srcpkgs/chromium/patches/riscv-angle.patch b/srcpkgs/chromium/patches/riscv-angle.patch new file mode 100644 index 0000000000000..a25bf0d3f3262 --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-angle.patch @@ -0,0 +1,27 @@ +Index: chromium-103.0.5060.53/third_party/angle/gni/angle.gni +=================================================================== +--- chromium-103.0.5060.53.orig/third_party/angle/gni/angle.gni ++++ chromium-103.0.5060.53/third_party/angle/gni/angle.gni +@@ -77,7 +77,8 @@ declare_args() { + + if (current_cpu == "arm64" || current_cpu == "x64" || + current_cpu == "mips64el" || current_cpu == "s390x" || +- current_cpu == "ppc64" || current_cpu == "loong64") { ++ current_cpu == "ppc64" || current_cpu == "loong64" || ++ current_cpu == "riscv64") { + angle_64bit_current_cpu = true + } else if (current_cpu == "arm" || current_cpu == "x86" || + current_cpu == "mipsel" || current_cpu == "s390" || +Index: chromium-103.0.5060.53/third_party/angle/src/common/platform.h +=================================================================== +--- chromium-103.0.5060.53.orig/third_party/angle/src/common/platform.h ++++ chromium-103.0.5060.53/third_party/angle/src/common/platform.h +@@ -102,7 +102,7 @@ + #endif + + // Mips and arm devices need to include stddef for size_t. +-#if defined(__mips__) || defined(__arm__) || defined(__aarch64__) ++#if defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(__riscv) + # include + #endif + diff --git a/srcpkgs/chromium/patches/riscv-breakpad.patch.old b/srcpkgs/chromium/patches/riscv-breakpad.patch.old new file mode 100644 index 0000000000000..6748bc1d561ea --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-breakpad.patch.old @@ -0,0 +1,569 @@ +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h +@@ -44,6 +44,8 @@ typedef MDRawContextARM RawContextCPU; + typedef MDRawContextARM64_Old RawContextCPU; + #elif defined(__mips__) + typedef MDRawContextMIPS RawContextCPU; ++#elif defined(__riscv) ++typedef MDRawContextRISCV64 RawContextCPU; + #else + #error "This code has not been ported to your platform yet." + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc +@@ -270,7 +270,23 @@ void ThreadInfo::FillCPUContext(RawConte + out->float_save.fir = mcontext.fpc_eir; + #endif + } +-#endif // __mips__ ++#elif defined(__riscv) ++ ++uintptr_t ThreadInfo::GetInstructionPointer() const { ++ return mcontext.__gregs[REG_PC]; ++} ++ ++void ThreadInfo::FillCPUContext(RawContextCPU* out) const { ++ out->context_flags = MD_CONTEXT_RISCV64_FULL; ++ ++ my_memcpy (out->iregs, mcontext.__gregs, MD_CONTEXT_RISCV64_GPR_COUNT * 8); ++ ++ out->float_save.fcsr = mcontext.__fpregs.__d.__fcsr; ++ my_memcpy(&out->float_save.regs, &mcontext.__fpregs.__d.__f, ++ MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT * 8); ++} ++ ++#endif // __riscv + + void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) { + assert(gp_regs || size); +@@ -279,6 +295,11 @@ void ThreadInfo::GetGeneralPurposeRegist + *gp_regs = mcontext.gregs; + if (size) + *size = sizeof(mcontext.gregs); ++#elif defined(__riscv) ++ if (gp_regs) ++ *gp_regs = mcontext.__gregs; ++ if (size) ++ *size = sizeof(mcontext.__gregs); + #else + if (gp_regs) + *gp_regs = ®s; +@@ -294,6 +315,11 @@ void ThreadInfo::GetFloatingPointRegiste + *fp_regs = &mcontext.fpregs; + if (size) + *size = sizeof(mcontext.fpregs); ++#elif defined(__riscv) ++ if (fp_regs) ++ *fp_regs = &mcontext.__fpregs; ++ if (size) ++ *size = sizeof(mcontext.__fpregs); + #else + if (fp_regs) + *fp_regs = &fpregs; +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h +@@ -68,7 +68,7 @@ struct ThreadInfo { + // Use the structures defined in + struct user_regs_struct regs; + struct user_fpsimd_struct fpregs; +-#elif defined(__mips__) ++#elif defined(__mips__) || defined(__riscv) + // Use the structure defined in . + mcontext_t mcontext; + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc +@@ -254,6 +254,27 @@ void UContextReader::FillCPUContext(RawC + out->float_save.fir = uc->uc_mcontext.fpc_eir; // Unused. + #endif + } ++ ++#elif defined(__riscv) ++ ++uintptr_t UContextReader::GetStackPointer(const ucontext_t* uc) { ++ return uc->uc_mcontext.__gregs[REG_SP]; ++} ++ ++uintptr_t UContextReader::GetInstructionPointer(const ucontext_t* uc) { ++ return uc->uc_mcontext.__gregs[REG_PC]; ++} ++ ++void UContextReader::FillCPUContext(RawContextCPU* out, const ucontext_t* uc) { ++ out->context_flags = MD_CONTEXT_RISCV64_FULL; ++ ++ for (int i = 0; i < MD_CONTEXT_RISCV64_GPR_COUNT; ++i) ++ out->iregs[i] = uc->uc_mcontext.__gregs[i]; ++ ++ out->float_save.fcsr = uc->uc_mcontext.__fpregs.__d.__fcsr; ++ for (int i = 0; i < MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT; ++i) ++ out->float_save.regs[i] = uc->uc_mcontext.__fpregs.__d.__f[i]; ++} + #endif + + } // namespace google_breakpad +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc +@@ -461,7 +461,7 @@ bool ExceptionHandler::HandleSignal(int + memcpy(&g_crash_context_.float_state, fp_ptr, + sizeof(g_crash_context_.float_state)); + } +-#elif !defined(__ARM_EABI__) && !defined(__mips__) ++#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + // FP state is not part of user ABI on ARM Linux. + // In case of MIPS Linux FP state is already part of ucontext_t + // and 'float_state' is not a member of CrashContext. +@@ -701,7 +701,7 @@ bool ExceptionHandler::WriteMinidump() { + } + #endif + +-#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv) + // FPU state is not part of ARM EABI ucontext_t. + memcpy(&context.float_state, context.context.uc_mcontext.fpregs, + sizeof(context.float_state)); +@@ -726,6 +726,9 @@ bool ExceptionHandler::WriteMinidump() { + #elif defined(__mips__) + context.siginfo.si_addr = + reinterpret_cast(context.context.uc_mcontext.pc); ++#elif defined(__riscv) ++ context.siginfo.si_addr = ++ reinterpret_cast(context.context.uc_mcontext.__gregs[REG_PC]); + #else + #error "This code has not been ported to your platform yet." + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h +@@ -192,7 +192,7 @@ class ExceptionHandler { + siginfo_t siginfo; + pid_t tid; // the crashing thread. + ucontext_t context; +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + // #ifdef this out because FP state is not part of user ABI for Linux ARM. + // In case of MIPS Linux FP state is already part of ucontext_t so + // 'float_state' is not required. +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc +@@ -138,7 +138,7 @@ class MicrodumpWriter { + const MicrodumpExtraInfo& microdump_extra_info, + LinuxDumper* dumper) + : ucontext_(context ? &context->context : NULL), +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + float_state_(context ? &context->float_state : NULL), + #endif + dumper_(dumper), +@@ -337,6 +337,12 @@ class MicrodumpWriter { + # else + # error "This mips ABI is currently not supported (n32)" + #endif ++#elif defined(__riscv) ++# if __riscv_xlen == 64 ++ const char kArch[] = "riscv64"; ++# else ++# error "This RISC-V ABI is currently not supported" ++#endif + #else + #error "This code has not been ported to your platform yet" + #endif +@@ -409,7 +415,7 @@ class MicrodumpWriter { + void DumpCPUState() { + RawContextCPU cpu; + my_memset(&cpu, 0, sizeof(RawContextCPU)); +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + UContextReader::FillCPUContext(&cpu, ucontext_, float_state_); + #else + UContextReader::FillCPUContext(&cpu, ucontext_); +@@ -605,7 +611,7 @@ class MicrodumpWriter { + void* Alloc(unsigned bytes) { return dumper_->allocator()->Alloc(bytes); } + + const ucontext_t* const ucontext_; +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + const google_breakpad::fpstate_t* const float_state_; + #endif + LinuxDumper* dumper_; +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc +@@ -112,6 +112,9 @@ bool LinuxCoreDumper::GetThreadInfoByInd + #elif defined(__mips__) + stack_pointer = + reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); ++#elif defined(__riscv) ++ stack_pointer = ++ reinterpret_cast(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]); + #else + #error "This code hasn't been ported to your platform yet." + #endif +@@ -218,6 +221,8 @@ bool LinuxCoreDumper::EnumerateThreads() + info.mcontext.mdlo = status->pr_reg[EF_LO]; + info.mcontext.mdhi = status->pr_reg[EF_HI]; + info.mcontext.pc = status->pr_reg[EF_CP0_EPC]; ++#elif defined(__riscv) ++ memcpy(info.mcontext.__gregs, status->pr_reg, sizeof(info.mcontext.__gregs)); + #else // __mips__ + memcpy(&info.regs, status->pr_reg, sizeof(info.regs)); + #endif // __mips__ +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h +@@ -63,7 +63,8 @@ namespace google_breakpad { + (defined(__mips__) && _MIPS_SIM == _ABIO32) + typedef Elf32_auxv_t elf_aux_entry; + #elif defined(__x86_64) || defined(__aarch64__) || \ +- (defined(__mips__) && _MIPS_SIM != _ABIO32) ++ (defined(__mips__) && _MIPS_SIM != _ABIO32) || \ ++ (defined(__riscv) && __riscv_xlen == 64) + typedef Elf64_auxv_t elf_aux_entry; + #endif + +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc +@@ -298,6 +298,9 @@ bool LinuxPtraceDumper::GetThreadInfoByI + #elif defined(__mips__) + stack_pointer = + reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); ++#elif defined(__riscv) ++ stack_pointer = ++ reinterpret_cast(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]); + #else + #error "This code hasn't been ported to your platform yet." + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc +@@ -136,7 +136,7 @@ class MinidumpWriter { + : fd_(minidump_fd), + path_(minidump_path), + ucontext_(context ? &context->context : NULL), +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + float_state_(context ? &context->float_state : NULL), + #endif + dumper_(dumper), +@@ -468,7 +468,7 @@ class MinidumpWriter { + if (!cpu.Allocate()) + return false; + my_memset(cpu.get(), 0, sizeof(RawContextCPU)); +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + UContextReader::FillCPUContext(cpu.get(), ucontext_, float_state_); + #else + UContextReader::FillCPUContext(cpu.get(), ucontext_); +@@ -897,7 +897,7 @@ class MinidumpWriter { + dirent->location.rva = 0; + } + +-#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) ++#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || defined(__riscv) + bool WriteCPUInformation(MDRawSystemInfo* sys_info) { + char vendor_id[sizeof(sys_info->cpu.x86_cpu_info.vendor_id) + 1] = {0}; + static const char vendor_id_name[] = "vendor_id"; +@@ -925,6 +925,12 @@ class MinidumpWriter { + # else + # error "This mips ABI is currently not supported (n32)" + #endif ++#elif defined(__riscv) ++# if __riscv_xlen == 64 ++ MD_CPU_ARCHITECTURE_RISCV64; ++# else ++# error "This RISC-V ABI is currently not supported" ++# endif + #elif defined(__i386__) + MD_CPU_ARCHITECTURE_X86; + #else +@@ -1333,7 +1339,7 @@ class MinidumpWriter { + const char* path_; // Path to the file where the minidum should be written. + + const ucontext_t* const ucontext_; // also from the signal handler +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + const google_breakpad::fpstate_t* const float_state_; // ditto + #endif + LinuxDumper* dumper_; +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h +@@ -48,7 +48,7 @@ class ExceptionHandler; + + #if defined(__aarch64__) + typedef struct fpsimd_context fpstate_t; +-#elif !defined(__ARM_EABI__) && !defined(__mips__) ++#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + typedef std::remove_pointer::type fpstate_t; + #endif + +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S +@@ -527,6 +527,68 @@ breakpad_getcontext: + .cfi_endproc + .size breakpad_getcontext, . - breakpad_getcontext + ++#elif defined(__riscv) && __riscv_xlen == 64 ++ ++#define __NR_rt_sigprocmask 135 ++#define _NSIG8 64 / 8 ++#define SIG_BLOCK 0 ++ ++ .text ++ .global breakpad_getcontext ++ .hidden breakpad_getcontext ++ .type breakpad_getcontext, @function ++ .align 2 ++breakpad_getcontext: ++ sd ra, MCONTEXT_GREGS_OFFSET + 0*8(a0) ++ sd ra, MCONTEXT_GREGS_OFFSET + 1*8(a0) ++ sd sp, MCONTEXT_GREGS_OFFSET + 2*8(a0) ++ sd s0, MCONTEXT_GREGS_OFFSET + 8*8(a0) ++ sd s1, MCONTEXT_GREGS_OFFSET + 9*8(a0) ++ sd x0, MCONTEXT_GREGS_OFFSET + 10*8(a0) /* return 0 by overwriting a0. */ ++ sd s2, MCONTEXT_GREGS_OFFSET + 18*8(a0) ++ sd s3, MCONTEXT_GREGS_OFFSET + 19*8(a0) ++ sd s4, MCONTEXT_GREGS_OFFSET + 20*8(a0) ++ sd s5, MCONTEXT_GREGS_OFFSET + 21*8(a0) ++ sd s6, MCONTEXT_GREGS_OFFSET + 22*8(a0) ++ sd s7, MCONTEXT_GREGS_OFFSET + 23*8(a0) ++ sd s8, MCONTEXT_GREGS_OFFSET + 24*8(a0) ++ sd s9, MCONTEXT_GREGS_OFFSET + 25*8(a0) ++ sd s10, MCONTEXT_GREGS_OFFSET + 26*8(a0) ++ sd s11, MCONTEXT_GREGS_OFFSET + 27*8(a0) ++ ++#ifndef __riscv_float_abi_soft ++ frsr a1 ++ ++ fsd fs0, MCONTEXT_FPREGS_OFFSET + 8*8(a0) ++ fsd fs1, MCONTEXT_FPREGS_OFFSET + 9*8(a0) ++ fsd fs2, MCONTEXT_FPREGS_OFFSET + 18*8(a0) ++ fsd fs3, MCONTEXT_FPREGS_OFFSET + 19*8(a0) ++ fsd fs4, MCONTEXT_FPREGS_OFFSET + 20*8(a0) ++ fsd fs5, MCONTEXT_FPREGS_OFFSET + 21*8(a0) ++ fsd fs6, MCONTEXT_FPREGS_OFFSET + 22*8(a0) ++ fsd fs7, MCONTEXT_FPREGS_OFFSET + 23*8(a0) ++ fsd fs8, MCONTEXT_FPREGS_OFFSET + 24*8(a0) ++ fsd fs9, MCONTEXT_FPREGS_OFFSET + 25*8(a0) ++ fsd fs10, MCONTEXT_FPREGS_OFFSET + 26*8(a0) ++ fsd fs11, MCONTEXT_FPREGS_OFFSET + 27*8(a0) ++ ++ sw a1, MCONTEXT_FSR_OFFSET(a0) ++#endif /* __riscv_float_abi_soft */ ++ ++/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG / 8) */ ++ li a3, _NSIG8 ++ add a2, a0, UCONTEXT_SIGMASK_OFFSET ++ mv a1, zero ++ li a0, SIG_BLOCK ++ ++ li a7, __NR_rt_sigprocmask ++ scall ++ ++ /* Always return 0 for success, even if sigprocmask failed. */ ++ mv a0, zero ++ ret ++ .size breakpad_getcontext, . - breakpad_getcontext ++ + #else + #error "This file has not been ported for your CPU!" + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc +@@ -65,7 +65,8 @@ bool MemoryMappedFile::Map(const char* p + } + + #if defined(__x86_64__) || defined(__aarch64__) || \ +- (defined(__mips__) && _MIPS_SIM == _ABI64) ++ (defined(__mips__) && _MIPS_SIM == _ABI64) || \ ++ (defined(__riscv) && __riscv_xlen == 64) + + struct kernel_stat st; + if (sys_fstat(fd, &st) == -1 || st.st_size < 0) { +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h +@@ -146,6 +146,14 @@ + #endif + #define FPREGS_OFFSET_MXCSR 24 + ++#elif defined(__riscv) ++ ++#define UCONTEXT_SIGMASK_OFFSET 40 ++ ++#define MCONTEXT_GREGS_OFFSET 176 ++#define MCONTEXT_FPREGS_OFFSET 432 ++#define MCONTEXT_FSR_OFFSET (MCONTEXT_FPREGS_OFFSET + 32*8) ++ + #else + #error "This header has not been ported for your CPU" + #endif +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h +=================================================================== +--- /dev/null ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h +@@ -0,0 +1,121 @@ ++/* Copyright 2013 Google Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are ++ * met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Google Inc. nor the names of its ++ * contributors may be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* minidump_format.h: A cross-platform reimplementation of minidump-related ++ * portions of DbgHelp.h from the Windows Platform SDK. ++ * ++ * (This is C99 source, please don't corrupt it with C++.) ++ * ++ * This file contains the necessary definitions to read minidump files ++ * produced on ARM. These files may be read on any platform provided ++ * that the alignments of these structures on the processing system are ++ * identical to the alignments of these structures on the producing system. ++ * For this reason, precise-sized types are used. The structures defined ++ * by this file have been laid out to minimize alignment problems by ++ * ensuring that all members are aligned on their natural boundaries. ++ * In some cases, tail-padding may be significant when different ABIs specify ++ * different tail-padding behaviors. To avoid problems when reading or ++ * writing affected structures, MD_*_SIZE macros are provided where needed, ++ * containing the useful size of the structures without padding. ++ * ++ * Structures that are defined by Microsoft to contain a zero-length array ++ * are instead defined here to contain an array with one element, as ++ * zero-length arrays are forbidden by standard C and C++. In these cases, ++ * *_minsize constants are provided to be used in place of sizeof. For a ++ * cleaner interface to these sizes when using C++, see minidump_size.h. ++ * ++ * These structures are also sufficient to populate minidump files. ++ * ++ * Because precise data type sizes are crucial for this implementation to ++ * function properly and portably, a set of primitive types with known sizes ++ * are used as the basis of each structure defined by this file. ++ * ++ * Author: Colin Blundell ++ */ ++ ++/* ++ * RISCV64 support ++ */ ++ ++#ifndef GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ ++#define GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ ++ ++#include "google_breakpad/common/breakpad_types.h" ++ ++#define MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT 32 ++#define MD_CONTEXT_RISCV64_GPR_COUNT 32 ++ ++typedef struct { ++ /* 32 64-bit floating point registers, f0 .. f31. */ ++ uint64_t regs[MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT]; ++ ++ uint32_t fcsr; /* FPU control and status register */ ++} MDFloatingSaveAreaRISCV64; ++ ++/* For (MDRawContextRISCV64).context_flags. These values indicate the type of ++ * context stored in the structure. */ ++#define MD_CONTEXT_RISCV64 0x00400000 ++#define MD_CONTEXT_RISCV64_CONTROL (MD_CONTEXT_RISCV64 | 0x00000001) ++#define MD_CONTEXT_RISCV64_INTEGER (MD_CONTEXT_RISCV64 | 0x00000002) ++#define MD_CONTEXT_RISCV64_FLOATING_POINT (MD_CONTEXT_RISCV64 | 0x00000004) ++#define MD_CONTEXT_RISCV64_DEBUG (MD_CONTEXT_RISCV64 | 0x00000008) ++#define MD_CONTEXT_RISCV64_FULL (MD_CONTEXT_RISCV64_CONTROL | \ ++ MD_CONTEXT_RISCV64_INTEGER | \ ++ MD_CONTEXT_RISCV64_FLOATING_POINT) ++#define MD_CONTEXT_RISCV64_ALL (MD_CONTEXT_RISCV64_FULL | MD_CONTEXT_RISCV64_DEBUG) ++ ++typedef struct { ++ /* Determines which fields of this struct are populated */ ++ uint32_t context_flags; ++ ++ /* 32 64-bit integer registers, x1 .. x31 + the PC ++ * Note the following fixed uses: ++ * x8 is the frame pointer ++ * x1 is the link register ++ * x2 is the stack pointer ++ * The PC is effectively x0. ++ */ ++ uint64_t iregs[MD_CONTEXT_RISCV64_GPR_COUNT]; ++ ++ /* The next field is included with MD_CONTEXT64_ARM_FLOATING_POINT */ ++ MDFloatingSaveAreaRISCV64 float_save; ++ ++} MDRawContextRISCV64; ++ ++/* Indices into iregs for registers with a dedicated or conventional ++ * purpose. ++ */ ++enum MDRISCV64RegisterNumbers { ++ MD_CONTEXT_RISCV64_REG_FP = 8, ++ MD_CONTEXT_RISCV64_REG_RA = 1, ++ MD_CONTEXT_RISCV64_REG_SP = 2, ++ MD_CONTEXT_RISCV64_REG_PC = 0 ++}; ++ ++#endif /* GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ */ +Index: chromium-102.0.5005.61/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h ++++ chromium-102.0.5005.61/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h +@@ -118,6 +118,7 @@ typedef struct { + #include "minidump_cpu_mips.h" + #include "minidump_cpu_ppc.h" + #include "minidump_cpu_ppc64.h" ++#include "minidump_cpu_riscv64.h" + #include "minidump_cpu_sparc.h" + #include "minidump_cpu_x86.h" + +@@ -660,6 +661,7 @@ typedef enum { + MD_CPU_ARCHITECTURE_PPC64 = 0x8002, /* Breakpad-defined value for PPC64 */ + MD_CPU_ARCHITECTURE_ARM64_OLD = 0x8003, /* Breakpad-defined value for ARM64 */ + MD_CPU_ARCHITECTURE_MIPS64 = 0x8004, /* Breakpad-defined value for MIPS64 */ ++ MD_CPU_ARCHITECTURE_RISCV64 = 0x8005, /* Breakpad-defined value for RISCV64 */ + MD_CPU_ARCHITECTURE_UNKNOWN = 0xffff /* PROCESSOR_ARCHITECTURE_UNKNOWN */ + } MDCPUArchitecture; + diff --git a/srcpkgs/chromium/patches/riscv-crashpad.patch b/srcpkgs/chromium/patches/riscv-crashpad.patch new file mode 100644 index 0000000000000..cc2c37791ace5 --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-crashpad.patch @@ -0,0 +1,777 @@ +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/minidump/minidump_context.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context.h +@@ -592,6 +592,41 @@ struct MinidumpContextMIPS64 { + uint64_t fir; + }; + ++//! \brief 64bit RISC-V-specifc flags for MinidumpContextRISCV64::context_flags. ++//! Based on minidump_cpu_riscv64.h from breakpad ++enum MinidumpContextRISCV64Flags : uint32_t { ++ //! \brief Identifies the context structure as RISCV64. ++ kMinidumpContextRISCV64 = 0x00080000, ++ ++ //! \brief Indicates the validity of integer registers. ++ //! ++ //! Registers `x1`-`x31` and pc are valid. ++ kMinidumpContextRISCV64Integer = kMinidumpContextRISCV64 | 0x00000002, ++ ++ //! \brief Indicates the validity of floating point registers. ++ //! ++ //! Floating point registers `f0`-`f31`, and `fcsr` are valid ++ kMinidumpContextRISCV64FloatingPoint = kMinidumpContextRISCV64 | 0x00000004, ++ ++ //! \brief Indicates the validity of all registers. ++ kMinidumpContextRISCV64All = kMinidumpContextRISCV64Integer | ++ kMinidumpContextRISCV64FloatingPoint, ++}; ++ ++//! \brief A 64bit RISCV CPU context (register state) carried in a minidump file. ++struct MinidumpContextRISCV64 { ++ uint64_t context_flags; ++ ++ //! \brief General purpose registers. ++ uint64_t regs[32]; ++ ++ //! \brief FPU registers. ++ uint64_t fpregs[32]; ++ ++ //! \brief FPU status register. ++ uint64_t fcsr; ++}; ++ + } // namespace crashpad + + #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc +@@ -102,6 +102,13 @@ MinidumpContextWriter::CreateFromSnapsho + break; + } + ++ case kCPUArchitectureRISCV64: { ++ context = std::make_unique(); ++ reinterpret_cast(context.get()) ++ ->InitializeFromSnapshot(context_snapshot->riscv64); ++ break; ++ } ++ + default: { + LOG(ERROR) << "unknown context architecture " + << context_snapshot->architecture; +@@ -453,5 +460,42 @@ size_t MinidumpContextMIPS64Writer::Cont + DCHECK_GE(state(), kStateFrozen); + return sizeof(context_); + } ++ ++MinidumpContextRISCV64Writer::MinidumpContextRISCV64Writer() ++ : MinidumpContextWriter(), context_() { ++ context_.context_flags = kMinidumpContextRISCV64; ++} ++ ++MinidumpContextRISCV64Writer::~MinidumpContextRISCV64Writer() = default; ++ ++void MinidumpContextRISCV64Writer::InitializeFromSnapshot( ++ const CPUContextRISCV64* context_snapshot) { ++ DCHECK_EQ(state(), kStateMutable); ++ DCHECK_EQ(context_.context_flags, kMinidumpContextRISCV64); ++ ++ context_.context_flags = kMinidumpContextRISCV64All; ++ ++ static_assert(sizeof(context_.regs) == sizeof(context_snapshot->regs), ++ "GPRs size mismatch"); ++ memcpy(context_.regs, context_snapshot->regs, sizeof(context_.regs)); ++ ++ static_assert(sizeof(context_.fpregs) == sizeof(context_snapshot->fpregs), ++ "FPRs size mismatch"); ++ memcpy(context_.fpregs, ++ context_snapshot->fpregs, ++ sizeof(context_.fpregs)); ++ context_.fcsr = context_snapshot->fcsr; ++} ++ ++bool MinidumpContextRISCV64Writer::WriteObject( ++ FileWriterInterface* file_writer) { ++ DCHECK_EQ(state(), kStateWritable); ++ return file_writer->Write(&context_, sizeof(context_)); ++} ++ ++size_t MinidumpContextRISCV64Writer::ContextSize() const { ++ DCHECK_GE(state(), kStateFrozen); ++ return sizeof(context_); ++} + + } // namespace crashpad +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context_writer.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/minidump/minidump_context_writer.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_context_writer.h +@@ -330,6 +330,49 @@ class MinidumpContextMIPS64Writer final + MinidumpContextMIPS64 context_; + }; + ++//! \brief The writer for a MinidumpContextRISCV64 structure in a minidump file. ++class MinidumpContextRISCV64Writer final : public MinidumpContextWriter { ++ public: ++ MinidumpContextRISCV64Writer(); ++ ++ MinidumpContextRISCV64Writer(const MinidumpContextRISCV64Writer&) = delete; ++ MinidumpContextRISCV64Writer& operator=(const MinidumpContextRISCV64Writer&) = ++ delete; ++ ++ ~MinidumpContextRISCV64Writer() override; ++ ++ //! \brief Initializes the MinidumpContextRISCV based on \a context_snapshot. ++ //! ++ //! \param[in] context_snapshot The context snapshot to use as source data. ++ //! ++ //! \note Valid in #kStateMutable. No mutation of context() may be done before ++ //! calling this method, and it is not normally necessary to alter ++ //! context() after calling this method. ++ void InitializeFromSnapshot(const CPUContextRISCV64* context_snapshot); ++ ++ //! \brief Returns a pointer to the context structure that this object will ++ //! write. ++ //! ++ //! \attention This returns a non-`const` pointer to this object’s private ++ //! data so that a caller can populate the context structure directly. ++ //! This is done because providing setter interfaces to each field in the ++ //! context structure would be unwieldy and cumbersome. Care must be taken ++ //! to populate the context structure correctly. The context structure ++ //! must only be modified while this object is in the #kStateMutable ++ //! state. ++ MinidumpContextRISCV64* context() { return &context_; } ++ ++ protected: ++ // MinidumpWritable: ++ bool WriteObject(FileWriterInterface* file_writer) override; ++ ++ // MinidumpContextWriter: ++ size_t ContextSize() const override; ++ ++ private: ++ MinidumpContextRISCV64 context_; ++}; ++ + } // namespace crashpad + + #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_WRITER_H_ +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc +@@ -135,6 +135,10 @@ std::string MinidumpMiscInfoDebugBuildSt + static constexpr char kCPU[] = "mips"; + #elif defined(ARCH_CPU_MIPS64EL) + static constexpr char kCPU[] = "mips64"; ++#elif defined(ARCH_CPU_RISCV32) ++ static constexpr char kCPU[] = "riscv32"; ++#elif defined(ARCH_CPU_RISCV64) ++ static constexpr char kCPU[] = "riscv64"; + #else + #error define kCPU for this CPU + #endif +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/capture_memory.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/capture_memory.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/capture_memory.cc +@@ -112,6 +112,16 @@ void CaptureMemory::PointedToByContext(c + for (size_t i = 0; i < std::size(context.mipsel->regs); ++i) { + MaybeCaptureMemoryAround(delegate, context.mipsel->regs[i]); + } ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ if (context.architecture == kCPUArchitectureRISCV64) { ++ for (size_t i = 0; i < std::size(context.riscv64->regs); ++i) { ++ MaybeCaptureMemoryAround(delegate, context.riscv64->regs[i]); ++ } ++ } else { ++ for (size_t i = 0; i < std::size(context.riscv32->regs); ++i) { ++ MaybeCaptureMemoryAround(delegate, context.riscv32->regs[i]); ++ } ++ } + #else + #error Port. + #endif +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_architecture.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/cpu_architecture.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_architecture.h +@@ -43,7 +43,13 @@ enum CPUArchitecture { + kCPUArchitectureMIPSEL, + + //! \brief 64-bit MIPSEL. +- kCPUArchitectureMIPS64EL ++ kCPUArchitectureMIPS64EL, ++ ++ //! \brief 32-bit RISCV. ++ kCPUArchitectureRISCV32, ++ ++ //! \brief 64-bit RISCV. ++ kCPUArchitectureRISCV64 + }; + + } // namespace crashpad +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_context.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/cpu_context.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_context.cc +@@ -197,10 +197,12 @@ bool CPUContext::Is64Bit() const { + case kCPUArchitectureX86_64: + case kCPUArchitectureARM64: + case kCPUArchitectureMIPS64EL: ++ case kCPUArchitectureRISCV64: + return true; + case kCPUArchitectureX86: + case kCPUArchitectureARM: + case kCPUArchitectureMIPSEL: ++ case kCPUArchitectureRISCV32: + return false; + default: + NOTREACHED(); +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_context.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/cpu_context.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/cpu_context.h +@@ -352,6 +352,20 @@ struct CPUContextMIPS64 { + uint64_t fir; + }; + ++//! \brief A context structure carrying RISCV32 CPU state. ++struct CPUContextRISCV32 { ++ uint32_t regs[32]; ++ uint64_t fpregs[32]; ++ uint32_t fcsr; ++}; ++ ++//! \brief A context structure carrying RISCV64 CPU state. ++struct CPUContextRISCV64 { ++ uint64_t regs[32]; ++ uint64_t fpregs[32]; ++ uint32_t fcsr; ++}; ++ + //! \brief A context structure capable of carrying the context of any supported + //! CPU architecture. + struct CPUContext { +@@ -382,6 +396,8 @@ struct CPUContext { + CPUContextARM64* arm64; + CPUContextMIPS* mipsel; + CPUContextMIPS64* mips64; ++ CPUContextRISCV32* riscv32; ++ CPUContextRISCV64* riscv64; + }; + }; + +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.cc +@@ -266,6 +266,30 @@ void InitializeCPUContextARM64_OnlyFPSIM + context->fpcr = float_context.fpcr; + } + ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ ++template ++void InitializeCPUContextRISCV( ++ const typename Traits::SignalThreadContext& thread_context, ++ const typename Traits::SignalFloatContext& float_context, ++ typename Traits::CPUContext* context) { ++ static_assert(sizeof(context->regs) == sizeof(thread_context), ++ "registers size mismatch"); ++ static_assert(sizeof(context->fpregs) == sizeof(float_context.f), ++ "fp registers size mismatch"); ++ memcpy(&context->regs, &thread_context, sizeof(context->regs)); ++ memcpy(&context->fpregs, &float_context.f, sizeof(context->fpregs)); ++ context->fcsr = float_context.fcsr; ++} ++template void InitializeCPUContextRISCV( ++ const ContextTraits32::SignalThreadContext& thread_context, ++ const ContextTraits32::SignalFloatContext& float_context, ++ ContextTraits32::CPUContext* context); ++template void InitializeCPUContextRISCV( ++ const ContextTraits64::SignalThreadContext& thread_context, ++ const ContextTraits64::SignalFloatContext& float_context, ++ ContextTraits64::CPUContext* context); ++ + #endif // ARCH_CPU_X86_FAMILY + + } // namespace internal +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h +@@ -174,6 +174,22 @@ void InitializeCPUContextMIPS( + + #endif // ARCH_CPU_MIPS_FAMILY || DOXYGEN + ++#if defined(ARCH_CPU_RISCV_FAMILY) || DOXYGEN ++ ++//! \brief Initializes a CPUContextRISCV structure from native context ++//! structures on Linux. ++//! ++//! \param[in] thread_context The native thread context. ++//! \param[in] float_context The native float context. ++//! \param[out] context The CPUContextRISCV structure to initialize. ++template ++void InitializeCPUContextRISCV( ++ const typename Traits::SignalThreadContext& thread_context, ++ const typename Traits::SignalFloatContext& float_context, ++ typename Traits::CPUContext* context); ++ ++#endif // ARCH_CPU_RISCV_FAMILY || DOXYGEN ++ + } // namespace internal + } // namespace crashpad + +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc +@@ -325,6 +325,61 @@ bool ExceptionSnapshotLinux::ReadContext + reader, context_address, context_.mips64); + } + ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ ++template ++static bool ReadContext(ProcessReaderLinux* reader, ++ LinuxVMAddress context_address, ++ typename Traits::CPUContext* dest_context) { ++ const ProcessMemory* memory = reader->Memory(); ++ ++ LinuxVMAddress gregs_address = context_address + ++ offsetof(UContext, mcontext) + ++ offsetof(typename Traits::MContext, gregs); ++ ++ typename Traits::SignalThreadContext thread_context; ++ if (!memory->Read(gregs_address, sizeof(thread_context), &thread_context)) { ++ LOG(ERROR) << "Couldn't read gregs"; ++ return false; ++ } ++ ++ LinuxVMAddress fpregs_address = context_address + ++ offsetof(UContext, mcontext) + ++ offsetof(typename Traits::MContext, fpregs); ++ ++ typename Traits::SignalFloatContext fp_context; ++ if (!memory->Read(fpregs_address, sizeof(fp_context), &fp_context)) { ++ LOG(ERROR) << "Couldn't read fpregs"; ++ return false; ++ } ++ ++ InitializeCPUContextRISCV(thread_context, fp_context, dest_context); ++ ++ return true; ++} ++ ++template <> ++bool ExceptionSnapshotLinux::ReadContext( ++ ProcessReaderLinux* reader, ++ LinuxVMAddress context_address) { ++ context_.architecture = kCPUArchitectureRISCV32; ++ context_.riscv32 = &context_union_.riscv32; ++ ++ return internal::ReadContext( ++ reader, context_address, context_.riscv32); ++} ++ ++template <> ++bool ExceptionSnapshotLinux::ReadContext( ++ ProcessReaderLinux* reader, ++ LinuxVMAddress context_address) { ++ context_.architecture = kCPUArchitectureRISCV64; ++ context_.riscv64 = &context_union_.riscv64; ++ ++ return internal::ReadContext( ++ reader, context_address, context_.riscv64); ++} ++ + #endif // ARCH_CPU_X86_FAMILY + + bool ExceptionSnapshotLinux::Initialize( +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h +@@ -89,6 +89,9 @@ class ExceptionSnapshotLinux final : pub + #elif defined(ARCH_CPU_MIPS_FAMILY) + CPUContextMIPS mipsel; + CPUContextMIPS64 mips64; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ CPUContextRISCV32 riscv32; ++ CPUContextRISCV64 riscv64; + #endif + } context_union_; + CPUContext context_; +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc +@@ -108,6 +108,9 @@ void ProcessReaderLinux::Thread::Initial + #elif defined(ARCH_CPU_MIPS_FAMILY) + stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.regs[29] + : thread_info.thread_context.t32.regs[29]; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.sp ++ : thread_info.thread_context.t32.sp; + #else + #error Port. + #endif +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/signal_context.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/signal_context.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/signal_context.h +@@ -422,6 +422,67 @@ static_assert(offsetof(UContext ++struct UContext { ++ typename Traits::ULong flags; ++ typename Traits::Address link; ++ SignalStack stack; ++ Sigset sigmask; ++ char padding[128 - sizeof(sigmask)]; ++ typename Traits::Char_64Only padding2[8]; ++ typename Traits::MContext mcontext; ++}; ++ ++#if defined(ARCH_CPU_RISCV32) ++static_assert(offsetof(UContext, mcontext) == ++ offsetof(ucontext_t, uc_mcontext), ++ "context offset mismatch"); ++static_assert(offsetof(UContext, mcontext.gregs) == ++ offsetof(ucontext_t, uc_mcontext.__gregs), ++ "context offset mismatch"); ++static_assert(offsetof(UContext, mcontext.fpregs) == ++ offsetof(ucontext_t, uc_mcontext.__fpregs), ++ "context offset mismatch"); ++#elif defined(ARCH_CPU_RISCV64) ++static_assert(offsetof(UContext, mcontext) == ++ offsetof(ucontext_t, uc_mcontext), ++ "context offset mismatch"); ++static_assert(offsetof(UContext, mcontext.gregs) == ++ offsetof(ucontext_t, uc_mcontext.__gregs), ++ "context offset mismatch"); ++static_assert(offsetof(UContext, mcontext.fpregs) == ++ offsetof(ucontext_t, uc_mcontext.__fpregs), ++ "context offset mismatch"); ++#endif ++ + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc +@@ -205,6 +205,9 @@ CPUArchitecture SystemSnapshotLinux::Get + #elif defined(ARCH_CPU_MIPS_FAMILY) + return process_reader_->Is64Bit() ? kCPUArchitectureMIPS64EL + : kCPUArchitectureMIPSEL; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ return process_reader_->Is64Bit() ? kCPUArchitectureRISCV64 ++ : kCPUArchitectureRISCV32; + #else + #error port to your architecture + #endif +@@ -220,6 +223,9 @@ uint32_t SystemSnapshotLinux::CPURevisio + #elif defined(ARCH_CPU_MIPS_FAMILY) + // Not implementable on MIPS + return 0; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Not implementable on RISCV ++ return 0; + #else + #error port to your architecture + #endif +@@ -240,6 +246,9 @@ std::string SystemSnapshotLinux::CPUVend + #elif defined(ARCH_CPU_MIPS_FAMILY) + // Not implementable on MIPS + return std::string(); ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Not implementable on RISCV ++ return std::string(); + #else + #error port to your architecture + #endif +@@ -373,6 +382,9 @@ bool SystemSnapshotLinux::NXEnabled() co + #elif defined(ARCH_CPU_MIPS_FAMILY) + // Not implementable on MIPS + return false; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Not implementable on RISCV ++ return false; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc +@@ -189,6 +189,22 @@ bool ThreadSnapshotLinux::Initialize( + thread.thread_info.float_context.f32, + context_.mipsel); + } ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ if (process_reader->Is64Bit()) { ++ context_.architecture = kCPUArchitectureRISCV64; ++ context_.riscv64 = &context_union_.riscv64; ++ InitializeCPUContextRISCV( ++ thread.thread_info.thread_context.t64, ++ thread.thread_info.float_context.f64, ++ context_.riscv64); ++ } else { ++ context_.architecture = kCPUArchitectureRISCV32; ++ context_.riscv32 = &context_union_.riscv32; ++ InitializeCPUContextRISCV( ++ thread.thread_info.thread_context.t32, ++ thread.thread_info.float_context.f32, ++ context_.riscv32); ++ } + #else + #error Port. + #endif +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h +@@ -73,6 +73,9 @@ class ThreadSnapshotLinux final : public + #elif defined(ARCH_CPU_MIPS_FAMILY) + CPUContextMIPS mipsel; + CPUContextMIPS64 mips64; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ CPUContextRISCV32 riscv32; ++ CPUContextRISCV64 riscv64; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/util/linux/ptracer.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/util/linux/ptracer.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/util/linux/ptracer.cc +@@ -398,6 +398,51 @@ bool GetThreadArea64(pid_t tid, + return true; + } + ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ ++template ++bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) { ++ iovec iov; ++ iov.iov_base = dest; ++ iov.iov_len = sizeof(*dest); ++ if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast(set), &iov) != 0) { ++ PLOG_IF(ERROR, can_log) << "ptrace"; ++ return false; ++ } ++ if (iov.iov_len != sizeof(*dest)) { ++ LOG_IF(ERROR, can_log) << "Unexpected registers size"; ++ return false; ++ } ++ return true; ++} ++ ++bool GetFloatingPointRegisters32(pid_t tid, ++ FloatContext* context, ++ bool can_log) { ++ return false; ++} ++ ++bool GetFloatingPointRegisters64(pid_t tid, ++ FloatContext* context, ++ bool can_log) { ++ return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log); ++} ++ ++bool GetThreadArea32(pid_t tid, ++ const ThreadContext& context, ++ LinuxVMAddress* address, ++ bool can_log) { ++ return false; ++} ++ ++bool GetThreadArea64(pid_t tid, ++ const ThreadContext& context, ++ LinuxVMAddress* address, ++ bool can_log) { ++ *address = context.t64.tp; ++ return true; ++} ++ + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/util/linux/thread_info.h +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/util/linux/thread_info.h ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/util/linux/thread_info.h +@@ -79,6 +79,40 @@ union ThreadContext { + uint32_t cp0_status; + uint32_t cp0_cause; + uint32_t padding1_; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Reflects user_regs_struct in asm/ptrace.h. ++ uint32_t pc; ++ uint32_t ra; ++ uint32_t sp; ++ uint32_t gp; ++ uint32_t tp; ++ uint32_t t0; ++ uint32_t t1; ++ uint32_t t2; ++ uint32_t s0; ++ uint32_t s1; ++ uint32_t a0; ++ uint32_t a1; ++ uint32_t a2; ++ uint32_t a3; ++ uint32_t a4; ++ uint32_t a5; ++ uint32_t a6; ++ uint32_t a7; ++ uint32_t s2; ++ uint32_t s3; ++ uint32_t s4; ++ uint32_t s5; ++ uint32_t s6; ++ uint32_t s7; ++ uint32_t s8; ++ uint32_t s9; ++ uint32_t s10; ++ uint32_t s11; ++ uint32_t t3; ++ uint32_t t4; ++ uint32_t t5; ++ uint32_t t6; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -132,6 +166,40 @@ union ThreadContext { + uint64_t cp0_badvaddr; + uint64_t cp0_status; + uint64_t cp0_cause; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Reflects user_regs_struct in asm/ptrace.h. ++ uint64_t pc; ++ uint64_t ra; ++ uint64_t sp; ++ uint64_t gp; ++ uint64_t tp; ++ uint64_t t0; ++ uint64_t t1; ++ uint64_t t2; ++ uint64_t s0; ++ uint64_t s1; ++ uint64_t a0; ++ uint64_t a1; ++ uint64_t a2; ++ uint64_t a3; ++ uint64_t a4; ++ uint64_t a5; ++ uint64_t a6; ++ uint64_t a7; ++ uint64_t s2; ++ uint64_t s3; ++ uint64_t s4; ++ uint64_t s5; ++ uint64_t s6; ++ uint64_t s7; ++ uint64_t s8; ++ uint64_t s9; ++ uint64_t s10; ++ uint64_t s11; ++ uint64_t t3; ++ uint64_t t4; ++ uint64_t t5; ++ uint64_t t6; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -143,11 +211,12 @@ union ThreadContext { + using NativeThreadContext = user_regs; + #elif defined(ARCH_CPU_MIPS_FAMILY) + // No appropriate NativeThreadsContext type available for MIPS ++#elif defined(ARCH_CPU_RISCV_FAMILY) + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 + +-#if !defined(ARCH_CPU_MIPS_FAMILY) ++#if !defined(ARCH_CPU_MIPS_FAMILY) && !defined(ARCH_CPU_RISCV_FAMILY) + #if defined(ARCH_CPU_32_BITS) + static_assert(sizeof(t32_t) == sizeof(NativeThreadContext), "Size mismatch"); + #else // ARCH_CPU_64_BITS +@@ -218,6 +287,9 @@ union FloatContext { + } fpregs[32]; + uint32_t fpcsr; + uint32_t fpu_id; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ uint64_t f[32]; ++ uint32_t fcsr; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -252,6 +324,9 @@ union FloatContext { + double fpregs[32]; + uint32_t fpcsr; + uint32_t fpu_id; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ uint64_t f[32]; ++ uint32_t fcsr; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -281,6 +356,7 @@ union FloatContext { + static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch"); + #elif defined(ARCH_CPU_MIPS_FAMILY) + // No appropriate floating point context native type for available MIPS. ++#elif defined(ARCH_CPU_RISCV_FAMILY) + #else + #error Port. + #endif // ARCH_CPU_X86 +Index: chromium-102.0.5005.61/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc +=================================================================== +--- chromium-102.0.5005.61.orig/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc ++++ chromium-102.0.5005.61/third_party/crashpad/crashpad/util/net/http_transport_libcurl.cc +@@ -237,6 +237,8 @@ std::string UserAgent() { + #elif defined(ARCH_CPU_BIG_ENDIAN) + static constexpr char arch[] = "aarch64_be"; + #endif ++#elif defined(ARCH_CPU_RISCV64) ++ static constexpr char arch[] = "riscv64"; + #else + #error Port + #endif diff --git a/srcpkgs/chromium/patches/riscv-dav1d.patch b/srcpkgs/chromium/patches/riscv-dav1d.patch new file mode 100644 index 0000000000000..d5c8058b41e24 --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-dav1d.patch @@ -0,0 +1,43 @@ +Index: chromium-102.0.5005.61/third_party/dav1d/config/linux/riscv64/config.h +=================================================================== +--- /dev/null ++++ chromium-102.0.5005.61/third_party/dav1d/config/linux/riscv64/config.h +@@ -0,0 +1,38 @@ ++/* ++ * Autogenerated by the Meson build system. ++ * Do not edit, your changes will be lost. ++ */ ++ ++#pragma once ++ ++#define ARCH_AARCH64 0 ++ ++#define ARCH_ARM 0 ++ ++#define ARCH_PPC64LE 0 ++ ++#define ARCH_X86 0 ++ ++#define ARCH_X86_32 0 ++ ++#define ARCH_X86_64 0 ++ ++#define CONFIG_16BPC 1 ++ ++#define CONFIG_8BPC 1 ++ ++// #define CONFIG_LOG 1 -- Logging is controlled by Chromium ++ ++#define ENDIANNESS_BIG 0 ++ ++#define HAVE_ASM 0 ++ ++#define HAVE_AS_FUNC 0 ++ ++#define HAVE_CLOCK_GETTIME 1 ++ ++#define HAVE_GETAUXVAL 1 ++ ++#define HAVE_POSIX_MEMALIGN 1 ++ ++#define HAVE_UNISTD_H 1 diff --git a/srcpkgs/chromium/patches/riscv-sandbox.patch.old b/srcpkgs/chromium/patches/riscv-sandbox.patch.old new file mode 100644 index 0000000000000..18e080fd25bda --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-sandbox.patch.old @@ -0,0 +1,1942 @@ +Index: chromium-103.0.5060.134/sandbox/features.gni +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/features.gni ++++ chromium-103.0.5060.134/sandbox/features.gni +@@ -9,7 +9,8 @@ + use_seccomp_bpf = (is_linux || is_chromeos || is_android) && + (current_cpu == "x86" || current_cpu == "x64" || + current_cpu == "arm" || current_cpu == "arm64" || +- current_cpu == "mipsel" || current_cpu == "mips64el") ++ current_cpu == "mipsel" || current_cpu == "mips64el" || ++ current_cpu == "riscv64") + + # SSBD (Speculative Store Bypass Disable) is a mitigation of Spectre Variant 4. + # As Spectre Variant 4 can be mitigated by site isolation, opt-out SSBD on site +Index: chromium-103.0.5060.134/sandbox/linux/bpf_dsl/linux_syscall_ranges.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/bpf_dsl/linux_syscall_ranges.h ++++ chromium-103.0.5060.134/sandbox/linux/bpf_dsl/linux_syscall_ranges.h +@@ -56,6 +56,12 @@ + #define MAX_PUBLIC_SYSCALL __NR_syscalls + #define MAX_SYSCALL MAX_PUBLIC_SYSCALL + ++#elif defined(__riscv) ++ ++#define MIN_SYSCALL 0u ++#define MAX_PUBLIC_SYSCALL 1024u ++#define MAX_SYSCALL MAX_PUBLIC_SYSCALL ++ + #else + #error "Unsupported architecture" + #endif +Index: chromium-103.0.5060.134/sandbox/linux/bpf_dsl/seccomp_macros.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/bpf_dsl/seccomp_macros.h ++++ chromium-103.0.5060.134/sandbox/linux/bpf_dsl/seccomp_macros.h +@@ -343,6 +343,46 @@ struct regs_struct { + #define SECCOMP_PT_PARM4(_regs) (_regs).regs[3] + #define SECCOMP_PT_PARM5(_regs) (_regs).regs[4] + #define SECCOMP_PT_PARM6(_regs) (_regs).regs[5] ++ ++#elif defined(__riscv) ++struct regs_struct { ++ unsigned long regs[32]; ++}; ++ ++#define SECCOMP_ARCH AUDIT_ARCH_RISCV64 ++ ++#define SECCOMP_REG(_ctx, _reg) ((_ctx)->uc_mcontext.__gregs[_reg]) ++ ++#define SECCOMP_RESULT(_ctx) SECCOMP_REG(_ctx, REG_A0) ++#define SECCOMP_SYSCALL(_ctx) SECCOMP_REG(_ctx, REG_A0+7) ++#define SECCOMP_IP(_ctx) (_ctx)->uc_mcontext.__gregs[REG_PC] ++#define SECCOMP_PARM1(_ctx) SECCOMP_REG(_ctx, REG_A0) ++#define SECCOMP_PARM2(_ctx) SECCOMP_REG(_ctx, REG_A0+1) ++#define SECCOMP_PARM3(_ctx) SECCOMP_REG(_ctx, REG_A0+2) ++#define SECCOMP_PARM4(_ctx) SECCOMP_REG(_ctx, REG_A0+3) ++#define SECCOMP_PARM5(_ctx) SECCOMP_REG(_ctx, REG_A0+4) ++#define SECCOMP_PARM6(_ctx) SECCOMP_REG(_ctx, REG_A0+5) ++ ++#define SECCOMP_NR_IDX (offsetof(struct arch_seccomp_data, nr)) ++#define SECCOMP_ARCH_IDX (offsetof(struct arch_seccomp_data, arch)) ++#define SECCOMP_IP_MSB_IDX \ ++ (offsetof(struct arch_seccomp_data, instruction_pointer) + 4) ++#define SECCOMP_IP_LSB_IDX \ ++ (offsetof(struct arch_seccomp_data, instruction_pointer) + 0) ++#define SECCOMP_ARG_MSB_IDX(nr) \ ++ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 4) ++#define SECCOMP_ARG_LSB_IDX(nr) \ ++ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 0) ++ ++#define SECCOMP_PT_RESULT(_regs) (_regs).regs[REG_A0] ++#define SECCOMP_PT_SYSCALL(_regs) (_regs).regs[REG_A0+7] ++#define SECCOMP_PT_IP(_regs) (_regs).regs[REG_PC] ++#define SECCOMP_PT_PARM1(_regs) (_regs).regs[REG_A0] ++#define SECCOMP_PT_PARM2(_regs) (_regs).regs[REG_A0+1] ++#define SECCOMP_PT_PARM3(_regs) (_regs).regs[REG_A0+2] ++#define SECCOMP_PT_PARM4(_regs) (_regs).regs[REG_A0+3] ++#define SECCOMP_PT_PARM5(_regs) (_regs).regs[REG_A0+4] ++#define SECCOMP_PT_PARM6(_regs) (_regs).regs[REG_A0+5] + #else + #error Unsupported target platform + +Index: chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc ++++ chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc +@@ -61,6 +61,9 @@ bool IsBaselinePolicyAllowed(int sysno) + #if defined(__mips__) + SyscallSets::IsMipsPrivate(sysno) || + #endif ++#if defined(__riscv) ++ SyscallSets::IsRiscvPrivate(sysno) || ++#endif + SyscallSets::IsAllowedOperationOnFd(sysno); + // clang-format on + } +@@ -198,7 +201,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + return RestrictFcntlCommands(); + #endif + +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + // fork() is never used as a system call (clone() is used instead), but we + // have seen it in fallback code on Android. + if (sysno == __NR_fork) { +@@ -253,7 +256,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + } + + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + if (sysno == __NR_mmap) + return RestrictMmapFlags(); + #endif +@@ -274,7 +277,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + return RestrictPrctl(); + + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + if (sysno == __NR_socketpair) { + // Only allow AF_UNIX, PF_UNIX. Crash if anything else is seen. + static_assert(AF_UNIX == PF_UNIX, +Index: chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc ++++ chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc +@@ -37,6 +37,7 @@ + + #if (BUILDFLAG(IS_LINUX) || BUILDFLAG(IS_CHROMEOS_LACROS)) && \ + !defined(__arm__) && !defined(__aarch64__) && \ ++ !defined(__riscv) && \ + !defined(PTRACE_GET_THREAD_AREA) + // Also include asm/ptrace-abi.h since ptrace.h in older libc (for instance + // the one in Ubuntu 16.04 LTS) is missing PTRACE_GET_THREAD_AREA. +@@ -443,7 +444,7 @@ ResultExpr RestrictPtrace() { + #endif + return Switch(request) + .CASES(( +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + PTRACE_GETREGS, PTRACE_GETFPREGS, PTRACE_GET_THREAD_AREA, + PTRACE_GETREGSET, + #endif +Index: chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc ++++ chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc +@@ -103,7 +103,7 @@ bool SyscallSets::IsUmask(int sysno) { + // Both EPERM and ENOENT are valid errno unless otherwise noted in comment. + bool SyscallSets::IsFileSystem(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_access: // EPERM not a valid errno. + case __NR_chmod: + case __NR_chown: +@@ -136,7 +136,7 @@ bool SyscallSets::IsFileSystem(int sysno + case __NR_faccessat2: + case __NR_fchmodat: + case __NR_fchownat: // Should be called chownat ? +-#if defined(__x86_64__) || defined(__aarch64__) ++#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv) + case __NR_newfstatat: // fstatat(). EPERM not a valid errno. + #elif defined(__i386__) || defined(__arm__) || \ + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) +@@ -226,7 +226,7 @@ bool SyscallSets::IsAllowedFileSystemAcc + case __NR_oldfstat: + #endif + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_sync_file_range: // EPERM not a valid errno. + #elif defined(__arm__) + case __NR_arm_sync_file_range: // EPERM not a valid errno. +@@ -245,7 +245,7 @@ bool SyscallSets::IsDeniedFileSystemAcce + #if defined(__i386__) || defined(__arm__) + case __NR_fchown32: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getdents: // EPERM not a valid errno. + #endif + case __NR_getdents64: // EPERM not a valid errno. +@@ -324,7 +324,7 @@ bool SyscallSets::IsProcessPrivilegeChan + bool SyscallSets::IsProcessGroupOrSession(int sysno) { + switch (sysno) { + case __NR_setpgid: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getpgrp: + #endif + case __NR_setsid: +@@ -358,7 +358,7 @@ bool SyscallSets::IsAllowedSignalHandlin + case __NR_rt_sigqueueinfo: + case __NR_rt_sigsuspend: + case __NR_rt_tgsigqueueinfo: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_signalfd: + #endif + case __NR_signalfd4: +@@ -382,12 +382,12 @@ bool SyscallSets::IsAllowedOperationOnFd + switch (sysno) { + case __NR_close: + case __NR_dup: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_dup2: + #endif + case __NR_dup3: + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_shutdown: + #endif + return true; +@@ -426,7 +426,7 @@ bool SyscallSets::IsAllowedProcessStartO + return true; + case __NR_clone: // Should be parameter-restricted. + case __NR_setns: // Privileged. +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_fork: + #endif + #if defined(__i386__) || defined(__x86_64__) +@@ -437,7 +437,7 @@ bool SyscallSets::IsAllowedProcessStartO + #endif + case __NR_set_tid_address: + case __NR_unshare: +-#if !defined(__mips__) && !defined(__aarch64__) ++#if !defined(__mips__) && !defined(__aarch64__) && !defined(__riscv) + case __NR_vfork: + #endif + default: +@@ -462,7 +462,7 @@ bool SyscallSets::IsAllowedFutex(int sys + + bool SyscallSets::IsAllowedEpoll(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_epoll_create: + case __NR_epoll_wait: + #endif +@@ -483,14 +483,14 @@ bool SyscallSets::IsAllowedEpoll(int sys + + bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_pipe: + #endif + case __NR_pipe2: + return true; + default: + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_socketpair: // We will want to inspect its argument. + #endif + return false; +@@ -500,7 +500,7 @@ bool SyscallSets::IsAllowedGetOrModifySo + bool SyscallSets::IsDeniedGetOrModifySocket(int sysno) { + switch (sysno) { + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_accept: + case __NR_accept4: + case __NR_bind: +@@ -554,7 +554,7 @@ bool SyscallSets::IsAllowedAddressSpaceA + case __NR_mincore: + case __NR_mlockall: + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_mmap: + #endif + #if defined(__i386__) || defined(__arm__) || \ +@@ -587,7 +587,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) + case __NR__llseek: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_poll: + #endif + case __NR_ppoll: +@@ -608,7 +608,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + case __NR_recv: + #endif + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_recvfrom: // Could specify source. + case __NR_recvmsg: // Could specify source. + #endif +@@ -623,7 +623,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + case __NR_send: + #endif + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_sendmsg: // Could specify destination. + case __NR_sendto: // Could specify destination. + #endif +@@ -672,7 +672,7 @@ bool SyscallSets::IsSeccomp(int sysno) { + bool SyscallSets::IsAllowedBasicScheduler(int sysno) { + switch (sysno) { + case __NR_sched_yield: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_pause: + #endif + case __NR_nanosleep: +@@ -756,7 +756,7 @@ bool SyscallSets::IsNuma(int sysno) { + case __NR_getcpu: + case __NR_mbind: + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_migrate_pages: + #endif + case __NR_move_pages: +@@ -791,7 +791,7 @@ bool SyscallSets::IsGlobalProcessEnviron + switch (sysno) { + case __NR_acct: // Privileged. + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_getrlimit: + #endif + #if defined(__i386__) || defined(__arm__) +@@ -826,7 +826,7 @@ bool SyscallSets::IsDebug(int sysno) { + + bool SyscallSets::IsGlobalSystemStatus(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR__sysctl: + case __NR_sysfs: + #endif +@@ -844,7 +844,7 @@ bool SyscallSets::IsGlobalSystemStatus(i + + bool SyscallSets::IsEventFd(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_eventfd: + #endif + case __NR_eventfd2: +@@ -896,7 +896,8 @@ bool SyscallSets::IsKeyManagement(int sy + } + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + bool SyscallSets::IsSystemVSemaphores(int sysno) { + switch (sysno) { + case __NR_semctl: +@@ -916,7 +917,8 @@ bool SyscallSets::IsSystemVSemaphores(in + + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ + defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + // These give a lot of ambient authority and bypass the setuid sandbox. + bool SyscallSets::IsSystemVSharedMemory(int sysno) { + switch (sysno) { +@@ -932,7 +934,8 @@ bool SyscallSets::IsSystemVSharedMemory( + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + bool SyscallSets::IsSystemVMessageQueue(int sysno) { + switch (sysno) { + case __NR_msgctl: +@@ -963,7 +966,8 @@ bool SyscallSets::IsSystemVIpc(int sysno + + bool SyscallSets::IsAnySystemV(int sysno) { + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + return IsSystemVMessageQueue(sysno) || IsSystemVSemaphores(sysno) || + IsSystemVSharedMemory(sysno); + #elif defined(__i386__) || \ +@@ -1000,7 +1004,7 @@ bool SyscallSets::IsAdvancedScheduler(in + bool SyscallSets::IsInotify(int sysno) { + switch (sysno) { + case __NR_inotify_add_watch: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_inotify_init: + #endif + case __NR_inotify_init1: +@@ -1138,7 +1142,7 @@ bool SyscallSets::IsMisc(int sysno) { + #if defined(__x86_64__) + case __NR_tuxcall: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_vserver: + #endif + return true; +@@ -1173,6 +1177,17 @@ bool SyscallSets::IsArmPrivate(int sysno + } + #endif // defined(__arm__) + ++#if defined(__riscv) ++bool SyscallSets::IsRiscvPrivate(int sysno) { ++ switch (sysno) { ++ case __NR_riscv_flush_icache: ++ return true; ++ default: ++ return false; ++ } ++} ++#endif // defined(__riscv) ++ + #if defined(__mips__) + bool SyscallSets::IsMipsPrivate(int sysno) { + switch (sysno) { +Index: chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h ++++ chromium-103.0.5060.134/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h +@@ -52,7 +52,7 @@ class SANDBOX_EXPORT SyscallSets { + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + static bool IsNetworkSocketInformation(int sysno); + #endif + +@@ -79,18 +79,21 @@ class SANDBOX_EXPORT SyscallSets { + static bool IsAsyncIo(int sysno); + static bool IsKeyManagement(int sysno); + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + static bool IsSystemVSemaphores(int sysno); + #endif + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ + defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + // These give a lot of ambient authority and bypass the setuid sandbox. + static bool IsSystemVSharedMemory(int sysno); + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + static bool IsSystemVMessageQueue(int sysno); + #endif + +@@ -117,6 +120,9 @@ class SANDBOX_EXPORT SyscallSets { + static bool IsMipsPrivate(int sysno); + static bool IsMipsMisc(int sysno); + #endif // defined(__mips__) ++#if defined(__riscv) ++ static bool IsRiscvPrivate(int sysno); ++#endif + }; + + } // namespace sandbox. +Index: chromium-103.0.5060.134/sandbox/linux/seccomp-bpf/syscall.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/seccomp-bpf/syscall.cc ++++ chromium-103.0.5060.134/sandbox/linux/seccomp-bpf/syscall.cc +@@ -18,7 +18,7 @@ namespace sandbox { + namespace { + + #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ +- defined(ARCH_CPU_MIPS_FAMILY) ++ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY) + // Number that's not currently used by any Linux kernel ABIs. + const int kInvalidSyscallNumber = 0x351d3; + #else +@@ -308,6 +308,28 @@ asm(// We need to be able to tell the ke + "2:ret\n" + ".cfi_endproc\n" + ".size SyscallAsm, .-SyscallAsm\n" ++#elif defined(__riscv) ++ ".text\n" ++ ".align 2\n" ++ ".type SyscallAsm, %function\n" ++ "SyscallAsm:\n" ++ ".cfi_startproc\n" ++ "bgez a0,1f\n" ++ "la a0,2f\n" ++ "j 2f\n" ++ "1:mv a7, a0\n" ++ "ld a0, (t0)\n" ++ "ld a1, 8(t0)\n" ++ "ld a2, 16(t0)\n" ++ "ld a3, 24(t0)\n" ++ "ld a4, 32(t0)\n" ++ "ld a5, 40(t0)\n" ++ "ld a6, 48(t0)\n" ++ // Enter the kernel ++ "scall\n" ++ "2:ret\n" ++ ".cfi_endproc\n" ++ ".size SyscallAsm, .-SyscallAsm\n" + #endif + ); // asm + +@@ -425,6 +447,18 @@ intptr_t Syscall::Call(int nr, + ret = inout; + } + ++#elif defined(__riscv) ++ intptr_t ret; ++ { ++ register intptr_t inout __asm__("a0") = nr; ++ register const intptr_t* data __asm__("t0") = args; ++ asm volatile("jal SyscallAsm\n" ++ : "+r"(inout) ++ : "r"(data) ++ : "memory", "a1", "a2", "a3", "a4", "a5", "a6"); ++ ret = inout; ++ } ++ + #else + #error "Unimplemented architecture" + #endif +Index: chromium-103.0.5060.134/sandbox/linux/services/credentials.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/services/credentials.cc ++++ chromium-103.0.5060.134/sandbox/linux/services/credentials.cc +@@ -80,7 +80,7 @@ bool ChrootToSafeEmptyDir() { + pid_t pid = -1; + alignas(16) char stack_buf[PTHREAD_STACK_MIN]; + #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ +- defined(ARCH_CPU_MIPS_FAMILY) ++ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY) + // The stack grows downward. + void* stack = stack_buf + sizeof(stack_buf); + #else +Index: chromium-103.0.5060.134/sandbox/linux/syscall_broker/broker_process.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/syscall_broker/broker_process.cc ++++ chromium-103.0.5060.134/sandbox/linux/syscall_broker/broker_process.cc +@@ -117,44 +117,46 @@ bool BrokerProcess::IsSyscallBrokerable( + // and are default disabled in Android. So, we should refuse to broker them + // to be consistent with the platform's restrictions. + switch (sysno) { +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_access: + #endif + case __NR_faccessat: + case __NR_faccessat2: + return !fast_check || policy_->allowed_command_set.test(COMMAND_ACCESS); + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_mkdir: + #endif + case __NR_mkdirat: + return !fast_check || policy_->allowed_command_set.test(COMMAND_MKDIR); + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_open: + #endif + case __NR_openat: + return !fast_check || policy_->allowed_command_set.test(COMMAND_OPEN); + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_readlink: + #endif + case __NR_readlinkat: + return !fast_check || policy_->allowed_command_set.test(COMMAND_READLINK); + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_rename: + #endif ++#ifdef __NR_renameat + case __NR_renameat: ++#endif + case __NR_renameat2: + return !fast_check || policy_->allowed_command_set.test(COMMAND_RENAME); + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_rmdir: + return !fast_check || policy_->allowed_command_set.test(COMMAND_RMDIR); + #endif + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_stat: + case __NR_lstat: + #endif +@@ -164,7 +166,7 @@ bool BrokerProcess::IsSyscallBrokerable( + #if defined(__NR_fstatat64) + case __NR_fstatat64: + #endif +-#if defined(__x86_64__) || defined(__aarch64__) ++#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv) + case __NR_newfstatat: + #endif + return !fast_check || policy_->allowed_command_set.test(COMMAND_STAT); +@@ -179,7 +181,7 @@ bool BrokerProcess::IsSyscallBrokerable( + return !fast_check || policy_->allowed_command_set.test(COMMAND_STAT); + #endif + +-#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) ++#if !defined(__aarch64__) && !BUILDFLAG(IS_ANDROID) && !defined(__riscv) + case __NR_unlink: + return !fast_check || policy_->allowed_command_set.test(COMMAND_UNLINK); + #endif +Index: chromium-103.0.5060.134/sandbox/linux/system_headers/linux_seccomp.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/system_headers/linux_seccomp.h ++++ chromium-103.0.5060.134/sandbox/linux/system_headers/linux_seccomp.h +@@ -38,6 +38,9 @@ + #ifndef EM_AARCH64 + #define EM_AARCH64 183 + #endif ++#ifndef EM_RISCV ++#define EM_RISCV 243 ++#endif + + #ifndef __AUDIT_ARCH_64BIT + #define __AUDIT_ARCH_64BIT 0x80000000 +@@ -70,6 +73,9 @@ + #ifndef AUDIT_ARCH_AARCH64 + #define AUDIT_ARCH_AARCH64 (EM_AARCH64 | __AUDIT_ARCH_64BIT | __AUDIT_ARCH_LE) + #endif ++#ifndef AUDIT_ARCH_RISCV64 ++#define AUDIT_ARCH_RISCV64 (EM_RISCV|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) ++#endif + + // For prctl.h + #ifndef PR_SET_SECCOMP +Index: chromium-103.0.5060.134/sandbox/linux/system_headers/linux_signal.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/system_headers/linux_signal.h ++++ chromium-103.0.5060.134/sandbox/linux/system_headers/linux_signal.h +@@ -13,7 +13,7 @@ + // (not undefined, but defined different values and in different memory + // layouts). So, fill the gap here. + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + + #define LINUX_SIGHUP 1 + #define LINUX_SIGINT 2 +Index: chromium-103.0.5060.134/sandbox/linux/system_headers/linux_stat.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/system_headers/linux_stat.h ++++ chromium-103.0.5060.134/sandbox/linux/system_headers/linux_stat.h +@@ -150,7 +150,7 @@ struct kernel_stat { + int st_blocks; + int st_pad4[14]; + }; +-#elif defined(__aarch64__) ++#elif defined(__aarch64__) || defined(__riscv) + struct kernel_stat { + unsigned long st_dev; + unsigned long st_ino; +Index: chromium-103.0.5060.134/sandbox/linux/system_headers/linux_syscalls.h +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/linux/system_headers/linux_syscalls.h ++++ chromium-103.0.5060.134/sandbox/linux/system_headers/linux_syscalls.h +@@ -35,5 +35,9 @@ + #include "sandbox/linux/system_headers/arm64_linux_syscalls.h" + #endif + ++#if defined(__riscv) && __riscv_xlen == 64 ++#include "sandbox/linux/system_headers/riscv64_linux_syscalls.h" ++#endif ++ + #endif // SANDBOX_LINUX_SYSTEM_HEADERS_LINUX_SYSCALLS_H_ + +Index: chromium-103.0.5060.134/sandbox/linux/system_headers/riscv64_linux_syscalls.h +=================================================================== +--- /dev/null ++++ chromium-103.0.5060.134/sandbox/linux/system_headers/riscv64_linux_syscalls.h +@@ -0,0 +1,1222 @@ ++// Copyright 2014 The Chromium Authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ ++#define SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ ++ ++#include ++ ++#if !defined(__NR_io_setup) ++#define __NR_io_setup 0 ++#endif ++ ++#if !defined(__NR_io_destroy) ++#define __NR_io_destroy 1 ++#endif ++ ++#if !defined(__NR_io_submit) ++#define __NR_io_submit 2 ++#endif ++ ++#if !defined(__NR_io_cancel) ++#define __NR_io_cancel 3 ++#endif ++ ++#if !defined(__NR_io_getevents) ++#define __NR_io_getevents 4 ++#endif ++ ++#if !defined(__NR_setxattr) ++#define __NR_setxattr 5 ++#endif ++ ++#if !defined(__NR_lsetxattr) ++#define __NR_lsetxattr 6 ++#endif ++ ++#if !defined(__NR_fsetxattr) ++#define __NR_fsetxattr 7 ++#endif ++ ++#if !defined(__NR_getxattr) ++#define __NR_getxattr 8 ++#endif ++ ++#if !defined(__NR_lgetxattr) ++#define __NR_lgetxattr 9 ++#endif ++ ++#if !defined(__NR_fgetxattr) ++#define __NR_fgetxattr 10 ++#endif ++ ++#if !defined(__NR_listxattr) ++#define __NR_listxattr 11 ++#endif ++ ++#if !defined(__NR_llistxattr) ++#define __NR_llistxattr 12 ++#endif ++ ++#if !defined(__NR_flistxattr) ++#define __NR_flistxattr 13 ++#endif ++ ++#if !defined(__NR_removexattr) ++#define __NR_removexattr 14 ++#endif ++ ++#if !defined(__NR_lremovexattr) ++#define __NR_lremovexattr 15 ++#endif ++ ++#if !defined(__NR_fremovexattr) ++#define __NR_fremovexattr 16 ++#endif ++ ++#if !defined(__NR_getcwd) ++#define __NR_getcwd 17 ++#endif ++ ++#if !defined(__NR_lookup_dcookie) ++#define __NR_lookup_dcookie 18 ++#endif ++ ++#if !defined(__NR_eventfd2) ++#define __NR_eventfd2 19 ++#endif ++ ++#if !defined(__NR_epoll_create1) ++#define __NR_epoll_create1 20 ++#endif ++ ++#if !defined(__NR_epoll_ctl) ++#define __NR_epoll_ctl 21 ++#endif ++ ++#if !defined(__NR_epoll_pwait) ++#define __NR_epoll_pwait 22 ++#endif ++ ++#if !defined(__NR_dup) ++#define __NR_dup 23 ++#endif ++ ++#if !defined(__NR_dup3) ++#define __NR_dup3 24 ++#endif ++ ++#if !defined(__NR_fcntl) ++#define __NR_fcntl 25 ++#endif ++ ++#if !defined(__NR_inotify_init1) ++#define __NR_inotify_init1 26 ++#endif ++ ++#if !defined(__NR_inotify_add_watch) ++#define __NR_inotify_add_watch 27 ++#endif ++ ++#if !defined(__NR_inotify_rm_watch) ++#define __NR_inotify_rm_watch 28 ++#endif ++ ++#if !defined(__NR_ioctl) ++#define __NR_ioctl 29 ++#endif ++ ++#if !defined(__NR_ioprio_set) ++#define __NR_ioprio_set 30 ++#endif ++ ++#if !defined(__NR_ioprio_get) ++#define __NR_ioprio_get 31 ++#endif ++ ++#if !defined(__NR_flock) ++#define __NR_flock 32 ++#endif ++ ++#if !defined(__NR_mknodat) ++#define __NR_mknodat 33 ++#endif ++ ++#if !defined(__NR_mkdirat) ++#define __NR_mkdirat 34 ++#endif ++ ++#if !defined(__NR_unlinkat) ++#define __NR_unlinkat 35 ++#endif ++ ++#if !defined(__NR_symlinkat) ++#define __NR_symlinkat 36 ++#endif ++ ++#if !defined(__NR_linkat) ++#define __NR_linkat 37 ++#endif ++ ++#if !defined(__NR_renameat) ++#define __NR_renameat 38 ++#endif ++ ++#if !defined(__NR_umount2) ++#define __NR_umount2 39 ++#endif ++ ++#if !defined(__NR_mount) ++#define __NR_mount 40 ++#endif ++ ++#if !defined(__NR_pivot_root) ++#define __NR_pivot_root 41 ++#endif ++ ++#if !defined(__NR_nfsservctl) ++#define __NR_nfsservctl 42 ++#endif ++ ++#if !defined(__NR_statfs) ++#define __NR_statfs 43 ++#endif ++ ++#if !defined(__NR_fstatfs) ++#define __NR_fstatfs 44 ++#endif ++ ++#if !defined(__NR_truncate) ++#define __NR_truncate 45 ++#endif ++ ++#if !defined(__NR_ftruncate) ++#define __NR_ftruncate 46 ++#endif ++ ++#if !defined(__NR_fallocate) ++#define __NR_fallocate 47 ++#endif ++ ++#if !defined(__NR_faccessat) ++#define __NR_faccessat 48 ++#endif ++ ++#if !defined(__NR_chdir) ++#define __NR_chdir 49 ++#endif ++ ++#if !defined(__NR_fchdir) ++#define __NR_fchdir 50 ++#endif ++ ++#if !defined(__NR_chroot) ++#define __NR_chroot 51 ++#endif ++ ++#if !defined(__NR_fchmod) ++#define __NR_fchmod 52 ++#endif ++ ++#if !defined(__NR_fchmodat) ++#define __NR_fchmodat 53 ++#endif ++ ++#if !defined(__NR_fchownat) ++#define __NR_fchownat 54 ++#endif ++ ++#if !defined(__NR_fchown) ++#define __NR_fchown 55 ++#endif ++ ++#if !defined(__NR_openat) ++#define __NR_openat 56 ++#endif ++ ++#if !defined(__NR_close) ++#define __NR_close 57 ++#endif ++ ++#if !defined(__NR_vhangup) ++#define __NR_vhangup 58 ++#endif ++ ++#if !defined(__NR_pipe2) ++#define __NR_pipe2 59 ++#endif ++ ++#if !defined(__NR_quotactl) ++#define __NR_quotactl 60 ++#endif ++ ++#if !defined(__NR_getdents64) ++#define __NR_getdents64 61 ++#endif ++ ++#if !defined(__NR_lseek) ++#define __NR_lseek 62 ++#endif ++ ++#if !defined(__NR_read) ++#define __NR_read 63 ++#endif ++ ++#if !defined(__NR_write) ++#define __NR_write 64 ++#endif ++ ++#if !defined(__NR_readv) ++#define __NR_readv 65 ++#endif ++ ++#if !defined(__NR_writev) ++#define __NR_writev 66 ++#endif ++ ++#if !defined(__NR_pread64) ++#define __NR_pread64 67 ++#endif ++ ++#if !defined(__NR_pwrite64) ++#define __NR_pwrite64 68 ++#endif ++ ++#if !defined(__NR_preadv) ++#define __NR_preadv 69 ++#endif ++ ++#if !defined(__NR_pwritev) ++#define __NR_pwritev 70 ++#endif ++ ++#if !defined(__NR_sendfile) ++#define __NR_sendfile 71 ++#endif ++ ++#if !defined(__NR_pselect6) ++#define __NR_pselect6 72 ++#endif ++ ++#if !defined(__NR_ppoll) ++#define __NR_ppoll 73 ++#endif ++ ++#if !defined(__NR_signalfd4) ++#define __NR_signalfd4 74 ++#endif ++ ++#if !defined(__NR_vmsplice) ++#define __NR_vmsplice 75 ++#endif ++ ++#if !defined(__NR_splice) ++#define __NR_splice 76 ++#endif ++ ++#if !defined(__NR_tee) ++#define __NR_tee 77 ++#endif ++ ++#if !defined(__NR_readlinkat) ++#define __NR_readlinkat 78 ++#endif ++ ++#if !defined(__NR_newfstatat) ++#define __NR_newfstatat 79 ++#endif ++ ++#if !defined(__NR_fstat) ++#define __NR_fstat 80 ++#endif ++ ++#if !defined(__NR_sync) ++#define __NR_sync 81 ++#endif ++ ++#if !defined(__NR_fsync) ++#define __NR_fsync 82 ++#endif ++ ++#if !defined(__NR_fdatasync) ++#define __NR_fdatasync 83 ++#endif ++ ++#if !defined(__NR_sync_file_range) ++#define __NR_sync_file_range 84 ++#endif ++ ++#if !defined(__NR_timerfd_create) ++#define __NR_timerfd_create 85 ++#endif ++ ++#if !defined(__NR_timerfd_settime) ++#define __NR_timerfd_settime 86 ++#endif ++ ++#if !defined(__NR_timerfd_gettime) ++#define __NR_timerfd_gettime 87 ++#endif ++ ++#if !defined(__NR_utimensat) ++#define __NR_utimensat 88 ++#endif ++ ++#if !defined(__NR_acct) ++#define __NR_acct 89 ++#endif ++ ++#if !defined(__NR_capget) ++#define __NR_capget 90 ++#endif ++ ++#if !defined(__NR_capset) ++#define __NR_capset 91 ++#endif ++ ++#if !defined(__NR_personality) ++#define __NR_personality 92 ++#endif ++ ++#if !defined(__NR_exit) ++#define __NR_exit 93 ++#endif ++ ++#if !defined(__NR_exit_group) ++#define __NR_exit_group 94 ++#endif ++ ++#if !defined(__NR_waitid) ++#define __NR_waitid 95 ++#endif ++ ++#if !defined(__NR_set_tid_address) ++#define __NR_set_tid_address 96 ++#endif ++ ++#if !defined(__NR_unshare) ++#define __NR_unshare 97 ++#endif ++ ++#if !defined(__NR_futex) ++#define __NR_futex 98 ++#endif ++ ++#if !defined(__NR_set_robust_list) ++#define __NR_set_robust_list 99 ++#endif ++ ++#if !defined(__NR_get_robust_list) ++#define __NR_get_robust_list 100 ++#endif ++ ++#if !defined(__NR_nanosleep) ++#define __NR_nanosleep 101 ++#endif ++ ++#if !defined(__NR_getitimer) ++#define __NR_getitimer 102 ++#endif ++ ++#if !defined(__NR_setitimer) ++#define __NR_setitimer 103 ++#endif ++ ++#if !defined(__NR_kexec_load) ++#define __NR_kexec_load 104 ++#endif ++ ++#if !defined(__NR_init_module) ++#define __NR_init_module 105 ++#endif ++ ++#if !defined(__NR_delete_module) ++#define __NR_delete_module 106 ++#endif ++ ++#if !defined(__NR_timer_create) ++#define __NR_timer_create 107 ++#endif ++ ++#if !defined(__NR_timer_gettime) ++#define __NR_timer_gettime 108 ++#endif ++ ++#if !defined(__NR_timer_getoverrun) ++#define __NR_timer_getoverrun 109 ++#endif ++ ++#if !defined(__NR_timer_settime) ++#define __NR_timer_settime 110 ++#endif ++ ++#if !defined(__NR_timer_delete) ++#define __NR_timer_delete 111 ++#endif ++ ++#if !defined(__NR_clock_settime) ++#define __NR_clock_settime 112 ++#endif ++ ++#if !defined(__NR_clock_gettime) ++#define __NR_clock_gettime 113 ++#endif ++ ++#if !defined(__NR_clock_getres) ++#define __NR_clock_getres 114 ++#endif ++ ++#if !defined(__NR_clock_nanosleep) ++#define __NR_clock_nanosleep 115 ++#endif ++ ++#if !defined(__NR_syslog) ++#define __NR_syslog 116 ++#endif ++ ++#if !defined(__NR_ptrace) ++#define __NR_ptrace 117 ++#endif ++ ++#if !defined(__NR_sched_setparam) ++#define __NR_sched_setparam 118 ++#endif ++ ++#if !defined(__NR_sched_setscheduler) ++#define __NR_sched_setscheduler 119 ++#endif ++ ++#if !defined(__NR_sched_getscheduler) ++#define __NR_sched_getscheduler 120 ++#endif ++ ++#if !defined(__NR_sched_getparam) ++#define __NR_sched_getparam 121 ++#endif ++ ++#if !defined(__NR_sched_setaffinity) ++#define __NR_sched_setaffinity 122 ++#endif ++ ++#if !defined(__NR_sched_getaffinity) ++#define __NR_sched_getaffinity 123 ++#endif ++ ++#if !defined(__NR_sched_yield) ++#define __NR_sched_yield 124 ++#endif ++ ++#if !defined(__NR_sched_get_priority_max) ++#define __NR_sched_get_priority_max 125 ++#endif ++ ++#if !defined(__NR_sched_get_priority_min) ++#define __NR_sched_get_priority_min 126 ++#endif ++ ++#if !defined(__NR_sched_rr_get_interval) ++#define __NR_sched_rr_get_interval 127 ++#endif ++ ++#if !defined(__NR_restart_syscall) ++#define __NR_restart_syscall 128 ++#endif ++ ++#if !defined(__NR_kill) ++#define __NR_kill 129 ++#endif ++ ++#if !defined(__NR_tkill) ++#define __NR_tkill 130 ++#endif ++ ++#if !defined(__NR_tgkill) ++#define __NR_tgkill 131 ++#endif ++ ++#if !defined(__NR_sigaltstack) ++#define __NR_sigaltstack 132 ++#endif ++ ++#if !defined(__NR_rt_sigsuspend) ++#define __NR_rt_sigsuspend 133 ++#endif ++ ++#if !defined(__NR_rt_sigaction) ++#define __NR_rt_sigaction 134 ++#endif ++ ++#if !defined(__NR_rt_sigprocmask) ++#define __NR_rt_sigprocmask 135 ++#endif ++ ++#if !defined(__NR_rt_sigpending) ++#define __NR_rt_sigpending 136 ++#endif ++ ++#if !defined(__NR_rt_sigtimedwait) ++#define __NR_rt_sigtimedwait 137 ++#endif ++ ++#if !defined(__NR_rt_sigqueueinfo) ++#define __NR_rt_sigqueueinfo 138 ++#endif ++ ++#if !defined(__NR_rt_sigreturn) ++#define __NR_rt_sigreturn 139 ++#endif ++ ++#if !defined(__NR_setpriority) ++#define __NR_setpriority 140 ++#endif ++ ++#if !defined(__NR_getpriority) ++#define __NR_getpriority 141 ++#endif ++ ++#if !defined(__NR_reboot) ++#define __NR_reboot 142 ++#endif ++ ++#if !defined(__NR_setregid) ++#define __NR_setregid 143 ++#endif ++ ++#if !defined(__NR_setgid) ++#define __NR_setgid 144 ++#endif ++ ++#if !defined(__NR_setreuid) ++#define __NR_setreuid 145 ++#endif ++ ++#if !defined(__NR_setuid) ++#define __NR_setuid 146 ++#endif ++ ++#if !defined(__NR_setresuid) ++#define __NR_setresuid 147 ++#endif ++ ++#if !defined(__NR_getresuid) ++#define __NR_getresuid 148 ++#endif ++ ++#if !defined(__NR_setresgid) ++#define __NR_setresgid 149 ++#endif ++ ++#if !defined(__NR_getresgid) ++#define __NR_getresgid 150 ++#endif ++ ++#if !defined(__NR_setfsuid) ++#define __NR_setfsuid 151 ++#endif ++ ++#if !defined(__NR_setfsgid) ++#define __NR_setfsgid 152 ++#endif ++ ++#if !defined(__NR_times) ++#define __NR_times 153 ++#endif ++ ++#if !defined(__NR_setpgid) ++#define __NR_setpgid 154 ++#endif ++ ++#if !defined(__NR_getpgid) ++#define __NR_getpgid 155 ++#endif ++ ++#if !defined(__NR_getsid) ++#define __NR_getsid 156 ++#endif ++ ++#if !defined(__NR_setsid) ++#define __NR_setsid 157 ++#endif ++ ++#if !defined(__NR_getgroups) ++#define __NR_getgroups 158 ++#endif ++ ++#if !defined(__NR_setgroups) ++#define __NR_setgroups 159 ++#endif ++ ++#if !defined(__NR_uname) ++#define __NR_uname 160 ++#endif ++ ++#if !defined(__NR_sethostname) ++#define __NR_sethostname 161 ++#endif ++ ++#if !defined(__NR_setdomainname) ++#define __NR_setdomainname 162 ++#endif ++ ++#if !defined(__NR_getrlimit) ++#define __NR_getrlimit 163 ++#endif ++ ++#if !defined(__NR_setrlimit) ++#define __NR_setrlimit 164 ++#endif ++ ++#if !defined(__NR_getrusage) ++#define __NR_getrusage 165 ++#endif ++ ++#if !defined(__NR_umask) ++#define __NR_umask 166 ++#endif ++ ++#if !defined(__NR_prctl) ++#define __NR_prctl 167 ++#endif ++ ++#if !defined(__NR_getcpu) ++#define __NR_getcpu 168 ++#endif ++ ++#if !defined(__NR_gettimeofday) ++#define __NR_gettimeofday 169 ++#endif ++ ++#if !defined(__NR_settimeofday) ++#define __NR_settimeofday 170 ++#endif ++ ++#if !defined(__NR_adjtimex) ++#define __NR_adjtimex 171 ++#endif ++ ++#if !defined(__NR_getpid) ++#define __NR_getpid 172 ++#endif ++ ++#if !defined(__NR_getppid) ++#define __NR_getppid 173 ++#endif ++ ++#if !defined(__NR_getuid) ++#define __NR_getuid 174 ++#endif ++ ++#if !defined(__NR_geteuid) ++#define __NR_geteuid 175 ++#endif ++ ++#if !defined(__NR_getgid) ++#define __NR_getgid 176 ++#endif ++ ++#if !defined(__NR_getegid) ++#define __NR_getegid 177 ++#endif ++ ++#if !defined(__NR_gettid) ++#define __NR_gettid 178 ++#endif ++ ++#if !defined(__NR_sysinfo) ++#define __NR_sysinfo 179 ++#endif ++ ++#if !defined(__NR_mq_open) ++#define __NR_mq_open 180 ++#endif ++ ++#if !defined(__NR_mq_unlink) ++#define __NR_mq_unlink 181 ++#endif ++ ++#if !defined(__NR_mq_timedsend) ++#define __NR_mq_timedsend 182 ++#endif ++ ++#if !defined(__NR_mq_timedreceive) ++#define __NR_mq_timedreceive 183 ++#endif ++ ++#if !defined(__NR_mq_notify) ++#define __NR_mq_notify 184 ++#endif ++ ++#if !defined(__NR_mq_getsetattr) ++#define __NR_mq_getsetattr 185 ++#endif ++ ++#if !defined(__NR_msgget) ++#define __NR_msgget 186 ++#endif ++ ++#if !defined(__NR_msgctl) ++#define __NR_msgctl 187 ++#endif ++ ++#if !defined(__NR_msgrcv) ++#define __NR_msgrcv 188 ++#endif ++ ++#if !defined(__NR_msgsnd) ++#define __NR_msgsnd 189 ++#endif ++ ++#if !defined(__NR_semget) ++#define __NR_semget 190 ++#endif ++ ++#if !defined(__NR_semctl) ++#define __NR_semctl 191 ++#endif ++ ++#if !defined(__NR_semtimedop) ++#define __NR_semtimedop 192 ++#endif ++ ++#if !defined(__NR_semop) ++#define __NR_semop 193 ++#endif ++ ++#if !defined(__NR_shmget) ++#define __NR_shmget 194 ++#endif ++ ++#if !defined(__NR_shmctl) ++#define __NR_shmctl 195 ++#endif ++ ++#if !defined(__NR_shmat) ++#define __NR_shmat 196 ++#endif ++ ++#if !defined(__NR_shmdt) ++#define __NR_shmdt 197 ++#endif ++ ++#if !defined(__NR_socket) ++#define __NR_socket 198 ++#endif ++ ++#if !defined(__NR_socketpair) ++#define __NR_socketpair 199 ++#endif ++ ++#if !defined(__NR_bind) ++#define __NR_bind 200 ++#endif ++ ++#if !defined(__NR_listen) ++#define __NR_listen 201 ++#endif ++ ++#if !defined(__NR_accept) ++#define __NR_accept 202 ++#endif ++ ++#if !defined(__NR_connect) ++#define __NR_connect 203 ++#endif ++ ++#if !defined(__NR_getsockname) ++#define __NR_getsockname 204 ++#endif ++ ++#if !defined(__NR_getpeername) ++#define __NR_getpeername 205 ++#endif ++ ++#if !defined(__NR_sendto) ++#define __NR_sendto 206 ++#endif ++ ++#if !defined(__NR_recvfrom) ++#define __NR_recvfrom 207 ++#endif ++ ++#if !defined(__NR_setsockopt) ++#define __NR_setsockopt 208 ++#endif ++ ++#if !defined(__NR_getsockopt) ++#define __NR_getsockopt 209 ++#endif ++ ++#if !defined(__NR_shutdown) ++#define __NR_shutdown 210 ++#endif ++ ++#if !defined(__NR_sendmsg) ++#define __NR_sendmsg 211 ++#endif ++ ++#if !defined(__NR_recvmsg) ++#define __NR_recvmsg 212 ++#endif ++ ++#if !defined(__NR_readahead) ++#define __NR_readahead 213 ++#endif ++ ++#if !defined(__NR_brk) ++#define __NR_brk 214 ++#endif ++ ++#if !defined(__NR_munmap) ++#define __NR_munmap 215 ++#endif ++ ++#if !defined(__NR_mremap) ++#define __NR_mremap 216 ++#endif ++ ++#if !defined(__NR_add_key) ++#define __NR_add_key 217 ++#endif ++ ++#if !defined(__NR_request_key) ++#define __NR_request_key 218 ++#endif ++ ++#if !defined(__NR_keyctl) ++#define __NR_keyctl 219 ++#endif ++ ++#if !defined(__NR_clone) ++#define __NR_clone 220 ++#endif ++ ++#if !defined(__NR_execve) ++#define __NR_execve 221 ++#endif ++ ++#if !defined(__NR_mmap) ++#define __NR_mmap 222 ++#endif ++ ++#if !defined(__NR_fadvise64) ++#define __NR_fadvise64 223 ++#endif ++ ++#if !defined(__NR_swapon) ++#define __NR_swapon 224 ++#endif ++ ++#if !defined(__NR_swapoff) ++#define __NR_swapoff 225 ++#endif ++ ++#if !defined(__NR_mprotect) ++#define __NR_mprotect 226 ++#endif ++ ++#if !defined(__NR_msync) ++#define __NR_msync 227 ++#endif ++ ++#if !defined(__NR_mlock) ++#define __NR_mlock 228 ++#endif ++ ++#if !defined(__NR_munlock) ++#define __NR_munlock 229 ++#endif ++ ++#if !defined(__NR_mlockall) ++#define __NR_mlockall 230 ++#endif ++ ++#if !defined(__NR_munlockall) ++#define __NR_munlockall 231 ++#endif ++ ++#if !defined(__NR_mincore) ++#define __NR_mincore 232 ++#endif ++ ++#if !defined(__NR_madvise) ++#define __NR_madvise 233 ++#endif ++ ++#if !defined(__NR_remap_file_pages) ++#define __NR_remap_file_pages 234 ++#endif ++ ++#if !defined(__NR_mbind) ++#define __NR_mbind 235 ++#endif ++ ++#if !defined(__NR_get_mempolicy) ++#define __NR_get_mempolicy 236 ++#endif ++ ++#if !defined(__NR_set_mempolicy) ++#define __NR_set_mempolicy 237 ++#endif ++ ++#if !defined(__NR_migrate_pages) ++#define __NR_migrate_pages 238 ++#endif ++ ++#if !defined(__NR_move_pages) ++#define __NR_move_pages 239 ++#endif ++ ++#if !defined(__NR_rt_tgsigqueueinfo) ++#define __NR_rt_tgsigqueueinfo 240 ++#endif ++ ++#if !defined(__NR_perf_event_open) ++#define __NR_perf_event_open 241 ++#endif ++ ++#if !defined(__NR_accept4) ++#define __NR_accept4 242 ++#endif ++ ++#if !defined(__NR_recvmmsg) ++#define __NR_recvmmsg 243 ++#endif ++ ++#if !defined(__NR_riscv_flush_icache) ++#define __NR_riscv_flush_icache 259 ++#endif ++ ++#if !defined(__NR_wait4) ++#define __NR_wait4 260 ++#endif ++ ++#if !defined(__NR_prlimit64) ++#define __NR_prlimit64 261 ++#endif ++ ++#if !defined(__NR_fanotify_init) ++#define __NR_fanotify_init 262 ++#endif ++ ++#if !defined(__NR_fanotify_mark) ++#define __NR_fanotify_mark 263 ++#endif ++ ++#if !defined(__NR_name_to_handle_at) ++#define __NR_name_to_handle_at 264 ++#endif ++ ++#if !defined(__NR_open_by_handle_at) ++#define __NR_open_by_handle_at 265 ++#endif ++ ++#if !defined(__NR_clock_adjtime) ++#define __NR_clock_adjtime 266 ++#endif ++ ++#if !defined(__NR_syncfs) ++#define __NR_syncfs 267 ++#endif ++ ++#if !defined(__NR_setns) ++#define __NR_setns 268 ++#endif ++ ++#if !defined(__NR_sendmmsg) ++#define __NR_sendmmsg 269 ++#endif ++ ++#if !defined(__NR_process_vm_readv) ++#define __NR_process_vm_readv 270 ++#endif ++ ++#if !defined(__NR_process_vm_writev) ++#define __NR_process_vm_writev 271 ++#endif ++ ++#if !defined(__NR_kcmp) ++#define __NR_kcmp 272 ++#endif ++ ++#if !defined(__NR_finit_module) ++#define __NR_finit_module 273 ++#endif ++ ++#if !defined(__NR_sched_setattr) ++#define __NR_sched_setattr 274 ++#endif ++ ++#if !defined(__NR_sched_getattr) ++#define __NR_sched_getattr 275 ++#endif ++ ++#if !defined(__NR_renameat2) ++#define __NR_renameat2 276 ++#endif ++ ++#if !defined(__NR_seccomp) ++#define __NR_seccomp 277 ++#endif ++ ++#if !defined(__NR_getrandom) ++#define __NR_getrandom 278 ++#endif ++ ++#if !defined(__NR_memfd_create) ++#define __NR_memfd_create 279 ++#endif ++ ++#if !defined(__NR_bpf) ++#define __NR_bpf 280 ++#endif ++ ++#if !defined(__NR_execveat) ++#define __NR_execveat 281 ++#endif ++ ++#if !defined(__NR_userfaultfd) ++#define __NR_userfaultfd 282 ++#endif ++ ++#if !defined(__NR_membarrier) ++#define __NR_membarrier 283 ++#endif ++ ++#if !defined(__NR_mlock2) ++#define __NR_mlock2 284 ++#endif ++ ++#if !defined(__NR_copy_file_range) ++#define __NR_copy_file_range 285 ++#endif ++ ++#if !defined(__NR_preadv2) ++#define __NR_preadv2 286 ++#endif ++ ++#if !defined(__NR_pwritev2) ++#define __NR_pwritev2 287 ++#endif ++ ++#if !defined(__NR_pkey_mprotect) ++#define __NR_pkey_mprotect 288 ++#endif ++ ++#if !defined(__NR_pkey_alloc) ++#define __NR_pkey_alloc 289 ++#endif ++ ++#if !defined(__NR_pkey_free) ++#define __NR_pkey_free 290 ++#endif ++ ++#if !defined(__NR_statx) ++#define __NR_statx 291 ++#endif ++ ++#if !defined(__NR_io_pgetevents) ++#define __NR_io_pgetevents 292 ++#endif ++ ++#if !defined(__NR_rseq) ++#define __NR_rseq 293 ++#endif ++ ++#if !defined(__NR_kexec_file_load) ++#define __NR_kexec_file_load 294 ++#endif ++ ++#if !defined(__NR_pidfd_send_signal) ++#define __NR_pidfd_send_signal 424 ++#endif ++ ++#if !defined(__NR_io_uring_setup) ++#define __NR_io_uring_setup 425 ++#endif ++ ++#if !defined(__NR_io_uring_enter) ++#define __NR_io_uring_enter 426 ++#endif ++ ++#if !defined(__NR_io_uring_register) ++#define __NR_io_uring_register 427 ++#endif ++ ++#if !defined(__NR_open_tree) ++#define __NR_open_tree 428 ++#endif ++ ++#if !defined(__NR_move_mount) ++#define __NR_move_mount 429 ++#endif ++ ++#if !defined(__NR_fsopen) ++#define __NR_fsopen 430 ++#endif ++ ++#if !defined(__NR_fsconfig) ++#define __NR_fsconfig 431 ++#endif ++ ++#if !defined(__NR_fsmount) ++#define __NR_fsmount 432 ++#endif ++ ++#if !defined(__NR_fspick) ++#define __NR_fspick 433 ++#endif ++ ++#if !defined(__NR_pidfd_open) ++#define __NR_pidfd_open 434 ++#endif ++ ++#if !defined(__NR_clone3) ++#define __NR_clone3 435 ++#endif ++ ++#if !defined(__NR_close_range) ++#define __NR_close_range 436 ++#endif ++ ++#if !defined(__NR_openat2) ++#define __NR_openat2 437 ++#endif ++ ++#if !defined(__NR_pidfd_getfd) ++#define __NR_pidfd_getfd 438 ++#endif ++ ++#if !defined(__NR_faccessat2) ++#define __NR_faccessat2 439 ++#endif ++ ++#if !defined(__NR_process_madvise) ++#define __NR_process_madvise 440 ++#endif ++ ++#if !defined(__NR_epoll_pwait2) ++#define __NR_epoll_pwait2 441 ++#endif ++ ++#if !defined(__NR_mount_setattr) ++#define __NR_mount_setattr 442 ++#endif ++ ++#if !defined(__NR_quotactl_path) ++#define __NR_quotactl_path 443 ++#endif ++ ++#if !defined(__NR_landlock_create_ruleset) ++#define __NR_landlock_create_ruleset 444 ++#endif ++ ++#if !defined(__NR_landlock_add_rule) ++#define __NR_landlock_add_rule 445 ++#endif ++ ++#if !defined(__NR_landlock_restrict_self) ++#define __NR_landlock_restrict_self 446 ++#endif ++ ++#endif // SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ +Index: chromium-103.0.5060.134/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc ++++ chromium-103.0.5060.134/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc +@@ -38,7 +38,7 @@ ResultExpr CrosAmdGpuProcessPolicy::Eval + case __NR_sched_setscheduler: + case __NR_sysinfo: + case __NR_uname: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_readlink: + case __NR_stat: + #endif +Index: chromium-103.0.5060.134/sandbox/policy/linux/bpf_gpu_policy_linux.cc +=================================================================== +--- chromium-103.0.5060.134.orig/sandbox/policy/linux/bpf_gpu_policy_linux.cc ++++ chromium-103.0.5060.134/sandbox/policy/linux/bpf_gpu_policy_linux.cc +@@ -73,7 +73,7 @@ ResultExpr GpuProcessPolicy::EvaluateSys + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) + case __NR_ftruncate64: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getdents: + #endif + case __NR_getdents64: diff --git a/srcpkgs/chromium/patches/riscv-v8.patch.old b/srcpkgs/chromium/patches/riscv-v8.patch.old new file mode 100644 index 0000000000000..01c7eb0cb695a --- /dev/null +++ b/srcpkgs/chromium/patches/riscv-v8.patch.old @@ -0,0 +1,176 @@ +Index: chromium-104.0.5112.79/v8/src/builtins/riscv64/builtins-riscv64.cc +=================================================================== +--- chromium-104.0.5112.79.orig/v8/src/builtins/riscv64/builtins-riscv64.cc ++++ chromium-104.0.5112.79/v8/src/builtins/riscv64/builtins-riscv64.cc +@@ -858,7 +858,7 @@ static void ReplaceClosureCodeWithOptimi + __ Move(scratch1, optimized_code); // Write barrier clobbers scratch1 below. + __ RecordWriteField(closure, JSFunction::kCodeOffset, scratch1, + kRAHasNotBeenSaved, SaveFPRegsMode::kIgnore, +- RememberedSetAction::kOmit, SmiCheck::kOmit); ++ SmiCheck::kOmit); + } + + static void LeaveInterpreterFrame(MacroAssembler* masm, Register scratch1, +Index: chromium-104.0.5112.79/v8/src/codegen/riscv64/macro-assembler-riscv64.cc +=================================================================== +--- chromium-104.0.5112.79.orig/v8/src/codegen/riscv64/macro-assembler-riscv64.cc ++++ chromium-104.0.5112.79/v8/src/codegen/riscv64/macro-assembler-riscv64.cc +@@ -142,7 +142,6 @@ int MacroAssembler::SafepointRegisterSta + void MacroAssembler::RecordWriteField(Register object, int offset, + Register value, RAStatus ra_status, + SaveFPRegsMode save_fp, +- RememberedSetAction remembered_set_action, + SmiCheck smi_check) { + DCHECK(!AreAliased(object, value)); + // First, check if a write barrier is even needed. The tests below +@@ -171,7 +170,7 @@ void MacroAssembler::RecordWriteField(Re + } + + RecordWrite(object, Operand(offset - kHeapObjectTag), value, ra_status, +- save_fp, remembered_set_action, SmiCheck::kOmit); ++ save_fp, SmiCheck::kOmit); + + bind(&done); + } +@@ -211,7 +210,7 @@ void TurboAssembler::CallEphemeronKeyBar + + void TurboAssembler::CallRecordWriteStubSaveRegisters( + Register object, Register slot_address, +- RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ SaveFPRegsMode fp_mode, + StubCallMode mode) { + DCHECK(!AreAliased(object, slot_address)); + RegList registers = +@@ -228,14 +227,14 @@ void TurboAssembler::CallRecordWriteStub + Pop(object_parameter); + + CallRecordWriteStub(object_parameter, slot_address_parameter, +- remembered_set_action, fp_mode, mode); ++ fp_mode, mode); + + MaybeRestoreRegisters(registers); + } + + void TurboAssembler::CallRecordWriteStub( + Register object, Register slot_address, +- RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ SaveFPRegsMode fp_mode, + StubCallMode mode) { + // Use CallRecordWriteStubSaveRegisters if the object and slot registers + // need to be caller saved. +@@ -243,10 +242,10 @@ void TurboAssembler::CallRecordWriteStub + DCHECK_EQ(WriteBarrierDescriptor::SlotAddressRegister(), slot_address); + if (mode == StubCallMode::kCallWasmRuntimeStub) { + auto wasm_target = +- wasm::WasmCode::GetRecordWriteStub(remembered_set_action, fp_mode); ++ wasm::WasmCode::GetRecordWriteStub(fp_mode); + Call(wasm_target, RelocInfo::WASM_STUB_CALL); + } else { +- auto builtin = Builtins::GetRecordWriteStub(remembered_set_action, fp_mode); ++ auto builtin = Builtins::GetRecordWriteStub(fp_mode); + if (options().inline_offheap_trampolines) { + // Inline the trampoline. //qj + RecordCommentForOffHeapTrampoline(builtin); +@@ -270,7 +269,6 @@ void TurboAssembler::CallRecordWriteStub + void MacroAssembler::RecordWrite(Register object, Operand offset, + Register value, RAStatus ra_status, + SaveFPRegsMode fp_mode, +- RememberedSetAction remembered_set_action, + SmiCheck smi_check) { + DCHECK(!AreAliased(object, value)); + +@@ -284,9 +282,7 @@ void MacroAssembler::RecordWrite(Registe + Operand(value)); + } + +- if ((remembered_set_action == RememberedSetAction::kOmit && +- !FLAG_incremental_marking) || +- FLAG_disable_write_barriers) { ++ if (FLAG_disable_write_barriers) { + return; + } + +@@ -325,7 +321,7 @@ void MacroAssembler::RecordWrite(Registe + // TODO(cbruni): Turn offset into int. + DCHECK(offset.IsImmediate()); + Add64(slot_address, object, offset); +- CallRecordWriteStub(object, slot_address, remembered_set_action, fp_mode); ++ CallRecordWriteStub(object, slot_address, fp_mode); + if (ra_status == kRAHasNotBeenSaved) { + pop(ra); + } +Index: chromium-104.0.5112.79/v8/src/codegen/riscv64/macro-assembler-riscv64.h +=================================================================== +--- chromium-104.0.5112.79.orig/v8/src/codegen/riscv64/macro-assembler-riscv64.h ++++ chromium-104.0.5112.79/v8/src/codegen/riscv64/macro-assembler-riscv64.h +@@ -347,11 +347,11 @@ class V8_EXPORT_PRIVATE TurboAssembler : + + void CallRecordWriteStubSaveRegisters( + Register object, Register slot_address, +- RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ SaveFPRegsMode fp_mode, + StubCallMode mode = StubCallMode::kCallBuiltinPointer); + void CallRecordWriteStub( + Register object, Register slot_address, +- RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ SaveFPRegsMode fp_mode, + StubCallMode mode = StubCallMode::kCallBuiltinPointer); + + // Push multiple registers on the stack. +@@ -1098,7 +1098,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : + void RecordWriteField( + Register object, int offset, Register value, RAStatus ra_status, + SaveFPRegsMode save_fp, +- RememberedSetAction remembered_set_action = RememberedSetAction::kEmit, + SmiCheck smi_check = SmiCheck::kInline); + + // For a given |object| notify the garbage collector that the slot |address| +@@ -1107,7 +1106,6 @@ class V8_EXPORT_PRIVATE MacroAssembler : + void RecordWrite( + Register object, Operand offset, Register value, RAStatus ra_status, + SaveFPRegsMode save_fp, +- RememberedSetAction remembered_set_action = RememberedSetAction::kEmit, + SmiCheck smi_check = SmiCheck::kInline); + + // void Pref(int32_t hint, const MemOperand& rs); +Index: chromium-104.0.5112.79/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc +=================================================================== +--- chromium-104.0.5112.79.orig/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc ++++ chromium-104.0.5112.79/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc +@@ -181,9 +181,6 @@ class OutOfLineRecordWrite final : publi + MemoryChunk::kPointersToHereAreInterestingMask, eq, + exit()); + __ Add64(scratch1_, object_, index_); +- RememberedSetAction const remembered_set_action = +- mode_ > RecordWriteMode::kValueIsMap ? RememberedSetAction::kEmit +- : RememberedSetAction::kOmit; + SaveFPRegsMode const save_fp_mode = frame()->DidAllocateDoubleRegisters() + ? SaveFPRegsMode::kSave + : SaveFPRegsMode::kIgnore; +@@ -198,11 +195,11 @@ class OutOfLineRecordWrite final : publi + // Just encode the stub index. This will be patched when the code + // is added to the native module and copied into wasm code space. + __ CallRecordWriteStubSaveRegisters(object_, scratch1_, +- remembered_set_action, save_fp_mode, ++ save_fp_mode, + StubCallMode::kCallWasmRuntimeStub); + } else { + __ CallRecordWriteStubSaveRegisters(object_, scratch1_, +- remembered_set_action, save_fp_mode); ++ save_fp_mode); + } + if (must_save_lr_) { + __ Pop(ra); +Index: chromium-104.0.5112.79/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h +=================================================================== +--- chromium-104.0.5112.79.orig/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h ++++ chromium-104.0.5112.79/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h +@@ -511,7 +511,7 @@ void LiftoffAssembler::StoreTaggedPointe + MemoryChunk::kPointersToHereAreInterestingMask, eq, &exit); + Add64(scratch, dst_op.rm(), dst_op.offset()); + CallRecordWriteStubSaveRegisters( +- dst_addr, scratch, RememberedSetAction::kEmit, SaveFPRegsMode::kSave, ++ dst_addr, scratch, SaveFPRegsMode::kSave, + StubCallMode::kCallWasmRuntimeStub); + bind(&exit); + } diff --git a/srcpkgs/chromium/patches/riscv.patch.old b/srcpkgs/chromium/patches/riscv.patch.old new file mode 100644 index 0000000000000..677c64d16db3a --- /dev/null +++ b/srcpkgs/chromium/patches/riscv.patch.old @@ -0,0 +1,118 @@ +Index: chromium-104.0.5112.79/components/update_client/update_query_params.cc +=================================================================== +--- chromium-104.0.5112.79.orig/components/update_client/update_query_params.cc ++++ chromium-104.0.5112.79/components/update_client/update_query_params.cc +@@ -63,6 +63,8 @@ const char kArch[] = + "loong32"; + #elif defined(__loongarch64) + "loong64"; ++#elif defined(__riscv) && __riscv_xlen == 64 ++ "riscv64"; + #else + #error "unknown arch" + #endif +@@ -136,6 +138,8 @@ const char* UpdateQueryParams::GetNaclAr + return "loong32"; + #elif defined(ARCH_CPU_LOONG64) + return "loong64"; ++#elif defined(ARCH_CPU_RISCV64) ++ return "riscv64"; + #else + // NOTE: when adding new values here, please remember to update the + // comment in the .h file about possible return values from this function. +Index: chromium-104.0.5112.79/components/update_client/update_query_params.h +=================================================================== +--- chromium-104.0.5112.79.orig/components/update_client/update_query_params.h ++++ chromium-104.0.5112.79/components/update_client/update_query_params.h +@@ -44,7 +44,7 @@ class UpdateQueryParams { + // Returns the value we use for the "nacl_arch" parameter. Note that this may + // be different from the "arch" parameter above (e.g. one may be 32-bit and + // the other 64-bit). Possible return values include: "x86-32", "x86-64", +- // "arm", "mips32", and "ppc64". ++ // "arm", "mips32", "ppc64", and "riscv64". + static const char* GetNaclArch(); + + // Returns the current version of Chrome/Chromium. +Index: chromium-104.0.5112.79/skia/BUILD.gn +=================================================================== +--- chromium-104.0.5112.79.orig/skia/BUILD.gn ++++ chromium-104.0.5112.79/skia/BUILD.gn +@@ -809,6 +809,8 @@ skia_source_set("skia_opts") { + sources = skia_opts.none_sources + } else if (current_cpu == "s390x") { + sources = skia_opts.none_sources ++ } else if (current_cpu == "riscv64") { ++ sources = skia_opts.none_sources + } else { + assert(false, "Need to port cpu specific stuff from skia_library_opts.gyp") + } +Index: chromium-104.0.5112.79/third_party/dawn/src/dawn/common/Platform.h +=================================================================== +--- chromium-104.0.5112.79.orig/third_party/dawn/src/dawn/common/Platform.h ++++ chromium-104.0.5112.79/third_party/dawn/src/dawn/common/Platform.h +@@ -68,7 +68,7 @@ + #endif + + #if defined(_WIN64) || defined(__aarch64__) || defined(__x86_64__) || defined(__mips64__) || \ +- defined(__s390x__) || defined(__PPC64__) ++ defined(__s390x__) || defined(__PPC64__) || (defined(__riscv) && __riscv_xlen == 64) + #define DAWN_PLATFORM_IS_64_BIT 1 + static_assert(sizeof(sizeof(char)) == 8, "Expect sizeof(size_t) == 8"); + #elif defined(_WIN32) || defined(__arm__) || defined(__i386__) || defined(__mips32__) || \ +Index: chromium-104.0.5112.79/third_party/highway/src/hwy/base.h +=================================================================== +--- chromium-104.0.5112.79.orig/third_party/highway/src/hwy/base.h ++++ chromium-104.0.5112.79/third_party/highway/src/hwy/base.h +@@ -316,7 +316,7 @@ namespace hwy { + #if HWY_ARCH_X86 + static constexpr HWY_MAYBE_UNUSED size_t kMaxVectorSize = 64; // AVX-512 + #define HWY_ALIGN_MAX alignas(64) +-#elif HWY_ARCH_RVV ++#elif HWY_ARCH_RVV && defined(__riscv_vector) + // Not actually an upper bound on the size, but this value prevents crossing a + // 4K boundary (relevant on Andes). + static constexpr HWY_MAYBE_UNUSED size_t kMaxVectorSize = 4096; +@@ -333,7 +333,7 @@ static constexpr HWY_MAYBE_UNUSED size_t + // by concatenating base type and bits. + + // RVV already has a builtin type and the GCC intrinsics require it. +-#if HWY_ARCH_RVV && HWY_COMPILER_GCC ++#if HWY_ARCH_RVV && HWY_COMPILER_GCC && defined(__riscv_vector) + #define HWY_NATIVE_FLOAT16 1 + #else + #define HWY_NATIVE_FLOAT16 0 +Index: chromium-104.0.5112.79/third_party/libaom/BUILD.gn +=================================================================== +--- chromium-104.0.5112.79.orig/third_party/libaom/BUILD.gn ++++ chromium-104.0.5112.79/third_party/libaom/BUILD.gn +@@ -36,6 +36,8 @@ if (current_cpu == "x86") { + } else { + cpu_arch_full = "arm" + } ++} else if (current_cpu == "riscv64") { ++ cpu_arch_full = "generic" + } else { + cpu_arch_full = current_cpu + } +Index: chromium-104.0.5112.79/third_party/libvpx/BUILD.gn +=================================================================== +--- chromium-104.0.5112.79.orig/third_party/libvpx/BUILD.gn ++++ chromium-104.0.5112.79/third_party/libvpx/BUILD.gn +@@ -35,6 +35,8 @@ if (current_cpu == "x86") { + } else { + cpu_arch_full = current_cpu + } ++} else if (current_cpu == "riscv64") { ++ cpu_arch_full = "generic" + } else { + cpu_arch_full = current_cpu + } +@@ -360,7 +362,7 @@ static_library("libvpx") { + configs += [ "//build/config/compiler:optimize_max" ] + } + +- if (is_nacl) { ++ if (is_nacl || current_cpu == "riscv64") { + sources = libvpx_srcs_generic + public_deps = [ ":libvpx_generic_headers" ] + } else if (current_cpu == "x86") { diff --git a/srcpkgs/chromium/template b/srcpkgs/chromium/template index 7fd0f94fa7b5e..1a3b43b5d7439 100644 --- a/srcpkgs/chromium/template +++ b/srcpkgs/chromium/template @@ -61,7 +61,7 @@ fi if [ "$CROSS_BUILD" ]; then case "${XBPS_TARGET_MACHINE}" in - aarch64*) ;; + aarch64*|riscv64*) ;; *) nocross="chromium can not be cross compiled for this architecture" ;; esac fi @@ -269,6 +269,7 @@ do_configure() { i686*) conf+=( 'target_cpu="x86"' ) ;; arm*) conf+=( 'target_cpu="arm"' ) ;; aarch64*) conf+=( 'target_cpu="arm64"' ) ;; + riscv64*) conf+=( 'target_cpu="riscv64"' ) ;; esac if [ "$CROSS_BUILD" ]; then @@ -277,6 +278,7 @@ do_configure() { i686*) conf+=( 'host_cpu="x86"' ) ;; arm*) conf+=( 'host_cpu="arm"' ) ;; aarch64*) conf+=( 'host_cpu="arm64"' ) ;; + riscv64*) conf+=( 'host_cpu="riscv64"' ) ;; esac fi _setup_toolchain From b8764be2526f97c10aa64b6f6545f0b6b029e182 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 00:15:41 +0100 Subject: [PATCH 073/189] qt5-webkit: mark riscv64 as unsupported --- srcpkgs/qt5-webkit/patches/riscv64.patch | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 srcpkgs/qt5-webkit/patches/riscv64.patch diff --git a/srcpkgs/qt5-webkit/patches/riscv64.patch b/srcpkgs/qt5-webkit/patches/riscv64.patch new file mode 100644 index 0000000000000..42c17586ede47 --- /dev/null +++ b/srcpkgs/qt5-webkit/patches/riscv64.patch @@ -0,0 +1,62 @@ +Description: add support for riscv64 architecture +Author: William Grant +Forwarded: https://github.com/qtwebkit/qtwebkit/pull/982 +Last-Update: 2020-04-28 + +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -83,6 +83,8 @@ elseif (LOWERCASE_CMAKE_SYSTEM_PROCESSOR + set(WTF_CPU_S390 1) + elseif (LOWERCASE_CMAKE_SYSTEM_PROCESSOR MATCHES "s390x") + set(WTF_CPU_S390X 1) ++elseif (LOWERCASE_CMAKE_SYSTEM_PROCESSOR MATCHES "riscv64") ++ set(WTF_CPU_RISCV64 1) + else () + message(FATAL_ERROR "Unknown CPU '${LOWERCASE_CMAKE_SYSTEM_PROCESSOR}'") + endif () +--- a/Source/JavaScriptCore/CMakeLists.txt ++++ b/Source/JavaScriptCore/CMakeLists.txt +@@ -1287,6 +1287,7 @@ elseif (WTF_CPU_S390) + elseif (WTF_CPU_S390X) + elseif (WTF_CPU_MIPS) + elseif (WTF_CPU_SH4) ++elseif (WTF_CPU_RISCV64) + elseif (WTF_CPU_X86) + elseif (WTF_CPU_X86_64) + if (MSVC AND ENABLE_JIT) +--- a/Source/WTF/wtf/Platform.h ++++ b/Source/WTF/wtf/Platform.h +@@ -176,6 +176,11 @@ + #define WTF_CPU_X86_SSE2 1 + #endif + ++/* CPU(RISCV64) - RISCV64 */ ++#if defined(__riscv) && defined(__riscv_xlen) && __riscv_xlen == 64 ++#define WTF_CPU_RISCV64 1 ++#endif ++ + /* CPU(ARM64) - Apple */ + #if (defined(__arm64__) && defined(__APPLE__)) || defined(__aarch64__) + #define WTF_CPU_ARM64 1 +@@ -707,7 +712,8 @@ + || CPU(S390X) \ + || CPU(MIPS64) \ + || CPU(PPC64) \ +- || CPU(PPC64LE) ++ || CPU(PPC64LE) \ ++ || CPU(RISCV64) + #define USE_JSVALUE64 1 + #else + #define USE_JSVALUE32_64 1 +--- a/Source/WTF/wtf/dtoa/utils.h ++++ b/Source/WTF/wtf/dtoa/utils.h +@@ -49,7 +49,7 @@ + defined(__ARMEL__) || \ + defined(_MIPS_ARCH_MIPS32R2) + #define DOUBLE_CONVERSION_CORRECT_DOUBLE_OPERATIONS 1 +-#elif CPU(MIPS) || CPU(MIPS64) || CPU(PPC) || CPU(PPC64) || CPU(PPC64LE) || CPU(SH4) || CPU(S390) || CPU(S390X) || CPU(IA64) || CPU(ALPHA) || CPU(ARM64) || CPU(HPPA) ++#elif CPU(MIPS) || CPU(MIPS64) || CPU(PPC) || CPU(PPC64) || CPU(PPC64LE) || CPU(SH4) || CPU(S390) || CPU(S390X) || CPU(IA64) || CPU(ALPHA) || CPU(ARM64) || CPU(HPPA) || CPU(RISCV64) + #define DOUBLE_CONVERSION_CORRECT_DOUBLE_OPERATIONS 1 + #elif defined(_M_IX86) || defined(__i386__) + #if defined(_WIN32) + From 2211d123f85949f01915f9618888449d1ee93e5d Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 00:36:16 +0100 Subject: [PATCH 074/189] libksysguard: disable webengine on riscv64 for now --- srcpkgs/libksysguard/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/libksysguard/template b/srcpkgs/libksysguard/template index ad183e28bdfeb..88c1213e4f12e 100644 --- a/srcpkgs/libksysguard/template +++ b/srcpkgs/libksysguard/template @@ -20,7 +20,7 @@ build_options="webengine" if [ "$XBPS_TARGET_ENDIAN" = "le" ] && [ "$XBPS_TARGET_WORDSIZE" = "$XBPS_WORDSIZE" ]; then # qt5-webengine cannot be built for armv5tel case "$XBPS_TARGET_MACHINE" in - armv5tel*) ;; + armv5tel*|riscv64*) ;; *) build_options_default=webengine ;; esac fi From ced2ea2716c357171f594fe3059cd58406fba00a Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 00:59:59 +0100 Subject: [PATCH 075/189] debootstrap: add riscv64 arch --- srcpkgs/debootstrap/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/debootstrap/template b/srcpkgs/debootstrap/template index 6e5c17dc453db..fe58d22c42081 100644 --- a/srcpkgs/debootstrap/template +++ b/srcpkgs/debootstrap/template @@ -21,6 +21,7 @@ case "$XBPS_TARGET_MACHINE" in ppc64le*) _debarch=ppc64el;; ppc64*) _debarch=ppc64;; ppc*) _debarch=powerpc;; + riscv64*) _debarch=riscv64;; *) broken="please add your architecture";; esac From a650c2e4f717b267c46a56b341b446e02b0fc674 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 01:19:57 +0100 Subject: [PATCH 076/189] android-tools: whitelist riscv64 --- srcpkgs/android-tools/template | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/srcpkgs/android-tools/template b/srcpkgs/android-tools/template index 351bdfef88df6..9e3e81625481e 100644 --- a/srcpkgs/android-tools/template +++ b/srcpkgs/android-tools/template @@ -2,7 +2,8 @@ pkgname=android-tools version=34.0.1 revision=3 -archs="armv* aarch64* x86_64* i686* ppc64le*" +revision=2 +archs="armv* aarch64* x86_64* i686* ppc64le* riscv64*" build_style=cmake configure_args="-DGO_EXECUTABLE=/usr/bin/go1.20" hostmakedepends="perl go1.20 protobuf pkg-config" From b542501afcb61df0e515d205a6471907f832850f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 17 Jan 2023 21:33:10 +0100 Subject: [PATCH 077/189] kaccounts-providers: disable nextcloud on riscv64 --- srcpkgs/kaccounts-providers/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/kaccounts-providers/template b/srcpkgs/kaccounts-providers/template index 36e94fdfba315..139e735da27e6 100644 --- a/srcpkgs/kaccounts-providers/template +++ b/srcpkgs/kaccounts-providers/template @@ -18,7 +18,7 @@ checksum=c0a16a225a930f32438230fb4e3130674c375a26d1a0a205bdf6fa04b29135d3 build_options="nextcloud" desc_option_nextcloud="Build nextcloud support (needs Qt5 WebEngine)" -if [ "$XBPS_TARGET_ENDIAN" = "le" ]; then +if [ "$XBPS_TARGET_ENDIAN" = "le" ] && ! [ "${XBPS_TARGET_MACHINE/-musl/}" = "riscv64" ]; then if [ "$XBPS_WORDSIZE" = "$XBPS_TARGET_WORDSIZE" ]; then build_options_default+=" nextcloud" fi From e561aca3466bae65de54acba88260c0d074ff409 Mon Sep 17 00:00:00 2001 From: John Date: Wed, 18 Jan 2023 22:24:43 +0100 Subject: [PATCH 078/189] mozjs78: mark riscv64 as broken --- srcpkgs/mozjs78/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/mozjs78/template b/srcpkgs/mozjs78/template index b1309da0f3439..7af62925a9b01 100644 --- a/srcpkgs/mozjs78/template +++ b/srcpkgs/mozjs78/template @@ -26,6 +26,7 @@ fi case "$XBPS_TARGET_MACHINE" in mips*) broken="no matching function for call to 'js::jit::MacroAssembler::unboxInt32(const js::jit::BaseObjectElementIndex&, js::jit::Register&)'";; + riscv64*) broken="ValueError: Unknown CPU type: riscv64";; esac do_configure() { From 4573304199d7845b635053b3c8bc4ed30567e9bd Mon Sep 17 00:00:00 2001 From: John Date: Wed, 25 Jan 2023 14:37:29 +0100 Subject: [PATCH 079/189] nodejs: add riscv64 --- srcpkgs/nodejs/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/nodejs/template b/srcpkgs/nodejs/template index 31268b558f81b..fe055e8b8a82a 100644 --- a/srcpkgs/nodejs/template +++ b/srcpkgs/nodejs/template @@ -61,6 +61,7 @@ do_configure() { mips*) _args="--dest-cpu=mips" ;; i686*) _args="--dest-cpu=x86" ;; x86_64*) _args="--dest-cpu=x86_64" ;; + riscv64*) _args="--dest-cpu=riscv64" ;; *) msg_error "$pkgver: cannot be cross compiled for ${XBPS_TARGET_MACHINE}.\n" ;; esac # this is necessary - for example, normally compiling from ppc64le From 811edab9da002d2d49b19a6bf0da06c57dfbb282 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 17:09:21 +0100 Subject: [PATCH 080/189] ruby: add patch for riscv64 --- srcpkgs/ruby/patches/fix-riscv64-build.patch | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 srcpkgs/ruby/patches/fix-riscv64-build.patch diff --git a/srcpkgs/ruby/patches/fix-riscv64-build.patch b/srcpkgs/ruby/patches/fix-riscv64-build.patch new file mode 100644 index 0000000000000..e81e8b62c7820 --- /dev/null +++ b/srcpkgs/ruby/patches/fix-riscv64-build.patch @@ -0,0 +1,38 @@ +Patch-Source: https://lists.openembedded.org/g/openembedded-core/message/161168 +partially extracted to actually apply onto a release tarball + +--- +From dfb22e4d6662bf72879eda806eaa78c7b52b519e Mon Sep 17 00:00:00 2001 +From: Khem Raj +Date: Tue, 25 Jan 2022 20:29:14 -0800 +Subject: [PATCH] vm_dump.c: Define REG_S1 and REG_S2 for musl/riscv + +These defines are missing in musl, there is a possible +patch to add them to musl, but we need a full list of +these names for mcontext that can be added once for all + +Upstream-Status: Inappropriate [musl bug] +Signed-off-by: Khem Raj +--- + vm_dump.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/vm_dump.c b/vm_dump.c +index a98f5aa..957b785 100644 +--- a/vm_dump.c ++++ b/vm_dump.c +@@ -39,6 +39,11 @@ + + #define MAX_POSBUF 128 + ++#if defined(__riscv) && !defined(__GLIBC__) ++# define REG_S1 9 ++# define REG_S2 18 ++#endif ++ + #define VM_CFP_CNT(ec, cfp) \ + ((rb_control_frame_t *)((ec)->vm_stack + (ec)->vm_stack_size) - \ + (rb_control_frame_t *)(cfp)) +-- +2.35.0 + From 6e75c0e5dd4670f4ddb596594cecbf9a2c85de77 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 21:14:51 +0100 Subject: [PATCH 081/189] ltrace: set broken on riscv --- srcpkgs/ltrace/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/ltrace/template b/srcpkgs/ltrace/template index 20809864c1f76..40a337701f200 100644 --- a/srcpkgs/ltrace/template +++ b/srcpkgs/ltrace/template @@ -15,6 +15,10 @@ checksum=4aecf69e4a33331aed1e50ce4907e73a98cbccc4835febc3473863474304d547 CFLAGS="-Wno-error -D_GNU_SOURCE" +if [ "${XBPS_TARGET_MACHINE/-musl/}" = "riscv64" ]; do + broken="$XBPS_TARGET_MACHINE not supported" +done + pre_configure() { if [ "$XBPS_TARGET_LIBC" = "musl" ]; then sed -i '/HOST_OS/s/linux-uclibc/linux-musl/g' configure.ac From 5baa64fcd6027e5cc83add84e425602f9a03ce69 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 22:23:39 +0100 Subject: [PATCH 082/189] seaweedfs: mark broken on riscv64 --- srcpkgs/seaweedfs/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/seaweedfs/template b/srcpkgs/seaweedfs/template index a9580e76ad299..ee1fd50f264b5 100644 --- a/srcpkgs/seaweedfs/template +++ b/srcpkgs/seaweedfs/template @@ -14,4 +14,5 @@ checksum=9c44b65cdc7ba0e2a544c31aeed0acde0c0080439971212242588cad94cd600f case "$XBPS_TARGET_MACHINE" in ppc64*) broken="build constraints exclude all Go files in ...";; + riscv64*) broken="https://github.com/hashicorp/raft-boltdb/issues/27" esac From 1996a8654c41e43f9a29f0b0ccf6e0c90afe0e41 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 22:55:52 +0100 Subject: [PATCH 083/189] nebula: add patch for riscv64 --- srcpkgs/nebula/patches/riscv64.patch | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 srcpkgs/nebula/patches/riscv64.patch diff --git a/srcpkgs/nebula/patches/riscv64.patch b/srcpkgs/nebula/patches/riscv64.patch new file mode 100644 index 0000000000000..46ad32f397949 --- /dev/null +++ b/srcpkgs/nebula/patches/riscv64.patch @@ -0,0 +1,9 @@ +--- a/udp_linux_64.go 2021-05-11 03:23:49.000000000 +0200 ++++ - 2023-01-28 22:54:02.482711168 +0100 +@@ -1,5 +1,5 @@ + // +build linux +-// +build amd64 arm64 ppc64 ppc64le mips64 mips64le s390x ++// +build amd64 arm64 ppc64 ppc64le mips64 mips64le s390x riscv64 + // +build !android + // +build !e2e_testing + From 3c93742d04705b454c928202a36195357f315abb Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 22:58:28 +0100 Subject: [PATCH 084/189] qt5-webview: disable webengine on riscv64 --- srcpkgs/qt5-webview/template | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/srcpkgs/qt5-webview/template b/srcpkgs/qt5-webview/template index 6464f10660406..3a407a613b71a 100644 --- a/srcpkgs/qt5-webview/template +++ b/srcpkgs/qt5-webview/template @@ -16,7 +16,10 @@ checksum=49f7c087e8e3662adf3c271c41c629e547f02b82b305641148f07170d4ea1a67 build_options="webengine" if [ "$XBPS_TARGET_ENDIAN" = "le" ] && [ "$XBPS_WORDSIZE" = "$XBPS_TARGET_WORDSIZE" ]; then - build_options_default="webengine" + case "$XBPS_TARGET_MACHINE" in + armv5tel*|riscv*);; + *) build_options_default="webengine";; + esac fi post_extract() { From ff6fc42d643dc22440cfdaea13001fd20acbd0f8 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 22:58:42 +0100 Subject: [PATCH 085/189] qtcreator: disable webengine on riscv64 --- srcpkgs/qtcreator/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/qtcreator/template b/srcpkgs/qtcreator/template index 0edbb7ec7d0b9..58bfba3c33039 100644 --- a/srcpkgs/qtcreator/template +++ b/srcpkgs/qtcreator/template @@ -64,7 +64,7 @@ qtcreator-qt5_package() { if [ "$XBPS_TARGET_ENDIAN" = "le" -a "$XBPS_TARGET_WORDSIZE" = "$XBPS_WORDSIZE" ]; then # qt5-webengine cannot be built for armv5tel case "$XBPS_TARGET_MACHINE" in - armv5tel*) ;; + armv5tel*|riscv*) ;; *) depends+=" qt5-webengine-devel" ;; esac fi From d7bdbf62c1b1a3f7601f28618f009d838c411647 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 23:16:58 +0100 Subject: [PATCH 086/189] fs-repo-migrations: don't build for riscv64 --- srcpkgs/fs-repo-migrations/template | 2 ++ 1 file changed, 2 insertions(+) diff --git a/srcpkgs/fs-repo-migrations/template b/srcpkgs/fs-repo-migrations/template index 00b9072beec5a..1faf0d0b7f105 100644 --- a/srcpkgs/fs-repo-migrations/template +++ b/srcpkgs/fs-repo-migrations/template @@ -2,6 +2,8 @@ pkgname=fs-repo-migrations version=1.7.1 revision=3 +# Many things don't seem to be ported to riscv (yet) +archs="~riscv64*" build_style=go go_import_path="github.com/ipfs/fs-repo-migrations" short_desc="Tool to upgrade the IPFS filesystem repository" From 1481eeddcd290e4eebbcbec434ffca0b6b08dc92 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 23:54:16 +0100 Subject: [PATCH 087/189] minio: don't build for riscv64 --- srcpkgs/minio/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/minio/template b/srcpkgs/minio/template index 1cde67ee210dd..68196176234df 100644 --- a/srcpkgs/minio/template +++ b/srcpkgs/minio/template @@ -3,6 +3,7 @@ pkgname=minio version=2021.04.06 revision=3 _version="${version//./-}T23-11-00Z" +archs="~riscv64*" # procfs@v0.2.0 doesn't fully support riscv build_style=go go_import_path="github.com/minio/minio" conf_files="/etc/default/minio /etc/minio/config.json" From d5ff194652b455379e4558839a0ce3e7b5b71724 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 28 Jan 2023 23:59:41 +0100 Subject: [PATCH 088/189] thunderbird: mark broken for riscv64 for now --- srcpkgs/thunderbird/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/thunderbird/template b/srcpkgs/thunderbird/template index e278af633cd67..5cf8fed820df9 100644 --- a/srcpkgs/thunderbird/template +++ b/srcpkgs/thunderbird/template @@ -33,6 +33,7 @@ case $XBPS_TARGET_MACHINE in armv[56]*) broken="required NEON extensions are not supported on armv6" ;; ppc64*) ;; ppc*) broken="xptcall bitrot" ;; + riscv64*) broken="Some rust crates need updating" ;; esac # try to minimize memory usage via debug symbols From b5519b9835f6becfafb1feb8892302f34d22434b Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:02:46 +0100 Subject: [PATCH 089/189] a2jmidid: add riscv64 patch --- srcpkgs/a2jmidid/patches/riscv64.patch | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 srcpkgs/a2jmidid/patches/riscv64.patch diff --git a/srcpkgs/a2jmidid/patches/riscv64.patch b/srcpkgs/a2jmidid/patches/riscv64.patch new file mode 100644 index 0000000000000..2b9e2ed1c5a1d --- /dev/null +++ b/srcpkgs/a2jmidid/patches/riscv64.patch @@ -0,0 +1,44 @@ +From 2c3fbef6854743416d95d85b1565dde51668488c Mon Sep 17 00:00:00 2001 +From: Heinrich Schuchardt +Date: Fri, 1 Oct 2021 16:15:29 +0200 +Subject: [PATCH] sigsegv: enable RISC-V build +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Avoid build error + +../sigsegv.c:104:39: error: ‘mcontext_t’ has no member named ‘gregs’; +did you mean ‘__gregs’? + 104 | ucontext->uc_mcontext.gregs[i] + | ^~~~~ + +Signed-off-by: Heinrich Schuchardt +--- + sigsegv.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/sigsegv.c b/sigsegv.c +index fb4456e..6930185 100644 +--- a/sigsegv.c ++++ b/sigsegv.c +@@ -91,7 +91,9 @@ static void signal_segv(int signum, siginfo_t* info, void*ptr) { + a2j_error("info.si_errno = %d", info->si_errno); + a2j_error("info.si_code = %d (%s)", info->si_code, si_codes[info->si_code]); + a2j_error("info.si_addr = %p", info->si_addr); +-#if !defined(__alpha__) && !defined(__ia64__) && !defined(__FreeBSD_kernel__) && !defined(__arm__) && !defined(__hppa__) && !defined(__sh__) && !defined(__aarch64__) ++#if !defined(__alpha__) && !defined(__ia64__) && \ ++ !defined(__FreeBSD_kernel__) && !defined(__arm__) && !defined(__hppa__) && \ ++ !defined(__sh__) && !defined(__aarch64__) && !defined(__riscv) + for(i = 0; i < NGREG; i++) + a2j_error("reg[%02d] = 0x" REGFORMAT, i, + #if defined(__powerpc__) && !defined(__powerpc64__) +@@ -108,7 +110,7 @@ static void signal_segv(int signum, siginfo_t* info, void*ptr) { + ucontext->uc_mcontext.gregs[i] + #endif + ); +-#endif /* alpha, ia64, kFreeBSD, arm, hppa, aarch64 */ ++#endif /* alpha, ia64, kFreeBSD, arm, hppa, aarch64, riscv */ + + #if defined(SIGSEGV_STACK_X86) || defined(SIGSEGV_STACK_IA64) + # if defined(SIGSEGV_STACK_IA64) From 1cf2e473b46ba1f015bdb12ca6f95a368128815e Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:09:46 +0100 Subject: [PATCH 090/189] ladish: add riscv64 patch --- srcpkgs/ladish/patches/aarch64.patch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/ladish/patches/aarch64.patch b/srcpkgs/ladish/patches/aarch64.patch index 3385f41871ef0..97a69923e81c5 100644 --- a/srcpkgs/ladish/patches/aarch64.patch +++ b/srcpkgs/ladish/patches/aarch64.patch @@ -5,7 +5,7 @@ #endif -#if defined(__arm__) || defined(__powerpc__) || defined (__ia64__) || defined (__alpha__) || defined (__FreeBSD_kernel__) || defined (__sh__) -+#if defined(__arm__) || defined(__aarch64__) || defined(__powerpc__) || defined (__ia64__) || defined (__alpha__) || defined (__FreeBSD_kernel__) || defined (__sh__) ++#if defined(__arm__) || defined(__aarch64__) || defined(__powerpc__) || defined (__ia64__) || defined (__alpha__) || defined (__FreeBSD_kernel__) || defined (__sh__) || defined(__riscv) # define DISABLE_STACKTRACE #endif From 5807a11919d7e5abc41877e4f63b7a0c3d87130b Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:31:32 +0100 Subject: [PATCH 091/189] exa: update libc crate for riscv64 compat --- srcpkgs/exa/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/exa/template b/srcpkgs/exa/template index 89bf6611d9fbc..11e5ea789d394 100644 --- a/srcpkgs/exa/template +++ b/srcpkgs/exa/template @@ -22,6 +22,11 @@ post_extract() { mv man "${build_wrksrc}/accoutrements/" } +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vcompletion completions/completions.bash bash vcompletion completions/completions.fish fish From 27f2661707cb04b5d59f1530d47674497b7791f0 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:36:24 +0100 Subject: [PATCH 092/189] acbuild: add riscv64 patch --- srcpkgs/acbuild/patches/riscv64.patch | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 srcpkgs/acbuild/patches/riscv64.patch diff --git a/srcpkgs/acbuild/patches/riscv64.patch b/srcpkgs/acbuild/patches/riscv64.patch new file mode 100644 index 0000000000000..fefe18bb50668 --- /dev/null +++ b/srcpkgs/acbuild/patches/riscv64.patch @@ -0,0 +1,26 @@ +--- /dev/null 2023-01-28 12:09:12.164165019 +0100 ++++ acbuild-0.4.0/vendor/github.com/coreos/rkt/pkg/sys/sys_linux_riscv64.go 2023-01-29 00:35:19.504891546 +0100 +@@ -0,0 +1,23 @@ ++// Copyright 2015 The rkt Authors ++// ++// Licensed under the Apache License, Version 2.0 (the "License"); ++// you may not use this file except in compliance with the License. ++// You may obtain a copy of the License at ++// ++// http://www.apache.org/licenses/LICENSE-2.0 ++// ++// Unless required by applicable law or agreed to in writing, software ++// distributed under the License is distributed on an "AS IS" BASIS, ++// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ++// See the License for the specific language governing permissions and ++// limitations under the License. ++ ++// +build linux,riscv64 ++ ++package sys ++ ++import "syscall" ++ ++const ( ++ SYS_SYNCFS = syscall.SYS_SYNCFS ++) From aff7b6fd1dc1946d69d20160e954b3f64b9a9a35 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:43:53 +0100 Subject: [PATCH 093/189] xq-api: mark broken on riscv64 --- srcpkgs/xq-api/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/xq-api/template b/srcpkgs/xq-api/template index b159653ea4bb0..daabf3dfe3a4a 100644 --- a/srcpkgs/xq-api/template +++ b/srcpkgs/xq-api/template @@ -15,6 +15,10 @@ checksum=087940a16830eaf821abfcb8c6e0daad47078b4859b9acf236464bfca809ed43 system_accounts="_xqapi" _xqapi_homedir="/var/lib/xq-api" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Uses old vendored broken sys/unix dep";; +esac + post_install() { vman xq-api.8 vlicense COPYING NOTICE From 55e77a5f1c20a9dcb7d4af05905b0e64b0c05075 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 00:45:08 +0100 Subject: [PATCH 094/189] fool: update libc crate for riscv64 compat --- srcpkgs/fool/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/fool/template b/srcpkgs/fool/template index 1008b78660486..7c0e6c1342b3c 100644 --- a/srcpkgs/fool/template +++ b/srcpkgs/fool/template @@ -12,8 +12,8 @@ distfiles="https://github.com/spacekookie/fool/archive/v${version}.tar.gz" checksum=41fa1a10a3b3cadba4700b809df13df9ed109ecc5c54ba8b645269abff84a41a pre_build() { - # default version too old for ppc musl systems - cargo update --package libc@0.2.34 --precise 0.2.66 + # default version too old for ppc musl and riscv64 systems + cargo update --package libc@0.2.34 --precise 0.2.139 } post_install() { From ab396a5a11d60217c95f20426d477787feccead6 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:09:48 +0100 Subject: [PATCH 095/189] nmon: mark broken on unsupported archs --- srcpkgs/nmon/template | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/srcpkgs/nmon/template b/srcpkgs/nmon/template index 790ed6d8d5c9d..862680686d06c 100644 --- a/srcpkgs/nmon/template +++ b/srcpkgs/nmon/template @@ -12,12 +12,14 @@ homepage="http://nmon.sourceforge.net/pmwiki.php?n=Main.HomePage" distfiles="${SOURCEFORGE_SITE}/nmon/files/lmon${version}.c" checksum=c0012cc2d925dee940c37ceae297abac64ba5a5c30e575e7418b04028613f5f2 +case "$XBPS_TARGET_MACHINE" in + ppc*) _ARCH="POWER" ;; + arm*|aarch64*) _ARCH="ARM" ;; + i686*|x86_64*) _ARCH="X86" ;; + *) broken="$XBPS_TARGET_MACHINE is unsupprted" +esac + do_build() { - case "$XBPS_TARGET_MACHINE" in - ppc*) _ARCH="POWER" ;; - arm*|aarch64*) _ARCH="ARM" ;; - i686*|x86_64*) _ARCH="X86" ;; - esac $CC ${CFLAGS} ${LDFLAGS} -D $_ARCH \ lmon${version}.c -lncurses -lm -o nmon } From cc36e84a4564d7cd595ae065acba2abeb43ad96c Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:10:47 +0100 Subject: [PATCH 096/189] valgrind: mark broken on riscv64 --- srcpkgs/valgrind/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/valgrind/template b/srcpkgs/valgrind/template index 6572a5483e52b..9abd2e2b40d20 100644 --- a/srcpkgs/valgrind/template +++ b/srcpkgs/valgrind/template @@ -35,7 +35,7 @@ lib32symlinks=" valgrind/none-x86-linux" case $XBPS_TARGET_MACHINE in - armv6*) broken="Unsupported architecture";; + armv6*|riscv64*) broken="Unsupported architecture";; esac if [ "$XBPS_TARGET_MACHINE" = "armv7l" ]; then From 4925e4826825f482c3da13b60d5415cd7e1915d2 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:12:02 +0100 Subject: [PATCH 097/189] xsv: update libc crate for riscv64 compat --- srcpkgs/xsv/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/xsv/template b/srcpkgs/xsv/template index 8724d22dab6e6..debc81e671bc1 100644 --- a/srcpkgs/xsv/template +++ b/srcpkgs/xsv/template @@ -11,8 +11,8 @@ distfiles="https://github.com/BurntSushi/${pkgname}/archive/${version}.tar.gz" checksum=2b75309b764c9f2f3fdc1dd31eeea5a74498f7da21ae757b3ffd6fd537ec5345 pre_build() { - # default version too old for ppc musl systems - cargo update --package libc@0.2.40 --precise 0.2.66 + # default version too old for ppc musl and riscv64 systems + cargo update --package libc@0.2.40 --precise 0.2.139 } post_install() { From 51bc1af6a759456815669dec30229354ce744e90 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:16:42 +0100 Subject: [PATCH 098/189] texlive: disable LuaJIT on riscv64 --- srcpkgs/texlive/template | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/srcpkgs/texlive/template b/srcpkgs/texlive/template index cd7ab47a061ab..b71fc59333d90 100644 --- a/srcpkgs/texlive/template +++ b/srcpkgs/texlive/template @@ -106,7 +106,9 @@ if [ "$XBPS_WORDSIZE" != "$XBPS_TARGET_WORDSIZE" ] ; then esac fi -if [ "${_luajit_host_cc}" != "broken" ] ; then +if [ "${_luajit_host_cc}" != "broken" ] && \ + ! [ "${XBPS_TARGET_MACHINE/-musl/}" = "riscv64" ] && \ + ! [ "${XBPS_MACHINE/-musl/}" = "riscv64" ]; then build_options_default+=" luajit" fi From 8a189d9864b5026d8d112c9bebe7e95459c788dc Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:33:27 +0100 Subject: [PATCH 099/189] otfcc: add riscv64 support --- srcpkgs/otfcc/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/otfcc/template b/srcpkgs/otfcc/template index a0a82674f7f73..736b74a47e9ed 100644 --- a/srcpkgs/otfcc/template +++ b/srcpkgs/otfcc/template @@ -14,7 +14,7 @@ checksum=d9c74825ddac700eb429de31de7cb0a249636f47c6a4cc64eaa102a40966cf00 # Yes, there are architectures besides x86 and x64 :-P case "$XBPS_TARGET_MACHINE" in - aarch64*|x86_64*|ppc64*) _platform="x64" ;; + aarch64*|x86_64*|ppc64*|riscv64*) _platform="x64" ;; arm*|i686*|mips*|ppc*) _platform="x86";; esac From 92569356b8a3655ee7880770b6992b1163a7161f Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:38:17 +0100 Subject: [PATCH 100/189] makedumpfile: disable on riscv64 --- srcpkgs/makedumpfile/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/makedumpfile/template b/srcpkgs/makedumpfile/template index 1744b94a78277..93627467501bd 100644 --- a/srcpkgs/makedumpfile/template +++ b/srcpkgs/makedumpfile/template @@ -2,6 +2,7 @@ pkgname=makedumpfile version=1.7.3 revision=1 +archs="~riscv64*" makedepends="elfutils-devel zlib-devel bzip2-devel liblzma-devel lzo-devel" depends="perl" short_desc="Make a small dumpfile of kdump" From 53d71d8467421a02abcf6604eba9ea4d717b913e Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:40:53 +0100 Subject: [PATCH 101/189] python3-mitmproxy_wireguard: mark broken on riscv64 --- srcpkgs/python3-mitmproxy_wireguard/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/python3-mitmproxy_wireguard/template b/srcpkgs/python3-mitmproxy_wireguard/template index bfa34a389a294..fd49015fb4d07 100644 --- a/srcpkgs/python3-mitmproxy_wireguard/template +++ b/srcpkgs/python3-mitmproxy_wireguard/template @@ -15,6 +15,10 @@ changelog="https://raw.githubusercontent.com/decathorpe/mitmproxy_wireguard/main distfiles="https://github.com/decathorpe/mitmproxy_wireguard/archive/${version}.tar.gz" checksum=749b5b45222b629f4cced154cc4bf70ba7ae3061db02e2ea0ae45a4ae6246463 +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="ring v0.16.20 doesn't support $XBPS_TARGET_MACHINE" +esac + do_build() { if [ "$CROSS_BUILD" ]; then export PYO3_CROSS_LIB_DIR="${XBPS_CROSS_BASE}/usr/lib" From 01cb3cd60ae6b10cd51bb759c0b431df91ea9600 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:44:04 +0100 Subject: [PATCH 102/189] gotty: mark broken on riscv64 --- srcpkgs/gotty/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/gotty/template b/srcpkgs/gotty/template index 655809e9d66b9..14a1ecd662e17 100644 --- a/srcpkgs/gotty/template +++ b/srcpkgs/gotty/template @@ -11,6 +11,10 @@ homepage="https://github.com/yudai/gotty/" distfiles="https://github.com/yudai/gotty/archive/v${version}.tar.gz" checksum=32695d70a79f55efdf4fba6f06f830515a2055abc58fc15e2124dff5be75695b +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="_build-gotty-xbps/src/github.com/yudai/gotty/vendor/github.com/kr/pty/pty_linux.go:34:8: undefined: _C_uint" +esac + post_install() { vlicense LICENSE } From 87c09c44d782ca8e73ae4f51c6ab13a539e9953c Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:45:12 +0100 Subject: [PATCH 103/189] licensor: update libc crate for riscv64 compat --- srcpkgs/licensor/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/licensor/template b/srcpkgs/licensor/template index 5e99091d5ea51..c907060506be0 100644 --- a/srcpkgs/licensor/template +++ b/srcpkgs/licensor/template @@ -10,6 +10,11 @@ homepage="https://github.com/raftario/licensor" distfiles="https://github.com/raftario/licensor/archive/v${version}.tar.gz" checksum=d061ce9fd26d58b0c6ababa7acdaf35222a4407f0b5ea9c4b78f6835527611fd +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From e127d664c56faf7f891cbaa2c5232c54b628f6ef Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 13:48:33 +0100 Subject: [PATCH 104/189] kcov: add riscv64 patch --- srcpkgs/kcov/patches/riscv64.patch | 67 ++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 srcpkgs/kcov/patches/riscv64.patch diff --git a/srcpkgs/kcov/patches/riscv64.patch b/srcpkgs/kcov/patches/riscv64.patch new file mode 100644 index 0000000000000..9c5fe9971dd06 --- /dev/null +++ b/srcpkgs/kcov/patches/riscv64.patch @@ -0,0 +1,67 @@ +From 3c4358ae63e13bbcebf00e5a933bc214e431654c Mon Sep 17 00:00:00 2001 +From: rvalue +Date: Tue, 27 Sep 2022 11:32:15 +0200 +Subject: [PATCH] Add basic support for RISC-V architecture + +--- + src/engines/ptrace.cc | 2 ++ + src/engines/ptrace_linux.cc | 5 ++++- + src/solib-parser/lib.c | 2 ++ + 3 files changed, 8 insertions(+), 1 deletion(-) + +diff --git a/src/engines/ptrace.cc b/src/engines/ptrace.cc +index ddcbe422..76767511 100644 +--- a/src/engines/ptrace.cc ++++ b/src/engines/ptrace.cc +@@ -50,6 +50,8 @@ static unsigned long arch_setupBreakpoint(unsigned long addr, unsigned long old_ + unsigned long shift = 8 * offs; + + val = (old_data & ~(0xffffffffUL << shift)) | (0xd4200000UL << shift); ++#elif defined(__riscv) ++ val = 0x00100073; /* ebreak */ // No width problem, prefer ebreak than c.ebreak for ISA w/o C extension. + #else + # error Unsupported architecture + #endif +diff --git a/src/engines/ptrace_linux.cc b/src/engines/ptrace_linux.cc +index bd25d0ef..4062a06f 100644 +--- a/src/engines/ptrace_linux.cc ++++ b/src/engines/ptrace_linux.cc +@@ -20,6 +20,7 @@ + enum + { + i386_EIP = 12, x86_64_RIP = 16, ppc_NIP = 32, arm_PC = 15, aarch64_PC = 32, // See Linux arch/arm64/include/asm/ptrace.h ++ riscv_EPC = 0 + }; + + static void arch_adjustPcAfterBreakpoint(unsigned long *regs); +@@ -40,7 +41,7 @@ static void arch_adjustPcAfterBreakpoint(unsigned long *regs) + regs[i386_EIP]--; + #elif defined(__x86_64__) + regs[x86_64_RIP]--; +-#elif defined(__powerpc__) || defined(__arm__) || defined(__aarch64__) ++#elif defined(__powerpc__) || defined(__arm__) || defined(__aarch64__) || defined(__riscv) + // Do nothing + #else + # error Unsupported architecture +@@ -61,6 +62,8 @@ static unsigned long arch_getPcFromRegs(unsigned long *regs) + out = regs[aarch64_PC]; + #elif defined(__powerpc__) + out = regs[ppc_NIP]; ++#elif defined(__riscv) ++ out = regs[riscv_EPC]; + #else + # error Unsupported architecture + #endif +diff --git a/src/solib-parser/lib.c b/src/solib-parser/lib.c +index 1aa8730d..87a23447 100644 +--- a/src/solib-parser/lib.c ++++ b/src/solib-parser/lib.c +@@ -95,6 +95,8 @@ static void force_breakpoint(void) + ".long 0xfedeffe7\n" /* undefined insn */ + #elif defined(__aarch64__) + ".long 0xd4200000\n" /* From https://github.com/scottt/debugbreak */ ++#elif defined(__riscv) ++ "ebreak\n" + #else + # error Unsupported architecture + #endif From 26ca4ab3936f1b6cb40ef09c2dc0e4f092797e63 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:04:42 +0100 Subject: [PATCH 105/189] hex: update libc crate for riscv64 compat --- srcpkgs/hex/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/hex/template b/srcpkgs/hex/template index 441aad4d3c140..38d4b0cbea51f 100644 --- a/srcpkgs/hex/template +++ b/srcpkgs/hex/template @@ -10,6 +10,11 @@ homepage="https://github.com/sitkevij/hex" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=a7cc1ece337fc19e77fbbbca145001bc5d447bde4118eb6de2c99407eb1a3b74 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { # avoid conflict with helix mv ${DESTDIR}/usr/bin/hx ${DESTDIR}/usr/bin/hex From 8cec4c7386b1627587371333932418a9b4ccc2d4 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:05:27 +0100 Subject: [PATCH 106/189] glider: disable on riscv64 --- srcpkgs/glider/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/glider/template b/srcpkgs/glider/template index c1037e2444a82..9325a8f16dced 100644 --- a/srcpkgs/glider/template +++ b/srcpkgs/glider/template @@ -2,6 +2,7 @@ pkgname=glider version=0.13.0 revision=3 +archs="~riscv64*" build_style=go go_import_path=github.com/nadoo/glider short_desc="Forward proxy with multiple protocols support" From 9af07fa8e5ac54e61873d10a464554004684acf3 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:09:36 +0100 Subject: [PATCH 107/189] git-series: update libc crate for riscv64 compat --- srcpkgs/git-series/template | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/srcpkgs/git-series/template b/srcpkgs/git-series/template index 365dc53ab02d9..42e62b4f83cab 100644 --- a/srcpkgs/git-series/template +++ b/srcpkgs/git-series/template @@ -14,7 +14,8 @@ distfiles="https://github.com/git-series/git-series/archive/refs/tags/${version} checksum=c0362e19d3fa168a7cb0e260fcdecfe070853b163c9f2dfd2ad8213289bc7e5f post_extract() { - cargo update --package libc@0.2.17 --precise 0.2.55 + # Newer libc needed for riscv64 + cargo update --package libc@0.2.17 --precise 0.2.139 cargo update --package url@1.2.3 --precise 1.7.2 cargo update --package openssl-sys@0.9.1 --precise 0.9.60 } From fd6cefc788a96fec2b7708c382f99758d98fcda6 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:13:13 +0100 Subject: [PATCH 108/189] drive: mark broken on riscv64 --- srcpkgs/drive/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/drive/template b/srcpkgs/drive/template index f77f9066951aa..31289f7d5c2e0 100644 --- a/srcpkgs/drive/template +++ b/srcpkgs/drive/template @@ -13,6 +13,10 @@ homepage="https://github.com/odeke-em/drive" distfiles="$homepage/archive/v$version.tar.gz" checksum=7a6445b54c6c13d0ddd8893ca02264211eeea68c7a0c7e9ccc6473f68af40a00 +case $XBPS_TARGET_MACHINE in + riscv64*) broken="Uses boltdb";; +esac + post_install() { vdoc README.md } From 623de01653b07d4c72422f7f1a2bbbfc0e1cb68f Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:22:27 +0100 Subject: [PATCH 109/189] ripgrep: update libc crate for riscv64 compat --- srcpkgs/ripgrep/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/ripgrep/template b/srcpkgs/ripgrep/template index ba4a48a42fb61..883cd105872fc 100644 --- a/srcpkgs/ripgrep/template +++ b/srcpkgs/ripgrep/template @@ -13,6 +13,11 @@ homepage="https://github.com/BurntSushi/ripgrep/" distfiles="https://github.com/BurntSushi/${pkgname}/archive/${version}.tar.gz" checksum=0fb17aaf285b3eee8ddab17b833af1e190d73de317ff9648751ab0660d763ed2 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE-MIT vlicense UNLICENSE From 6c91ec7a11d96fe8d7f107748fd080793e4c17d0 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 29 Jan 2023 14:25:32 +0100 Subject: [PATCH 110/189] angle-grinder: update libc crate for riscv64 compat --- srcpkgs/angle-grinder/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/angle-grinder/template b/srcpkgs/angle-grinder/template index b99d65270d170..8717490285669 100644 --- a/srcpkgs/angle-grinder/template +++ b/srcpkgs/angle-grinder/template @@ -15,6 +15,11 @@ pre_configure() { cargo update -p h2 -p crossbeam-channel } +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From 37bf475ce940f6da285edefabbe046bdd36adadf Mon Sep 17 00:00:00 2001 From: John Date: Tue, 31 Jan 2023 23:19:10 +0100 Subject: [PATCH 111/189] papi: mark broken in riscv64 --- srcpkgs/papi/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/papi/template b/srcpkgs/papi/template index b343a6e363739..83c5b1b4a8824 100644 --- a/srcpkgs/papi/template +++ b/srcpkgs/papi/template @@ -20,6 +20,7 @@ fi case "$XBPS_TARGET_MACHINE" in ppc*-musl) broken="requires non-standard __ppc_get_timebase_freq";; + riscv*) broken="unsupported by papi" esac post_install() { From f8853fb0a4bc6fd4bfa01ef536af53e4b441f7e5 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 31 Jan 2023 23:34:05 +0100 Subject: [PATCH 112/189] tbb: add riscv64 to template --- srcpkgs/tbb/template | 3 +++ 1 file changed, 3 insertions(+) diff --git a/srcpkgs/tbb/template b/srcpkgs/tbb/template index 250561cde8e70..33a61b840f580 100644 --- a/srcpkgs/tbb/template +++ b/srcpkgs/tbb/template @@ -33,6 +33,9 @@ case "$XBPS_TARGET_MACHINE" in ppc*) make_build_args="arch=ppc32" ;; + riscv64*) + make_build_args="arch=riscv64" + ;; *) # make sure to fall back instead of letting host uname control it make_build_args="arch=generic" From 703b4de4ee5c1fdf268c7c89a3c01655563d513f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 31 Jan 2023 23:39:53 +0100 Subject: [PATCH 113/189] diskus: update libc crate for riscv64 compat --- srcpkgs/diskus/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/diskus/template b/srcpkgs/diskus/template index bdc028731925e..089b1f5717b39 100644 --- a/srcpkgs/diskus/template +++ b/srcpkgs/diskus/template @@ -10,6 +10,11 @@ homepage="https://github.com/sharkdp/diskus" distfiles="https://github.com/sharkdp/diskus/archive/v${version}.tar.gz" checksum=64b1b2e397ef4de81ea20274f98ec418b0fe19b025860e33beaba5494d3b8bd1 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE-MIT } From c11cc6ccf94837fe9b14c3c541cb8de9f9f23fbe Mon Sep 17 00:00:00 2001 From: John Date: Tue, 31 Jan 2023 23:50:32 +0100 Subject: [PATCH 114/189] helvum: mark broken on riscv64-musl --- srcpkgs/helvum/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/helvum/template b/srcpkgs/helvum/template index 1f3c89a66717c..be28ed533d392 100644 --- a/srcpkgs/helvum/template +++ b/srcpkgs/helvum/template @@ -13,6 +13,10 @@ homepage="https://gitlab.freedesktop.org/pipewire/helvum" distfiles="https://gitlab.freedesktop.org/pipewire/helvum/-/archive/${version}/helvum-${version}.tar.gz" checksum=e93afa788d3e50bae489db888ecf0d79e5735b8f4f8b29fe4174540b0872b622 +case "$XBPS_TARGET_MACHINE" in + riscv64-musl) broken="Old nix crate" ;; +esac + post_install() { # Normally, meson would do this, but it's simpler to use the cargo build style and do this manually # This also avoids the need for makedeps/build steps that are made unnecessary by xbps' hooks From 3b758f3e304cc3aa0b8194c789177ad89a35b023 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 31 Jan 2023 23:59:01 +0100 Subject: [PATCH 115/189] libticables2: add riscv64 patch --- .../patches/{ppc64le.patch => ppc64le-riscv64.patch} | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) rename srcpkgs/libticables2/patches/{ppc64le.patch => ppc64le-riscv64.patch} (84%) diff --git a/srcpkgs/libticables2/patches/ppc64le.patch b/srcpkgs/libticables2/patches/ppc64le-riscv64.patch similarity index 84% rename from srcpkgs/libticables2/patches/ppc64le.patch rename to srcpkgs/libticables2/patches/ppc64le-riscv64.patch index 009fb9a61febb..c44d1417055dc 100644 --- a/srcpkgs/libticables2/patches/ppc64le.patch +++ b/srcpkgs/libticables2/patches/ppc64le-riscv64.patch @@ -1,11 +1,12 @@ --- a/configure.ac +++ b/configure.ac -@@ -159,7 +159,7 @@ case "$host" in +@@ -159,7 +159,8 @@ case "$host" in mips-*-linux-*) ARCH="-D__MIPS__ -D__LINUX__" ;; mipsel-*-linux-*) ARCH="-D__MIPS__ -D__LINUX__" ;; powerpc-*-linux-*) ARCH="-D__PPC__ -D__LINUX__" ;; - powerpc64-*-linux-*) ARCH="-D__PPC__ -D__LINUX__" ;; + powerpc64*-*-linux-*) ARCH="-D__PPC__ -D__LINUX__" ;; ++ riscv64*-*-linux-*) ARCH="-D__riscv__ -D__LINUX__" ;; powerpc-apple-darwin*) ARCH="-D__PPC__ -D__MACOSX__" ;; powerpc64-apple-darwin*) ARCH="-D__PPC__ -D__MACOSX__" ;; s390*-*-linux-*) ARCH="-D__LINUX__" ;; From 2afb99aa51b137a5788bef0d031f05f71449bf5f Mon Sep 17 00:00:00 2001 From: John Date: Fri, 3 Feb 2023 00:13:22 +0100 Subject: [PATCH 116/189] Revert "qt5-webview: disable webengine on riscv64" This reverts commit 2c9e14d8083fda9416dd515602c5bcf379582130. --- srcpkgs/qt5-webview/template | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/srcpkgs/qt5-webview/template b/srcpkgs/qt5-webview/template index 3a407a613b71a..6464f10660406 100644 --- a/srcpkgs/qt5-webview/template +++ b/srcpkgs/qt5-webview/template @@ -16,10 +16,7 @@ checksum=49f7c087e8e3662adf3c271c41c629e547f02b82b305641148f07170d4ea1a67 build_options="webengine" if [ "$XBPS_TARGET_ENDIAN" = "le" ] && [ "$XBPS_WORDSIZE" = "$XBPS_TARGET_WORDSIZE" ]; then - case "$XBPS_TARGET_MACHINE" in - armv5tel*|riscv*);; - *) build_options_default="webengine";; - esac + build_options_default="webengine" fi post_extract() { From 926beb52b9f2bc808cf8f98ff40bdf72734fd807 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 3 Feb 2023 00:13:37 +0100 Subject: [PATCH 117/189] Revert "libksysguard: disable webengine on riscv64 for now" This reverts commit 91919f964659f91f63bd43d86121c9d460f8b850. --- srcpkgs/libksysguard/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/libksysguard/template b/srcpkgs/libksysguard/template index 88c1213e4f12e..ad183e28bdfeb 100644 --- a/srcpkgs/libksysguard/template +++ b/srcpkgs/libksysguard/template @@ -20,7 +20,7 @@ build_options="webengine" if [ "$XBPS_TARGET_ENDIAN" = "le" ] && [ "$XBPS_TARGET_WORDSIZE" = "$XBPS_WORDSIZE" ]; then # qt5-webengine cannot be built for armv5tel case "$XBPS_TARGET_MACHINE" in - armv5tel*|riscv64*) ;; + armv5tel*) ;; *) build_options_default=webengine ;; esac fi From 54b16ce81d03223c30327aca9444dc9fe979a5ca Mon Sep 17 00:00:00 2001 From: John Date: Sat, 4 Feb 2023 16:58:46 +0100 Subject: [PATCH 118/189] linux6.1: add riscv dotconfig --- srcpkgs/linux6.1/files/riscv-dotconfig | 10182 +++++++++++++++++++++++ srcpkgs/linux6.1/template | 11 +- 2 files changed, 10192 insertions(+), 1 deletion(-) create mode 100644 srcpkgs/linux6.1/files/riscv-dotconfig diff --git a/srcpkgs/linux6.1/files/riscv-dotconfig b/srcpkgs/linux6.1/files/riscv-dotconfig new file mode 100644 index 0000000000000..d1f6815a6fcfc --- /dev/null +++ b/srcpkgs/linux6.1/files/riscv-dotconfig @@ -0,0 +1,10182 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 6.1.12 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (GCC) 12.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=120200 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23900 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23900 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=123 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="_1" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_WATCH_QUEUE=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_SIM=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ_FULL=y +CONFIG_CONTEXT_TRACKING_USER=y +CONFIG_CONTEXT_TRACKING_USER_FORCE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_LSM=y +# end of BPF subsystem + +CONFIG_PREEMPT_VOLUNTARY_BUILD=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_GCC12_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_MEMCG=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_AS_HAS_INSN=y + +# +# SoC selection +# +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SOC_SIFIVE=y +CONFIG_SOC_STARFIVE=y +CONFIG_SOC_VIRT=y +# end of SoC selection + +# +# CPU errata selection +# +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +# CONFIG_ERRATA_THEAD is not set +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_NONPORTABLE is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_SMP=y +CONFIG_NR_CPUS=480 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_TOOLCHAIN_HAS_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_RISCV_SBI_V01 is not set +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_KEXEC=y +# CONFIG_KEXEC_FILE is not set +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Boot options + +CONFIG_PORTABLE=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_DPM_WATCHDOG=y +CONFIG_DPM_WATCHDOG_TIMEOUT=60 +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle +# end of CPU Power Management + +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_KVM_XFER_TO_GUEST_WORK=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_MQ_RDMA=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_DEFERRED_STRUCT_PAGE_INIT=y +CONFIG_PAGE_IDLE_FLAG=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +CONFIG_GET_FREE_REGION=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +# CONFIG_DAMON_LRU_SORT is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XFRM_ESPINTCP=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_BPF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_NETLABEL=y +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +# CONFIG_BPFILTER_UMH is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_DEBUG=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +# end of AX.25 network device drivers + +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_MTK=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_VIRTIO=m +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=y +CONFIG_AF_KCM=m +CONFIG_STREAM_PARSER=y +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_SPI is not set +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +# end of Near Field Communication (NFC) devices + +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_MICROCHIP_HOST=y + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCI_MESON=y +CONFIG_PCIE_FU740=y +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +CONFIG_PCIE_CADENCE=y +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_EP=y +CONFIG_PCIE_CADENCE_PLAT=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m +CONFIG_PCI_EPF_VNTB=m +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +CONFIG_CXL_BUS=m +CONFIG_CXL_PCI=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PMEM=m +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m + +# +# RapidIO Switch drivers +# +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_UPLOAD=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_ARCH_NUMA=y +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MOXTET=m +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_CS_DSP=m +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +# CONFIG_SM_FTL is not set +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PSTORE is not set +CONFIG_MTD_SWAP=m +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +CONFIG_MTD_MAP_BANK_WIDTH_16=y +CONFIG_MTD_MAP_BANK_WIDTH_32=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m + +# +# Raw/parallel NAND flash controllers +# +CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m + +# +# Misc +# +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y +CONFIG_MTD_SPI_NAND=m + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_MXIC=y +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_NUMA=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +CONFIG_PARPORT_AX88796=m +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +# CONFIG_NVME_AUTH is not set +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_AUTH is not set +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_XILINX_SDFEC=m +CONFIG_MISC_RTSX=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_C2PORT=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_SPI=y +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_ECHO=m +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_HABANA_AI=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_GP_PCI1XXXX=m +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_AHCI_CEVA=m +CONFIG_AHCI_QORIQ=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +# CONFIG_PATA_OF_PLATFORM is not set +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_DM_AUDIT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RIONET_RX_SIZE=128 +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_SUNGEM_PHY=m +# CONFIG_ARCNET is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI_TUNE_BURST=y +CONFIG_ATM_ENI_BURST_TX_16W=y +CONFIG_ATM_ENI_BURST_TX_8W=y +CONFIG_ATM_ENI_BURST_TX_4W=y +CONFIG_ATM_ENI_BURST_TX_2W=y +CONFIG_ATM_ENI_BURST_RX_16W=y +CONFIG_ATM_ENI_BURST_RX_8W=y +CONFIG_ATM_ENI_BURST_RX_4W=y +CONFIG_ATM_ENI_BURST_RX_2W=y +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_NICSTAR_USE_SUNI=y +CONFIG_ATM_NICSTAR_USE_IDT77105=y +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +# CONFIG_CAIF_DRIVERS is not set + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_SEVILLE=m +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m +CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_SLICOSS=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AX88796C_COMPRESSION is not set +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACB_PCI=m +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_CAVIUM_PTP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +CONFIG_NET_VENDOR_CORTINA=y +CONFIG_GEMINI_ETHERNET=m +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +CONFIG_TULIP_NAPI=y +CONFIG_TULIP_NAPI_HW_MITIGATION=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NGBE=m +# CONFIG_TXGBE is not set +CONFIG_JME=m +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +# CONFIG_OCTEON_EP is not set +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_EN_MACSEC is not set +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXFW=m +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NI=y +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_APP_ABM_NIC=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_IONIC=m +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_LL2=y +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +CONFIG_QED_RDMA=y +CONFIG_QED_ISCSI=y +CONFIG_QED_FCOE=y +CONFIG_QED_OOO=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_QCA7000=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_SXGBE_ETH=m +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_LOONGSON=m +CONFIG_STMMAC_PCI=m +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_MSE102X=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIN1100_PHY is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TD510_PHY is not set +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_FLEXCAN=m +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_C_CAN=m +# CONFIG_CAN_C_CAN_PLATFORM is not set +CONFIG_CAN_C_CAN_PCI=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_USB is not set +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set + +# +# MCTP Device Drivers +# +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# end of MCTP Device Drivers + +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +CONFIG_PCS_LYNX=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ADM8211=m +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +# CONFIG_WIL6210_DEBUGFS is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K_DEBUGFS=y +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH11K_SPECTRAL=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +CONFIG_LIBIPW_DEBUG=y +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# CONFIG_IWLEGACY_DEBUGFS is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615_COMMON=m +CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921_COMMON=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW89=m +CONFIG_RTW89_CORE=m +CONFIG_RTW89_PCI=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852CE=m +# CONFIG_RTW89_DEBUGMSG is not set +# CONFIG_RTW89_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WFX=m +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +# CONFIG_CW1200_WLAN_SPI is not set +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +# CONFIG_WL1251_SPI is not set +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=y +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +# CONFIG_IOSM is not set +CONFIG_MTK_T7XX=m +# end of Wireless WAN + +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +# CONFIG_KEYBOARD_SAMSUNG is not set +CONFIG_KEYBOARD_GOLDFISH_EVENTS=y +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_IQS62X=m +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_KEYBOARD_BCM is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUR40=m +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +# CONFIG_INPUT_AD714X_SPI is not set +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MMA8450=m +# CONFIG_INPUT_GPIO_BEEPER is not set +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +# CONFIG_INPUT_IQS7222 is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SC16IS7XX_CORE=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=y +CONFIG_SERIAL_SC16IS7XX_SPI=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_SPRD=y +CONFIG_SERIAL_SPRD_CONSOLE=y +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=y +CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_HVC_DRIVER=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_PANIC_EVENT=y +# CONFIG_IPMI_PANIC_STRING is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_POLARFIRE_SOC=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_APPLICOM=m + +# +# PCMCIA character devices +# +CONFIG_SYNCLINK_CS=m +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +CONFIG_SCR24X=m +CONFIG_IPWIRELESS=m +# end of PCMCIA character devices + +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +CONFIG_RANDOM_TRUST_CPU=y +CONFIG_RANDOM_TRUST_BOOTLOADER=y +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RK3X=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_XILINX=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_VIRTIO=m +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_SLAVE_TESTUNIT=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_NXP_FLEXSPI=m +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_OC_TINY=m +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y + +# +# HSI controllers +# + +# +# HSI clients +# +CONFIG_HSI_CHAR=m +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CY8C95X0=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_CS47L15=y +CONFIG_PINCTRL_CS47L35=y +CONFIG_PINCTRL_CS47L85=y +CONFIG_PINCTRL_CS47L90=y +CONFIG_PINCTRL_CS47L92=y + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MAX730X=m + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_74XX_MMIO=m +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +# CONFIG_GPIO_EXAR is not set +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +CONFIG_GPIO_MB86S7X=m +# CONFIG_GPIO_SIFIVE is not set +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_XILINX=m +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_TQMX86=m +# CONFIG_GPIO_WM8994 is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +CONFIG_GPIO_MAX3191X=m +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_MOCKUP=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +# end of Virtual GPIO drivers + +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# end of 1-wire Slaves + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PDA_POWER=m +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_IP5XXX_POWER=m +# CONFIG_TEST_POWER is not set +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_CPCAP=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_BQ27XXX_HDQ=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_GPIO=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_BQ2415X is not set +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_BATTERY_UG3105=m +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_ADT7310 is not set +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_MAX1111 is not set +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +# CONFIG_SENSORS_MAX197 is not set +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +# CONFIG_SENSORS_MENF21BMC_HWMON is not set +CONFIG_SENSORS_MR75203=m +# CONFIG_SENSORS_ADCXX is not set +CONFIG_SENSORS_LM63=m +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +# CONFIG_SENSORS_NTC_THERMISTOR is not set +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_CORE=m +CONFIG_SENSORS_NCT6775=m +# CONFIG_SENSORS_NCT6775_I2C is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_SENSORS_PECI=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +# CONFIG_SENSORS_IR38064_REGULATOR is not set +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +# CONFIG_SENSORS_XDPE152 is not set +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +# CONFIG_SENSORS_ADS7871 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_CPU_THERMAL=y +# CONFIG_CPU_IDLE_THERMAL is not set +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=m +CONFIG_MAX77620_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_MENF21BMC_WATCHDOG is not set +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +CONFIG_MFD_ATMEL_HLCDC=m +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_HTC_PASIC3=m +# CONFIG_HTC_I2CPLD is not set +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_MFD_IQS62X=m +# CONFIG_MFD_JANZ_CMODIO is not set +CONFIG_MFD_KEMPLD=m +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m +# CONFIG_MFD_MT6397 is not set +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_OCELOT=m +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_UCB1400_CORE is not set +CONFIG_MFD_SY7636A=m +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=m +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SM501 is not set +CONFIG_MFD_SKY81452=m +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +# CONFIG_MFD_LP8788 is not set +CONFIG_MFD_TI_LMU=m +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_LM3533=m +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +# CONFIG_RAVE_SP_CORE is not set +CONFIG_MFD_INTEL_M10_BMC=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_88PG86X=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA9121=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +# CONFIG_REGULATOR_ISL6271A is not set +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +CONFIG_REGULATOR_LP873X=m +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_ROHM=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=m +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y + +# +# CEC support +# +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +# end of CEC support + +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=m +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +CONFIG_VIDEOBUF_VMALLOC=m +# end of Video4Linux options + +# +# Media controller options +# +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y + +# +# Analog TV USB devices +# +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_ZORAN is not set + +# +# Media capture/analog TV support +# +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +# CONFIG_I2C_SI470X is not set +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# +CONFIG_VIDEO_ASPEED=m + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +CONFIG_VIDEO_CAFE_CCIC=m + +# +# Mediatek media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# + +# +# Sunxi media platform drivers +# + +# +# Texas Instruments drivers +# + +# +# Verisilicon media platform drivers +# + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_VIDEO_XILINX_VTC=m + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=m + +# +# Camera sensor devices +# +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M032=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T001=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_NOON010PC30=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K4ECGX=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_S5K6AA=m +CONFIG_VIDEO_SR030PC30=m +CONFIG_VIDEO_VS6624=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_M5MOLS=m +# end of Camera sensor devices + +# +# Lens drivers +# +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +# end of Flash devices + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +CONFIG_VIDEO_AD9389B=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +# end of Video encoders + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +CONFIG_SDR_MAX2175=m +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +# end of Miscellaneous helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_EC100=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_L64781=m +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_STV0297=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_VES1820=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_MN88443X=m +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_DRX39XYJ=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +CONFIG_DRM=m +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_USE_DYNAMIC_DEBUG=y +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_BUDDY=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m +# end of I2C encoder or helper chips + +# +# ARM devices +# +CONFIG_DRM_KOMEDA=m +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +# CONFIG_DRM_AMD_DC_HDCP is not set +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_DRM_NOUVEAU=m +# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_RCAR_DW_HDMI=m +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_EBBG_FT8719=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_DW_HDMI=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +CONFIG_DRM_DW_HDMI_CEC=m +# end of Display Interface Bridges + +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV_THERMAL=y +CONFIG_DRM_LOGICVC=m +CONFIG_DRM_MXS=y +# CONFIG_DRM_MXSFB is not set +CONFIG_DRM_IMX_LCDIF=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_SIMPLEDRM=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_NOMODESET=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_I740=m +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SMSCUFX=m +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_GOLDFISH is not set +CONFIG_FB_VIRTUAL=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTL_DEBUG is not set +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_PREALLOC_SIZE=1024 +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_IMX_AUDMUX=m +# end of SoC Audio for Freescale CPUs + +CONFIG_SND_I2S_HI6210_I2S=m +# CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_OF=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45_TABLES=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_ICS43432=m +# CONFIG_SND_SOC_INNO_RK3036 is not set +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8315=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_VIRTIO=m +CONFIG_AC97_BUS=m + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +# end of I2C HID support + +CONFIG_I2C_HID_CORE=m +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_FOTG210_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +# CONFIG_USB_SL811_HCD_ISO is not set +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DUAL_ROLE is not set + +# +# Platform Glue Layer +# +CONFIG_USB_MUSB_POLARFIRE_SOC=m + +# +# MUSB DMA mode +# +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC2=m +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=m +# CONFIG_USB_CHIPIDEA_UDC is not set +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_IMX=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_TEGRA=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_DUAL_ROLE is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +# CONFIG_USB_CHAOSKEY is not set +CONFIG_USB_ONBOARD_HUB=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_USB_ISP1301=m +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_U_SERIAL_CONSOLE=y + +# +# USB Peripheral Controller +# +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SNP_UDC_PLAT=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=m +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_TCM=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_PI3USB30532=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_CRYPTO=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +# CONFIG_MMC_SDHCI_MILBEAUT is not set +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_AM654=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y + +# +# LED drivers +# +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_TCA6507=m +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m + +# +# RGB LED drivers +# +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m + +# +# Simple LED drivers +# +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_SIFIVE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_SD3078=m + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +CONFIG_RTC_DRV_MAX6916=m +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_PCF2127=m +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_RTC_DRV_NTXEC=m + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_POLARFIRE_SOC=m +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=m +CONFIG_DMA_OF=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +# CONFIG_INTEL_IDMA64 is not set +CONFIG_PLX_DMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_LINEDISP=m +CONFIG_HD44780_COMMON=m +CONFIG_HD44780=m +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PARPORT_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +CONFIG_PANEL=m +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_VIRQFD=m +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_VFIO_MDEV=m +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +CONFIG_VP_VDPA=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_COMEDI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +# CONFIG_COMEDI_MISC_DRIVERS is not set +# CONFIG_COMEDI_ISA_DRIVERS is not set +# CONFIG_COMEDI_PCI_DRIVERS is not set +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_ROUTING=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +CONFIG_FB_SM750=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_MAX96712=m +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STAGING_BOARD is not set +CONFIG_LTE_GDM724X=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +# CONFIG_VME_BUS is not set +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIPE=m +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SI5341=m +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_VC7=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_MCHP_CLK_MPFS=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_XILINX_VCU=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_HWSPINLOCK=y + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_RISCV_TIMER=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PLATFORM_MHU=m +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_POLARFIRE_SOC_MAILBOX=m +CONFIG_IOMMU_IOVA=m +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_QCOM=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +CONFIG_POLARFIRE_SOC_SYS_CTRL=m + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +CONFIG_SIFIVE_CCACHE=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_PTN5150=m +# CONFIG_EXTCON_RT8973A is not set +CONFIG_EXTCON_SM5502=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_FPGA_DFL_EMIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +CONFIG_MC3230=m +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +CONFIG_MMA9551_CORE=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MSA311=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +# end of Accelerometers + +# +# Analog to digital converters +# +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +# CONFIG_CC10001_ADC is not set +CONFIG_CPCAP_ADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +# CONFIG_MAX1027 is not set +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX1241=m +# CONFIG_MAX1363 is not set +CONFIG_MAX9611=m +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +CONFIG_MCP3911=m +CONFIG_MP2629_ADC=m +# CONFIG_NAU7802 is not set +CONFIG_QCOM_VADC_COMMON=m +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RICHTEK_RTQ6056=m +CONFIG_SD_ADC_MODULATOR=m +# CONFIG_TI_ADC081C is not set +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +# CONFIG_TI_ADC128S052 is not set +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +# CONFIG_TI_AM335X_ADC is not set +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_XILINX_XADC=m +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +CONFIG_AD74413R=m +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +CONFIG_IIO_RESCALE=m +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +CONFIG_ADA4250=m +CONFIG_HMC425=m +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +CONFIG_IIO_MS_SENSORS_I2C=m + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +CONFIG_AD3552R=m +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +CONFIG_AD5592R_BASE=m +CONFIG_AD5592R=m +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +CONFIG_LTC2688=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +# CONFIG_AD5755 is not set +CONFIG_AD5758=m +CONFIG_AD5761=m +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +CONFIG_AD7293=m +# CONFIG_AD7303 is not set +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Filters +# +CONFIG_ADMV8818=m +# end of Filters + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +CONFIG_ADF4371=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +# CONFIG_ADRF6780 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +CONFIG_AM2315=m +# CONFIG_DHT11 is not set +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +# end of Inertial measurement units + +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=m +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9960=m +CONFIG_AS73211=m +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +CONFIG_IQS621_ALS=m +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_RPR0521=m +# CONFIG_SENSORS_LM3533 is not set +# CONFIG_LTR501 is not set +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +# CONFIG_STK3310 is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +CONFIG_TSL2591=m +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_US5182D=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +# CONFIG_VEML6070 is not set +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +# end of Light sensors + +# +# Magnetometer sensors +# +CONFIG_AK8974=m +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_RM3100=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +CONFIG_IIO_MUX=m +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +CONFIG_IIO_HRTIMER_TRIGGER=m +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +CONFIG_IQS624_POS=m +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +CONFIG_AD5110=m +CONFIG_AD5272=m +# CONFIG_DS1803 is not set +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +# CONFIG_MCP4131 is not set +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +# end of Digital potentiometers + +# +# Digital potentiostats +# +CONFIG_LMP91000=m +# end of Digital potentiostats + +# +# Pressure sensors +# +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +CONFIG_ICP10100=m +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX_COMMON=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +CONFIG_MLX90632=m +# CONFIG_TMP006 is not set +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +# end of Temperature sensors + +CONFIG_NTB=y +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +# CONFIG_NTB_PINGPONG is not set +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +# CONFIG_NTB_MSI_TEST is not set +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_XILINX=m + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_AL_FIC=y +CONFIG_MADERA_IRQ=m +# CONFIG_XILINX_INTC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_POLARFIRE_SOC=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m + +# +# PHY drivers for Broadcom platforms +# +CONFIG_BCM_KONA_USB2_PHY=m +# end of PHY drivers for Broadcom platforms + +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_LAN966X_SERDES=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +CONFIG_RAS=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set + +# +# Android +# +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +CONFIG_LIBNVDIMM=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +CONFIG_OF_PMEM=m +CONFIG_NVDIMM_KEYS=y +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_U_BOOT_ENV=m + +# +# HW tracing support +# +CONFIG_STM=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +# CONFIG_STM_DUMMY is not set +CONFIG_STM_SOURCE_CONSOLE=y +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STM_SOURCE_FTRACE=m +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +CONFIG_PECI=m +CONFIG_PECI_CPU=m +CONFIG_HTE=y +# end of Device Drivers + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +CONFIG_QNX6FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_ROMFS_FS=m +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_ZSTD_COMPRESS=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_ZONE=m +CONFIG_PSTORE_BLK=m +CONFIG_PSTORE_BLK_BLKDEV="" +CONFIG_PSTORE_BLK_KMSG_SIZE=64 +CONFIG_PSTORE_BLK_MAX_REASON=2 +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EROFS_FS=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEPRECATED_API is not set +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=y +# end of Compression + +# +# Random number generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +CONFIG_PACKING=y +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=y +CONFIG_CRC4=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=y +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=y +CONFIG_842_DECOMPRESS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_BCH=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CHECK_SIGNATURE=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +CONFIG_FONT_TER16x32=y +# CONFIG_FONT_6x8 is not set +CONFIG_SG_POOL=y +CONFIG_MEMREGION=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +CONFIG_PARMAN=m +CONFIG_OBJAGG=m +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m +CONFIG_POLYNOMIAL=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_NONE is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_BTF=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_PAGE_OWNER=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_TORTURE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_OSNOISE_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set +# CONFIG_SAMPLES is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# riscv Debugging +# +# end of riscv Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ASYNC_RAID6_TEST=m +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_SIPHASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/srcpkgs/linux6.1/template b/srcpkgs/linux6.1/template index 432766ad9eb3c..05948cb6ee8e5 100644 --- a/srcpkgs/linux6.1/template +++ b/srcpkgs/linux6.1/template @@ -18,7 +18,7 @@ checksum="2ca1f17051a430f6fed1196e4952717507171acfd97d96577212502703b25deb python_version=3 # XXX Restrict archs until a proper -dotconfig is available in FILESDIR. -archs="x86_64* i686* aarch64* ppc*" +archs="x86_64* i686* aarch64* ppc* riscv64*" nodebug=yes # -dbg package is generated below manually nostrip=yes @@ -79,6 +79,7 @@ do_configure() { ppc64*) arch=powerpc; subarch=ppc64;; ppc*) arch=powerpc; subarch=ppc;; mips*) arch=mips;; + riscv64*) arch=riscv;; esac if [ -f ${FILESDIR}/${subarch:-$arch}-dotconfig-custom ]; then @@ -90,6 +91,7 @@ do_configure() { cp -f ${FILESDIR}/${subarch:-$arch}-dotconfig .config make ${makejobs} ARCH=$arch ${_cross} oldconfig fi + # Always use our revision to CONFIG_LOCALVERSION to match our pkg version. sed -i -e "s|^\(CONFIG_LOCALVERSION=\).*|\1\"_${revision}\"|" .config } @@ -104,6 +106,7 @@ do_build() { aarch64*) _args="Image modules dtbs"; arch=arm64;; ppc*) _args="zImage modules"; arch=powerpc;; mips*) _args="uImage modules dtbs"; arch=mips;; + riscv64*) _args="Image modules dtbs"; arch=riscv;; esac export LDFLAGS= make ARCH=$arch ${_cross} ${makejobs} prepare @@ -120,6 +123,7 @@ do_install() { aarch64*) arch=arm64;; ppc*) arch=powerpc;; mips*) arch=mips;; + riscv*) arch=riscv;; esac # Run depmod after compressing modules - makes depmod.sh a noop @@ -157,6 +161,10 @@ do_install() { vinstall arch/mips/boot/uImage.bin 644 boot uImage-${_kernver} make ${makejobs} ARCH=${subarch:-$arch} INSTALL_DTBS_PATH=${DESTDIR}/boot/dtbs/dtbs-${_kernver} ${_cross} dtbs_install ;; + riscv) + vinstall arch/riscv/boot/Image 644 boot vmlinux-${_kernver} + make ${makejobs} ARCH=${subarch:-$arch} INSTALL_DTBS_PATH=${DESTDIR}/boot/dtbs/dtbs-${_kernver} ${_cross} dtbs_install + ;; esac # Switch to /usr. @@ -289,6 +297,7 @@ do_install() { arm|arm64) _args="x86* m* p*";; powerpc) _args="arm* m* x86* parisc";; mips) _args="arm* x86* p*";; + riscv) _args="arm* m* x86* p*";; esac for arch in alpha avr32 blackfin cris frv h8300 \ ia64 s* um v850 xtensa ${_args}; do From 85b58177ecb2bdcaccd944c79b0cff84ef035a61 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 4 Feb 2023 17:13:12 +0100 Subject: [PATCH 119/189] thunderbird: add riscv64 patches --- srcpkgs/thunderbird/template | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/srcpkgs/thunderbird/template b/srcpkgs/thunderbird/template index 5cf8fed820df9..78eb31816e885 100644 --- a/srcpkgs/thunderbird/template +++ b/srcpkgs/thunderbird/template @@ -33,7 +33,6 @@ case $XBPS_TARGET_MACHINE in armv[56]*) broken="required NEON extensions are not supported on armv6" ;; ppc64*) ;; ppc*) broken="xptcall bitrot" ;; - riscv64*) broken="Some rust crates need updating" ;; esac # try to minimize memory usage via debug symbols @@ -70,6 +69,8 @@ post_patch() { _clear_vendor_checksums num-traits _clear_vendor_checksums glslopt _clear_vendor_checksums mp4parse + _clear_vendor_checksums nix + _clear_vendor_checksums authenticator } do_build() { From 557e6fc5974ee630138a1d4cc212accab1e1bf62 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 12:46:22 +0100 Subject: [PATCH 120/189] nim: add riscv64 support to template --- srcpkgs/nim/template | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/srcpkgs/nim/template b/srcpkgs/nim/template index 175dcbaea8439..1e0a5f5220b83 100644 --- a/srcpkgs/nim/template +++ b/srcpkgs/nim/template @@ -45,10 +45,11 @@ do_build() { ppc64le*) _arch=powerpc64el;; ppc64*) _arch=powerpc64;; ppc*) _arch=powerpc;; + riscv64*) _arch=riscv64;; esac case "$XBPS_TARGET_MACHINE" - in arm*|aarch64*|ppc*) + in arm*|aarch64*|ppc*|riscv64*) vsed -i config/nim.cfg -e 's/^arm\.linux\.gcc\.\(linker\)\?exe /#&/' cat >>config/nim.cfg <<-EDIT # VOIDLINUX TEMP From 2e6a2d86d9bab17baf93f833ce226f0a45437f3b Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 13:24:58 +0100 Subject: [PATCH 121/189] resvg: update to 0.29.0. the usvg tool was removed upsteam and might be a seperate project in the future https://github.com/RazrFalcon/resvg/issues/568 --- srcpkgs/resvg/patches/QPainterPath.patch | 20 --------------- srcpkgs/resvg/template | 31 ++++++++++-------------- 2 files changed, 13 insertions(+), 38 deletions(-) delete mode 100644 srcpkgs/resvg/patches/QPainterPath.patch diff --git a/srcpkgs/resvg/patches/QPainterPath.patch b/srcpkgs/resvg/patches/QPainterPath.patch deleted file mode 100644 index 870a1be3080e7..0000000000000 --- a/srcpkgs/resvg/patches/QPainterPath.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/capi/include/ResvgQt.h 2019-03-21 21:50:09.719296805 +0100 -+++ b/capi/include/ResvgQt.h 2020-09-01 01:20:43.903570695 +0200 -@@ -23,6 +23,7 @@ - #include - #include - #include -+#include - #include - #include - #include ---- a/resvg-qt/cpp/qt_capi.cpp 2019-03-21 21:50:09.719296805 +0100 -+++ b/resvg-qt/cpp/qt_capi.cpp 2020-09-01 01:23:19.594578727 +0200 -@@ -1,6 +1,7 @@ - #include - #include - #include -+#include - #include - - #include "qt_capi.hpp" diff --git a/srcpkgs/resvg/template b/srcpkgs/resvg/template index c48e52ae2f2e6..9487c98258c9f 100644 --- a/srcpkgs/resvg/template +++ b/srcpkgs/resvg/template @@ -1,41 +1,36 @@ # Template file for 'resvg' pkgname=resvg -version=0.6.1 +version=0.29.0 revision=1 +build_style=cargo build_helper="rust" -hostmakedepends="cargo qt5-host-tools pkg-config" -makedepends="pango-devel cairo-devel gdk-pixbuf-devel rust-std qt5-devel" +hostmakedepends="cargo" +makedepends="rust-std" short_desc="SVG rendering library written in Rust" maintainer="Orphaned " license="MPL-2.0" homepage="https://github.com/RazrFalcon/resvg" distfiles="https://github.com/RazrFalcon/resvg/releases/download/v${version}/resvg-${version}.tar.xz" -checksum=7206f79f67b4c8610353134c375ed3ff9c5eb63b16fae267b94730c23ebe4ee1 +checksum=ba82f5348899e4dc869c57dc0a616ab8bd153746abede79830d78ca9c184dd60 -do_build() { - for dir in capi tools/{render,u}svg; do - ( +post_build() { + for dir in c-api; do + ( cd $dir - if grep -q cairo-backend Cargo.toml; then - cargo build --release --target ${RUST_TARGET} --features="qt-backend cairo-backend" - else - cargo build --release --target ${RUST_TARGET} - fi - ) + cargo auditable build --release --target ${RUST_TARGET} + ) done } do_install() { - for t in {render,u}svg; do - vbin target/${RUST_TARGET}/release/$t - done + vbin target/${RUST_TARGET}/release/resvg # Install library as libresvg.so.0 and make the solink vinstall target/${RUST_TARGET}/release/libresvg.so 755 usr/lib libresvg.so.0 ln -rs "${DESTDIR}"/usr/lib/libresvg.so.0 "${DESTDIR}"/usr/lib/libresvg.so - vinstall capi/include/resvg.h 644 usr/include - vinstall capi/include/ResvgQt.h 644 usr/include + vinstall c-api/resvg.h 644 usr/include + vinstall c-api/ResvgQt.h 644 usr/include } libresvg0_package() { From 2d3bcfe007d5b58da32d14cc95933c7630cf95d9 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 13:28:03 +0100 Subject: [PATCH 122/189] klibc: add riscv support to template --- srcpkgs/klibc/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/klibc/template b/srcpkgs/klibc/template index 50c73deb454e8..189f83f42d3a0 100644 --- a/srcpkgs/klibc/template +++ b/srcpkgs/klibc/template @@ -32,6 +32,7 @@ _make() { ppc*) _arch=ppc ;; mips*64*) _arch=mips64 ;; mips*) _arch=mips ;; + riscv64*) _arch=riscv64 ;; *) msg_error "not supported" ;; esac PATH=/usr/bin From 661b1a886b5010ab6878990fbf4b12918c88dd83 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 13:56:56 +0100 Subject: [PATCH 123/189] pazi: update libc crate for riscv64 compat --- srcpkgs/pazi/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/pazi/template b/srcpkgs/pazi/template index 94d5419ed26db..41afa048b73f1 100644 --- a/srcpkgs/pazi/template +++ b/srcpkgs/pazi/template @@ -9,3 +9,8 @@ license="GPL-3.0-only" homepage="https://github.com/euank/pazi" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=f513561451b29fed6d4eb3387524df597b5811cd7744eac77d96e368022b6adc + +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} From 9fdd48f27bf7078b558c36530374a36c7ceb3237 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 14:16:18 +0100 Subject: [PATCH 124/189] ugdb: update libc crate for riscv64 compat --- srcpkgs/ugdb/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/ugdb/template b/srcpkgs/ugdb/template index 4333dd2b53fa0..152d324e7dbbf 100644 --- a/srcpkgs/ugdb/template +++ b/srcpkgs/ugdb/template @@ -13,6 +13,11 @@ homepage="https://github.com/ftilde/ugdb" distfiles="${homepage}/archive/${version}.tar.gz" checksum=d092356534774505b6b081b82db71d1fab1fbccdb814a44d4c435bafe5efd312 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From 9f0a6af819ef00563259e1964d29c36f2d20dc16 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 14:17:20 +0100 Subject: [PATCH 125/189] rot8: update libc crate for riscv64 compat --- srcpkgs/rot8/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/rot8/template b/srcpkgs/rot8/template index b6e24a7fb228a..2e890f2d48941 100644 --- a/srcpkgs/rot8/template +++ b/srcpkgs/rot8/template @@ -10,6 +10,11 @@ homepage="https://github.com/efernau/rot8" distfiles="https://github.com/efernau/rot8/archive/refs/tags/v${version}.tar.gz" checksum=d8dae505a0f736e6462d4745d9adc330afd9177fcba25a02e73650bdfe295495 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From 6eacfcfaf03bf77b9845921c79a22b312e3ac22f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 15:30:02 +0100 Subject: [PATCH 126/189] libfirm: mark broken on riscv64 --- srcpkgs/libfirm/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/libfirm/template b/srcpkgs/libfirm/template index 3690ae493c1a0..16181d76a0ce0 100644 --- a/srcpkgs/libfirm/template +++ b/srcpkgs/libfirm/template @@ -12,7 +12,7 @@ distfiles="https://github.com/MatzeB/${pkgname}/archive/${pkgname}-${version}.ta checksum=2e681db62610a41394f1aa3a62583acff8a67cea138354be6b3d2d8d390665c3 case "$XBPS_TARGET_MACHINE" in - aarch64*|ppc*) broken="Unsupported long double format" ;; + aarch64*|ppc*|riscv64*) broken="Unsupported long double format" ;; esac do_configure() { From bf53c1d033352912f2d4825aa44809621e2b0935 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 15:44:35 +0100 Subject: [PATCH 127/189] slurm-wlm: add python3 to hostdeps to fix build --- srcpkgs/slurm-wlm/template | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/srcpkgs/slurm-wlm/template b/srcpkgs/slurm-wlm/template index 4405ed46fc1b1..d8ad30476b518 100644 --- a/srcpkgs/slurm-wlm/template +++ b/srcpkgs/slurm-wlm/template @@ -5,7 +5,7 @@ revision=4 _distver="${version//./-}" build_style=gnu-configure configure_args="--disable-static" -hostmakedepends="perl cgit pkg-config" +hostmakedepends="perl cgit pkg-config python3" # XXX: ofed, DataWarp, netloc, blcr makedepends="munge-devel lua53-devel pam-devel openssl-devel gtk+-devel ncurses-devel readline-devel libmariadbclient-devel json-c-devel libhwloc-devel @@ -23,6 +23,8 @@ CFLAGS="-fcommon" # https://bugs.schedmd.com/show_bug.cgi?id=2443 LDFLAGS="-Wl,-z,lazy" +#broken="/usr/bin/env: ‘python’: No such file or directory" + if [ "$XBPS_TARGET_WORDSIZE" = "32" ]; then # configure: error: 32-bit support is deprecated, and not tested # regularly. Use at your own risk. From 6a71538a58741dd78dd94569635fe2832c79394d Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 16:10:33 +0100 Subject: [PATCH 128/189] gsl-ucg: add patch for riscv64 --- srcpkgs/gsl-ucg/patches/riscv64.patch | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 srcpkgs/gsl-ucg/patches/riscv64.patch diff --git a/srcpkgs/gsl-ucg/patches/riscv64.patch b/srcpkgs/gsl-ucg/patches/riscv64.patch new file mode 100644 index 0000000000000..956214b555a13 --- /dev/null +++ b/srcpkgs/gsl-ucg/patches/riscv64.patch @@ -0,0 +1,24 @@ +--- a/src/sfl.h 2017-09-13 15:35:49.000000000 +0200 ++++ - 2023-02-07 16:09:26.971059849 +0100 +@@ -130,7 +130,8 @@ + + #if (defined (__64BIT__) || defined (__x86_64__) || defined (__AARCH64EL__) \ + || defined (__PPC64__) || defined (__powerpc64__) || defined (__ppc64__) \ +- || defined (__s390x__)) ++ || defined (__s390x__)) \ ++ || defined (__riscv64) || (defined (__riscv_xlen) && __riscv_xlen == 64) + # define __IS_64BIT__ /* May have 64-bit OS/compiler */ + #else + # define __IS_32BIT__ /* Else assume 32-bit OS/compiler */ +--- a/src/prelude.h 2017-09-13 15:35:49.000000000 +0200 ++++ - 2023-02-07 16:09:50.387722331 +0100 +@@ -91,7 +91,8 @@ + + #if (defined (__64BIT__) || defined (__x86_64__) || defined (__AARCH64EL__) \ + || defined (__PPC64__) || defined (__powerpc64__) || defined (__ppc64__) \ +- || defined (__s390x__)) ++ || defined (__s390x__)) \ ++ || defined (__riscv64) || (defined (__riscv_xlen) && __riscv_xlen == 64) + # define __IS_64BIT__ /* May have 64-bit OS/compiler */ + #else + # define __IS_32BIT__ /* Else assume 32-bit OS/compiler */ From 8dfd90b3589cb35bbc12f34deadc221ffa270e5f Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 16:49:04 +0100 Subject: [PATCH 129/189] nrg2iso: fix build --- srcpkgs/nrg2iso/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/nrg2iso/template b/srcpkgs/nrg2iso/template index a4bcf40e557b6..7be916a4f533e 100644 --- a/srcpkgs/nrg2iso/template +++ b/srcpkgs/nrg2iso/template @@ -2,7 +2,7 @@ pkgname=nrg2iso version=0.4.1 revision=1 -build_style=gnu-makefile +build_wrksrc="$pkgname-${version}" short_desc="Simple tool to convert from Nero Burning Rom (NRG) to ISO" maintainer="Orphaned " license="GPL-2.0-only" From 95cb574b9db80623d128354ca80fc2d06c3d89c7 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 16:57:51 +0100 Subject: [PATCH 130/189] openblas: add riscv64 support to template --- srcpkgs/openblas/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/openblas/template b/srcpkgs/openblas/template index 61a891a86a30d..d3973039687da 100644 --- a/srcpkgs/openblas/template +++ b/srcpkgs/openblas/template @@ -30,6 +30,7 @@ case "${XBPS_TARGET_MACHINE}" in ppc64le*) make_build_args+=" TARGET=POWER8 DYNAMIC_ARCH=1" ;; ppc64*) make_build_args+=" TARGET=PPC970MP" ;; # dynamic arch broken for Date: Tue, 7 Feb 2023 17:09:36 +0100 Subject: [PATCH 131/189] ice-ssb: fix build --- srcpkgs/ice-ssb/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/ice-ssb/template b/srcpkgs/ice-ssb/template index d869defeb160d..5b790dc91c0d8 100644 --- a/srcpkgs/ice-ssb/template +++ b/srcpkgs/ice-ssb/template @@ -4,7 +4,7 @@ version=6.0.8 revision=2 depends="gtk+3 python3-BeautifulSoup4 python3-gobject python3-requests" short_desc="Site Specific Browsers (SSBs) manager" -maintainer="John " +maintainer="Orphaned " license="GPL-2.0-or-later" homepage="https://github.com/peppermintos/ice/" changelog="https://github.com/peppermintos/ice/blob/${version}/debian/changelog" From 3c1887cdb1fd4f310c884b97da10b3e962994787 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 17:27:00 +0100 Subject: [PATCH 132/189] i3lockr: update libc crate for riscv64 compat --- srcpkgs/i3lockr/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/i3lockr/template b/srcpkgs/i3lockr/template index 9d5f3ec247618..5f18e15d29c3c 100644 --- a/srcpkgs/i3lockr/template +++ b/srcpkgs/i3lockr/template @@ -12,6 +12,11 @@ homepage="https://github.com/owenthewizard/i3lockr" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=d4b31fb67cbb4d231437e02589146a1cfea7d49afbaf123109f6b0eec359d71c +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE-MIT.md } From 848adbe252f08b16af697dee08e3066beaa34fde Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 21:57:50 +0100 Subject: [PATCH 133/189] dijo: update libc crate for riscv64 compat --- srcpkgs/dijo/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/dijo/template b/srcpkgs/dijo/template index f1bf4dd5a9a14..797a395cc1b52 100644 --- a/srcpkgs/dijo/template +++ b/srcpkgs/dijo/template @@ -11,6 +11,11 @@ homepage="https://github.com/NerdyPepper/dijo" distfiles="https://github.com/NerdyPepper/dijo/archive/v${version}.tar.gz" checksum=d82ce7adb19e5206e014f0a895fe3ed361f32088048116e9d33aea37f3cccb00 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From 2f015a8df52dba1b4c2cb05a7fe8481a0d62d00d Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 22:19:33 +0100 Subject: [PATCH 134/189] mumble: fix build with newer musl --- srcpkgs/hardinfo/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/hardinfo/template b/srcpkgs/hardinfo/template index 087687bfa06ce..ae6da70e564fd 100644 --- a/srcpkgs/hardinfo/template +++ b/srcpkgs/hardinfo/template @@ -14,6 +14,10 @@ distfiles="${SOURCEFORGE_SITE}/${pkgname}.berlios/${pkgname}-${version}.tar.bz2" checksum=a0df6c0d7c92a7d20710b8eb551197398a965aaae053782b89a32a160b731b7a lib32disabled=yes +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Your architecture is not supported yet. Please send the";; +esac + post_patch() { local _arch _arch="${XBPS_TARGET_MACHINE%-*}" From a8f9a930fa3d9d15945e5696b51a2fdefd4a08f9 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 22:26:12 +0100 Subject: [PATCH 135/189] getdns: mark broken --- srcpkgs/getdns/template | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/srcpkgs/getdns/template b/srcpkgs/getdns/template index 67672e19ff30f..04f6681c8e923 100644 --- a/srcpkgs/getdns/template +++ b/srcpkgs/getdns/template @@ -3,7 +3,8 @@ pkgname=getdns version=1.7.0 revision=1 build_style=cmake -makedepends="libev-devel libidn-devel libuv-devel unbound-devel +configure_args="--trace-expand" +makedepends="libev-devel libuv-devel unbound-devel check-devel libidn2-devel" short_desc="Modern asynchronous DNS API" maintainer="Frank Steinborn " @@ -14,6 +15,8 @@ checksum=ea8713ce5e077ac76b1418ceb6afd25e6d4e39e9600f6f5e81d3a3a13a60f652 # GitHub Actions fail due to no IPv6 make_check=ci-skip +broken="Fun regex in cmake to get libidn2 version" + post_install() { vlicense LICENSE } From f52e545ea7f5db24a836ee2c1189d94b46ee13c1 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 22:41:14 +0100 Subject: [PATCH 136/189] waitforfile: update libc crate for riscv64 compat --- srcpkgs/waitforfile/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/waitforfile/template b/srcpkgs/waitforfile/template index b6f4b3c249f30..a97ee31e9ce75 100644 --- a/srcpkgs/waitforfile/template +++ b/srcpkgs/waitforfile/template @@ -10,6 +10,11 @@ homepage="https://github.com/nroi/waitforfile" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=e63c7b964d4b475f4d84fba62a8b2e43593cbe73c7ce4840474836a978ca01a3 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From 1f3362835c31ad54187bd73417ee3b4ff4f082d7 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 7 Feb 2023 22:54:17 +0100 Subject: [PATCH 137/189] tokei: update libc crate for riscv64 compat --- srcpkgs/tokei/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/tokei/template b/srcpkgs/tokei/template index ef99d76777e74..6706de0bd0be8 100644 --- a/srcpkgs/tokei/template +++ b/srcpkgs/tokei/template @@ -17,6 +17,11 @@ case "$XBPS_TARGET_MACHINE" in *) ;; esac +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENCE-MIT } From 1b04d991ac787af6f80022c013318c3ab6d53b3d Mon Sep 17 00:00:00 2001 From: John Date: Sat, 11 Feb 2023 19:09:33 +0100 Subject: [PATCH 138/189] New package: Visionfive2-kernel-5.15.0 --- srcpkgs/Visionfive2-kernel-dbg | 1 + srcpkgs/Visionfive2-kernel-headers | 1 + srcpkgs/Visionfive2-kernel/files/dotconfig | 9322 +++++++++++++++++ srcpkgs/Visionfive2-kernel/files/mv-debug | 7 + .../patches/0001-gcc12.patch | 55 + .../patches/0002-gcc12.patch | 55 + .../pls-dont-pick-only-half-a-patch.patch | 13 + srcpkgs/Visionfive2-kernel/template | 244 + 8 files changed, 9698 insertions(+) create mode 120000 srcpkgs/Visionfive2-kernel-dbg create mode 120000 srcpkgs/Visionfive2-kernel-headers create mode 100644 srcpkgs/Visionfive2-kernel/files/dotconfig create mode 100755 srcpkgs/Visionfive2-kernel/files/mv-debug create mode 100644 srcpkgs/Visionfive2-kernel/patches/0001-gcc12.patch create mode 100644 srcpkgs/Visionfive2-kernel/patches/0002-gcc12.patch create mode 100644 srcpkgs/Visionfive2-kernel/patches/pls-dont-pick-only-half-a-patch.patch create mode 100644 srcpkgs/Visionfive2-kernel/template diff --git a/srcpkgs/Visionfive2-kernel-dbg b/srcpkgs/Visionfive2-kernel-dbg new file mode 120000 index 0000000000000..f09aa92ac48ef --- /dev/null +++ b/srcpkgs/Visionfive2-kernel-dbg @@ -0,0 +1 @@ +Visionfive2-kernel \ No newline at end of file diff --git a/srcpkgs/Visionfive2-kernel-headers b/srcpkgs/Visionfive2-kernel-headers new file mode 120000 index 0000000000000..f09aa92ac48ef --- /dev/null +++ b/srcpkgs/Visionfive2-kernel-headers @@ -0,0 +1 @@ +Visionfive2-kernel \ No newline at end of file diff --git a/srcpkgs/Visionfive2-kernel/files/dotconfig b/srcpkgs/Visionfive2-kernel/files/dotconfig new file mode 100644 index 0000000000000..06e45d6eb02b4 --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/files/dotconfig @@ -0,0 +1,9322 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 5.15.0 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (GCC) 12.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=120200 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23900 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23900 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="_1" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_WATCH_QUEUE=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_SIM=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_LSM=y +# end of BPF subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RCU=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_USERFAULTFD=y +CONFIG_KCMP=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_VA_BITS=39 +CONFIG_PA_BITS=56 +CONFIG_PAGE_OFFSET=0xffffffe000000000 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_LOCKDEP_SUPPORT=y + +# +# SoC selection +# +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +CONFIG_SOC_SIFIVE=y +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_STARFIVE_VIC7100 is not set +CONFIG_SOC_STARFIVE_JH7110=y + +# +# StarFive JH SoC Debug Option +# +# CONFIG_FPGA_GMAC_SPEED10 is not set +# CONFIG_FPGA_GMAC_SPEED100 is not set +CONFIG_FPGA_GMAC_SPEED_AUTO=y +# end of StarFive JH SoC Debug Option + +CONFIG_SOC_VIRT=y +# end of SoC selection + +# +# CPU errata selection +# +CONFIG_RISCV_ERRATA_ALTERNATIVE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_MAXPHYSMEM_128GB=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_RISCV_ISA_C=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_RISCV_SBI_V01=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# CONFIG_PHYS_RAM_BASE_FIXED is not set +# CONFIG_XIP_KERNEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_HEADER=y +# end of Boot options + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_DPM_WATCHDOG=y +CONFIG_DPM_WATCHDOG_TIMEOUT=60 +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +CONFIG_ENERGY_MODEL=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle +# end of CPU Power Management + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_MQ_RDMA=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +# CONFIG_ZSWAP_DEFAULT_ON is not set +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_DEFERRED_STRUCT_PAGE_INIT=y +CONFIG_PAGE_IDLE_FLAG=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_DBGFS=y +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XFRM_ESPINTCP=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_BPF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_NETLABEL=y +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +# CONFIG_BPFILTER_UMH is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_DEBUG=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +# end of AX.25 network device drivers + +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_DEV=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_FLEXCAN=m +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_IPMS_CAN=m +CONFIG_CAN_C_CAN=m +# CONFIG_CAN_C_CAN_PLATFORM is not set +CONFIG_CAN_C_CAN_PCI=m +# CONFIG_CAN_CC770 is not set +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set +# end of CAN Device Drivers + +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_VIRTIO=m +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=y +CONFIG_AF_KCM=m +CONFIG_STREAM_PARSER=y +CONFIG_MCTP=m +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_SPI is not set +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +# end of Near Field Communication (NFC) devices + +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_PLDA=m + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCI_MESON=y +CONFIG_PCIE_FU740=y +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +CONFIG_PCIE_CADENCE=y +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_EP=y +CONFIG_PCIE_CADENCE_PLAT=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +CONFIG_CXL_BUS=m +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PMEM=m +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m + +# +# RapidIO Switch drivers +# +CONFIG_RAPIDIO_TSI57X=m +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_TSI568=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_CACHE=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_ARCH_NUMA=y +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MOXTET=m +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +# CONFIG_SM_FTL is not set +CONFIG_MTD_OOPS=m +CONFIG_MTD_SWAP=m +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +CONFIG_MTD_MAP_BANK_WIDTH_16=y +CONFIG_MTD_MAP_BANK_WIDTH_32=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m + +# +# Raw/parallel NAND flash controllers +# +CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m + +# +# Misc +# +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y +CONFIG_MTD_SPI_NAND=m + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_BCH=y +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_NUMA=y +CONFIG_OF_CONFIGFS=y +CONFIG_PARPORT=m +CONFIG_PARPORT_AX88796=m +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_SX8=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RSXX=m +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=m +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_XILINX_SDFEC=m +CONFIG_MISC_RTSX=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_C2PORT=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_SPI=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_ECHO=m +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_HABANA_AI=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_CEVA=m +CONFIG_AHCI_QORIQ=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +# CONFIG_SATA_DWC_DEBUG is not set +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +CONFIG_PATA_PLATFORM=m +# CONFIG_PATA_OF_PLATFORM is not set +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +# CONFIG_MD is not set +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RIONET_RX_SIZE=128 +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_SUNGEM_PHY=m +# CONFIG_ARCNET is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI_TUNE_BURST=y +CONFIG_ATM_ENI_BURST_TX_16W=y +CONFIG_ATM_ENI_BURST_TX_8W=y +CONFIG_ATM_ENI_BURST_TX_4W=y +CONFIG_ATM_ENI_BURST_TX_2W=y +CONFIG_ATM_ENI_BURST_RX_16W=y +CONFIG_ATM_ENI_BURST_RX_8W=y +CONFIG_ATM_ENI_BURST_RX_4W=y +CONFIG_ATM_ENI_BURST_RX_2W=y +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_NICSTAR_USE_SUNI=y +CONFIG_ATM_NICSTAR_USE_IDT77105=y +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +# CONFIG_CAIF_DRIVERS is not set + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ8795=m +CONFIG_NET_DSA_MICROCHIP_KSZ8795_SPI=m +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_SEVILLE=m +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_SLICOSS=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACB_PCI=m +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_CAVIUM_PTP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +CONFIG_NET_VENDOR_CORTINA=y +CONFIG_GEMINI_ETHERNET=m +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +CONFIG_TULIP_NAPI=y +CONFIG_TULIP_NAPI_HW_MITIGATION=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_JME=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_ACCEL=y +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_FPGA_IPSEC=y +CONFIG_MLX5_IPSEC=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_FPGA_TLS=y +CONFIG_MLX5_TLS=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXFW=m +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_VXGE=m +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_APP_ABM_NIC=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NET_VENDOR_NI=y +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_IONIC=m +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_LL2=y +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +CONFIG_QED_RDMA=y +CONFIG_QED_ISCSI=y +CONFIG_QED_FCOE=y +CONFIG_QED_OOO=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_QCA7000=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_SXGBE_ETH=m +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_STARFIVE_PLAT=y +CONFIG_DWMAC_LOONGSON=m +CONFIG_STMMAC_PCI=m +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m + +# +# MCTP Device Drivers +# +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +CONFIG_PCS_LYNX=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ADM8211=m +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +# CONFIG_WIL6210_DEBUGFS is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K_DEBUGFS=y +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH11K_SPECTRAL=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +CONFIG_LIBIPW_DEBUG=y +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# CONFIG_IWLEGACY_DEBUGFS is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y +# CONFIG_IWLWIFI_BCAST_FILTERING is not set + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615_COMMON=m +CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921E=m +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8821CE=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +# CONFIG_CW1200_WLAN_SPI is not set +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +# CONFIG_WL1251_SPI is not set +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +# CONFIG_WILINK_PLATFORM_DATA is not set +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +# CONFIG_USB_WIFI_ECR6600U is not set +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=y +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +# end of Wireless WAN + +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=m + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +# CONFIG_KEYBOARD_SAMSUNG is not set +CONFIG_KEYBOARD_GOLDFISH_EVENTS=m +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_IQS62X=m +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_KEYBOARD_BCM is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_GT9XX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TOUCHSCREEN_TINKER_FT5406=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +# CONFIG_INPUT_AD714X_SPI is not set +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MMA8450=m +# CONFIG_INPUT_GPIO_BEEPER is not set +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SC16IS7XX_CORE=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=y +CONFIG_SERIAL_SC16IS7XX_SPI=y +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_SPRD=y +CONFIG_SERIAL_SPRD_CONSOLE=y +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_HVC_DRIVER=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_PANIC_EVENT=y +# CONFIG_IPMI_PANIC_STRING is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM_STARFIVE=y +CONFIG_APPLICOM=m + +# +# PCMCIA character devices +# +CONFIG_SYNCLINK_CS=m +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +CONFIG_SCR24X=m +CONFIG_IPWIRELESS=m +# end of PCMCIA character devices + +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +CONFIG_RANDOM_TRUST_BOOTLOADER=y +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_KEMPLD=m +# CONFIG_I2C_NOMADIK is not set +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RK3X=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_XILINX=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_VIRTIO=m +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_SLAVE_TESTUNIT=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_NXP_FLEXSPI=m +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_PL022=m +CONFIG_SPI_PL022_STARFIVE=y +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y + +# +# HSI controllers +# + +# +# HSI clients +# +CONFIG_HSI_CHAR=m +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_RK805=m +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_MICROCHIP_SGPIO=y + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_CS47L15=y +CONFIG_PINCTRL_CS47L35=y +CONFIG_PINCTRL_CS47L85=y +CONFIG_PINCTRL_CS47L90=y +CONFIG_PINCTRL_CS47L92=y +CONFIG_PINCTRL_STARFIVE=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MAX730X=m + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_74XX_MMIO=m +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +# CONFIG_GPIO_EXAR is not set +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_PL061=y +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SIFIVE is not set +CONFIG_GPIO_STARFIVE_JH7110=y +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_XILINX=m +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +CONFIG_GPIO_ADP5588=m +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_BD70528=m +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_TQMX86=m +# CONFIG_GPIO_WM8994 is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +CONFIG_GPIO_MAX3191X=m +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_MOCKUP=m +CONFIG_GPIO_VIRTIO=m +# end of Virtual GPIO drivers + +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# end of 1-wire Slaves + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_PDA_POWER=m +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_CPCAP=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_BQ27XXX_HDQ=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_GPIO=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MP2629=m +# CONFIG_CHARGER_BQ2415X is not set +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_ADT7310 is not set +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ASPEED=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_MAX1111 is not set +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +# CONFIG_SENSORS_MAX197 is not set +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +# CONFIG_SENSORS_MENF21BMC_HWMON is not set +CONFIG_SENSORS_MR75203=m +# CONFIG_SENSORS_ADCXX is not set +CONFIG_SENSORS_LM63=m +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +# CONFIG_SENSORS_NTC_THERMISTOR is not set +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_FSP_3Y=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SFCTEMP=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +# CONFIG_SENSORS_ADS7871 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_IDLE_THERMAL is not set +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=m +CONFIG_MAX77620_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_MENF21BMC_WATCHDOG is not set +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_STARFIVE_WATCHDOG=y + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +CONFIG_MFD_ATMEL_HLCDC=m +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_HTC_PASIC3=m +# CONFIG_HTC_I2CPLD is not set +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_MFD_INTEL_PMT=m +CONFIG_MFD_IQS62X=m +# CONFIG_MFD_JANZ_CMODIO is not set +CONFIG_MFD_KEMPLD=m +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6397 is not set +CONFIG_MFD_MENF21BMC=m +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=m +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +CONFIG_MFD_SKY81452=m +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +# CONFIG_MFD_LP8788 is not set +CONFIG_MFD_TI_LMU=m +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_LM3533=m +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD70528=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +# CONFIG_RAVE_SP_CORE is not set +CONFIG_MFD_INTEL_M10_BMC=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_88PG86X=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP15060=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA9121=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +# CONFIG_REGULATOR_ISL6271A is not set +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +CONFIG_REGULATOR_LP873X=m +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_ROHM=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STARFIVE_JH7110=y +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=m +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_RC_MAP=m +CONFIG_LIRC=y +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_RC_ATI_REMOTE=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SIR=m +CONFIG_RC_XBOX_DVD=m +CONFIG_IR_TOY=m +CONFIG_CEC_CORE=y +CONFIG_CEC_NOTIFIER=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +# CONFIG_VIDEO_DEV is not set +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Media controller options +# +CONFIG_MEDIA_CONTROLLER_DVB=y +# end of Media controller options + +# +# Digital TV options +# +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# + +# +# Analog TV USB devices +# + +# +# Analog/digital TV USB devices +# + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_AS102=m + +# +# Webcam, TV (analog/digital) USB devices +# + +# +# Software defined radio USB devices +# +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# + +# +# Media capture/analog TV support +# + +# +# Media capture/analog/hybrid TV support +# + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_DM1105=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_SMIPCIE=m +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_VIDEO_TVEEPROM=m +CONFIG_TTPCI_EEPROM=m +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_CADENCE=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_S5H1411=m +CONFIG_DVB_MXL692=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_TC90522=m +CONFIG_DVB_MN88443X=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_DRX39XYJ=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_HELENE=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DP_AUX_CHARDEV=y +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_CMA_HELPER=y +CONFIG_DRM_KMS_CMA_HELPER=y +CONFIG_DRM_GEM_SHMEM_HELPER=y +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=y +CONFIG_DRM_I2C_NXP_TDA9950=m +# end of I2C encoder or helper chips + +# +# ARM devices +# +CONFIG_DRM_KOMEDA=m +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +# CONFIG_DRM_AMD_DC_HDCP is not set +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_DRM_NOUVEAU=m +# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_RCAR_LVDS=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX424AKP=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_LONTIUM_LT8912B=m +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_DW_HDMI=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +CONFIG_DRM_DW_HDMI_CEC=m +# end of Display Interface Bridges + +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV_THERMAL=y +# CONFIG_DRM_MXSFB is not set +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_SIMPLEDRM=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_VERISILICON=y +CONFIG_VERISILICON_VIRTUAL_DISPLAY=y +CONFIG_VERISILICON_DW_MIPI_DSI=y +CONFIG_VERISILICON_MMU=y +CONFIG_VERISILICON_DEC=y +CONFIG_STARFIVE_INNO_HDMI=y +CONFIG_STARFIVE_DSI=y +CONFIG_DRM_I2C_ADV7513=m +CONFIG_DRM_IMG=y +CONFIG_DRM_IMG_ROGUE=y +CONFIG_DRM_LEGACY=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_I740=m +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SMSCUFX=m +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +CONFIG_FB_GOLDFISH=m +CONFIG_FB_VIRTUAL=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_CTL_VALIDATION is not set +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_PREALLOC_SIZE=1024 +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_ADI is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# end of SoC Audio for Freescale CPUs + +# CONFIG_SND_I2S_HI6210_I2S is not set +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_STARFIVE=y +CONFIG_SND_SOC_STARFIVE_PWMDAC=y +# CONFIG_SND_SOC_STARFIVE_PWMDAC_PCM is not set +CONFIG_SND_SOC_STARFIVE_I2S=y +CONFIG_SND_SOC_STARFIVE_PDM=y +CONFIG_SND_SOC_STARFIVE_TDM=y +CONFIG_SND_SOC_STARFIVE_SPDIF=y +# CONFIG_SND_SOC_STARFIVE_SPDIF_PCM is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +CONFIG_SND_SOC_AC108=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_AK5558 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_BD28623 is not set +# CONFIG_SND_SOC_BT_SCO is not set +# CONFIG_SND_SOC_CPCAP is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +# CONFIG_SND_SOC_CS35L34 is not set +# CONFIG_SND_SOC_CS35L35 is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS42L42 is not set +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4234 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_CS43130 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS53L30 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DA7213 is not set +# CONFIG_SND_SOC_DMIC is not set +CONFIG_SND_SOC_HDMI_CODEC=y +# CONFIG_SND_SOC_ES7134 is not set +# CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8316 is not set +# CONFIG_SND_SOC_ES8328_I2C is not set +# CONFIG_SND_SOC_ES8328_SPI is not set +# CONFIG_SND_SOC_GTM601 is not set +# CONFIG_SND_SOC_ICS43432 is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_LOCHNAGAR_SC is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MAX98504 is not set +# CONFIG_SND_SOC_MAX9867 is not set +# CONFIG_SND_SOC_MAX98927 is not set +# CONFIG_SND_SOC_MAX98373_I2C is not set +# CONFIG_SND_SOC_MAX98373_SDW is not set +# CONFIG_SND_SOC_MAX98390 is not set +# CONFIG_SND_SOC_MAX9860 is not set +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1789_I2C is not set +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +# CONFIG_SND_SOC_PCM186X_I2C is not set +# CONFIG_SND_SOC_PCM186X_SPI is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK817 is not set +# CONFIG_SND_SOC_RT1308_SDW is not set +# CONFIG_SND_SOC_RT1316_SDW is not set +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +# CONFIG_SND_SOC_RT5640 is not set +# CONFIG_SND_SOC_RT5659 is not set +# CONFIG_SND_SOC_RT5682_SDW is not set +# CONFIG_SND_SOC_RT700_SDW is not set +# CONFIG_SND_SOC_RT711_SDW is not set +# CONFIG_SND_SOC_RT711_SDCA_SDW is not set +# CONFIG_SND_SOC_RT715_SDW is not set +# CONFIG_SND_SOC_RT715_SDCA_SDW is not set +# CONFIG_SND_SOC_SDW_MOCKUP is not set +# CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set +# CONFIG_SND_SOC_SIMPLE_MUX is not set +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS2562 is not set +# CONFIG_SND_SOC_TAS2764 is not set +# CONFIG_SND_SOC_TAS2770 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +# CONFIG_SND_SOC_TAS6424 is not set +# CONFIG_SND_SOC_TDA7419 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set +# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TLV320ADCX140 is not set +# CONFIG_SND_SOC_TS3A227E is not set +# CONFIG_SND_SOC_TSCS42XX is not set +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WCD938X_SDW is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8524 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +# CONFIG_SND_SOC_WM8804_I2C is not set +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +CONFIG_SND_SOC_WM8960=y +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_WSA881X is not set +# CONFIG_SND_SOC_ZL38060 is not set +# CONFIG_SND_SOC_MAX9759 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_NAU8824 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_VIRTIO=m +CONFIG_AC97_BUS=y + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_GOODIX=m +# end of I2C HID support + +CONFIG_I2C_HID_CORE=m +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_FOTG210_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +# CONFIG_USB_SL811_HCD_ISO is not set +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DUAL_ROLE is not set + +# +# Platform Glue Layer +# + +# +# MUSB DMA mode +# +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC2=m +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=m +# CONFIG_USB_CHIPIDEA_UDC is not set +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_IMX=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_TEGRA=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_DUAL_ROLE is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +# CONFIG_USB_CHAOSKEY is not set +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_USB_ISP1301=m +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_U_SERIAL_CONSOLE=y + +# +# USB Peripheral Controller +# +# CONFIG_USB_FOTG210_UDC is not set +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SNP_UDC_PLAT=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=m +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_TCM=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_RAW_GADGET=m +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_PI3USB30532=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_CRYPTO=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_ARMMMCI=m +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +# CONFIG_MMC_SDHCI_MILBEAUT is not set +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_AM654=m +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y + +# +# LED drivers +# +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_TCA6507=m +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_OCRDMA=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_QEDR=m +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_SIFIVE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_SD3078=m + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +CONFIG_RTC_DRV_MAX6916=m +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_PCF2127=m +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_RTC_DRV_NTXEC=m +CONFIG_RTC_DRV_STARFIVE=y + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_PL030=y +CONFIG_RTC_DRV_PL031=y +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_AMBA_PL08X=y +CONFIG_DW_AXI_DMAC=y +CONFIG_DW_AXI_DMAC_STARFIVE=y +CONFIG_FSL_EDMA=m +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +CONFIG_PLX_DMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_HD44780_COMMON=m +CONFIG_HD44780=m +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PARPORT_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +CONFIG_PANEL=m +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_VIRQFD=m +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_VFIO_MDEV=m +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +CONFIG_VP_VDPA=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_COMEDI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +# CONFIG_COMEDI_MISC_DRIVERS is not set +# CONFIG_COMEDI_ISA_DRIVERS is not set +# CONFIG_COMEDI_PCI_DRIVERS is not set +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_ROUTING=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_R8188EU=m +CONFIG_88EU_AP_MODE=y +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# CONFIG_AD7280 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Capacitance to digital converters +# +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +CONFIG_FB_SM750=m +CONFIG_STAGING_MEDIA=y + +# +# Android +# +CONFIG_ASHMEM=y +# end of Android + +# CONFIG_STAGING_BOARD is not set +CONFIG_LTE_GDM724X=m +CONFIG_FIREWIRE_SERIAL=m +CONFIG_FWTTY_MAX_TOTAL_PORTS=64 +CONFIG_FWTTY_MAX_CARD_PORTS=32 +# CONFIG_GS_FPGABOOT is not set +# CONFIG_UNISYSSPAR is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_FB_TFT_WATTEROTT=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +CONFIG_WFX=m +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIPE=m +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +CONFIG_ICST=y +CONFIG_CLK_SP810=y +# end of Clock driver for ARM Reference designs + +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SI5341=m +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_STARFIVE_JH7110=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_XILINX_VCU=m +CONFIG_HWSPINLOCK=y + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_RISCV_TIMER=y +CONFIG_STARFIVE_TIMER=y +# CONFIG_MICROCHIP_PIT64B is not set +# end of Clock Source drivers + +CONFIG_MAILBOX=y +# CONFIG_ARM_MHU is not set +CONFIG_ARM_MHU_V2=m +CONFIG_PLATFORM_MHU=m +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_STARFIVE_MBOX=m +CONFIG_STARFIVE_MBOX_TEST=m +CONFIG_IOMMU_IOVA=m +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_OF_IOMMU=y + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_QCOM=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +CONFIG_SIFIVE_L2=y +CONFIG_SIFIVE_L2_FLUSH=y +CONFIG_SIFIVE_L2_FLUSH_START=0x40000000 +CONFIG_SIFIVE_L2_FLUSH_SIZE=0x400000000 +CONFIG_STARFIVE_PMU=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_PTN5150=m +# CONFIG_EXTCON_RT8973A is not set +CONFIG_EXTCON_SM5502=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_ARM_PL172_MPMC=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +CONFIG_ADXL372=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +CONFIG_MC3230=m +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +CONFIG_MMA9551_CORE=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +# end of Accelerometers + +# +# Analog to digital converters +# +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +# CONFIG_CC10001_ADC is not set +CONFIG_CPCAP_ADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +# CONFIG_MAX1027 is not set +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX1241=m +# CONFIG_MAX1363 is not set +CONFIG_MAX9611=m +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +CONFIG_MCP3911=m +CONFIG_MP2629_ADC=m +# CONFIG_NAU7802 is not set +CONFIG_QCOM_VADC_COMMON=m +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_SD_ADC_MODULATOR=m +# CONFIG_TI_ADC081C is not set +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +# CONFIG_TI_ADC128S052 is not set +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +# CONFIG_TI_AM335X_ADC is not set +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_XILINX_XADC=m +# end of Analog to digital converters + +# +# Analog Front Ends +# +CONFIG_IIO_RESCALE=m +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +CONFIG_HMC425=m +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_VZ89X=m +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +CONFIG_IIO_MS_SENSORS_I2C=m + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +CONFIG_AD5592R_BASE=m +CONFIG_AD5592R=m +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +# CONFIG_AD5755 is not set +CONFIG_AD5758=m +CONFIG_AD5761=m +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +# CONFIG_AD7303 is not set +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +# CONFIG_MAX517 is not set +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +CONFIG_ADF4371=m +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +CONFIG_AM2315=m +# CONFIG_DHT11 is not set +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +CONFIG_IIO_ST_LSM9DS0=m +CONFIG_IIO_ST_LSM9DS0_I2C=m +CONFIG_IIO_ST_LSM9DS0_SPI=m +# end of Inertial measurement units + +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=m +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9960=m +CONFIG_AS73211=m +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +CONFIG_IQS621_ALS=m +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_RPR0521=m +# CONFIG_SENSORS_LM3533 is not set +# CONFIG_LTR501 is not set +CONFIG_LV0104CS=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +# CONFIG_STK3310 is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +CONFIG_TSL2591=m +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_US5182D=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +# CONFIG_VEML6070 is not set +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +# end of Light sensors + +# +# Magnetometer sensors +# +CONFIG_AK8974=m +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_RM3100=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +CONFIG_IIO_MUX=m +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +CONFIG_IIO_HRTIMER_TRIGGER=m +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +CONFIG_IQS624_POS=m +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +CONFIG_AD5110=m +CONFIG_AD5272=m +# CONFIG_DS1803 is not set +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +# CONFIG_MCP4131 is not set +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +# end of Digital potentiometers + +# +# Digital potentiostats +# +CONFIG_LMP91000=m +# end of Digital potentiostats + +# +# Pressure sensors +# +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +CONFIG_ICP10100=m +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX9310=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +CONFIG_MLX90632=m +# CONFIG_TMP006 is not set +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX31856=m +# end of Temperature sensors + +CONFIG_NTB=y +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +# CONFIG_NTB_PINGPONG is not set +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +# CONFIG_NTB_MSI_TEST is not set +CONFIG_NTB_TRANSPORT=m +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_STARFIVE_PTC=m + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_AL_FIC=y +CONFIG_MADERA_IRQ=m +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_BCM_KONA_USB2_PHY=m +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_MIXEL_MIPI_DPHY=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_TUSB1210 is not set +CONFIG_PHY_M31_DPHY_RX0=m +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +CONFIG_RAS=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +CONFIG_LIBNVDIMM=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_BLK=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +CONFIG_OF_PMEM=m +CONFIG_NVDIMM_KEYS=y +CONFIG_DAX_DRIVER=y +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_SPMI_SDAM=m +# CONFIG_NVMEM_RMEM is not set + +# +# HW tracing support +# +CONFIG_STM=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +# CONFIG_STM_DUMMY is not set +CONFIG_STM_SOURCE_CONSOLE=y +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STM_SOURCE_FTRACE=m +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set +CONFIG_FPGA_DFL_PCI=m +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_RISCV_STARFIVE_CPUFREQ=y +# end of CPU Frequency scaling +# end of Device Drivers + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_DAX=y +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_FUSE_DAX=y +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +CONFIG_QNX6FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_ROMFS_FS=m +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_ZSTD_COMPRESS=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EROFS_FS=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_ENCRYPTED_KEYS=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY_FALLBACK is not set +# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ENGINE=y + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CHACHA20POLY1305=m +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_NHPOLY1305=m +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ESSIV=m + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_XXHASH=m +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +CONFIG_CRYPTO_RMD160=m +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_STREEBOG=m +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +# CONFIG_CRYPTO_SM4 is not set +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=y + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_USER_API_AKCIPHER=m +CONFIG_CRYPTO_USER_API_KPP=m +CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=m +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_JH7110_ENCRYPT=y +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_TPM_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +CONFIG_PACKING=y +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=m +CONFIG_CRC4=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=y +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=y +CONFIG_842_DECOMPRESS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_BCH=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +CONFIG_FONT_TER16x32=y +# CONFIG_FONT_6x8 is not set +CONFIG_SG_POOL=y +CONFIG_MEMREGION=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_STACK_HASH_ORDER=20 +CONFIG_SBITMAP=y +CONFIG_PARMAN=m +CONFIG_OBJAGG=m +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_COMPRESSED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_DEBUG_INFO_BTF=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_TORTURE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_OSNOISE_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# riscv Debugging +# + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage +# end of Kernel hacking diff --git a/srcpkgs/Visionfive2-kernel/files/mv-debug b/srcpkgs/Visionfive2-kernel/files/mv-debug new file mode 100755 index 0000000000000..4b0fcabe0e4e4 --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/files/mv-debug @@ -0,0 +1,7 @@ +#!/bin/sh +mod=$1 +mkdir -p usr/lib/debug/${mod%/*} +$OBJCOPY --only-keep-debug --compress-debug-sections $mod usr/lib/debug/$mod +$OBJCOPY --add-gnu-debuglink=${DESTDIR}/usr/lib/debug/$mod $mod +/usr/bin/$STRIP --strip-debug $mod +zstd --rm -19 $mod diff --git a/srcpkgs/Visionfive2-kernel/patches/0001-gcc12.patch b/srcpkgs/Visionfive2-kernel/patches/0001-gcc12.patch new file mode 100644 index 0000000000000..094dba33508cc --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/patches/0001-gcc12.patch @@ -0,0 +1,55 @@ +From: Aurelien Jarno +To: linux-kernel@vger.kernel.org +Cc: Aurelien Jarno , + stable@vger.kernel.org, Kito Cheng , + Paul Walmsley , + Palmer Dabbelt , + Albert Ou , + linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) +Subject: [PATCH] riscv: fix build with binutils 2.38 +Date: Wed, 26 Jan 2022 18:14:42 +0100 [thread overview] +Message-ID: <20220126171442.1338740-1-aurelien@aurel32.net> (raw) + +From version 2.38, binutils default to ISA spec version 20191213. This +means that the csr read/write (csrr*/csrw*) instructions and fence.i +instruction has separated from the `I` extension, become two standalone +extensions: Zicsr and Zifencei. As the kernel uses those instruction, +this causes the following build failure: + + CC arch/riscv/kernel/vdso/vgettimeofday.o + <>/arch/riscv/include/asm/vdso/gettimeofday.h: Assembler messages: + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' + <>/arch/riscv/include/asm/vdso/gettimeofday.h:71: Error: unrecognized opcode `csrr a5,0xc01' + +The fix is to specify those extensions explicitely in -march. However as +older binutils version do not support this, we first need to detect +that. + +Cc: stable@vger.kernel.org # 4.15+ +Cc: Kito Cheng +Signed-off-by: Aurelien Jarno +--- + arch/riscv/Makefile | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile +index 8a107ed18b0d..7d81102cffd4 100644 +--- a/arch/riscv/Makefile ++++ b/arch/riscv/Makefile +@@ -50,6 +50,12 @@ riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima + riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima + riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd + riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c ++ ++# Newer binutils versions default to ISA spec version 20191213 which moves some ++# instructions from the I extension to the Zicsr and Zifencei extensions. ++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -march=$(riscv-march-y)_zicsr_zifencei) ++riscv-march-$(toolchain-need-zicsr-zifencei) := $(riscv-march-y)_zicsr_zifencei ++ + KBUILD_CFLAGS += -march=$(subst fd,,$(riscv-march-y)) + KBUILD_AFLAGS += -march=$(riscv-march-y) + +-- +2.34.1 diff --git a/srcpkgs/Visionfive2-kernel/patches/0002-gcc12.patch b/srcpkgs/Visionfive2-kernel/patches/0002-gcc12.patch new file mode 100644 index 0000000000000..0a59783c4c26b --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/patches/0002-gcc12.patch @@ -0,0 +1,55 @@ +While the current code builds fine with gcc 11, it does not with gcc 12, +resulting in: + +In file included from help.c:12: +In function 'xrealloc', + inlined from 'add_cmdname' at help.c:24:2: +subcmd-util.h:56:23: error: pointer may be used after 'realloc' [-Werror=use-after-free] + 56 | ret = realloc(ptr, size); + | ^~~~~~~~~~~~~~~~~~ +subcmd-util.h:52:21: note: call to 'realloc' here + 52 | void *ret = realloc(ptr, size); + | ^~~~~~~~~~~~~~~~~~ +subcmd-util.h:58:31: error: pointer may be used after 'realloc' [-Werror=use-after-free] + 58 | ret = realloc(ptr, 1); + | ^~~~~~~~~~~~~~~ +subcmd-util.h:52:21: note: call to 'realloc' here + 52 | void *ret = realloc(ptr, size); + | ^~~~~~~~~~~~~~~~~~ + +The was mentioned in upstream gcc bug +https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104069 where it was +determined that gcc was correct and the kernel needed to change. This +fixes that use-after-free and makes things build again. + +Signed-off-by: Justin M. Forbes <jforbes@xxxxxxxxxxxxxxxxx> +Cc: Jakub Jelinek <jakub@xxxxxxxxxx> + +--- + tools/lib/subcmd/subcmd-util.h | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +diff --git a/tools/lib/subcmd/subcmd-util.h b/tools/lib/subcmd/subcmd-util.h +index 794a375dad36..7009fc176636 100644 +--- a/tools/lib/subcmd/subcmd-util.h ++++ b/tools/lib/subcmd/subcmd-util.h +@@ -49,13 +49,12 @@ static NORETURN inline void die(const char *err, ...) + + static inline void *xrealloc(void *ptr, size_t size) + { +- void *ret = realloc(ptr, size); +- if (!ret && !size) +- ret = realloc(ptr, 1); ++ void *ret; ++ if (!size) ++ size = 1; ++ ret = realloc(ptr, size); + if (!ret) { + ret = realloc(ptr, size); +- if (!ret && !size) +- ret = realloc(ptr, 1); + if (!ret) + die("Out of memory, realloc failed"); + } +-- +2.34.1 diff --git a/srcpkgs/Visionfive2-kernel/patches/pls-dont-pick-only-half-a-patch.patch b/srcpkgs/Visionfive2-kernel/patches/pls-dont-pick-only-half-a-patch.patch new file mode 100644 index 0000000000000..30801abc7f922 --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/patches/pls-dont-pick-only-half-a-patch.patch @@ -0,0 +1,13 @@ +Seomeone picked half of 215bebc8c6ac438c382a6a56bd2764a2d4e1da72 but didn't want the other half... +--- +--- Visionfive2-kernel-5.15.0/security/keys/dh.c 2023-01-11 16:29:35.000000000 +0100 ++++ - 2023-02-01 22:15:10.262387290 +0100 +@@ -14,7 +14,7 @@ + #include + #include "internal.h" + +-static ssize_t dh_data_from_key(key_serial_t keyid, void **data) ++static ssize_t dh_data_from_key(key_serial_t keyid, const void **data) + { + struct key *key; + key_ref_t key_ref; diff --git a/srcpkgs/Visionfive2-kernel/template b/srcpkgs/Visionfive2-kernel/template new file mode 100644 index 0000000000000..06a44654dde1c --- /dev/null +++ b/srcpkgs/Visionfive2-kernel/template @@ -0,0 +1,244 @@ +# Template file for 'Visionfive2-kernel' +pkgname=Visionfive2-kernel +version=5.15.0 +_tag=VF2_v2.8.0 +revision=1 +archs="riscv64*" +wrksrc="linux-${_tag}" +hostmakedepends="tar xz bc elfutils-devel flex gmp-devel kmod libmpc-devel + openssl-devel perl uboot-mkimage cpio pahole python3 zstd" +short_desc="Vendor Kernel for Wondershare Visionfive2" +maintainer="John " +license="GPL-3.0-or-later" +homepage="https://github.com/starfive-tech/VisionFive2" +distfiles="https://github.com/starfive-tech/linux/archive/${_tag}.tar.gz" +checksum=c97a15c8a195b3b974a51d0d54edf418a7982b1d56706d7456e2c00034f8729c + +python_version=3 +odebug=yes # -dbg package is generated below manually +nostrip=yes +noverifyrdeps=yes +noshlibprovides=yes +preserve=yes + +_kernver="${version}_${revision}" +triggers="kernel-hooks" +kernel_hooks_version="${_kernver}" + +# These files could be modified when an external module is built. +mutable_files=" + /usr/lib/modules/${_kernver}/modules.builtin.bin + /usr/lib/modules/${_kernver}/modules.builtin.alias.bin + /usr/lib/modules/${_kernver}/modules.softdep + /usr/lib/modules/${_kernver}/modules.dep + /usr/lib/modules/${_kernver}/modules.dep.bin + /usr/lib/modules/${_kernver}/modules.symbols + /usr/lib/modules/${_kernver}/modules.symbols.bin + /usr/lib/modules/${_kernver}/modules.alias + /usr/lib/modules/${_kernver}/modules.alias.bin + /usr/lib/modules/${_kernver}/modules.devname" + +# reproducible build +export KBUILD_BUILD_TIMESTAMP=$(LC_ALL=C date -ud @${SOURCE_DATE_EPOCH:-0}) +export KBUILD_BUILD_USER=voidlinux +export KBUILD_BUILD_HOST=voidlinux + +if [ "$CROSS_BUILD" ]; then + _cross="CROSS_COMPILE=${XBPS_CROSS_TRIPLET}-" +fi + +pre_patch() { + xzcat $XBPS_SRCDISTDIR/$pkgname-$version/patch-${version}.xz | patch -Np1 +} + +do_configure() { + local arch + + arch=riscv + + cp -f ${FILESDIR}/dotconfig .config + make ${makejobs} ARCH=$arch ${_cross} oldconfig + + # Always use our revision to CONFIG_LOCALVERSION to match our pkg version. + sed -i -e "s|^\(CONFIG_LOCALVERSION=\).*|\1\"_${revision}\"|" .config +} + +do_build() { + local arch _args + + _args="Image modules dtbs" + arch=riscv + + export LDFLAGS= + make ARCH=$arch ${_cross} ${makejobs} prepare + make ARCH=$arch ${_cross} ${makejobs} ${_args} +} + +do_install() { + local arch subarch _args hdrdest + + arch=riscv + + # Run depmod after compressing modules. + sed -i '2iexit 0' scripts/depmod.sh + + # Install kernel, firmware and modules + make ${makejobs} ARCH=${subarch:-$arch} INSTALL_MOD_PATH=${DESTDIR} ${_cross} modules_install + + hdrdest=${DESTDIR}/usr/src/kernel-headers-${_kernver} + + vinstall .config 644 boot config-${_kernver} + vinstall System.map 644 boot System.map-${_kernver} + + vinstall arch/riscv/boot/Image 644 boot vmlinux-${_kernver} + make ${makejobs} ARCH=${subarch:-$arch} INSTALL_DTBS_PATH=${DESTDIR}/boot/dtbs/dtbs-${_kernver} ${_cross} dtbs_install + + # Switch to /usr. + vmkdir usr + mv ${DESTDIR}/lib ${DESTDIR}/usr + + cd ${DESTDIR}/usr/lib/modules/${_kernver} + rm -f source build + ln -sf ../../../src/kernel-headers-${_kernver} build + + cd ${wrksrc} + # Install required headers to build external modules + install -Dm644 Makefile ${hdrdest}/Makefile + install -Dm644 kernel/Makefile ${hdrdest}/kernel/Makefile + install -Dm644 .config ${hdrdest}/.config + for file in $(find . -name Kconfig\*); do + mkdir -p ${hdrdest}/$(dirname $file) + install -Dm644 $file ${hdrdest}/${file} + done + for file in $(find arch/${subarch:-$arch} scripts -name module.lds -o -name Kbuild.platforms -o -name Platform); do + mkdir -p ${hdrdest}/$(dirname $file) + install -Dm644 $file ${hdrdest}/${file} + done + mkdir -p ${hdrdest}/include + # Remove firmware stuff provided by the "linux-firmware" pkg. + rm -rf ${DESTDIR}/usr/lib/firmware + + for i in acpi asm-generic clocksource config crypto drm generated linux vdso \ + math-emu media net pcmcia scsi sound trace uapi video xen dt-bindings; do + if [ -d include/$i ]; then + cp -a include/$i ${hdrdest}/include + fi + done + + cd ${wrksrc} + mkdir -p ${hdrdest}/arch/${arch} + cp -a arch/${arch}/include ${hdrdest}/arch/${arch} + + # Remove helper binaries built for host, + # if generated files from the scripts/ directory need to be included, + # they need to be copied to ${hdrdest} before this step + if [ "$CROSS_BUILD" ]; then + make ${makejobs} ARCH=${subarch:-$arch} ${_cross} _mrproper_scripts + # remove host specific objects as well + find scripts -name '*.o' -delete + fi + + # Copy files necessary for later builds, like nvidia and vmware + cp Module.symvers ${hdrdest} + cp -a scripts ${hdrdest} + mkdir -p ${hdrdest}/security/selinux + cp -a security/selinux/include ${hdrdest}/security/selinux + mkdir -p ${hdrdest}/tools/include + cp -a tools/include/tools ${hdrdest}/tools/include + + mkdir -p ${hdrdest}/arch/${arch}/kernel + cp arch/${arch}/Makefile ${hdrdest}/arch/${arch} + + mkdir -p ${hdrdest}/arch/riscv/kernel + cp -a arch/riscv/kernel/vdso ${hdrdest}/arch/riscv/kernel/ + + # add headers for lirc package + # pci + for i in bt8xx cx88 saa7134; do + mkdir -p ${hdrdest}/drivers/media/pci/${i} + cp -a drivers/media/pci/${i}/*.h ${hdrdest}/drivers/media/pci/${i} + done + # usb + for i in cpia2 em28xx pwc; do + mkdir -p ${hdrdest}/drivers/media/usb/${i} + cp -a drivers/media/usb/${i}/*.h ${hdrdest}/drivers/media/usb/${i} + done + # i2c + mkdir -p ${hdrdest}/drivers/media/i2c + cp drivers/media/i2c/*.h ${hdrdest}/drivers/media/i2c + for i in cx25840; do + mkdir -p ${hdrdest}/drivers/media/i2c/${i} + cp -a drivers/media/i2c/${i}/*.h ${hdrdest}/drivers/media/i2c/${i} + done + + # Add md headers + mkdir -p ${hdrdest}/drivers/md + cp drivers/md/*.h ${hdrdest}/drivers/md + + # Add inotify.h + mkdir -p ${hdrdest}/include/linux + cp include/linux/inotify.h ${hdrdest}/include/linux + + # Add wireless headers + mkdir -p ${hdrdest}/net/mac80211/ + cp net/mac80211/*.h ${hdrdest}/net/mac80211 + + # add dvb headers for http://mcentral.de/hg/~mrec/em28xx-new + cp drivers/media/i2c/msp3400-driver.h ${hdrdest}/drivers/media/i2c/ + + # add dvb headers + mkdir -p ${hdrdest}/drivers/media/usb/dvb-usb + cp drivers/media/usb/dvb-usb/*.h ${hdrdest}/drivers/media/usb/dvb-usb/ + mkdir -p ${hdrdest}/drivers/media/dvb-frontends + cp drivers/media/dvb-frontends/*.h ${hdrdest}/drivers/media/dvb-frontends/ + mkdir -p ${hdrdest}/drivers/media/tuners + cp drivers/media/tuners/*.h ${hdrdest}/drivers/media/tuners/ + + # Add xfs and shmem for aufs building + mkdir -p ${hdrdest}/fs/xfs/libxfs + mkdir -p ${hdrdest}/mm + cp fs/xfs/libxfs/xfs_sb.h ${hdrdest}/fs/xfs/libxfs/xfs_sb.h + + # Remove unneeded architectures + for arch in alpha avr32 blackfin cris frv h8300 \ + ia64 m* s* um v850 xtensa x86* p*; do + rm -rf ${hdrdest}/arch/${arch} + done + # Keep arch/x86/ras/Kconfig as it is needed by drivers/ras/Kconfig + mkdir -p ${hdrdest}/arch/x86/ras + cp -a arch/x86/ras/Kconfig ${hdrdest}/arch/x86/ras/Kconfig + + # Extract debugging symbols and compress modules + msg_normal "$pkgver: extracting debug info and compressing modules, please wait...\n" + install -Dm644 vmlinux ${DESTDIR}/usr/lib/debug/boot/vmlinux-${_kernver} + ( + cd ${DESTDIR} + export DESTDIR + find ./ -name '*.ko' -print0 | \ + xargs -0r -n1 -P ${XBPS_MAKEJOBS} ${FILESDIR}/mv-debug + ) + # ... and run depmod again. + depmod -b ${DESTDIR}/usr -F System.map ${_kernver} +} +Visionfive2-kernel-headers_package() { + preserve=yes + nostrip=yes + noshlibprovides=yes + short_desc+=" - source headers for 3rd party modules" + pkg_install() { + vmove usr/src + vmove usr/lib/modules/${_kernver}/build + } +} +Visionfive2-kernel-dbg_package() { + preserve=yes + nostrip=yes + noverifyrdeps=yes + noshlibprovides=yes + repository=debug + short_desc+=" - debugging symbols" + pkg_install() { + vmove usr/lib/debug + vmove "boot/System.map-${_kernver}" + } +} From 667a339cb70fe51f629cee5970bd0c336f405704 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 21 Feb 2023 13:11:30 +0100 Subject: [PATCH 139/189] firebird3: update to 3.0.10. --- srcpkgs/firebird3/patches/riscv64.patch | 132 ++++++++++++++++++++++++ srcpkgs/firebird3/template | 15 +-- 2 files changed, 140 insertions(+), 7 deletions(-) create mode 100644 srcpkgs/firebird3/patches/riscv64.patch diff --git a/srcpkgs/firebird3/patches/riscv64.patch b/srcpkgs/firebird3/patches/riscv64.patch new file mode 100644 index 0000000000000..9be83e42b7b80 --- /dev/null +++ b/srcpkgs/firebird3/patches/riscv64.patch @@ -0,0 +1,132 @@ +--- a/src/common/classes/DbImplementation.cpp 2023-02-01 19:30:57.076858326 +0100 ++++ - 2023-02-01 19:33:15.127538628 +0100 +@@ -49,6 +49,7 @@ + static const UCHAR CpuArm64 = 15; + static const UCHAR CpuPowerPc64el = 16; + static const UCHAR CpuM68k = 17; ++static const UCHAR CpuRiscV64 = 18; + + static const UCHAR OsWindows = 0; + static const UCHAR OsLinux = 1; +@@ -89,7 +90,8 @@ + "Alpha", + "ARM64", + "PowerPC64el", +- "M68k" ++ "M68k", ++ "RiscV64" + }; + + const char* operatingSystem[] = { +@@ -116,22 +118,22 @@ + // This table lists pre-fb3 implementation codes + const UCHAR backwardTable[FB_NELEM(hardware) * FB_NELEM(operatingSystem)] = + { +-// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el +-/* Windows */ 50, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* Linux */ 60, 66, 65, 69, 86, 71, 72, 75, 76, 79, 78, 80, 81, 82, 83, 84, 85, +-/* Darwin */ 70, 73, 0, 63, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* Solaris */ 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* HPUX */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, +-/* AIX */ 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* MVS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* FreeBSD */ 61, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +-/* NetBSD */ 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ++// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k RiscV64 ++/* Windows */ 50, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* Linux */ 60, 66, 65, 69, 86, 71, 72, 75, 76, 79, 78, 80, 81, 82, 83, 84, 85, 87, 88, ++/* Darwin */ 70, 73, 0, 63, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* Solaris */ 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* HPUX */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, ++/* AIX */ 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* MVS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* FreeBSD */ 61, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++/* NetBSD */ 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }; + + const UCHAR backEndianess[FB_NELEM(hardware)] = + { +-// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k +- 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 1 ++// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k Riscv64 ++ 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0 + }; + + } // anonymous namespace +--- a/src/common/common.h 2023-02-01 19:33:54.143740923 +0100 ++++ - 2023-02-01 19:34:01.240793843 +0100 +@@ -135,6 +135,10 @@ + #define FB_CPU CpuArm64 + #endif /* ARM64 */ + ++#ifdef RISCV64 ++#define FB_CPU CpuRiscV64 ++#endif /* RISCV64 */ ++ + #ifdef sparc + #define FB_CPU CpuUltraSparc + #define RISC_ALIGNMENT +--- a/src/jrd/inf_pub.h 2023-02-01 19:35:06.223507281 +0100 ++++ - 2023-02-01 19:35:09.457639774 +0100 +@@ -245,7 +245,7 @@ + isc_info_db_impl_linux_ppc64el = 85, + isc_info_db_impl_linux_ppc64 = 86, + isc_info_db_impl_linux_m68k = 87, +- ++ isc_info_db_impl_linux_riscv64 = 88, + + isc_info_db_impl_last_value // Leave this LAST! + }; +--- a/configure.ac 2022-06-07 10:18:52.000000000 +0200 ++++ - 2023-02-01 19:41:02.528880906 +0100 +@@ -251,6 +251,18 @@ + libdir=/usr/lib64 + ;; + ++ riscv64*-*-linux*) ++ MAKEFILE_PREFIX=linux_riscv64 ++ INSTALL_PREFIX=linux ++ PLATFORM=LINUX ++ AC_DEFINE(LINUX, 1, [Define this if OS is Linux]) ++ EDITLINE_FLG=Y ++ SHRLIB_EXT=so ++ STD_EDITLINE=true ++ STD_ICU=true ++ libdir=/usr/lib64 ++ ;; ++ + powerpc64le-*-linux*) + MAKEFILE_PREFIX=linux_powerpc64el + INSTALL_PREFIX=linux +--- /dev/null 2023-01-31 17:00:41.224859885 +0100 ++++ firebird3-3.0.10/builds/posix/prefix.linux_riscv64 2023-02-01 20:07:41.781216748 +0100 +@@ -0,0 +1,29 @@ ++ ++# The contents of this file are subject to the Interbase Public ++# License Version 1.0 (the "License"); you may not use this file ++# except in compliance with the License. You may obtain a copy ++# of the License at http://www.Inprise.com/IPL.html ++# ++# Software distributed under the License is distributed on an ++# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express ++# or implied. See the License for the specific language governing ++# rights and limitations under the License. ++# ++# The Original Code was created by Inprise Corporation ++# and its predecessors. Portions created by Inprise Corporation are ++# Copyright (C) Inprise Corporation. ++# ++# All Rights Reserved. ++# Contributor(s): ______________________________________. ++# Start of file prefix.linux: $(VERSION) $(PLATFORM) ++# 14 Apr 2008 Alan Barclay alan AT escribe.co.uk ++# 2018, "Manuel A. Fernandez Montecelo" ++ ++ ++#LD=@CXX@ ++ ++#PROD_FLAGS=-ggdb -O3 -fno-omit-frame-pointer -DLINUX -pipe -MMD -fPIC ++#DEV_FLAGS=-ggdb -DLINUX -DDEBUG_GDS_ALLOC -pipe -MMD -p -fPIC -Werror=delete-incomplete -Wall -Wno-switch ++ ++PROD_FLAGS=-O3 -DLINUX -DRISCV64 -pipe -p -MMD -fPIC -fsigned-char -fmessage-length=0 -std=gnu++03 -fno-delete-null-pointer-checks ++DEV_FLAGS=-ggdb -DLINUX -DRISCV64 -pipe -p -MMD -fPIC -Werror=delete-incomplete -Wall -fsigned-char -fmessage-length=0 -Wno-non-virtual-dtor diff --git a/srcpkgs/firebird3/template b/srcpkgs/firebird3/template index 575415d2128f1..423c79138e5d3 100644 --- a/srcpkgs/firebird3/template +++ b/srcpkgs/firebird3/template @@ -1,9 +1,9 @@ # Template file for 'firebird3' pkgname=firebird3 -version=3.0.6.33328 +version=3.0.10 +_tag=33601 revision=2 _build=0 -_uver=${version//./_} build_style=gnu-configure build_helper="qemu" configure_args="--prefix=/usr @@ -32,10 +32,10 @@ short_desc="Relational database offering many ANSI SQL standard features (V3)" maintainer="Orphaned " license="custom:IDPL-1.0, Interbase-1.0" homepage="https://www.firebirdsql.org/en/start/" -distfiles="https://github.com/FirebirdSQL/firebird/releases/download/R${_uver%_*}/Firebird-${version}-${_build}.tar.bz2" -checksum=34c1d2a29bbaf288e682cd1b5f8083f2baf73f351062245ace0bee35a3f7d35f +distfiles="https://github.com/FirebirdSQL/firebird/releases/download/v${version}/Firebird-${version}.${_tag}-${_build}.tar.bz2" +checksum=9138bb60d27eabb15947c8bd0184dd7b795cc19ca6324b76db8ff719641f0340 replaces="firebird>=0" -nocross="Fails to build gpre_boot for host but builds for target" +disable_parallel_build="True" CFLAGS="-fno-strict-aliasing" CXXFLAGS="-fno-delete-null-pointer-checks -Wno-deprecated -Wno-deprecated-declarations" @@ -51,7 +51,7 @@ fi pre_configure() { local _arch - if [ "$CROSS_BUILD" ]; then + if false; then # XXX: This is not yet working right and needs more work. # The generated gpre_boot is built with the target C++ and can # not be executed. Trying to run it with qemu--static @@ -67,14 +67,15 @@ pre_configure() { ppc64*) _arch="linux_powerpc64";; ppc*) _arch="linux_powerpc";; x86_64*) _arch="linux_amd64";; + *) msg_error "$XBPS_TARGET_MACHINE has not cross arch set yet";; esac - configure_args+=" --with-cross-build=$_arch" # Remove -msse4 for non-x86_64 arch because it leaks # into the target CXXFLAGS. if [ "$_arch" != "linux_amd64" ]; then vsed -i builds/posix/prefix.linux{,_amd64} -e "s;-msse4;;" fi fi + configure_args+=" --with-cross-build=$_arch" if [ "$XBPS_TARGET_LIBC" = musl ]; then vsed -i -e '/FLAGS=/s/ \-p / /g' \ From d3b32b1e6b12a989ee3e3b1c924504822d5a1779 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 21 Feb 2023 13:11:38 +0100 Subject: [PATCH 140/189] Revert "firebird3: update to 3.0.10." This reverts commit 6bd1b6efec844ca47c8d63013a45af512334928f. --- srcpkgs/firebird3/patches/riscv64.patch | 132 ------------------------ srcpkgs/firebird3/template | 16 +-- 2 files changed, 8 insertions(+), 140 deletions(-) delete mode 100644 srcpkgs/firebird3/patches/riscv64.patch diff --git a/srcpkgs/firebird3/patches/riscv64.patch b/srcpkgs/firebird3/patches/riscv64.patch deleted file mode 100644 index 9be83e42b7b80..0000000000000 --- a/srcpkgs/firebird3/patches/riscv64.patch +++ /dev/null @@ -1,132 +0,0 @@ ---- a/src/common/classes/DbImplementation.cpp 2023-02-01 19:30:57.076858326 +0100 -+++ - 2023-02-01 19:33:15.127538628 +0100 -@@ -49,6 +49,7 @@ - static const UCHAR CpuArm64 = 15; - static const UCHAR CpuPowerPc64el = 16; - static const UCHAR CpuM68k = 17; -+static const UCHAR CpuRiscV64 = 18; - - static const UCHAR OsWindows = 0; - static const UCHAR OsLinux = 1; -@@ -89,7 +90,8 @@ - "Alpha", - "ARM64", - "PowerPC64el", -- "M68k" -+ "M68k", -+ "RiscV64" - }; - - const char* operatingSystem[] = { -@@ -116,22 +118,22 @@ - // This table lists pre-fb3 implementation codes - const UCHAR backwardTable[FB_NELEM(hardware) * FB_NELEM(operatingSystem)] = - { --// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el --/* Windows */ 50, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* Linux */ 60, 66, 65, 69, 86, 71, 72, 75, 76, 79, 78, 80, 81, 82, 83, 84, 85, --/* Darwin */ 70, 73, 0, 63, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* Solaris */ 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* HPUX */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, --/* AIX */ 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* MVS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* FreeBSD */ 61, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, --/* NetBSD */ 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -+// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k RiscV64 -+/* Windows */ 50, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* Linux */ 60, 66, 65, 69, 86, 71, 72, 75, 76, 79, 78, 80, 81, 82, 83, 84, 85, 87, 88, -+/* Darwin */ 70, 73, 0, 63, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* Solaris */ 0, 0, 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* HPUX */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, -+/* AIX */ 0, 0, 0, 35, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* MVS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* FreeBSD */ 61, 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -+/* NetBSD */ 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - }; - - const UCHAR backEndianess[FB_NELEM(hardware)] = - { --// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k -- 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 1 -+// Intel AMD Sparc PPC PPC64 MIPSEL MIPS ARM IA64 s390 s390x SH SHEB HPPA Alpha ARM64 PowerPC64el M68k Riscv64 -+ 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0 - }; - - } // anonymous namespace ---- a/src/common/common.h 2023-02-01 19:33:54.143740923 +0100 -+++ - 2023-02-01 19:34:01.240793843 +0100 -@@ -135,6 +135,10 @@ - #define FB_CPU CpuArm64 - #endif /* ARM64 */ - -+#ifdef RISCV64 -+#define FB_CPU CpuRiscV64 -+#endif /* RISCV64 */ -+ - #ifdef sparc - #define FB_CPU CpuUltraSparc - #define RISC_ALIGNMENT ---- a/src/jrd/inf_pub.h 2023-02-01 19:35:06.223507281 +0100 -+++ - 2023-02-01 19:35:09.457639774 +0100 -@@ -245,7 +245,7 @@ - isc_info_db_impl_linux_ppc64el = 85, - isc_info_db_impl_linux_ppc64 = 86, - isc_info_db_impl_linux_m68k = 87, -- -+ isc_info_db_impl_linux_riscv64 = 88, - - isc_info_db_impl_last_value // Leave this LAST! - }; ---- a/configure.ac 2022-06-07 10:18:52.000000000 +0200 -+++ - 2023-02-01 19:41:02.528880906 +0100 -@@ -251,6 +251,18 @@ - libdir=/usr/lib64 - ;; - -+ riscv64*-*-linux*) -+ MAKEFILE_PREFIX=linux_riscv64 -+ INSTALL_PREFIX=linux -+ PLATFORM=LINUX -+ AC_DEFINE(LINUX, 1, [Define this if OS is Linux]) -+ EDITLINE_FLG=Y -+ SHRLIB_EXT=so -+ STD_EDITLINE=true -+ STD_ICU=true -+ libdir=/usr/lib64 -+ ;; -+ - powerpc64le-*-linux*) - MAKEFILE_PREFIX=linux_powerpc64el - INSTALL_PREFIX=linux ---- /dev/null 2023-01-31 17:00:41.224859885 +0100 -+++ firebird3-3.0.10/builds/posix/prefix.linux_riscv64 2023-02-01 20:07:41.781216748 +0100 -@@ -0,0 +1,29 @@ -+ -+# The contents of this file are subject to the Interbase Public -+# License Version 1.0 (the "License"); you may not use this file -+# except in compliance with the License. You may obtain a copy -+# of the License at http://www.Inprise.com/IPL.html -+# -+# Software distributed under the License is distributed on an -+# "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express -+# or implied. See the License for the specific language governing -+# rights and limitations under the License. -+# -+# The Original Code was created by Inprise Corporation -+# and its predecessors. Portions created by Inprise Corporation are -+# Copyright (C) Inprise Corporation. -+# -+# All Rights Reserved. -+# Contributor(s): ______________________________________. -+# Start of file prefix.linux: $(VERSION) $(PLATFORM) -+# 14 Apr 2008 Alan Barclay alan AT escribe.co.uk -+# 2018, "Manuel A. Fernandez Montecelo" -+ -+ -+#LD=@CXX@ -+ -+#PROD_FLAGS=-ggdb -O3 -fno-omit-frame-pointer -DLINUX -pipe -MMD -fPIC -+#DEV_FLAGS=-ggdb -DLINUX -DDEBUG_GDS_ALLOC -pipe -MMD -p -fPIC -Werror=delete-incomplete -Wall -Wno-switch -+ -+PROD_FLAGS=-O3 -DLINUX -DRISCV64 -pipe -p -MMD -fPIC -fsigned-char -fmessage-length=0 -std=gnu++03 -fno-delete-null-pointer-checks -+DEV_FLAGS=-ggdb -DLINUX -DRISCV64 -pipe -p -MMD -fPIC -Werror=delete-incomplete -Wall -fsigned-char -fmessage-length=0 -Wno-non-virtual-dtor diff --git a/srcpkgs/firebird3/template b/srcpkgs/firebird3/template index 423c79138e5d3..900b69570f0c6 100644 --- a/srcpkgs/firebird3/template +++ b/srcpkgs/firebird3/template @@ -1,9 +1,10 @@ # Template file for 'firebird3' pkgname=firebird3 -version=3.0.10 -_tag=33601 +version=3.0.6.33328 +revision=2 revision=2 _build=0 +_uver=${version//./_} build_style=gnu-configure build_helper="qemu" configure_args="--prefix=/usr @@ -32,10 +33,10 @@ short_desc="Relational database offering many ANSI SQL standard features (V3)" maintainer="Orphaned " license="custom:IDPL-1.0, Interbase-1.0" homepage="https://www.firebirdsql.org/en/start/" -distfiles="https://github.com/FirebirdSQL/firebird/releases/download/v${version}/Firebird-${version}.${_tag}-${_build}.tar.bz2" -checksum=9138bb60d27eabb15947c8bd0184dd7b795cc19ca6324b76db8ff719641f0340 +distfiles="https://github.com/FirebirdSQL/firebird/releases/download/R${_uver%_*}/Firebird-${version}-${_build}.tar.bz2" +checksum=34c1d2a29bbaf288e682cd1b5f8083f2baf73f351062245ace0bee35a3f7d35f replaces="firebird>=0" -disable_parallel_build="True" +nocross="Fails to build gpre_boot for host but builds for target" CFLAGS="-fno-strict-aliasing" CXXFLAGS="-fno-delete-null-pointer-checks -Wno-deprecated -Wno-deprecated-declarations" @@ -51,7 +52,7 @@ fi pre_configure() { local _arch - if false; then + if [ "$CROSS_BUILD" ]; then # XXX: This is not yet working right and needs more work. # The generated gpre_boot is built with the target C++ and can # not be executed. Trying to run it with qemu--static @@ -67,15 +68,14 @@ pre_configure() { ppc64*) _arch="linux_powerpc64";; ppc*) _arch="linux_powerpc";; x86_64*) _arch="linux_amd64";; - *) msg_error "$XBPS_TARGET_MACHINE has not cross arch set yet";; esac + configure_args+=" --with-cross-build=$_arch" # Remove -msse4 for non-x86_64 arch because it leaks # into the target CXXFLAGS. if [ "$_arch" != "linux_amd64" ]; then vsed -i builds/posix/prefix.linux{,_amd64} -e "s;-msse4;;" fi fi - configure_args+=" --with-cross-build=$_arch" if [ "$XBPS_TARGET_LIBC" = musl ]; then vsed -i -e '/FLAGS=/s/ \-p / /g' \ From 4ae11319717af8b943bd77c55e20bb1a5ef0de4b Mon Sep 17 00:00:00 2001 From: John Date: Thu, 23 Feb 2023 13:22:00 +0100 Subject: [PATCH 141/189] abiword: add patch for musl 1.2.3+ --- srcpkgs/abiword/patches/musl-1.2.3.patch | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 srcpkgs/abiword/patches/musl-1.2.3.patch diff --git a/srcpkgs/abiword/patches/musl-1.2.3.patch b/srcpkgs/abiword/patches/musl-1.2.3.patch new file mode 100644 index 0000000000000..c5e3b56939d93 --- /dev/null +++ b/srcpkgs/abiword/patches/musl-1.2.3.patch @@ -0,0 +1,11 @@ +--- src/af/xap/xp/xap_Dialog.cpp 2021-07-03 17:46:07.000000000 +0200 ++++ - 2023-02-23 13:21:03.557255506 +0100 +@@ -267,7 +267,7 @@ + // This function constructs and returns the window name of a modeless dialog by + // concatenating the active frame with the dialog name + +- *pWindowName = (char) NULL; ++ *pWindowName = (char) 0; + UT_UTF8String wn = UT_UTF8String(pDialogName); + + XAP_Frame* pFrame = getActiveFrame(); From b2a1aad82f625394e7aa22ccd952708501e4a9a3 Mon Sep 17 00:00:00 2001 From: John Date: Thu, 23 Feb 2023 14:08:48 +0100 Subject: [PATCH 142/189] opencollada: add patch for musl 1.2.3+ --- srcpkgs/opencollada/patches/musl-1.2.3.patch | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 srcpkgs/opencollada/patches/musl-1.2.3.patch diff --git a/srcpkgs/opencollada/patches/musl-1.2.3.patch b/srcpkgs/opencollada/patches/musl-1.2.3.patch new file mode 100644 index 0000000000000..00b2b3e2ef98e --- /dev/null +++ b/srcpkgs/opencollada/patches/musl-1.2.3.patch @@ -0,0 +1,11 @@ +--- a/COLLADAStreamWriter/src/COLLADASWLibraryAnimations.cpp 2018-11-26 23:43:10.000000000 +0100 ++++ - 2023-02-23 13:47:42.819812753 +0100 +@@ -62,7 +62,7 @@ + + //--------------------------------------------------------------- + LibraryAnimations::LibraryAnimations ( COLLADASW::StreamWriter * streamWriter ) +- : Library ( streamWriter, CSWC::CSW_ELEMENT_LIBRARY_ANIMATIONS ), mOpenAnimations ( NULL ) ++ : Library ( streamWriter, CSWC::CSW_ELEMENT_LIBRARY_ANIMATIONS ), mOpenAnimations ( std::vector {} ) + {} + + //--------------------------------------------------------------- From cc30c904af64b1f95faabdaf066123461a9ea84e Mon Sep 17 00:00:00 2001 From: John Date: Thu, 23 Feb 2023 14:16:55 +0100 Subject: [PATCH 143/189] choosenim: add riscv64 to template --- srcpkgs/choosenim/template | 2 ++ 1 file changed, 2 insertions(+) diff --git a/srcpkgs/choosenim/template b/srcpkgs/choosenim/template index 064dbbbdf4d52..edc91b97a3616 100644 --- a/srcpkgs/choosenim/template +++ b/srcpkgs/choosenim/template @@ -33,6 +33,8 @@ do_build() { ppc64le*) arch=powerpc64el;; ppc64*) arch=powerpc64;; ppc*) arch=powerpc;; + riscv64*) arch=riscv64;; + *) msg_error "choosenim: $XBPS_TARGET_MACHINE unknown to template";; esac LDFLAGS+=" $($PKG_CONFIG --libs-only-l --static openssl)" LDFLAGS+=" $($PKG_CONFIG --libs-only-l --static libarchive)" From efa3a861ba1deb630a473b1c113e141a7f511dae Mon Sep 17 00:00:00 2001 From: John Date: Thu, 23 Feb 2023 14:25:27 +0100 Subject: [PATCH 144/189] ruplacer: update libc crate for riscv64 compat --- srcpkgs/ruplacer/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/ruplacer/template b/srcpkgs/ruplacer/template index 75c29f6d357e5..c7feb5dbe9769 100644 --- a/srcpkgs/ruplacer/template +++ b/srcpkgs/ruplacer/template @@ -11,6 +11,11 @@ changelog="https://github.com/your-tools/ruplacer/raw/main/CHANGELOG.md" distfiles="https://github.com/dmerejkowsky/ruplacer/archive/refs/tags/v${version}.tar.gz" checksum=aed24fc2bd688733c0176a79c8709adee2251f721a3405972906b8ac82b1ba74 +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} + post_install() { vlicense LICENSE } From fe3a1c4addb1d61e1679e7c1808cc117c3c19e46 Mon Sep 17 00:00:00 2001 From: John Date: Thu, 23 Feb 2023 14:26:18 +0100 Subject: [PATCH 145/189] fastmod: update libc crate for riscv64 compat --- srcpkgs/fastmod/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/fastmod/template b/srcpkgs/fastmod/template index 4ce12d509c8d4..ad16d04e8e6c4 100644 --- a/srcpkgs/fastmod/template +++ b/srcpkgs/fastmod/template @@ -9,3 +9,8 @@ license="Apache-2.0" homepage="https://github.com/facebookincubator/fastmod" distfiles="https://github.com/facebookincubator/fastmod/archive/v${version}.tar.gz" checksum=0e0c2d50489c90cb8c8904772be2e9d31353fbed814d9088ee6013c27c2d111b + +pre_build() { + # Newer libc needed for riscv64 + cargo update --package libc --precise 0.2.139 +} From 38578b4a64aa871b63f11e5658ef0f326ebfda60 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 24 Feb 2023 13:46:31 +0100 Subject: [PATCH 146/189] obs: add luajit buildoption --- srcpkgs/obs/template | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/srcpkgs/obs/template b/srcpkgs/obs/template index 7b69c630d30d4..7ac7211fdbadb 100644 --- a/srcpkgs/obs/template +++ b/srcpkgs/obs/template @@ -2,12 +2,13 @@ pkgname=obs version=29.1.2 revision=1 -archs="i686* x86_64* ppc64le* aarch64*" +archs="i686* x86_64* ppc64le* aarch64* riscv64*" build_style=cmake configure_args="-DOBS_VERSION_OVERRIDE=${version} -DENABLE_JACK=ON - -DENABLE_VST=OFF -DENABLE_AJA=OFF -DCALM_DEPRECATION=ON" + -DENABLE_VST=OFF -DENABLE_AJA=OFF -DCALM_DEPRECATION=ON + -DENABLE_SCRIPTING_LUA=$(vopt_if luajit 'ON' 'OFF')" hostmakedepends="pkg-config swig python3-devel qt6-base" -makedepends="LuaJIT-devel fdk-aac-devel ffmpeg-devel glu-devel +makedepends="$(vopt_if luajit LuaJIT-devel) fdk-aac-devel ffmpeg-devel glu-devel jack-devel libXcomposite-devel libcurl-devel libva-devel pulseaudio-devel python3-devel speexdsp-devel v4l-utils-devel vlc-devel qt6-svg-devel x264-devel mbedtls-devel jansson-devel @@ -22,6 +23,12 @@ changelog="https://github.com/obsproject/obs-studio/releases" distfiles="https://github.com/obsproject/obs-studio/archive/${version}.tar.gz" checksum=215f1fa5772c5dd9f3d6e35b0cb573912b00320149666a77864f9d305525504b +build_options="luajit" +case $XBPS_TARGET_MACHINE in + riscv64*);; + *) build_options_default="luajit";; +esac + pre_configure() { # it's not enough to use -DENABLE_BROWSER ... touch plugins/obs-browser/CMakeLists.txt From 6ee34338e9ba3ab1515d7185c21f453209e6358d Mon Sep 17 00:00:00 2001 From: John Date: Sun, 12 Mar 2023 22:00:00 +0100 Subject: [PATCH 147/189] linux6.2: update to 6.2.2. --- ...orm-Add-snps-dwmac-5.20-IP-compatibl.patch | 32 ++ ...snps-dwmac-Add-an-optional-resets-si.patch | 48 ++ ...ive-jh7110-Add-ethernet-device-nodes.patch | 125 +++++ ...d-glue-layer-for-StarFive-JH7110-SoC.patch | 199 ++++++++ ...starfive-jh7110-dwmac-Add-starfive-s.patch | 47 ++ ...five_dmac-Add-phy-interface-settings.patch | 97 ++++ ...ve-jh7110-Add-syscon-to-support-phy-.patch | 37 ++ ...ve-visionfive-2-v1.3b-Add-gmac-phy-s.patch | 55 +++ ...ve-visionfive-2-v1.2a-Add-gmac-phy-s.patch | 41 ++ ...ve-visionfive-2-Enable-gmac-device-t.patch | 45 ++ ...dings-net-Add-support-StarFive-dwmac.patch | 31 ++ ...-glue-layer-for-StarFive-JH7110-SoCs.patch | 192 +++++++ ...et-Add-Motorcomm-yt8xxx-ethernet-phy.patch | 167 +++++++ ...macro-for-Motorcomm-yt8521-yt8531-gi.patch | 111 +++++ ...support-for-Motorcomm-yt8521-gigabit.patch | 347 +++++++++++++ ...support-for-Motorcomm-yt8531s-gigabi.patch | 104 ++++ ...er-for-Motorcomm-yt8531-gigabit-ethe.patch | 308 ++++++++++++ ...dings-hwmon-Add-starfive-jh71x0-temp.patch | 95 ++++ ...d-StarFive-JH71x0-temperature-sensor.patch | 467 ++++++++++++++++++ 19 files changed, 2548 insertions(+) create mode 100644 srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch create mode 100644 srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch create mode 100644 srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch create mode 100644 srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch create mode 100644 srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch create mode 100644 srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch create mode 100644 srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch create mode 100644 srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch create mode 100644 srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch create mode 100644 srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch create mode 100644 srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch create mode 100644 srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch create mode 100644 srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch create mode 100644 srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch create mode 100644 srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch create mode 100644 srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch create mode 100644 srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch create mode 100644 srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch diff --git a/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch b/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch new file mode 100644 index 0000000000000..984f0fe5a5866 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch @@ -0,0 +1,32 @@ +From 238f315bbcebe9d4168b5d75cff4a9af7b38bc7f Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Fri, 3 Mar 2023 16:59:18 +0800 +Subject: [PATCH 51/70] net: stmmac: platform: Add snps,dwmac-5.20 IP + compatible string + +Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid +to define some platform data in the glue layer. + +Signed-off-by: Emil Renner Berthing +Signed-off-by: Samin Guo +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +index 0046a4ee6e64..807eca7edf53 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -519,7 +519,8 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) + if (of_device_is_compatible(np, "snps,dwmac-4.00") || + of_device_is_compatible(np, "snps,dwmac-4.10a") || + of_device_is_compatible(np, "snps,dwmac-4.20a") || +- of_device_is_compatible(np, "snps,dwmac-5.10a")) { ++ of_device_is_compatible(np, "snps,dwmac-5.10a") || ++ of_device_is_compatible(np, "snps,dwmac-5.20")) { + plat->has_gmac4 = 1; + plat->has_gmac = 0; + plat->pmt = 1; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch b/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch new file mode 100644 index 0000000000000..8a432c21972bc --- /dev/null +++ b/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch @@ -0,0 +1,48 @@ +From 4f6a9a8acb9b9da0f3bee80c46800d7593db851d Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:19 +0800 +Subject: [PATCH 52/70] dt-bindings: net: snps,dwmac: Add an optional resets + single 'ahb' + +According to: +stmmac_platform.c: stmmac_probe_config_dt +stmmac_main.c: stmmac_dvr_probe + +dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb) +reset signals, and the maxItems of resets/reset-names is going to be 2. + +Signed-off-by: Samin Guo +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 14 ++++++++++---- + 1 file changed, 10 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index b4135d5297b4..89099a888f0b 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -133,12 +133,18 @@ properties: + - ptp_ref + + resets: +- maxItems: 1 +- description: +- MAC Reset signal. ++ minItems: 1 ++ items: ++ - description: GMAC stmmaceth reset ++ - description: AHB reset + + reset-names: +- const: stmmaceth ++ minItems: 1 ++ maxItems: 2 ++ contains: ++ enum: ++ - stmmaceth ++ - ahb + + power-domains: + maxItems: 1 +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch b/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch new file mode 100644 index 0000000000000..0e9b25758ad11 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch @@ -0,0 +1,125 @@ +From 46355830a010e30b11d02da939d1b7214dd0e4e0 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:21 +0800 +Subject: [PATCH 54/70] riscv: dts: starfive: jh7110: Add ethernet device nodes + +Add JH7110 ethernet device node to support gmac driver for the JH7110 +RISC-V SoC. + +Signed-off-by: Yanhong Wang +Signed-off-by: Samin Guo +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 91 ++++++++++++++++++++++++ + 1 file changed, 91 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 3724c2c9035a..b0e87198808a 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -234,6 +234,13 @@ i2srx_lrck_ext: i2srx-lrck-ext-clock { + #clock-cells = <0>; + }; + ++ stmmac_axi_setup: stmmac-axi-config { ++ snps,lpi_en; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <4>; ++ snps,blen = <256 128 64 32 0 0 0>; ++ }; ++ + tdm_ext: tdm-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "tdm_ext"; +@@ -658,5 +665,89 @@ mmc1: mmc@16020000 { + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; ++ ++ gmac0: ethernet@16030000 { ++ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; ++ reg = <0x0 0x16030000 0x0 0x10000>; ++ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, ++ <&aoncrg JH7110_AONCLK_GMAC0_AHB>, ++ <&syscrg JH7110_SYSCLK_GMAC0_PTP>, ++ <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, ++ <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; ++ clock-names = "stmmaceth", "pclk", "ptp_ref", ++ "tx", "gtx"; ++ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, ++ <&aoncrg JH7110_AONRST_GMAC0_AHB>; ++ reset-names = "stmmaceth", "ahb"; ++ interrupts = <7>, <6>, <5>; ++ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; ++ phy-mode = "rgmii-id"; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <8>; ++ rx-fifo-depth = <2048>; ++ tx-fifo-depth = <2048>; ++ snps,fixed-burst; ++ snps,no-pbl-x8; ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,tso; ++ snps,en-tx-lpi-clockgating; ++ snps,txpbl = <16>; ++ snps,rxpbl = <16>; ++ status = "disabled"; ++ phy-handle = <&phy0>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++ }; ++ ++ gmac1: ethernet@16040000 { ++ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; ++ reg = <0x0 0x16040000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, ++ <&syscrg JH7110_SYSCLK_GMAC1_AHB>, ++ <&syscrg JH7110_SYSCLK_GMAC1_PTP>, ++ <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, ++ <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; ++ clock-names = "stmmaceth", "pclk", "ptp_ref", ++ "tx", "gtx"; ++ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, ++ <&syscrg JH7110_SYSRST_GMAC1_AHB>; ++ reset-names = "stmmaceth", "ahb"; ++ interrupts = <78>, <77>, <76>; ++ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; ++ phy-mode = "rgmii-id"; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <8>; ++ rx-fifo-depth = <2048>; ++ tx-fifo-depth = <2048>; ++ snps,fixed-burst; ++ snps,no-pbl-x8; ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,tso; ++ snps,en-tx-lpi-clockgating; ++ snps,txpbl = <16>; ++ snps,rxpbl = <16>; ++ status = "disabled"; ++ phy-handle = <&phy1>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <0>; ++ }; ++ }; ++ }; + }; + }; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch b/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch new file mode 100644 index 0000000000000..97f1527b27e1c --- /dev/null +++ b/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch @@ -0,0 +1,199 @@ +From bd106dc923482e9c6b8fc96e04ef03ab3f37f47d Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:22 +0800 +Subject: [PATCH 55/70] net: stmmac: Add glue layer for StarFive JH7110 SoC + +This adds StarFive dwmac driver support on the StarFive JH7110 SoC. + +Co-developed-by: Emil Renner Berthing +Signed-off-by: Emil Renner Berthing +Signed-off-by: Samin Guo +--- + MAINTAINERS | 1 + + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 125 ++++++++++++++++++ + 4 files changed, 139 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 31560d13afed..8ff112156e1f 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19915,6 +19915,7 @@ STARFIVE DWMAC GLUE LAYER + M: Emil Renner Berthing + M: Samin Guo + S: Maintained ++F: Documentation/devicetree/bindings/net/dwmac-starfive.c + F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml + + STARFIVE JH71X0 CLOCK DRIVERS +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index f77511fe4e87..47fbccef9d04 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -165,6 +165,18 @@ config DWMAC_SOCFPGA + for the stmmac device driver. This driver is used for + arria5 and cyclone5 FPGA SoCs. + ++config DWMAC_STARFIVE ++ tristate "StarFive dwmac support" ++ depends on OF && (ARCH_STARFIVE || COMPILE_TEST) ++ depends on STMMAC_ETH ++ default ARCH_STARFIVE ++ help ++ Support for ethernet controllers on StarFive RISC-V SoCs ++ ++ This selects the StarFive platform specific glue layer support for ++ the stmmac device driver. This driver is used for StarFive JH7110 ++ ethernet controller. ++ + config DWMAC_STI + tristate "STi GMAC support" + default ARCH_STI +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 057e4bab5c08..8738fdbb4b2d 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o + obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o + obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o ++obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o + obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o + obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +new file mode 100644 +index 000000000000..566378306f67 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +@@ -0,0 +1,125 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive DWMAC platform driver ++ * ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022 Emil Renner Berthing ++ * ++ */ ++ ++#include ++ ++#include "stmmac_platform.h" ++ ++struct starfive_dwmac { ++ struct device *dev; ++ struct clk *clk_tx; ++ struct clk *clk_gtx; ++ bool tx_use_rgmii_rxin_clk; ++}; ++ ++static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct starfive_dwmac *dwmac = priv; ++ unsigned long rate; ++ int err; ++ ++ /* Generally, the rgmii_tx clock is provided by the internal clock, ++ * which needs to match the corresponding clock frequency according ++ * to different speeds. If the rgmii_tx clock is provided by the ++ * external rgmii_rxin, there is no need to configure the clock ++ * internally, because rgmii_rxin will be adaptively adjusted. ++ */ ++ if (dwmac->tx_use_rgmii_rxin_clk) ++ return; ++ ++ switch (speed) { ++ case SPEED_1000: ++ rate = 125000000; ++ break; ++ case SPEED_100: ++ rate = 25000000; ++ break; ++ case SPEED_10: ++ rate = 2500000; ++ break; ++ default: ++ dev_err(dwmac->dev, "invalid speed %u\n", speed); ++ break; ++ } ++ ++ err = clk_set_rate(dwmac->clk_tx, rate); ++ if (err) ++ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); ++} ++ ++static int starfive_dwmac_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct starfive_dwmac *dwmac; ++ int err; ++ ++ err = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (err) ++ return err; ++ ++ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ if (IS_ERR(plat_dat)) { ++ dev_err(&pdev->dev, "dt configuration failed\n"); ++ return PTR_ERR(plat_dat); ++ } ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) ++ return -ENOMEM; ++ ++ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); ++ if (IS_ERR(dwmac->clk_tx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx), ++ "error getting tx clock\n"); ++ ++ dwmac->clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx"); ++ if (IS_ERR(dwmac->clk_gtx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtx), ++ "error getting gtx clock\n"); ++ ++ if (device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk")) ++ dwmac->tx_use_rgmii_rxin_clk = true; ++ ++ dwmac->dev = &pdev->dev; ++ plat_dat->fix_mac_speed = starfive_eth_fix_mac_speed; ++ plat_dat->init = NULL; ++ plat_dat->bsp_priv = dwmac; ++ plat_dat->dma_cfg->dche = true; ++ ++ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (err) { ++ stmmac_remove_config_dt(pdev, plat_dat); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_dwmac_match[] = { ++ { .compatible = "starfive,jh7110-dwmac" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_dwmac_match); ++ ++static struct platform_driver starfive_dwmac_driver = { ++ .probe = starfive_dwmac_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "starfive-dwmac", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = starfive_dwmac_match, ++ }, ++}; ++module_platform_driver(starfive_dwmac_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("StarFive DWMAC platform driver"); ++MODULE_AUTHOR("Emil Renner Berthing "); ++MODULE_AUTHOR("Samin Guo "); +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch b/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch new file mode 100644 index 0000000000000..2d76a47560ad0 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch @@ -0,0 +1,47 @@ +From 8d53004571daa30044aa83b0fa806762ea628b1b Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:23 +0800 +Subject: [PATCH 56/70] dt-bindings: net: starfive,jh7110-dwmac: Add + starfive,syscon + +A phandle to syscon with two arguments that configure phy mode. + +Signed-off-by: Samin Guo +--- + .../bindings/net/starfive,jh7110-dwmac.yaml | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +index eb0767da834a..cd313ca8b8cf 100644 +--- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +@@ -54,6 +54,18 @@ properties: + - const: stmmaceth + - const: ahb + ++ starfive,syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to syscon that configures phy mode ++ - description: Offset of phy mode selection ++ - description: Mask of phy mode selection ++ description: ++ A phandle to syscon with two arguments that configure phy mode. ++ The argument one is the offset of phy mode selection, the ++ argument two is the mask of phy mode selection. ++ + allOf: + - $ref: snps,dwmac.yaml# + +@@ -92,6 +104,7 @@ examples: + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; ++ starfive,syscon = <&aon_syscon 0xc 0x1c0000>; + phy-handle = <&phy0>; + + mdio { +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch b/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch new file mode 100644 index 0000000000000..3d60456065665 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch @@ -0,0 +1,97 @@ +From 7fe07e3a0d81babf67672ef428756c3098f12a22 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:24 +0800 +Subject: [PATCH 57/70] net: stmmac: starfive_dmac: Add phy interface settings + +dwmac supports multiple modess. When working under rmii and rgmii, +you need to set different phy interfaces. + +According to the dwmac document, when working in rmii, it needs to be +set to 0x4, and rgmii needs to be set to 0x1. + +The phy interface needs to be set in syscon, the format is as follows: +starfive,syscon: <&syscon, offset, mask> + +Signed-off-by: Samin Guo +--- + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +index 566378306f67..40fdd7036127 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +@@ -7,10 +7,15 @@ + * + */ + ++#include + #include ++#include + + #include "stmmac_platform.h" + ++#define MACPHYC_PHY_INFT_RMII 0x4 ++#define MACPHYC_PHY_INFT_RGMII 0x1 ++ + struct starfive_dwmac { + struct device *dev; + struct clk *clk_tx; +@@ -53,6 +58,46 @@ static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed) + dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); + } + ++static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat) ++{ ++ struct starfive_dwmac *dwmac = plat_dat->bsp_priv; ++ struct of_phandle_args args; ++ struct regmap *regmap; ++ unsigned int reg, mask, mode; ++ int err; ++ ++ switch (plat_dat->interface) { ++ case PHY_INTERFACE_MODE_RMII: ++ mode = MACPHYC_PHY_INFT_RMII; ++ break; ++ ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ mode = MACPHYC_PHY_INFT_RGMII; ++ break; ++ ++ default: ++ dev_err(dwmac->dev, "Unsupported interface %d\n", ++ plat_dat->interface); ++ } ++ ++ err = of_parse_phandle_with_fixed_args(dwmac->dev->of_node, ++ "starfive,syscon", 2, 0, &args); ++ if (err) { ++ dev_dbg(dwmac->dev, "syscon reg not found\n"); ++ return -EINVAL; ++ } ++ ++ reg = args.args[0]; ++ mask = args.args[1]; ++ regmap = syscon_node_to_regmap(args.np); ++ of_node_put(args.np); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ return regmap_update_bits(regmap, reg, mask, mode << __ffs(mask)); ++} ++ + static int starfive_dwmac_probe(struct platform_device *pdev) + { + struct plat_stmmacenet_data *plat_dat; +@@ -93,6 +138,7 @@ static int starfive_dwmac_probe(struct platform_device *pdev) + plat_dat->bsp_priv = dwmac; + plat_dat->dma_cfg->dche = true; + ++ starfive_dwmac_set_mode(plat_dat); + err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (err) { + stmmac_remove_config_dt(pdev, plat_dat); +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch b/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch new file mode 100644 index 0000000000000..54ff01a2b5c83 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch @@ -0,0 +1,37 @@ +From 7a0bac9436e69b30f5b3aaadf8d2ad87d8d04559 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:25 +0800 +Subject: [PATCH 58/70] riscv: dts: starfive: jh7110: Add syscon to support phy + interface settings + +The phy interface needs to be set in syscon, the format is as follows: +starfive,syscon: <&syscon, offset, mask> + +Signed-off-by: Samin Guo +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index b0e87198808a..8b73d01c226c 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -694,6 +694,7 @@ gmac0: ethernet@16030000 { + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; ++ starfive,syscon = <&aon_syscon 0xc 0x1c0000>; + status = "disabled"; + phy-handle = <&phy0>; + +@@ -736,6 +737,7 @@ gmac1: ethernet@16040000 { + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; ++ starfive,syscon = <&sys_syscon 0x90 0x1c>; + status = "disabled"; + phy-handle = <&phy1>; + +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch b/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch new file mode 100644 index 0000000000000..bb87c6f17bdf6 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch @@ -0,0 +1,55 @@ +From 11f9513b0475fc7c841a4f50ea15207a90e45940 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:26 +0800 +Subject: [PATCH 59/70] riscv: dts: starfive: visionfive-2-v1.3b: Add + gmac+phy's delay configuration + +v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and +inverse configurations. + +The tx_clk of v1.3B uses an external clock and needs to be +switched to an external clock source. + +Signed-off-by: Samin Guo +--- + .../jh7110-starfive-visionfive-2-v1.3b.dts | 27 +++++++++++++++++++ + 1 file changed, 27 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +index 9230cc3d8946..32fae0de9a44 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +@@ -11,3 +11,30 @@ / { + model = "StarFive VisionFive 2 v1.3B"; + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; + }; ++ ++&gmac0 { ++ starfive,tx-use-rgmii-clk; ++ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; ++ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; ++}; ++ ++&gmac1 { ++ starfive,tx-use-rgmii-clk; ++ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; ++ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; ++}; ++ ++&phy0 { ++ motorcomm,tx-clk-adj-enabled; ++ motorcomm,tx-clk-100-inverted; ++ motorcomm,tx-clk-1000-inverted; ++ rx-internal-delay-ps = <1900>; ++ tx-internal-delay-ps = <1500>; ++}; ++ ++&phy1 { ++ motorcomm,tx-clk-adj-enabled; ++ motorcomm,tx-clk-100-inverted; ++ rx-internal-delay-ps = <0>; ++ tx-internal-delay-ps = <0>; ++}; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch b/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch new file mode 100644 index 0000000000000..d24341f8a476c --- /dev/null +++ b/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch @@ -0,0 +1,41 @@ +From de94625d0b77c717ce794a80c41541bb95b0d21b Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Fri, 3 Mar 2023 16:59:27 +0800 +Subject: [PATCH 60/70] riscv: dts: starfive: visionfive-2-v1.2a: Add + gmac+phy's delay configuration + +v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay +configurations. + +v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to +switch rx and rx to external clock sources. + +Signed-off-by: Samin Guo +--- + .../starfive/jh7110-starfive-visionfive-2-v1.2a.dts | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +index 4af3300f3cf3..205a13d8c8b1 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +@@ -11,3 +11,16 @@ / { + model = "StarFive VisionFive 2 v1.2A"; + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; + }; ++ ++&gmac1 { ++ phy-mode = "rmii"; ++ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, ++ <&syscrg JH7110_SYSCLK_GMAC1_RX>; ++ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, ++ <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; ++}; ++ ++&phy0 { ++ rx-internal-delay-ps = <1900>; ++ tx-internal-delay-ps = <1350>; ++}; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch b/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch new file mode 100644 index 0000000000000..9591d052c9247 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch @@ -0,0 +1,45 @@ +From 868c93e6035b1a511fe1d105d88b86d66bd5a2b2 Mon Sep 17 00:00:00 2001 +From: Yanhong Wang +Date: Fri, 3 Mar 2023 16:59:28 +0800 +Subject: [PATCH 61/70] riscv: dts: starfive: visionfive 2: Enable gmac device + tree node + +Update gmac device tree node status to okay. + +Signed-off-by: Yanhong Wang +Signed-off-by: Samin Guo +--- + .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 295af73b0d08..3c3dc2a94ff6 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -12,6 +12,8 @@ + / { + aliases { + serial0 = &uart0; ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c5 = &i2c5; +@@ -123,6 +125,14 @@ &uart0 { + status = "okay"; + }; + ++&gmac0 { ++ status = "okay"; ++}; ++ ++&gmac1 { ++ status = "okay"; ++}; ++ + &i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch b/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch new file mode 100644 index 0000000000000..00c0877d5fe03 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch @@ -0,0 +1,31 @@ +From 9345758b8ec31007bd2ce6f116c0154b3f0c1c5c Mon Sep 17 00:00:00 2001 +From: Yanhong Wang +Date: Wed, 18 Jan 2023 14:16:58 +0800 +Subject: [PATCH 62/70] dt-bindings: net: Add support StarFive dwmac + +Add documentation to describe StarFive dwmac driver(GMAC). + +Signed-off-by: Yanhong Wang +--- + MAINTAINERS | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 8ff112156e1f..b27451ff95eb 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19977,6 +19977,11 @@ F: Documentation/devicetree/bindings/power/starfive* + F: drivers/soc/starfive/jh71xx_pmu.c + F: include/dt-bindings/power/starfive,jh7110-pmu.h + ++STARFIVE DWMAC GLUE LAYER ++M: Yanhong Wang ++S: Maintained ++F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml ++ + STATIC BRANCH/CALL + M: Peter Zijlstra + M: Josh Poimboeuf +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch b/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch new file mode 100644 index 0000000000000..600b9c816525a --- /dev/null +++ b/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch @@ -0,0 +1,192 @@ +From 1b5b040a5eaec091fd46b64459d4828971b17b66 Mon Sep 17 00:00:00 2001 +From: Yanhong Wang +Date: Wed, 18 Jan 2023 14:16:59 +0800 +Subject: [PATCH 63/70] net: stmmac: Add glue layer for StarFive JH7110 SoCs + +This adds StarFive dwmac driver support on the StarFive JH7110 SoCs. + +Signed-off-by: Yanhong Wang +Co-developed-by: Emil Renner Berthing +Signed-off-by: Emil Renner Berthing +--- + MAINTAINERS | 1 + + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../stmicro/stmmac/dwmac-starfive-plat.c | 118 ++++++++++++++++++ + 4 files changed, 132 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index b27451ff95eb..bed2c33be517 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19980,6 +19980,7 @@ F: include/dt-bindings/power/starfive,jh7110-pmu.h + STARFIVE DWMAC GLUE LAYER + M: Yanhong Wang + S: Maintained ++F: Documentation/devicetree/bindings/net/dwmac-starfive-plat.c + F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml + + STATIC BRANCH/CALL +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index 47fbccef9d04..99f6716d6dc9 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -256,6 +256,18 @@ config DWMAC_TEGRA + layer on top of the stmmac driver required for these NVIDIA Tegra SoC + devices. + ++config DWMAC_STARFIVE_PLAT ++ tristate "StarFive dwmac support" ++ depends on OF && COMMON_CLK ++ depends on STMMAC_ETH ++ default SOC_STARFIVE ++ help ++ Support for ethernet controllers on StarFive RISC-V SoCs ++ ++ This selects the StarFive platform specific glue layer support for ++ the stmmac device driver. This driver is used for StarFive JH7110 ++ ethernet controller. ++ + config DWMAC_VISCONTI + tristate "Toshiba Visconti DWMAC support" + default ARCH_VISCONTI +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 8738fdbb4b2d..576d9c5f7954 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o + obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o + obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o + obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o ++obj-$(CONFIG_DWMAC_STARFIVE_PLAT) += dwmac-starfive-plat.o + obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o + obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o + stmmac-platform-objs:= stmmac_platform.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c +new file mode 100644 +index 000000000000..e441d920933a +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c +@@ -0,0 +1,118 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive DWMAC platform driver ++ * ++ * Copyright(C) 2022 StarFive Technology Co., Ltd. ++ * ++ */ ++ ++#include ++ ++#include "stmmac_platform.h" ++ ++struct starfive_dwmac { ++ struct device *dev; ++ struct clk *clk_tx; ++ struct clk *clk_gtx; ++ struct clk *clk_gtxc; ++}; ++ ++static void starfive_eth_plat_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct starfive_dwmac *dwmac = priv; ++ unsigned long rate; ++ int err; ++ ++ rate = clk_get_rate(dwmac->clk_gtx); ++ ++ switch (speed) { ++ case SPEED_1000: ++ rate = 125000000; ++ break; ++ case SPEED_100: ++ rate = 25000000; ++ break; ++ case SPEED_10: ++ rate = 2500000; ++ break; ++ default: ++ dev_err(dwmac->dev, "invalid speed %u\n", speed); ++ break; ++ } ++ ++ err = clk_set_rate(dwmac->clk_gtx, rate); ++ if (err) ++ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); ++} ++ ++static int starfive_eth_plat_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct starfive_dwmac *dwmac; ++ int err; ++ ++ err = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (err) ++ return err; ++ ++ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ if (IS_ERR(plat_dat)) { ++ dev_err(&pdev->dev, "dt configuration failed\n"); ++ return PTR_ERR(plat_dat); ++ } ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) ++ return -ENOMEM; ++ ++ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); ++ if (IS_ERR(dwmac->clk_tx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx), ++ "error getting tx clock\n"); ++ ++ dwmac->clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx"); ++ if (IS_ERR(dwmac->clk_gtx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtx), ++ "error getting gtx clock\n"); ++ ++ dwmac->clk_gtxc = devm_clk_get_enabled(&pdev->dev, "gtxc"); ++ if (IS_ERR(dwmac->clk_gtxc)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtxc), ++ "error getting gtxc clock\n"); ++ ++ dwmac->dev = &pdev->dev; ++ plat_dat->fix_mac_speed = starfive_eth_plat_fix_mac_speed; ++ plat_dat->init = NULL; ++ plat_dat->bsp_priv = dwmac; ++ plat_dat->dma_cfg->dche = true; ++ ++ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (err) { ++ stmmac_remove_config_dt(pdev, plat_dat); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_eth_plat_match[] = { ++ { .compatible = "starfive,jh7110-dwmac" }, ++ { } ++}; ++ ++static struct platform_driver starfive_eth_plat_driver = { ++ .probe = starfive_eth_plat_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "starfive-eth-plat", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = starfive_eth_plat_match, ++ }, ++}; ++ ++module_platform_driver(starfive_eth_plat_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("StarFive DWMAC platform driver"); ++MODULE_AUTHOR("Yanhong Wang "); +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch b/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch new file mode 100644 index 0000000000000..781747a9c5284 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch @@ -0,0 +1,167 @@ +From 3365b5995c6b24ce6fe25cc705b864936a19b3bc Mon Sep 17 00:00:00 2001 +From: Frank Sae +Date: Thu, 2 Feb 2023 11:00:33 +0800 +Subject: [PATCH 64/70] dt-bindings: net: Add Motorcomm yt8xxx ethernet phy + +Add a YAML binding document for the Motorcomm yt8xxx Ethernet phy. + +Signed-off-by: Frank Sae +Reviewed-by: Rob Herring +--- + .../bindings/net/motorcomm,yt8xxx.yaml | 117 ++++++++++++++++++ + .../devicetree/bindings/vendor-prefixes.yaml | 2 + + MAINTAINERS | 1 + + 3 files changed, 120 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml + +diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +new file mode 100644 +index 000000000000..157e3bbcaf6f +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +@@ -0,0 +1,117 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: MotorComm yt8xxx Ethernet PHY ++ ++maintainers: ++ - Frank Sae ++ ++allOf: ++ - $ref: ethernet-phy.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - ethernet-phy-id4f51.e91a ++ - ethernet-phy-id4f51.e91b ++ ++ rx-internal-delay-ps: ++ description: | ++ RGMII RX Clock Delay used only when PHY operates in RGMII mode with ++ internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. ++ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, ++ 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800, ++ 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ] ++ default: 1950 ++ ++ tx-internal-delay-ps: ++ description: | ++ RGMII TX Clock Delay used only when PHY operates in RGMII mode with ++ internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. ++ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800, ++ 1950, 2100, 2250 ] ++ default: 1950 ++ ++ motorcomm,clk-out-frequency-hz: ++ description: clock output on clock output pin. ++ enum: [0, 25000000, 125000000] ++ default: 0 ++ ++ motorcomm,keep-pll-enabled: ++ description: | ++ If set, keep the PLL enabled even if there is no link. Useful if you ++ want to use the clock output without an ethernet link. ++ type: boolean ++ ++ motorcomm,auto-sleep-disabled: ++ description: | ++ If set, PHY will not enter sleep mode and close AFE after unplug cable ++ for a timer. ++ type: boolean ++ ++ motorcomm,tx-clk-adj-enabled: ++ description: | ++ This configuration is mainly to adapt to VF2 with JH7110 SoC. ++ Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk. ++ type: boolean ++ ++ motorcomm,tx-clk-10-inverted: ++ description: | ++ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII ++ Transmit PHY Clock delay train configuration when speed is 10Mbps. ++ type: boolean ++ ++ motorcomm,tx-clk-100-inverted: ++ description: | ++ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII ++ Transmit PHY Clock delay train configuration when speed is 100Mbps. ++ type: boolean ++ ++ motorcomm,tx-clk-1000-inverted: ++ description: | ++ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII ++ Transmit PHY Clock delay train configuration when speed is 1000Mbps. ++ type: boolean ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ phy-mode = "rgmii-id"; ++ ethernet-phy@4 { ++ /* Only needed to make DT lint tools work. Do not copy/paste ++ * into real DTS files. ++ */ ++ compatible = "ethernet-phy-id4f51.e91a"; ++ ++ reg = <4>; ++ rx-internal-delay-ps = <2100>; ++ tx-internal-delay-ps = <150>; ++ motorcomm,clk-out-frequency-hz = <0>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ }; ++ }; ++ - | ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ phy-mode = "rgmii"; ++ ethernet-phy@5 { ++ /* Only needed to make DT lint tools work. Do not copy/paste ++ * into real DTS files. ++ */ ++ compatible = "ethernet-phy-id4f51.e91a"; ++ ++ reg = <5>; ++ motorcomm,clk-out-frequency-hz = <125000000>; ++ motorcomm,keep-pll-enabled; ++ motorcomm,auto-sleep-disabled; ++ }; ++ }; +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 70ffb3780621..8d19157e85b7 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -845,6 +845,8 @@ patternProperties: + description: Moortec Semiconductor Ltd. + "^mosaixtech,.*": + description: Mosaix Technologies, Inc. ++ "^motorcomm,.*": ++ description: MotorComm, Inc. + "^motorola,.*": + description: Motorola, Inc. + "^moxa,.*": +diff --git a/MAINTAINERS b/MAINTAINERS +index bed2c33be517..7c73cdbe1259 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -14169,6 +14169,7 @@ M: Peter Geis + M: Frank + L: netdev@vger.kernel.org + S: Maintained ++F: Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml + F: drivers/net/phy/motorcomm.c + + MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch b/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch new file mode 100644 index 0000000000000..afd296f9f2f93 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch @@ -0,0 +1,111 @@ +From 5e416205a846fef3174ebe0509f6a4926e947580 Mon Sep 17 00:00:00 2001 +From: Frank Sae +Date: Thu, 2 Feb 2023 11:00:34 +0800 +Subject: [PATCH 65/70] net: phy: Add BIT macro for Motorcomm yt8521/yt8531 + gigabit ethernet phy + +Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy. + This is a preparatory patch. Add BIT macro for 0xA012 reg, and + supplement for 0xA001 and 0xA003 reg. These will be used to support dts. + +Signed-off-by: Frank Sae +Reviewed-by: Andrew Lunn +--- + drivers/net/phy/motorcomm.c | 55 ++++++++++++++++++++++++++++++++++--- + 1 file changed, 51 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index 685190db72de..d8523e33424d 100644 +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -161,6 +161,11 @@ + + #define YT8521_CHIP_CONFIG_REG 0xA001 + #define YT8521_CCR_SW_RST BIT(15) ++/* 1b0 disable 1.9ns rxc clock delay *default* ++ * 1b1 enable 1.9ns rxc clock delay ++ */ ++#define YT8521_CCR_RXC_DLY_EN BIT(8) ++#define YT8521_CCR_RXC_DLY_1_900_NS 1900 + + #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) + #define YT8521_CCR_MODE_UTP_TO_RGMII 0 +@@ -178,22 +183,41 @@ + #define YT8521_MODE_POLL 0x3 + + #define YT8521_RGMII_CONFIG1_REG 0xA003 +- ++/* 1b0 use original tx_clk_rgmii *default* ++ * 1b1 use inverted tx_clk_rgmii. ++ */ ++#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) + /* TX Gig-E Delay is bits 3:0, default 0x1 + * TX Fast-E Delay is bits 7:4, default 0xf + * RX Delay is bits 13:10, default 0x0 + * Delay = 150ps * N + * On = 2250ps, off = 0ps + */ +-#define YT8521_RC1R_RX_DELAY_MASK (0xF << 10) ++#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) + #define YT8521_RC1R_RX_DELAY_EN (0xF << 10) + #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) +-#define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4) ++#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) + #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) + #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) +-#define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0) ++#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) + #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) + #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) ++#define YT8521_RC1R_RGMII_0_000_NS 0 ++#define YT8521_RC1R_RGMII_0_150_NS 1 ++#define YT8521_RC1R_RGMII_0_300_NS 2 ++#define YT8521_RC1R_RGMII_0_450_NS 3 ++#define YT8521_RC1R_RGMII_0_600_NS 4 ++#define YT8521_RC1R_RGMII_0_750_NS 5 ++#define YT8521_RC1R_RGMII_0_900_NS 6 ++#define YT8521_RC1R_RGMII_1_050_NS 7 ++#define YT8521_RC1R_RGMII_1_200_NS 8 ++#define YT8521_RC1R_RGMII_1_350_NS 9 ++#define YT8521_RC1R_RGMII_1_500_NS 10 ++#define YT8521_RC1R_RGMII_1_650_NS 11 ++#define YT8521_RC1R_RGMII_1_800_NS 12 ++#define YT8521_RC1R_RGMII_1_950_NS 13 ++#define YT8521_RC1R_RGMII_2_100_NS 14 ++#define YT8521_RC1R_RGMII_2_250_NS 15 + + #define YTPHY_MISC_CONFIG_REG 0xA006 + #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) +@@ -222,6 +246,29 @@ + */ + #define YTPHY_WCR_TYPE_PULSE BIT(0) + ++#define YTPHY_SYNCE_CFG_REG 0xA012 ++#define YT8521_SCR_SYNCE_ENABLE BIT(5) ++/* 1b0 output 25m clock ++ * 1b1 output 125m clock *default* ++ */ ++#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) ++#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) ++#define YT8521_SCR_CLK_SRC_PLL_125M 0 ++#define YT8521_SCR_CLK_SRC_UTP_RX 1 ++#define YT8521_SCR_CLK_SRC_SDS_RX 2 ++#define YT8521_SCR_CLK_SRC_REF_25M 3 ++#define YT8531_SCR_SYNCE_ENABLE BIT(6) ++/* 1b0 output 25m clock *default* ++ * 1b1 output 125m clock ++ */ ++#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) ++#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) ++#define YT8531_SCR_CLK_SRC_PLL_125M 0 ++#define YT8531_SCR_CLK_SRC_UTP_RX 1 ++#define YT8531_SCR_CLK_SRC_SDS_RX 2 ++#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 ++#define YT8531_SCR_CLK_SRC_REF_25M 4 ++#define YT8531_SCR_CLK_SRC_SSC_25M 5 + #define YT8531S_SYNCE_CFG_REG 0xA012 + #define YT8531S_SCR_SYNCE_ENABLE BIT(6) + +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch b/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch new file mode 100644 index 0000000000000..206cedbcbd23e --- /dev/null +++ b/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch @@ -0,0 +1,347 @@ +From 1dd58db7f1ce60c13771a32d553be80112962600 Mon Sep 17 00:00:00 2001 +From: Frank Sae +Date: Thu, 2 Feb 2023 11:00:35 +0800 +Subject: [PATCH 66/70] net: phy: Add dts support for Motorcomm yt8521 gigabit + ethernet phy + +Add dts support for Motorcomm yt8521 gigabit ethernet phy. + Add ytphy_rgmii_clk_delay_config function to support dst config for + the delay of rgmii clk. This funciont is common for yt8521, yt8531s + and yt8531. + This patch has been verified on AM335x platform. + +Signed-off-by: Frank Sae +Reviewed-by: Andrew Lunn +--- + drivers/net/phy/motorcomm.c | 253 ++++++++++++++++++++++++++++-------- + 1 file changed, 199 insertions(+), 54 deletions(-) + +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index d8523e33424d..fc06fe6ef9ba 100644 +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + + #define PHY_ID_YT8511 0x0000010a + #define PHY_ID_YT8521 0x0000011A +@@ -187,21 +188,9 @@ + * 1b1 use inverted tx_clk_rgmii. + */ + #define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) +-/* TX Gig-E Delay is bits 3:0, default 0x1 +- * TX Fast-E Delay is bits 7:4, default 0xf +- * RX Delay is bits 13:10, default 0x0 +- * Delay = 150ps * N +- * On = 2250ps, off = 0ps +- */ + #define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) +-#define YT8521_RC1R_RX_DELAY_EN (0xF << 10) +-#define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) + #define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) +-#define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) +-#define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) + #define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) +-#define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) +-#define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) + #define YT8521_RC1R_RGMII_0_000_NS 0 + #define YT8521_RC1R_RGMII_0_150_NS 1 + #define YT8521_RC1R_RGMII_0_300_NS 2 +@@ -274,6 +263,10 @@ + + /* Extended Register end */ + ++#define YTPHY_DTS_OUTPUT_CLK_DIS 0 ++#define YTPHY_DTS_OUTPUT_CLK_25M 25000000 ++#define YTPHY_DTS_OUTPUT_CLK_125M 125000000 ++ + struct yt8521_priv { + /* combo_advertising is used for case of YT8521 in combo mode, + * this means that yt8521 may work in utp or fiber mode which depends +@@ -640,6 +633,142 @@ static int yt8521_write_page(struct phy_device *phydev, int page) + return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); + }; + ++/** ++ * struct ytphy_cfg_reg_map - map a config value to a register value ++ * @cfg: value in device configuration ++ * @reg: value in the register ++ */ ++struct ytphy_cfg_reg_map { ++ u32 cfg; ++ u32 reg; ++}; ++ ++static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { ++ /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ ++ { 0, YT8521_RC1R_RGMII_0_000_NS }, ++ { 150, YT8521_RC1R_RGMII_0_150_NS }, ++ { 300, YT8521_RC1R_RGMII_0_300_NS }, ++ { 450, YT8521_RC1R_RGMII_0_450_NS }, ++ { 600, YT8521_RC1R_RGMII_0_600_NS }, ++ { 750, YT8521_RC1R_RGMII_0_750_NS }, ++ { 900, YT8521_RC1R_RGMII_0_900_NS }, ++ { 1050, YT8521_RC1R_RGMII_1_050_NS }, ++ { 1200, YT8521_RC1R_RGMII_1_200_NS }, ++ { 1350, YT8521_RC1R_RGMII_1_350_NS }, ++ { 1500, YT8521_RC1R_RGMII_1_500_NS }, ++ { 1650, YT8521_RC1R_RGMII_1_650_NS }, ++ { 1800, YT8521_RC1R_RGMII_1_800_NS }, ++ { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ ++ { 2100, YT8521_RC1R_RGMII_2_100_NS }, ++ { 2250, YT8521_RC1R_RGMII_2_250_NS }, ++ ++ /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ ++ { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, ++ { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, ++ { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, ++ { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, ++ { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, ++ { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, ++ { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, ++ { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, ++ { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, ++ { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, ++ { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, ++ { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, ++ { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, ++ { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, ++ { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, ++ { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } ++}; ++ ++static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, ++ const char *prop_name, ++ const struct ytphy_cfg_reg_map *tbl, ++ int tb_size, ++ u16 *rxc_dly_en, ++ u32 dflt) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ int tb_size_half = tb_size / 2; ++ u32 val; ++ int i; ++ ++ if (of_property_read_u32(node, prop_name, &val)) ++ goto err_dts_val; ++ ++ /* when rxc_dly_en is NULL, it is get the delay for tx, only half of ++ * tb_size is valid. ++ */ ++ if (!rxc_dly_en) ++ tb_size = tb_size_half; ++ ++ for (i = 0; i < tb_size; i++) { ++ if (tbl[i].cfg == val) { ++ if (rxc_dly_en && i < tb_size_half) ++ *rxc_dly_en = 0; ++ return tbl[i].reg; ++ } ++ } ++ ++ phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", ++ val, prop_name, dflt); ++ ++err_dts_val: ++ /* when rxc_dly_en is not NULL, it is get the delay for rx. ++ * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, ++ * so YT8521_CCR_RXC_DLY_EN should not be set. ++ */ ++ if (rxc_dly_en) ++ *rxc_dly_en = 0; ++ ++ return dflt; ++} ++ ++static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) ++{ ++ int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); ++ u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; ++ u32 rx_reg, tx_reg; ++ u16 mask, val = 0; ++ int ret; ++ ++ rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", ++ ytphy_rgmii_delays, tb_size, ++ &rxc_dly_en, ++ YT8521_RC1R_RGMII_1_950_NS); ++ tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", ++ ytphy_rgmii_delays, tb_size, NULL, ++ YT8521_RC1R_RGMII_1_950_NS); ++ ++ switch (phydev->interface) { ++ case PHY_INTERFACE_MODE_RGMII: ++ rxc_dly_en = 0; ++ break; ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); ++ break; ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ rxc_dly_en = 0; ++ val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); ++ break; ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | ++ FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); ++ break; ++ default: /* do not support other modes */ ++ return -EOPNOTSUPP; ++ } ++ ++ ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, ++ YT8521_CCR_RXC_DLY_EN, rxc_dly_en); ++ if (ret < 0) ++ return ret; ++ ++ /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ ++ mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; ++ return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); ++} ++ + /** + * yt8521_probe() - read chip config then set suitable polling_mode + * @phydev: a pointer to a &struct phy_device +@@ -648,9 +777,12 @@ static int yt8521_write_page(struct phy_device *phydev, int page) + */ + static int yt8521_probe(struct phy_device *phydev) + { ++ struct device_node *node = phydev->mdio.dev.of_node; + struct device *dev = &phydev->mdio.dev; + struct yt8521_priv *priv; + int chip_config; ++ u16 mask, val; ++ u32 freq; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); +@@ -695,7 +827,45 @@ static int yt8521_probe(struct phy_device *phydev) + return ret; + } + +- return 0; ++ if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) ++ freq = YTPHY_DTS_OUTPUT_CLK_DIS; ++ ++ if (phydev->drv->phy_id == PHY_ID_YT8521) { ++ switch (freq) { ++ case YTPHY_DTS_OUTPUT_CLK_DIS: ++ mask = YT8521_SCR_SYNCE_ENABLE; ++ val = 0; ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_25M: ++ mask = YT8521_SCR_SYNCE_ENABLE | ++ YT8521_SCR_CLK_SRC_MASK | ++ YT8521_SCR_CLK_FRE_SEL_125M; ++ val = YT8521_SCR_SYNCE_ENABLE | ++ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, ++ YT8521_SCR_CLK_SRC_REF_25M); ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_125M: ++ mask = YT8521_SCR_SYNCE_ENABLE | ++ YT8521_SCR_CLK_SRC_MASK | ++ YT8521_SCR_CLK_FRE_SEL_125M; ++ val = YT8521_SCR_SYNCE_ENABLE | ++ YT8521_SCR_CLK_FRE_SEL_125M | ++ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, ++ YT8521_SCR_CLK_SRC_PLL_125M); ++ break; ++ default: ++ phydev_warn(phydev, "Freq err:%u\n", freq); ++ return -EINVAL; ++ } ++ } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { ++ return 0; ++ } else { ++ phydev_warn(phydev, "PHY id err\n"); ++ return -EINVAL; ++ } ++ ++ return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, ++ val); + } + + /** +@@ -1180,61 +1350,36 @@ static int yt8521_resume(struct phy_device *phydev) + */ + static int yt8521_config_init(struct phy_device *phydev) + { ++ struct device_node *node = phydev->mdio.dev.of_node; + int old_page; + int ret = 0; +- u16 val; + + old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); + if (old_page < 0) + goto err_restore_page; + +- switch (phydev->interface) { +- case PHY_INTERFACE_MODE_RGMII: +- val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; +- val |= YT8521_RC1R_RX_DELAY_DIS; +- break; +- case PHY_INTERFACE_MODE_RGMII_RXID: +- val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; +- val |= YT8521_RC1R_RX_DELAY_EN; +- break; +- case PHY_INTERFACE_MODE_RGMII_TXID: +- val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; +- val |= YT8521_RC1R_RX_DELAY_DIS; +- break; +- case PHY_INTERFACE_MODE_RGMII_ID: +- val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; +- val |= YT8521_RC1R_RX_DELAY_EN; +- break; +- case PHY_INTERFACE_MODE_SGMII: +- break; +- default: /* do not support other modes */ +- ret = -EOPNOTSUPP; +- goto err_restore_page; +- } +- + /* set rgmii delay mode */ + if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { +- ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, +- (YT8521_RC1R_RX_DELAY_MASK | +- YT8521_RC1R_FE_TX_DELAY_MASK | +- YT8521_RC1R_GE_TX_DELAY_MASK), +- val); ++ ret = ytphy_rgmii_clk_delay_config(phydev); + if (ret < 0) + goto err_restore_page; + } + +- /* disable auto sleep */ +- ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, +- YT8521_ESC1R_SLEEP_SW, 0); +- if (ret < 0) +- goto err_restore_page; +- +- /* enable RXC clock when no wire plug */ +- ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, +- YT8521_CGR_RX_CLK_EN, 0); +- if (ret < 0) +- goto err_restore_page; ++ if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { ++ /* disable auto sleep */ ++ ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, ++ YT8521_ESC1R_SLEEP_SW, 0); ++ if (ret < 0) ++ goto err_restore_page; ++ } + ++ if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { ++ /* enable RXC clock when no wire plug */ ++ ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, ++ YT8521_CGR_RX_CLK_EN, 0); ++ if (ret < 0) ++ goto err_restore_page; ++ } + err_restore_page: + return phy_restore_page(phydev, old_page, ret); + } +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch b/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch new file mode 100644 index 0000000000000..2aac9aeb25fa3 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch @@ -0,0 +1,104 @@ +From 5d942efe006c8d22cf03be7c1423e37667560729 Mon Sep 17 00:00:00 2001 +From: Frank Sae +Date: Thu, 2 Feb 2023 11:00:36 +0800 +Subject: [PATCH 67/70] net: phy: Add dts support for Motorcomm yt8531s gigabit + ethernet phy + +Add dts support for Motorcomm yt8531s gigabit ethernet phy. + Change yt8521_probe to support clk config of yt8531s. Becase + yt8521_probe does the things which yt8531s is needed, so + removed yt8531s function. + This patch has been verified on AM335x platform with yt8531s board. + +Signed-off-by: Frank Sae +Reviewed-by: Andrew Lunn +--- + drivers/net/phy/motorcomm.c | 51 ++++++++++++++++++++----------------- + 1 file changed, 27 insertions(+), 24 deletions(-) + +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index fc06fe6ef9ba..78392174536b 100644 +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -258,8 +258,6 @@ + #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 + #define YT8531_SCR_CLK_SRC_REF_25M 4 + #define YT8531_SCR_CLK_SRC_SSC_25M 5 +-#define YT8531S_SYNCE_CFG_REG 0xA012 +-#define YT8531S_SCR_SYNCE_ENABLE BIT(6) + + /* Extended Register end */ + +@@ -858,7 +856,32 @@ static int yt8521_probe(struct phy_device *phydev) + return -EINVAL; + } + } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { +- return 0; ++ switch (freq) { ++ case YTPHY_DTS_OUTPUT_CLK_DIS: ++ mask = YT8531_SCR_SYNCE_ENABLE; ++ val = 0; ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_25M: ++ mask = YT8531_SCR_SYNCE_ENABLE | ++ YT8531_SCR_CLK_SRC_MASK | ++ YT8531_SCR_CLK_FRE_SEL_125M; ++ val = YT8531_SCR_SYNCE_ENABLE | ++ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, ++ YT8531_SCR_CLK_SRC_REF_25M); ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_125M: ++ mask = YT8531_SCR_SYNCE_ENABLE | ++ YT8531_SCR_CLK_SRC_MASK | ++ YT8531_SCR_CLK_FRE_SEL_125M; ++ val = YT8531_SCR_SYNCE_ENABLE | ++ YT8531_SCR_CLK_FRE_SEL_125M | ++ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, ++ YT8531_SCR_CLK_SRC_PLL_125M); ++ break; ++ default: ++ phydev_warn(phydev, "Freq err:%u\n", freq); ++ return -EINVAL; ++ } + } else { + phydev_warn(phydev, "PHY id err\n"); + return -EINVAL; +@@ -868,26 +891,6 @@ static int yt8521_probe(struct phy_device *phydev) + val); + } + +-/** +- * yt8531s_probe() - read chip config then set suitable polling_mode +- * @phydev: a pointer to a &struct phy_device +- * +- * returns 0 or negative errno code +- */ +-static int yt8531s_probe(struct phy_device *phydev) +-{ +- int ret; +- +- /* Disable SyncE clock output by default */ +- ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG, +- YT8531S_SCR_SYNCE_ENABLE, 0); +- if (ret < 0) +- return ret; +- +- /* same as yt8521_probe */ +- return yt8521_probe(phydev); +-} +- + /** + * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp + * @phydev: a pointer to a &struct phy_device +@@ -1970,7 +1973,7 @@ static struct phy_driver motorcomm_phy_drvs[] = { + PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), + .name = "YT8531S Gigabit Ethernet", + .get_features = yt8521_get_features, +- .probe = yt8531s_probe, ++ .probe = yt8521_probe, + .read_page = yt8521_read_page, + .write_page = yt8521_write_page, + .get_wol = ytphy_get_wol, +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch b/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch new file mode 100644 index 0000000000000..cd63e496448a9 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch @@ -0,0 +1,308 @@ +From 4067c531d9ed4ccab0d134fb64856a62ac9044cc Mon Sep 17 00:00:00 2001 +From: Frank Sae +Date: Thu, 2 Feb 2023 11:00:37 +0800 +Subject: [PATCH 68/70] net: phy: Add driver for Motorcomm yt8531 gigabit + ethernet phy + +Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have + verified the driver on AM335x platform with yt8531 board. On the + board, yt8531 gigabit ethernet phy works in utp mode, RGMII + interface, supports 1000M/100M/10M speeds, and wol(magic package). + +Signed-off-by: Frank Sae +Reviewed-by: Andrew Lunn +--- + drivers/net/phy/Kconfig | 2 +- + drivers/net/phy/motorcomm.c | 208 +++++++++++++++++++++++++++++++++++- + 2 files changed, 207 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 1327290decab..6bf557ed0c8e 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -257,7 +257,7 @@ config MOTORCOMM_PHY + tristate "Motorcomm PHYs" + help + Enables support for Motorcomm network PHYs. +- Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs. ++ Currently supports YT85xx Gigabit Ethernet PHYs. + + config NATIONAL_PHY + tristate "National Semiconductor PHYs" +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index 78392174536b..3f96659cab8c 100644 +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Motorcomm 8511/8521/8531S PHY driver. ++ * Motorcomm 8511/8521/8531/8531S PHY driver. + * + * Author: Peter Geis + * Author: Frank +@@ -14,6 +14,7 @@ + + #define PHY_ID_YT8511 0x0000010a + #define PHY_ID_YT8521 0x0000011A ++#define PHY_ID_YT8531 0x4F51E91B + #define PHY_ID_YT8531S 0x4F51E91A + + /* YT8521/YT8531S Register Overview +@@ -517,6 +518,61 @@ static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) + return phy_restore_page(phydev, old_page, ret); + } + ++static int yt8531_set_wol(struct phy_device *phydev, ++ struct ethtool_wolinfo *wol) ++{ ++ const u16 mac_addr_reg[] = { ++ YTPHY_WOL_MACADDR2_REG, ++ YTPHY_WOL_MACADDR1_REG, ++ YTPHY_WOL_MACADDR0_REG, ++ }; ++ const u8 *mac_addr; ++ u16 mask, val; ++ int ret; ++ u8 i; ++ ++ if (wol->wolopts & WAKE_MAGIC) { ++ mac_addr = phydev->attached_dev->dev_addr; ++ ++ /* Store the device address for the magic packet */ ++ for (i = 0; i < 3; i++) { ++ ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], ++ ((mac_addr[i * 2] << 8)) | ++ (mac_addr[i * 2 + 1])); ++ if (ret < 0) ++ return ret; ++ } ++ ++ /* Enable WOL feature */ ++ mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; ++ val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; ++ val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; ++ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, ++ mask, val); ++ if (ret < 0) ++ return ret; ++ ++ /* Enable WOL interrupt */ ++ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, ++ YTPHY_IER_WOL); ++ if (ret < 0) ++ return ret; ++ } else { ++ /* Disable WOL feature */ ++ mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; ++ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, ++ mask, 0); ++ ++ /* Disable WOL interrupt */ ++ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, ++ YTPHY_IER_WOL, 0); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int yt8511_read_page(struct phy_device *phydev) + { + return __phy_read(phydev, YT8511_PAGE_SELECT); +@@ -767,6 +823,17 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) + return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); + } + ++static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) ++{ ++ int ret; ++ ++ phy_lock_mdio_bus(phydev); ++ ret = ytphy_rgmii_clk_delay_config(phydev); ++ phy_unlock_mdio_bus(phydev); ++ ++ return ret; ++} ++ + /** + * yt8521_probe() - read chip config then set suitable polling_mode + * @phydev: a pointer to a &struct phy_device +@@ -891,6 +958,43 @@ static int yt8521_probe(struct phy_device *phydev) + val); + } + ++static int yt8531_probe(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ u16 mask, val; ++ u32 freq; ++ ++ if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) ++ freq = YTPHY_DTS_OUTPUT_CLK_DIS; ++ ++ switch (freq) { ++ case YTPHY_DTS_OUTPUT_CLK_DIS: ++ mask = YT8531_SCR_SYNCE_ENABLE; ++ val = 0; ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_25M: ++ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | ++ YT8531_SCR_CLK_FRE_SEL_125M; ++ val = YT8531_SCR_SYNCE_ENABLE | ++ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, ++ YT8531_SCR_CLK_SRC_REF_25M); ++ break; ++ case YTPHY_DTS_OUTPUT_CLK_125M: ++ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | ++ YT8531_SCR_CLK_FRE_SEL_125M; ++ val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | ++ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, ++ YT8531_SCR_CLK_SRC_PLL_125M); ++ break; ++ default: ++ phydev_warn(phydev, "Freq err:%u\n", freq); ++ return -EINVAL; ++ } ++ ++ return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, ++ val); ++} ++ + /** + * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp + * @phydev: a pointer to a &struct phy_device +@@ -1387,6 +1491,94 @@ static int yt8521_config_init(struct phy_device *phydev) + return phy_restore_page(phydev, old_page, ret); + } + ++static int yt8531_config_init(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ int ret; ++ ++ ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); ++ if (ret < 0) ++ return ret; ++ ++ if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { ++ /* disable auto sleep */ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YT8521_EXTREG_SLEEP_CONTROL1_REG, ++ YT8521_ESC1R_SLEEP_SW, 0); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { ++ /* enable RXC clock when no wire plug */ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YT8521_CLOCK_GATING_REG, ++ YT8521_CGR_RX_CLK_EN, 0); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/** ++ * yt8531_link_change_notify() - Adjust the tx clock direction according to ++ * the current speed and dts config. ++ * @phydev: a pointer to a &struct phy_device ++ * ++ * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please ++ * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not ++ * JH7110. ++ */ ++static void yt8531_link_change_notify(struct phy_device *phydev) ++{ ++ struct device_node *node = phydev->mdio.dev.of_node; ++ bool tx_clk_adj_enabled = false; ++ bool tx_clk_1000_inverted; ++ bool tx_clk_100_inverted; ++ bool tx_clk_10_inverted; ++ u16 val = 0; ++ int ret; ++ ++ if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled")) ++ tx_clk_adj_enabled = true; ++ ++ if (!tx_clk_adj_enabled) ++ return; ++ ++ if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted")) ++ tx_clk_10_inverted = true; ++ if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted")) ++ tx_clk_100_inverted = true; ++ if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) ++ tx_clk_1000_inverted = true; ++ ++ if (phydev->speed < 0) ++ return; ++ ++ switch (phydev->speed) { ++ case SPEED_1000: ++ if (tx_clk_1000_inverted) ++ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; ++ break; ++ case SPEED_100: ++ if (tx_clk_100_inverted) ++ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; ++ break; ++ case SPEED_10: ++ if (tx_clk_10_inverted) ++ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; ++ break; ++ default: ++ return; ++ } ++ ++ ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, ++ YT8521_RC1R_TX_CLK_SEL_INVERTED, val); ++ if (ret < 0) ++ phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); ++} ++ + /** + * yt8521_prepare_fiber_features() - A small helper function that setup + * fiber's features. +@@ -1969,6 +2161,17 @@ static struct phy_driver motorcomm_phy_drvs[] = { + .suspend = yt8521_suspend, + .resume = yt8521_resume, + }, ++ { ++ PHY_ID_MATCH_EXACT(PHY_ID_YT8531), ++ .name = "YT8531 Gigabit Ethernet", ++ .probe = yt8531_probe, ++ .config_init = yt8531_config_init, ++ .suspend = genphy_suspend, ++ .resume = genphy_resume, ++ .get_wol = ytphy_get_wol, ++ .set_wol = yt8531_set_wol, ++ .link_change_notify = yt8531_link_change_notify, ++ }, + { + PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), + .name = "YT8531S Gigabit Ethernet", +@@ -1990,7 +2193,7 @@ static struct phy_driver motorcomm_phy_drvs[] = { + + module_phy_driver(motorcomm_phy_drvs); + +-MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver"); ++MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver"); + MODULE_AUTHOR("Peter Geis"); + MODULE_AUTHOR("Frank"); + MODULE_LICENSE("GPL"); +@@ -1998,6 +2201,7 @@ MODULE_LICENSE("GPL"); + static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { + { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, + { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, ++ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, + { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, + { /* sentinal */ } + }; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch b/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch new file mode 100644 index 0000000000000..1f9249bda2228 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch @@ -0,0 +1,95 @@ +From 240b171ea0dc33255bf53da1ba07c02498acb9ad Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 27 Feb 2023 21:41:24 +0800 +Subject: [PATCH 69/70] dt-bindings: hwmon: Add starfive,jh71x0-temp + +Add bindings for the temperature sensor on the StarFive JH7100 and +JH7110 SoCs. + +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +Reviewed-by: Rob Herring +--- + .../bindings/hwmon/starfive,jh71x0-temp.yaml | 70 +++++++++++++++++++ + 1 file changed, 70 insertions(+) + create mode 100644 Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml + +diff --git a/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml +new file mode 100644 +index 000000000000..f5b34528928d +--- /dev/null ++++ b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml +@@ -0,0 +1,70 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH71x0 Temperature Sensor ++ ++maintainers: ++ - Emil Renner Berthing ++ ++description: | ++ StarFive Technology Co. JH71x0 embedded temperature sensor ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7100-temp ++ - starfive,jh7110-temp ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 2 ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: "sense" ++ - const: "bus" ++ ++ '#thermal-sensor-cells': ++ const: 0 ++ ++ resets: ++ minItems: 2 ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: "sense" ++ - const: "bus" ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ temperature-sensor@124a0000 { ++ compatible = "starfive,jh7100-temp"; ++ reg = <0x124a0000 0x10000>; ++ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, ++ <&clkgen JH7100_CLK_TEMP_APB>; ++ clock-names = "sense", "bus"; ++ #thermal-sensor-cells = <0>; ++ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, ++ <&rstgen JH7100_RSTN_TEMP_APB>; ++ reset-names = "sense", "bus"; ++ }; +-- +2.39.2 + diff --git a/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch b/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch new file mode 100644 index 0000000000000..51a005d872691 --- /dev/null +++ b/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch @@ -0,0 +1,467 @@ +From be2917cfa4f7bed92ebfa8d439a4f0fb361f28a2 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 27 Feb 2023 21:41:25 +0800 +Subject: [PATCH 70/70] hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor + +Add driver for the StarFive JH71x0 temperature sensor. You +can enable/disable it and read temperature in milli Celcius +through sysfs. + +Signed-off-by: Emil Renner Berthing +Co-developed-by: Samin Guo +Signed-off-by: Samin Guo +Signed-off-by: Hal Feng +--- + Documentation/hwmon/index.rst | 1 + + Documentation/hwmon/sfctemp.rst | 33 ++++ + MAINTAINERS | 8 + + drivers/hwmon/Kconfig | 10 + + drivers/hwmon/Makefile | 1 + + drivers/hwmon/sfctemp.c | 331 ++++++++++++++++++++++++++++++++ + 6 files changed, 384 insertions(+) + create mode 100644 Documentation/hwmon/sfctemp.rst + create mode 100644 drivers/hwmon/sfctemp.c + +diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst +index fe2cc6b73634..a666e3706ea2 100644 +--- a/Documentation/hwmon/index.rst ++++ b/Documentation/hwmon/index.rst +@@ -180,6 +180,7 @@ Hardware Monitoring Kernel Drivers + sch5627 + sch5636 + scpi-hwmon ++ sfctemp + sht15 + sht21 + sht3x +diff --git a/Documentation/hwmon/sfctemp.rst b/Documentation/hwmon/sfctemp.rst +new file mode 100644 +index 000000000000..9fbd5bb1f356 +--- /dev/null ++++ b/Documentation/hwmon/sfctemp.rst +@@ -0,0 +1,33 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver sfctemp ++===================== ++ ++Supported chips: ++ - StarFive JH7100 ++ - StarFive JH7110 ++ ++Authors: ++ - Emil Renner Berthing ++ ++Description ++----------- ++ ++This driver adds support for reading the built-in temperature sensor on the ++JH7100 and JH7110 RISC-V SoCs by StarFive Technology Co. Ltd. ++ ++``sysfs`` interface ++------------------- ++ ++The temperature sensor can be enabled, disabled and queried via the standard ++hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of ++``X``: ++ ++================ ==== ============================================= ++Name Perm Description ++================ ==== ============================================= ++temp1_enable RW Enable or disable temperature sensor. ++ Automatically enabled by the driver, ++ but may be disabled to save power. ++temp1_input RO Temperature reading in milli-degrees Celsius. ++================ ==== ============================================= +diff --git a/MAINTAINERS b/MAINTAINERS +index 7c73cdbe1259..dbc570dda496 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -18918,6 +18918,14 @@ L: netdev@vger.kernel.org + S: Supported + F: drivers/net/ethernet/sfc/ + ++SFCTEMP HWMON DRIVER ++M: Emil Renner Berthing ++L: linux-hwmon@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml ++F: Documentation/hwmon/sfctemp.rst ++F: drivers/hwmon/sfctemp.c ++ + SFF/SFP/SFP+ MODULE SUPPORT + M: Russell King + L: netdev@vger.kernel.org +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 3176c33af6c6..572e1b2541bb 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -1930,6 +1930,16 @@ config SENSORS_STTS751 + This driver can also be built as a module. If so, the module + will be called stts751. + ++config SENSORS_SFCTEMP ++ tristate "Starfive JH71x0 temperature sensor" ++ depends on SOC_STARFIVE || COMPILE_TEST ++ help ++ If you say yes here you get support for temperature sensor ++ on the Starfive JH71x0 SoCs. ++ ++ This driver can also be built as a module. If so, the module ++ will be called sfctemp. ++ + config SENSORS_SMM665 + tristate "Summit Microelectronics SMM665" + depends on I2C +diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile +index e2e4e87b282f..337e1b19678a 100644 +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -180,6 +180,7 @@ obj-$(CONFIG_SENSORS_SBRMI) += sbrmi.o + obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o + obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o + obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o ++obj-$(CONFIG_SENSORS_SFCTEMP) += sfctemp.o + obj-$(CONFIG_SENSORS_SL28CPLD) += sl28cpld-hwmon.o + obj-$(CONFIG_SENSORS_SHT15) += sht15.o + obj-$(CONFIG_SENSORS_SHT21) += sht21.o +diff --git a/drivers/hwmon/sfctemp.c b/drivers/hwmon/sfctemp.c +new file mode 100644 +index 000000000000..d7484e2b8100 +--- /dev/null ++++ b/drivers/hwmon/sfctemp.c +@@ -0,0 +1,331 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2021 Emil Renner Berthing ++ * Copyright (C) 2021 Samin Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * TempSensor reset. The RSTN can be de-asserted once the analog core has ++ * powered up. Trst(min 100ns) ++ * 0:reset 1:de-assert ++ */ ++#define SFCTEMP_RSTN BIT(0) ++ ++/* ++ * TempSensor analog core power down. The analog core will be powered up ++ * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the ++ * analog core is powered up. ++ * 0:power up 1:power down ++ */ ++#define SFCTEMP_PD BIT(1) ++ ++/* ++ * TempSensor start conversion enable. ++ * 0:disable 1:enable ++ */ ++#define SFCTEMP_RUN BIT(2) ++ ++/* ++ * TempSensor conversion value output. ++ * Temp(C)=DOUT*Y/4094 - K ++ */ ++#define SFCTEMP_DOUT_POS 16 ++#define SFCTEMP_DOUT_MSK GENMASK(27, 16) ++ ++/* DOUT to Celcius conversion constants */ ++#define SFCTEMP_Y1000 237500L ++#define SFCTEMP_Z 4094L ++#define SFCTEMP_K1000 81100L ++ ++struct sfctemp { ++ /* serialize access to hardware register and enabled below */ ++ struct mutex lock; ++ void __iomem *regs; ++ struct clk *clk_sense; ++ struct clk *clk_bus; ++ struct reset_control *rst_sense; ++ struct reset_control *rst_bus; ++ bool enabled; ++}; ++ ++static void sfctemp_power_up(struct sfctemp *sfctemp) ++{ ++ /* make sure we're powered down first */ ++ writel(SFCTEMP_PD, sfctemp->regs); ++ udelay(1); ++ ++ writel(0, sfctemp->regs); ++ /* wait t_pu(50us) + t_rst(100ns) */ ++ usleep_range(60, 200); ++ ++ /* de-assert reset */ ++ writel(SFCTEMP_RSTN, sfctemp->regs); ++ udelay(1); /* wait t_su(500ps) */ ++} ++ ++static void sfctemp_power_down(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_PD, sfctemp->regs); ++} ++ ++static void sfctemp_run(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs); ++ udelay(1); ++} ++ ++static void sfctemp_stop(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_RSTN, sfctemp->regs); ++} ++ ++static int sfctemp_enable(struct sfctemp *sfctemp) ++{ ++ int ret = 0; ++ ++ mutex_lock(&sfctemp->lock); ++ if (sfctemp->enabled) ++ goto done; ++ ++ ret = clk_prepare_enable(sfctemp->clk_bus); ++ if (ret) ++ goto err; ++ ret = reset_control_deassert(sfctemp->rst_bus); ++ if (ret) ++ goto err_disable_bus; ++ ++ ret = clk_prepare_enable(sfctemp->clk_sense); ++ if (ret) ++ goto err_assert_bus; ++ ret = reset_control_deassert(sfctemp->rst_sense); ++ if (ret) ++ goto err_disable_sense; ++ ++ sfctemp_power_up(sfctemp); ++ sfctemp_run(sfctemp); ++ sfctemp->enabled = true; ++done: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++ ++err_disable_sense: ++ clk_disable_unprepare(sfctemp->clk_sense); ++err_assert_bus: ++ reset_control_assert(sfctemp->rst_bus); ++err_disable_bus: ++ clk_disable_unprepare(sfctemp->clk_bus); ++err: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++} ++ ++static int sfctemp_disable(struct sfctemp *sfctemp) ++{ ++ mutex_lock(&sfctemp->lock); ++ if (!sfctemp->enabled) ++ goto done; ++ ++ sfctemp_stop(sfctemp); ++ sfctemp_power_down(sfctemp); ++ reset_control_assert(sfctemp->rst_sense); ++ clk_disable_unprepare(sfctemp->clk_sense); ++ reset_control_assert(sfctemp->rst_bus); ++ clk_disable_unprepare(sfctemp->clk_bus); ++ sfctemp->enabled = false; ++done: ++ mutex_unlock(&sfctemp->lock); ++ return 0; ++} ++ ++static void sfctemp_disable_action(void *data) ++{ ++ sfctemp_disable(data); ++} ++ ++static int sfctemp_convert(struct sfctemp *sfctemp, long *val) ++{ ++ int ret; ++ ++ mutex_lock(&sfctemp->lock); ++ if (!sfctemp->enabled) { ++ ret = -ENODATA; ++ goto out; ++ } ++ ++ /* calculate temperature in milli Celcius */ ++ *val = (long)((readl(sfctemp->regs) & SFCTEMP_DOUT_MSK) >> SFCTEMP_DOUT_POS) ++ * SFCTEMP_Y1000 / SFCTEMP_Z - SFCTEMP_K1000; ++ ++ ret = 0; ++out: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++} ++ ++static umode_t sfctemp_is_visible(const void *data, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ return 0644; ++ case hwmon_temp_input: ++ return 0444; ++ default: ++ return 0; ++ } ++ default: ++ return 0; ++ } ++} ++ ++static int sfctemp_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ struct sfctemp *sfctemp = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ *val = sfctemp->enabled; ++ return 0; ++ case hwmon_temp_input: ++ return sfctemp_convert(sfctemp, val); ++ default: ++ return -EINVAL; ++ } ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int sfctemp_write(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long val) ++{ ++ struct sfctemp *sfctemp = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ if (val == 0) ++ return sfctemp_disable(sfctemp); ++ if (val == 1) ++ return sfctemp_enable(sfctemp); ++ return -EINVAL; ++ default: ++ return -EINVAL; ++ } ++ default: ++ return -EINVAL; ++ } ++} ++ ++static const struct hwmon_channel_info *sfctemp_info[] = { ++ HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), ++ HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT), ++ NULL ++}; ++ ++static const struct hwmon_ops sfctemp_hwmon_ops = { ++ .is_visible = sfctemp_is_visible, ++ .read = sfctemp_read, ++ .write = sfctemp_write, ++}; ++ ++static const struct hwmon_chip_info sfctemp_chip_info = { ++ .ops = &sfctemp_hwmon_ops, ++ .info = sfctemp_info, ++}; ++ ++static int sfctemp_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device *hwmon_dev; ++ struct sfctemp *sfctemp; ++ int ret; ++ ++ sfctemp = devm_kzalloc(dev, sizeof(*sfctemp), GFP_KERNEL); ++ if (!sfctemp) ++ return -ENOMEM; ++ ++ dev_set_drvdata(dev, sfctemp); ++ mutex_init(&sfctemp->lock); ++ ++ sfctemp->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(sfctemp->regs)) ++ return PTR_ERR(sfctemp->regs); ++ ++ sfctemp->clk_sense = devm_clk_get(dev, "sense"); ++ if (IS_ERR(sfctemp->clk_sense)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_sense), ++ "error getting sense clock\n"); ++ ++ sfctemp->clk_bus = devm_clk_get(dev, "bus"); ++ if (IS_ERR(sfctemp->clk_bus)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_bus), ++ "error getting bus clock\n"); ++ ++ sfctemp->rst_sense = devm_reset_control_get_exclusive(dev, "sense"); ++ if (IS_ERR(sfctemp->rst_sense)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_sense), ++ "error getting sense reset\n"); ++ ++ sfctemp->rst_bus = devm_reset_control_get_exclusive(dev, "bus"); ++ if (IS_ERR(sfctemp->rst_bus)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_bus), ++ "error getting busreset\n"); ++ ++ ret = reset_control_assert(sfctemp->rst_sense); ++ if (ret) ++ return dev_err_probe(dev, ret, "error asserting sense reset\n"); ++ ++ ret = reset_control_assert(sfctemp->rst_bus); ++ if (ret) ++ return dev_err_probe(dev, ret, "error asserting bus reset\n"); ++ ++ ret = devm_add_action(dev, sfctemp_disable_action, sfctemp); ++ if (ret) ++ return ret; ++ ++ ret = sfctemp_enable(sfctemp); ++ if (ret) ++ return dev_err_probe(dev, ret, "error enabling temperature sensor: %d\n", ret); ++ ++ hwmon_dev = devm_hwmon_device_register_with_info(dev, "sfctemp", sfctemp, ++ &sfctemp_chip_info, NULL); ++ return PTR_ERR_OR_ZERO(hwmon_dev); ++} ++ ++static const struct of_device_id sfctemp_of_match[] = { ++ { .compatible = "starfive,jh7100-temp" }, ++ { .compatible = "starfive,jh7110-temp" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, sfctemp_of_match); ++ ++static struct platform_driver sfctemp_driver = { ++ .probe = sfctemp_probe, ++ .driver = { ++ .name = "sfctemp", ++ .of_match_table = sfctemp_of_match, ++ }, ++}; ++module_platform_driver(sfctemp_driver); ++ ++MODULE_AUTHOR("Emil Renner Berthing"); ++MODULE_DESCRIPTION("StarFive JH71x0 temperature sensor driver"); ++MODULE_LICENSE("GPL"); +-- +2.39.2 + From 190f97ac133cba4b99228f21bed7500339b981e9 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 12 Mar 2023 22:00:45 +0100 Subject: [PATCH 148/189] qt5-webengine: add riscv patch --- .../patches/0089-enable-ppc64.patch | 37 - .../patches/0090-qtwebengine-ppc64.patch | 3603 -- .../patches/0091-chromium-ppc64le-musl.patch | 169 - .../0092-ppc64le-sandbox-linux-stat.patch | 31 - .../qt5-webengine/patches/0114-riscv64.patch | 2999 ++ .../patches/0115-riscv64-v8.patch | 33254 ++++++++++++++++ 6 files changed, 36253 insertions(+), 3840 deletions(-) delete mode 100644 srcpkgs/qt5-webengine/patches/0089-enable-ppc64.patch delete mode 100644 srcpkgs/qt5-webengine/patches/0090-qtwebengine-ppc64.patch delete mode 100644 srcpkgs/qt5-webengine/patches/0091-chromium-ppc64le-musl.patch delete mode 100644 srcpkgs/qt5-webengine/patches/0092-ppc64le-sandbox-linux-stat.patch create mode 100644 srcpkgs/qt5-webengine/patches/0114-riscv64.patch create mode 100644 srcpkgs/qt5-webengine/patches/0115-riscv64-v8.patch diff --git a/srcpkgs/qt5-webengine/patches/0089-enable-ppc64.patch b/srcpkgs/qt5-webengine/patches/0089-enable-ppc64.patch deleted file mode 100644 index 4fb19ccdd2e54..0000000000000 --- a/srcpkgs/qt5-webengine/patches/0089-enable-ppc64.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 463f1234c57a36e78ff666bd55094a9d4e68f296 Mon Sep 17 00:00:00 2001 -From: q66 -Date: Sat, 18 Jan 2020 23:52:55 +0100 -Subject: [PATCH 1/3] Enable ppc64 builds - ---- - configure.pri | 1 + - mkspecs/features/functions.prf | 1 + - 2 files changed, 2 insertions(+) - -diff --git a/configure.pri b/configure.pri -index 3a144e3f8..cabe8b24a 100644 ---- a/configure.pri 2021-02-24 10:45:58.000000000 +0100 -+++ - 2021-03-07 21:18:43.124754796 +0100 -@@ -144,6 +144,7 @@ - contains(QT_ARCH, "arm")|contains(QT_ARCH, "arm64"): return(true) - contains(QT_ARCH, "mips"): return(true) - contains(QT_ARCH, "mips64"): return(true) -+ contains(QT_ARCH, "power64"): return(true) - qtLog("Architecture not supported.") - return(false) - } -diff --git a/mkspecs/features/functions.prf b/mkspecs/features/functions.prf -index 512e2523b..e31123654 100644 ---- a/mkspecs/features/functions.prf 2021-02-24 10:45:58.000000000 +0100 -+++ - 2021-03-07 21:19:21.345036293 +0100 -@@ -107,6 +107,7 @@ - contains(qtArch, "mips"): return(mipsel) - contains(qtArch, "mips64"): return(mips64el) - contains(qtArch, "mips64el"): return(mips64el) -+ contains(qtArch, "power64"): return(ppc64) - return(unknown) - } - --- -2.26.0 - diff --git a/srcpkgs/qt5-webengine/patches/0090-qtwebengine-ppc64.patch b/srcpkgs/qt5-webengine/patches/0090-qtwebengine-ppc64.patch deleted file mode 100644 index 8c222ca89ee1d..0000000000000 --- a/srcpkgs/qt5-webengine/patches/0090-qtwebengine-ppc64.patch +++ /dev/null @@ -1,3603 +0,0 @@ -diff --git a/src/3rdparty/chromium/chrome/installer/linux/BUILD.gn b/src/3rdparty/chromium/chrome/installer/linux/BUILD.gn -index 9c92012ce..a4a5cd86d 100644 ---- a/src/3rdparty/chromium/chrome/installer/linux/BUILD.gn -+++ b/src/3rdparty/chromium/chrome/installer/linux/BUILD.gn -@@ -65,8 +65,6 @@ packaging_files = packaging_files_binaries + [ - "$root_out_dir/xdg-mime", - "$root_out_dir/xdg-settings", - "$root_out_dir/locales/en-US.pak", -- "$root_out_dir/MEIPreload/manifest.json", -- "$root_out_dir/MEIPreload/preloaded_data.pb", - ] - - action_foreach("calculate_deb_dependencies") { -@@ -331,7 +329,6 @@ group("installer_deps") { - ":theme_files", - "//chrome", - "//chrome:packed_resources", -- "//chrome/browser/resources/media/mei_preload:component", - "//sandbox/linux:chrome_sandbox", - "//third_party/crashpad/crashpad/handler:crashpad_handler", - ] -diff --git a/src/3rdparty/chromium/sandbox/features.gni b/src/3rdparty/chromium/sandbox/features.gni -index 09280d35f..42514157f 100644 ---- a/src/3rdparty/chromium/sandbox/features.gni -+++ b/src/3rdparty/chromium/sandbox/features.gni -@@ -11,6 +11,7 @@ import("//build/config/nacl/config.gni") - use_seccomp_bpf = (is_linux || is_android) && - (current_cpu == "x86" || current_cpu == "x64" || - current_cpu == "arm" || current_cpu == "arm64" || -- current_cpu == "mipsel" || current_cpu == "mips64el") -+ current_cpu == "mipsel" || current_cpu == "mips64el" || -+ current_cpu == "ppc64") - - use_seccomp_bpf = use_seccomp_bpf || is_nacl_nonsfi -diff --git a/src/3rdparty/chromium/sandbox/linux/BUILD.gn b/src/3rdparty/chromium/sandbox/linux/BUILD.gn -index c27351f9a..9141e1239 100644 ---- a/src/3rdparty/chromium/sandbox/linux/BUILD.gn -+++ b/src/3rdparty/chromium/sandbox/linux/BUILD.gn -@@ -407,6 +407,8 @@ component("sandbox_services") { - - source_set("sandbox_services_headers") { - sources = [ -+ "system_headers/ppc64_linux_syscalls.h", -+ "system_headers/ppc64_linux_ucontext.h", - "system_headers/arm64_linux_syscalls.h", - "system_headers/arm_linux_syscalls.h", - "system_headers/arm_linux_ucontext.h", -diff --git a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h -index 313511f22..0ca3a326f 100644 ---- a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h -+++ b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h -@@ -56,6 +56,13 @@ - #define MAX_PUBLIC_SYSCALL __NR_syscalls - #define MAX_SYSCALL MAX_PUBLIC_SYSCALL - -+#elif defined(__powerpc64__) -+ -+#include -+#define MIN_SYSCALL 0u -+#define MAX_PUBLIC_SYSCALL 386u -+#define MAX_SYSCALL MAX_PUBLIC_SYSCALL -+ - #else - #error "Unsupported architecture" - #endif -diff --git a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -index 1a407b952..a6aec544e 100644 ---- a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -+++ b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -@@ -16,6 +16,9 @@ - #if defined(__mips__) - // sys/user.h in eglibc misses size_t definition - #include -+#elif defined(__powerpc64__) -+// Manually define greg_t on ppc64 -+typedef unsigned long long greg_t; - #endif - #endif - -@@ -346,6 +349,51 @@ struct regs_struct { - #define SECCOMP_PT_PARM4(_regs) (_regs).regs[3] - #define SECCOMP_PT_PARM5(_regs) (_regs).regs[4] - #define SECCOMP_PT_PARM6(_regs) (_regs).regs[5] -+ -+#elif defined(__powerpc64__) -+#include -+ -+typedef struct pt_regs regs_struct; -+ -+#ifdef ARCH_CPU_LITTLE_ENDIAN -+#define SECCOMP_ARCH AUDIT_ARCH_PPC64LE -+#else -+#define SECCOMP_ARCH AUDIT_ARCH_PPC64 -+#endif -+ -+#define SECCOMP_REG(_ctx, _reg) ((_ctx)->uc_mcontext.regs->gpr[_reg]) -+ -+#define SECCOMP_RESULT(_ctx) SECCOMP_REG(_ctx, 3) -+#define SECCOMP_SYSCALL(_ctx) SECCOMP_REG(_ctx, 0) -+#define SECCOMP_IP(_ctx) (_ctx)->uc_mcontext.regs->nip -+#define SECCOMP_PARM1(_ctx) SECCOMP_REG(_ctx, 3) -+#define SECCOMP_PARM2(_ctx) SECCOMP_REG(_ctx, 4) -+#define SECCOMP_PARM3(_ctx) SECCOMP_REG(_ctx, 5) -+#define SECCOMP_PARM4(_ctx) SECCOMP_REG(_ctx, 6) -+#define SECCOMP_PARM5(_ctx) SECCOMP_REG(_ctx, 7) -+#define SECCOMP_PARM6(_ctx) SECCOMP_REG(_ctx, 8) -+ -+#define SECCOMP_NR_IDX (offsetof(struct arch_seccomp_data, nr)) -+#define SECCOMP_ARCH_IDX (offsetof(struct arch_seccomp_data, arch)) -+#define SECCOMP_IP_MSB_IDX \ -+ (offsetof(struct arch_seccomp_data, instruction_pointer) + 4) -+#define SECCOMP_IP_LSB_IDX \ -+ (offsetof(struct arch_seccomp_data, instruction_pointer) + 0) -+#define SECCOMP_ARG_MSB_IDX(nr) \ -+ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 4) -+#define SECCOMP_ARG_LSB_IDX(nr) \ -+ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 0) -+ -+#define SECCOMP_PT_RESULT(_regs) (_regs).gpr[3] -+#define SECCOMP_PT_SYSCALL(_regs) (_regs).gpr[0] -+#define SECCOMP_PT_IP(_regs) (_regs).nip -+#define SECCOMP_PT_PARM1(_regs) (_regs).gpr[3] -+#define SECCOMP_PT_PARM2(_regs) (_regs).gpr[4] -+#define SECCOMP_PT_PARM3(_regs) (_regs).gpr[5] -+#define SECCOMP_PT_PARM4(_regs) (_regs).gpr[6] -+#define SECCOMP_PT_PARM5(_regs) (_regs).gpr[7] -+#define SECCOMP_PT_PARM6(_regs) (_regs).gpr[8] -+ - #else - #error Unsupported target platform - -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc -index 712f9699a..55f062817 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc -@@ -88,7 +88,8 @@ bool IsBaselinePolicyWatched(int sysno) { - SyscallSets::IsPrctl(sysno) || - SyscallSets::IsProcessGroupOrSession(sysno) || - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - SyscallSets::IsSocketCall(sysno) || - #endif - #if defined(__arm__) -@@ -210,7 +211,7 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno, - } - - #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - if (sysno == __NR_mmap) - return RestrictMmapFlags(); - #endif -@@ -228,7 +229,7 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno, - return RestrictPrctl(); - - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - if (sysno == __NR_socketpair) { - // Only allow AF_UNIX, PF_UNIX. Crash if anything else is seen. - static_assert(AF_UNIX == PF_UNIX, -@@ -268,7 +269,8 @@ ResultExpr EvaluateSyscallImpl(int fs_denied_errno, - } - - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - if (SyscallSets::IsSocketCall(sysno)) - return RestrictSocketcallCommand(); - #endif -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy_unittest.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy_unittest.cc -index fc36187c9..1affc9189 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy_unittest.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy_unittest.cc -@@ -291,8 +291,10 @@ TEST_BASELINE_SIGSYS(__NR_timer_create) - #if !defined(__aarch64__) - TEST_BASELINE_SIGSYS(__NR_eventfd) - TEST_BASELINE_SIGSYS(__NR_inotify_init) -+#if !defined(__powerpc64__) - TEST_BASELINE_SIGSYS(__NR_vserver) - #endif -+#endif - - #if defined(LIBC_GLIBC) && !defined(OS_CHROMEOS) - BPF_TEST_C(BaselinePolicy, FutexEINVAL, BaselinePolicy) { -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc -index 002b07a25..f390f106a 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc -@@ -36,7 +36,8 @@ - #include - #include - #if defined(OS_LINUX) && !defined(OS_CHROMEOS) && !defined(__arm__) && \ -- !defined(__aarch64__) && !defined(PTRACE_GET_THREAD_AREA) -+ !defined(__aarch64__) && !defined(PTRACE_GET_THREAD_AREA) && \ -+ !defined(__powerpc64__) - // Also include asm/ptrace-abi.h since ptrace.h in older libc (for instance - // the one in Ubuntu 16.04 LTS) is missing PTRACE_GET_THREAD_AREA. - // asm/ptrace-abi.h doesn't exist on arm32 and PTRACE_GET_THREAD_AREA isn't -@@ -45,6 +46,11 @@ - #endif - #endif // !OS_NACL_NONSFI - -+// On PPC64, TCGETS is defined in terms of struct termios, so we must include termios.h -+#ifdef __powerpc64__ -+#include -+#endif -+ - #if defined(OS_ANDROID) - - #if !defined(F_DUPFD_CLOEXEC) -@@ -107,6 +113,15 @@ inline bool IsArchitectureMips() { - #endif - } - -+inline bool IsArchitecturePPC64() { -+#if defined(__powerpc64__) -+ return true; -+#else -+ return false; -+#endif -+} -+ -+ - // Ubuntu's version of glibc has a race condition in sem_post that can cause - // it to call futex(2) with bogus op arguments. To workaround this, we need - // to allow those futex(2) calls to fail with EINVAL, instead of crashing the -@@ -259,6 +274,8 @@ ResultExpr RestrictFcntlCommands() { - uint64_t kOLargeFileFlag = O_LARGEFILE; - if (IsArchitectureX86_64() || IsArchitectureI386() || IsArchitectureMips()) - kOLargeFileFlag = 0100000; -+ else if (IsArchitecturePPC64()) -+ kOLargeFileFlag = 0200000; - - const Arg cmd(1); - const Arg long_arg(2); -@@ -273,14 +290,23 @@ ResultExpr RestrictFcntlCommands() { - F_SETLKW, - F_GETLK, - F_DUPFD, -- F_DUPFD_CLOEXEC), -- Allow()) -+ F_DUPFD_CLOEXEC -+#if defined(__powerpc64__) -+// On PPC64, F_SETLK, F_GETLK, F_SETLKW are defined as the 64-bit variants -+// but glibc will sometimes still use the 32-bit versions. Allow both. -+ , -+ 5, /* F_GETLK (32) */ -+ 6, /* F_SETLK (32) */ -+ 7 /* F_SETLKW (32) */ -+#endif -+ ), -+ Allow()) - .Case(F_SETFL, - If((long_arg & ~kAllowedMask) == 0, Allow()).Else(CrashSIGSYS())) - .Default(CrashSIGSYS()); - } - --#if defined(__i386__) || defined(__mips__) -+#if defined(__i386__) || defined(__mips__) || defined(__powerpc64__) - ResultExpr RestrictSocketcallCommand() { - // Unfortunately, we are unable to restrict the first parameter to - // socketpair(2). Whilst initially sounding bad, it's noteworthy that very -@@ -429,7 +455,7 @@ ResultExpr RestrictPrlimitToGetrlimit(pid_t target_pid) { - ResultExpr RestrictPtrace() { - const Arg request(0); - return Switch(request).CASES(( --#if !defined(__aarch64__) -+#if !defined(__aarch64__) && !defined(__powerpc64__) - PTRACE_GETREGS, - PTRACE_GETFPREGS, - #if defined(TRACE_GET_THREAD_AREA) -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.h b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.h -index ba4289f05..9a4d5ab2d 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.h -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.h -@@ -48,7 +48,7 @@ SANDBOX_EXPORT bpf_dsl::ResultExpr RestrictMprotectFlags(); - // O_NONBLOCK | O_SYNC | O_LARGEFILE | O_CLOEXEC | O_NOATIME. - SANDBOX_EXPORT bpf_dsl::ResultExpr RestrictFcntlCommands(); - --#if defined(__i386__) || defined(__mips__) -+#if defined(__i386__) || defined(__mips__) || defined(__powerpc64__) - // Restrict socketcall(2) to only allow socketpair(2), send(2), recv(2), - // sendto(2), recvfrom(2), shutdown(2), sendmsg(2) and recvmsg(2). - SANDBOX_EXPORT bpf_dsl::ResultExpr RestrictSocketcallCommand(); -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc -index e16223a5e..8f37dd7dc 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc -@@ -29,7 +29,8 @@ bool SyscallSets::IsAllowedGettime(int sysno) { - switch (sysno) { - case __NR_gettimeofday: - #if defined(__i386__) || defined(__x86_64__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_time: - #endif - return true; -@@ -41,12 +42,14 @@ bool SyscallSets::IsAllowedGettime(int sysno) { - case __NR_clock_nanosleep: // Parameters filtered by RestrictClockID(). - case __NR_clock_settime: // Privileged. - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_ftime: // Obsolete. - #endif - case __NR_settimeofday: // Privileged. - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_stime: - #endif - default: -@@ -112,7 +115,7 @@ bool SyscallSets::IsFileSystem(int sysno) { - case __NR_faccessat: // EPERM not a valid errno. - case __NR_fchmodat: - case __NR_fchownat: // Should be called chownat ? --#if defined(__x86_64__) || defined(__aarch64__) -+#if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) - case __NR_newfstatat: // fstatat(). EPERM not a valid errno. - #elif defined(__i386__) || defined(__arm__) || \ - (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -@@ -131,7 +134,7 @@ bool SyscallSets::IsFileSystem(int sysno) { - case __NR_memfd_create: - case __NR_mkdirat: - case __NR_mknodat: --#if defined(__i386__) -+#if defined(__i386__) || defined(__powerpc64__) - case __NR_oldlstat: - case __NR_oldstat: - #endif -@@ -145,7 +148,8 @@ bool SyscallSets::IsFileSystem(int sysno) { - #endif - case __NR_statfs: // EPERM not a valid errno. - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_statfs64: - #endif - case __NR_symlinkat: -@@ -155,7 +159,8 @@ bool SyscallSets::IsFileSystem(int sysno) { - case __NR_truncate64: - #endif - case __NR_unlinkat: --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_utime: - #endif - case __NR_utimensat: // New. -@@ -174,7 +179,8 @@ bool SyscallSets::IsAllowedFileSystemAccessViaFd(int sysno) { - #endif - return true; - // TODO(jln): these should be denied gracefully as well (moved below). --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_fadvise64: // EPERM not a valid errno. - #endif - #if defined(__i386__) -@@ -187,11 +193,12 @@ bool SyscallSets::IsAllowedFileSystemAccessViaFd(int sysno) { - case __NR_flock: // EPERM not a valid errno. - case __NR_fstatfs: // Give information about the whole filesystem. - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_fstatfs64: - #endif - case __NR_fsync: // EPERM not a valid errno. --#if defined(__i386__) -+#if defined(__i386__) || defined(__powerpc64__) - case __NR_oldfstat: - #endif - #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -@@ -199,6 +206,8 @@ bool SyscallSets::IsAllowedFileSystemAccessViaFd(int sysno) { - case __NR_sync_file_range: // EPERM not a valid errno. - #elif defined(__arm__) - case __NR_arm_sync_file_range: // EPERM not a valid errno. -+#elif defined(__powerpc64__) -+ case __NR_sync_file_range2: // EPERM not a valid errno. - #endif - default: - return false; -@@ -224,7 +233,8 @@ bool SyscallSets::IsDeniedFileSystemAccessViaFd(int sysno) { - #endif - case __NR_getdents64: // EPERM not a valid errno. - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_readdir: - #endif - return true; -@@ -265,7 +275,7 @@ bool SyscallSets::IsGetSimpleId(int sysno) { - bool SyscallSets::IsProcessPrivilegeChange(int sysno) { - switch (sysno) { - case __NR_capset: --#if defined(__i386__) || defined(__x86_64__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc64__) - case __NR_ioperm: // Intel privilege. - case __NR_iopl: // Intel privilege. - #endif -@@ -316,7 +326,8 @@ bool SyscallSets::IsAllowedSignalHandling(int sysno) { - case __NR_rt_sigreturn: - case __NR_rt_sigtimedwait: - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_sigaction: - case __NR_sigprocmask: - case __NR_sigreturn: -@@ -332,7 +343,8 @@ bool SyscallSets::IsAllowedSignalHandling(int sysno) { - #endif - case __NR_signalfd4: - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_sigpending: - case __NR_sigsuspend: - #endif -@@ -356,7 +368,7 @@ bool SyscallSets::IsAllowedOperationOnFd(int sysno) { - #endif - case __NR_dup3: - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_shutdown: - #endif - return true; -@@ -390,7 +402,7 @@ bool SyscallSets::IsAllowedProcessStartOrDeath(int sysno) { - case __NR_membarrier: - case __NR_wait4: - case __NR_waitid: --#if defined(__i386__) -+#if defined(__i386__) || defined(__powerpc64__) - case __NR_waitpid: - #endif - #if !defined(__GLIBC__) -@@ -412,7 +424,7 @@ bool SyscallSets::IsAllowedProcessStartOrDeath(int sysno) { - case __NR_set_tid_address: - #endif - case __NR_unshare: --#if !defined(__mips__) && !defined(__aarch64__) -+#if !defined(__mips__) && !defined(__aarch64__) || defined(__powerpc64__) - case __NR_vfork: - #endif - default: -@@ -461,7 +473,7 @@ bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) { - return true; - default: - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_socketpair: // We will want to inspect its argument. - #endif - return false; -@@ -471,7 +483,7 @@ bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) { - bool SyscallSets::IsDeniedGetOrModifySocket(int sysno) { - switch (sysno) { - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_accept: - case __NR_accept4: - case __NR_bind: -@@ -486,7 +498,8 @@ bool SyscallSets::IsDeniedGetOrModifySocket(int sysno) { - } - - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - // Big multiplexing system call for sockets. - bool SyscallSets::IsSocketCall(int sysno) { - switch (sysno) { -@@ -500,7 +513,8 @@ bool SyscallSets::IsSocketCall(int sysno) { - } - #endif - --#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) -+#if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -+ defined(__powerpc64__) - bool SyscallSets::IsNetworkSocketInformation(int sysno) { - switch (sysno) { - case __NR_getpeername: -@@ -528,7 +542,7 @@ bool SyscallSets::IsAllowedAddressSpaceAccess(int sysno) { - case __NR_mincore: - case __NR_mlockall: - #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_mmap: - #endif - #if defined(__i386__) || defined(__arm__) || \ -@@ -560,7 +574,8 @@ bool SyscallSets::IsAllowedGeneralIo(int sysno) { - switch (sysno) { - case __NR_lseek: - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR__llseek: - #endif - #if !defined(__aarch64__) -@@ -572,26 +587,28 @@ bool SyscallSets::IsAllowedGeneralIo(int sysno) { - case __NR_readv: - case __NR_pread64: - #if defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_recv: - #endif - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_recvfrom: // Could specify source. - case __NR_recvmsg: // Could specify source. - #endif --#if defined(__i386__) || defined(__x86_64__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__powerpc64__) - case __NR_select: - #endif --#if defined(__i386__) || defined(__arm__) || defined(__mips__) -+#if defined(__i386__) || defined(__arm__) || defined(__mips__) || defined(__powerpc64__) - case __NR__newselect: - #endif - #if defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_send: - #endif - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_sendmsg: // Could specify destination. - case __NR_sendto: // Could specify destination. - #endif -@@ -648,7 +665,8 @@ bool SyscallSets::IsAllowedBasicScheduler(int sysno) { - return true; - case __NR_getpriority: - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_nice: - #endif - case __NR_setpriority: -@@ -660,7 +678,8 @@ bool SyscallSets::IsAllowedBasicScheduler(int sysno) { - bool SyscallSets::IsAdminOperation(int sysno) { - switch (sysno) { - #if defined(__i386__) || defined(__arm__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_bdflush: - #endif - case __NR_kexec_load: -@@ -676,7 +695,8 @@ bool SyscallSets::IsAdminOperation(int sysno) { - - bool SyscallSets::IsKernelModule(int sysno) { - switch (sysno) { --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_create_module: - case __NR_get_kernel_syms: // Should ENOSYS. - case __NR_query_module: -@@ -709,7 +729,8 @@ bool SyscallSets::IsFsControl(int sysno) { - case __NR_swapoff: - case __NR_swapon: - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_umount: - #endif - case __NR_umount2: -@@ -725,7 +746,7 @@ bool SyscallSets::IsNuma(int sysno) { - case __NR_getcpu: - case __NR_mbind: - #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_migrate_pages: - #endif - case __NR_move_pages: -@@ -754,14 +775,15 @@ bool SyscallSets::IsGlobalProcessEnvironment(int sysno) { - switch (sysno) { - case __NR_acct: // Privileged. - #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - case __NR_getrlimit: - #endif --#if defined(__i386__) || defined(__arm__) -+#if defined(__i386__) || defined(__arm__) || defined(__powerpc64__) - case __NR_ugetrlimit: - #endif - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_ulimit: - #endif - case __NR_getrusage: -@@ -795,7 +817,7 @@ bool SyscallSets::IsGlobalSystemStatus(int sysno) { - #endif - case __NR_sysinfo: - case __NR_uname: --#if defined(__i386__) -+#if defined(__i386__) || defined(__powerpc64__) - case __NR_olduname: - case __NR_oldolduname: - #endif -@@ -890,7 +912,8 @@ bool SyscallSets::IsSystemVMessageQueue(int sysno) { - #endif - - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - // Big system V multiplexing system call. - bool SyscallSets::IsSystemVIpc(int sysno) { - switch (sysno) { -@@ -910,7 +933,8 @@ bool SyscallSets::IsAnySystemV(int sysno) { - return IsSystemVMessageQueue(sysno) || IsSystemVSemaphores(sysno) || - IsSystemVSharedMemory(sysno); - #elif defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - return IsSystemVIpc(sysno); - #endif - } -@@ -963,7 +987,8 @@ bool SyscallSets::IsFaNotify(int sysno) { - bool SyscallSets::IsTimer(int sysno) { - switch (sysno) { - case __NR_getitimer: --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_alarm: - #endif - case __NR_setitimer: -@@ -1022,18 +1047,22 @@ bool SyscallSets::IsMisc(int sysno) { - case __NR_syncfs: - case __NR_vhangup: - // The system calls below are not implemented. --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_afs_syscall: - #endif - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_break: - #endif --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_getpmsg: - #endif - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_gtty: - case __NR_idle: - case __NR_lock: -@@ -1041,20 +1070,22 @@ bool SyscallSets::IsMisc(int sysno) { - case __NR_prof: - case __NR_profil: - #endif --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ -+ defined(__powerpc64__) - case __NR_putpmsg: - #endif - #if defined(__x86_64__) - case __NR_security: - #endif - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - case __NR_stty: - #endif --#if defined(__x86_64__) -+#if defined(__x86_64__) || defined(__powerpc64__) - case __NR_tuxcall: - #endif --#if !defined(__aarch64__) -+#if !defined(__aarch64__) && !defined(__powerpc64__) - case __NR_vserver: - #endif - return true; -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h -index 923533ec9..e2bb1db98 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h -@@ -43,13 +43,14 @@ class SANDBOX_EXPORT SyscallSets { - static bool IsDeniedGetOrModifySocket(int sysno); - - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - // Big multiplexing system call for sockets. - static bool IsSocketCall(int sysno); - #endif - - #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - static bool IsNetworkSocketInformation(int sysno); - #endif - -@@ -88,7 +89,8 @@ class SANDBOX_EXPORT SyscallSets { - #endif - - #if defined(__i386__) || \ -- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) -+ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) || \ -+ defined(__powerpc64__) - // Big system V multiplexing system call. - static bool IsSystemVIpc(int sysno); - #endif -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -index 34edabd2b..10fa5fd07 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -@@ -16,7 +16,7 @@ namespace sandbox { - namespace { - - #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ -- defined(ARCH_CPU_MIPS_FAMILY) -+ defined(ARCH_CPU_MIPS_FAMILY) || defined (ARCH_CPU_PPC64_FAMILY) - // Number that's not currently used by any Linux kernel ABIs. - const int kInvalidSyscallNumber = 0x351d3; - #else -@@ -308,12 +308,56 @@ asm(// We need to be able to tell the kernel exactly where we made a - // Enter the kernel - "svc 0\n" - "2:ret\n" -+ ".cfi_endproc\n" -+ ".size SyscallAsm, .-SyscallAsm\n" -+#elif defined(__powerpc64__) -+ ".text\n" -+ ".align 4\n" -+ ".type SyscallAsm @function\n" -+ "SyscallAsm:\n" -+ ".cfi_startproc\n" -+ -+ // Check if r3 is negative -+ "cmpdi 3, 0\n" -+ "bgt 2f\n" -+ -+ // Load address of 3f into r3 and return -+ "mflr 10\n" -+ "bl 1f\n" -+ "1: mflr 3\n" -+ "mtlr 10\n" -+ "addi 3, 3, 4*13\n" -+ "blr\n" -+ -+ // Load arguments from array into r3-8 -+ // save param 3 in r10 -+ "2:\n" -+ "mr 0, 3\n" -+ "ld 3, 0(4)\n" -+ "ld 5, 16(4)\n" -+ "ld 6, 24(4)\n" -+ "ld 7, 32(4)\n" -+ "ld 8, 40(4)\n" -+ "ld 4, 8(4)\n" -+ "li 9, 0\n" -+ -+ // Enter kernel -+ "sc\n" -+ -+ // Magic return address -+ "3:\n" -+ // Like MIPS, ppc64 return values are always positive. -+ // Check for error in cr0.SO and negate upon error -+ "bc 4, 3, 4f\n" -+ "neg 3, 3\n" -+ "4: blr\n" -+ - ".cfi_endproc\n" - ".size SyscallAsm, .-SyscallAsm\n" - #endif - ); // asm - --#if defined(__x86_64__) -+#if defined(__x86_64__) || defined(__powerpc64__) - extern "C" { - intptr_t SyscallAsm(intptr_t nr, const intptr_t args[6]); - } -@@ -427,6 +471,8 @@ intptr_t Syscall::Call(int nr, - ret = inout; - } - -+#elif defined(__powerpc64__) -+ intptr_t ret = SyscallAsm(nr, args); - #else - #error "Unimplemented architecture" - #endif -@@ -443,8 +489,18 @@ void Syscall::PutValueInUcontext(intptr_t ret_val, ucontext_t* ctx) { - // needs to be changed back. - ret_val = -ret_val; - SECCOMP_PARM4(ctx) = 1; -- } else -+ } else { - SECCOMP_PARM4(ctx) = 0; -+ } -+#endif -+#if defined(__powerpc64__) -+ // Same as MIPS, need to invert ret and set error register (cr0.SO) -+ if (ret_val <= -1 && ret_val >= -4095) { -+ ret_val = -ret_val; -+ ctx->uc_mcontext.regs->ccr |= (1 << 28); -+ } else { -+ ctx->uc_mcontext.regs->ccr &= ~(1 << 28); -+ } - #endif - SECCOMP_RESULT(ctx) = static_cast(ret_val); - } -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/trap.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/trap.cc -index 663d9e896..f55e03ed5 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/trap.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/trap.cc -@@ -237,6 +237,20 @@ void Trap::SigSys(int nr, LinuxSigInfo* info, ucontext_t* ctx) { - SetIsInSigHandler(); - } - -+#if defined(__powerpc64__) -+ // On ppc64+glibc, some syscalls seem to accidentally negate the first -+ // parameter which causes checks against it to fail. For now, manually -+ // negate them back. -+ // TODO(shawn@anastas.io): investigate this issue further -+ auto nr = SECCOMP_SYSCALL(ctx); -+ if (nr == __NR_openat || nr == __NR_mkdirat || nr == __NR_faccessat || nr == __NR_readlinkat || -+ nr == __NR_renameat || nr == __NR_renameat2 || nr == __NR_newfstatat || nr == __NR_unlinkat) { -+ if (static_cast(SECCOMP_PARM1(ctx)) > 0) { -+ SECCOMP_PARM1(ctx) = -SECCOMP_PARM1(ctx); -+ } -+ } -+#endif -+ - // Copy the seccomp-specific data into a arch_seccomp_data structure. This - // is what we are showing to TrapFnc callbacks that the system call - // evaluator registered with the sandbox. -diff --git a/src/3rdparty/chromium/sandbox/linux/services/credentials.cc b/src/3rdparty/chromium/sandbox/linux/services/credentials.cc -index d7b5d8c44..4adc6d0d4 100644 ---- a/src/3rdparty/chromium/sandbox/linux/services/credentials.cc -+++ b/src/3rdparty/chromium/sandbox/linux/services/credentials.cc -@@ -81,7 +81,7 @@ bool ChrootToSafeEmptyDir() { - pid_t pid = -1; - alignas(16) char stack_buf[PTHREAD_STACK_MIN]; - #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ -- defined(ARCH_CPU_MIPS_FAMILY) -+ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_PPC64_FAMILY) - // The stack grows downward. - void* stack = stack_buf + sizeof(stack_buf); - #else -diff --git a/src/3rdparty/chromium/sandbox/linux/services/syscall_wrappers.cc b/src/3rdparty/chromium/sandbox/linux/services/syscall_wrappers.cc -index fcfd2aa12..f6eb32fb7 100644 ---- a/src/3rdparty/chromium/sandbox/linux/services/syscall_wrappers.cc -+++ b/src/3rdparty/chromium/sandbox/linux/services/syscall_wrappers.cc -@@ -58,7 +58,7 @@ long sys_clone(unsigned long flags, - #if defined(ARCH_CPU_X86_64) - return syscall(__NR_clone, flags, child_stack, ptid, ctid, tls); - #elif defined(ARCH_CPU_X86) || defined(ARCH_CPU_ARM_FAMILY) || \ -- defined(ARCH_CPU_MIPS_FAMILY) -+ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_PPC64_FAMILY) - // CONFIG_CLONE_BACKWARDS defined. - return syscall(__NR_clone, flags, child_stack, ptid, tls, ctid); - #endif -diff --git a/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc b/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc -index 8321d2379..7e5ad1de3 100644 ---- a/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc -+++ b/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc -@@ -157,7 +157,7 @@ bool BrokerProcess::IsSyscallAllowed(int sysno) const { - #if defined(__NR_fstatat) - case __NR_fstatat: - #endif --#if defined(__x86_64__) || defined(__aarch64__) -+#if defined(__x86_64__) || defined(__aarch64__) || defined(__powerpc64__) - case __NR_newfstatat: - #endif - return !fast_check_in_client_ || allowed_command_set_.test(COMMAND_STAT); -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h -index a60fe2ad3..9dccdb51d 100644 ---- a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h -@@ -29,6 +29,9 @@ - #ifndef EM_AARCH64 - #define EM_AARCH64 183 - #endif -+#ifndef EM_PPC64 -+#define EM_PPC64 21 -+#endif - - #ifndef __AUDIT_ARCH_64BIT - #define __AUDIT_ARCH_64BIT 0x80000000 -@@ -54,6 +57,12 @@ - #ifndef AUDIT_ARCH_AARCH64 - #define AUDIT_ARCH_AARCH64 (EM_AARCH64 | __AUDIT_ARCH_64BIT | __AUDIT_ARCH_LE) - #endif -+#ifndef AUDIT_ARCH_PPC64 -+#define AUDIT_ARCH_PPC64 (EM_PPC64 | __AUDIT_ARCH_64BIT) -+#endif -+#ifndef AUDIT_ARCH_PPC64LE -+#define AUDIT_ARCH_PPC64LE (EM_PPC64 | __AUDIT_ARCH_64BIT | __AUDIT_ARCH_LE) -+#endif - - // For prctl.h - #ifndef PR_SET_SECCOMP -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h -index f5a736761..515b21a5f 100644 ---- a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h -@@ -13,7 +13,7 @@ - // (not undefined, but defined different values and in different memory - // layouts). So, fill the gap here. - #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ -- defined(__aarch64__) -+ defined(__aarch64__) || defined(__powerpc64__) - - #define LINUX_SIGHUP 1 - #define LINUX_SIGINT 2 -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h -index 2b78a0cc3..0a70f5ea5 100644 ---- a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h -@@ -35,5 +35,9 @@ - #include "sandbox/linux/system_headers/arm64_linux_syscalls.h" - #endif - -+#if defined(__powerpc64__) -+#include "sandbox/linux/system_headers/ppc64_linux_syscalls.h" -+#endif -+ - #endif // SANDBOX_LINUX_SYSTEM_HEADERS_LINUX_SYSCALLS_H_ - -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_ucontext.h b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_ucontext.h -index 22ce78027..a69b024c2 100644 ---- a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_ucontext.h -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_ucontext.h -@@ -11,6 +11,8 @@ - #include "sandbox/linux/system_headers/arm_linux_ucontext.h" - #elif defined(__i386__) - #include "sandbox/linux/system_headers/i386_linux_ucontext.h" -+#elif defined(__powerpc64__) -+#include "sandbox/linux/system_headers/ppc64_linux_ucontext.h" - #else - #error "No support for your architecture in PNaCl header" - #endif -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_syscalls.h b/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_syscalls.h -new file mode 100644 -index 000000000..ccacffe22 ---- /dev/null -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_syscalls.h -@@ -0,0 +1,12 @@ -+// Copyright 2014 The Chromium Authors. All rights reserved. -+// Use of this source code is governed by a BSD-style license that can be -+// found in the LICENSE file. -+ -+#ifndef SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_SYSCALLS_H_ -+#define SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_SYSCALLS_H_ -+ -+#include -+ -+//TODO: is it necessary to redefine syscall numbers for PPC64? -+ -+#endif // SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_SYSCALLS_H_ -diff --git a/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_ucontext.h b/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_ucontext.h -new file mode 100644 -index 000000000..07728e087 ---- /dev/null -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/ppc64_linux_ucontext.h -@@ -0,0 +1,12 @@ -+// Copyright 2014 The Chromium Authors. All rights reserved. -+// Use of this source code is governed by a BSD-style license that can be -+// found in the LICENSE file. -+ -+#ifndef SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_UCONTEXT_H_ -+#define SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_UCONTEXT_H_ -+ -+#include -+ -+//TODO: is it necessary to redefine ucontext on PPC64? -+ -+#endif // SANDBOX_LINUX_SYSTEM_HEADERS_PPC64_LINUX_UCONTEXT_H_ -diff --git a/src/3rdparty/chromium/sandbox/policy/linux/bpf_renderer_policy_linux.cc b/src/3rdparty/chromium/sandbox/policy/linux/bpf_renderer_policy_linux.cc -index 443e9114b..6df5678d6 100644 ---- a/src/3rdparty/chromium/sandbox/policy/linux/bpf_renderer_policy_linux.cc -+++ b/src/3rdparty/chromium/sandbox/policy/linux/bpf_renderer_policy_linux.cc -@@ -15,6 +15,11 @@ - #include "sandbox/linux/system_headers/linux_syscalls.h" - #include "services/service_manager/sandbox/linux/sandbox_linux.h" - -+// On PPC64, TCGETS is defined in terms of struct termios, so we must include termios.h -+#ifdef __powerpc64__ -+#include -+#endif -+ - // TODO(vignatti): replace the local definitions below with #include - // once kernel version 4.6 becomes widely used. - #include -diff --git a/src/3rdparty/chromium/third_party/angle/src/compiler/translator/InfoSink.h b/src/3rdparty/chromium/third_party/angle/src/compiler/translator/InfoSink.h -index 3a807e1e3..5258617a7 100644 ---- a/src/3rdparty/chromium/third_party/angle/src/compiler/translator/InfoSink.h -+++ b/src/3rdparty/chromium/third_party/angle/src/compiler/translator/InfoSink.h -@@ -92,7 +92,16 @@ class TInfoSinkBase - stream.precision(8); - stream << f; - } -- sink.append(stream.str()); -+ -+ // Hack to work around a bug where negative floating point values -+ // are rendered like '.0.5' instead of '-0.5' -+ std::string res(stream.str()); -+ -+ if (signbit(f)) { // test if f is negative -+ res[0] = '-'; -+ } -+ -+ sink.append(res); - return *this; - } - // Write boolean values as their names instead of integral value. -diff --git a/src/3rdparty/chromium/third_party/angle/src/libANGLE/Constants.h b/src/3rdparty/chromium/third_party/angle/src/libANGLE/Constants.h -index 746789913..9132b3fc0 100644 ---- a/src/3rdparty/chromium/third_party/angle/src/libANGLE/Constants.h -+++ b/src/3rdparty/chromium/third_party/angle/src/libANGLE/Constants.h -@@ -9,6 +9,7 @@ - #ifndef LIBANGLE_CONSTANTS_H_ - #define LIBANGLE_CONSTANTS_H_ - -+#include - #include "common/platform.h" - - #include -diff --git a/src/3rdparty/chromium/third_party/boringssl/BUILD.gn b/src/3rdparty/chromium/third_party/boringssl/BUILD.gn -index b435499f4..ac8a84b6d 100644 ---- a/src/3rdparty/chromium/third_party/boringssl/BUILD.gn -+++ b/src/3rdparty/chromium/third_party/boringssl/BUILD.gn -@@ -101,6 +101,13 @@ if (is_win && !is_msan && current_cpu != "arm64") { - } else { - public_configs = [ ":no_asm_config" ] - } -+ } else if (current_cpu == "ppc64") { -+ if (is_linux) { -+ # TODO: ppc64 (be) check -+ sources += crypto_sources_linux_ppc64le -+ } else { -+ public_configs = [ ":no_asm_config" ] -+ } - } else { - public_configs = [ ":no_asm_config" ] - } -diff --git a/src/3rdparty/chromium/third_party/breakpad/BUILD.gn b/src/3rdparty/chromium/third_party/breakpad/BUILD.gn -index 5617de88..dc8bc176 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/BUILD.gn -+++ b/src/3rdparty/chromium/third_party/breakpad/BUILD.gn -@@ -598,7 +598,6 @@ if (is_linux || is_android) { - "breakpad/src/client/minidump_file_writer.h", - "breakpad/src/common/convert_UTF.cc", - "breakpad/src/common/convert_UTF.h", -- "breakpad/src/common/linux/breakpad_getcontext.S", - "breakpad/src/common/linux/elf_core_dump.cc", - "breakpad/src/common/linux/elf_core_dump.h", - "breakpad/src/common/linux/elfutils.cc", -@@ -636,6 +635,15 @@ if (is_linux || is_android) { - - libs = [ "dl" ] - -+ if (current_cpu == "ppc64") { -+ defines = [ "HAVE_GETCONTEXT" ] -+ #libs += [ "ucontext" ] -+ } else { -+ sources += [ -+ "breakpad/src/common/linux/breakpad_getcontext.S" -+ ] -+ } -+ - include_dirs = [ - ".", - "breakpad/src", -@@ -686,7 +693,6 @@ if (is_linux || is_android) { - "breakpad/src/client/linux/minidump_writer/minidump_writer_unittest.cc", - "breakpad/src/client/linux/minidump_writer/minidump_writer_unittest_utils.cc", - "breakpad/src/client/linux/minidump_writer/proc_cpuinfo_reader_unittest.cc", -- "breakpad/src/common/linux/breakpad_getcontext_unittest.cc", - "breakpad/src/common/linux/elf_core_dump_unittest.cc", - "breakpad/src/common/linux/file_id_unittest.cc", - "breakpad/src/common/linux/linux_libc_support_unittest.cc", -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h -index 07d9171a0..9aed4cb36 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h -@@ -44,6 +44,8 @@ typedef MDRawContextARM RawContextCPU; - typedef MDRawContextARM64_Old RawContextCPU; - #elif defined(__mips__) - typedef MDRawContextMIPS RawContextCPU; -+#elif defined(__powerpc64__) -+typedef MDRawContextPPC64 RawContextCPU; - #else - #error "This code has not been ported to your platform yet." - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -index aae1dc13b..03afec7a5 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -@@ -270,7 +270,42 @@ void ThreadInfo::FillCPUContext(RawContextCPU* out) const { - out->float_save.fir = mcontext.fpc_eir; - #endif - } --#endif // __mips__ -+ -+#elif defined(__powerpc64__) -+ -+uintptr_t ThreadInfo::GetInstructionPointer() const { -+ return mcontext.gp_regs[PT_NIP]; -+} -+ -+void ThreadInfo::FillCPUContext(RawContextCPU* out) const { -+ out->context_flags = MD_CONTEXT_PPC64_FULL; -+ for (int i = 0; i < MD_CONTEXT_PPC64_GPR_COUNT; i++) -+ out->gpr[i] = mcontext.gp_regs[i]; -+ -+ out->lr = mcontext.gp_regs[PT_LNK]; -+ out->srr0 = mcontext.gp_regs[PT_NIP]; -+ out->srr1 = mcontext.gp_regs[PT_MSR]; -+ out->cr = mcontext.gp_regs[PT_CCR]; -+ out->xer = mcontext.gp_regs[PT_XER]; -+ out->ctr = mcontext.gp_regs[PT_CTR]; -+ -+ for (int i = 0; i < MD_FLOATINGSAVEAREA_PPC_FPR_COUNT; i++) -+ out->float_save.fpregs[i] = mcontext.fp_regs[i]; -+ -+ out->float_save.fpscr = mcontext.fp_regs[NFPREG-1]; -+ -+ for (int i = 0; i < MD_VECTORSAVEAREA_PPC_VR_COUNT; i++) -+ out->vector_save.save_vr[i] = \ -+ {(((uint64_t)vregs.vrregs[i][0]) << 32) -+ | vregs.vrregs[i][1], -+ (((uint64_t)vregs.vrregs[i][2]) << 32) -+ | vregs.vrregs[i][3]}; -+ -+ out->vrsave = vregs.vrsave; -+ out->vector_save.save_vscr = {0, vregs.vscr.vscr_word}; -+ out->vector_save.save_vrvalid = 0xFFFFFFFF; -+} -+#endif // __powerpc64__ - - void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) { - assert(gp_regs || size); -@@ -279,6 +314,11 @@ void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) { - *gp_regs = mcontext.gregs; - if (size) - *size = sizeof(mcontext.gregs); -+#elif defined(__powerpc64__) -+ if (gp_regs) -+ *gp_regs = mcontext.gp_regs; -+ if (size) -+ *size = sizeof(mcontext.gp_regs); - #else - if (gp_regs) - *gp_regs = ®s; -@@ -294,6 +334,11 @@ void ThreadInfo::GetFloatingPointRegisters(void** fp_regs, size_t* size) { - *fp_regs = &mcontext.fpregs; - if (size) - *size = sizeof(mcontext.fpregs); -+#elif defined(__powerpc64__) -+ if (fp_regs) -+ *fp_regs = &mcontext.fp_regs; -+ if (size) -+ *size = sizeof(mcontext.fp_regs); - #else - if (fp_regs) - *fp_regs = &fpregs; -@@ -302,4 +347,13 @@ void ThreadInfo::GetFloatingPointRegisters(void** fp_regs, size_t* size) { - #endif - } - -+#if defined(__powerpc64__) -+void ThreadInfo::GetVectorRegisters(void** v_regs, size_t* size) { -+ if (v_regs) -+ *v_regs = &vregs; -+ if (size) -+ *size = sizeof(vregs); -+} -+#endif -+ - } // namespace google_breakpad -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h -index fb216fa6d..593aac822 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h -@@ -68,6 +68,10 @@ struct ThreadInfo { - // Use the structures defined in - struct user_regs_struct regs; - struct user_fpsimd_struct fpregs; -+#elif defined(__powerpc64__) -+ // Use the structures defined in . -+ mcontext_t mcontext; -+ vrregset_t vregs; - #elif defined(__mips__) - // Use the structure defined in . - mcontext_t mcontext; -@@ -84,6 +88,11 @@ struct ThreadInfo { - - // Returns the pointer and size of float point register area. - void GetFloatingPointRegisters(void** fp_regs, size_t* size); -+ -+#if defined(__powerpc64__) -+ // Returns the pointer and size of the vector register area. (PPC64 only) -+ void GetVectorRegisters(void** v_regs, size_t* size); -+#endif - }; - - } // namespace google_breakpad -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -index a8f9ccc72..7620cf6f7 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -@@ -254,6 +254,48 @@ void UContextReader::FillCPUContext(RawContextCPU *out, const ucontext_t *uc) { - out->float_save.fir = uc->uc_mcontext.fpc_eir; // Unused. - #endif - } -+ -+#elif defined(__powerpc64__) -+ -+uintptr_t UContextReader::GetStackPointer(const ucontext_t* uc) { -+ return uc->uc_mcontext.gp_regs[MD_CONTEXT_PPC64_REG_SP]; -+} -+ -+uintptr_t UContextReader::GetInstructionPointer(const ucontext_t* uc) { -+ return uc->uc_mcontext.gp_regs[PT_NIP]; -+} -+ -+void UContextReader::FillCPUContext(RawContextCPU* out, const ucontext_t* uc, -+ const vrregset_t* vregs) { -+ out->context_flags = MD_CONTEXT_PPC64_FULL; -+ -+ for (int i = 0; i < MD_CONTEXT_PPC64_GPR_COUNT; i++) -+ out->gpr[i] = uc->uc_mcontext.gp_regs[i]; -+ -+ out->lr = uc->uc_mcontext.gp_regs[PT_LNK]; -+ out->srr0 = uc->uc_mcontext.gp_regs[PT_NIP]; -+ out->srr1 = uc->uc_mcontext.gp_regs[PT_MSR]; -+ out->cr = uc->uc_mcontext.gp_regs[PT_CCR]; -+ out->xer = uc->uc_mcontext.gp_regs[PT_XER]; -+ out->ctr = uc->uc_mcontext.gp_regs[PT_CTR]; -+ -+ for (int i = 0; i < MD_FLOATINGSAVEAREA_PPC_FPR_COUNT; i++) -+ out->float_save.fpregs[i] = uc->uc_mcontext.fp_regs[i]; -+ -+ out->float_save.fpscr = uc->uc_mcontext.fp_regs[NFPREG-1]; -+ -+ for (int i = 0; i < MD_VECTORSAVEAREA_PPC_VR_COUNT; i++) -+ out->vector_save.save_vr[i] = -+ {(((uint64_t)vregs->vrregs[i][0]) << 32) -+ | vregs->vrregs[i][1], -+ (((uint64_t)vregs->vrregs[i][2]) << 32) -+ | vregs->vrregs[i][3]}; -+ -+ out->vrsave = vregs->vrsave; -+ out->vector_save.save_vscr = {0, vregs->vscr.vscr_word}; -+ out->vector_save.save_vrvalid = 0xFFFFFFFF; -+} -+ - #endif - - } // namespace google_breakpad -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.h -index f3dde1f4d..96079169d 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.h -@@ -54,6 +54,9 @@ struct UContextReader { - #elif defined(__aarch64__) - static void FillCPUContext(RawContextCPU *out, const ucontext_t *uc, - const struct fpsimd_context* fpregs); -+#elif defined(__powerpc64__) -+ static void FillCPUContext(RawContextCPU *out, const ucontext_t *uc, -+ const vrregset_t* vregs); - #else - static void FillCPUContext(RawContextCPU *out, const ucontext_t *uc); - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -index b895f6d7a..901cd68fb 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -@@ -461,9 +461,16 @@ bool ExceptionHandler::HandleSignal(int /*sig*/, siginfo_t* info, void* uc) { - memcpy(&g_crash_context_.float_state, fp_ptr, - sizeof(g_crash_context_.float_state)); - } -+#elif defined(__powerpc64__) -+ // On PPC64, we must copy VR state -+ ucontext_t* uc_ptr = (ucontext_t*)uc; -+ if (uc_ptr->uc_mcontext.v_regs) { -+ memcpy(&g_crash_context_.vector_state, uc_ptr->uc_mcontext.v_regs, -+ sizeof(g_crash_context_.vector_state)); -+ } - #elif !defined(__ARM_EABI__) && !defined(__mips__) - // FP state is not part of user ABI on ARM Linux. -- // In case of MIPS Linux FP state is already part of ucontext_t -+ // In case of MIPS, Linux FP state is already part of ucontext_t - // and 'float_state' is not a member of CrashContext. - ucontext_t* uc_ptr = (ucontext_t*)uc; - if (uc_ptr->uc_mcontext.fpregs) { -@@ -701,11 +708,19 @@ bool ExceptionHandler::WriteMinidump() { - } - #endif - --#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) -+#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) \ -+ && !defined(__powerpc64__) - // FPU state is not part of ARM EABI ucontext_t. - memcpy(&context.float_state, context.context.uc_mcontext.fpregs, - sizeof(context.float_state)); - #endif -+ -+#if defined(__powerpc64__) -+ // Vector registers must be copied on PPC64 -+ memcpy(&context.vector_state, context.context.uc_mcontext.v_regs, -+ sizeof(context.vector_state)); -+#endif -+ - context.tid = sys_gettid(); - - // Add an exception stream to the minidump for better reporting. -@@ -726,6 +741,9 @@ bool ExceptionHandler::WriteMinidump() { - #elif defined(__mips__) - context.siginfo.si_addr = - reinterpret_cast(context.context.uc_mcontext.pc); -+#elif defined(__powerpc64__) -+ context.siginfo.si_addr = -+ reinterpret_cast(context.context.uc_mcontext.gp_regs[PT_NIP]); - #else - #error "This code has not been ported to your platform yet." - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h -index f44483ff0..36ce6d6ce 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h -@@ -192,7 +192,11 @@ class ExceptionHandler { - siginfo_t siginfo; - pid_t tid; // the crashing thread. - ucontext_t context; --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ // PPC64's FP state is a part of ucontext_t like MIPS but the vector -+ // state is not, so a struct is needed. -+ vstate_t vector_state; -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - // #ifdef this out because FP state is not part of user ABI for Linux ARM. - // In case of MIPS Linux FP state is already part of ucontext_t so - // 'float_state' is not required. -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler_unittest.cc -index bcbf9c26f..2c36ed41f 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler_unittest.cc -@@ -307,7 +307,7 @@ TEST(ExceptionHandlerTest, ParallelChildCrashesDontHang) { - } - - // Wait a while until the child should have crashed. -- usleep(1000000); -+ usleep(2000000); - // Kill the child if it is still running. - kill(child, SIGKILL); - -@@ -559,6 +559,8 @@ const unsigned char kIllegalInstruction[] = { - #if defined(__mips__) - // mfc2 zero,Impl - usually illegal in userspace. - 0x48, 0x00, 0x00, 0x48 -+#elif defined(__powerpc64__) -+ 0x01, 0x01, 0x01, 0x01 // Crashes on a tested POWER9 cpu - #else - // This crashes with SIGILL on x86/x86-64/arm. - 0xff, 0xff, 0xff, 0xff -@@ -754,10 +756,10 @@ TEST(ExceptionHandlerTest, InstructionPointerMemoryMaxBound) { - - // These are defined here so the parent can use them to check the - // data from the minidump afterwards. -- // Use 4k here because the OS will hand out a single page even -+ // Use the page size here because the OS will hand out a single page even - // if a smaller size is requested, and this test wants to - // test the upper bound of the memory range. -- const uint32_t kMemorySize = 4096; // bytes -+ const uint32_t kMemorySize = getpagesize(); // bytes - const int kOffset = kMemorySize - sizeof(kIllegalInstruction); - - const pid_t child = fork(); -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc -index fa3c1713a..6ce709e2f 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc -@@ -138,7 +138,9 @@ class MicrodumpWriter { - const MicrodumpExtraInfo& microdump_extra_info, - LinuxDumper* dumper) - : ucontext_(context ? &context->context : NULL), --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ vector_state_(context ? &context->vector_state : NULL), -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - float_state_(context ? &context->float_state : NULL), - #endif - dumper_(dumper), -@@ -337,6 +339,8 @@ class MicrodumpWriter { - # else - # error "This mips ABI is currently not supported (n32)" - #endif -+#elif defined(__powerpc64__) -+ const char kArch[] = "ppc64"; - #else - #error "This code has not been ported to your platform yet" - #endif -@@ -409,7 +413,9 @@ class MicrodumpWriter { - void DumpCPUState() { - RawContextCPU cpu; - my_memset(&cpu, 0, sizeof(RawContextCPU)); --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ UContextReader::FillCPUContext(&cpu, ucontext_, vector_state_); -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - UContextReader::FillCPUContext(&cpu, ucontext_, float_state_); - #else - UContextReader::FillCPUContext(&cpu, ucontext_); -@@ -605,7 +611,9 @@ class MicrodumpWriter { - void* Alloc(unsigned bytes) { return dumper_->allocator()->Alloc(bytes); } - - const ucontext_t* const ucontext_; --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ const google_breakpad::vstate_t* const vector_state_; -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - const google_breakpad::fpstate_t* const float_state_; - #endif - LinuxDumper* dumper_; -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer_unittest.cc -index c2fea0225..8c62c524a 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer_unittest.cc -@@ -278,10 +278,19 @@ TEST(MicrodumpWriterTest, BasicWithMappings) { - CrashAndGetMicrodump(mappings, MicrodumpExtraInfo(), &buf); - ASSERT_TRUE(ContainsMicrodump(buf)); - -+ int page_size = getpagesize(); - #ifdef __LP64__ -- ASSERT_NE(std::string::npos, -- buf.find("M 0000000000001000 000000000000002A 0000000000001000 " -- "33221100554477668899AABBCCDDEEFF0 libfoo.so")); -+ // This test is only available for the following page sizes -+ ASSERT_TRUE((page_size == 4096) || (page_size == 65536)); -+ if (page_size == 4096) { -+ ASSERT_NE(std::string::npos, -+ buf.find("M 0000000000001000 000000000000002A 0000000000001000 " -+ "33221100554477668899AABBCCDDEEFF0 libfoo.so")); -+ } else { -+ ASSERT_NE(std::string::npos, -+ buf.find("M 0000000000010000 000000000000002A 0000000000010000 " -+ "33221100554477668899AABBCCDDEEFF0 libfoo.so")); -+ } - #else - ASSERT_NE(std::string::npos, - buf.find("M 00001000 0000002A 00001000 " -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc -index 4756a5416..4805fb694 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc -@@ -117,6 +117,9 @@ bool LinuxCoreDumper::GetThreadInfoByIndex(size_t index, ThreadInfo* info) { - #elif defined(__mips__) - stack_pointer = - reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); -+#elif defined(__powerpc64__) -+ stack_pointer = -+ reinterpret_cast(info->mcontext.gp_regs[MD_CONTEXT_PPC64_REG_SP]); - #else - #error "This code hasn't been ported to your platform yet." - #endif -@@ -202,7 +205,10 @@ bool LinuxCoreDumper::EnumerateThreads() { - memset(&info, 0, sizeof(ThreadInfo)); - info.tgid = status->pr_pgrp; - info.ppid = status->pr_ppid; --#if defined(__mips__) -+#if defined(__powerpc64__) -+ for (int i = 0; i < 31; i++) -+ info.mcontext.gp_regs[i] = status->pr_reg[i]; -+#elif defined(__mips__) - #if defined(__ANDROID__) - for (int i = EF_R0; i <= EF_R31; i++) - info.mcontext.gregs[i - EF_R0] = status->pr_reg[i]; -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.cc -index 1112035bc..8523dad63 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.cc -@@ -765,7 +765,9 @@ bool LinuxDumper::GetStackInfo(const void** stack, size_t* stack_len, - reinterpret_cast(int_stack_pointer & ~(page_size - 1)); - - // The number of bytes of stack which we try to capture. -- static const ptrdiff_t kStackToCapture = 32 * 1024; -+ // This now depends on page_size to avoid missing data -+ // on systems with larger page sizes. -+ static const ptrdiff_t kStackToCapture = 8 * page_size; - - const MappingInfo* mapping = FindMapping(stack_pointer); - if (!mapping) -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h -index f4a75d906..020981f57 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h -@@ -63,7 +63,8 @@ namespace google_breakpad { - (defined(__mips__) && _MIPS_SIM == _ABIO32) - typedef Elf32_auxv_t elf_aux_entry; - #elif defined(__x86_64) || defined(__aarch64__) || \ -- (defined(__mips__) && _MIPS_SIM != _ABIO32) -+ (defined(__mips__) && _MIPS_SIM != _ABIO32) || \ -+ defined(__powerpc64__) - typedef Elf64_auxv_t elf_aux_entry; - #endif - -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper_unittest_helper.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper_unittest_helper.cc -index 3ad48e501..1688c365e 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper_unittest_helper.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper_unittest_helper.cc -@@ -51,6 +51,8 @@ - #define TID_PTR_REGISTER "rcx" - #elif defined(__mips__) - #define TID_PTR_REGISTER "$1" -+#elif defined(__powerpc64__) -+#define TID_PTR_REGISTER "r8" - #else - #error This test has not been ported to this platform. - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc -index 8a3f04e29..e607b28d5 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc -@@ -154,19 +154,27 @@ bool LinuxPtraceDumper::CopyFromProcess(void* dest, pid_t child, - return true; - } - --bool LinuxPtraceDumper::ReadRegisterSet(ThreadInfo* info, pid_t tid) --{ -+bool LinuxPtraceDumper::ReadRegisterSet(ThreadInfo* info, pid_t tid) { - #ifdef PTRACE_GETREGSET - struct iovec io; - info->GetGeneralPurposeRegisters(&io.iov_base, &io.iov_len); -- if (sys_ptrace(PTRACE_GETREGSET, tid, (void*)NT_PRSTATUS, (void*)&io) == -1) { -+ if (ptrace(PTRACE_GETREGSET, tid, (void*)NT_PRSTATUS, (void*)&io) == -1) { - return false; - } - - info->GetFloatingPointRegisters(&io.iov_base, &io.iov_len); -- if (sys_ptrace(PTRACE_GETREGSET, tid, (void*)NT_FPREGSET, (void*)&io) == -1) { -+ if (ptrace(PTRACE_GETREGSET, tid, (void*)NT_FPREGSET, (void*)&io) == -1) { - return false; - } -+ -+#if defined(__powerpc64__) -+ // Grab the vector registers on PPC64 too -+ info->GetVectorRegisters(&io.iov_base, &io.iov_len); -+ if (ptrace(PTRACE_GETREGSET, tid, (void*)NT_PPC_VMX, (void*)&io) == -1) { -+ return false; -+ } -+#endif // defined(__powerpc64__) -+ - return true; - #else - return false; -@@ -303,6 +311,9 @@ bool LinuxPtraceDumper::GetThreadInfoByIndex(size_t index, ThreadInfo* info) { - #elif defined(__mips__) - stack_pointer = - reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); -+#elif defined(__powerpc64__) -+ stack_pointer = -+ reinterpret_cast(info->mcontext.gp_regs[MD_CONTEXT_PPC64_REG_SP]); - #else - #error "This code hasn't been ported to your platform yet." - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper_unittest.cc -index a41dafce0..31743940d 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper_unittest.cc -@@ -462,6 +462,9 @@ TEST(LinuxPtraceDumperTest, VerifyStackReadWithMultipleThreads) { - #elif defined(__mips__) - pid_t* process_tid_location = - reinterpret_cast(one_thread.mcontext.gregs[1]); -+#elif defined(__powerpc64__) -+ pid_t* process_tid_location = -+ reinterpret_cast(one_thread.mcontext.gp_regs[8]); - #else - #error This test has not been ported to this platform. - #endif -@@ -559,6 +562,8 @@ TEST_F(LinuxPtraceDumperTest, SanitizeStackCopy) { - uintptr_t heap_addr = thread_info.regs.rcx; - #elif defined(__mips__) - uintptr_t heap_addr = thread_info.mcontext.gregs[1]; -+#elif defined(__powerpc64__) -+ uintptr_t heap_addr = thread_info.mcontext.gp_regs[8]; - #else - #error This test has not been ported to this platform. - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc -index f8cdf2a1c..cb808c151 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc -@@ -136,7 +136,9 @@ class MinidumpWriter { - : fd_(minidump_fd), - path_(minidump_path), - ucontext_(context ? &context->context : NULL), --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ vector_state_(context ? &context->vector_state : NULL), -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - float_state_(context ? &context->float_state : NULL), - #endif - dumper_(dumper), -@@ -468,7 +470,9 @@ class MinidumpWriter { - if (!cpu.Allocate()) - return false; - my_memset(cpu.get(), 0, sizeof(RawContextCPU)); --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ UContextReader::FillCPUContext(cpu.get(), ucontext_, vector_state_); -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - UContextReader::FillCPUContext(cpu.get(), ucontext_, float_state_); - #else - UContextReader::FillCPUContext(cpu.get(), ucontext_); -@@ -897,7 +901,7 @@ class MinidumpWriter { - dirent->location.rva = 0; - } - --#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) -+#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || defined(__powerpc64__) - bool WriteCPUInformation(MDRawSystemInfo* sys_info) { - char vendor_id[sizeof(sys_info->cpu.x86_cpu_info.vendor_id) + 1] = {0}; - static const char vendor_id_name[] = "vendor_id"; -@@ -917,7 +921,9 @@ class MinidumpWriter { - - // processor_architecture should always be set, do this first - sys_info->processor_architecture = --#if defined(__mips__) -+#if defined(__powerpc64__) -+ MD_CPU_ARCHITECTURE_PPC64; -+#elif defined(__mips__) - # if _MIPS_SIM == _ABIO32 - MD_CPU_ARCHITECTURE_MIPS; - # elif _MIPS_SIM == _ABI64 -@@ -1333,7 +1339,9 @@ class MinidumpWriter { - const char* path_; // Path to the file where the minidum should be written. - - const ucontext_t* const ucontext_; // also from the signal handler --#if !defined(__ARM_EABI__) && !defined(__mips__) -+#if defined(__powerpc64__) -+ const google_breakpad::vstate_t* const vector_state_; -+#elif !defined(__ARM_EABI__) && !defined(__mips__) - const google_breakpad::fpstate_t* const float_state_; // ditto - #endif - LinuxDumper* dumper_; -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h -index d1cc5624c..320847643 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h -@@ -47,6 +47,8 @@ class ExceptionHandler; - - #if defined(__aarch64__) - typedef struct fpsimd_context fpstate_t; -+#elif defined(__powerpc64__) -+typedef vrregset_t vstate_t; - #elif !defined(__ARM_EABI__) && !defined(__mips__) - typedef struct _fpstate fpstate_t; - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer_unittest.cc -index c951e69d8..e1d6e40d6 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer_unittest.cc -@@ -714,6 +714,9 @@ TEST(MinidumpWriterTest, InvalidStackPointer) { - #elif defined(__mips__) - context.context.uc_mcontext.gregs[MD_CONTEXT_MIPS_REG_SP] = - invalid_stack_pointer; -+#elif defined(__powerpc64__) -+ context.context.uc_mcontext.gp_regs[MD_CONTEXT_PPC64_REG_SP] = -+ invalid_stack_pointer; - #else - # error "This code has not been ported to your platform yet." - #endif -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc -index 4e938269f..f0ff15d96 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc -@@ -65,8 +65,7 @@ bool MemoryMappedFile::Map(const char* path, size_t offset) { - } - - #if defined(__x86_64__) || defined(__aarch64__) || \ -- (defined(__mips__) && _MIPS_SIM == _ABI64) -- -+ (defined(__mips__) && _MIPS_SIM == _ABI64) || defined(__powerpc64__) - struct kernel_stat st; - if (sys_fstat(fd, &st) == -1 || st.st_size < 0) { - #else -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file_unittest.cc -index fad59f40c..616496d67 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file_unittest.cc -@@ -176,9 +176,10 @@ TEST_F(MemoryMappedFileTest, RemapAfterMap) { - TEST_F(MemoryMappedFileTest, MapWithOffset) { - // Put more data in the test file this time. Offsets can only be - // done on page boundaries, so we need a two page file to test this. -- const int page_size = 4096; -- char data1[2 * page_size]; -- size_t data1_size = sizeof(data1); -+ const int page_size = getpagesize(); -+ char *data1 = static_cast(malloc(2 * page_size)); -+ EXPECT_TRUE(data1 != NULL); -+ size_t data1_size = (2 * page_size); - for (size_t i = 0; i < data1_size; ++i) { - data1[i] = i & 0x7f; - } -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/memory_allocator_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/memory_allocator_unittest.cc -index 43c86314c..27325b813 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/memory_allocator_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/memory_allocator_unittest.cc -@@ -57,8 +57,9 @@ - - EXPECT_EQ(0U, allocator.pages_allocated()); - uint8_t* p = reinterpret_cast(allocator.Alloc(10000)); -+ uint64_t expected_pages = 1 + ((10000 - 1) / getpagesize()); - ASSERT_FALSE(p == NULL); -- EXPECT_EQ(3U, allocator.pages_allocated()); -+ EXPECT_EQ(expected_pages, allocator.pages_allocated()); - for (unsigned i = 1; i < 10; ++i) { - uint8_t* p = reinterpret_cast(allocator.Alloc(i)); - ASSERT_FALSE(p == NULL); -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_linux.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_linux.cc -index ccc9f1459..debaed4d6 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_linux.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_linux.cc -@@ -202,12 +202,14 @@ bool ExploitabilityLinux::EndedOnIllegalWrite(uint64_t instruction_ptr) { - // Check architecture and set architecture variable to corresponding flag - // in objdump. - switch (context->GetContextCPU()) { -+#if defined(__i386) || defined(__x86_64) - case MD_CONTEXT_X86: - architecture = "i386"; - break; - case MD_CONTEXT_AMD64: - architecture = "i386:x86-64"; - break; -+#endif - default: - // Unsupported architecture. Note that ARM architectures are not - // supported because objdump does not support ARM. -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_unittest.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_unittest.cc -index 528ee5f21..72764d6c1 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_unittest.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/processor/exploitability_unittest.cc -@@ -104,6 +104,8 @@ ExploitabilityFor(const string& filename) { - } - - TEST(ExploitabilityTest, TestWindowsEngine) { -+// The following tests are only executable on an x86-class linux machine. -+#if !defined(_WIN32) && (defined(__i386) || defined(__x86_64)) - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, - ExploitabilityFor("ascii_read_av.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, -@@ -136,9 +138,12 @@ TEST(ExploitabilityTest, TestWindowsEngine) { - ExploitabilityFor("read_av_clobber_write.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_LOW, - ExploitabilityFor("read_av_conditional.dmp")); -+#endif - } - - TEST(ExploitabilityTest, TestLinuxEngine) { -+// The following tests are only executable on an x86-class linux machine. -+#if defined(__i386) || defined(__x86_64) - ASSERT_EQ(google_breakpad::EXPLOITABILITY_INTERESTING, - ExploitabilityFor("linux_null_read_av.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, -@@ -171,7 +176,8 @@ TEST(ExploitabilityTest, TestLinuxEngine) { - ExploitabilityFor("linux_executable_heap.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, - ExploitabilityFor("linux_jmp_to_module_not_exe_region.dmp")); --#ifndef _WIN32 -+#endif -+#if !defined(_WIN32) && (defined(__i386) || defined(__x86_64)) - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, - ExploitabilityFor("linux_write_to_nonwritable_module.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_HIGH, -@@ -182,10 +188,10 @@ TEST(ExploitabilityTest, TestLinuxEngine) { - ExploitabilityFor("linux_write_to_outside_module_via_math.dmp")); - ASSERT_EQ(google_breakpad::EXPLOITABILITY_INTERESTING, - ExploitabilityFor("linux_write_to_under_4k.dmp")); --#endif // _WIN32 -+#endif // !defined(_WIN32) && (!defined(__i386) && !defined(__x86_64)) - } - --#ifndef _WIN32 -+#if !defined(_WIN32) && (defined(__i386) || defined(__x86_64)) - TEST(ExploitabilityLinuxUtilsTest, DisassembleBytesTest) { - ASSERT_FALSE(ExploitabilityLinuxTest::DisassembleBytes("", NULL, 5, NULL)); - uint8_t bytes[6] = {0xc7, 0x0, 0x5, 0x0, 0x0, 0x0}; -@@ -301,6 +307,7 @@ TEST(ExploitabilityLinuxUtilsTest, CalculateAddressTest) { - context, - &write_address)); - } --#endif // _WIN32 -+#endif // !defined(_WIN32) && (defined(__i386) || defined(__x86_64)) -+ - - } // namespace -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/tools/linux/md2core/minidump-2-core.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/tools/linux/md2core/minidump-2-core.cc -index 941586e9f..49cdc3fc2 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/tools/linux/md2core/minidump-2-core.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/tools/linux/md2core/minidump-2-core.cc -@@ -76,6 +76,8 @@ - #define ELF_ARCH EM_MIPS - #elif defined(__aarch64__) - #define ELF_ARCH EM_AARCH64 -+#elif defined(__powerpc64__) -+ #define ELF_ARCH EM_PPC64 - #endif - - #if defined(__arm__) -@@ -86,6 +88,8 @@ typedef user_regs user_regs_struct; - #elif defined (__mips__) - // This file-local typedef simplifies the source code. - typedef gregset_t user_regs_struct; -+#elif defined(__powerpc64__) -+typedef struct pt_regs user_regs_struct; - #endif - - using google_breakpad::MDTypeHelper; -@@ -320,6 +324,9 @@ struct CrashedProcess { - #endif - #if defined(__aarch64__) - user_fpsimd_struct fpregs; -+#endif -+#if defined(__powerpc64__) -+ mcontext_t mcontext; - #endif - uintptr_t stack_addr; - const uint8_t* stack; -@@ -534,6 +541,38 @@ ParseThreadRegisters(CrashedProcess::Thread* thread, - thread->mcontext.fpc_eir = rawregs->float_save.fir; - #endif - } -+#elif defined(__powerpc64__) -+static void -+ParseThreadRegisters(CrashedProcess::Thread* thread, -+ const MinidumpMemoryRange& range) { -+ const MDRawContextPPC64* rawregs = range.GetData(0); -+ -+ for (int i = 0; i < MD_CONTEXT_PPC64_GPR_COUNT; i++) -+ thread->mcontext.gp_regs[i] = rawregs->gpr[i]; -+ -+ thread->mcontext.gp_regs[PT_LNK] = rawregs->lr; -+ thread->mcontext.gp_regs[PT_NIP] = rawregs->srr0; -+ thread->mcontext.gp_regs[PT_MSR] = rawregs->srr1; -+ thread->mcontext.gp_regs[PT_CCR] = rawregs->cr; -+ thread->mcontext.gp_regs[PT_XER] = rawregs->xer; -+ thread->mcontext.gp_regs[PT_CTR] = rawregs->ctr; -+ thread->mcontext.v_regs->vrsave = rawregs->vrsave; -+ -+ for (int i = 0; i < MD_FLOATINGSAVEAREA_PPC_FPR_COUNT; i++) -+ thread->mcontext.fp_regs[i] = rawregs->float_save.fpregs[i]; -+ -+ thread->mcontext.fp_regs[NFPREG-1] = rawregs->float_save.fpscr; -+ -+ for (int i = 0; i < MD_VECTORSAVEAREA_PPC_VR_COUNT; i++) { -+ thread->mcontext.v_regs->vrregs[i][0] = rawregs->vector_save.save_vr[i].high >> 32; -+ thread->mcontext.v_regs->vrregs[i][1] = rawregs->vector_save.save_vr[i].high; -+ thread->mcontext.v_regs->vrregs[i][2] = rawregs->vector_save.save_vr[i].low >> 32; -+ thread->mcontext.v_regs->vrregs[i][3] = rawregs->vector_save.save_vr[i].low; -+ } -+ -+ thread->mcontext.v_regs->vscr.vscr_word = rawregs->vector_save.save_vscr.low & 0xFFFFFFFF; -+} -+ - #else - #error "This code has not been ported to your platform yet" - #endif -@@ -622,6 +661,12 @@ ParseSystemInfo(const Options& options, CrashedProcess* crashinfo, - # else - # error "This mips ABI is currently not supported (n32)" - # endif -+#elif defined(__powerpc64__) -+ if (sysinfo->processor_architecture != MD_CPU_ARCHITECTURE_PPC64) { -+ fprintf(stderr, -+ "This version of minidump-2-core only supports PPC64.\n"); -+ exit(1); -+ } - #else - #error "This code has not been ported to your platform yet" - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/CONTRIBUTORS b/src/3rdparty/chromium/third_party/crashpad/crashpad/CONTRIBUTORS -index 8724b7f32..8e29424ef 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/CONTRIBUTORS -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/CONTRIBUTORS -@@ -13,3 +13,4 @@ Mark Mentovai - Robert Sesek - Scott Graham - Joshua Peraza -+Shawn Anastasio -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/compat/linux/sys/user.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/compat/linux/sys/user.h -index 6ed77a98e..1fd83469a 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/compat/linux/sys/user.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/compat/linux/sys/user.h -@@ -15,6 +15,7 @@ - #ifndef CRASHPAD_COMPAT_LINUX_SYS_USER_H_ - #define CRASHPAD_COMPAT_LINUX_SYS_USER_H_ - -+#include - #include_next - - #include -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context.h -index 3a3e603cb..3118d9e9f 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context.h -@@ -592,6 +592,70 @@ struct MinidumpContextMIPS64 { - uint64_t fir; - }; - -+//! \brief ppc64-specific flags for MinidumpPPC64::context_flags -+//! Based on minidump_cpu_ppc64.h from breakpad -+enum MinidumpContextPPC64Flags : uint32_t { -+ //! \brief Identifies the context as PPC64. -+ kMinidumpContextPPC64 = 0x01000000, -+ -+ //! \brief Indicates the validity of general purpose registers. -+ //! -+ //! Registers `r0`-`r31`, `nip`, `msr`, `lr`, etc. are valid. -+ kMinidumpContextPPC64Base = kMinidumpContextPPC64 | 0x00000001, -+ -+ //! \brief Indicates the validity of floating point registers. -+ //! -+ //! Registers `fp0`-`fp31`, `fpscr` are valid. -+ kMinidumpContextPPC64Floating = kMinidumpContextPPC64 | 0x00000008, -+ -+ //! \brief Indicates the validity of Altivec/VMX registers. -+ //! -+ //! Registers `v0`-`v31`, `vscr`, `vrsave`. -+ kMinidumpContextPPC64Vector = kMinidumpContextPPC64 | 0x00000020, -+ -+ //! \brief Indicates the validity of all registers -+ kMinidumpContextPPC64All = kMinidumpContextPPC64Base | -+ kMinidumpContextPPC64Floating | -+ kMinidumpContextPPC64Vector -+}; -+ -+//! \brief A PPC64 CPU context carried in a minidump file. -+//! Based on minidump_cpu_ppc64.h from breakpad. -+struct MinidumpContextPPC64 { -+ uint64_t context_flags; -+ -+ //! \brief General purpose registers. -+ uint64_t nip; -+ uint64_t msr; -+ uint64_t regs[32]; -+ uint64_t ccr; -+ uint64_t xer; -+ uint64_t lnk; -+ uint64_t ctr; -+ -+ //! \brief Floating point registers. -+ double fpregs[32]; -+ -+ //! \brief FPU status register. -+ double fpscr; -+ -+ //! \brief Altivec/VMX vector registers. -+ struct { -+ //! \brief Vector registers are 128bits. -+ uint128_struct save_vr[32]; -+ uint128_struct save_vscr; -+ -+ //! \brief Padding included for breakpad compatibiltiy. -+ uint32_t save_pad5[4]; -+ -+ //! \brief VRSAVE register. -+ uint32_t save_vrsave; -+ -+ //! \brief Padding included for breakpad compatibiltiy. -+ uint32_t save_pad6[7]; -+ } vregs; -+}; -+ - } // namespace crashpad - - #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_H_ -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -index d7e53a493..d89eb9e01 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.cc -@@ -101,6 +101,13 @@ MinidumpContextWriter::CreateFromSnapshot(const CPUContext* context_snapshot) { - break; - } - -+ case kCPUArchitecturePPC64: { -+ context = std::make_unique(); -+ reinterpret_cast(context.get()) -+ ->InitalizeFromSnapshot(context_snapshot->ppc64); -+ break; -+ } -+ - default: { - LOG(ERROR) << "unknown context architecture " - << context_snapshot->architecture; -@@ -453,4 +460,47 @@ size_t MinidumpContextMIPS64Writer::ContextSize() const { - return sizeof(context_); - } - -+MinidumpContextPPC64Writer::MinidumpContextPPC64Writer() -+ : MinidumpContextWriter(), context_() { -+ context_.context_flags = kMinidumpContextPPC64; -+} -+ -+MinidumpContextPPC64Writer::~MinidumpContextPPC64Writer() = default; -+ -+void MinidumpContextPPC64Writer::InitalizeFromSnapshot( -+ const CPUContextPPC64* context_snapshot) { -+ DCHECK_EQ(state(), kStateMutable); -+ DCHECK_EQ(context_.context_flags, kMinidumpContextPPC64); -+ -+ context_.context_flags = kMinidumpContextPPC64All; -+ -+ memcpy(context_.regs, context_snapshot->regs, sizeof(context_.regs)); -+ context_.nip = context_snapshot->nip; -+ context_.msr = context_snapshot->msr; -+ context_.ccr = context_snapshot->ccr; -+ context_.xer = context_snapshot->xer; -+ context_.lnk = context_snapshot->lnk; -+ context_.ctr = context_snapshot->ctr; -+ -+ memcpy(context_.fpregs, context_snapshot->fpregs, sizeof(context_.fpregs)); -+ context_.fpscr = context_snapshot->fpscr; -+ -+ memcpy(context_.vregs.save_vr, context_snapshot->vregs.save_vr, -+ sizeof(context_.vregs.save_vr)); -+ memcpy(&context_.vregs.save_vscr, &context_snapshot->vregs.save_vscr, -+ sizeof(context_.vregs.save_vscr)); -+ context_.vregs.save_vrsave = context_snapshot->vregs.save_vrsave; -+} -+ -+bool MinidumpContextPPC64Writer::WriteObject( -+ FileWriterInterface* file_writer) { -+ DCHECK_EQ(state(), kStateWritable); -+ return file_writer->Write(&context_, sizeof(context_)); -+} -+ -+size_t MinidumpContextPPC64Writer::ContextSize() const { -+ DCHECK_GE(state(), kStateFrozen); -+ return sizeof(context_); -+} -+ - } // namespace crashpad -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -index d4ab936ee..1d22fc59c 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer.h -@@ -315,6 +315,45 @@ class MinidumpContextMIPS64Writer final : public MinidumpContextWriter { - DISALLOW_COPY_AND_ASSIGN(MinidumpContextMIPS64Writer); - }; - -+class MinidumpContextPPC64Writer final : public MinidumpContextWriter { -+ public: -+ MinidumpContextPPC64Writer(); -+ ~MinidumpContextPPC64Writer() override; -+ -+ //! \brief Initalizes the MinidumpContextPPC64 based on \a context_snapshot. -+ //! -+ //! \param[in] context_snapshot The context snapshot to use as source data. -+ //! -+ //! \note Valid in #kStateMutable. No mutation of context() may be done before -+ //! calling this method, and it is not normally necessary to alter -+ //! context() after calling this method. -+ void InitalizeFromSnapshot(const CPUContextPPC64* context_snapshot); -+ -+ //! \brief Returns a pointer to the context structure that this object will -+ //! write. -+ //! -+ //! \attention This returns a non-`const` pointer to this object’s private -+ //! data so that a caller can populate the context structure directly. -+ //! This is done because providing setter interfaces to each field in the -+ //! context structure would be unwieldy and cumbersome. Care must be taken -+ //! to populate the context structure correctly. The context structure -+ //! must only be modified while this object is in the #kStateMutable -+ //! state. -+ MinidumpContextPPC64* context() { return &context_; } -+ -+ protected: -+ // MinidumpWritable: -+ bool WriteObject(FileWriterInterface* file_writer) override; -+ -+ // MinidumpContextWriter: -+ size_t ContextSize() const override; -+ -+ private: -+ MinidumpContextPPC64 context_; -+ -+ DISALLOW_COPY_AND_ASSIGN(MinidumpContextPPC64Writer); -+}; -+ - } // namespace crashpad - - #endif // CRASHPAD_MINIDUMP_MINIDUMP_CONTEXT_WRITER_H_ -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer_test.cc -index 3216a906b..a9fcbe9d8 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_context_writer_test.cc -@@ -213,6 +213,21 @@ TEST(MinidumpContextWriter, MIPS64_FromSnapshot) { - context, ExpectMinidumpContextMIPS64, kSeed); - } - -+TEST(MinidumpContextWriter, PPC64_Zeros) { -+ EmptyContextTest( -+ ExpectMinidumpContextPPC64); -+} -+ -+TEST(MinidumpContextWriter, PPC64_FromSnapshot) { -+ constexpr uint32_t kSeed = 64; -+ CPUContextPPC64 context_ppc64; -+ CPUContext context; -+ context.ppc64 = &context_ppc64; -+ InitializeCPUContextPPC64(&context, kSeed); -+ FromSnapshotTest( -+ context, ExpectMinidumpContextPPC64, kSeed); -+} -+ - } // namespace - } // namespace test - } // namespace crashpad -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -index a13407605..95dc92524 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/minidump/minidump_misc_info_writer.cc -@@ -126,6 +126,8 @@ std::string MinidumpMiscInfoDebugBuildString() { - static constexpr char kCPU[] = "mips"; - #elif defined(ARCH_CPU_MIPS64EL) - static constexpr char kCPU[] = "mips64"; -+#elif defined(ARCH_CPU_PPC64) -+ static constexpr char kCPU[] = "ppc64"; - #else - #error define kCPU for this CPU - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc -index a51626ccd..61e0b20a1 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/capture_memory.cc -@@ -111,6 +111,11 @@ void CaptureMemory::PointedToByContext(const CPUContext& context, - for (size_t i = 0; i < base::size(context.mipsel->regs); ++i) { - MaybeCaptureMemoryAround(delegate, context.mipsel->regs[i]); - } -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ MaybeCaptureMemoryAround(delegate, context.ppc64->nip); -+ for (size_t i = 0; i < base::size(context.ppc64->regs); ++i) { -+ MaybeCaptureMemoryAround(delegate, context.ppc64->regs[i]); -+ } - #else - #error Port. - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -index 811a72095..f4f83981d 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_architecture.h -@@ -43,7 +43,10 @@ enum CPUArchitecture { - kCPUArchitectureMIPSEL, - - //! \brief 64-bit MIPSEL. -- kCPUArchitectureMIPS64EL -+ kCPUArchitectureMIPS64EL, -+ -+ //! \brief 64-bit PPC64. -+ kCPUArchitecturePPC64 - }; - - } // namespace crashpad -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc -index 6fb8d7e71..b01f7cad1 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.cc -@@ -169,6 +169,8 @@ uint64_t CPUContext::InstructionPointer() const { - return arm->pc; - case kCPUArchitectureARM64: - return arm64->pc; -+ case kCPUArchitecturePPC64: -+ return ppc64->nip; - default: - NOTREACHED(); - return ~0ull; -@@ -185,6 +187,8 @@ uint64_t CPUContext::StackPointer() const { - return arm->sp; - case kCPUArchitectureARM64: - return arm64->sp; -+ case kCPUArchitecturePPC64: -+ return ppc64->regs[1]; - default: - NOTREACHED(); - return ~0ull; -@@ -196,6 +200,7 @@ bool CPUContext::Is64Bit() const { - case kCPUArchitectureX86_64: - case kCPUArchitectureARM64: - case kCPUArchitectureMIPS64EL: -+ case kCPUArchitecturePPC64: - return true; - case kCPUArchitectureX86: - case kCPUArchitectureARM: -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h -index fb23c4679..eebede63c 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/cpu_context.h -@@ -352,6 +352,24 @@ struct CPUContextMIPS64 { - uint64_t fir; - }; - -+//! \brief A context structure carrying PPC64 CPU state. -+struct CPUContextPPC64 { -+ uint64_t nip; -+ uint64_t msr; -+ uint64_t regs[32]; -+ uint64_t ccr; -+ uint64_t xer; -+ uint64_t lnk; -+ uint64_t ctr; -+ double fpregs[32]; -+ double fpscr; -+ struct { -+ uint128_struct save_vr[32]; -+ uint128_struct save_vscr; -+ uint32_t save_vrsave; -+ } vregs; -+}; -+ - //! \brief A context structure capable of carrying the context of any supported - //! CPU architecture. - struct CPUContext { -@@ -382,6 +400,7 @@ struct CPUContext { - CPUContextARM64* arm64; - CPUContextMIPS* mipsel; - CPUContextMIPS64* mips64; -+ CPUContextPPC64* ppc64; - }; - }; - -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -index 9f46a4897..aa677c4eb 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/cpu_context_linux.h -@@ -15,6 +15,7 @@ - #ifndef CRASHPAD_SNAPSHOT_LINUX_CPU_CONTEXT_LINUX_H_ - #define CRASHPAD_SNAPSHOT_LINUX_CPU_CONTEXT_LINUX_H_ - -+#include - #include "build/build_config.h" - #include "snapshot/cpu_context.h" - #include "snapshot/linux/signal_context.h" -@@ -174,6 +175,78 @@ void InitializeCPUContextMIPS( - - #endif // ARCH_CPU_MIPS_FAMILY || DOXYGEN - -+#if defined(ARCH_CPU_PPC64_FAMILY) || DOXYGEN -+ -+//! \brief Initalizes a CPUContextPPC64 structure from native context -+//! structures on Linux. -+//! -+//! \param[in] thread_context The native thread context. -+//! \param[in] float_context The native float context. -+//! \param[in] vector_context The native vector context. -+//! \param[out] context The CPUContextPPC64 structure to initalize. -+template -+void InitializeCPUContextPPC64( -+ const ThreadContext::t64_t& thread_context, -+ const FloatContext::f64_t& float_context, -+ const VectorContext::v64_t& vector_context, -+ typename Traits::CPUContext* context) { -+ -+ memcpy(context->regs, thread_context.gpr, sizeof(context->regs)); -+ context->nip = thread_context.nip; -+ context->msr = thread_context.msr; -+ context->ccr = thread_context.ccr; -+ context->xer = thread_context.xer; -+ context->lnk = thread_context.lnk; -+ context->ctr = thread_context.ctr; -+ -+ memcpy(context->fpregs, float_context.fpregs, sizeof(context->fpregs)); -+ context->fpscr = float_context.fpscr; -+ -+ for (uint8_t i = 0; i < 32; i++) { -+ context->vregs.save_vr[i] = { -+ (((uint64_t)vector_context.vrregs[i][0]) << 32) | -+ vector_context.vrregs[i][1], -+ (((uint64_t)vector_context.vrregs[i][2]) << 32) | -+ vector_context.vrregs[i][3] -+ }; -+ } -+ context->vregs.save_vrsave = vector_context.vrsave; -+ context->vregs.save_vscr = {0, (uint64_t)vector_context.vscr.vscr_word}; -+} -+ -+template -+void InitializeCPUContextPPC64( -+ const SignalThreadContext64 &thread_context, -+ const SignalFloatContext64 &float_context, -+ const SignalVectorContext64 &vector_context, -+ typename Traits::CPUContext* context) { -+ -+ memcpy(context->regs, thread_context.regs, sizeof(context->regs)); -+ context->nip = thread_context.nip; -+ context->msr = thread_context.msr; -+ context->ccr = thread_context.ccr; -+ context->xer = thread_context.xer; -+ context->lnk = thread_context.lnk; -+ context->ctr = thread_context.ctr; -+ -+ memcpy(context->fpregs, float_context.regs, sizeof(context->fpregs)); -+ context->fpscr = float_context.fpscr; -+ -+ for (uint8_t i = 0; i < 32; i++) { -+ context->vregs.save_vr[i] = { -+ (((uint64_t)vector_context.vrregs[i][0]) << 32) | -+ vector_context.vrregs[i][1], -+ (((uint64_t)vector_context.vrregs[i][2]) << 32) | -+ vector_context.vrregs[i][3] -+ }; -+ } -+ context->vregs.save_vrsave = vector_context.vrsave; -+ context->vregs.save_vscr = {0, (uint64_t)vector_context.vscr.vscr_word}; -+} -+ -+ -+#endif -+ - } // namespace internal - } // namespace crashpad - -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/debug_rendezvous_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/debug_rendezvous_test.cc -index be22c9031..c5df23d1b 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/debug_rendezvous_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/debug_rendezvous_test.cc -@@ -159,9 +159,11 @@ void TestAgainstTarget(PtraceConnection* connection) { - const bool is_vdso_mapping = - device == 0 && inode == 0 && mapping_name == "[vdso]"; - static constexpr char kPrefix[] = "linux-vdso.so."; -+ static constexpr char kPrefix64[] = "linux-vdso64.so."; - return is_vdso_mapping == - (module_name.empty() || -- module_name.compare(0, strlen(kPrefix), kPrefix) == 0); -+ module_name.compare(0, strlen(kPrefix), kPrefix) == 0 || -+ module_name.compare(0, strlen(kPrefix64), kPrefix64) == 0); - }, - module_mapping->name, - module_mapping->device, -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -index cd40b3b12..6bcf23b6f 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.cc -@@ -323,6 +323,69 @@ bool ExceptionSnapshotLinux::ReadContext( - reader, context_address, context_.mips64); - } - -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ -+template -+static bool ReadContext(ProcessReaderLinux* reader, -+ LinuxVMAddress context_address, -+ typename Traits::CPUContext* dest_context) { -+ const ProcessMemory* memory = reader->Memory(); -+ -+ LinuxVMAddress gp_regs_address = context_address + -+ offsetof(UContext, mcontext) + -+ offsetof(typename Traits::MContext, gp_regs); -+ -+ typename Traits::SignalThreadContext thread_context; -+ if (!memory->Read(gp_regs_address, sizeof(thread_context), &thread_context)) { -+ LOG(ERROR) << "Couldn't read gp_regs!"; -+ return false; -+ } -+ -+ LinuxVMAddress fp_regs_address = context_address + -+ offsetof(UContext, mcontext) + -+ offsetof(typename Traits::MContext, fp_regs); -+ -+ typename Traits::SignalFloatContext fp_context; -+ if (!memory->Read(fp_regs_address, sizeof(fp_context), &fp_context)) { -+ LOG(ERROR) << "Couldn't read fp_regs!"; -+ return false; -+ } -+ -+ LinuxVMAddress v_regs_ptr_address = context_address + -+ offsetof(UContext, mcontext) + -+ offsetof(typename Traits::MContext, vmx_reserve) + 8; -+ -+ typename Traits::SignalVectorContext v_context; -+ if (!memory->Read(v_regs_ptr_address, sizeof(v_context), &v_context)) { -+ LOG(ERROR) << "Couldn't read v_regs!"; -+ return false; -+ } -+ -+ InitializeCPUContextPPC64(thread_context, fp_context, -+ v_context, dest_context); -+ -+ return true; -+} -+ -+template<> -+bool ExceptionSnapshotLinux::ReadContext( -+ ProcessReaderLinux* reader, -+ LinuxVMAddress context_address) { -+ context_.architecture = kCPUArchitecturePPC64; -+ context_.ppc64 = &context_union_.ppc64; -+ -+ return internal::ReadContext( -+ reader, context_address, context_.ppc64); -+} -+ -+template<> -+bool ExceptionSnapshotLinux::ReadContext( -+ ProcessReaderLinux* reader, -+ LinuxVMAddress context_address) { -+ // PPC64 is 64-bit -+ return false; -+} -+ - #endif // ARCH_CPU_X86_FAMILY - - bool ExceptionSnapshotLinux::Initialize(ProcessReaderLinux* process_reader, -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -index ea0cd2106..e42df520f 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux.h -@@ -84,6 +84,8 @@ class ExceptionSnapshotLinux final : public ExceptionSnapshot { - #elif defined(ARCH_CPU_MIPS_FAMILY) - CPUContextMIPS mipsel; - CPUContextMIPS64 mips64; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ CPUContextPPC64 ppc64; - #endif - } context_union_; - CPUContext context_; -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux_test.cc -index e4ff1ab79..25534dd08 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/exception_snapshot_linux_test.cc -@@ -296,7 +296,28 @@ void ExpectContext(const CPUContext& actual, const NativeCPUContext& expected) { - 0); - #undef CPU_ARCH_NAME - } -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+using NativeCPUContext = ucontext_t; -+ -+void InitializeContext(NativeCPUContext* context) { -+ for (size_t reg = 0; reg < 32; ++reg) { -+ context->uc_mcontext.gp_regs[reg] = reg; -+ } -+ -+ memset(&context->uc_mcontext.fp_regs, 44, -+ sizeof(context->uc_mcontext.fp_regs)); -+} - -+void ExpectContext(const CPUContext& actual, const NativeCPUContext& expected) { -+ EXPECT_EQ(actual.architecture, kCPUArchitecturePPC64); -+ -+ for (size_t reg = 0; reg < 32; ++reg) { -+ EXPECT_EQ(actual.ppc64->regs[reg], expected.uc_mcontext.gp_regs[reg]); -+ } -+ -+ EXPECT_EQ(memcmp(actual.ppc64->fpregs, expected.uc_mcontext.fp_regs, -+ sizeof(actual.ppc64->fpregs)), 0); -+} - #else - #error Port. - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -index b96abfe74..df12ca566 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux.cc -@@ -108,6 +108,8 @@ void ProcessReaderLinux::Thread::InitializeStack(ProcessReaderLinux* reader) { - #elif defined(ARCH_CPU_MIPS_FAMILY) - stack_pointer = reader->Is64Bit() ? thread_info.thread_context.t64.regs[29] - : thread_info.thread_context.t32.regs[29]; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ stack_pointer = thread_info.thread_context.t64.gpr[1]; - #else - #error Port. - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux_test.cc -index 5b5723616..049c32858 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/process_reader_linux_test.cc -@@ -612,6 +612,8 @@ bool WriteTestModule(const base::FilePath& module_path) { - module.ehdr.e_machine = EM_AARCH64; - #elif defined(ARCH_CPU_MIPSEL) || defined(ARCH_CPU_MIPS64EL) - module.ehdr.e_machine = EM_MIPS; -+#elif defined(ARCH_CPU_PPC64) -+ module.ehdr.e_machine = EM_PPC64; - #endif - - module.ehdr.e_version = EV_CURRENT; -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -index 110024680..a1f2da259 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/signal_context.h -@@ -422,6 +422,89 @@ static_assert(offsetof(UContext, mcontext.fpregs) == - "context offset mismatch"); - #endif - -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ -+struct SignalThreadContext64 { -+ uint64_t regs[32]; -+ uint64_t nip; -+ uint64_t msr; -+ uint64_t orig_r3; -+ uint64_t ctr; -+ uint64_t lnk; -+ uint64_t xer; -+ uint64_t ccr; -+ uint64_t softe; -+ uint64_t trap; -+ uint64_t dar; -+ uint64_t dsisr; -+ uint64_t result; -+ uint64_t dscr; -+ uint64_t fpr0[3]; -+}; -+ -+struct SignalFloatContext64 { -+ double regs[32]; -+ double fpscr; -+}; -+ -+struct SignalVectorContext64 { -+ int32_t vrregs[32][4]; -+ struct { -+ int32_t __pad[3]; -+ int32_t vscr_word; -+ } vscr; -+ int32_t vrsave; -+ int32_t __pad[3]; -+} __attribute__((__aligned__(16))); -+ -+ -+#pragma pack(pop) -+struct MContext64 { -+ uint64_t reserved[4]; -+ int32_t signal; -+ int32_t __pad0; -+ uint64_t handler; -+ uint64_t oldmask; -+ uint64_t pt_regs_ptr; -+ SignalThreadContext64 gp_regs; -+ SignalFloatContext64 fp_regs; -+ SignalVectorContext64 *v_regs; -+ int64_t vmx_reserve[69]; -+}; -+ -+struct ContextTraits64 : public Traits64 { -+ using MContext = MContext64; -+ using SignalThreadContext = SignalThreadContext64; -+ using SignalFloatContext = SignalFloatContext64; -+ using SignalVectorContext = SignalVectorContext64; -+ using CPUContext = CPUContextPPC64; -+}; -+ -+struct ContextTraits32 : public Traits32 {}; -+ -+struct UContext { -+ uint64_t flags; -+ uint64_t link; -+ SignalStack stack; -+ Sigset sigmask; -+ MContext64 mcontext; -+}; -+#pragma pack(push, 1) -+ -+static_assert(sizeof(UContext) == sizeof(ucontext_t), -+ "ucontext_t size mismatch"); -+static_assert(sizeof(MContext64) == sizeof(mcontext_t), -+ "mcontext_t size mismatch"); -+static_assert(sizeof(SignalThreadContext64) == sizeof(gregset_t), -+ "gregset_t size mismatch"); -+static_assert(sizeof(SignalFloatContext64) == sizeof(fpregset_t), -+ "fpregset_t size mismatch"); -+static_assert(sizeof(SignalVectorContext64) == sizeof(vrregset_t), -+ "vrregset_t size mismatch"); -+static_assert(offsetof(UContext, mcontext) == -+ offsetof(ucontext_t, uc_mcontext), "mcontext offset mismatch"); -+static_assert(offsetof(MContext64, gp_regs) == -+ offsetof(mcontext_t, gp_regs), "gp_regs offset mismatch"); - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -index 8564d3d45..b690ecd48 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/system_snapshot_linux.cc -@@ -203,6 +203,8 @@ CPUArchitecture SystemSnapshotLinux::GetCPUArchitecture() const { - #elif defined(ARCH_CPU_MIPS_FAMILY) - return process_reader_->Is64Bit() ? kCPUArchitectureMIPS64EL - : kCPUArchitectureMIPSEL; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ return kCPUArchitecturePPC64; - #else - #error port to your architecture - #endif -@@ -218,6 +220,9 @@ uint32_t SystemSnapshotLinux::CPURevision() const { - #elif defined(ARCH_CPU_MIPS_FAMILY) - // Not implementable on MIPS - return 0; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Not yet implemented on PPC64 -+ return 0; - #else - #error port to your architecture - #endif -@@ -238,6 +243,9 @@ std::string SystemSnapshotLinux::CPUVendor() const { - #elif defined(ARCH_CPU_MIPS_FAMILY) - // Not implementable on MIPS - return std::string(); -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Not yet implemented on PPC64 -+ return std::string(); - #else - #error port to your architecture - #endif -@@ -371,6 +379,9 @@ bool SystemSnapshotLinux::NXEnabled() const { - #elif defined(ARCH_CPU_MIPS_FAMILY) - // Not implementable on MIPS - return false; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Not yet implemented on PPC64 -+ return false; - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -index e3e2bebdd..8ef43752e 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.cc -@@ -186,6 +186,14 @@ bool ThreadSnapshotLinux::Initialize(ProcessReaderLinux* process_reader, - thread.thread_info.float_context.f32, - context_.mipsel); - } -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ context_.architecture = kCPUArchitecturePPC64; -+ context_.ppc64 = &context_union_.ppc64; -+ InitializeCPUContextPPC64( -+ thread.thread_info.thread_context.t64, -+ thread.thread_info.float_context.f64, -+ thread.thread_info.vector_context.v64, -+ context_.ppc64); - #else - #error Port. - #endif -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -index 44cc6f6d9..d4136461e 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/snapshot/linux/thread_snapshot_linux.h -@@ -68,6 +68,8 @@ class ThreadSnapshotLinux final : public ThreadSnapshot { - #elif defined(ARCH_CPU_MIPS_FAMILY) - CPUContextMIPS mipsel; - CPUContextMIPS64 mips64; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ CPUContextPPC64 ppc64; - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/auxiliary_vector.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/auxiliary_vector.cc -index d3d5ebdfb..3fd730cb5 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/auxiliary_vector.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/auxiliary_vector.cc -@@ -56,6 +56,11 @@ bool AuxiliaryVector::Read(PtraceConnection* connection) { - if (type == AT_IGNORE) { - continue; - } -+#if defined(ARCH_CPU_PPC64_FAMILY) -+ if (type == AT_IGNOREPPC) { -+ continue; -+ } -+#endif - if (!MapInsertOrReplace(&values_, type, value, nullptr)) { - LOG(ERROR) << "duplicate auxv entry"; - return false; -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptrace_broker.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptrace_broker.cc -index 155a1e0c6..5e50ceb5f 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptrace_broker.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptrace_broker.cc -@@ -94,8 +94,8 @@ int PtraceBroker::Run() { - } - - bool PtraceBroker::AllocateAttachments() { -- constexpr size_t page_size = 4096; -- constexpr size_t alloc_size = -+ static size_t page_size = getpagesize(); -+ size_t alloc_size = - (sizeof(ScopedPtraceAttach) + page_size - 1) & ~(page_size - 1); - void* alloc = sbrk(alloc_size); - if (reinterpret_cast(alloc) == -1) { -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc -index 557e0d363..08ae434b8 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc -@@ -398,6 +398,64 @@ bool GetThreadArea64(pid_t tid, - return true; - } - -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+// PPC64 has had HAVE_ARCH_TRACEHOOK set since 2.6.27 (even before x86 had it). -+// That means we can simply use PTRACE_GETREGESET. -+ -+template -+bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) { -+ iovec iov; -+ iov.iov_base = reinterpret_cast(dest); -+ iov.iov_len = sizeof(*dest); -+ if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast(set), &iov) != 0) { -+ PLOG_IF(ERROR, can_log) << "ptrace"; -+ return false; -+ } -+ if (iov.iov_len != sizeof(*dest)) { -+ LOG_IF(ERROR, can_log) << "Unexpected registers size"; -+ return false; -+ } -+ return true; -+} -+ -+bool GetVectorRegisters64(pid_t tid, -+ VectorContext* context, -+ bool can_log) { -+ return GetRegisterSet(tid, NT_PPC_VMX, &context->v64, can_log); -+} -+ -+bool GetFloatingPointRegisters64(pid_t tid, -+ FloatContext* context, -+ bool can_log) { -+ return GetRegisterSet(tid, NT_PRFPREG, &context->f64, can_log); -+} -+ -+bool GetThreadArea64(pid_t tid, -+ const ThreadContext& context, -+ LinuxVMAddress* address, -+ bool can_log) { -+ // PPC64 doesn't have PTRACE_GET_THREAD_AREA since the thread pointer -+ // is stored in GPR 13. -+ ThreadContext::t64_t tc; -+ if (!GetRegisterSet(tid, NT_PRSTATUS, &tc, can_log)) { -+ LOG_IF(ERROR, can_log) << "Unable to get thread pointer!"; -+ return false; -+ } -+ -+ *address = tc.gpr[13]; -+ -+ return true; -+} -+ -+// Stubs for 32-bit functions not applicable on PPC64 -+bool GetFloatingPointRegisters32(pid_t tid, -+ FloatContext* context, -+ bool can_log) { return false; } -+bool GetThreadArea32(pid_t tid, -+ const ThreadContext &context, -+ LinuxVMAddress *address, -+ bool can_log) { return false; } -+ - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -@@ -494,6 +552,9 @@ bool Ptracer::GetThreadInfo(pid_t tid, ThreadInfo* info) { - if (is_64_bit_) { - return GetGeneralPurposeRegisters64(tid, &info->thread_context, can_log_) && - GetFloatingPointRegisters64(tid, &info->float_context, can_log_) && -+#if defined(ARCH_CPU_PPC64_FAMILY) -+ GetVectorRegisters64(tid, &info->vector_context, can_log_) && -+#endif - GetThreadArea64(tid, - info->thread_context, - &info->thread_specific_data_address, -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -index 5b55c24a7..dea0d1f39 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -@@ -28,6 +28,10 @@ - #include - #endif - -+#if defined(ARCH_CPU_PPC64_FAMILY) -+#include -+#endif -+ - namespace crashpad { - - //! \brief The set of general purpose registers for an architecture family. -@@ -79,6 +83,8 @@ union ThreadContext { - uint32_t cp0_status; - uint32_t cp0_cause; - uint32_t padding1_; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // PPC64 is 64-bit - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -@@ -132,6 +138,21 @@ union ThreadContext { - uint64_t cp0_badvaddr; - uint64_t cp0_status; - uint64_t cp0_cause; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Reflects struct pt_regs in asm/ptrace.h. -+ uint64_t gpr[32]; -+ uint64_t nip; -+ uint64_t msr; -+ uint64_t orig_gpr3; -+ uint64_t ctr; -+ uint64_t lnk; -+ uint64_t xer; -+ uint64_t ccr; -+ uint64_t softe; -+ uint64_t trap; -+ uint64_t dar; -+ uint64_t dsisr; -+ uint64_t result; - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -@@ -143,6 +164,8 @@ union ThreadContext { - using NativeThreadContext = user_regs; - #elif defined(ARCH_CPU_MIPS_FAMILY) - // No appropriate NativeThreadsContext type available for MIPS -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ using NativeThreadContext = struct pt_regs; - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 -@@ -218,6 +241,9 @@ union FloatContext { - } fpregs[32]; - uint32_t fpcsr; - uint32_t fpu_id; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Crashpad's PPC support is 64-bit only, so this -+ // 32bit-only struct is declared as empty. - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -@@ -252,6 +278,10 @@ union FloatContext { - double fpregs[32]; - uint32_t fpcsr; - uint32_t fpu_id; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ // Reflects fpregset_t in sys/ucontext.h -+ double fpregs[32]; -+ double fpscr; - #else - #error Port. - #endif // ARCH_CPU_X86_FAMILY -@@ -280,6 +310,8 @@ union FloatContext { - static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch"); - #elif defined(ARCH_CPU_MIPS_FAMILY) - // No appropriate floating point context native type for available MIPS. -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ static_assert(sizeof(f64) == sizeof(fpregset_t), "Size mismatch"); - #else - #error Port. - #endif // ARCH_CPU_X86 -@@ -287,6 +319,26 @@ union FloatContext { - static_assert(std::is_standard_layout::value, - "Not standard layout"); - -+//! \brief The vector registers used for an architecture family -+union VectorContext { -+ struct v32_t {} v32; -+#if defined(ARCH_CPU_PPC64_FAMILY) -+ __attribute__((__aligned__(16))) // Vector context must be doubleword aligned. -+#endif -+ struct v64_t { -+#if defined(ARCH_CPU_PPC64_FAMILY) -+ // Reflects vrregset_t in sys/ucontext.h -+ uint32_t vrregs[32][4]; -+ struct { -+ uint32_t __pad[3]; -+ uint32_t vscr_word; -+ } vscr; -+ uint32_t vrsave; -+ uint32_t __pad[3]; -+#endif -+ } v64; -+}; -+ - //! \brief A collection of `ptrace`-able information about a thread. - struct ThreadInfo { - ThreadInfo(); -@@ -298,6 +350,9 @@ struct ThreadInfo { - //! \brief The floating point registers for the thread. - FloatContext float_context; - -+ //! \brief (Optional) The vector registers used for the thread. -+ VectorContext vector_context; -+ - //! \brief The thread-local storage address for the thread. - LinuxVMAddress thread_specific_data_address; - }; -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context.h -index a88a10336..b0d6578bd 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context.h -@@ -70,6 +70,7 @@ using NativeCPUContext = ucontext_t; - //! macOS/Linux/Fuchsia | x86_64 | `%%rdi` - //! Linux | ARM/ARM64 | `r0`/`x0` - //! Linux | MIPS/MIPS64 | `$a0` -+//! Linux | PPC64 | `r3` - //! - //! Additionally, the value `LR` on ARM/ARM64 will be the return address of - //! this function. -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_linux.S b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_linux.S -index 52215ee5d..b3e4a3ec7 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_linux.S -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_linux.S -@@ -32,7 +32,7 @@ - .balign 4, 0x0 - .type CAPTURECONTEXT_SYMBOL, %function - .type CAPTURECONTEXT_SYMBOL2, %function --#elif defined(__mips__) -+#elif defined(__mips__) || defined(__powerpc64__) - .balign 4, 0x0 - #endif - -@@ -423,4 +423,214 @@ CAPTURECONTEXT_SYMBOL2: - jr $ra - - .set at -+#elif defined(__powerpc64__) -+ // Store r0-r31 -+ std 0, 0xe8(3) // context->uc_mcontext.gp_regs[0] -+ std 1, 0xf0(3) // context->uc_mcontext.gp_regs[1] -+ std 2, 0xf8(3) // context->uc_mcontext.gp_regs[2] -+ // note that r3's original value was lost -+ std 3, 0x100(3) // context->uc_mcontext.gp_regs[3] -+ std 4, 0x108(3) // context->uc_mcontext.gp_regs[4] -+ std 5, 0x110(3) // context->uc_mcontext.gp_regs[5] -+ std 6, 0x118(3) // context->uc_mcontext.gp_regs[6] -+ std 7, 0x120(3) // context->uc_mcontext.gp_regs[7] -+ std 8, 0x128(3) // context->uc_mcontext.gp_regs[8] -+ std 9, 0x130(3) // context->uc_mcontext.gp_regs[9] -+ std 10, 0x138(3) // context->uc_mcontext.gp_regs[10] -+ std 11, 0x140(3) // context->uc_mcontext.gp_regs[11] -+ std 12, 0x148(3) // context->uc_mcontext.gp_regs[12] -+ std 13, 0x150(3) // context->uc_mcontext.gp_regs[13] -+ std 14, 0x158(3) // context->uc_mcontext.gp_regs[14] -+ std 15, 0x160(3) // context->uc_mcontext.gp_regs[15] -+ std 16, 0x168(3) // context->uc_mcontext.gp_regs[16] -+ std 17, 0x170(3) // context->uc_mcontext.gp_regs[17] -+ std 18, 0x178(3) // context->uc_mcontext.gp_regs[18] -+ std 19, 0x180(3) // context->uc_mcontext.gp_regs[19] -+ std 20, 0x188(3) // context->uc_mcontext.gp_regs[20] -+ std 21, 0x190(3) // context->uc_mcontext.gp_regs[21] -+ std 22, 0x198(3) // context->uc_mcontext.gp_regs[22] -+ std 23, 0x1a0(3) // context->uc_mcontext.gp_regs[23] -+ std 24, 0x1a8(3) // context->uc_mcontext.gp_regs[24] -+ std 25, 0x1b0(3) // context->uc_mcontext.gp_regs[25] -+ std 26, 0x1b8(3) // context->uc_mcontext.gp_regs[26] -+ std 27, 0x1c0(3) // context->uc_mcontext.gp_regs[27] -+ std 28, 0x1c8(3) // context->uc_mcontext.gp_regs[28] -+ std 29, 0x1d0(3) // context->uc_mcontext.gp_regs[29] -+ std 30, 0x1d8(3) // context->uc_mcontext.gp_regs[30] -+ std 31, 0x1e0(3) // context->uc_mcontext.gp_regs[31] -+ -+ // For NIP, we can use the value in the link register -+ mflr 0 -+ std 0, 0x1e8(3) // context->uc_mcontext.gp_regs[PT_NIP] -+ -+ // CTR -+ mfctr 0 -+ std 0, 0x200(3) // context->uc_mcontext.gp_regs[PT_CTR] -+ -+ // For LNK, we'll use the caller's LR save area (2 stack frames up). -+ // r4 can be used as a scratch register since it has already been saved. -+ ld 4, 0(1) -+ ld 4, 16(4) -+ std 4, 0x208(3) // context->uc_mcontext.gp_regs[PT_LNK] -+ -+ // XER -+ mfxer 0 -+ std 0, 0x210(3) // context->uc_mcontext.gp_regs[PT_XER] -+ -+ // CCR -+ mfcr 0 -+ std 0, 0x218(3) // context->uc_mcontext.gp_regs[PT_CCR] -+ -+ // MSR, orig_r3, MQ, TRAP, DAR, DSISR, RESULT, DSCR, -+ // not used or not relevant, zero them out. -+ li 4, 0 -+ std 4, 0x1f0(3) // context->uc_mcontext.gp_regs[PT_MSR] -+ std 4, 0x1f8(3) // context->uc_mcontext.gp_regs[PT_ORIG_R3] -+ std 4, 0x220(3) // context->uc_mcontext.gp_regs[PT_MQ] -+ std 4, 0x228(3) // context->uc_mcontext.gp_regs[PT_TRAP] -+ std 4, 0x230(3) // context->uc_mcontext.gp_regs[PT_DAR] -+ std 4, 0x238(3) // context->uc_mcontext.gp_regs[PT_DSISR] -+ std 4, 0x240(3) // context->uc_mcontext.gp_regs[PT_RESULT] -+ std 4, 0x248(3) // context->uc_mcontext.gp_regs[PT_DSCR] -+ -+ // Update context->uc_mcontext.regs to point to gp_regs -+ addi 0, 3, 0xe8 -+ std 0, 0xe0(3) -+ -+ // Save floating point registers 0-31 -+ stfd 0, 0x268(3) // context->uc_mcontext.fp_regs[0] -+ stfd 1, 0x270(3) // context->uc_mcontext.fp_regs[1] -+ stfd 2, 0x278(3) // context->uc_mcontext.fp_regs[2] -+ stfd 3, 0x280(3) // context->uc_mcontext.fp_regs[3] -+ stfd 4, 0x288(3) // context->uc_mcontext.fp_regs[4] -+ stfd 5, 0x290(3) // context->uc_mcontext.fp_regs[5] -+ stfd 6, 0x298(3) // context->uc_mcontext.fp_regs[6] -+ stfd 7, 0x2a0(3) // context->uc_mcontext.fp_regs[7] -+ stfd 8, 0x2a8(3) // context->uc_mcontext.fp_regs[8] -+ stfd 9, 0x2b0(3) // context->uc_mcontext.fp_regs[9] -+ stfd 10, 0x2b8(3) // context->uc_mcontext.fp_regs[10] -+ stfd 11, 0x2c0(3) // context->uc_mcontext.fp_regs[11] -+ stfd 12, 0x2c8(3) // context->uc_mcontext.fp_regs[12] -+ stfd 13, 0x2d0(3) // context->uc_mcontext.fp_regs[13] -+ stfd 14, 0x2d8(3) // context->uc_mcontext.fp_regs[14] -+ stfd 15, 0x2e0(3) // context->uc_mcontext.fp_regs[15] -+ stfd 16, 0x2e8(3) // context->uc_mcontext.fp_regs[16] -+ stfd 17, 0x2f0(3) // context->uc_mcontext.fp_regs[17] -+ stfd 18, 0x2f8(3) // context->uc_mcontext.fp_regs[18] -+ stfd 19, 0x300(3) // context->uc_mcontext.fp_regs[19] -+ stfd 20, 0x308(3) // context->uc_mcontext.fp_regs[20] -+ stfd 21, 0x310(3) // context->uc_mcontext.fp_regs[21] -+ stfd 22, 0x318(3) // context->uc_mcontext.fp_regs[22] -+ stfd 23, 0x320(3) // context->uc_mcontext.fp_regs[23] -+ stfd 24, 0x328(3) // context->uc_mcontext.fp_regs[24] -+ stfd 25, 0x330(3) // context->uc_mcontext.fp_regs[25] -+ stfd 26, 0x338(3) // context->uc_mcontext.fp_regs[26] -+ stfd 27, 0x340(3) // context->uc_mcontext.fp_regs[27] -+ stfd 28, 0x348(3) // context->uc_mcontext.fp_regs[28] -+ stfd 29, 0x350(3) // context->uc_mcontext.fp_regs[29] -+ stfd 30, 0x358(3) // context->uc_mcontext.fp_regs[30] -+ stfd 31, 0x360(3) // context->uc_mcontext.fp_regs[31] -+ -+ // FPSCR -+ mffs 0 -+ stfd 0, 0x368(3) // context->uc_mcontext.fp_regs[32] -+ -+ // Save VMX Vector registers -+ // Update r4 to contain the base address of vmx_reserve -+ addi 4, 3, 0x378 -+ // Ensure that it is quadword aligned -+ andi. 5, 4, 0xF -+ beq 1f // No alignment is necessary -+ // Address is doubleword aligned and not quadword aligned, add 8 -+ addi 4, 4, 8 -+ -+1: -+ // Store VMX registers 0-31 -+ // r4 will contain the base address -+ // r5 will contain the index -+ li 5, 0 -+ stvx 0, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 0] -+ addi 5, 5, 16 -+ stvx 1, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 1] -+ addi 5, 5, 16 -+ stvx 2, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 2] -+ addi 5, 5, 16 -+ stvx 3, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 3] -+ addi 5, 5, 16 -+ stvx 4, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 4] -+ addi 5, 5, 16 -+ stvx 5, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 5] -+ addi 5, 5, 16 -+ stvx 6, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 6] -+ addi 5, 5, 16 -+ stvx 7, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 7] -+ addi 5, 5, 16 -+ stvx 8, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 8] -+ addi 5, 5, 16 -+ stvx 9, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 9] -+ addi 5, 5, 16 -+ stvx 10, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 10] -+ addi 5, 5, 16 -+ stvx 11, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 11] -+ addi 5, 5, 16 -+ stvx 12, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 12] -+ addi 5, 5, 16 -+ stvx 13, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 13] -+ addi 5, 5, 16 -+ stvx 14, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 14] -+ addi 5, 5, 16 -+ stvx 15, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 15] -+ addi 5, 5, 16 -+ stvx 16, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 16] -+ addi 5, 5, 16 -+ stvx 17, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 17] -+ addi 5, 5, 16 -+ stvx 18, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 18] -+ addi 5, 5, 16 -+ stvx 19, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 19] -+ addi 5, 5, 16 -+ stvx 20, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 20] -+ addi 5, 5, 16 -+ stvx 21, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 21] -+ addi 5, 5, 16 -+ stvx 22, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 22] -+ addi 5, 5, 16 -+ stvx 23, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 23] -+ addi 5, 5, 16 -+ stvx 24, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 24] -+ addi 5, 5, 16 -+ stvx 25, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 25] -+ addi 5, 5, 16 -+ stvx 26, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 26] -+ addi 5, 5, 16 -+ stvx 27, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 27] -+ addi 5, 5, 16 -+ stvx 28, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 28] -+ addi 5, 5, 16 -+ stvx 29, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 29] -+ addi 5, 5, 16 -+ stvx 30, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 30] -+ addi 5, 5, 16 -+ stvx 31, 4, 5 // context->uc_mcontext.vmx_reserve[(align) + 31] -+ addi 5, 5, 16 -+ -+ // VSCR -+ mfvscr 0 -+ stvx 0, 4, 5 -+ addi 5, 5, 16 -+ -+ // VRSAVE -+ mfvrsave 0 -+ stwx 0, 4, 5 -+ -+ // Update context->uc_mcontext.v_regs to point to vmx_reserve + alignment. -+ std 4, 0x370(3) -+ -+ // Zero out all unused fields -+ li 4, 0 -+ std 4, 0xc8(3) // context->uc_mcontext.signal -+ std 4, 0xd0(3) // context->uc_mcontext.handler -+ std 4, 0xd8(3) // context->uc_mcontext.oldmask -+ -+ blr - #endif // __i386__ -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test.cc -index cf23c2def..5f264bc92 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test.cc -@@ -57,7 +57,7 @@ void TestCaptureContext() { - uintptr_t pc = ProgramCounterFromContext(context_1); - - #if !defined(ADDRESS_SANITIZER) && !defined(ARCH_CPU_MIPS_FAMILY) && \ -- !defined(MEMORY_SANITIZER) -+ !defined(MEMORY_SANITIZER) && !defined(ARCH_CPU_PPC64_FAMILY) - // Sanitizers can cause enough code bloat that the “nearby” check would - // likely fail. - const uintptr_t kReferencePC = -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test_util_linux.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test_util_linux.cc -index 9fc5db28c..5f69f8dce 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test_util_linux.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/misc/capture_context_test_util_linux.cc -@@ -36,6 +36,8 @@ void SanityCheckContext(const NativeCPUContext& context) { - EXPECT_EQ(context.uc_mcontext.regs[0], FromPointerCast(&context)); - #elif defined(ARCH_CPU_MIPS_FAMILY) - EXPECT_EQ(context.uc_mcontext.gregs[4], FromPointerCast(&context)); -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ EXPECT_EQ(context.uc_mcontext.gp_regs[3], FromPointerCast(&context)); - #endif - } - -@@ -50,6 +52,8 @@ uintptr_t ProgramCounterFromContext(const NativeCPUContext& context) { - return context.uc_mcontext.pc; - #elif defined(ARCH_CPU_MIPS_FAMILY) - return context.uc_mcontext.pc; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ return context.uc_mcontext.gp_regs[PT_NIP]; - #endif - } - -@@ -64,6 +68,8 @@ uintptr_t StackPointerFromContext(const NativeCPUContext& context) { - return context.uc_mcontext.sp; - #elif defined(ARCH_CPU_MIPS_FAMILY) - return context.uc_mcontext.gregs[29]; -+#elif defined(ARCH_CPU_PPC64_FAMILY) -+ return context.uc_mcontext.gp_regs[1]; - #endif - } - -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/posix/signals_test.cc b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/posix/signals_test.cc -index 58bfa8f83..8fc37c464 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/posix/signals_test.cc -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/posix/signals_test.cc -@@ -46,12 +46,12 @@ bool CanCauseSignal(int sig) { - return sig == SIGABRT || - sig == SIGALRM || - sig == SIGBUS || --#if !defined(ARCH_CPU_ARM64) -+#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_PPC64) - sig == SIGFPE || --#endif // !defined(ARCH_CPU_ARM64) -+#endif // !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_PPC64) - #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARMEL) - sig == SIGILL || - #endif // defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARMEL) - sig == SIGPIPE || - sig == SIGSEGV || - #if defined(OS_MACOSX) -@@ -117,9 +117,11 @@ void CauseSignal(int sig) { - break; - } - --#if !defined(ARCH_CPU_ARM64) -+#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_PPC64) - // ARM64 has hardware integer division instructions that don’t generate a - // trap for divide-by-zero, so this doesn’t produce SIGFPE. -+ // -+ // PPC64 fixed-point division by zero also doesn't produce a SIGFPE. - case SIGFPE: { - // Optimization makes this tricky, so get zero from a system call likely - // to succeed, and try to do something with the result. -@@ -137,7 +139,7 @@ void CauseSignal(int sig) { - fstat(quotient, &stat_buf); - break; - } --#endif // ARCH_CPU_ARM64 -+#endif // !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_PPC64) - - #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARMEL) - case SIGILL: { -diff --git a/src/3rdparty/chromium/third_party/dav1d/BUILD.gn b/src/3rdparty/chromium/third_party/dav1d/BUILD.gn -index 788dc6cff..5fd7e8fda 100644 ---- a/src/3rdparty/chromium/third_party/dav1d/BUILD.gn -+++ b/src/3rdparty/chromium/third_party/dav1d/BUILD.gn -@@ -182,6 +182,8 @@ static_library("dav1d_8bit") { - sources += arm_template_sources - } else if (current_cpu == "arm64") { - sources += arm_template_sources -+ } else if (current_cpu == "ppc64") { -+ sources += ppc64_template_sources - } - - cflags = dav1d_copts -@@ -210,6 +212,8 @@ static_library("dav1d_10bit") { - sources += arm_template_sources - } else if (current_cpu == "arm64") { - sources += arm_template_sources -+ } else if (current_cpu == "ppc64") { -+ sources += ppc64_template_sources - } - - cflags = dav1d_copts -@@ -256,6 +260,21 @@ if (current_cpu == "x86" || current_cpu == "x64") { - ":dav1d_config", - ] - -+ cflags = dav1d_copts -+ } -+} else if (current_cpu == "ppc64") { -+ static_library("dav1d_ppc") { -+ sources = [ -+ "libdav1d/src/ppc/cpu.c", -+ "libdav1d/src/ppc/cpu.h", -+ ] -+ -+ configs -= [ "//build/config/compiler:chromium_code" ] -+ configs += [ -+ "//build/config/compiler:no_chromium_code", -+ ":dav1d_config", -+ ] -+ - cflags = dav1d_copts - } - } -@@ -285,5 +304,7 @@ static_library("dav1d") { - } - } else if (current_cpu == "arm" || current_cpu == "arm64") { - deps += [ ":dav1d_arm" ] -+ } else if (current_cpu == "ppc64") { -+ deps += [ ":dav1d_ppc" ] - } - } -diff --git a/src/3rdparty/chromium/third_party/dav1d/config/linux/ppc64/config.h b/src/3rdparty/chromium/third_party/dav1d/config/linux/ppc64/config.h -new file mode 100644 -index 000000000..9fbbf75cc ---- /dev/null -+++ b/src/3rdparty/chromium/third_party/dav1d/config/linux/ppc64/config.h -@@ -0,0 +1,39 @@ -+/* -+ * Autogenerated by the Meson build system. -+ * Do not edit, your changes will be lost. -+ */ -+ -+#pragma once -+ -+#define ARCH_AARCH64 0 -+ -+#define ARCH_ARM 0 -+ -+#define ARCH_PPC64LE 1 -+ -+#define ARCH_X86 0 -+ -+#define ARCH_X86_32 0 -+ -+#define ARCH_X86_64 0 -+ -+#define CONFIG_16BPC 1 -+ -+#define CONFIG_8BPC 1 -+ -+// #define CONFIG_LOG 1 -- Logging is controlled by Chromium -+ -+#define ENDIANNESS_BIG 0 -+ -+#define HAVE_ASM 1 -+ -+#define HAVE_CLOCK_GETTIME 1 -+ -+#define HAVE_DLSYM 1 -+ -+#define HAVE_GETAUXVAL 1 -+ -+#define HAVE_POSIX_MEMALIGN 1 -+ -+#define HAVE_UNISTD_H 1 -+ -diff --git a/src/3rdparty/chromium/third_party/dav1d/dav1d_generated.gni b/src/3rdparty/chromium/third_party/dav1d/dav1d_generated.gni -index 458935cd8..f0cbc4aed 100644 ---- a/src/3rdparty/chromium/third_party/dav1d/dav1d_generated.gni -+++ b/src/3rdparty/chromium/third_party/dav1d/dav1d_generated.gni -@@ -70,6 +70,11 @@ arm_template_sources = [ - "libdav1d/src/arm/mc_init_tmpl.c", - ] - -+ppc64_template_sources = [ -+ "libdav1d/src/ppc/cdef_init_tmpl.c", -+ "libdav1d/src/ppc/looprestoration_init_tmpl.c", -+] -+ - template_sources = [ - "libdav1d/src/cdef_apply_tmpl.c", - "libdav1d/src/cdef_tmpl.c", -diff --git a/src/3rdparty/chromium/third_party/dav1d/generate_source.py b/src/3rdparty/chromium/third_party/dav1d/generate_source.py -index 9ab5e00b8..ad3feffee 100755 ---- a/src/3rdparty/chromium/third_party/dav1d/generate_source.py -+++ b/src/3rdparty/chromium/third_party/dav1d/generate_source.py -@@ -50,7 +50,8 @@ def WriteGn(fd): - WriteArray(fd, "arm32_asm_sources", glob.glob("libdav1d/src/arm/32/*.S")) - WriteArray(fd, "arm64_asm_sources", glob.glob("libdav1d/src/arm/64/*.S")) - WriteArray(fd, "arm_template_sources", glob.glob("libdav1d/src/arm/*_tmpl.c")) -- -+ WriteArray(fd, "ppc64_template_sources", glob.glob("libdav1d/src/ppc/*_tmpl.c")) -+ - template_sources = glob.glob("libdav1d/src/*_tmpl.c") - WriteArray(fd, "template_sources", template_sources) - -diff --git a/src/3rdparty/chromium/third_party/dav1d/libdav1d/src/ppc/types.h b/src/3rdparty/chromium/third_party/dav1d/libdav1d/src/ppc/types.h -index 0b4bd72f0..a0caa5e71 100644 ---- a/src/3rdparty/chromium/third_party/dav1d/libdav1d/src/ppc/types.h -+++ b/src/3rdparty/chromium/third_party/dav1d/libdav1d/src/ppc/types.h -@@ -51,4 +51,19 @@ - #define u16l_to_i32(v) ((i32x4) vec_mergel((u16x8) v, vec_splat_u16(0))) - #define i16l_to_i32(v) ((i32x4) vec_unpackl((i16x8)v)) - -+#if defined(__clang__) -+#undef vec_splats -+#define vec_splats(N) \ -+ _Generic((N), \ -+ unsigned char: ((u8x16)(N)), \ -+ signed char: ((i8x16)(N)), \ -+ unsigned short: ((u16x8)(N)), \ -+ signed short: ((i16x8)(N)), \ -+ unsigned int: ((u32x4)(N)), \ -+ signed int: ((i32x4)(N)), \ -+ unsigned long long: ((u64x2)(N)), \ -+ signed long long: ((i64x2)(N)) \ -+ ) -+#endif -+ - #endif /* DAV1D_SRC_PPC_TYPES_H */ -diff --git a/src/3rdparty/chromium/third_party/libdrm/src/xf86drm.c b/src/3rdparty/chromium/third_party/libdrm/src/xf86drm.c -index b7d586591..cead05021 100644 ---- a/src/3rdparty/chromium/third_party/libdrm/src/xf86drm.c -+++ b/src/3rdparty/chromium/third_party/libdrm/src/xf86drm.c -@@ -51,10 +51,10 @@ - #include - #include - #include --#ifdef MAJOR_IN_MKDEV -+#if __has_include() - #include - #endif --#ifdef MAJOR_IN_SYSMACROS -+#if __has_include() - #include - #endif - #include -diff --git a/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h b/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -index 597d8b6e5..99d1ec0c7 100644 ---- a/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -+++ b/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -@@ -3931,7 +3931,7 @@ struct kernel_statfs { - LSS_REG(2, buf); - LSS_BODY(void*, mmap2, "0"(__r2)); - } --#else -+#elif !defined(__powerpc64__) /* ppc64 doesn't have mmap2 */ - #define __NR__mmap2 __NR_mmap2 - LSS_INLINE _syscall6(void*, _mmap2, void*, s, - size_t, l, int, p, -@@ -4042,7 +4042,7 @@ struct kernel_statfs { - #if defined(__i386__) || \ - defined(__ARM_ARCH_3__) || defined(__ARM_EABI__) || \ - (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32) || \ -- defined(__PPC__) || \ -+ (defined(__PPC__) && !defined(__powerpc64__)) || \ - (defined(__s390__) && !defined(__s390x__)) - /* On these architectures, implement mmap() with mmap2(). */ - LSS_INLINE void* LSS_NAME(mmap)(void *s, size_t l, int p, int f, int d, -diff --git a/src/3rdparty/chromium/third_party/pffft/src/pffft.c b/src/3rdparty/chromium/third_party/pffft/src/pffft.c -index bdac4d784..51e0f2cac 100644 ---- a/src/3rdparty/chromium/third_party/pffft/src/pffft.c -+++ b/src/3rdparty/chromium/third_party/pffft/src/pffft.c -@@ -100,6 +100,7 @@ - Altivec support macros - */ - #if !defined(PFFFT_SIMD_DISABLE) && (defined(__ppc__) || defined(__ppc64__)) -+#include - typedef vector float v4sf; - # define SIMD_SZ 4 - # define VZERO() ((vector float) vec_splat_u8(0)) -diff --git a/src/3rdparty/chromium/third_party/skia/src/sksl/SkSLString.cpp b/src/3rdparty/chromium/third_party/skia/src/sksl/SkSLString.cpp -index 88eb1c7d3..4be33fa5b 100644 ---- a/src/3rdparty/chromium/third_party/skia/src/sksl/SkSLString.cpp -+++ b/src/3rdparty/chromium/third_party/skia/src/sksl/SkSLString.cpp -@@ -240,7 +240,12 @@ String to_string(double value) { - if (needsDotZero) { - buffer << ".0"; - } -- return String(buffer.str().c_str()); -+ -+ std::string ret(buffer.str()); -+ if (signbit(value) && ret[0] == '.') { -+ ret[0] = '-'; -+ } -+ return String(ret.c_str()); - } - - SKSL_INT stoi(const String& s) { -diff --git a/src/3rdparty/chromium/third_party/sqlite/src/amalgamation/sqlite3.c b/src/3rdparty/chromium/third_party/sqlite/src/amalgamation/sqlite3.c -index 1b2c2ec7a..baa2b2a5d 100644 ---- a/src/3rdparty/chromium/third_party/sqlite/src/amalgamation/sqlite3.c -+++ b/src/3rdparty/chromium/third_party/sqlite/src/amalgamation/sqlite3.c -@@ -14400,7 +14400,8 @@ typedef INT16_TYPE LogEst; - # if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) -+ defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) || \ -+ defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - # elif defined(sparc) || defined(__ppc__) || \ - defined(__ARMEB__) || defined(__AARCH64EB__) -@@ -187118,7 +187119,7 @@ struct RtreeMatchArg { - #if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__arm__) -+ defined(__arm__) || defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - #elif defined(sparc) || defined(__ppc__) - # define SQLITE_BYTEORDER 4321 -diff --git a/src/3rdparty/chromium/third_party/sqlite/src/amalgamation_dev/sqlite3.c b/src/3rdparty/chromium/third_party/sqlite/src/amalgamation_dev/sqlite3.c -index 734ac355d..43fabe805 100644 ---- a/src/3rdparty/chromium/third_party/sqlite/src/amalgamation_dev/sqlite3.c -+++ b/src/3rdparty/chromium/third_party/sqlite/src/amalgamation_dev/sqlite3.c -@@ -14314,7 +14314,8 @@ typedef INT16_TYPE LogEst; - # if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) -+ defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) || \ -+ defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - # elif defined(sparc) || defined(__ppc__) || \ - defined(__ARMEB__) || defined(__AARCH64EB__) -@@ -186514,7 +186515,7 @@ struct RtreeMatchArg { - #if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__arm__) -+ defined(__arm__) || defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - #elif defined(sparc) || defined(__ppc__) - # define SQLITE_BYTEORDER 4321 -diff --git a/src/3rdparty/chromium/third_party/sqlite/src/ext/rtree/rtree.c b/src/3rdparty/chromium/third_party/sqlite/src/ext/rtree/rtree.c -index 1eef1a1b5..b53097b7f 100644 ---- a/src/3rdparty/chromium/third_party/sqlite/src/ext/rtree/rtree.c -+++ b/src/3rdparty/chromium/third_party/sqlite/src/ext/rtree/rtree.c -@@ -432,7 +432,7 @@ struct RtreeMatchArg { - #if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__arm__) -+ defined(__arm__) || defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - #elif defined(sparc) || defined(__ppc__) - # define SQLITE_BYTEORDER 4321 -diff --git a/src/3rdparty/chromium/third_party/sqlite/src/src/sqliteInt.h b/src/3rdparty/chromium/third_party/sqlite/src/src/sqliteInt.h -index 9ef2437b0..6c70148c7 100644 ---- a/src/3rdparty/chromium/third_party/sqlite/src/src/sqliteInt.h -+++ b/src/3rdparty/chromium/third_party/sqlite/src/src/sqliteInt.h -@@ -853,7 +853,8 @@ typedef INT16_TYPE LogEst; - # if defined(i386) || defined(__i386__) || defined(_M_IX86) || \ - defined(__x86_64) || defined(__x86_64__) || defined(_M_X64) || \ - defined(_M_AMD64) || defined(_M_ARM) || defined(__x86) || \ -- defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) -+ defined(__ARMEL__) || defined(__AARCH64EL__) || defined(_M_ARM64) || \ -+ defined(__powerpc64__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) - # define SQLITE_BYTEORDER 1234 - # elif defined(sparc) || defined(__ppc__) || \ - defined(__ARMEB__) || defined(__AARCH64EB__) -diff --git a/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc b/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc -index dd9ab457e..c005d9599 100644 ---- a/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc -+++ b/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc -@@ -30,11 +30,7 @@ - static bool (*diff_proc)(const uint8_t*, const uint8_t*) = nullptr; - - if (!diff_proc) { --#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) -- // For ARM and MIPS processors, always use C version. -- // TODO(hclam): Implement a NEON version. -- diff_proc = &VectorDifference_C; --#else -+#if defined(WEBRTC_ARCH_X86_FAMILY) - bool have_sse2 = GetCPUInfo(kSSE2) != 0; - // For x86 processors, check if SSE2 is supported. - if (have_sse2 && kBlockSize == 32) { -@@ -44,6 +40,10 @@ bool VectorDifference(const uint8_t* image1, const uint8_t* image2) { - } else { - diff_proc = &VectorDifference_C; - } -+#else -+ // For other processors, always use C version. -+ // TODO(hclam): Implement a NEON version. -+ diff_proc = &VectorDifference_C; - #endif - } - -diff --git a/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h b/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h -index ed216e660..25d36c071 100644 ---- a/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h -+++ b/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h -@@ -50,6 +50,18 @@ - #elif defined(__EMSCRIPTEN__) - #define WEBRTC_ARCH_32_BITS - #define WEBRTC_ARCH_LITTLE_ENDIAN -+#elif defined(__PPC__) -+#define WEBRTC_ARCH_PPC_FAMILY -+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ -+#define WEBRTC_ARCH_LITTLE_ENDIAN -+#else -+#define WEBRTC_ARCH_BIG_ENDIAN -+#endif -+#if defined(__LP64__) -+#define WEBRTC_ARCH_64_BITS -+#else -+#define WEBRTC_ARCH_32_BITS -+#endif - #else - #error Please add support for your architecture in rtc_base/system/arch.h - #endif -diff --git a/src/3rdparty/chromium/v8/BUILD.gn b/src/3rdparty/chromium/v8/BUILD.gn -index ab20142de..001921c59 100644 ---- a/src/3rdparty/chromium/v8/BUILD.gn -+++ b/src/3rdparty/chromium/v8/BUILD.gn -@@ -678,6 +678,12 @@ config("toolchain") { - } - if (host_byteorder == "little") { - defines += [ "V8_TARGET_ARCH_PPC_LE" ] -+ cflags += [ -+ # Enable usage of AltiVec, VSX, and other POWER8 and higher features -+ "-mcpu=power8", -+ "-maltivec", -+ "-mvsx", -+ ] - } else if (host_byteorder == "big") { - defines += [ "V8_TARGET_ARCH_PPC_BE" ] - if (current_os == "aix") { diff --git a/srcpkgs/qt5-webengine/patches/0091-chromium-ppc64le-musl.patch b/srcpkgs/qt5-webengine/patches/0091-chromium-ppc64le-musl.patch deleted file mode 100644 index 961f782e04a63..0000000000000 --- a/srcpkgs/qt5-webengine/patches/0091-chromium-ppc64le-musl.patch +++ /dev/null @@ -1,169 +0,0 @@ -diff --git a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -index a6aec544e..2a4a7f1bc 100644 ---- a/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -+++ b/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h -@@ -16,7 +16,7 @@ - #if defined(__mips__) - // sys/user.h in eglibc misses size_t definition - #include --#elif defined(__powerpc64__) -+#elif defined(__powerpc64__) && defined(__GLIBC__) - // Manually define greg_t on ppc64 - typedef unsigned long long greg_t; - #endif -@@ -361,11 +361,11 @@ typedef struct pt_regs regs_struct; - #define SECCOMP_ARCH AUDIT_ARCH_PPC64 - #endif - --#define SECCOMP_REG(_ctx, _reg) ((_ctx)->uc_mcontext.regs->gpr[_reg]) -+#define SECCOMP_REG(_ctx, _reg) (((struct pt_regs *)(_ctx)->uc_mcontext.regs)->gpr[_reg]) - - #define SECCOMP_RESULT(_ctx) SECCOMP_REG(_ctx, 3) - #define SECCOMP_SYSCALL(_ctx) SECCOMP_REG(_ctx, 0) --#define SECCOMP_IP(_ctx) (_ctx)->uc_mcontext.regs->nip -+#define SECCOMP_IP(_ctx) ((struct pt_regs *)(_ctx)->uc_mcontext.regs)->nip - #define SECCOMP_PARM1(_ctx) SECCOMP_REG(_ctx, 3) - #define SECCOMP_PARM2(_ctx) SECCOMP_REG(_ctx, 4) - #define SECCOMP_PARM3(_ctx) SECCOMP_REG(_ctx, 5) -diff --git a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -index 10fa5fd07..30b7b3851 100644 ---- a/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -+++ b/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc -@@ -497,9 +497,9 @@ void Syscall::PutValueInUcontext(intptr_t ret_val, ucontext_t* ctx) { - // Same as MIPS, need to invert ret and set error register (cr0.SO) - if (ret_val <= -1 && ret_val >= -4095) { - ret_val = -ret_val; -- ctx->uc_mcontext.regs->ccr |= (1 << 28); -+ ((struct pt_regs *)ctx->uc_mcontext.regs)->ccr |= (1 << 28); - } else { -- ctx->uc_mcontext.regs->ccr &= ~(1 << 28); -+ ((struct pt_regs *)ctx->uc_mcontext.regs)->ccr &= ~(1 << 28); - } - #endif - SECCOMP_RESULT(ctx) = static_cast(ret_val); -diff --git a/src/3rdparty/chromium/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.h b/src/3rdparty/chromium/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.h -index cdce9bf8a..73d77dda4 100644 ---- a/src/3rdparty/chromium/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.h -+++ b/src/3rdparty/chromium/third_party/abseil-cpp/absl/base/internal/unscaledcycleclock.h -@@ -46,7 +46,7 @@ - - // The following platforms have an implementation of a hardware counter. - #if defined(__i386__) || defined(__x86_64__) || defined(__aarch64__) || \ -- defined(__powerpc__) || defined(__ppc__) || \ -+ ((defined(__powerpc__) || defined(__ppc__)) && defined(__GLIBC__)) || \ - defined(_M_IX86) || defined(_M_X64) - #define ABSL_HAVE_UNSCALED_CYCLECLOCK_IMPLEMENTATION 1 - #else ---- a/src/3rdparty/chromium/third_party/abseil-cpp/absl/debugging/internal/stacktrace_config.h -+++ b/src/3rdparty/chromium/third_party/abseil-cpp/absl/debugging/internal/stacktrace_config.h -@@ -64,7 +64,7 @@ - #elif defined(__i386__) || defined(__x86_64__) - #define ABSL_STACKTRACE_INL_HEADER \ - "absl/debugging/internal/stacktrace_x86-inl.inc" --#elif defined(__ppc__) || defined(__PPC__) -+#elif (defined(__ppc__) || defined(__PPC__)) && defined(__GLIBC__) - #define ABSL_STACKTRACE_INL_HEADER \ - "absl/debugging/internal/stacktrace_powerpc-inl.inc" - #elif defined(__aarch64__) -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -index 03afec7a5..0264ecf13 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc -@@ -273,6 +273,9 @@ void ThreadInfo::FillCPUContext(RawContextCPU* out) const { - - #elif defined(__powerpc64__) - -+#include -+#include -+ - uintptr_t ThreadInfo::GetInstructionPointer() const { - return mcontext.gp_regs[PT_NIP]; - } -@@ -290,9 +293,9 @@ void ThreadInfo::FillCPUContext(RawContextCPU* out) const { - out->ctr = mcontext.gp_regs[PT_CTR]; - - for (int i = 0; i < MD_FLOATINGSAVEAREA_PPC_FPR_COUNT; i++) -- out->float_save.fpregs[i] = mcontext.fp_regs[i]; -+ out->float_save.fpregs[i] = ((uint64_t *)&mcontext.fp_regs)[i]; - -- out->float_save.fpscr = mcontext.fp_regs[NFPREG-1]; -+ out->float_save.fpscr = ((uint64_t *)&mcontext.fp_regs)[ELF_NFPREG-1]; - - for (int i = 0; i < MD_VECTORSAVEAREA_PPC_VR_COUNT; i++) - out->vector_save.save_vr[i] = \ -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -index 7620cf6f7..54e373611 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/ucontext_reader.cc -@@ -257,6 +257,9 @@ void UContextReader::FillCPUContext(RawContextCPU *out, const ucontext_t *uc) { - - #elif defined(__powerpc64__) - -+#include -+#include -+ - uintptr_t UContextReader::GetStackPointer(const ucontext_t* uc) { - return uc->uc_mcontext.gp_regs[MD_CONTEXT_PPC64_REG_SP]; - } -@@ -280,9 +283,9 @@ void UContextReader::FillCPUContext(RawContextCPU* out, const ucontext_t* uc, - out->ctr = uc->uc_mcontext.gp_regs[PT_CTR]; - - for (int i = 0; i < MD_FLOATINGSAVEAREA_PPC_FPR_COUNT; i++) -- out->float_save.fpregs[i] = uc->uc_mcontext.fp_regs[i]; -+ out->float_save.fpregs[i] = ((uint64_t *)&uc->uc_mcontext.fp_regs)[i]; - -- out->float_save.fpscr = uc->uc_mcontext.fp_regs[NFPREG-1]; -+ out->float_save.fpscr = ((uint64_t *)&uc->uc_mcontext.fp_regs)[ELF_NFPREG-1]; - - for (int i = 0; i < MD_VECTORSAVEAREA_PPC_VR_COUNT; i++) - out->vector_save.save_vr[i] = -diff --git a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -index 901cd68fb..561958c44 100644 ---- a/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -+++ b/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc -@@ -105,6 +105,11 @@ - #define PR_SET_PTRACER 0x59616d61 - #endif - -+/* musl hack, can't include asm/ptrace.h as that causes conflicts */ -+#if defined(__powerpc64__) && !defined(PT_NIP) -+#define PT_NIP 32 -+#endif -+ - namespace google_breakpad { - - namespace { -diff --git a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -index dea0d1f39..b203e5b2f 100644 ---- a/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -+++ b/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h -@@ -30,6 +30,7 @@ - - #if defined(ARCH_CPU_PPC64_FAMILY) - #include -+#include - #endif - - namespace crashpad { -diff --git a/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h b/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -index 9955ce44..4c1cc488 100644 ---- a/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -+++ b/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h -@@ -4216,9 +4216,17 @@ struct kernel_statfs { - } - #endif - #if defined(__NR_fstatat64) -+ // musl does #define fstatat64 fstatat -+ #ifndef __GLIBC__ -+ #undef fstatat64 -+ #endif - LSS_INLINE _syscall4(int, fstatat64, int, d, - const char *, p, - struct kernel_stat64 *, b, int, f) -+ // set it back like it was -+ #ifndef __GLIBC__ -+ #define fstatat64 fstatat -+ #endif - #endif - #if defined(__NR_waitpid) - // waitpid is polyfilled below when not available. diff --git a/srcpkgs/qt5-webengine/patches/0092-ppc64le-sandbox-linux-stat.patch b/srcpkgs/qt5-webengine/patches/0092-ppc64le-sandbox-linux-stat.patch deleted file mode 100644 index b3a439a0e162d..0000000000000 --- a/srcpkgs/qt5-webengine/patches/0092-ppc64le-sandbox-linux-stat.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h -+++ b/src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h -@@ -155,6 +155,28 @@ struct kernel_stat { - unsigned int __unused4; - unsigned int __unused5; - }; -+#elif defined(__powerpc64__) -+struct kernel_stat { -+ unsigned long st_dev; -+ unsigned long st_ino; -+ unsigned long st_nlink; -+ unsigned int st_mode; -+ unsigned int st_uid; -+ unsigned int st_gid; -+ unsigned long st_rdev; -+ long st_size; -+ unsigned long st_blksize; -+ unsigned long st_blocks; -+ unsigned long st_atime_; -+ unsigned long st_atime_nsec_; -+ unsigned long st_mtime_; -+ unsigned long st_mtime_nsec_; -+ unsigned long st_ctime_; -+ unsigned long st_ctime_nsec_; -+ unsigned long __unused4; -+ unsigned long __unused5; -+ unsigned long __unused6; -+}; - #endif - - // On 32-bit systems, we default to the 64-bit stat struct like libc diff --git a/srcpkgs/qt5-webengine/patches/0114-riscv64.patch b/srcpkgs/qt5-webengine/patches/0114-riscv64.patch new file mode 100644 index 0000000000000..58b852a10798b --- /dev/null +++ b/srcpkgs/qt5-webengine/patches/0114-riscv64.patch @@ -0,0 +1,2999 @@ +Index: qtwebengine-everywhere-src-5.15.7/configure.pri +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/configure.pri ++++ qtwebengine-everywhere-src-5.15.7/configure.pri +@@ -144,6 +144,7 @@ defineTest(qtConfTest_detectArch) { + contains(QT_ARCH, "arm")|contains(QT_ARCH, "arm64"): return(true) + contains(QT_ARCH, "mips"): return(true) + contains(QT_ARCH, "mips64"): return(true) ++ contains(QT_ARCH, "riscv64"): return(true) + qtLog("Architecture not supported.") + return(false) + } +Index: qtwebengine-everywhere-src-5.15.7/mkspecs/features/functions.prf +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/mkspecs/features/functions.prf ++++ qtwebengine-everywhere-src-5.15.7/mkspecs/features/functions.prf +@@ -107,6 +107,7 @@ defineReplace(gnArch) { + contains(qtArch, "mips"): return(mipsel) + contains(qtArch, "mips64"): return(mips64el) + contains(qtArch, "mips64el"): return(mips64el) ++ contains(qtArch, "riscv64"): return(riscv64) + return(unknown) + } + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/base/process/launch_posix.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/base/process/launch_posix.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/base/process/launch_posix.cc +@@ -704,7 +704,7 @@ NOINLINE pid_t CloneAndLongjmpInChild(un + alignas(16) char stack_buf[PTHREAD_STACK_MIN]; + #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ + defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_S390_FAMILY) || \ +- defined(ARCH_CPU_PPC64_FAMILY) ++ defined(ARCH_CPU_PPC64_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY) + // The stack grows downward. + void* stack = stack_buf + sizeof(stack_buf); + #else +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/build_config.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/build/build_config.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/build_config.h +@@ -193,6 +193,11 @@ + #define ARCH_CPU_32_BITS 1 + #define ARCH_CPU_BIG_ENDIAN 1 + #endif ++#elif defined(__riscv) && __riscv_xlen == 64 ++#define ARCH_CPU_RISCV_FAMILY 1 ++#define ARCH_CPU_RISCV64 1 ++#define ARCH_CPU_64_BITS 1 ++#define ARCH_CPU_LITTLE_ENDIAN 1 + #else + #error Please add support for your architecture in build/build_config.h + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/config/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/build/config/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/config/BUILD.gn +@@ -238,6 +238,7 @@ config("default_libs") { + "dl", + "pthread", + "rt", ++ "atomic", + ] + } + } +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/build/toolchain/linux/BUILD.gn +@@ -298,3 +298,20 @@ gcc_toolchain("mips64") { + is_clang = false + } + } ++ ++gcc_toolchain("riscv64") { ++ cc = "gcc" ++ cxx = "g++" ++ ++ readelf = "readelf" ++ nm = "nm" ++ ar = "ar" ++ ld = cxx ++ ++ toolchain_args = { ++ current_cpu = "riscv64" ++ current_os = "linux" ++ is_clang = false ++ } ++} ++ +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/features.gni +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/features.gni ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/features.gni +@@ -11,7 +11,8 @@ import("//build/config/nacl/config.gni") + use_seccomp_bpf = (is_linux || is_chromeos || is_android) && + (current_cpu == "x86" || current_cpu == "x64" || + current_cpu == "arm" || current_cpu == "arm64" || +- current_cpu == "mipsel" || current_cpu == "mips64el") ++ current_cpu == "mipsel" || current_cpu == "mips64el" || ++ current_cpu == "riscv64") + + use_seccomp_bpf = use_seccomp_bpf || is_nacl_nonsfi + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/bpf_dsl/linux_syscall_ranges.h +@@ -56,6 +56,12 @@ + #define MAX_PUBLIC_SYSCALL __NR_syscalls + #define MAX_SYSCALL MAX_PUBLIC_SYSCALL + ++#elif defined(__riscv) ++ ++#define MIN_SYSCALL 0u ++#define MAX_PUBLIC_SYSCALL 1024u ++#define MAX_SYSCALL MAX_PUBLIC_SYSCALL ++ + #else + #error "Unsupported architecture" + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/bpf_dsl/seccomp_macros.h +@@ -346,6 +346,46 @@ struct regs_struct { + #define SECCOMP_PT_PARM4(_regs) (_regs).regs[3] + #define SECCOMP_PT_PARM5(_regs) (_regs).regs[4] + #define SECCOMP_PT_PARM6(_regs) (_regs).regs[5] ++ ++#elif defined(__riscv) ++struct regs_struct { ++ unsigned long regs[32]; ++}; ++ ++#define SECCOMP_ARCH AUDIT_ARCH_RISCV64 ++ ++#define SECCOMP_REG(_ctx, _reg) ((_ctx)->uc_mcontext.__gregs[_reg]) ++ ++#define SECCOMP_RESULT(_ctx) SECCOMP_REG(_ctx, REG_A0) ++#define SECCOMP_SYSCALL(_ctx) SECCOMP_REG(_ctx, REG_A0+7) ++#define SECCOMP_IP(_ctx) (_ctx)->uc_mcontext.__gregs[REG_PC] ++#define SECCOMP_PARM1(_ctx) SECCOMP_REG(_ctx, REG_A0) ++#define SECCOMP_PARM2(_ctx) SECCOMP_REG(_ctx, REG_A0+1) ++#define SECCOMP_PARM3(_ctx) SECCOMP_REG(_ctx, REG_A0+2) ++#define SECCOMP_PARM4(_ctx) SECCOMP_REG(_ctx, REG_A0+3) ++#define SECCOMP_PARM5(_ctx) SECCOMP_REG(_ctx, REG_A0+4) ++#define SECCOMP_PARM6(_ctx) SECCOMP_REG(_ctx, REG_A0+5) ++ ++#define SECCOMP_NR_IDX (offsetof(struct arch_seccomp_data, nr)) ++#define SECCOMP_ARCH_IDX (offsetof(struct arch_seccomp_data, arch)) ++#define SECCOMP_IP_MSB_IDX \ ++ (offsetof(struct arch_seccomp_data, instruction_pointer) + 4) ++#define SECCOMP_IP_LSB_IDX \ ++ (offsetof(struct arch_seccomp_data, instruction_pointer) + 0) ++#define SECCOMP_ARG_MSB_IDX(nr) \ ++ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 4) ++#define SECCOMP_ARG_LSB_IDX(nr) \ ++ (offsetof(struct arch_seccomp_data, args) + 8 * (nr) + 0) ++ ++#define SECCOMP_PT_RESULT(_regs) (_regs).regs[REG_A0] ++#define SECCOMP_PT_SYSCALL(_regs) (_regs).regs[REG_A0+7] ++#define SECCOMP_PT_IP(_regs) (_regs).regs[REG_PC] ++#define SECCOMP_PT_PARM1(_regs) (_regs).regs[REG_A0] ++#define SECCOMP_PT_PARM2(_regs) (_regs).regs[REG_A0+1] ++#define SECCOMP_PT_PARM3(_regs) (_regs).regs[REG_A0+2] ++#define SECCOMP_PT_PARM4(_regs) (_regs).regs[REG_A0+3] ++#define SECCOMP_PT_PARM5(_regs) (_regs).regs[REG_A0+4] ++#define SECCOMP_PT_PARM6(_regs) (_regs).regs[REG_A0+5] + #else + #error Unsupported target platform + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/baseline_policy.cc +@@ -181,7 +181,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + return RestrictFcntlCommands(); + #endif + +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + // fork() is never used as a system call (clone() is used instead), but we + // have seen it in fallback code on Android. + if (sysno == __NR_fork) { +@@ -231,7 +231,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + } + + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + if (sysno == __NR_mmap) + return RestrictMmapFlags(); + #endif +@@ -249,7 +249,7 @@ ResultExpr EvaluateSyscallImpl(int fs_de + return RestrictPrctl(); + + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + if (sysno == __NR_socketpair) { + // Only allow AF_UNIX, PF_UNIX. Crash if anything else is seen. + static_assert(AF_UNIX == PF_UNIX, +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_parameters_restrictions.cc +@@ -37,7 +37,7 @@ + #include + #include + #if defined(OS_LINUX) && !defined(OS_CHROMEOS) && !defined(__arm__) && \ +- !defined(__aarch64__) && !defined(PTRACE_GET_THREAD_AREA) ++ !defined(__aarch64__) && !defined(__riscv) && !defined(PTRACE_GET_THREAD_AREA) + // Also include asm/ptrace-abi.h since ptrace.h in older libc (for instance + // the one in Ubuntu 16.04 LTS) is missing PTRACE_GET_THREAD_AREA. + // asm/ptrace-abi.h doesn't exist on arm32 and PTRACE_GET_THREAD_AREA isn't +@@ -406,7 +406,7 @@ ResultExpr RestrictPrlimitToGetrlimit(pi + ResultExpr RestrictPtrace() { + const Arg request(0); + return Switch(request).CASES(( +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + PTRACE_GETREGS, + PTRACE_GETFPREGS, + #if defined(TRACE_GET_THREAD_AREA) +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.cc +@@ -86,7 +86,7 @@ bool SyscallSets::IsUmask(int sysno) { + // Both EPERM and ENOENT are valid errno unless otherwise noted in comment. + bool SyscallSets::IsFileSystem(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_access: // EPERM not a valid errno. + case __NR_chmod: + case __NR_chown: +@@ -118,7 +118,7 @@ bool SyscallSets::IsFileSystem(int sysno + case __NR_faccessat: // EPERM not a valid errno. + case __NR_fchmodat: + case __NR_fchownat: // Should be called chownat ? +-#if defined(__x86_64__) || defined(__aarch64__) ++#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv) + case __NR_newfstatat: // fstatat(). EPERM not a valid errno. + #elif defined(__i386__) || defined(__arm__) || \ + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) +@@ -201,7 +201,7 @@ bool SyscallSets::IsAllowedFileSystemAcc + case __NR_oldfstat: + #endif + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_sync_file_range: // EPERM not a valid errno. + #elif defined(__arm__) + case __NR_arm_sync_file_range: // EPERM not a valid errno. +@@ -225,7 +225,7 @@ bool SyscallSets::IsDeniedFileSystemAcce + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) + case __NR_ftruncate64: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getdents: // EPERM not a valid errno. + #endif + case __NR_getdents64: // EPERM not a valid errno. +@@ -304,7 +304,7 @@ bool SyscallSets::IsProcessPrivilegeChan + bool SyscallSets::IsProcessGroupOrSession(int sysno) { + switch (sysno) { + case __NR_setpgid: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getpgrp: + #endif + case __NR_setsid: +@@ -333,7 +333,7 @@ bool SyscallSets::IsAllowedSignalHandlin + case __NR_rt_sigsuspend: + case __NR_rt_tgsigqueueinfo: + case __NR_sigaltstack: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_signalfd: + #endif + case __NR_signalfd4: +@@ -357,12 +357,12 @@ bool SyscallSets::IsAllowedOperationOnFd + switch (sysno) { + case __NR_close: + case __NR_dup: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_dup2: + #endif + case __NR_dup3: + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_shutdown: + #endif + return true; +@@ -401,7 +401,7 @@ bool SyscallSets::IsAllowedProcessStartO + return true; + case __NR_clone: // Should be parameter-restricted. + case __NR_setns: // Privileged. +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_fork: + #endif + #if defined(__i386__) || defined(__x86_64__) +@@ -412,7 +412,7 @@ bool SyscallSets::IsAllowedProcessStartO + #endif + case __NR_set_tid_address: + case __NR_unshare: +-#if !defined(__mips__) && !defined(__aarch64__) ++#if !defined(__mips__) && !defined(__aarch64__) && !defined(__riscv) + case __NR_vfork: + #endif + default: +@@ -433,7 +433,7 @@ bool SyscallSets::IsAllowedFutex(int sys + + bool SyscallSets::IsAllowedEpoll(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_epoll_create: + case __NR_epoll_wait: + #endif +@@ -454,14 +454,14 @@ bool SyscallSets::IsAllowedEpoll(int sys + + bool SyscallSets::IsAllowedGetOrModifySocket(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_pipe: + #endif + case __NR_pipe2: + return true; + default: + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_socketpair: // We will want to inspect its argument. + #endif + return false; +@@ -471,7 +471,7 @@ bool SyscallSets::IsAllowedGetOrModifySo + bool SyscallSets::IsDeniedGetOrModifySocket(int sysno) { + switch (sysno) { + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_accept: + case __NR_accept4: + case __NR_bind: +@@ -525,7 +525,7 @@ bool SyscallSets::IsAllowedAddressSpaceA + case __NR_mincore: + case __NR_mlockall: + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_mmap: + #endif + #if defined(__i386__) || defined(__arm__) || \ +@@ -558,7 +558,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) + case __NR__llseek: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_poll: + #endif + case __NR_ppoll: +@@ -571,7 +571,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + case __NR_recv: + #endif + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_recvfrom: // Could specify source. + case __NR_recvmsg: // Could specify source. + #endif +@@ -586,7 +586,7 @@ bool SyscallSets::IsAllowedGeneralIo(int + case __NR_send: + #endif + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_sendmsg: // Could specify destination. + case __NR_sendto: // Could specify destination. + #endif +@@ -636,7 +636,7 @@ bool SyscallSets::IsSeccomp(int sysno) { + bool SyscallSets::IsAllowedBasicScheduler(int sysno) { + switch (sysno) { + case __NR_sched_yield: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_pause: + #endif + case __NR_nanosleep: +@@ -720,7 +720,7 @@ bool SyscallSets::IsNuma(int sysno) { + case __NR_getcpu: + case __NR_mbind: + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_migrate_pages: + #endif + case __NR_move_pages: +@@ -749,7 +749,7 @@ bool SyscallSets::IsGlobalProcessEnviron + switch (sysno) { + case __NR_acct: // Privileged. + #if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + case __NR_getrlimit: + #endif + #if defined(__i386__) || defined(__arm__) +@@ -784,7 +784,7 @@ bool SyscallSets::IsDebug(int sysno) { + + bool SyscallSets::IsGlobalSystemStatus(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR__sysctl: + case __NR_sysfs: + #endif +@@ -802,7 +802,7 @@ bool SyscallSets::IsGlobalSystemStatus(i + + bool SyscallSets::IsEventFd(int sysno) { + switch (sysno) { +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_eventfd: + #endif + case __NR_eventfd2: +@@ -838,7 +838,8 @@ bool SyscallSets::IsKeyManagement(int sy + } + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + bool SyscallSets::IsSystemVSemaphores(int sysno) { + switch (sysno) { + case __NR_semctl: +@@ -854,7 +855,8 @@ bool SyscallSets::IsSystemVSemaphores(in + + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ + defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + // These give a lot of ambient authority and bypass the setuid sandbox. + bool SyscallSets::IsSystemVSharedMemory(int sysno) { + switch (sysno) { +@@ -870,7 +872,8 @@ bool SyscallSets::IsSystemVSharedMemory( + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + bool SyscallSets::IsSystemVMessageQueue(int sysno) { + switch (sysno) { + case __NR_msgctl: +@@ -901,7 +904,8 @@ bool SyscallSets::IsSystemVIpc(int sysno + + bool SyscallSets::IsAnySystemV(int sysno) { + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + return IsSystemVMessageQueue(sysno) || IsSystemVSemaphores(sysno) || + IsSystemVSharedMemory(sysno); + #elif defined(__i386__) || \ +@@ -934,7 +938,7 @@ bool SyscallSets::IsAdvancedScheduler(in + bool SyscallSets::IsInotify(int sysno) { + switch (sysno) { + case __NR_inotify_add_watch: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_inotify_init: + #endif + case __NR_inotify_init1: +@@ -1065,7 +1069,7 @@ bool SyscallSets::IsMisc(int sysno) { + #if defined(__x86_64__) + case __NR_tuxcall: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_vserver: + #endif + return true; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf-helpers/syscall_sets.h +@@ -49,7 +49,7 @@ class SANDBOX_EXPORT SyscallSets { + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__mips__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + static bool IsNetworkSocketInformation(int sysno); + #endif + +@@ -72,18 +72,21 @@ class SANDBOX_EXPORT SyscallSets { + static bool IsAsyncIo(int sysno); + static bool IsKeyManagement(int sysno); + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + static bool IsSystemVSemaphores(int sysno); + #endif + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ + defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + // These give a lot of ambient authority and bypass the setuid sandbox. + static bool IsSystemVSharedMemory(int sysno); + #endif + + #if defined(__x86_64__) || defined(__arm__) || defined(__aarch64__) || \ +- (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) ++ (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_64_BITS)) || \ ++ defined(__riscv) + static bool IsSystemVMessageQueue(int sysno); + #endif + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/seccomp-bpf/syscall.cc +@@ -18,7 +18,7 @@ namespace sandbox { + namespace { + + #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ +- defined(ARCH_CPU_MIPS_FAMILY) ++ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY) + // Number that's not currently used by any Linux kernel ABIs. + const int kInvalidSyscallNumber = 0x351d3; + #else +@@ -312,6 +312,28 @@ asm(// We need to be able to tell the ke + "2:ret\n" + ".cfi_endproc\n" + ".size SyscallAsm, .-SyscallAsm\n" ++#elif defined(__riscv) ++ ".text\n" ++ ".align 2\n" ++ ".type SyscallAsm, %function\n" ++ "SyscallAsm:\n" ++ ".cfi_startproc\n" ++ "bgez a0,1f\n" ++ "la a0,2f\n" ++ "j 2f\n" ++ "1:mv a7, a0\n" ++ "ld a0, (t0)\n" ++ "ld a1, 8(t0)\n" ++ "ld a2, 16(t0)\n" ++ "ld a3, 24(t0)\n" ++ "ld a4, 32(t0)\n" ++ "ld a5, 40(t0)\n" ++ "ld a6, 48(t0)\n" ++ // Enter the kernel ++ "scall\n" ++ "2:ret\n" ++ ".cfi_endproc\n" ++ ".size SyscallAsm, .-SyscallAsm\n" + #endif + ); // asm + +@@ -429,6 +451,18 @@ intptr_t Syscall::Call(int nr, + ret = inout; + } + ++#elif defined(__riscv) ++ intptr_t ret; ++ { ++ register intptr_t inout __asm__("a0") = nr; ++ register const intptr_t* data __asm__("t0") = args; ++ asm volatile("jal SyscallAsm\n" ++ : "+r"(inout) ++ : "r"(data) ++ : "memory", "a1", "a2", "a3", "a4", "a5", "a6"); ++ ret = inout; ++ } ++ + #else + #error "Unimplemented architecture" + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/services/credentials.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/services/credentials.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/services/credentials.cc +@@ -81,7 +81,7 @@ bool ChrootToSafeEmptyDir() { + pid_t pid = -1; + alignas(16) char stack_buf[PTHREAD_STACK_MIN]; + #if defined(ARCH_CPU_X86_FAMILY) || defined(ARCH_CPU_ARM_FAMILY) || \ +- defined(ARCH_CPU_MIPS_FAMILY) ++ defined(ARCH_CPU_MIPS_FAMILY) || defined(ARCH_CPU_RISCV_FAMILY) + // The stack grows downward. + void* stack = stack_buf + sizeof(stack_buf); + #else +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/syscall_broker/broker_process.cc +@@ -128,43 +128,43 @@ bool BrokerProcess::IsSyscallBrokerable( + // and are default disabled in Android. So, we should refuse to broker them + // to be consistent with the platform's restrictions. + switch (sysno) { +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_access: + #endif + case __NR_faccessat: + return !fast_check || allowed_command_set_.test(COMMAND_ACCESS); + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_mkdir: + #endif + case __NR_mkdirat: + return !fast_check || allowed_command_set_.test(COMMAND_MKDIR); + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_open: + #endif + case __NR_openat: + return !fast_check || allowed_command_set_.test(COMMAND_OPEN); + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_readlink: + #endif + case __NR_readlinkat: + return !fast_check || allowed_command_set_.test(COMMAND_READLINK); + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_rename: + #endif + case __NR_renameat: + case __NR_renameat2: + return !fast_check || allowed_command_set_.test(COMMAND_RENAME); + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_rmdir: + return !fast_check || allowed_command_set_.test(COMMAND_RMDIR); + #endif + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_stat: + case __NR_lstat: + #endif +@@ -174,7 +174,7 @@ bool BrokerProcess::IsSyscallBrokerable( + #if defined(__NR_fstatat64) + case __NR_fstatat64: + #endif +-#if defined(__x86_64__) || defined(__aarch64__) ++#if defined(__x86_64__) || defined(__aarch64__) || defined(__riscv) + case __NR_newfstatat: + #endif + return !fast_check || allowed_command_set_.test(COMMAND_STAT); +@@ -189,7 +189,7 @@ bool BrokerProcess::IsSyscallBrokerable( + return !fast_check || allowed_command_set_.test(COMMAND_STAT); + #endif + +-#if !defined(__aarch64__) && !defined(OS_ANDROID) ++#if !defined(__aarch64__) && !defined(OS_ANDROID) && !defined(__riscv) + case __NR_unlink: + return !fast_check || allowed_command_set_.test(COMMAND_UNLINK); + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_seccomp.h +@@ -41,6 +41,9 @@ + #ifndef EM_AARCH64 + #define EM_AARCH64 183 + #endif ++#ifndef EM_RISCV ++#define EM_RISCV 243 ++#endif + + #ifndef __AUDIT_ARCH_64BIT + #define __AUDIT_ARCH_64BIT 0x80000000 +@@ -73,6 +76,9 @@ + #ifndef AUDIT_ARCH_AARCH64 + #define AUDIT_ARCH_AARCH64 (EM_AARCH64 | __AUDIT_ARCH_64BIT | __AUDIT_ARCH_LE) + #endif ++#ifndef AUDIT_ARCH_RISCV64 ++#define AUDIT_ARCH_RISCV64 (EM_RISCV|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) ++#endif + + // For prctl.h + #ifndef PR_SET_SECCOMP +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_signal.h +@@ -13,7 +13,7 @@ + // (not undefined, but defined different values and in different memory + // layouts). So, fill the gap here. + #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) || \ +- defined(__aarch64__) ++ defined(__aarch64__) || defined(__riscv) + + #define LINUX_SIGHUP 1 + #define LINUX_SIGINT 2 +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_stat.h +@@ -132,7 +132,7 @@ struct kernel_stat { + int st_blocks; + int st_pad4[14]; + }; +-#elif defined(__aarch64__) ++#elif defined(__aarch64__) || defined(__riscv) + struct kernel_stat { + unsigned long st_dev; + unsigned long st_ino; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/linux_syscalls.h +@@ -35,5 +35,9 @@ + #include "sandbox/linux/system_headers/arm64_linux_syscalls.h" + #endif + ++#if defined(__riscv) && __riscv_xlen == 64 ++#include "sandbox/linux/system_headers/riscv64_linux_syscalls.h" ++#endif ++ + #endif // SANDBOX_LINUX_SYSTEM_HEADERS_LINUX_SYSCALLS_H_ + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/riscv64_linux_syscalls.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/linux/system_headers/riscv64_linux_syscalls.h +@@ -0,0 +1,1066 @@ ++// Copyright 2014 The Chromium Authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ ++#define SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ ++ ++#include ++ ++#if !defined(__NR_io_setup) ++#define __NR_io_setup 0 ++#endif ++ ++#if !defined(__NR_io_destroy) ++#define __NR_io_destroy 1 ++#endif ++ ++#if !defined(__NR_io_submit) ++#define __NR_io_submit 2 ++#endif ++ ++#if !defined(__NR_io_cancel) ++#define __NR_io_cancel 3 ++#endif ++ ++#if !defined(__NR_io_getevents) ++#define __NR_io_getevents 4 ++#endif ++ ++#if !defined(__NR_setxattr) ++#define __NR_setxattr 5 ++#endif ++ ++#if !defined(__NR_lsetxattr) ++#define __NR_lsetxattr 6 ++#endif ++ ++#if !defined(__NR_fsetxattr) ++#define __NR_fsetxattr 7 ++#endif ++ ++#if !defined(__NR_getxattr) ++#define __NR_getxattr 8 ++#endif ++ ++#if !defined(__NR_lgetxattr) ++#define __NR_lgetxattr 9 ++#endif ++ ++#if !defined(__NR_fgetxattr) ++#define __NR_fgetxattr 10 ++#endif ++ ++#if !defined(__NR_listxattr) ++#define __NR_listxattr 11 ++#endif ++ ++#if !defined(__NR_llistxattr) ++#define __NR_llistxattr 12 ++#endif ++ ++#if !defined(__NR_flistxattr) ++#define __NR_flistxattr 13 ++#endif ++ ++#if !defined(__NR_removexattr) ++#define __NR_removexattr 14 ++#endif ++ ++#if !defined(__NR_lremovexattr) ++#define __NR_lremovexattr 15 ++#endif ++ ++#if !defined(__NR_fremovexattr) ++#define __NR_fremovexattr 16 ++#endif ++ ++#if !defined(__NR_getcwd) ++#define __NR_getcwd 17 ++#endif ++ ++#if !defined(__NR_lookup_dcookie) ++#define __NR_lookup_dcookie 18 ++#endif ++ ++#if !defined(__NR_eventfd2) ++#define __NR_eventfd2 19 ++#endif ++ ++#if !defined(__NR_epoll_create1) ++#define __NR_epoll_create1 20 ++#endif ++ ++#if !defined(__NR_epoll_ctl) ++#define __NR_epoll_ctl 21 ++#endif ++ ++#if !defined(__NR_epoll_pwait) ++#define __NR_epoll_pwait 22 ++#endif ++ ++#if !defined(__NR_dup) ++#define __NR_dup 23 ++#endif ++ ++#if !defined(__NR_dup3) ++#define __NR_dup3 24 ++#endif ++ ++#if !defined(__NR_fcntl) ++#define __NR_fcntl 25 ++#endif ++ ++#if !defined(__NR_inotify_init1) ++#define __NR_inotify_init1 26 ++#endif ++ ++#if !defined(__NR_inotify_add_watch) ++#define __NR_inotify_add_watch 27 ++#endif ++ ++#if !defined(__NR_inotify_rm_watch) ++#define __NR_inotify_rm_watch 28 ++#endif ++ ++#if !defined(__NR_ioctl) ++#define __NR_ioctl 29 ++#endif ++ ++#if !defined(__NR_ioprio_set) ++#define __NR_ioprio_set 30 ++#endif ++ ++#if !defined(__NR_ioprio_get) ++#define __NR_ioprio_get 31 ++#endif ++ ++#if !defined(__NR_flock) ++#define __NR_flock 32 ++#endif ++ ++#if !defined(__NR_mknodat) ++#define __NR_mknodat 33 ++#endif ++ ++#if !defined(__NR_mkdirat) ++#define __NR_mkdirat 34 ++#endif ++ ++#if !defined(__NR_unlinkat) ++#define __NR_unlinkat 35 ++#endif ++ ++#if !defined(__NR_symlinkat) ++#define __NR_symlinkat 36 ++#endif ++ ++#if !defined(__NR_linkat) ++#define __NR_linkat 37 ++#endif ++ ++#if !defined(__NR_renameat) ++#define __NR_renameat 38 ++#endif ++ ++#if !defined(__NR_umount2) ++#define __NR_umount2 39 ++#endif ++ ++#if !defined(__NR_mount) ++#define __NR_mount 40 ++#endif ++ ++#if !defined(__NR_pivot_root) ++#define __NR_pivot_root 41 ++#endif ++ ++#if !defined(__NR_nfsservctl) ++#define __NR_nfsservctl 42 ++#endif ++ ++#if !defined(__NR_statfs) ++#define __NR_statfs 43 ++#endif ++ ++#if !defined(__NR_fstatfs) ++#define __NR_fstatfs 44 ++#endif ++ ++#if !defined(__NR_truncate) ++#define __NR_truncate 45 ++#endif ++ ++#if !defined(__NR_ftruncate) ++#define __NR_ftruncate 46 ++#endif ++ ++#if !defined(__NR_fallocate) ++#define __NR_fallocate 47 ++#endif ++ ++#if !defined(__NR_faccessat) ++#define __NR_faccessat 48 ++#endif ++ ++#if !defined(__NR_chdir) ++#define __NR_chdir 49 ++#endif ++ ++#if !defined(__NR_fchdir) ++#define __NR_fchdir 50 ++#endif ++ ++#if !defined(__NR_chroot) ++#define __NR_chroot 51 ++#endif ++ ++#if !defined(__NR_fchmod) ++#define __NR_fchmod 52 ++#endif ++ ++#if !defined(__NR_fchmodat) ++#define __NR_fchmodat 53 ++#endif ++ ++#if !defined(__NR_fchownat) ++#define __NR_fchownat 54 ++#endif ++ ++#if !defined(__NR_fchown) ++#define __NR_fchown 55 ++#endif ++ ++#if !defined(__NR_openat) ++#define __NR_openat 56 ++#endif ++ ++#if !defined(__NR_close) ++#define __NR_close 57 ++#endif ++ ++#if !defined(__NR_vhangup) ++#define __NR_vhangup 58 ++#endif ++ ++#if !defined(__NR_pipe2) ++#define __NR_pipe2 59 ++#endif ++ ++#if !defined(__NR_quotactl) ++#define __NR_quotactl 60 ++#endif ++ ++#if !defined(__NR_getdents64) ++#define __NR_getdents64 61 ++#endif ++ ++#if !defined(__NR_lseek) ++#define __NR_lseek 62 ++#endif ++ ++#if !defined(__NR_read) ++#define __NR_read 63 ++#endif ++ ++#if !defined(__NR_write) ++#define __NR_write 64 ++#endif ++ ++#if !defined(__NR_readv) ++#define __NR_readv 65 ++#endif ++ ++#if !defined(__NR_writev) ++#define __NR_writev 66 ++#endif ++ ++#if !defined(__NR_pread64) ++#define __NR_pread64 67 ++#endif ++ ++#if !defined(__NR_pwrite64) ++#define __NR_pwrite64 68 ++#endif ++ ++#if !defined(__NR_preadv) ++#define __NR_preadv 69 ++#endif ++ ++#if !defined(__NR_pwritev) ++#define __NR_pwritev 70 ++#endif ++ ++#if !defined(__NR_sendfile) ++#define __NR_sendfile 71 ++#endif ++ ++#if !defined(__NR_pselect6) ++#define __NR_pselect6 72 ++#endif ++ ++#if !defined(__NR_ppoll) ++#define __NR_ppoll 73 ++#endif ++ ++#if !defined(__NR_signalfd4) ++#define __NR_signalfd4 74 ++#endif ++ ++#if !defined(__NR_vmsplice) ++#define __NR_vmsplice 75 ++#endif ++ ++#if !defined(__NR_splice) ++#define __NR_splice 76 ++#endif ++ ++#if !defined(__NR_tee) ++#define __NR_tee 77 ++#endif ++ ++#if !defined(__NR_readlinkat) ++#define __NR_readlinkat 78 ++#endif ++ ++#if !defined(__NR_newfstatat) ++#define __NR_newfstatat 79 ++#endif ++ ++#if !defined(__NR_fstat) ++#define __NR_fstat 80 ++#endif ++ ++#if !defined(__NR_sync) ++#define __NR_sync 81 ++#endif ++ ++#if !defined(__NR_fsync) ++#define __NR_fsync 82 ++#endif ++ ++#if !defined(__NR_fdatasync) ++#define __NR_fdatasync 83 ++#endif ++ ++#if !defined(__NR_sync_file_range) ++#define __NR_sync_file_range 84 ++#endif ++ ++#if !defined(__NR_timerfd_create) ++#define __NR_timerfd_create 85 ++#endif ++ ++#if !defined(__NR_timerfd_settime) ++#define __NR_timerfd_settime 86 ++#endif ++ ++#if !defined(__NR_timerfd_gettime) ++#define __NR_timerfd_gettime 87 ++#endif ++ ++#if !defined(__NR_utimensat) ++#define __NR_utimensat 88 ++#endif ++ ++#if !defined(__NR_acct) ++#define __NR_acct 89 ++#endif ++ ++#if !defined(__NR_capget) ++#define __NR_capget 90 ++#endif ++ ++#if !defined(__NR_capset) ++#define __NR_capset 91 ++#endif ++ ++#if !defined(__NR_personality) ++#define __NR_personality 92 ++#endif ++ ++#if !defined(__NR_exit) ++#define __NR_exit 93 ++#endif ++ ++#if !defined(__NR_exit_group) ++#define __NR_exit_group 94 ++#endif ++ ++#if !defined(__NR_waitid) ++#define __NR_waitid 95 ++#endif ++ ++#if !defined(__NR_set_tid_address) ++#define __NR_set_tid_address 96 ++#endif ++ ++#if !defined(__NR_unshare) ++#define __NR_unshare 97 ++#endif ++ ++#if !defined(__NR_futex) ++#define __NR_futex 98 ++#endif ++ ++#if !defined(__NR_set_robust_list) ++#define __NR_set_robust_list 99 ++#endif ++ ++#if !defined(__NR_get_robust_list) ++#define __NR_get_robust_list 100 ++#endif ++ ++#if !defined(__NR_nanosleep) ++#define __NR_nanosleep 101 ++#endif ++ ++#if !defined(__NR_getitimer) ++#define __NR_getitimer 102 ++#endif ++ ++#if !defined(__NR_setitimer) ++#define __NR_setitimer 103 ++#endif ++ ++#if !defined(__NR_kexec_load) ++#define __NR_kexec_load 104 ++#endif ++ ++#if !defined(__NR_init_module) ++#define __NR_init_module 105 ++#endif ++ ++#if !defined(__NR_delete_module) ++#define __NR_delete_module 106 ++#endif ++ ++#if !defined(__NR_timer_create) ++#define __NR_timer_create 107 ++#endif ++ ++#if !defined(__NR_timer_gettime) ++#define __NR_timer_gettime 108 ++#endif ++ ++#if !defined(__NR_timer_getoverrun) ++#define __NR_timer_getoverrun 109 ++#endif ++ ++#if !defined(__NR_timer_settime) ++#define __NR_timer_settime 110 ++#endif ++ ++#if !defined(__NR_timer_delete) ++#define __NR_timer_delete 111 ++#endif ++ ++#if !defined(__NR_clock_settime) ++#define __NR_clock_settime 112 ++#endif ++ ++#if !defined(__NR_clock_gettime) ++#define __NR_clock_gettime 113 ++#endif ++ ++#if !defined(__NR_clock_getres) ++#define __NR_clock_getres 114 ++#endif ++ ++#if !defined(__NR_clock_nanosleep) ++#define __NR_clock_nanosleep 115 ++#endif ++ ++#if !defined(__NR_syslog) ++#define __NR_syslog 116 ++#endif ++ ++#if !defined(__NR_ptrace) ++#define __NR_ptrace 117 ++#endif ++ ++#if !defined(__NR_sched_setparam) ++#define __NR_sched_setparam 118 ++#endif ++ ++#if !defined(__NR_sched_setscheduler) ++#define __NR_sched_setscheduler 119 ++#endif ++ ++#if !defined(__NR_sched_getscheduler) ++#define __NR_sched_getscheduler 120 ++#endif ++ ++#if !defined(__NR_sched_getparam) ++#define __NR_sched_getparam 121 ++#endif ++ ++#if !defined(__NR_sched_setaffinity) ++#define __NR_sched_setaffinity 122 ++#endif ++ ++#if !defined(__NR_sched_getaffinity) ++#define __NR_sched_getaffinity 123 ++#endif ++ ++#if !defined(__NR_sched_yield) ++#define __NR_sched_yield 124 ++#endif ++ ++#if !defined(__NR_sched_get_priority_max) ++#define __NR_sched_get_priority_max 125 ++#endif ++ ++#if !defined(__NR_sched_get_priority_min) ++#define __NR_sched_get_priority_min 126 ++#endif ++ ++#if !defined(__NR_sched_rr_get_interval) ++#define __NR_sched_rr_get_interval 127 ++#endif ++ ++#if !defined(__NR_restart_syscall) ++#define __NR_restart_syscall 128 ++#endif ++ ++#if !defined(__NR_kill) ++#define __NR_kill 129 ++#endif ++ ++#if !defined(__NR_tkill) ++#define __NR_tkill 130 ++#endif ++ ++#if !defined(__NR_tgkill) ++#define __NR_tgkill 131 ++#endif ++ ++#if !defined(__NR_sigaltstack) ++#define __NR_sigaltstack 132 ++#endif ++ ++#if !defined(__NR_rt_sigsuspend) ++#define __NR_rt_sigsuspend 133 ++#endif ++ ++#if !defined(__NR_rt_sigaction) ++#define __NR_rt_sigaction 134 ++#endif ++ ++#if !defined(__NR_rt_sigprocmask) ++#define __NR_rt_sigprocmask 135 ++#endif ++ ++#if !defined(__NR_rt_sigpending) ++#define __NR_rt_sigpending 136 ++#endif ++ ++#if !defined(__NR_rt_sigtimedwait) ++#define __NR_rt_sigtimedwait 137 ++#endif ++ ++#if !defined(__NR_rt_sigqueueinfo) ++#define __NR_rt_sigqueueinfo 138 ++#endif ++ ++#if !defined(__NR_rt_sigreturn) ++#define __NR_rt_sigreturn 139 ++#endif ++ ++#if !defined(__NR_setpriority) ++#define __NR_setpriority 140 ++#endif ++ ++#if !defined(__NR_getpriority) ++#define __NR_getpriority 141 ++#endif ++ ++#if !defined(__NR_reboot) ++#define __NR_reboot 142 ++#endif ++ ++#if !defined(__NR_setregid) ++#define __NR_setregid 143 ++#endif ++ ++#if !defined(__NR_setgid) ++#define __NR_setgid 144 ++#endif ++ ++#if !defined(__NR_setreuid) ++#define __NR_setreuid 145 ++#endif ++ ++#if !defined(__NR_setuid) ++#define __NR_setuid 146 ++#endif ++ ++#if !defined(__NR_setresuid) ++#define __NR_setresuid 147 ++#endif ++ ++#if !defined(__NR_getresuid) ++#define __NR_getresuid 148 ++#endif ++ ++#if !defined(__NR_setresgid) ++#define __NR_setresgid 149 ++#endif ++ ++#if !defined(__NR_getresgid) ++#define __NR_getresgid 150 ++#endif ++ ++#if !defined(__NR_setfsuid) ++#define __NR_setfsuid 151 ++#endif ++ ++#if !defined(__NR_setfsgid) ++#define __NR_setfsgid 152 ++#endif ++ ++#if !defined(__NR_times) ++#define __NR_times 153 ++#endif ++ ++#if !defined(__NR_setpgid) ++#define __NR_setpgid 154 ++#endif ++ ++#if !defined(__NR_getpgid) ++#define __NR_getpgid 155 ++#endif ++ ++#if !defined(__NR_getsid) ++#define __NR_getsid 156 ++#endif ++ ++#if !defined(__NR_setsid) ++#define __NR_setsid 157 ++#endif ++ ++#if !defined(__NR_getgroups) ++#define __NR_getgroups 158 ++#endif ++ ++#if !defined(__NR_setgroups) ++#define __NR_setgroups 159 ++#endif ++ ++#if !defined(__NR_uname) ++#define __NR_uname 160 ++#endif ++ ++#if !defined(__NR_sethostname) ++#define __NR_sethostname 161 ++#endif ++ ++#if !defined(__NR_setdomainname) ++#define __NR_setdomainname 162 ++#endif ++ ++#if !defined(__NR_getrlimit) ++#define __NR_getrlimit 163 ++#endif ++ ++#if !defined(__NR_setrlimit) ++#define __NR_setrlimit 164 ++#endif ++ ++#if !defined(__NR_getrusage) ++#define __NR_getrusage 165 ++#endif ++ ++#if !defined(__NR_umask) ++#define __NR_umask 166 ++#endif ++ ++#if !defined(__NR_prctl) ++#define __NR_prctl 167 ++#endif ++ ++#if !defined(__NR_getcpu) ++#define __NR_getcpu 168 ++#endif ++ ++#if !defined(__NR_gettimeofday) ++#define __NR_gettimeofday 169 ++#endif ++ ++#if !defined(__NR_settimeofday) ++#define __NR_settimeofday 170 ++#endif ++ ++#if !defined(__NR_adjtimex) ++#define __NR_adjtimex 171 ++#endif ++ ++#if !defined(__NR_getpid) ++#define __NR_getpid 172 ++#endif ++ ++#if !defined(__NR_getppid) ++#define __NR_getppid 173 ++#endif ++ ++#if !defined(__NR_getuid) ++#define __NR_getuid 174 ++#endif ++ ++#if !defined(__NR_geteuid) ++#define __NR_geteuid 175 ++#endif ++ ++#if !defined(__NR_getgid) ++#define __NR_getgid 176 ++#endif ++ ++#if !defined(__NR_getegid) ++#define __NR_getegid 177 ++#endif ++ ++#if !defined(__NR_gettid) ++#define __NR_gettid 178 ++#endif ++ ++#if !defined(__NR_sysinfo) ++#define __NR_sysinfo 179 ++#endif ++ ++#if !defined(__NR_mq_open) ++#define __NR_mq_open 180 ++#endif ++ ++#if !defined(__NR_mq_unlink) ++#define __NR_mq_unlink 181 ++#endif ++ ++#if !defined(__NR_mq_timedsend) ++#define __NR_mq_timedsend 182 ++#endif ++ ++#if !defined(__NR_mq_timedreceive) ++#define __NR_mq_timedreceive 183 ++#endif ++ ++#if !defined(__NR_mq_notify) ++#define __NR_mq_notify 184 ++#endif ++ ++#if !defined(__NR_mq_getsetattr) ++#define __NR_mq_getsetattr 185 ++#endif ++ ++#if !defined(__NR_msgget) ++#define __NR_msgget 186 ++#endif ++ ++#if !defined(__NR_msgctl) ++#define __NR_msgctl 187 ++#endif ++ ++#if !defined(__NR_msgrcv) ++#define __NR_msgrcv 188 ++#endif ++ ++#if !defined(__NR_msgsnd) ++#define __NR_msgsnd 189 ++#endif ++ ++#if !defined(__NR_semget) ++#define __NR_semget 190 ++#endif ++ ++#if !defined(__NR_semctl) ++#define __NR_semctl 191 ++#endif ++ ++#if !defined(__NR_semtimedop) ++#define __NR_semtimedop 192 ++#endif ++ ++#if !defined(__NR_semop) ++#define __NR_semop 193 ++#endif ++ ++#if !defined(__NR_shmget) ++#define __NR_shmget 194 ++#endif ++ ++#if !defined(__NR_shmctl) ++#define __NR_shmctl 195 ++#endif ++ ++#if !defined(__NR_shmat) ++#define __NR_shmat 196 ++#endif ++ ++#if !defined(__NR_shmdt) ++#define __NR_shmdt 197 ++#endif ++ ++#if !defined(__NR_socket) ++#define __NR_socket 198 ++#endif ++ ++#if !defined(__NR_socketpair) ++#define __NR_socketpair 199 ++#endif ++ ++#if !defined(__NR_bind) ++#define __NR_bind 200 ++#endif ++ ++#if !defined(__NR_listen) ++#define __NR_listen 201 ++#endif ++ ++#if !defined(__NR_accept) ++#define __NR_accept 202 ++#endif ++ ++#if !defined(__NR_connect) ++#define __NR_connect 203 ++#endif ++ ++#if !defined(__NR_getsockname) ++#define __NR_getsockname 204 ++#endif ++ ++#if !defined(__NR_getpeername) ++#define __NR_getpeername 205 ++#endif ++ ++#if !defined(__NR_sendto) ++#define __NR_sendto 206 ++#endif ++ ++#if !defined(__NR_recvfrom) ++#define __NR_recvfrom 207 ++#endif ++ ++#if !defined(__NR_setsockopt) ++#define __NR_setsockopt 208 ++#endif ++ ++#if !defined(__NR_getsockopt) ++#define __NR_getsockopt 209 ++#endif ++ ++#if !defined(__NR_shutdown) ++#define __NR_shutdown 210 ++#endif ++ ++#if !defined(__NR_sendmsg) ++#define __NR_sendmsg 211 ++#endif ++ ++#if !defined(__NR_recvmsg) ++#define __NR_recvmsg 212 ++#endif ++ ++#if !defined(__NR_readahead) ++#define __NR_readahead 213 ++#endif ++ ++#if !defined(__NR_brk) ++#define __NR_brk 214 ++#endif ++ ++#if !defined(__NR_munmap) ++#define __NR_munmap 215 ++#endif ++ ++#if !defined(__NR_mremap) ++#define __NR_mremap 216 ++#endif ++ ++#if !defined(__NR_add_key) ++#define __NR_add_key 217 ++#endif ++ ++#if !defined(__NR_request_key) ++#define __NR_request_key 218 ++#endif ++ ++#if !defined(__NR_keyctl) ++#define __NR_keyctl 219 ++#endif ++ ++#if !defined(__NR_clone) ++#define __NR_clone 220 ++#endif ++ ++#if !defined(__NR_execve) ++#define __NR_execve 221 ++#endif ++ ++#if !defined(__NR_mmap) ++#define __NR_mmap 222 ++#endif ++ ++#if !defined(__NR_fadvise64) ++#define __NR_fadvise64 223 ++#endif ++ ++#if !defined(__NR_swapon) ++#define __NR_swapon 224 ++#endif ++ ++#if !defined(__NR_swapoff) ++#define __NR_swapoff 225 ++#endif ++ ++#if !defined(__NR_mprotect) ++#define __NR_mprotect 226 ++#endif ++ ++#if !defined(__NR_msync) ++#define __NR_msync 227 ++#endif ++ ++#if !defined(__NR_mlock) ++#define __NR_mlock 228 ++#endif ++ ++#if !defined(__NR_munlock) ++#define __NR_munlock 229 ++#endif ++ ++#if !defined(__NR_mlockall) ++#define __NR_mlockall 230 ++#endif ++ ++#if !defined(__NR_munlockall) ++#define __NR_munlockall 231 ++#endif ++ ++#if !defined(__NR_mincore) ++#define __NR_mincore 232 ++#endif ++ ++#if !defined(__NR_madvise) ++#define __NR_madvise 233 ++#endif ++ ++#if !defined(__NR_remap_file_pages) ++#define __NR_remap_file_pages 234 ++#endif ++ ++#if !defined(__NR_mbind) ++#define __NR_mbind 235 ++#endif ++ ++#if !defined(__NR_get_mempolicy) ++#define __NR_get_mempolicy 236 ++#endif ++ ++#if !defined(__NR_set_mempolicy) ++#define __NR_set_mempolicy 237 ++#endif ++ ++#if !defined(__NR_migrate_pages) ++#define __NR_migrate_pages 238 ++#endif ++ ++#if !defined(__NR_move_pages) ++#define __NR_move_pages 239 ++#endif ++ ++#if !defined(__NR_rt_tgsigqueueinfo) ++#define __NR_rt_tgsigqueueinfo 240 ++#endif ++ ++#if !defined(__NR_perf_event_open) ++#define __NR_perf_event_open 241 ++#endif ++ ++#if !defined(__NR_accept4) ++#define __NR_accept4 242 ++#endif ++ ++#if !defined(__NR_recvmmsg) ++#define __NR_recvmmsg 243 ++#endif ++ ++#if !defined(__NR_wait4) ++#define __NR_wait4 260 ++#endif ++ ++#if !defined(__NR_prlimit64) ++#define __NR_prlimit64 261 ++#endif ++ ++#if !defined(__NR_fanotify_init) ++#define __NR_fanotify_init 262 ++#endif ++ ++#if !defined(__NR_fanotify_mark) ++#define __NR_fanotify_mark 263 ++#endif ++ ++#if !defined(__NR_name_to_handle_at) ++#define __NR_name_to_handle_at 264 ++#endif ++ ++#if !defined(__NR_open_by_handle_at) ++#define __NR_open_by_handle_at 265 ++#endif ++ ++#if !defined(__NR_clock_adjtime) ++#define __NR_clock_adjtime 266 ++#endif ++ ++#if !defined(__NR_syncfs) ++#define __NR_syncfs 267 ++#endif ++ ++#if !defined(__NR_setns) ++#define __NR_setns 268 ++#endif ++ ++#if !defined(__NR_sendmmsg) ++#define __NR_sendmmsg 269 ++#endif ++ ++#if !defined(__NR_process_vm_readv) ++#define __NR_process_vm_readv 270 ++#endif ++ ++#if !defined(__NR_process_vm_writev) ++#define __NR_process_vm_writev 271 ++#endif ++ ++#if !defined(__NR_kcmp) ++#define __NR_kcmp 272 ++#endif ++ ++#if !defined(__NR_finit_module) ++#define __NR_finit_module 273 ++#endif ++ ++#if !defined(__NR_sched_setattr) ++#define __NR_sched_setattr 274 ++#endif ++ ++#if !defined(__NR_sched_getattr) ++#define __NR_sched_getattr 275 ++#endif ++ ++#if !defined(__NR_renameat2) ++#define __NR_renameat2 276 ++#endif ++ ++#if !defined(__NR_seccomp) ++#define __NR_seccomp 277 ++#endif ++ ++#if !defined(__NR_getrandom) ++#define __NR_getrandom 278 ++#endif ++ ++#if !defined(__NR_memfd_create) ++#define __NR_memfd_create 279 ++#endif ++ ++#endif // SANDBOX_LINUX_SYSTEM_HEADERS_RISCV64_LINUX_SYSCALLS_H_ +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/bpf_cros_amd_gpu_policy_linux.cc +@@ -38,7 +38,7 @@ ResultExpr CrosAmdGpuProcessPolicy::Eval + case __NR_sched_setscheduler: + case __NR_sysinfo: + case __NR_uname: +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_readlink: + case __NR_stat: + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/bpf_gpu_policy_linux.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/policy/linux/bpf_gpu_policy_linux.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/bpf_gpu_policy_linux.cc +@@ -70,7 +70,7 @@ ResultExpr GpuProcessPolicy::EvaluateSys + (defined(ARCH_CPU_MIPS_FAMILY) && defined(ARCH_CPU_32_BITS)) + case __NR_ftruncate64: + #endif +-#if !defined(__aarch64__) ++#if !defined(__aarch64__) && !defined(__riscv) + case __NR_getdents: + #endif + case __NR_getdents64: +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/sandbox_seccomp_bpf_linux.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/sandbox/policy/linux/sandbox_seccomp_bpf_linux.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/sandbox/policy/linux/sandbox_seccomp_bpf_linux.cc +@@ -64,7 +64,7 @@ using sandbox::bpf_dsl::ResultExpr; + + // Make sure that seccomp-bpf does not get disabled by mistake. Also make sure + // that we think twice about this when adding a new architecture. +-#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL) ++#if !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL) && !defined(ARCH_CPU_RISCV64) + #error "Seccomp-bpf disabled on supported architecture!" + #endif // !defined(ARCH_CPU_ARM64) && !defined(ARCH_CPU_MIPS64EL) + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/skia/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/skia/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/skia/BUILD.gn +@@ -821,6 +821,8 @@ skia_source_set("skia_opts") { + sources = skia_opts.none_sources + } else if (current_cpu == "s390x") { + sources = skia_opts.none_sources ++ } else if (current_cpu == "riscv64") { ++ sources = skia_opts.none_sources + } else { + assert(false, "Need to port cpu specific stuff from skia_library_opts.gyp") + } +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/angle/gni/angle.gni +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/angle/gni/angle.gni ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/angle/gni/angle.gni +@@ -54,7 +54,7 @@ angle_data_dir = "angledata" + declare_args() { + if (current_cpu == "arm64" || current_cpu == "x64" || + current_cpu == "mips64el" || current_cpu == "s390x" || +- current_cpu == "ppc64") { ++ current_cpu == "ppc64" || current_cpu == "riscv64") { + angle_64bit_current_cpu = true + } else if (current_cpu == "arm" || current_cpu == "x86" || + current_cpu == "mipsel" || current_cpu == "s390" || +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/angle/include/platform/PlatformMethods.h +@@ -9,6 +9,7 @@ + #ifndef ANGLE_PLATFORMMETHODS_H + #define ANGLE_PLATFORMMETHODS_H + ++#include + #include + #include + #include +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/BUILD.gn +@@ -38,6 +38,8 @@ if (current_cpu == "x86" || current_cpu + sources = [ "SaveRegisters_mips64.S" ] + } else if (current_cpu == "ppc64") { + sources = [ "SaveRegisters_ppc64.S" ] ++ } else if (current_cpu == "riscv64") { ++ sources = [ "SaveRegisters_riscv64.S" ] + } + + if (current_cpu == "arm") { +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/blink/renderer/platform/heap/asm/SaveRegisters_riscv64.S +@@ -0,0 +1,45 @@ ++/* ++ * typedef void (*PushAllRegistersCallback)(ThreadState*, intptr_t*); ++ * extern "C" void PushAllRegisters(ThreadState*, PushAllRegistersCallback) ++ */ ++ ++.type PushAllRegisters, %function ++.global PushAllRegisters ++.hidden PushAllRegisters ++PushAllRegisters: ++ /* Push all callee-saves registers to get them ++ * on the stack for conservative stack scanning. ++ * Reserve space for callee-saved registers and return address. ++ */ ++ addi sp,sp,-112 ++ /* Save the callee-saved registers and the return address. */ ++ sd ra,0(sp) ++ sd s0,8(sp) ++ sd s1,16(sp) ++ sd s2,24(sp) ++ sd s3,32(sp) ++ sd s4,40(sp) ++ sd s5,48(sp) ++ sd s6,56(sp) ++ sd s7,64(sp) ++ sd s8,72(sp) ++ sd s9,80(sp) ++ sd s10,88(sp) ++ sd s11,96(sp) ++ /* Note: the callee-saved floating point registers do not need to be ++ * copied to the stack, because fp registers never hold heap pointers ++ * and so do not need to be kept visible to the garbage collector. ++ * Pass the first argument untouched in a0 and the ++ * stack pointer to the callback. ++ */ ++ mv ra,a1 ++ mv a1,sp ++ jalr ra ++ /* Restore return address, adjust stack and return. ++ * Note: the copied registers do not need to be reloaded here, ++ * because they were preserved by the called routine. ++ */ ++ ld ra,0(sp) ++ addi sp,sp,112 ++ ret ++.size PushAllRegisters, . - PushAllRegisters +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/boringssl/src/include/openssl/base.h +@@ -114,6 +114,8 @@ extern "C" { + #define OPENSSL_32_BIT + #elif defined(__myriad2__) + #define OPENSSL_32_BIT ++#elif defined(__riscv) && __riscv_xlen == 64 ++#define OPENSSL_64_BIT + #else + // Note BoringSSL only supports standard 32-bit and 64-bit two's-complement, + // little-endian architectures. Functions will not produce the correct answer +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/raw_context_cpu.h +@@ -44,6 +44,8 @@ typedef MDRawContextARM RawContextCPU; + typedef MDRawContextARM64_Old RawContextCPU; + #elif defined(__mips__) + typedef MDRawContextMIPS RawContextCPU; ++#elif defined(__riscv) ++typedef MDRawContextRISCV64 RawContextCPU; + #else + #error "This code has not been ported to your platform yet." + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.cc +@@ -270,7 +270,23 @@ void ThreadInfo::FillCPUContext(RawConte + out->float_save.fir = mcontext.fpc_eir; + #endif + } +-#endif // __mips__ ++#elif defined(__riscv) ++ ++uintptr_t ThreadInfo::GetInstructionPointer() const { ++ return mcontext.__gregs[REG_PC]; ++} ++ ++void ThreadInfo::FillCPUContext(RawContextCPU* out) const { ++ out->context_flags = MD_CONTEXT_RISCV64_FULL; ++ ++ my_memcpy (out->iregs, mcontext.__gregs, MD_CONTEXT_RISCV64_GPR_COUNT * 8); ++ ++ out->float_save.fcsr = mcontext.__fpregs.__d.__fcsr; ++ my_memcpy(&out->float_save.regs, &mcontext.__fpregs.__d.__f, ++ MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT * 8); ++} ++ ++#endif // __riscv + + void ThreadInfo::GetGeneralPurposeRegisters(void** gp_regs, size_t* size) { + assert(gp_regs || size); +@@ -279,6 +295,11 @@ void ThreadInfo::GetGeneralPurposeRegist + *gp_regs = mcontext.gregs; + if (size) + *size = sizeof(mcontext.gregs); ++#elif defined(__riscv) ++ if (gp_regs) ++ *gp_regs = mcontext.__gregs; ++ if (size) ++ *size = sizeof(mcontext.__gregs); + #else + if (gp_regs) + *gp_regs = ®s; +@@ -294,6 +315,11 @@ void ThreadInfo::GetFloatingPointRegiste + *fp_regs = &mcontext.fpregs; + if (size) + *size = sizeof(mcontext.fpregs); ++#elif defined(__riscv) ++ if (fp_regs) ++ *fp_regs = &mcontext.__fpregs; ++ if (size) ++ *size = sizeof(mcontext.__fpregs); + #else + if (fp_regs) + *fp_regs = &fpregs; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/dump_writer_common/thread_info.h +@@ -68,7 +68,7 @@ struct ThreadInfo { + // Use the structures defined in + struct user_regs_struct regs; + struct user_fpsimd_struct fpregs; +-#elif defined(__mips__) ++#elif defined(__mips__) || defined(__riscv) + // Use the structure defined in . + mcontext_t mcontext; + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.cc +@@ -461,7 +461,7 @@ bool ExceptionHandler::HandleSignal(int + memcpy(&g_crash_context_.float_state, fp_ptr, + sizeof(g_crash_context_.float_state)); + } +-#elif !defined(__ARM_EABI__) && !defined(__mips__) ++#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + // FP state is not part of user ABI on ARM Linux. + // In case of MIPS Linux FP state is already part of ucontext_t + // and 'float_state' is not a member of CrashContext. +@@ -701,7 +701,7 @@ bool ExceptionHandler::WriteMinidump() { + } + #endif + +-#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__aarch64__) && !defined(__mips__) && !defined(__riscv) + // FPU state is not part of ARM EABI ucontext_t. + memcpy(&context.float_state, context.context.uc_mcontext.fpregs, + sizeof(context.float_state)); +@@ -726,6 +726,9 @@ bool ExceptionHandler::WriteMinidump() { + #elif defined(__mips__) + context.siginfo.si_addr = + reinterpret_cast(context.context.uc_mcontext.pc); ++#elif defined(__riscv) ++ context.siginfo.si_addr = ++ reinterpret_cast(context.context.uc_mcontext.__gregs[REG_PC]); + #else + #error "This code has not been ported to your platform yet." + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/handler/exception_handler.h +@@ -192,7 +192,7 @@ class ExceptionHandler { + siginfo_t siginfo; + pid_t tid; // the crashing thread. + ucontext_t context; +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + // #ifdef this out because FP state is not part of user ABI for Linux ARM. + // In case of MIPS Linux FP state is already part of ucontext_t so + // 'float_state' is not required. +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/microdump_writer/microdump_writer.cc +@@ -138,7 +138,7 @@ class MicrodumpWriter { + const MicrodumpExtraInfo& microdump_extra_info, + LinuxDumper* dumper) + : ucontext_(context ? &context->context : NULL), +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + float_state_(context ? &context->float_state : NULL), + #endif + dumper_(dumper), +@@ -337,6 +337,12 @@ class MicrodumpWriter { + # else + # error "This mips ABI is currently not supported (n32)" + #endif ++#elif defined(__riscv) ++# if __riscv_xlen == 64 ++ const char kArch[] = "riscv64"; ++# else ++# error "This RISC-V ABI is currently not supported" ++#endif + #else + #error "This code has not been ported to your platform yet" + #endif +@@ -409,7 +415,7 @@ class MicrodumpWriter { + void DumpCPUState() { + RawContextCPU cpu; + my_memset(&cpu, 0, sizeof(RawContextCPU)); +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + UContextReader::FillCPUContext(&cpu, ucontext_, float_state_); + #else + UContextReader::FillCPUContext(&cpu, ucontext_); +@@ -605,7 +611,7 @@ class MicrodumpWriter { + void* Alloc(unsigned bytes) { return dumper_->allocator()->Alloc(bytes); } + + const ucontext_t* const ucontext_; +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + const google_breakpad::fpstate_t* const float_state_; + #endif + LinuxDumper* dumper_; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_core_dumper.cc +@@ -112,6 +112,9 @@ bool LinuxCoreDumper::GetThreadInfoByInd + #elif defined(__mips__) + stack_pointer = + reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); ++#elif defined(__riscv) ++ stack_pointer = ++ reinterpret_cast(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]); + #else + #error "This code hasn't been ported to your platform yet." + #endif +@@ -208,6 +211,8 @@ bool LinuxCoreDumper::EnumerateThreads() + info.mcontext.mdlo = status->pr_reg[EF_LO]; + info.mcontext.mdhi = status->pr_reg[EF_HI]; + info.mcontext.pc = status->pr_reg[EF_CP0_EPC]; ++#elif defined(__riscv) ++ memcpy(info.mcontext.__gregs, status->pr_reg, sizeof(info.mcontext.__gregs)); + #else // __mips__ + memcpy(&info.regs, status->pr_reg, sizeof(info.regs)); + #endif // __mips__ +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_dumper.h +@@ -63,7 +63,8 @@ namespace google_breakpad { + (defined(__mips__) && _MIPS_SIM == _ABIO32) + typedef Elf32_auxv_t elf_aux_entry; + #elif defined(__x86_64) || defined(__aarch64__) || \ +- (defined(__mips__) && _MIPS_SIM != _ABIO32) ++ (defined(__mips__) && _MIPS_SIM != _ABIO32) || \ ++ (defined(__riscv) && __riscv_xlen == 64) + typedef Elf64_auxv_t elf_aux_entry; + #endif + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/linux_ptrace_dumper.cc +@@ -298,6 +298,9 @@ bool LinuxPtraceDumper::GetThreadInfoByI + #elif defined(__mips__) + stack_pointer = + reinterpret_cast(info->mcontext.gregs[MD_CONTEXT_MIPS_REG_SP]); ++#elif defined(__riscv) ++ stack_pointer = ++ reinterpret_cast(info->mcontext.__gregs[MD_CONTEXT_RISCV64_REG_SP]); + #else + #error "This code hasn't been ported to your platform yet." + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.cc +@@ -136,7 +136,7 @@ class MinidumpWriter { + : fd_(minidump_fd), + path_(minidump_path), + ucontext_(context ? &context->context : NULL), +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + float_state_(context ? &context->float_state : NULL), + #endif + dumper_(dumper), +@@ -468,7 +468,7 @@ class MinidumpWriter { + if (!cpu.Allocate()) + return false; + my_memset(cpu.get(), 0, sizeof(RawContextCPU)); +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + UContextReader::FillCPUContext(cpu.get(), ucontext_, float_state_); + #else + UContextReader::FillCPUContext(cpu.get(), ucontext_); +@@ -897,7 +897,7 @@ class MinidumpWriter { + dirent->location.rva = 0; + } + +-#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) ++#if defined(__i386__) || defined(__x86_64__) || defined(__mips__) || defined(__riscv) + bool WriteCPUInformation(MDRawSystemInfo* sys_info) { + char vendor_id[sizeof(sys_info->cpu.x86_cpu_info.vendor_id) + 1] = {0}; + static const char vendor_id_name[] = "vendor_id"; +@@ -925,6 +925,12 @@ class MinidumpWriter { + # else + # error "This mips ABI is currently not supported (n32)" + #endif ++#elif defined(__riscv) ++# if __riscv_xlen == 64 ++ MD_CPU_ARCHITECTURE_RISCV64; ++# else ++# error "This RISC-V ABI is currently not supported" ++# endif + #elif defined(__i386__) + MD_CPU_ARCHITECTURE_X86; + #else +@@ -1333,7 +1339,7 @@ class MinidumpWriter { + const char* path_; // Path to the file where the minidum should be written. + + const ucontext_t* const ucontext_; // also from the signal handler +-#if !defined(__ARM_EABI__) && !defined(__mips__) ++#if !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + const google_breakpad::fpstate_t* const float_state_; // ditto + #endif + LinuxDumper* dumper_; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/client/linux/minidump_writer/minidump_writer.h +@@ -48,7 +48,7 @@ class ExceptionHandler; + + #if defined(__aarch64__) + typedef struct fpsimd_context fpstate_t; +-#elif !defined(__ARM_EABI__) && !defined(__mips__) ++#elif !defined(__ARM_EABI__) && !defined(__mips__) && !defined(__riscv) + typedef std::remove_pointer::type fpstate_t; + #endif + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/breakpad_getcontext.S +@@ -481,6 +481,68 @@ breakpad_getcontext: + .cfi_endproc + .size breakpad_getcontext, . - breakpad_getcontext + ++#elif defined(__riscv) && __riscv_xlen == 64 ++ ++#define __NR_rt_sigprocmask 135 ++#define _NSIG8 64 / 8 ++#define SIG_BLOCK 0 ++ ++ .text ++ .global breakpad_getcontext ++ .hidden breakpad_getcontext ++ .type breakpad_getcontext, @function ++ .align 2 ++breakpad_getcontext: ++ sd ra, MCONTEXT_GREGS_OFFSET + 0*8(a0) ++ sd ra, MCONTEXT_GREGS_OFFSET + 1*8(a0) ++ sd sp, MCONTEXT_GREGS_OFFSET + 2*8(a0) ++ sd s0, MCONTEXT_GREGS_OFFSET + 8*8(a0) ++ sd s1, MCONTEXT_GREGS_OFFSET + 9*8(a0) ++ sd x0, MCONTEXT_GREGS_OFFSET + 10*8(a0) /* return 0 by overwriting a0. */ ++ sd s2, MCONTEXT_GREGS_OFFSET + 18*8(a0) ++ sd s3, MCONTEXT_GREGS_OFFSET + 19*8(a0) ++ sd s4, MCONTEXT_GREGS_OFFSET + 20*8(a0) ++ sd s5, MCONTEXT_GREGS_OFFSET + 21*8(a0) ++ sd s6, MCONTEXT_GREGS_OFFSET + 22*8(a0) ++ sd s7, MCONTEXT_GREGS_OFFSET + 23*8(a0) ++ sd s8, MCONTEXT_GREGS_OFFSET + 24*8(a0) ++ sd s9, MCONTEXT_GREGS_OFFSET + 25*8(a0) ++ sd s10, MCONTEXT_GREGS_OFFSET + 26*8(a0) ++ sd s11, MCONTEXT_GREGS_OFFSET + 27*8(a0) ++ ++#ifndef __riscv_float_abi_soft ++ frsr a1 ++ ++ fsd fs0, MCONTEXT_FPREGS_OFFSET + 8*8(a0) ++ fsd fs1, MCONTEXT_FPREGS_OFFSET + 9*8(a0) ++ fsd fs2, MCONTEXT_FPREGS_OFFSET + 18*8(a0) ++ fsd fs3, MCONTEXT_FPREGS_OFFSET + 19*8(a0) ++ fsd fs4, MCONTEXT_FPREGS_OFFSET + 20*8(a0) ++ fsd fs5, MCONTEXT_FPREGS_OFFSET + 21*8(a0) ++ fsd fs6, MCONTEXT_FPREGS_OFFSET + 22*8(a0) ++ fsd fs7, MCONTEXT_FPREGS_OFFSET + 23*8(a0) ++ fsd fs8, MCONTEXT_FPREGS_OFFSET + 24*8(a0) ++ fsd fs9, MCONTEXT_FPREGS_OFFSET + 25*8(a0) ++ fsd fs10, MCONTEXT_FPREGS_OFFSET + 26*8(a0) ++ fsd fs11, MCONTEXT_FPREGS_OFFSET + 27*8(a0) ++ ++ sw a1, MCONTEXT_FSR_OFFSET(a0) ++#endif /* __riscv_float_abi_soft */ ++ ++/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG / 8) */ ++ li a3, _NSIG8 ++ add a2, a0, UCONTEXT_SIGMASK_OFFSET ++ mv a1, zero ++ li a0, SIG_BLOCK ++ ++ li a7, __NR_rt_sigprocmask ++ scall ++ ++ /* Always return 0 for success, even if sigprocmask failed. */ ++ mv a0, zero ++ ret ++ .size breakpad_getcontext, . - breakpad_getcontext ++ + #else + #error "This file has not been ported for your CPU!" + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/memory_mapped_file.cc +@@ -65,7 +65,8 @@ bool MemoryMappedFile::Map(const char* p + } + + #if defined(__x86_64__) || defined(__aarch64__) || \ +- (defined(__mips__) && _MIPS_SIM == _ABI64) ++ (defined(__mips__) && _MIPS_SIM == _ABI64) || \ ++ (defined(__riscv) && __riscv_xlen == 64) + + struct kernel_stat st; + if (sys_fstat(fd, &st) == -1 || st.st_size < 0) { +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/common/linux/ucontext_constants.h +@@ -146,6 +146,14 @@ + #endif + #define FPREGS_OFFSET_MXCSR 24 + ++#elif defined(__riscv) ++ ++#define UCONTEXT_SIGMASK_OFFSET 40 ++ ++#define MCONTEXT_GREGS_OFFSET 176 ++#define MCONTEXT_FPREGS_OFFSET 432 ++#define MCONTEXT_FSR_OFFSET (MCONTEXT_FPREGS_OFFSET + 32*8) ++ + #else + #error "This header has not been ported for your CPU" + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_cpu_riscv64.h +@@ -0,0 +1,121 @@ ++/* Copyright 2013 Google Inc. ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are ++ * met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following disclaimer ++ * in the documentation and/or other materials provided with the ++ * distribution. ++ * * Neither the name of Google Inc. nor the names of its ++ * contributors may be used to endorse or promote products derived from ++ * this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ++ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ++ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ++ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ++ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ++ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ++ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ++ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* minidump_format.h: A cross-platform reimplementation of minidump-related ++ * portions of DbgHelp.h from the Windows Platform SDK. ++ * ++ * (This is C99 source, please don't corrupt it with C++.) ++ * ++ * This file contains the necessary definitions to read minidump files ++ * produced on ARM. These files may be read on any platform provided ++ * that the alignments of these structures on the processing system are ++ * identical to the alignments of these structures on the producing system. ++ * For this reason, precise-sized types are used. The structures defined ++ * by this file have been laid out to minimize alignment problems by ++ * ensuring that all members are aligned on their natural boundaries. ++ * In some cases, tail-padding may be significant when different ABIs specify ++ * different tail-padding behaviors. To avoid problems when reading or ++ * writing affected structures, MD_*_SIZE macros are provided where needed, ++ * containing the useful size of the structures without padding. ++ * ++ * Structures that are defined by Microsoft to contain a zero-length array ++ * are instead defined here to contain an array with one element, as ++ * zero-length arrays are forbidden by standard C and C++. In these cases, ++ * *_minsize constants are provided to be used in place of sizeof. For a ++ * cleaner interface to these sizes when using C++, see minidump_size.h. ++ * ++ * These structures are also sufficient to populate minidump files. ++ * ++ * Because precise data type sizes are crucial for this implementation to ++ * function properly and portably, a set of primitive types with known sizes ++ * are used as the basis of each structure defined by this file. ++ * ++ * Author: Colin Blundell ++ */ ++ ++/* ++ * RISCV64 support ++ */ ++ ++#ifndef GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ ++#define GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ ++ ++#include "google_breakpad/common/breakpad_types.h" ++ ++#define MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT 32 ++#define MD_CONTEXT_RISCV64_GPR_COUNT 32 ++ ++typedef struct { ++ /* 32 64-bit floating point registers, f0 .. f31. */ ++ uint64_t regs[MD_FLOATINGSAVEAREA_RISCV64_FPR_COUNT]; ++ ++ uint32_t fcsr; /* FPU control and status register */ ++} MDFloatingSaveAreaRISCV64; ++ ++/* For (MDRawContextRISCV64).context_flags. These values indicate the type of ++ * context stored in the structure. */ ++#define MD_CONTEXT_RISCV64 0x00400000 ++#define MD_CONTEXT_RISCV64_CONTROL (MD_CONTEXT_RISCV64 | 0x00000001) ++#define MD_CONTEXT_RISCV64_INTEGER (MD_CONTEXT_RISCV64 | 0x00000002) ++#define MD_CONTEXT_RISCV64_FLOATING_POINT (MD_CONTEXT_RISCV64 | 0x00000004) ++#define MD_CONTEXT_RISCV64_DEBUG (MD_CONTEXT_RISCV64 | 0x00000008) ++#define MD_CONTEXT_RISCV64_FULL (MD_CONTEXT_RISCV64_CONTROL | \ ++ MD_CONTEXT_RISCV64_INTEGER | \ ++ MD_CONTEXT_RISCV64_FLOATING_POINT) ++#define MD_CONTEXT_RISCV64_ALL (MD_CONTEXT_RISCV64_FULL | MD_CONTEXT_RISCV64_DEBUG) ++ ++typedef struct { ++ /* Determines which fields of this struct are populated */ ++ uint32_t context_flags; ++ ++ /* 32 64-bit integer registers, x1 .. x31 + the PC ++ * Note the following fixed uses: ++ * x8 is the frame pointer ++ * x1 is the link register ++ * x2 is the stack pointer ++ * The PC is effectively x0. ++ */ ++ uint64_t iregs[MD_CONTEXT_RISCV64_GPR_COUNT]; ++ ++ /* The next field is included with MD_CONTEXT64_ARM_FLOATING_POINT */ ++ MDFloatingSaveAreaRISCV64 float_save; ++ ++} MDRawContextRISCV64; ++ ++/* Indices into iregs for registers with a dedicated or conventional ++ * purpose. ++ */ ++enum MDRISCV64RegisterNumbers { ++ MD_CONTEXT_RISCV64_REG_FP = 8, ++ MD_CONTEXT_RISCV64_REG_RA = 1, ++ MD_CONTEXT_RISCV64_REG_SP = 2, ++ MD_CONTEXT_RISCV64_REG_PC = 0 ++}; ++ ++#endif /* GOOGLE_BREAKPAD_COMMON_MINIDUMP_CPU_RISCV64_H__ */ +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/breakpad/breakpad/src/google_breakpad/common/minidump_format.h +@@ -118,6 +118,7 @@ typedef struct { + #include "minidump_cpu_mips.h" + #include "minidump_cpu_ppc.h" + #include "minidump_cpu_ppc64.h" ++#include "minidump_cpu_riscv64.h" + #include "minidump_cpu_sparc.h" + #include "minidump_cpu_x86.h" + +@@ -660,6 +661,7 @@ typedef enum { + MD_CPU_ARCHITECTURE_PPC64 = 0x8002, /* Breakpad-defined value for PPC64 */ + MD_CPU_ARCHITECTURE_ARM64_OLD = 0x8003, /* Breakpad-defined value for ARM64 */ + MD_CPU_ARCHITECTURE_MIPS64 = 0x8004, /* Breakpad-defined value for MIPS64 */ ++ MD_CPU_ARCHITECTURE_RISCV64 = 0x8005, /* Breakpad-defined value for RISCV64 */ + MD_CPU_ARCHITECTURE_UNKNOWN = 0xffff /* PROCESSOR_ARCHITECTURE_UNKNOWN */ + } MDCPUArchitecture; + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/ptracer.cc +@@ -398,6 +398,51 @@ bool GetThreadArea64(pid_t tid, + return true; + } + ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ ++template ++bool GetRegisterSet(pid_t tid, int set, Destination* dest, bool can_log) { ++ iovec iov; ++ iov.iov_base = dest; ++ iov.iov_len = sizeof(*dest); ++ if (ptrace(PTRACE_GETREGSET, tid, reinterpret_cast(set), &iov) != 0) { ++ PLOG_IF(ERROR, can_log) << "ptrace"; ++ return false; ++ } ++ if (iov.iov_len != sizeof(*dest)) { ++ LOG_IF(ERROR, can_log) << "Unexpected registers size"; ++ return false; ++ } ++ return true; ++} ++ ++bool GetFloatingPointRegisters32(pid_t tid, ++ FloatContext* context, ++ bool can_log) { ++ return false; ++} ++ ++bool GetFloatingPointRegisters64(pid_t tid, ++ FloatContext* context, ++ bool can_log) { ++ return GetRegisterSet(tid, NT_PRFPREG, &context->f64.f, can_log); ++} ++ ++bool GetThreadArea32(pid_t tid, ++ const ThreadContext& context, ++ LinuxVMAddress* address, ++ bool can_log) { ++ return false; ++} ++ ++bool GetThreadArea64(pid_t tid, ++ const ThreadContext& context, ++ LinuxVMAddress* address, ++ bool can_log) { ++ *address = context.t64.tp; ++ return true; ++} ++ + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/crashpad/crashpad/util/linux/thread_info.h +@@ -79,6 +79,40 @@ union ThreadContext { + uint32_t cp0_status; + uint32_t cp0_cause; + uint32_t padding1_; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Reflects user_regs_struct in asm/ptrace.h. ++ uint32_t pc; ++ uint32_t ra; ++ uint32_t sp; ++ uint32_t gp; ++ uint32_t tp; ++ uint32_t t0; ++ uint32_t t1; ++ uint32_t t2; ++ uint32_t s0; ++ uint32_t s1; ++ uint32_t a0; ++ uint32_t a1; ++ uint32_t a2; ++ uint32_t a3; ++ uint32_t a4; ++ uint32_t a5; ++ uint32_t a6; ++ uint32_t a7; ++ uint32_t s2; ++ uint32_t s3; ++ uint32_t s4; ++ uint32_t s5; ++ uint32_t s6; ++ uint32_t s7; ++ uint32_t s8; ++ uint32_t s9; ++ uint32_t s10; ++ uint32_t s11; ++ uint32_t t3; ++ uint32_t t4; ++ uint32_t t5; ++ uint32_t t6; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -132,6 +166,40 @@ union ThreadContext { + uint64_t cp0_badvaddr; + uint64_t cp0_status; + uint64_t cp0_cause; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ // Reflects user_regs_struct in asm/ptrace.h. ++ uint64_t pc; ++ uint64_t ra; ++ uint64_t sp; ++ uint64_t gp; ++ uint64_t tp; ++ uint64_t t0; ++ uint64_t t1; ++ uint64_t t2; ++ uint64_t s0; ++ uint64_t s1; ++ uint64_t a0; ++ uint64_t a1; ++ uint64_t a2; ++ uint64_t a3; ++ uint64_t a4; ++ uint64_t a5; ++ uint64_t a6; ++ uint64_t a7; ++ uint64_t s2; ++ uint64_t s3; ++ uint64_t s4; ++ uint64_t s5; ++ uint64_t s6; ++ uint64_t s7; ++ uint64_t s8; ++ uint64_t s9; ++ uint64_t s10; ++ uint64_t s11; ++ uint64_t t3; ++ uint64_t t4; ++ uint64_t t5; ++ uint64_t t6; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -143,11 +211,12 @@ union ThreadContext { + using NativeThreadContext = user_regs; + #elif defined(ARCH_CPU_MIPS_FAMILY) + // No appropriate NativeThreadsContext type available for MIPS ++#elif defined(ARCH_CPU_RISCV_FAMILY) + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY || ARCH_CPU_ARM64 + +-#if !defined(ARCH_CPU_MIPS_FAMILY) ++#if !defined(ARCH_CPU_MIPS_FAMILY) && !defined(ARCH_CPU_RISCV_FAMILY) + #if defined(ARCH_CPU_32_BITS) + static_assert(sizeof(t32_t) == sizeof(NativeThreadContext), "Size mismatch"); + #else // ARCH_CPU_64_BITS +@@ -218,6 +287,9 @@ union FloatContext { + } fpregs[32]; + uint32_t fpcsr; + uint32_t fpu_id; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ uint64_t f[32]; ++ uint32_t fcsr; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -252,6 +324,9 @@ union FloatContext { + double fpregs[32]; + uint32_t fpcsr; + uint32_t fpu_id; ++#elif defined(ARCH_CPU_RISCV_FAMILY) ++ uint64_t f[32]; ++ uint32_t fcsr; + #else + #error Port. + #endif // ARCH_CPU_X86_FAMILY +@@ -280,6 +355,7 @@ union FloatContext { + static_assert(sizeof(f64) == sizeof(user_fpsimd_struct), "Size mismatch"); + #elif defined(ARCH_CPU_MIPS_FAMILY) + // No appropriate floating point context native type for available MIPS. ++#elif defined(ARCH_CPU_RISCV_FAMILY) + #else + #error Port. + #endif // ARCH_CPU_X86 +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/dav1d/config/linux/riscv64/config.h +@@ -0,0 +1,38 @@ ++/* ++ * Autogenerated by the Meson build system. ++ * Do not edit, your changes will be lost. ++ */ ++ ++#pragma once ++ ++#define ARCH_AARCH64 0 ++ ++#define ARCH_ARM 0 ++ ++#define ARCH_PPC64LE 0 ++ ++#define ARCH_X86 0 ++ ++#define ARCH_X86_32 0 ++ ++#define ARCH_X86_64 0 ++ ++#define CONFIG_16BPC 1 ++ ++#define CONFIG_8BPC 1 ++ ++// #define CONFIG_LOG 1 -- Logging is controlled by Chromium ++ ++#define ENDIANNESS_BIG 0 ++ ++#define HAVE_ASM 0 ++ ++#define HAVE_AS_FUNC 0 ++ ++#define HAVE_CLOCK_GETTIME 1 ++ ++#define HAVE_GETAUXVAL 1 ++ ++#define HAVE_POSIX_MEMALIGN 1 ++ ++#define HAVE_UNISTD_H 1 +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/lss/linux_syscall_support.h +@@ -88,7 +88,7 @@ + */ + #if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) || \ + defined(__mips__) || defined(__PPC__) || defined(__ARM_EABI__) || \ +- defined(__aarch64__) || defined(__s390__)) \ ++ defined(__aarch64__) || defined(__s390__) || defined(__riscv)) \ + && (defined(__linux) || defined(__ANDROID__)) + + #ifndef SYS_CPLUSPLUS +@@ -301,7 +301,7 @@ struct kernel_old_sigaction { + } __attribute__((packed,aligned(4))); + #elif (defined(__mips__) && _MIPS_SIM == _MIPS_SIM_ABI32) + #define kernel_old_sigaction kernel_sigaction +-#elif defined(__aarch64__) ++#elif defined(__aarch64__) || defined(__riscv) + // No kernel_old_sigaction defined for arm64. + #endif + +@@ -519,7 +519,7 @@ struct kernel_stat { + int st_blocks; + int st_pad4[14]; + }; +-#elif defined(__aarch64__) ++#elif defined(__aarch64__) || defined(__riscv) + struct kernel_stat { + unsigned long st_dev; + unsigned long st_ino; +@@ -1065,7 +1065,7 @@ struct kernel_statfs { + #define __NR_getrandom (__NR_SYSCALL_BASE + 384) + #endif + /* End of ARM 3/EABI definitions */ +-#elif defined(__aarch64__) ++#elif defined(__aarch64__) || defined(__riscv) + #ifndef __NR_setxattr + #define __NR_setxattr 5 + #endif +@@ -1880,7 +1880,7 @@ struct kernel_statfs { + + #undef LSS_RETURN + #if (defined(__i386__) || defined(__x86_64__) || defined(__ARM_ARCH_3__) \ +- || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__)) ++ || defined(__ARM_EABI__) || defined(__aarch64__) || defined(__s390__) || defined(__riscv)) + /* Failing system calls return a negative result in the range of + * -1..-4095. These are "errno" values with the sign inverted. + */ +@@ -3373,6 +3373,122 @@ struct kernel_statfs { + } + LSS_RETURN(int, __ret); + } ++ #elif defined(__riscv) ++ #undef LSS_REG ++ #define LSS_REG(r,a) register int64_t __r##r __asm__("a"#r) = (int64_t)a ++ #undef LSS_BODY ++ #define LSS_BODY(type,name,args...) \ ++ register int64_t __res_a0 __asm__("a0"); \ ++ register int64_t __a7 __asm__("a7") = __NR_##name; \ ++ int64_t __res; \ ++ __asm__ __volatile__ ("scall\n" \ ++ : "=r"(__res_a0) \ ++ : "r"(__a7) , ## args \ ++ : "memory"); \ ++ __res = __res_a0; \ ++ LSS_RETURN(type, __res) ++ #undef _syscall0 ++ #define _syscall0(type, name) \ ++ type LSS_NAME(name)(void) { \ ++ LSS_BODY(type, name); \ ++ } ++ #undef _syscall1 ++ #define _syscall1(type, name, type1, arg1) \ ++ type LSS_NAME(name)(type1 arg1) { \ ++ LSS_REG(0, arg1); LSS_BODY(type, name, "r"(__r0)); \ ++ } ++ #undef _syscall2 ++ #define _syscall2(type, name, type1, arg1, type2, arg2) \ ++ type LSS_NAME(name)(type1 arg1, type2 arg2) { \ ++ LSS_REG(0, arg1); LSS_REG(1, arg2); \ ++ LSS_BODY(type, name, "r"(__r0), "r"(__r1)); \ ++ } ++ #undef _syscall3 ++ #define _syscall3(type, name, type1, arg1, type2, arg2, type3, arg3) \ ++ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3) { \ ++ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \ ++ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2)); \ ++ } ++ #undef _syscall4 ++ #define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ ++ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \ ++ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \ ++ LSS_REG(3, arg4); \ ++ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3)); \ ++ } ++ #undef _syscall5 ++ #define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ ++ type5,arg5) \ ++ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \ ++ type5 arg5) { \ ++ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \ ++ LSS_REG(3, arg4); LSS_REG(4, arg5); \ ++ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \ ++ "r"(__r4)); \ ++ } ++ #undef _syscall6 ++ #define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4, \ ++ type5,arg5,type6,arg6) \ ++ type LSS_NAME(name)(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \ ++ type5 arg5, type6 arg6) { \ ++ LSS_REG(0, arg1); LSS_REG(1, arg2); LSS_REG(2, arg3); \ ++ LSS_REG(3, arg4); LSS_REG(4, arg5); LSS_REG(5, arg6); \ ++ LSS_BODY(type, name, "r"(__r0), "r"(__r1), "r"(__r2), "r"(__r3), \ ++ "r"(__r4), "r"(__r5)); \ ++ } ++ ++ LSS_INLINE int LSS_NAME(clone)(int (*fn)(void *), void *child_stack, ++ int flags, void *arg, int *parent_tidptr, ++ void *newtls, int *child_tidptr) { ++ int64_t __res; ++ { ++ register int64_t __res_a0 __asm__("a0"); ++ register uint64_t __flags __asm__("a0") = flags; ++ register void *__stack __asm__("a1") = child_stack; ++ register void *__ptid __asm__("a2") = parent_tidptr; ++ register void *__tls __asm__("a3") = newtls; ++ register int *__ctid __asm__("a4") = child_tidptr; ++ __asm__ __volatile__(/* Push "arg" and "fn" onto the stack that will be ++ * used by the child. ++ */ ++ "addi %2,%2,-16\n" ++ "sd %1, 0(%2)\n" ++ "sd %4, 8(%2)\n" ++ ++ /* %a0 = syscall(%a0 = flags, ++ * %a1 = child_stack, ++ * %a2 = parent_tidptr, ++ * %a3 = newtls, ++ * %a4 = child_tidptr) ++ */ ++ "li a7, %8\n" ++ "scall\n" ++ ++ /* if (%a0 != 0) ++ * return %a0; ++ */ ++ "bnez %0, 1f\n" ++ ++ /* In the child, now. Call "fn(arg)". ++ */ ++ "ld a1, 0(sp)\n" ++ "ld a0, 8(sp)\n" ++ "jalr a1\n" ++ ++ /* Call _exit(%a0). ++ */ ++ "li a7, %9\n" ++ "scall\n" ++ "1:\n" ++ : "=r" (__res_a0) ++ : "r"(fn), "r"(__stack), "r"(__flags), "r"(arg), ++ "r"(__ptid), "r"(__tls), "r"(__ctid), ++ "i"(__NR_clone), "i"(__NR_exit) ++ : "cc", "memory"); ++ __res = __res_a0; ++ } ++ LSS_RETURN(int, __res); ++ } + #endif + #define __NR__exit __NR_exit + #define __NR__gettid __NR_gettid +@@ -4181,7 +4297,7 @@ struct kernel_statfs { + LSS_SC_BODY(4, int, 8, d, type, protocol, sv); + } + #endif +- #if defined(__ARM_EABI__) || defined (__aarch64__) ++ #if defined(__ARM_EABI__) || defined (__aarch64__) || defined(__riscv) + LSS_INLINE _syscall3(ssize_t, recvmsg, int, s, struct kernel_msghdr*, msg, + int, flags) + LSS_INLINE _syscall3(ssize_t, sendmsg, int, s, const struct kernel_msghdr*, +@@ -4503,7 +4619,7 @@ struct kernel_statfs { + // TODO: define this in an arch-independant way instead of inlining the clone + // syscall body. + +-# if defined(__aarch64__) ++# if defined(__aarch64__) || defined(__riscv) + LSS_INLINE pid_t LSS_NAME(fork)(void) { + // No fork syscall on aarch64 - implement by means of the clone syscall. + // Note that this does not reset glibc's cached view of the PID/TID, so +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/swiftshader/third_party/llvm-10.0/BUILD.gn +@@ -149,6 +149,7 @@ swiftshader_llvm_source_set("swiftshader + deps += [ ":swiftshader_llvm_ppc" ] + } else if (current_cpu == "x86" || current_cpu == "x64") { + deps += [ ":swiftshader_llvm_x86" ] ++ } else if (current_cpu == "riscv64") { + } else { + assert(false, "Unsupported current_cpu") + } +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/webrtc/modules/desktop_capture/differ_block.cc +@@ -30,7 +30,7 @@ bool VectorDifference(const uint8_t* ima + static bool (*diff_proc)(const uint8_t*, const uint8_t*) = nullptr; + + if (!diff_proc) { +-#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) ++#if defined(WEBRTC_ARCH_ARM_FAMILY) || defined(WEBRTC_ARCH_MIPS_FAMILY) || defined(WEBRTC_ARCH_RISCV_FAMILY) + // For ARM and MIPS processors, always use C version. + // TODO(hclam): Implement a NEON version. + diff_proc = &VectorDifference_C; +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/chromium/third_party/webrtc/rtc_base/system/arch.h +@@ -50,6 +50,10 @@ + #elif defined(__EMSCRIPTEN__) + #define WEBRTC_ARCH_32_BITS + #define WEBRTC_ARCH_LITTLE_ENDIAN ++#elif defined(__riscv) && __riscv_xlen == 64 ++#define WEBRTC_ARCH_RISCV_FAMILY ++#define WEBRTC_ARCH_64_BITS ++#define WEBRTC_ARCH_LITTLE_ENDIAN + #else + #error Please add support for your architecture in rtc_base/system/arch.h + #endif +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/gn/tools/gn/args.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/gn/tools/gn/args.cc ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/gn/tools/gn/args.cc +@@ -329,6 +329,7 @@ void Args::SetSystemVarsLocked(Scope* de + static const char kMips64[] = "mips64el"; + static const char kS390X[] = "s390x"; + static const char kPPC64[] = "ppc64"; ++ static const char kRiscv64[] = "riscv64"; + const char* arch = nullptr; + + // Set the host CPU architecture based on the underlying OS, not +@@ -353,6 +354,8 @@ void Args::SetSystemVarsLocked(Scope* de + // This allows us to use the same toolchain as ppc64 BE + // and specific flags are included using the host_byteorder logic. + arch = kPPC64; ++ else if (os_arch == "riscv64") ++ arch = kRiscv64; + else + CHECK(false) << "OS architecture not handled. (" << os_arch << ")"; + +Index: qtwebengine-everywhere-src-5.15.7/src/3rdparty/gn/util/build_config.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.7.orig/src/3rdparty/gn/util/build_config.h ++++ qtwebengine-everywhere-src-5.15.7/src/3rdparty/gn/util/build_config.h +@@ -172,6 +172,16 @@ + #define ARCH_CPU_32_BITS 1 + #define ARCH_CPU_BIG_ENDIAN 1 + #endif ++#elif defined(__riscv) ++#define ARCH_CPU_RISCV_FAMILY 1 ++#if __riscv_xlen == 64 ++#define ARCH_CPU_RISCV64 1 ++#define ARCH_CPU_64_BITS 1 ++#else ++#define ARCH_CPU_RISCV32 1 ++#define ARCH_CPU_32_BITS 1 ++#endif ++#define ARCH_CPU_LITTLE_ENDIAN 1 + #else + #error Please add support for your architecture in build_config.h + #endif diff --git a/srcpkgs/qt5-webengine/patches/0115-riscv64-v8.patch b/srcpkgs/qt5-webengine/patches/0115-riscv64-v8.patch new file mode 100644 index 0000000000000..bc7870aa51a5a --- /dev/null +++ b/srcpkgs/qt5-webengine/patches/0115-riscv64-v8.patch @@ -0,0 +1,33254 @@ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/BUILD.gn +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/BUILD.gn ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/BUILD.gn +@@ -714,7 +714,7 @@ config("toolchain") { + + # Mips64el/mipsel simulators. + if (target_is_simulator && +- (v8_current_cpu == "mipsel" || v8_current_cpu == "mips64el")) { ++ (v8_current_cpu == "mipsel" || v8_current_cpu == "mips64el" || v8_current_cpu == "riscv64")) { + defines += [ "_MIPS_TARGET_SIMULATOR" ] + } + +@@ -817,6 +817,21 @@ config("toolchain") { + } + } + ++ # Under simulator build, compiler will not provide __riscv_xlen. Define here ++ if (v8_current_cpu == "riscv") { ++ defines += [ "V8_TARGET_ARCH_RISCV" ] ++ defines += [ "__riscv_xlen=32" ] ++ } ++ ++ if (v8_current_cpu == "riscv64") { ++ defines += [ "V8_TARGET_ARCH_RISCV64" ] ++ defines += [ "__riscv_xlen=64" ] ++ #FIXME: Temporarily use MIPS macro for the building. ++ defines += [ ++ "CAN_USE_FPU_INSTRUCTIONS", ++ ] ++ } ++ + if (v8_current_cpu == "x86") { + defines += [ "V8_TARGET_ARCH_IA32" ] + if (is_win) { +@@ -905,7 +920,7 @@ config("toolchain") { + } + + if (v8_current_cpu == "x64" || v8_current_cpu == "arm64" || +- v8_current_cpu == "mips64el") { ++ v8_current_cpu == "mips64el" || v8_current_cpu == "riscv64") { + cflags += [ "-Wshorten-64-to-32" ] + } + } +@@ -1888,6 +1903,16 @@ v8_source_set("v8_initializers") { + ### gcmole(arch:s390) ### + "src/builtins/s390/builtins-s390.cc", + ] ++ } else if (v8_current_cpu == "riscv64") { ++ sources += [ ++ ### gcmole(arch:riscv64) ### ++ "src/builtins/riscv64/builtins-riscv64.cc", ++ ] ++ } else if (v8_current_cpu == "riscv") { ++ sources += [ ++ ### gcmole(arch:riscv) ### ++ "src/builtins/riscv/builtins-riscv.cc", ++ ] + } + + if (!v8_enable_i18n_support) { +@@ -3762,6 +3787,60 @@ v8_source_set("v8_base_without_compiler" + "src/regexp/s390/regexp-macro-assembler-s390.h", + "src/wasm/baseline/s390/liftoff-assembler-s390.h", + ] ++ } else if (v8_current_cpu == "riscv64") { ++ sources += [ ### gcmole(arch:riscv64) ### ++ "src/codegen/riscv64/assembler-riscv64-inl.h", ++ "src/codegen/riscv64/assembler-riscv64.cc", ++ "src/codegen/riscv64/assembler-riscv64.h", ++ "src/codegen/riscv64/constants-riscv64.cc", ++ "src/codegen/riscv64/constants-riscv64.h", ++ "src/codegen/riscv64/cpu-riscv64.cc", ++ "src/codegen/riscv64/interface-descriptors-riscv64.cc", ++ "src/codegen/riscv64/macro-assembler-riscv64.cc", ++ "src/codegen/riscv64/macro-assembler-riscv64.h", ++ "src/codegen/riscv64/register-riscv64.h", ++ "src/compiler/backend/riscv64/code-generator-riscv64.cc", ++ "src/compiler/backend/riscv64/instruction-codes-riscv64.h", ++ "src/compiler/backend/riscv64/instruction-scheduler-riscv64.cc", ++ "src/compiler/backend/riscv64/instruction-selector-riscv64.cc", ++ "src/debug/riscv64/debug-riscv64.cc", ++ "src/deoptimizer/riscv64/deoptimizer-riscv64.cc", ++ "src/diagnostics/riscv64/disasm-riscv64.cc", ++ "src/execution/riscv64/frame-constants-riscv64.cc", ++ "src/execution/riscv64/frame-constants-riscv64.h", ++ "src/execution/riscv64/simulator-riscv64.cc", ++ "src/execution/riscv64/simulator-riscv64.h", ++ "src/regexp/riscv64/regexp-macro-assembler-riscv64.cc", ++ "src/regexp/riscv64/regexp-macro-assembler-riscv64.h", ++ "src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h", ++ ] ++ } else if (v8_current_cpu == "riscv") { ++ sources += [ ### gcmole(arch:riscv) ### ++ "src/codegen/riscv/assembler-riscv-inl.h", ++ "src/codegen/riscv/assembler-riscv.cc", ++ "src/codegen/riscv/assembler-riscv.h", ++ "src/codegen/riscv/constants-riscv.cc", ++ "src/codegen/riscv/constants-riscv.h", ++ "src/codegen/riscv/cpu-riscv.cc", ++ "src/codegen/riscv/interface-descriptors-riscv.cc", ++ "src/codegen/riscv/macro-assembler-riscv.cc", ++ "src/codegen/riscv/macro-assembler-riscv.h", ++ "src/codegen/riscv/register-riscv.h", ++ "src/compiler/backend/riscv/code-generator-riscv.cc", ++ "src/compiler/backend/riscv/instruction-codes-riscv.h", ++ "src/compiler/backend/riscv/instruction-scheduler-riscv.cc", ++ "src/compiler/backend/riscv/instruction-selector-riscv.cc", ++ "src/debug/riscv/debug-riscv.cc", ++ "src/deoptimizer/riscv/deoptimizer-riscv.cc", ++ "src/diagnostics/riscv/disasm-riscv.cc", ++ "src/execution/riscv/frame-constants-riscv.cc", ++ "src/execution/riscv/frame-constants-riscv.h", ++ "src/execution/riscv/simulator-riscv.cc", ++ "src/execution/riscv/simulator-riscv.h", ++ "src/regexp/riscv/regexp-macro-assembler-riscv.cc", ++ "src/regexp/riscv/regexp-macro-assembler-riscv.h", ++ "src/wasm/baseline/riscv/liftoff-assembler-riscv.h", ++ ] + } + + configs = [ +@@ -3862,7 +3941,8 @@ v8_source_set("v8_base_without_compiler" + if (v8_current_cpu == "mips" || v8_current_cpu == "mipsel" || + v8_current_cpu == "mips64" || v8_current_cpu == "mips64el" || + v8_current_cpu == "ppc" || v8_current_cpu == "ppc64" || +- v8_current_cpu == "s390" || v8_current_cpu == "s390x") { ++ v8_current_cpu == "s390" || v8_current_cpu == "s390x" || ++ v8_current_cpu == "riscv64" || v8_current_cpu == "riscv") { + libs += [ "atomic" ] + } + +@@ -4197,7 +4277,7 @@ v8_component("v8_libbase") { + } + + if (is_ubsan && (v8_current_cpu == "x86" || v8_current_cpu == "arm" || +- v8_current_cpu == "mips")) { ++ v8_current_cpu == "mips" || v8_current_cpu == "riscv")) { + # Special UBSan 32-bit requirement. + sources += [ "src/base/ubsan.cc" ] + } +@@ -4328,6 +4408,8 @@ v8_source_set("v8_cppgc_shared") { + sources += [ "src/heap/base/asm/mips/push_registers_asm.cc" ] + } else if (current_cpu == "mips64el") { + sources += [ "src/heap/base/asm/mips64/push_registers_asm.cc" ] ++ } else if (current_cpu == "riscv64") { ++ sources += [ "src/heap/base/asm/riscv64/push_registers_asm.cc" ] + } + } else if (is_win) { + if (current_cpu == "x64") { +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/gni/snapshot_toolchain.gni +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/gni/snapshot_toolchain.gni ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/gni/snapshot_toolchain.gni +@@ -79,7 +79,8 @@ if (v8_snapshot_toolchain == "") { + + if (v8_current_cpu == "x64" || v8_current_cpu == "x86") { + _cpus = v8_current_cpu +- } else if (v8_current_cpu == "arm64" || v8_current_cpu == "mips64el") { ++ } else if (v8_current_cpu == "arm64" || v8_current_cpu == "mips64el" ++ || v8_current_cpu == "riscv64") { + if (is_win && v8_current_cpu == "arm64") { + # set _cpus to blank for Windows ARM64 so host_toolchain could be + # selected as snapshot toolchain later. +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/infra/mb/mb_config.pyl +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/infra/mb/mb_config.pyl ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/infra/mb/mb_config.pyl +@@ -33,6 +33,12 @@ + 'ppc64.debug.sim': 'default_debug_ppc64_sim', + 'ppc64.optdebug.sim': 'default_optdebug_ppc64_sim', + 'ppc64.release.sim': 'default_release_ppc64_sim', ++ 'riscv64.debug': 'default_debug_riscv64', ++ 'riscv64.optdebug': 'default_optdebug_riscv64', ++ 'riscv64.release': 'default_release_riscv64', ++ 'riscv64.debug.sim': 'default_debug_riscv64_sim', ++ 'riscv64.optdebug.sim': 'default_optdebug_riscv64_sim', ++ 'riscv64.release.sim': 'default_release_riscv64_sim', + 's390x.debug': 'default_debug_s390x', + 's390x.optdebug': 'default_optdebug_s390x', + 's390x.release': 'default_release_s390x', +@@ -175,6 +181,8 @@ + # IBM. + 'V8 Linux - ppc64 - sim': 'release_simulate_ppc64', + 'V8 Linux - s390x - sim': 'release_simulate_s390x', ++ # RISC-V ++ 'V8 Linux - riscv64 - sim': 'release_simulate_riscv64', + }, + 'client.v8.branches': { + 'V8 Linux - previous branch': 'release_x86', +@@ -207,6 +215,9 @@ + 'V8 s390x - sim - previous branch': 'release_simulate_s390x', + 'V8 s390x - sim - beta branch': 'release_simulate_s390x', + 'V8 s390x - sim - stable branch': 'release_simulate_s390x', ++ 'V8 riscv64 - sim - previous branch': 'release_simulate_riscv64', ++ 'V8 riscv64 - sim - beta branch': 'release_simulate_riscv64', ++ 'V8 riscv64 - sim - stable branch': 'release_simulate_riscv64', + }, + 'tryserver.v8': { + 'v8_android_arm_compile_rel': 'release_android_arm', +@@ -323,6 +334,18 @@ + 'debug', 'simulate_mips64el', 'v8_enable_slow_dchecks'], + 'default_release_mips64el': [ + 'release', 'simulate_mips64el'], ++ 'default_debug_riscv64': [ ++ 'debug', 'riscv64', 'gcc', 'v8_enable_slow_dchecks', 'v8_full_debug'], ++ 'default_optdebug_riscv64': [ ++ 'debug', 'riscv64', 'gcc', 'v8_enable_slow_dchecks'], ++ 'default_release_riscv64': [ ++ 'release', 'riscv64', 'gcc'], ++ 'default_debug_riscv64_sim': [ ++ 'debug', 'simulate_riscv64', 'v8_enable_slow_dchecks', 'v8_full_debug'], ++ 'default_optdebug_riscv64_sim': [ ++ 'debug', 'simulate_riscv64', 'v8_enable_slow_dchecks'], ++ 'default_release_riscv64_sim': [ ++ 'release', 'simulate_riscv64'], + 'default_debug_ppc64': [ + 'debug', 'ppc64', 'gcc', 'v8_enable_slow_dchecks', 'v8_full_debug'], + 'default_optdebug_ppc64': [ +@@ -410,6 +433,8 @@ + 'release_bot', 'simulate_mips64el'], + 'release_simulate_ppc64': [ + 'release_bot', 'simulate_ppc64'], ++ 'release_simulate_riscv64': [ ++ 'release_bot', 'simulate_riscv64'], + 'release_simulate_s390x': [ + 'release_bot', 'simulate_s390x'], + +@@ -812,6 +837,10 @@ + 'gn_args': 'target_cpu="x64" v8_target_cpu="ppc64"', + }, + ++ 'simulate_riscv64': { ++ 'gn_args': 'target_cpu="x64" v8_target_cpu="riscv64"', ++ }, ++ + 'simulate_s390x': { + 'gn_args': 'target_cpu="x64" v8_target_cpu="s390x"', + }, +@@ -918,6 +947,10 @@ + 'gn_args': 'target_cpu="ppc64" use_custom_libcxx=false', + }, + ++ 'riscv64': { ++ 'gn_args': 'target_cpu="riscv64" use_custom_libcxx=false', ++ }, ++ + 'x64': { + 'gn_args': 'target_cpu="x64"', + }, +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/build_config.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/base/build_config.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/build_config.h +@@ -46,6 +46,16 @@ + #else + #define V8_HOST_ARCH_32_BIT 1 + #endif ++#elif defined(__riscv) || defined(__riscv__) ++#if __riscv_xlen == 64 ++#define V8_HOST_ARCH_RISCV64 1 ++#define V8_HOST_ARCH_64_BIT 1 ++#elif __riscv_xlen == 32 ++#define V8_HOST_ARCH_RISCV 1 ++#define V8_HOST_ARCH_32_BIT 1 ++#else ++#error "Cannot detect Riscv's bitwidth" ++#endif + #else + #error "Host architecture was not detected as supported by v8" + #endif +@@ -77,7 +87,8 @@ + // environment as presented by the compiler. + #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM && \ + !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64 && \ +- !V8_TARGET_ARCH_PPC && !V8_TARGET_ARCH_PPC64 && !V8_TARGET_ARCH_S390 ++ !V8_TARGET_ARCH_PPC && !V8_TARGET_ARCH_PPC64 && !V8_TARGET_ARCH_S390 && \ ++ !V8_TARGET_ARCH_RISCV64 && !V8_TARGET_ARCH_RISCV + #if defined(_M_X64) || defined(__x86_64__) + #define V8_TARGET_ARCH_X64 1 + #elif defined(_M_IX86) || defined(__i386__) +@@ -94,6 +105,12 @@ + #define V8_TARGET_ARCH_PPC64 1 + #elif defined(_ARCH_PPC) + #define V8_TARGET_ARCH_PPC 1 ++#elif defined(__riscv) || defined(__riscv__) ++#if __riscv_xlen == 64 ++#define V8_TARGET_ARCH_RISCV64 1 ++#elif __riscv_xlen == 32 ++#define V8_TARGET_ARCH_RISCV 1 ++#endif + #else + #error Target architecture was not detected as supported by v8 + #endif +@@ -128,6 +145,10 @@ + #else + #define V8_TARGET_ARCH_32_BIT 1 + #endif ++#elif V8_TARGET_ARCH_RISCV64 ++#define V8_TARGET_ARCH_64_BIT 1 ++#elif V8_TARGET_ARCH_RISCV ++#define V8_TARGET_ARCH_32_BIT 1 + #else + #error Unknown target architecture pointer size + #endif +@@ -156,6 +177,13 @@ + #if (V8_TARGET_ARCH_MIPS64 && !(V8_HOST_ARCH_X64 || V8_HOST_ARCH_MIPS64)) + #error Target architecture mips64 is only supported on mips64 and x64 host + #endif ++#if (V8_TARGET_ARCH_RISCV64 && !(V8_HOST_ARCH_X64 || V8_HOST_ARCH_RISCV64)) ++#error Target architecture riscv64 is only supported on riscv64 and x64 host ++#endif ++#if (V8_TARGET_ARCH_RISCV && \ ++ !(V8_HOST_ARCH_X64 || V8_HOST_ARCH_RISCV || V8_HOST_ARCH_RISCV64)) ++#error Target architecture riscv (32) is only supported on riscv(32), riscv64, and x64 host ++#endif + + // Determine architecture endianness. + #if V8_TARGET_ARCH_IA32 +@@ -190,6 +218,8 @@ + #else + #define V8_TARGET_BIG_ENDIAN 1 + #endif ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++#define V8_TARGET_LITTLE_ENDIAN 1 + #else + #error Unknown target architecture endianness + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/compiler-specific.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/base/compiler-specific.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/compiler-specific.h +@@ -96,9 +96,10 @@ + // do not support adding noexcept to default members. + // Disabled on MSVC because constructors of standard containers are not noexcept + // there. +-#if ((!defined(V8_CC_GNU) && !defined(V8_CC_MSVC) && \ +- !defined(V8_TARGET_ARCH_MIPS) && !defined(V8_TARGET_ARCH_MIPS64) && \ +- !defined(V8_TARGET_ARCH_PPC) && !defined(V8_TARGET_ARCH_PPC64)) || \ ++#if ((!defined(V8_CC_GNU) && !defined(V8_CC_MSVC) && \ ++ !defined(V8_TARGET_ARCH_MIPS) && !defined(V8_TARGET_ARCH_MIPS64) && \ ++ !defined(V8_TARGET_ARCH_PPC) && !defined(V8_TARGET_ARCH_PPC64) && \ ++ !defined(V8_TARGET_ARCH_RISCV64) && !defined(V8_TARGET_ARCH_RISCV)) || \ + (defined(__clang__) && __cplusplus > 201300L)) + #define V8_NOEXCEPT noexcept + #else +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/macros.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/base/macros.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/macros.h +@@ -11,6 +11,8 @@ + #include "src/base/compiler-specific.h" + #include "src/base/logging.h" + ++#define DEBUG_PRINTF(...) if (FLAG_debug_riscv) { printf(__VA_ARGS__); } ++ + // No-op macro which is used to work around MSVC's funky VA_ARGS support. + #define EXPAND(x) x + +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/platform/platform-posix.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/base/platform/platform-posix.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/base/platform/platform-posix.cc +@@ -324,6 +324,12 @@ void* OS::GetRandomMmapAddr() { + // 42 bits of virtual addressing. Truncate to 40 bits to allow kernel chance + // to fulfill request. + raw_addr &= uint64_t{0xFFFFFF0000}; ++#elif V8_TARGET_ARCH_RISCV64 ++ // FIXME(RISCV): We need more information from the kernel to correctly mask ++ // this address for RISC-V. ++ raw_addr &= uint64_t{0xFFFFFF0000}; ++#elif V8_TARGET_ARCH_RISCV ++ #error RISCV archiecture not supported + #else + raw_addr &= 0x3FFFF000; + +@@ -512,6 +518,8 @@ void OS::DebugBreak() { + #elif V8_HOST_ARCH_S390 + // Software breakpoint instruction is 0x0001 + asm volatile(".word 0x0001"); ++#elif V8_HOST_ARCH_RISCV64 || V8_HOST_ARCH_RISCV ++ asm("ebreak"); + #else + #error Unsupported host architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/builtins-sharedarraybuffer-gen.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/builtins/builtins-sharedarraybuffer-gen.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/builtins-sharedarraybuffer-gen.cc +@@ -379,7 +379,9 @@ TF_BUILTIN(AtomicsExchange, SharedArrayB + // 2. Let i be ? ValidateAtomicAccess(typedArray, index). + TNode index_word = ValidateAtomicAccess(array, index, context); + +-#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 ++#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_RISCV64 || \ ++ V8_TARGET_ARCH_RISCV ++ // FIXME(RISCV): Review this special case once atomics are added + USE(array_buffer); + TNode index_number = ChangeUintPtrToTagged(index_word); + Return(CallRuntime(Runtime::kAtomicsExchange, context, array, index_number, +@@ -481,7 +483,8 @@ TF_BUILTIN(AtomicsExchange, SharedArrayB + // This shouldn't happen, we've already validated the type. + BIND(&other); + Unreachable(); +-#endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 ++#endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || ++ // V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + + BIND(&detached); + { +@@ -510,7 +513,9 @@ TF_BUILTIN(AtomicsCompareExchange, Share + TNode index_word = ValidateAtomicAccess(array, index, context); + + #if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 || \ +- V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ++ V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X || \ ++ V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ // FIXME(RISCV): Review this special case once atomics are added + USE(array_buffer); + TNode index_number = ChangeUintPtrToTagged(index_word); + Return(CallRuntime(Runtime::kAtomicsCompareExchange, context, array, +@@ -632,6 +637,7 @@ TF_BUILTIN(AtomicsCompareExchange, Share + Unreachable(); + #endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 + // || V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ++ // || V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + + BIND(&detached); + { +@@ -679,7 +685,9 @@ void SharedArrayBufferBuiltinsAssembler: + TNode index_word = ValidateAtomicAccess(array, index, context); + + #if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 || \ +- V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ++ V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X || \ ++ V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ // FIXME(RISCV): Review this special case once atomics are added + USE(array_buffer); + TNode index_number = ChangeUintPtrToTagged(index_word); + Return(CallRuntime(runtime_function, context, array, index_number, value)); +@@ -783,6 +791,7 @@ void SharedArrayBufferBuiltinsAssembler: + Unreachable(); + #endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 + // || V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ++ // || V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + + BIND(&detached); + ThrowTypeError(context, MessageTemplate::kDetachedOperation, method_name); +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/builtins.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/builtins/builtins.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/builtins.cc +@@ -490,14 +490,17 @@ bool Builtins::CodeObjectIsExecutable(in + case Builtins::kCEntry_Return1_DontSaveFPRegs_ArgvOnStack_NoBuiltinExit: + return true; + default: +-#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 ++#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_RISCV64 || \ ++ V8_TARGET_ARCH_RISCV ++ // FIXME(RISCV): Is this correct for RISC-V? + // TODO(Loongson): Move non-JS linkage builtins code objects into RO_SPACE + // caused MIPS platform to crash, and we need some time to handle it. Now + // disable this change temporarily on MIPS platform. + return true; + #else + return false; +-#endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 ++#endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || ++ // V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + } + } + +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/riscv64/builtins-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/builtins/riscv64/builtins-riscv64.cc +@@ -0,0 +1,3197 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/api/api-arguments.h" ++#include "src/codegen/code-factory.h" ++#include "src/debug/debug.h" ++#include "src/deoptimizer/deoptimizer.h" ++#include "src/execution/frame-constants.h" ++#include "src/execution/frames.h" ++#include "src/logging/counters.h" ++// For interpreter_entry_return_pc_offset. TODO(jkummerow): Drop. ++#include "src/codegen/macro-assembler-inl.h" ++#include "src/codegen/register-configuration.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/heap/heap-inl.h" ++#include "src/objects/cell.h" ++#include "src/objects/foreign.h" ++#include "src/objects/heap-number.h" ++#include "src/objects/js-generator.h" ++#include "src/objects/objects-inl.h" ++#include "src/objects/smi.h" ++#include "src/runtime/runtime.h" ++#include "src/wasm/wasm-linkage.h" ++#include "src/wasm/wasm-objects.h" ++ ++namespace v8 { ++namespace internal { ++ ++#define __ ACCESS_MASM(masm) ++ ++void Builtins::Generate_Adaptor(MacroAssembler* masm, Address address) { ++ __ li(kJavaScriptCallExtraArg1Register, ExternalReference::Create(address)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), AdaptorWithBuiltinExitFrame), ++ RelocInfo::CODE_TARGET); ++} ++ ++static void GenerateTailCallToReturnedCode(MacroAssembler* masm, ++ Runtime::FunctionId function_id) { ++ // ----------- S t a t e ------------- ++ // -- a1 : target function (preserved for callee) ++ // -- a3 : new target (preserved for callee) ++ // ----------------------------------- ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ // Push a copy of the function onto the stack. ++ // Push a copy of the target function and the new target. ++ __ Push(a1, a3, a1); ++ ++ __ CallRuntime(function_id, 1); ++ // Restore target function and new target. ++ __ Pop(a1, a3); ++ } ++ ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Add64(a2, a0, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Jump(a2); ++} ++ ++namespace { ++ ++enum StackLimitKind { kInterruptStackLimit, kRealStackLimit }; ++ ++void LoadStackLimit(MacroAssembler* masm, Register destination, ++ StackLimitKind kind) { ++ DCHECK(masm->root_array_available()); ++ Isolate* isolate = masm->isolate(); ++ ExternalReference limit = ++ kind == StackLimitKind::kRealStackLimit ++ ? ExternalReference::address_of_real_jslimit(isolate) ++ : ExternalReference::address_of_jslimit(isolate); ++ DCHECK(TurboAssembler::IsAddressableThroughRootRegister(isolate, limit)); ++ ++ intptr_t offset = ++ TurboAssembler::RootRegisterOffsetForExternalReference(isolate, limit); ++ CHECK(is_int32(offset)); ++ __ Ld(destination, MemOperand(kRootRegister, static_cast(offset))); ++} ++ ++void Generate_JSBuiltinsConstructStubHelper(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : number of arguments ++ // -- a1 : constructor function ++ // -- a3 : new target ++ // -- cp : context ++ // -- ra : return address ++ // -- sp[...]: constructor arguments ++ // ----------------------------------- ++ ++ // Enter a construct frame. ++ { ++ FrameScope scope(masm, StackFrame::CONSTRUCT); ++ ++ // Preserve the incoming parameters on the stack. ++ __ SmiTag(a0); ++ __ Push(cp, a0); ++ __ SmiUntag(a0); ++ ++ // The receiver for the builtin/api call. ++ __ PushRoot(RootIndex::kTheHoleValue); ++ ++ // Set up pointer to last argument. ++ __ Add64(t2, fp, Operand(StandardFrameConstants::kCallerSPOffset)); ++ ++ // Copy arguments and receiver to the expression stack. ++ Label loop, entry; ++ __ Move(t4, a0); ++ // ----------- S t a t e ------------- ++ // -- a0: number of arguments (untagged) ++ // -- a3: new target ++ // -- t2: pointer to last argument ++ // -- t4: counter ++ // -- sp[0*kPointerSize]: the hole (receiver) ++ // -- sp[1*kPointerSize]: number of arguments (tagged) ++ // -- sp[2*kPointerSize]: context ++ // ----------------------------------- ++ __ Branch(&entry); ++ __ bind(&loop); ++ __ CalcScaledAddress(t0, t2, t4, kPointerSizeLog2); ++ __ Ld(t1, MemOperand(t0)); ++ __ push(t1); ++ __ bind(&entry); ++ __ Add64(t4, t4, Operand(-1)); ++ __ Branch(&loop, greater_equal, t4, Operand(zero_reg)); ++ ++ // Call the function. ++ // a0: number of arguments (untagged) ++ // a1: constructor function ++ // a3: new target ++ __ InvokeFunctionWithNewTarget(a1, a3, a0, CALL_FUNCTION); ++ ++ // Restore context from the frame. ++ __ Ld(cp, MemOperand(fp, ConstructFrameConstants::kContextOffset)); ++ // Restore smi-tagged arguments count from the frame. ++ __ Ld(a1, MemOperand(fp, ConstructFrameConstants::kLengthOffset)); ++ // Leave construct frame. ++ } ++ ++ // Remove caller arguments from the stack and return. ++ __ SmiScale(a4, a1, kPointerSizeLog2); ++ __ Add64(sp, sp, a4); ++ __ Add64(sp, sp, kPointerSize); ++ __ Ret(); ++} ++ ++static void Generate_StackOverflowCheck(MacroAssembler* masm, Register num_args, ++ Register scratch1, Register scratch2, ++ Label* stack_overflow) { ++ // Check the stack for overflow. We are not trying to catch ++ // interruptions (e.g. debug break and preemption) here, so the "real stack ++ // limit" is checked. ++ LoadStackLimit(masm, scratch1, StackLimitKind::kRealStackLimit); ++ // Make scratch1 the space we have left. The stack might already be overflowed ++ // here which will cause scratch1 to become negative. ++ __ Sub64(scratch1, sp, scratch1); ++ // Check if the arguments will overflow the stack. ++ __ Sll64(scratch2, num_args, kPointerSizeLog2); ++ // Signed comparison. ++ __ Branch(stack_overflow, le, scratch1, Operand(scratch2)); ++} ++ ++} // namespace ++ ++// The construct stub for ES5 constructor functions and ES6 class constructors. ++void Builtins::Generate_JSConstructStubGeneric(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0: number of arguments (untagged) ++ // -- a1: constructor function ++ // -- a3: new target ++ // -- cp: context ++ // -- ra: return address ++ // -- sp[...]: constructor arguments ++ // ----------------------------------- ++ ++ // Enter a construct frame. ++ { ++ FrameScope scope(masm, StackFrame::CONSTRUCT); ++ Label post_instantiation_deopt_entry, not_create_implicit_receiver; ++ ++ // Preserve the incoming parameters on the stack. ++ __ SmiTag(a0); ++ __ Push(cp, a0, a1); ++ __ PushRoot(RootIndex::kTheHoleValue); ++ __ Push(a3); ++ ++ // ----------- S t a t e ------------- ++ // -- sp[0*kPointerSize]: new target ++ // -- sp[1*kPointerSize]: padding ++ // -- a1 and sp[2*kPointerSize]: constructor function ++ // -- sp[3*kPointerSize]: number of arguments (tagged) ++ // -- sp[4*kPointerSize]: context ++ // ----------------------------------- ++ ++ __ Ld(t2, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lwu(t2, FieldMemOperand(t2, SharedFunctionInfo::kFlagsOffset)); ++ __ DecodeField(t2); ++ __ JumpIfIsInRange(t2, kDefaultDerivedConstructor, kDerivedConstructor, ++ ¬_create_implicit_receiver); ++ ++ // If not derived class constructor: Allocate the new receiver object. ++ __ IncrementCounter(masm->isolate()->counters()->constructed_objects(), 1, ++ t2, t4); ++ __ Call(BUILTIN_CODE(masm->isolate(), FastNewObject), ++ RelocInfo::CODE_TARGET); ++ __ Branch(&post_instantiation_deopt_entry); ++ ++ // Else: use TheHoleValue as receiver for constructor call ++ __ bind(¬_create_implicit_receiver); ++ __ LoadRoot(a0, RootIndex::kTheHoleValue); ++ ++ // ----------- S t a t e ------------- ++ // -- a0: receiver ++ // -- Slot 4 / sp[0*kPointerSize]: new target ++ // -- Slot 3 / sp[1*kPointerSize]: padding ++ // -- Slot 2 / sp[2*kPointerSize]: constructor function ++ // -- Slot 1 / sp[3*kPointerSize]: number of arguments (tagged) ++ // -- Slot 0 / sp[4*kPointerSize]: context ++ // ----------------------------------- ++ // Deoptimizer enters here. ++ masm->isolate()->heap()->SetConstructStubCreateDeoptPCOffset( ++ masm->pc_offset()); ++ __ bind(&post_instantiation_deopt_entry); ++ ++ // Restore new target. ++ __ Pop(a3); ++ // Push the allocated receiver to the stack. We need two copies ++ // because we may have to return the original one and the calling ++ // conventions dictate that the called function pops the receiver. ++ __ Push(a0, a0); ++ ++ // ----------- S t a t e ------------- ++ // -- r3: new target ++ // -- sp[0*kPointerSize]: implicit receiver ++ // -- sp[1*kPointerSize]: implicit receiver ++ // -- sp[2*kPointerSize]: padding ++ // -- sp[3*kPointerSize]: constructor function ++ // -- sp[4*kPointerSize]: number of arguments (tagged) ++ // -- sp[5*kPointerSize]: context ++ // ----------------------------------- ++ ++ // Restore constructor function and argument count. ++ __ Ld(a1, MemOperand(fp, ConstructFrameConstants::kConstructorOffset)); ++ __ Ld(a0, MemOperand(fp, ConstructFrameConstants::kLengthOffset)); ++ __ SmiUntag(a0); ++ ++ // Set up pointer to last argument. ++ __ Add64(t2, fp, Operand(StandardFrameConstants::kCallerSPOffset)); ++ ++ Label enough_stack_space, stack_overflow; ++ Generate_StackOverflowCheck(masm, a0, t0, t1, &stack_overflow); ++ __ Branch(&enough_stack_space); ++ ++ __ bind(&stack_overflow); ++ // Restore the context from the frame. ++ __ Ld(cp, MemOperand(fp, ConstructFrameConstants::kContextOffset)); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ // Unreachable code. ++ __ break_(0xCC); ++ ++ __ bind(&enough_stack_space); ++ ++ // Copy arguments and receiver to the expression stack. ++ Label loop, entry; ++ __ Move(t4, a0); ++ // ----------- S t a t e ------------- ++ // -- a0: number of arguments (untagged) ++ // -- a3: new target ++ // -- t2: pointer to last argument ++ // -- t4: counter ++ // -- sp[0*kPointerSize]: implicit receiver ++ // -- sp[1*kPointerSize]: implicit receiver ++ // -- sp[2*kPointerSize]: padding ++ // -- a1 and sp[3*kPointerSize]: constructor function ++ // -- sp[4*kPointerSize]: number of arguments (tagged) ++ // -- sp[5*kPointerSize]: context ++ // ----------------------------------- ++ __ Branch(&entry); ++ __ bind(&loop); ++ __ CalcScaledAddress(t0, t2, t4, kPointerSizeLog2); ++ __ Ld(t1, MemOperand(t0)); ++ __ push(t1); ++ __ bind(&entry); ++ __ Add64(t4, t4, Operand(-1)); ++ __ Branch(&loop, greater_equal, t4, Operand(zero_reg)); ++ ++ // Call the function. ++ __ InvokeFunctionWithNewTarget(a1, a3, a0, CALL_FUNCTION); ++ ++ // ----------- S t a t e ------------- ++ // -- a0: constructor result ++ // -- sp[0*kPointerSize]: implicit receiver ++ // -- sp[1*kPointerSize]: padding ++ // -- sp[2*kPointerSize]: constructor function ++ // -- sp[3*kPointerSize]: number of arguments ++ // -- sp[4*kPointerSize]: context ++ // ----------------------------------- ++ ++ // Store offset of return address for deoptimizer. ++ masm->isolate()->heap()->SetConstructStubInvokeDeoptPCOffset( ++ masm->pc_offset()); ++ ++ // Restore the context from the frame. ++ __ Ld(cp, MemOperand(fp, ConstructFrameConstants::kContextOffset)); ++ ++ // If the result is an object (in the ECMA sense), we should get rid ++ // of the receiver and use the result; see ECMA-262 section 13.2.2-7 ++ // on page 74. ++ Label use_receiver, do_throw, leave_frame; ++ ++ // If the result is undefined, we jump out to using the implicit receiver. ++ __ JumpIfRoot(a0, RootIndex::kUndefinedValue, &use_receiver); ++ ++ // Otherwise we do a smi check and fall through to check if the return value ++ // is a valid receiver. ++ ++ // If the result is a smi, it is *not* an object in the ECMA sense. ++ __ JumpIfSmi(a0, &use_receiver); ++ ++ // If the type of the result (stored in its map) is less than ++ // FIRST_JS_RECEIVER_TYPE, it is not an object in the ECMA sense. ++ __ GetObjectType(a0, t2, t2); ++ STATIC_ASSERT(LAST_JS_RECEIVER_TYPE == LAST_TYPE); ++ __ Branch(&leave_frame, greater_equal, t2, Operand(FIRST_JS_RECEIVER_TYPE)); ++ __ Branch(&use_receiver); ++ ++ __ bind(&do_throw); ++ __ CallRuntime(Runtime::kThrowConstructorReturnedNonObject); ++ ++ // Throw away the result of the constructor invocation and use the ++ // on-stack receiver as the result. ++ __ bind(&use_receiver); ++ __ Ld(a0, MemOperand(sp, 0 * kPointerSize)); ++ __ JumpIfRoot(a0, RootIndex::kTheHoleValue, &do_throw); ++ ++ __ bind(&leave_frame); ++ // Restore smi-tagged arguments count from the frame. ++ __ Ld(a1, MemOperand(fp, ConstructFrameConstants::kLengthOffset)); ++ // Leave construct frame. ++ } ++ // Remove caller arguments from the stack and return. ++ __ SmiScale(a4, a1, kPointerSizeLog2); ++ __ Add64(sp, sp, a4); ++ __ Add64(sp, sp, kPointerSize); ++ __ Ret(); ++} ++ ++void Builtins::Generate_JSBuiltinsConstructStub(MacroAssembler* masm) { ++ Generate_JSBuiltinsConstructStubHelper(masm); ++} ++ ++static void GetSharedFunctionInfoBytecode(MacroAssembler* masm, ++ Register sfi_data, ++ Register scratch1) { ++ Label done; ++ ++ __ GetObjectType(sfi_data, scratch1, scratch1); ++ __ Branch(&done, ne, scratch1, Operand(INTERPRETER_DATA_TYPE)); ++ __ Ld(sfi_data, ++ FieldMemOperand(sfi_data, InterpreterData::kBytecodeArrayOffset)); ++ ++ __ bind(&done); ++} ++ ++// static ++void Builtins::Generate_ResumeGeneratorTrampoline(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the value to pass to the generator ++ // -- a1 : the JSGeneratorObject to resume ++ // -- ra : return address ++ // ----------------------------------- ++ __ AssertGeneratorObject(a1); ++ ++ // Store input value into generator object. ++ __ Sd(a0, FieldMemOperand(a1, JSGeneratorObject::kInputOrDebugPosOffset)); ++ __ RecordWriteField(a1, JSGeneratorObject::kInputOrDebugPosOffset, a0, a3, ++ kRAHasNotBeenSaved, kDontSaveFPRegs); ++ ++ // Load suspended function and context. ++ __ Ld(a4, FieldMemOperand(a1, JSGeneratorObject::kFunctionOffset)); ++ __ Ld(cp, FieldMemOperand(a4, JSFunction::kContextOffset)); ++ ++ // Flood function if we are stepping. ++ Label prepare_step_in_if_stepping, prepare_step_in_suspended_generator; ++ Label stepping_prepared; ++ ExternalReference debug_hook = ++ ExternalReference::debug_hook_on_function_call_address(masm->isolate()); ++ __ li(a5, debug_hook); ++ __ Lb(a5, MemOperand(a5)); ++ __ Branch(&prepare_step_in_if_stepping, ne, a5, Operand(zero_reg)); ++ ++ // Flood function if we need to continue stepping in the suspended generator. ++ ExternalReference debug_suspended_generator = ++ ExternalReference::debug_suspended_generator_address(masm->isolate()); ++ __ li(a5, debug_suspended_generator); ++ __ Ld(a5, MemOperand(a5)); ++ __ Branch(&prepare_step_in_suspended_generator, eq, a1, Operand(a5)); ++ __ bind(&stepping_prepared); ++ ++ // Check the stack for overflow. We are not trying to catch interruptions ++ // (i.e. debug break and preemption) here, so check the "real stack limit". ++ Label stack_overflow; ++ LoadStackLimit(masm, kScratchReg, StackLimitKind::kRealStackLimit); ++ __ Branch(&stack_overflow, Uless, sp, Operand(kScratchReg)); ++ ++ // Push receiver. ++ __ Ld(a5, FieldMemOperand(a1, JSGeneratorObject::kReceiverOffset)); ++ __ Push(a5); ++ ++ // ----------- S t a t e ------------- ++ // -- a1 : the JSGeneratorObject to resume ++ // -- a4 : generator function ++ // -- cp : generator context ++ // -- ra : return address ++ // -- sp[0] : generator receiver ++ // ----------------------------------- ++ ++ // Push holes for arguments to generator function. Since the parser forced ++ // context allocation for any variables in generators, the actual argument ++ // values have already been copied into the context and these dummy values ++ // will never be used. ++ __ Ld(a3, FieldMemOperand(a4, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lhu(a3, ++ FieldMemOperand(a3, SharedFunctionInfo::kFormalParameterCountOffset)); ++ __ Ld(t1, ++ FieldMemOperand(a1, JSGeneratorObject::kParametersAndRegistersOffset)); ++ { ++ Label done_loop, loop; ++ __ Move(t2, zero_reg); ++ __ bind(&loop); ++ __ Sub64(a3, a3, Operand(1)); ++ __ Branch(&done_loop, lt, a3, Operand(zero_reg)); ++ __ CalcScaledAddress(kScratchReg, t1, t2, kPointerSizeLog2); ++ __ Ld(kScratchReg, FieldMemOperand(kScratchReg, FixedArray::kHeaderSize)); ++ __ Push(kScratchReg); ++ __ Add64(t2, t2, Operand(1)); ++ __ Branch(&loop); ++ __ bind(&done_loop); ++ } ++ ++ // Underlying function needs to have bytecode available. ++ if (FLAG_debug_code) { ++ __ Ld(a3, FieldMemOperand(a4, JSFunction::kSharedFunctionInfoOffset)); ++ __ Ld(a3, FieldMemOperand(a3, SharedFunctionInfo::kFunctionDataOffset)); ++ GetSharedFunctionInfoBytecode(masm, a3, a0); ++ __ GetObjectType(a3, a3, a3); ++ __ Assert(eq, AbortReason::kMissingBytecodeArray, a3, ++ Operand(BYTECODE_ARRAY_TYPE)); ++ } ++ ++ // Resume (Ignition/TurboFan) generator object. ++ { ++ __ Ld(a0, FieldMemOperand(a4, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lhu(a0, FieldMemOperand( ++ a0, SharedFunctionInfo::kFormalParameterCountOffset)); ++ // We abuse new.target both to indicate that this is a resume call and to ++ // pass in the generator object. In ordinary calls, new.target is always ++ // undefined because generator functions are non-constructable. ++ __ Move(a3, a1); ++ __ Move(a1, a4); ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Ld(a2, FieldMemOperand(a1, JSFunction::kCodeOffset)); ++ __ Add64(a2, a2, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Jump(a2); ++ } ++ ++ __ bind(&prepare_step_in_if_stepping); ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ Push(a1, a4); ++ // Push hole as receiver since we do not use it for stepping. ++ __ PushRoot(RootIndex::kTheHoleValue); ++ __ CallRuntime(Runtime::kDebugOnFunctionCall); ++ __ Pop(a1); ++ } ++ __ Ld(a4, FieldMemOperand(a1, JSGeneratorObject::kFunctionOffset)); ++ __ Branch(&stepping_prepared); ++ ++ __ bind(&prepare_step_in_suspended_generator); ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ Push(a1); ++ __ CallRuntime(Runtime::kDebugPrepareStepInSuspendedGenerator); ++ __ Pop(a1); ++ } ++ __ Ld(a4, FieldMemOperand(a1, JSGeneratorObject::kFunctionOffset)); ++ __ Branch(&stepping_prepared); ++ ++ __ bind(&stack_overflow); ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ __ break_(0xCC); // This should be unreachable. ++ } ++} ++ ++void Builtins::Generate_ConstructedNonConstructable(MacroAssembler* masm) { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ Push(a1); ++ __ CallRuntime(Runtime::kThrowConstructedNonConstructable); ++} ++ ++// Clobbers scratch1 and scratch2; preserves all other registers. ++static void Generate_CheckStackOverflow(MacroAssembler* masm, Register argc, ++ Register scratch1, Register scratch2) { ++ // Check the stack for overflow. We are not trying to catch ++ // interruptions (e.g. debug break and preemption) here, so the "real stack ++ // limit" is checked. ++ Label okay; ++ LoadStackLimit(masm, scratch1, StackLimitKind::kRealStackLimit); ++ // Make a2 the space we have left. The stack might already be overflowed ++ // here which will cause r2 to become negative. ++ __ Sub64(scratch1, sp, scratch1); ++ // Check if the arguments will overflow the stack. ++ __ Sll64(scratch2, argc, kPointerSizeLog2); ++ __ Branch(&okay, gt, scratch1, Operand(scratch2)); // Signed comparison. ++ ++ // Out of stack space. ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ ++ __ bind(&okay); ++} ++ ++namespace { ++ ++// Called with the native C calling convention. The corresponding function ++// signature is either: ++// ++// using JSEntryFunction = GeneratedCode; ++// or ++// using JSEntryFunction = GeneratedCode; ++void Generate_JSEntryVariant(MacroAssembler* masm, StackFrame::Type type, ++ Builtins::Name entry_trampoline) { ++ Label invoke, handler_entry, exit; ++ ++ { ++ NoRootArrayScope no_root_array(masm); ++ ++ // TODO(plind): unify the ABI description here. ++ // Registers: ++ // either ++ // a0: root register value ++ // a1: entry address ++ // a2: function ++ // a3: receiver ++ // a4: argc ++ // a5: argv ++ // or ++ // a0: root register value ++ // a1: microtask_queue ++ ++ // Save callee saved registers on the stack. ++ __ MultiPush(kCalleeSaved | ra.bit()); ++ ++ // Save callee-saved FPU registers. ++ __ MultiPushFPU(kCalleeSavedFPU); ++ // Set up the reserved register for 0.0. ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0); ++ ++ // Initialize the root register. ++ // C calling convention. The first argument is passed in a0. ++ __ Move(kRootRegister, a0); ++ } ++ ++ // a1: entry address ++ // a2: function ++ // a3: receiver ++ // a4: argc ++ // a5: argv ++ ++ // We build an EntryFrame. ++ __ li(s1, Operand(-1)); // Push a bad frame pointer to fail if it is used. ++ __ li(s2, Operand(StackFrame::TypeToMarker(type))); ++ __ li(s3, Operand(StackFrame::TypeToMarker(type))); ++ ExternalReference c_entry_fp = ExternalReference::Create( ++ IsolateAddressId::kCEntryFPAddress, masm->isolate()); ++ __ li(s4, c_entry_fp); ++ __ Ld(s4, MemOperand(s4)); ++ __ Push(s1, s2, s3, s4); ++ // Set up frame pointer for the frame to be pushed. ++ __ Add64(fp, sp, -EntryFrameConstants::kCallerFPOffset); ++ // Registers: ++ // either ++ // a1: entry address ++ // a2: function ++ // a3: receiver ++ // a4: argc ++ // a5: argv ++ // or ++ // a1: microtask_queue ++ // ++ // Stack: ++ // caller fp | ++ // function slot | entry frame ++ // context slot | ++ // bad fp (0xFF...F) | ++ // callee saved registers + ra ++ // [ O32: 4 args slots] ++ // args ++ ++ // If this is the outermost JS call, set js_entry_sp value. ++ Label non_outermost_js; ++ ExternalReference js_entry_sp = ExternalReference::Create( ++ IsolateAddressId::kJSEntrySPAddress, masm->isolate()); ++ __ li(s1, js_entry_sp); ++ __ Ld(s2, MemOperand(s1)); ++ __ Branch(&non_outermost_js, ne, s2, Operand(zero_reg)); ++ __ Sd(fp, MemOperand(s1)); ++ __ li(s3, Operand(StackFrame::OUTERMOST_JSENTRY_FRAME)); ++ Label cont; ++ __ Branch(&cont); ++ __ bind(&non_outermost_js); ++ __ li(s3, Operand(StackFrame::INNER_JSENTRY_FRAME)); ++ __ bind(&cont); ++ __ push(s3); ++ ++ // Jump to a faked try block that does the invoke, with a faked catch ++ // block that sets the pending exception. ++ __ Branch(&invoke); ++ __ bind(&handler_entry); ++ ++ // Store the current pc as the handler offset. It's used later to create the ++ // handler table. ++ masm->isolate()->builtins()->SetJSEntryHandlerOffset(handler_entry.pos()); ++ ++ // Caught exception: Store result (exception) in the pending exception ++ // field in the JSEnv and return a failure sentinel. Coming in here the ++ // fp will be invalid because the PushStackHandler below sets it to 0 to ++ // signal the existence of the JSEntry frame. ++ __ li(s1, ExternalReference::Create( ++ IsolateAddressId::kPendingExceptionAddress, masm->isolate())); ++ __ Sd(a0, MemOperand(s1)); // We come back from 'invoke'. result is in a0. ++ __ LoadRoot(a0, RootIndex::kException); ++ __ Branch(&exit); ++ ++ // Invoke: Link this frame into the handler chain. ++ __ bind(&invoke); ++ __ PushStackHandler(); ++ // If an exception not caught by another handler occurs, this handler ++ // returns control to the code after the bal(&invoke) above, which ++ // restores all kCalleeSaved registers (including cp and fp) to their ++ // saved values before returning a failure to C. ++ // ++ // Registers: ++ // either ++ // a0: root register value ++ // a1: entry address ++ // a2: function ++ // a3: receiver ++ // a4: argc ++ // a5: argv ++ // or ++ // a0: root register value ++ // a1: microtask_queue ++ // ++ // Stack: ++ // handler frame ++ // entry frame ++ // callee saved registers + ra ++ // [ O32: 4 args slots] ++ // args ++ // ++ // Invoke the function by calling through JS entry trampoline builtin and ++ // pop the faked function when we return. ++ ++ Handle trampoline_code = ++ masm->isolate()->builtins()->builtin_handle(entry_trampoline); ++ __ Call(trampoline_code, RelocInfo::CODE_TARGET); ++ ++ // Unlink this frame from the handler chain. ++ __ PopStackHandler(); ++ ++ __ bind(&exit); // a0 holds result ++ // Check if the current stack frame is marked as the outermost JS frame. ++ Label non_outermost_js_2; ++ __ pop(a5); ++ __ Branch(&non_outermost_js_2, ne, a5, ++ Operand(StackFrame::OUTERMOST_JSENTRY_FRAME)); ++ __ li(a5, js_entry_sp); ++ __ Sd(zero_reg, MemOperand(a5)); ++ __ bind(&non_outermost_js_2); ++ ++ // Restore the top frame descriptors from the stack. ++ __ pop(a5); ++ __ li(a4, ExternalReference::Create(IsolateAddressId::kCEntryFPAddress, ++ masm->isolate())); ++ __ Sd(a5, MemOperand(a4)); ++ ++ // Reset the stack to the callee saved registers. ++ __ Add64(sp, sp, -EntryFrameConstants::kCallerFPOffset); ++ ++ // Restore callee-saved fpu registers. ++ __ MultiPopFPU(kCalleeSavedFPU); ++ ++ // Restore callee saved registers from the stack. ++ __ MultiPop(kCalleeSaved | ra.bit()); ++ // Return. ++ __ Jump(ra); ++} ++ ++} // namespace ++ ++void Builtins::Generate_JSEntry(MacroAssembler* masm) { ++ Generate_JSEntryVariant(masm, StackFrame::ENTRY, ++ Builtins::kJSEntryTrampoline); ++} ++ ++void Builtins::Generate_JSConstructEntry(MacroAssembler* masm) { ++ Generate_JSEntryVariant(masm, StackFrame::CONSTRUCT_ENTRY, ++ Builtins::kJSConstructEntryTrampoline); ++} ++ ++void Builtins::Generate_JSRunMicrotasksEntry(MacroAssembler* masm) { ++ Generate_JSEntryVariant(masm, StackFrame::ENTRY, ++ Builtins::kRunMicrotasksTrampoline); ++} ++ ++static void Generate_JSEntryTrampolineHelper(MacroAssembler* masm, ++ bool is_construct) { ++ // ----------- S t a t e ------------- ++ // -- a1: new.target ++ // -- a2: function ++ // -- a3: receiver_pointer ++ // -- a4: argc ++ // -- a5: argv ++ // ----------------------------------- ++ ++ // Enter an internal frame. ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ ++ // Setup the context (we need to use the caller context from the isolate). ++ ExternalReference context_address = ExternalReference::Create( ++ IsolateAddressId::kContextAddress, masm->isolate()); ++ __ li(cp, context_address); ++ __ Ld(cp, MemOperand(cp)); ++ ++ // Push the function and the receiver onto the stack. ++ __ Push(a2, a3); ++ ++ // Check if we have enough stack space to push all arguments. ++ // Clobbers a0 and a3. ++ Generate_CheckStackOverflow(masm, a4, a0, a3); ++ ++ // Setup new.target, function and argc. ++ __ Move(a3, a1); ++ __ Move(a1, a2); ++ __ Move(a0, a4); ++ ++ // a0: argc ++ // a1: function ++ // a3: new.target ++ // a5: argv ++ ++ // Copy arguments to the stack in a loop. ++ // a3: argc ++ // a5: argv, i.e. points to first arg ++ Label loop, entry; ++ __ CalcScaledAddress(s1, a5, a4, kPointerSizeLog2); ++ __ Branch(&entry); ++ // s1 points past last arg. ++ __ bind(&loop); ++ __ Ld(s2, MemOperand(a5)); // Read next parameter. ++ __ Add64(a5, a5, kPointerSize); ++ __ Ld(s2, MemOperand(s2)); // Dereference handle. ++ __ push(s2); // Push parameter. ++ __ bind(&entry); ++ __ Branch(&loop, ne, a5, Operand(s1)); ++ ++ // a0: argc ++ // a1: function ++ // a3: new.target ++ ++ // Initialize all JavaScript callee-saved registers, since they will be seen ++ // by the garbage collector as part of handlers. ++ __ LoadRoot(a4, RootIndex::kUndefinedValue); ++ __ Move(a5, a4); ++ __ Move(s1, a4); ++ __ Move(s2, a4); ++ __ Move(s3, a4); ++ __ Move(s4, a4); ++ __ Move(s5, a4); ++ // s6 holds the root address. Do not clobber. ++ // s7 is cp. Do not init. ++ ++ // Invoke the code. ++ Handle builtin = is_construct ++ ? BUILTIN_CODE(masm->isolate(), Construct) ++ : masm->isolate()->builtins()->Call(); ++ __ Call(builtin, RelocInfo::CODE_TARGET); ++ ++ // Leave internal frame. ++ } ++ __ Jump(ra); ++} ++ ++void Builtins::Generate_JSEntryTrampoline(MacroAssembler* masm) { ++ Generate_JSEntryTrampolineHelper(masm, false); ++} ++ ++void Builtins::Generate_JSConstructEntryTrampoline(MacroAssembler* masm) { ++ Generate_JSEntryTrampolineHelper(masm, true); ++} ++ ++void Builtins::Generate_RunMicrotasksTrampoline(MacroAssembler* masm) { ++ // a1: microtask_queue ++ __ Move(RunMicrotasksDescriptor::MicrotaskQueueRegister(), a1); ++ __ Jump(BUILTIN_CODE(masm->isolate(), RunMicrotasks), RelocInfo::CODE_TARGET); ++} ++ ++static void ReplaceClosureCodeWithOptimizedCode(MacroAssembler* masm, ++ Register optimized_code, ++ Register closure, ++ Register scratch1, ++ Register scratch2) { ++ // Store code entry in the closure. ++ __ Sd(optimized_code, FieldMemOperand(closure, JSFunction::kCodeOffset)); ++ __ Move(scratch1, optimized_code); // Write barrier clobbers scratch1 below. ++ __ RecordWriteField(closure, JSFunction::kCodeOffset, scratch1, scratch2, ++ kRAHasNotBeenSaved, kDontSaveFPRegs, OMIT_REMEMBERED_SET, ++ OMIT_SMI_CHECK); ++} ++ ++static void LeaveInterpreterFrame(MacroAssembler* masm, Register scratch) { ++ Register args_count = scratch; ++ ++ // Get the arguments + receiver count. ++ __ Ld(args_count, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp)); ++ __ Lw(t0, FieldMemOperand(args_count, BytecodeArray::kParameterSizeOffset)); ++ ++ // Leave the frame (also dropping the register file). ++ __ LeaveFrame(StackFrame::INTERPRETED); ++ ++ // Drop receiver + arguments. ++ __ Add64(sp, sp, args_count); ++} ++ ++// Tail-call |function_id| if |smi_entry| == |marker| ++static void TailCallRuntimeIfMarkerEquals(MacroAssembler* masm, ++ Register smi_entry, ++ OptimizationMarker marker, ++ Runtime::FunctionId function_id) { ++ Label no_match; ++ __ Branch(&no_match, ne, smi_entry, Operand(Smi::FromEnum(marker))); ++ GenerateTailCallToReturnedCode(masm, function_id); ++ __ bind(&no_match); ++} ++ ++static void TailCallOptimizedCodeSlot(MacroAssembler* masm, ++ Register optimized_code_entry, ++ Register scratch1, Register scratch2) { ++ // ----------- S t a t e ------------- ++ // -- a3 : new target (preserved for callee if needed, and caller) ++ // -- a1 : target function (preserved for callee if needed, and caller) ++ // ----------------------------------- ++ DCHECK(!AreAliased(optimized_code_entry, a1, a3, scratch1, scratch2)); ++ ++ Register closure = a1; ++ ++ // Check if the optimized code is marked for deopt. If it is, call the ++ // runtime to clear it. ++ Label found_deoptimized_code; ++ __ Ld(a5, ++ FieldMemOperand(optimized_code_entry, Code::kCodeDataContainerOffset)); ++ __ Lw(a5, FieldMemOperand(a5, CodeDataContainer::kKindSpecificFlagsOffset)); ++ __ And(a5, a5, Operand(1 << Code::kMarkedForDeoptimizationBit)); ++ __ Branch(&found_deoptimized_code, ne, a5, Operand(zero_reg)); ++ ++ // Optimized code is good, get it into the closure and link the closure into ++ // the optimized functions list, then tail call the optimized code. ++ // The feedback vector is no longer used, so re-use it as a scratch ++ // register. ++ ReplaceClosureCodeWithOptimizedCode(masm, optimized_code_entry, closure, ++ scratch1, scratch2); ++ ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Add64(a2, optimized_code_entry, ++ Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Jump(a2); ++ ++ // Optimized code slot contains deoptimized code, evict it and re-enter the ++ // closure's code. ++ __ bind(&found_deoptimized_code); ++ GenerateTailCallToReturnedCode(masm, Runtime::kEvictOptimizedCodeSlot); ++} ++ ++static void MaybeOptimizeCode(MacroAssembler* masm, Register feedback_vector, ++ Register optimization_marker) { ++ // ----------- S t a t e ------------- ++ // -- a3 : new target (preserved for callee if needed, and caller) ++ // -- a1 : target function (preserved for callee if needed, and caller) ++ // -- feedback vector (preserved for caller if needed) ++ // -- optimization_marker : a Smi containing a non-zero optimization marker. ++ // ----------------------------------- ++ DCHECK(!AreAliased(feedback_vector, a1, a3, optimization_marker)); ++ ++ // TODO(v8:8394): The logging of first execution will break if ++ // feedback vectors are not allocated. We need to find a different way of ++ // logging these events if required. ++ TailCallRuntimeIfMarkerEquals(masm, optimization_marker, ++ OptimizationMarker::kLogFirstExecution, ++ Runtime::kFunctionFirstExecution); ++ TailCallRuntimeIfMarkerEquals(masm, optimization_marker, ++ OptimizationMarker::kCompileOptimized, ++ Runtime::kCompileOptimized_NotConcurrent); ++ TailCallRuntimeIfMarkerEquals(masm, optimization_marker, ++ OptimizationMarker::kCompileOptimizedConcurrent, ++ Runtime::kCompileOptimized_Concurrent); ++ ++ // Otherwise, the marker is InOptimizationQueue, so fall through hoping ++ // that an interrupt will eventually update the slot with optimized code. ++ if (FLAG_debug_code) { ++ __ Assert(eq, AbortReason::kExpectedOptimizationSentinel, ++ optimization_marker, ++ Operand(Smi::FromEnum(OptimizationMarker::kInOptimizationQueue))); ++ } ++} ++ ++// Advance the current bytecode offset. This simulates what all bytecode ++// handlers do upon completion of the underlying operation. Will bail out to a ++// label if the bytecode (without prefix) is a return bytecode. Will not advance ++// the bytecode offset if the current bytecode is a JumpLoop, instead just ++// re-executing the JumpLoop to jump to the correct bytecode. ++static void AdvanceBytecodeOffsetOrReturn(MacroAssembler* masm, ++ Register bytecode_array, ++ Register bytecode_offset, ++ Register bytecode, Register scratch1, ++ Register scratch2, Register scratch3, ++ Label* if_return) { ++ Register bytecode_size_table = scratch1; ++ ++ // The bytecode offset value will be increased by one in wide and extra wide ++ // cases. In the case of having a wide or extra wide JumpLoop bytecode, we ++ // will restore the original bytecode. In order to simplify the code, we have ++ // a backup of it. ++ Register original_bytecode_offset = scratch3; ++ DCHECK(!AreAliased(bytecode_array, bytecode_offset, bytecode, ++ bytecode_size_table, original_bytecode_offset)); ++ __ Move(original_bytecode_offset, bytecode_offset); ++ __ li(bytecode_size_table, ExternalReference::bytecode_size_table_address()); ++ ++ // Check if the bytecode is a Wide or ExtraWide prefix bytecode. ++ Label process_bytecode, extra_wide; ++ STATIC_ASSERT(0 == static_cast(interpreter::Bytecode::kWide)); ++ STATIC_ASSERT(1 == static_cast(interpreter::Bytecode::kExtraWide)); ++ STATIC_ASSERT(2 == static_cast(interpreter::Bytecode::kDebugBreakWide)); ++ STATIC_ASSERT(3 == ++ static_cast(interpreter::Bytecode::kDebugBreakExtraWide)); ++ __ Branch(&process_bytecode, Ugreater, bytecode, Operand(3)); ++ __ And(scratch2, bytecode, Operand(1)); ++ __ Branch(&extra_wide, ne, scratch2, Operand(zero_reg)); ++ ++ // Load the next bytecode and update table to the wide scaled table. ++ __ Add64(bytecode_offset, bytecode_offset, Operand(1)); ++ __ Add64(scratch2, bytecode_array, bytecode_offset); ++ __ Lbu(bytecode, MemOperand(scratch2)); ++ __ Add64(bytecode_size_table, bytecode_size_table, ++ Operand(kIntSize * interpreter::Bytecodes::kBytecodeCount)); ++ __ Branch(&process_bytecode); ++ ++ __ bind(&extra_wide); ++ // Load the next bytecode and update table to the extra wide scaled table. ++ __ Add64(bytecode_offset, bytecode_offset, Operand(1)); ++ __ Add64(scratch2, bytecode_array, bytecode_offset); ++ __ Lbu(bytecode, MemOperand(scratch2)); ++ __ Add64(bytecode_size_table, bytecode_size_table, ++ Operand(2 * kIntSize * interpreter::Bytecodes::kBytecodeCount)); ++ ++ __ bind(&process_bytecode); ++ ++// Bailout to the return label if this is a return bytecode. ++#define JUMP_IF_EQUAL(NAME) \ ++ __ Branch(if_return, eq, bytecode, \ ++ Operand(static_cast(interpreter::Bytecode::k##NAME))); ++ RETURN_BYTECODE_LIST(JUMP_IF_EQUAL) ++#undef JUMP_IF_EQUAL ++ ++ // If this is a JumpLoop, re-execute it to perform the jump to the beginning ++ // of the loop. ++ Label end, not_jump_loop; ++ __ Branch(¬_jump_loop, ne, bytecode, ++ Operand(static_cast(interpreter::Bytecode::kJumpLoop))); ++ // We need to restore the original bytecode_offset since we might have ++ // increased it to skip the wide / extra-wide prefix bytecode. ++ __ Move(bytecode_offset, original_bytecode_offset); ++ __ Branch(&end); ++ ++ __ bind(¬_jump_loop); ++ // Otherwise, load the size of the current bytecode and advance the offset. ++ __ CalcScaledAddress(scratch2, bytecode_size_table, bytecode, 2); ++ __ Lw(scratch2, MemOperand(scratch2)); ++ __ Add64(bytecode_offset, bytecode_offset, scratch2); ++ ++ __ bind(&end); ++} ++ ++// Generate code for entering a JS function with the interpreter. ++// On entry to the function the receiver and arguments have been pushed on the ++// stack left to right. The actual argument count matches the formal parameter ++// count expected by the function. ++// ++// The live registers are: ++// o a1: the JS function object being called. ++// o a3: the incoming new target or generator object ++// o cp: our context ++// o fp: the caller's frame pointer ++// o sp: stack pointer ++// o ra: return address ++// ++// The function builds an interpreter frame. See InterpreterFrameConstants in ++// frames.h for its layout. ++void Builtins::Generate_InterpreterEntryTrampoline(MacroAssembler* masm) { ++ Register closure = a1; ++ Register feedback_vector = a2; ++ ++ // Get the bytecode array from the function object and load it into ++ // kInterpreterBytecodeArrayRegister. ++ __ Ld(a0, FieldMemOperand(closure, JSFunction::kSharedFunctionInfoOffset)); ++ __ Ld(kInterpreterBytecodeArrayRegister, ++ FieldMemOperand(a0, SharedFunctionInfo::kFunctionDataOffset)); ++ GetSharedFunctionInfoBytecode(masm, kInterpreterBytecodeArrayRegister, a4); ++ ++ // The bytecode array could have been flushed from the shared function info, ++ // if so, call into CompileLazy. ++ Label compile_lazy; ++ __ GetObjectType(kInterpreterBytecodeArrayRegister, a0, a0); ++ __ Branch(&compile_lazy, ne, a0, Operand(BYTECODE_ARRAY_TYPE)); ++ ++ // Load the feedback vector from the closure. ++ __ Ld(feedback_vector, ++ FieldMemOperand(closure, JSFunction::kFeedbackCellOffset)); ++ __ Ld(feedback_vector, FieldMemOperand(feedback_vector, Cell::kValueOffset)); ++ ++ Label push_stack_frame; ++ // Check if feedback vector is valid. If valid, check for optimized code ++ // and update invocation count. Otherwise, setup the stack frame. ++ __ Ld(a4, FieldMemOperand(feedback_vector, HeapObject::kMapOffset)); ++ __ Lhu(a4, FieldMemOperand(a4, Map::kInstanceTypeOffset)); ++ __ Branch(&push_stack_frame, ne, a4, Operand(FEEDBACK_VECTOR_TYPE)); ++ ++ // Read off the optimized code slot in the feedback vector, and if there ++ // is optimized code or an optimization marker, call that instead. ++ Register optimized_code_entry = a4; ++ __ Ld(optimized_code_entry, ++ FieldMemOperand(feedback_vector, ++ FeedbackVector::kOptimizedCodeWeakOrSmiOffset)); ++ ++ // Check if the optimized code slot is not empty. ++ Label optimized_code_slot_not_empty; ++ ++ __ Branch(&optimized_code_slot_not_empty, ne, optimized_code_entry, ++ Operand(Smi::FromEnum(OptimizationMarker::kNone))); ++ ++ Label not_optimized; ++ __ bind(¬_optimized); ++ ++ // Increment invocation count for the function. ++ __ Lw(a4, FieldMemOperand(feedback_vector, ++ FeedbackVector::kInvocationCountOffset)); ++ __ Add32(a4, a4, Operand(1)); ++ __ Sw(a4, FieldMemOperand(feedback_vector, ++ FeedbackVector::kInvocationCountOffset)); ++ ++ // Open a frame scope to indicate that there is a frame on the stack. The ++ // MANUAL indicates that the scope shouldn't actually generate code to set up ++ // the frame (that is done below). ++ __ bind(&push_stack_frame); ++ FrameScope frame_scope(masm, StackFrame::MANUAL); ++ __ PushStandardFrame(closure); ++ ++ // Reset code age and the OSR arming. The OSR field and BytecodeAgeOffset are ++ // 8-bit fields next to each other, so we could just optimize by writing a ++ // 16-bit. These static asserts guard our assumption is valid. ++ STATIC_ASSERT(BytecodeArray::kBytecodeAgeOffset == ++ BytecodeArray::kOsrNestingLevelOffset + kCharSize); ++ STATIC_ASSERT(BytecodeArray::kNoAgeBytecodeAge == 0); ++ __ Sh(zero_reg, FieldMemOperand(kInterpreterBytecodeArrayRegister, ++ BytecodeArray::kOsrNestingLevelOffset)); ++ ++ // Load initial bytecode offset. ++ __ li(kInterpreterBytecodeOffsetRegister, ++ Operand(BytecodeArray::kHeaderSize - kHeapObjectTag)); ++ ++ // Push bytecode array and Smi tagged bytecode array offset. ++ __ SmiTag(a4, kInterpreterBytecodeOffsetRegister); ++ __ Push(kInterpreterBytecodeArrayRegister, a4); ++ ++ // Allocate the local and temporary register file on the stack. ++ Label stack_overflow; ++ { ++ // Load frame size (word) from the BytecodeArray object. ++ __ Lw(a4, FieldMemOperand(kInterpreterBytecodeArrayRegister, ++ BytecodeArray::kFrameSizeOffset)); ++ ++ // Do a stack check to ensure we don't go over the limit. ++ __ Sub64(a5, sp, Operand(a4)); ++ LoadStackLimit(masm, a2, StackLimitKind::kRealStackLimit); ++ __ Branch(&stack_overflow, Uless, a5, Operand(a2)); ++ ++ // If ok, push undefined as the initial value for all register file entries. ++ Label loop_header; ++ Label loop_check; ++ __ LoadRoot(a5, RootIndex::kUndefinedValue); ++ __ Branch(&loop_check); ++ __ bind(&loop_header); ++ // TODO(rmcilroy): Consider doing more than one push per loop iteration. ++ __ push(a5); ++ // Continue loop if not done. ++ __ bind(&loop_check); ++ __ Sub64(a4, a4, Operand(kPointerSize)); ++ __ Branch(&loop_header, ge, a4, Operand(zero_reg)); ++ } ++ ++ // If the bytecode array has a valid incoming new target or generator object ++ // register, initialize it with incoming value which was passed in r3. ++ Label no_incoming_new_target_or_generator_register; ++ __ Lw(a5, FieldMemOperand( ++ kInterpreterBytecodeArrayRegister, ++ BytecodeArray::kIncomingNewTargetOrGeneratorRegisterOffset)); ++ __ Branch(&no_incoming_new_target_or_generator_register, eq, a5, ++ Operand(zero_reg)); ++ __ CalcScaledAddress(a5, fp, a5, kPointerSizeLog2); ++ __ Sd(a3, MemOperand(a5)); ++ __ bind(&no_incoming_new_target_or_generator_register); ++ ++ // Perform interrupt stack check. ++ // TODO(solanes): Merge with the real stack limit check above. ++ Label stack_check_interrupt, after_stack_check_interrupt; ++ LoadStackLimit(masm, a5, StackLimitKind::kInterruptStackLimit); ++ __ Branch(&stack_check_interrupt, Uless, sp, Operand(a5)); ++ __ bind(&after_stack_check_interrupt); ++ ++ // Load accumulator as undefined. ++ __ LoadRoot(kInterpreterAccumulatorRegister, RootIndex::kUndefinedValue); ++ ++ // Load the dispatch table into a register and dispatch to the bytecode ++ // handler at the current bytecode offset. ++ Label do_dispatch; ++ __ bind(&do_dispatch); ++ __ li(kInterpreterDispatchTableRegister, ++ ExternalReference::interpreter_dispatch_table_address(masm->isolate())); ++ __ Add64(a1, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister); ++ __ Lbu(a7, MemOperand(a1)); ++ __ CalcScaledAddress(kScratchReg, kInterpreterDispatchTableRegister, a7, ++ kPointerSizeLog2); ++ __ Ld(kJavaScriptCallCodeStartRegister, MemOperand(kScratchReg)); ++ __ Call(kJavaScriptCallCodeStartRegister); ++ masm->isolate()->heap()->SetInterpreterEntryReturnPCOffset(masm->pc_offset()); ++ ++ // Any returns to the entry trampoline are either due to the return bytecode ++ // or the interpreter tail calling a builtin and then a dispatch. ++ ++ // Get bytecode array and bytecode offset from the stack frame. ++ __ Ld(kInterpreterBytecodeArrayRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp)); ++ __ Ld(kInterpreterBytecodeOffsetRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ __ SmiUntag(kInterpreterBytecodeOffsetRegister); ++ ++ // Either return, or advance to the next bytecode and dispatch. ++ Label do_return; ++ __ Add64(a1, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister); ++ __ Lbu(a1, MemOperand(a1)); ++ AdvanceBytecodeOffsetOrReturn(masm, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister, a1, a2, a3, ++ a4, &do_return); ++ __ Branch(&do_dispatch); ++ ++ __ bind(&do_return); ++ // The return value is in a0. ++ LeaveInterpreterFrame(masm, t0); ++ __ Jump(ra); ++ ++ __ bind(&stack_check_interrupt); ++ // Modify the bytecode offset in the stack to be kFunctionEntryBytecodeOffset ++ // for the call to the StackGuard. ++ __ li(kInterpreterBytecodeOffsetRegister, ++ Operand(Smi::FromInt(BytecodeArray::kHeaderSize - kHeapObjectTag + ++ kFunctionEntryBytecodeOffset))); ++ __ Sd(kInterpreterBytecodeOffsetRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ __ CallRuntime(Runtime::kStackGuard); ++ ++ // After the call, restore the bytecode array, bytecode offset and accumulator ++ // registers again. Also, restore the bytecode offset in the stack to its ++ // previous value. ++ __ Ld(kInterpreterBytecodeArrayRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp)); ++ __ li(kInterpreterBytecodeOffsetRegister, ++ Operand(BytecodeArray::kHeaderSize - kHeapObjectTag)); ++ __ LoadRoot(kInterpreterAccumulatorRegister, RootIndex::kUndefinedValue); ++ ++ __ SmiTag(a5, kInterpreterBytecodeOffsetRegister); ++ __ Sd(a5, MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ ++ __ Branch(&after_stack_check_interrupt); ++ ++ __ bind(&optimized_code_slot_not_empty); ++ Label maybe_has_optimized_code; ++ // Check if optimized code marker is actually a weak reference to the ++ // optimized code as opposed to an optimization marker. ++ __ JumpIfNotSmi(optimized_code_entry, &maybe_has_optimized_code); ++ MaybeOptimizeCode(masm, feedback_vector, optimized_code_entry); ++ // Fall through if there's no runnable optimized code. ++ __ Branch(¬_optimized); ++ ++ __ bind(&maybe_has_optimized_code); ++ // Load code entry from the weak reference, if it was cleared, resume ++ // execution of unoptimized code. ++ __ LoadWeakValue(optimized_code_entry, optimized_code_entry, ¬_optimized); ++ TailCallOptimizedCodeSlot(masm, optimized_code_entry, t4, a5); ++ ++ __ bind(&compile_lazy); ++ GenerateTailCallToReturnedCode(masm, Runtime::kCompileLazy); ++ // Unreachable code. ++ __ break_(0xCC); ++ ++ __ bind(&stack_overflow); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ // Unreachable code. ++ __ break_(0xCC); ++} ++ ++static void Generate_InterpreterPushArgs(MacroAssembler* masm, ++ Register num_args, Register index, ++ Register scratch, Register scratch2) { ++ // Find the address of the last argument. ++ __ Move(scratch2, num_args); ++ __ Sll64(scratch2, scratch2, kPointerSizeLog2); ++ __ Sub64(scratch2, index, Operand(scratch2)); ++ ++ // Push the arguments. ++ Label loop_header, loop_check; ++ __ Branch(&loop_check); ++ __ bind(&loop_header); ++ __ Ld(scratch, MemOperand(index)); ++ __ Add64(index, index, Operand(-kPointerSize)); ++ __ push(scratch); ++ __ bind(&loop_check); ++ __ Branch(&loop_header, Ugreater, index, Operand(scratch2)); ++} ++ ++// static ++void Builtins::Generate_InterpreterPushArgsThenCallImpl( ++ MacroAssembler* masm, ConvertReceiverMode receiver_mode, ++ InterpreterPushArgsMode mode) { ++ DCHECK(mode != InterpreterPushArgsMode::kArrayFunction); ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a2 : the address of the first argument to be pushed. Subsequent ++ // arguments should be consecutive above this, in the same order as ++ // they are to be pushed onto the stack. ++ // -- a1 : the target to call (can be any Object). ++ // ----------------------------------- ++ Label stack_overflow; ++ ++ __ Add64(a3, a0, Operand(1)); // Add one for receiver. ++ ++ // Push "undefined" as the receiver arg if we need to. ++ if (receiver_mode == ConvertReceiverMode::kNullOrUndefined) { ++ __ PushRoot(RootIndex::kUndefinedValue); ++ __ Sub64(a3, a3, Operand(1)); // Subtract one for receiver. ++ } ++ ++ Generate_StackOverflowCheck(masm, a3, a4, t0, &stack_overflow); ++ ++ // This function modifies a2, t0 and a4. ++ Generate_InterpreterPushArgs(masm, a3, a2, a4, t0); ++ ++ if (mode == InterpreterPushArgsMode::kWithFinalSpread) { ++ __ Pop(a2); // Pass the spread in a register ++ __ Sub64(a0, a0, Operand(1)); // Subtract one for spread ++ } ++ ++ // Call the target. ++ if (mode == InterpreterPushArgsMode::kWithFinalSpread) { ++ __ Jump(BUILTIN_CODE(masm->isolate(), CallWithSpread), ++ RelocInfo::CODE_TARGET); ++ } else { ++ __ Jump(masm->isolate()->builtins()->Call(ConvertReceiverMode::kAny), ++ RelocInfo::CODE_TARGET); ++ } ++ ++ __ bind(&stack_overflow); ++ { ++ __ TailCallRuntime(Runtime::kThrowStackOverflow); ++ // Unreachable code. ++ __ break_(0xCC); ++ } ++} ++ ++// static ++void Builtins::Generate_InterpreterPushArgsThenConstructImpl( ++ MacroAssembler* masm, InterpreterPushArgsMode mode) { ++ // ----------- S t a t e ------------- ++ // -- a0 : argument count (not including receiver) ++ // -- a3 : new target ++ // -- a1 : constructor to call ++ // -- a2 : allocation site feedback if available, undefined otherwise. ++ // -- a4 : address of the first argument ++ // ----------------------------------- ++ Label stack_overflow; ++ ++ // Push a slot for the receiver. ++ __ push(zero_reg); ++ ++ Generate_StackOverflowCheck(masm, a0, a5, t0, &stack_overflow); ++ ++ // This function modifies t0, a4 and a5. ++ Generate_InterpreterPushArgs(masm, a0, a4, a5, t0); ++ ++ if (mode == InterpreterPushArgsMode::kWithFinalSpread) { ++ __ Pop(a2); // Pass the spread in a register ++ __ Sub64(a0, a0, Operand(1)); // Subtract one for spread ++ } else { ++ __ AssertUndefinedOrAllocationSite(a2, t0); ++ } ++ ++ if (mode == InterpreterPushArgsMode::kArrayFunction) { ++ __ AssertFunction(a1); ++ ++ // Tail call to the function-specific construct stub (still in the caller ++ // context at this point). ++ __ Jump(BUILTIN_CODE(masm->isolate(), ArrayConstructorImpl), ++ RelocInfo::CODE_TARGET); ++ } else if (mode == InterpreterPushArgsMode::kWithFinalSpread) { ++ // Call the constructor with a0, a1, and a3 unmodified. ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructWithSpread), ++ RelocInfo::CODE_TARGET); ++ } else { ++ DCHECK_EQ(InterpreterPushArgsMode::kOther, mode); ++ // Call the constructor with a0, a1, and a3 unmodified. ++ __ Jump(BUILTIN_CODE(masm->isolate(), Construct), RelocInfo::CODE_TARGET); ++ } ++ ++ __ bind(&stack_overflow); ++ { ++ __ TailCallRuntime(Runtime::kThrowStackOverflow); ++ // Unreachable code. ++ __ break_(0xCC); ++ } ++} ++ ++static void Generate_InterpreterEnterBytecode(MacroAssembler* masm) { ++ // Set the return address to the correct point in the interpreter entry ++ // trampoline. ++ Label builtin_trampoline, trampoline_loaded; ++ Smi interpreter_entry_return_pc_offset( ++ masm->isolate()->heap()->interpreter_entry_return_pc_offset()); ++ DCHECK_NE(interpreter_entry_return_pc_offset, Smi::zero()); ++ ++ // If the SFI function_data is an InterpreterData, the function will have a ++ // custom copy of the interpreter entry trampoline for profiling. If so, ++ // get the custom trampoline, otherwise grab the entry address of the global ++ // trampoline. ++ __ Ld(t0, MemOperand(fp, StandardFrameConstants::kFunctionOffset)); ++ __ Ld(t0, FieldMemOperand(t0, JSFunction::kSharedFunctionInfoOffset)); ++ __ Ld(t0, FieldMemOperand(t0, SharedFunctionInfo::kFunctionDataOffset)); ++ __ GetObjectType(t0, kInterpreterDispatchTableRegister, ++ kInterpreterDispatchTableRegister); ++ __ Branch(&builtin_trampoline, ne, kInterpreterDispatchTableRegister, ++ Operand(INTERPRETER_DATA_TYPE)); ++ ++ __ Ld(t0, FieldMemOperand(t0, InterpreterData::kInterpreterTrampolineOffset)); ++ __ Add64(t0, t0, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Branch(&trampoline_loaded); ++ ++ __ bind(&builtin_trampoline); ++ __ li(t0, ExternalReference:: ++ address_of_interpreter_entry_trampoline_instruction_start( ++ masm->isolate())); ++ __ Ld(t0, MemOperand(t0)); ++ ++ __ bind(&trampoline_loaded); ++ __ Add64(ra, t0, Operand(interpreter_entry_return_pc_offset.value())); ++ ++ // Initialize the dispatch table register. ++ __ li(kInterpreterDispatchTableRegister, ++ ExternalReference::interpreter_dispatch_table_address(masm->isolate())); ++ ++ // Get the bytecode array pointer from the frame. ++ __ Ld(kInterpreterBytecodeArrayRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp)); ++ ++ if (FLAG_debug_code) { ++ // Check function data field is actually a BytecodeArray object. ++ __ SmiTst(kInterpreterBytecodeArrayRegister, kScratchReg); ++ __ Assert(ne, ++ AbortReason::kFunctionDataShouldBeBytecodeArrayOnInterpreterEntry, ++ kScratchReg, Operand(zero_reg)); ++ __ GetObjectType(kInterpreterBytecodeArrayRegister, a1, a1); ++ __ Assert(eq, ++ AbortReason::kFunctionDataShouldBeBytecodeArrayOnInterpreterEntry, ++ a1, Operand(BYTECODE_ARRAY_TYPE)); ++ } ++ ++ // Get the target bytecode offset from the frame. ++ __ SmiUntag(kInterpreterBytecodeOffsetRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ ++ if (FLAG_debug_code) { ++ Label okay; ++ __ Branch(&okay, ge, kInterpreterBytecodeOffsetRegister, ++ Operand(BytecodeArray::kHeaderSize - kHeapObjectTag)); ++ // Unreachable code. ++ __ break_(0xCC); ++ __ bind(&okay); ++ } ++ ++ // Dispatch to the target bytecode. ++ __ Add64(a1, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister); ++ __ Lbu(a7, MemOperand(a1)); ++ __ CalcScaledAddress(a1, kInterpreterDispatchTableRegister, a7, ++ kPointerSizeLog2); ++ __ Ld(kJavaScriptCallCodeStartRegister, MemOperand(a1)); ++ __ Jump(kJavaScriptCallCodeStartRegister); ++} ++ ++void Builtins::Generate_InterpreterEnterBytecodeAdvance(MacroAssembler* masm) { ++ // Advance the current bytecode offset stored within the given interpreter ++ // stack frame. This simulates what all bytecode handlers do upon completion ++ // of the underlying operation. ++ __ Ld(kInterpreterBytecodeArrayRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeArrayFromFp)); ++ __ Ld(kInterpreterBytecodeOffsetRegister, ++ MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ __ SmiUntag(kInterpreterBytecodeOffsetRegister); ++ ++ Label enter_bytecode, function_entry_bytecode; ++ __ Branch(&function_entry_bytecode, eq, kInterpreterBytecodeOffsetRegister, ++ Operand(BytecodeArray::kHeaderSize - kHeapObjectTag + ++ kFunctionEntryBytecodeOffset)); ++ ++ // Load the current bytecode. ++ __ Add64(a1, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister); ++ __ Lbu(a1, MemOperand(a1)); ++ ++ // Advance to the next bytecode. ++ Label if_return; ++ AdvanceBytecodeOffsetOrReturn(masm, kInterpreterBytecodeArrayRegister, ++ kInterpreterBytecodeOffsetRegister, a1, a2, a3, ++ a4, &if_return); ++ ++ __ bind(&enter_bytecode); ++ // Convert new bytecode offset to a Smi and save in the stackframe. ++ __ SmiTag(a2, kInterpreterBytecodeOffsetRegister); ++ __ Sd(a2, MemOperand(fp, InterpreterFrameConstants::kBytecodeOffsetFromFp)); ++ ++ Generate_InterpreterEnterBytecode(masm); ++ ++ __ bind(&function_entry_bytecode); ++ // If the code deoptimizes during the implicit function entry stack interrupt ++ // check, it will have a bailout ID of kFunctionEntryBytecodeOffset, which is ++ // not a valid bytecode offset. Detect this case and advance to the first ++ // actual bytecode. ++ __ li(kInterpreterBytecodeOffsetRegister, ++ Operand(BytecodeArray::kHeaderSize - kHeapObjectTag)); ++ __ Branch(&enter_bytecode); ++ ++ // We should never take the if_return path. ++ __ bind(&if_return); ++ __ Abort(AbortReason::kInvalidBytecodeAdvance); ++} ++ ++void Builtins::Generate_InterpreterEnterBytecodeDispatch(MacroAssembler* masm) { ++ Generate_InterpreterEnterBytecode(masm); ++} ++ ++namespace { ++void Generate_ContinueToBuiltinHelper(MacroAssembler* masm, ++ bool java_script_builtin, ++ bool with_result) { ++ const RegisterConfiguration* config(RegisterConfiguration::Default()); ++ int allocatable_register_count = config->num_allocatable_general_registers(); ++ if (with_result) { ++ // Overwrite the hole inserted by the deoptimizer with the return value from ++ // the LAZY deopt point. ++ __ Sd(a0, ++ MemOperand( ++ sp, config->num_allocatable_general_registers() * kPointerSize + ++ BuiltinContinuationFrameConstants::kFixedFrameSize)); ++ } ++ for (int i = allocatable_register_count - 1; i >= 0; --i) { ++ int code = config->GetAllocatableGeneralCode(i); ++ __ Pop(Register::from_code(code)); ++ if (java_script_builtin && code == kJavaScriptCallArgCountRegister.code()) { ++ __ SmiUntag(Register::from_code(code)); ++ } ++ } ++ __ Ld(fp, MemOperand( ++ sp, BuiltinContinuationFrameConstants::kFixedFrameSizeFromFp)); ++ // Load builtin index (stored as a Smi) and use it to get the builtin start ++ // address from the builtins table. ++ __ Pop(t0); ++ __ Add64(sp, sp, ++ Operand(BuiltinContinuationFrameConstants::kFixedFrameSizeFromFp)); ++ __ Pop(ra); ++ __ LoadEntryFromBuiltinIndex(t0); ++ __ Jump(t0); ++} ++} // namespace ++ ++void Builtins::Generate_ContinueToCodeStubBuiltin(MacroAssembler* masm) { ++ Generate_ContinueToBuiltinHelper(masm, false, false); ++} ++ ++void Builtins::Generate_ContinueToCodeStubBuiltinWithResult( ++ MacroAssembler* masm) { ++ Generate_ContinueToBuiltinHelper(masm, false, true); ++} ++ ++void Builtins::Generate_ContinueToJavaScriptBuiltin(MacroAssembler* masm) { ++ Generate_ContinueToBuiltinHelper(masm, true, false); ++} ++ ++void Builtins::Generate_ContinueToJavaScriptBuiltinWithResult( ++ MacroAssembler* masm) { ++ Generate_ContinueToBuiltinHelper(masm, true, true); ++} ++ ++void Builtins::Generate_NotifyDeoptimized(MacroAssembler* masm) { ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kNotifyDeoptimized); ++ } ++ ++ DCHECK_EQ(kInterpreterAccumulatorRegister.code(), a0.code()); ++ __ Ld(a0, MemOperand(sp, 0 * kPointerSize)); ++ __ Add64(sp, sp, Operand(1 * kPointerSize)); // Remove state. ++ __ Ret(); ++} ++ ++void Builtins::Generate_InterpreterOnStackReplacement(MacroAssembler* masm) { ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kCompileForOnStackReplacement); ++ } ++ ++ // If the code object is null, just return to the caller. ++ __ Ret(eq, a0, Operand(Smi::zero())); ++ ++ // Drop the handler frame that is be sitting on top of the actual ++ // JavaScript frame. This is the case then OSR is triggered from bytecode. ++ __ LeaveFrame(StackFrame::STUB); ++ ++ // Load deoptimization data from the code object. ++ // = [#deoptimization_data_offset] ++ __ Ld(a1, MemOperand(a0, Code::kDeoptimizationDataOffset - kHeapObjectTag)); ++ ++ // Load the OSR entrypoint offset from the deoptimization data. ++ // = [#header_size + #osr_pc_offset] ++ __ SmiUntag(a1, MemOperand(a1, FixedArray::OffsetOfElementAt( ++ DeoptimizationData::kOsrPcOffsetIndex) - ++ kHeapObjectTag)); ++ ++ // Compute the target address = code_obj + header_size + osr_offset ++ // = + #header_size + ++ __ Add64(a0, a0, a1); ++ __ Add64(ra, a0, Code::kHeaderSize - kHeapObjectTag); ++ // And "return" to the OSR entry point of the function. ++ __ Ret(); ++} ++ ++// static ++void Builtins::Generate_FunctionPrototypeApply(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : argc ++ // -- sp[0] : argArray ++ // -- sp[4] : thisArg ++ // -- sp[8] : receiver ++ // ----------------------------------- ++ ++ Register argc = a0; ++ Register arg_array = a2; ++ Register receiver = a1; ++ Register this_arg = a5; ++ Register undefined_value = a3; ++ ++ __ LoadRoot(undefined_value, RootIndex::kUndefinedValue); ++ ++ // 1. Load receiver into a1, argArray into a2 (if present), remove all ++ // arguments from the stack (including the receiver), and push thisArg (if ++ // present) instead. ++ { ++ // Claim (2 - argc) dummy arguments form the stack, to put the stack in a ++ // consistent state for a simple pop operation. ++ ++ __ Sub64(sp, sp, Operand(2 * kPointerSize)); ++ __ CalcScaledAddress(sp, sp, argc, kPointerSizeLog2); ++ __ Pop(this_arg, arg_array); // Overwrite argc ++ ++ Label done0, done1; ++ __ Branch(&done0, ne, argc, Operand(zero_reg)); ++ __ Move(arg_array, undefined_value); // if argc == 0 ++ __ Move(this_arg, undefined_value); // if argc == 0 ++ __ bind(&done0); // else (i.e., argc > 0) ++ ++ __ Branch(&done1, ne, argc, Operand(1)); ++ __ Move(arg_array, undefined_value); // if argc == 1 ++ __ bind(&done1); // else (i.e., argc > 1) ++ ++ __ Ld(receiver, MemOperand(sp)); ++ __ Sd(this_arg, MemOperand(sp)); ++ } ++ ++ // ----------- S t a t e ------------- ++ // -- a2 : argArray ++ // -- a1 : receiver ++ // -- a3 : undefined root value ++ // -- sp[0] : thisArg ++ // ----------------------------------- ++ ++ // 2. We don't need to check explicitly for callable receiver here, ++ // since that's the first thing the Call/CallWithArrayLike builtins ++ // will do. ++ ++ // 3. Tail call with no arguments if argArray is null or undefined. ++ Label no_arguments; ++ __ JumpIfRoot(arg_array, RootIndex::kNullValue, &no_arguments); ++ __ Branch(&no_arguments, eq, arg_array, Operand(undefined_value)); ++ ++ // 4a. Apply the receiver to the given argArray. ++ __ Jump(BUILTIN_CODE(masm->isolate(), CallWithArrayLike), ++ RelocInfo::CODE_TARGET); ++ ++ // 4b. The argArray is either null or undefined, so we tail call without any ++ // arguments to the receiver. ++ __ bind(&no_arguments); ++ { ++ __ Move(a0, zero_reg); ++ DCHECK(receiver == a1); ++ __ Jump(masm->isolate()->builtins()->Call(), RelocInfo::CODE_TARGET); ++ } ++} ++ ++// static ++void Builtins::Generate_FunctionPrototypeCall(MacroAssembler* masm) { ++ // 1. Make sure we have at least one argument. ++ // a0: actual number of arguments ++ { ++ Label done; ++ __ Branch(&done, ne, a0, Operand(zero_reg)); ++ __ PushRoot(RootIndex::kUndefinedValue); ++ __ Add64(a0, a0, Operand(1)); ++ __ bind(&done); ++ } ++ ++ // 2. Get the function to call (passed as receiver) from the stack. ++ // a0: actual number of arguments ++ __ CalcScaledAddress(kScratchReg, sp, a0, kPointerSizeLog2); ++ __ Ld(a1, MemOperand(kScratchReg)); ++ ++ // 3. Shift arguments and return address one slot down on the stack ++ // (overwriting the original receiver). Adjust argument count to make ++ // the original first argument the new receiver. ++ // a0: actual number of arguments ++ // a1: function ++ { ++ Label loop; ++ // Calculate the copy start address (destination). Copy end address is sp. ++ __ CalcScaledAddress(a2, sp, a0, kPointerSizeLog2); ++ ++ __ bind(&loop); ++ __ Ld(kScratchReg, MemOperand(a2, -kPointerSize)); ++ __ Sd(kScratchReg, MemOperand(a2)); ++ __ Sub64(a2, a2, Operand(kPointerSize)); ++ __ Branch(&loop, ne, a2, Operand(sp)); ++ // Adjust the actual number of arguments and remove the top element ++ // (which is a copy of the last argument). ++ __ Sub64(a0, a0, Operand(1)); ++ __ Pop(); ++ } ++ ++ // 4. Call the callable. ++ __ Jump(masm->isolate()->builtins()->Call(), RelocInfo::CODE_TARGET); ++} ++ ++void Builtins::Generate_ReflectApply(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : argc ++ // -- sp[0] : argumentsList (if argc ==3) ++ // -- sp[4] : thisArgument (if argc >=2) ++ // -- sp[8] : target (if argc >=1) ++ // -- sp[12] : receiver ++ // ----------------------------------- ++ ++ Register argc = a0; ++ Register arguments_list = a2; ++ Register target = a1; ++ Register this_argument = a5; ++ Register undefined_value = a3; ++ ++ __ LoadRoot(undefined_value, RootIndex::kUndefinedValue); ++ ++ // 1. Load target into a1 (if present), argumentsList into a2 (if present), ++ // remove all arguments from the stack (including the receiver), and push ++ // thisArgument (if present) instead. ++ { ++ // Claim (3 - argc) dummy arguments form the stack, to put the stack in a ++ // consistent state for a simple pop operation. ++ ++ __ Sub64(sp, sp, Operand(3 * kPointerSize)); ++ __ CalcScaledAddress(sp, sp, argc, kPointerSizeLog2); ++ __ Pop(target, this_argument, arguments_list); ++ ++ Label done0, done1, done2; ++ __ Branch(&done0, ne, argc, Operand(zero_reg)); ++ __ Move(arguments_list, undefined_value); // if argc == 0 ++ __ Move(this_argument, undefined_value); // if argc == 0 ++ __ Move(target, undefined_value); // if argc == 0 ++ __ bind(&done0); // argc != 0 ++ ++ __ Branch(&done1, ne, argc, Operand(1)); ++ __ Move(arguments_list, undefined_value); // if argc == 1 ++ __ Move(this_argument, undefined_value); // if argc == 1 ++ __ bind(&done1); // argc > 1 ++ ++ __ Branch(&done2, ne, argc, Operand(2)); ++ __ Move(arguments_list, undefined_value); // if argc == 2 ++ __ bind(&done2); // argc > 2 ++ ++ __ Sd(this_argument, MemOperand(sp, 0)); // Overwrite receiver ++ } ++ ++ // ----------- S t a t e ------------- ++ // -- a2 : argumentsList ++ // -- a1 : target ++ // -- a3 : undefined root value ++ // -- sp[0] : thisArgument ++ // ----------------------------------- ++ ++ // 2. We don't need to check explicitly for callable target here, ++ // since that's the first thing the Call/CallWithArrayLike builtins ++ // will do. ++ ++ // 3. Apply the target to the given argumentsList. ++ __ Jump(BUILTIN_CODE(masm->isolate(), CallWithArrayLike), ++ RelocInfo::CODE_TARGET); ++} ++ ++void Builtins::Generate_ReflectConstruct(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : argc ++ // -- sp[0] : new.target (optional) (dummy value if argc <= 2) ++ // -- sp[4] : argumentsList (dummy value if argc <= 1) ++ // -- sp[8] : target (dummy value if argc == 0) ++ // -- sp[12] : receiver ++ // ----------------------------------- ++ Register argc = a0; ++ Register arguments_list = a2; ++ Register target = a1; ++ Register new_target = a3; ++ Register undefined_value = a4; ++ ++ __ LoadRoot(undefined_value, RootIndex::kUndefinedValue); ++ ++ // 1. Load target into a1 (if present), argumentsList into a2 (if present), ++ // new.target into a3 (if present, otherwise use target), remove all ++ // arguments from the stack (including the receiver), and push thisArgument ++ // (if present) instead. ++ { ++ // Claim (3 - argc) dummy arguments form the stack, to put the stack in a ++ // consistent state for a simple pop operation. ++ __ Sub64(sp, sp, Operand(3 * kPointerSize)); ++ __ CalcScaledAddress(sp, sp, argc, kPointerSizeLog2); ++ __ Pop(target, arguments_list, new_target); ++ ++ Label done0, done1, done2; ++ __ Branch(&done0, ne, argc, Operand(zero_reg)); ++ __ Move(arguments_list, undefined_value); // if argc == 0 ++ __ Move(new_target, undefined_value); // if argc == 0 ++ __ Move(target, undefined_value); // if argc == 0 ++ __ bind(&done0); ++ ++ __ Branch(&done1, ne, argc, Operand(1)); ++ __ Move(arguments_list, undefined_value); // if argc == 1 ++ __ Move(new_target, target); // if argc == 1 ++ __ bind(&done1); ++ ++ __ Branch(&done2, ne, argc, Operand(2)); ++ __ Move(new_target, target); // if argc == 2 ++ __ bind(&done2); ++ ++ __ Sd(undefined_value, MemOperand(sp, 0)); // Overwrite receiver ++ } ++ ++ // ----------- S t a t e ------------- ++ // -- a2 : argumentsList ++ // -- a1 : target ++ // -- a3 : new.target ++ // -- sp[0] : receiver (undefined) ++ // ----------------------------------- ++ ++ // 2. We don't need to check explicitly for constructor target here, ++ // since that's the first thing the Construct/ConstructWithArrayLike ++ // builtins will do. ++ ++ // 3. We don't need to check explicitly for constructor new.target here, ++ // since that's the second thing the Construct/ConstructWithArrayLike ++ // builtins will do. ++ ++ // 4. Construct the target with the given new.target and argumentsList. ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructWithArrayLike), ++ RelocInfo::CODE_TARGET); ++} ++ ++static void EnterArgumentsAdaptorFrame(MacroAssembler* masm) { ++ __ SmiTag(a0); ++ __ li(a4, Operand(StackFrame::TypeToMarker(StackFrame::ARGUMENTS_ADAPTOR))); ++ __ MultiPush(a0.bit() | a1.bit() | a4.bit() | fp.bit() | ra.bit()); ++ __ Push(Smi::zero()); // Padding. ++ __ Add64(fp, sp, ++ Operand(ArgumentsAdaptorFrameConstants::kFixedFrameSizeFromFp)); ++} ++ ++static void LeaveArgumentsAdaptorFrame(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : result being passed through ++ // ----------------------------------- ++ // Get the number of arguments passed (as a smi), tear down the frame and ++ // then tear down the parameters. ++ __ Ld(a1, MemOperand(fp, ArgumentsAdaptorFrameConstants::kLengthOffset)); ++ __ Move(sp, fp); ++ __ MultiPop(fp.bit() | ra.bit()); ++ __ SmiScale(a4, a1, kPointerSizeLog2); ++ __ Add64(sp, sp, a4); ++ // Adjust for the receiver. ++ __ Add64(sp, sp, Operand(kPointerSize)); ++} ++ ++// static ++void Builtins::Generate_CallOrConstructVarargs(MacroAssembler* masm, ++ Handle code) { ++ // ----------- S t a t e ------------- ++ // -- a1 : target ++ // -- a0 : number of parameters on the stack (not including the receiver) ++ // -- a2 : arguments list (a FixedArray) ++ // -- a4 : len (number of elements to push from args) ++ // -- a3 : new.target (for [[Construct]]) ++ // ----------------------------------- ++ if (masm->emit_debug_code()) { ++ // Allow a2 to be a FixedArray, or a FixedDoubleArray if a4 == 0. ++ Label ok, fail; ++ __ AssertNotSmi(a2); ++ __ GetObjectType(a2, t5, t5); ++ __ Branch(&ok, eq, t5, Operand(FIXED_ARRAY_TYPE)); ++ __ Branch(&fail, ne, t5, Operand(FIXED_DOUBLE_ARRAY_TYPE)); ++ __ Branch(&ok, eq, a4, Operand(zero_reg)); ++ // Fall through. ++ __ bind(&fail); ++ __ Abort(AbortReason::kOperandIsNotAFixedArray); ++ ++ __ bind(&ok); ++ } ++ ++ Register args = a2; ++ Register len = a4; ++ ++ // Check for stack overflow. ++ Label stack_overflow; ++ Generate_StackOverflowCheck(masm, len, kScratchReg, a5, &stack_overflow); ++ ++ // Push arguments onto the stack (thisArgument is already on the stack). ++ { ++ Label done, push, loop; ++ Register src = a6; ++ Register scratch = len; ++ __ Add64(src, args, FixedArray::kHeaderSize - kHeapObjectTag); ++ __ Add64(a0, a0, len); // The 'len' argument for Call() or Construct(). ++ __ Branch(&done, eq, len, Operand(zero_reg)); ++ __ Sll64(scratch, len, kPointerSizeLog2); ++ __ Sub64(scratch, sp, Operand(scratch)); ++ __ LoadRoot(t1, RootIndex::kTheHoleValue); ++ __ bind(&loop); ++ __ Ld(a5, MemOperand(src)); ++ __ Branch(&push, ne, a5, Operand(t1)); ++ __ LoadRoot(a5, RootIndex::kUndefinedValue); ++ __ bind(&push); ++ __ Add64(src, src, kPointerSize); ++ __ Push(a5); ++ __ Branch(&loop, ne, scratch, Operand(sp)); ++ __ bind(&done); ++ } ++ ++ // Tail-call to the actual Call or Construct builtin. ++ __ Jump(code, RelocInfo::CODE_TARGET); ++ ++ __ bind(&stack_overflow); ++ __ TailCallRuntime(Runtime::kThrowStackOverflow); ++} ++ ++// static ++void Builtins::Generate_CallOrConstructForwardVarargs(MacroAssembler* masm, ++ CallOrConstructMode mode, ++ Handle code) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a3 : the new.target (for [[Construct]] calls) ++ // -- a1 : the target to call (can be any Object) ++ // -- a2 : start index (to support rest parameters) ++ // ----------------------------------- ++ ++ // Check if new.target has a [[Construct]] internal method. ++ if (mode == CallOrConstructMode::kConstruct) { ++ Label new_target_constructor, new_target_not_constructor; ++ __ JumpIfSmi(a3, &new_target_not_constructor); ++ __ Ld(t1, FieldMemOperand(a3, HeapObject::kMapOffset)); ++ __ Lbu(t1, FieldMemOperand(t1, Map::kBitFieldOffset)); ++ __ And(t1, t1, Operand(Map::Bits1::IsConstructorBit::kMask)); ++ __ Branch(&new_target_constructor, ne, t1, Operand(zero_reg)); ++ __ bind(&new_target_not_constructor); ++ { ++ FrameScope scope(masm, StackFrame::MANUAL); ++ __ EnterFrame(StackFrame::INTERNAL); ++ __ Push(a3); ++ __ CallRuntime(Runtime::kThrowNotConstructor); ++ } ++ __ bind(&new_target_constructor); ++ } ++ ++ // Check if we have an arguments adaptor frame below the function frame. ++ Label arguments_adaptor, arguments_done; ++ __ Ld(a6, MemOperand(fp, StandardFrameConstants::kCallerFPOffset)); ++ __ Ld(a7, MemOperand(a6, CommonFrameConstants::kContextOrFrameTypeOffset)); ++ __ Branch(&arguments_adaptor, eq, a7, ++ Operand(StackFrame::TypeToMarker(StackFrame::ARGUMENTS_ADAPTOR))); ++ { ++ __ Ld(a7, MemOperand(fp, StandardFrameConstants::kFunctionOffset)); ++ __ Ld(a7, FieldMemOperand(a7, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lhu(a7, FieldMemOperand( ++ a7, SharedFunctionInfo::kFormalParameterCountOffset)); ++ __ Move(a6, fp); ++ } ++ __ Branch(&arguments_done); ++ __ bind(&arguments_adaptor); ++ { ++ // Just get the length from the ArgumentsAdaptorFrame. ++ __ SmiUntag(a7, ++ MemOperand(a6, ArgumentsAdaptorFrameConstants::kLengthOffset)); ++ } ++ __ bind(&arguments_done); ++ ++ Label stack_done, stack_overflow; ++ __ Sub32(a7, a7, a2); ++ __ Branch(&stack_done, le, a7, Operand(zero_reg)); ++ { ++ // Check for stack overflow. ++ Generate_StackOverflowCheck(masm, a7, a4, a5, &stack_overflow); ++ ++ // Forward the arguments from the caller frame. ++ { ++ Label loop; ++ __ Add64(a0, a0, a7); ++ __ bind(&loop); ++ { ++ __ CalcScaledAddress(kScratchReg, a6, a7, kPointerSizeLog2); ++ __ Ld(kScratchReg, MemOperand(kScratchReg, 1 * kPointerSize)); ++ __ push(kScratchReg); ++ __ Sub32(a7, a7, Operand(1)); ++ __ Branch(&loop, ne, a7, Operand(zero_reg)); ++ } ++ } ++ } ++ __ Branch(&stack_done); ++ __ bind(&stack_overflow); ++ __ TailCallRuntime(Runtime::kThrowStackOverflow); ++ __ bind(&stack_done); ++ ++ // Tail-call to the {code} handler. ++ __ Jump(code, RelocInfo::CODE_TARGET); ++} ++ ++// static ++void Builtins::Generate_CallFunction(MacroAssembler* masm, ++ ConvertReceiverMode mode) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSFunction) ++ // ----------------------------------- ++ __ AssertFunction(a1); ++ ++ // See ES6 section 9.2.1 [[Call]] ( thisArgument, argumentsList) ++ // Check that function is not a "classConstructor". ++ Label class_constructor; ++ __ Ld(a2, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lwu(a3, FieldMemOperand(a2, SharedFunctionInfo::kFlagsOffset)); ++ __ And(kScratchReg, a3, ++ Operand(SharedFunctionInfo::IsClassConstructorBit::kMask)); ++ __ Branch(&class_constructor, ne, kScratchReg, Operand(zero_reg)); ++ ++ // Enter the context of the function; ToObject has to run in the function ++ // context, and we also need to take the global proxy from the function ++ // context in case of conversion. ++ __ Ld(cp, FieldMemOperand(a1, JSFunction::kContextOffset)); ++ // We need to convert the receiver for non-native sloppy mode functions. ++ Label done_convert; ++ __ Lwu(a3, FieldMemOperand(a2, SharedFunctionInfo::kFlagsOffset)); ++ __ And(kScratchReg, a3, ++ Operand(SharedFunctionInfo::IsNativeBit::kMask | ++ SharedFunctionInfo::IsStrictBit::kMask)); ++ __ Branch(&done_convert, ne, kScratchReg, Operand(zero_reg)); ++ { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSFunction) ++ // -- a2 : the shared function info. ++ // -- cp : the function context. ++ // ----------------------------------- ++ ++ if (mode == ConvertReceiverMode::kNullOrUndefined) { ++ // Patch receiver to global proxy. ++ __ LoadGlobalProxy(a3); ++ } else { ++ Label convert_to_object, convert_receiver; ++ __ CalcScaledAddress(kScratchReg, sp, a0, kPointerSizeLog2); ++ __ Ld(a3, MemOperand(kScratchReg)); ++ __ JumpIfSmi(a3, &convert_to_object); ++ STATIC_ASSERT(LAST_JS_RECEIVER_TYPE == LAST_TYPE); ++ __ GetObjectType(a3, a4, a4); ++ __ Branch(&done_convert, Ugreater_equal, a4, ++ Operand(FIRST_JS_RECEIVER_TYPE)); ++ if (mode != ConvertReceiverMode::kNotNullOrUndefined) { ++ Label convert_global_proxy; ++ __ JumpIfRoot(a3, RootIndex::kUndefinedValue, &convert_global_proxy); ++ __ JumpIfNotRoot(a3, RootIndex::kNullValue, &convert_to_object); ++ __ bind(&convert_global_proxy); ++ { ++ // Patch receiver to global proxy. ++ __ LoadGlobalProxy(a3); ++ } ++ __ Branch(&convert_receiver); ++ } ++ __ bind(&convert_to_object); ++ { ++ // Convert receiver using ToObject. ++ // TODO(bmeurer): Inline the allocation here to avoid building the frame ++ // in the fast case? (fall back to AllocateInNewSpace?) ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ SmiTag(a0); ++ __ Push(a0, a1); ++ __ Move(a0, a3); ++ __ Push(cp); ++ __ Call(BUILTIN_CODE(masm->isolate(), ToObject), ++ RelocInfo::CODE_TARGET); ++ __ Pop(cp); ++ __ Move(a3, a0); ++ __ Pop(a0, a1); ++ __ SmiUntag(a0); ++ } ++ __ Ld(a2, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ __ bind(&convert_receiver); ++ } ++ __ CalcScaledAddress(kScratchReg, sp, a0, kPointerSizeLog2); ++ __ Sd(a3, MemOperand(kScratchReg)); ++ } ++ __ bind(&done_convert); ++ ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSFunction) ++ // -- a2 : the shared function info. ++ // -- cp : the function context. ++ // ----------------------------------- ++ ++ __ Lhu(a2, ++ FieldMemOperand(a2, SharedFunctionInfo::kFormalParameterCountOffset)); ++ __ InvokeFunctionCode(a1, no_reg, a2, a0, JUMP_FUNCTION); ++ ++ // The function is a "classConstructor", need to raise an exception. ++ __ bind(&class_constructor); ++ { ++ FrameScope frame(masm, StackFrame::INTERNAL); ++ __ Push(a1); ++ __ CallRuntime(Runtime::kThrowConstructorNonCallableError); ++ } ++} ++ ++// static ++void Builtins::Generate_CallBoundFunctionImpl(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSBoundFunction) ++ // ----------------------------------- ++ __ AssertBoundFunction(a1); ++ ++ // Patch the receiver to [[BoundThis]]. ++ { ++ __ Ld(kScratchReg, FieldMemOperand(a1, JSBoundFunction::kBoundThisOffset)); ++ __ CalcScaledAddress(a4, sp, a0, kPointerSizeLog2); ++ __ Sd(kScratchReg, MemOperand(a4)); ++ } ++ ++ // Load [[BoundArguments]] into a2 and length of that into a4. ++ __ Ld(a2, FieldMemOperand(a1, JSBoundFunction::kBoundArgumentsOffset)); ++ __ SmiUntag(a4, FieldMemOperand(a2, FixedArray::kLengthOffset)); ++ ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSBoundFunction) ++ // -- a2 : the [[BoundArguments]] (implemented as FixedArray) ++ // -- a4 : the number of [[BoundArguments]] ++ // ----------------------------------- ++ ++ // Reserve stack space for the [[BoundArguments]]. ++ { ++ Label done; ++ __ Sll64(a5, a4, kPointerSizeLog2); ++ __ Sub64(sp, sp, Operand(a5)); ++ // Check the stack for overflow. We are not trying to catch interruptions ++ // (i.e. debug break and preemption) here, so check the "real stack limit". ++ LoadStackLimit(masm, kScratchReg, StackLimitKind::kRealStackLimit); ++ __ Branch(&done, Ugreater_equal, sp, Operand(kScratchReg)); ++ // Restore the stack pointer. ++ __ Add64(sp, sp, Operand(a5)); ++ { ++ FrameScope scope(masm, StackFrame::MANUAL); ++ __ EnterFrame(StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ } ++ __ bind(&done); ++ } ++ ++ // Relocate arguments down the stack. ++ { ++ Label loop, done_loop; ++ __ Move(a5, zero_reg); ++ __ bind(&loop); ++ __ Branch(&done_loop, gt, a5, Operand(a0)); ++ __ CalcScaledAddress(a6, sp, a4, kPointerSizeLog2); ++ __ Ld(kScratchReg, MemOperand(a6)); ++ __ CalcScaledAddress(a6, sp, a5, kPointerSizeLog2); ++ __ Sd(kScratchReg, MemOperand(a6)); ++ __ Add64(a4, a4, Operand(1)); ++ __ Add64(a5, a5, Operand(1)); ++ __ Branch(&loop); ++ __ bind(&done_loop); ++ } ++ ++ // Copy [[BoundArguments]] to the stack (below the arguments). ++ { ++ Label loop, done_loop; ++ __ SmiUntag(a4, FieldMemOperand(a2, FixedArray::kLengthOffset)); ++ __ Add64(a2, a2, Operand(FixedArray::kHeaderSize - kHeapObjectTag)); ++ __ bind(&loop); ++ __ Sub64(a4, a4, Operand(1)); ++ __ Branch(&done_loop, lt, a4, Operand(zero_reg)); ++ __ CalcScaledAddress(a5, a2, a4, kPointerSizeLog2); ++ __ Ld(kScratchReg, MemOperand(a5)); ++ __ CalcScaledAddress(a5, sp, a0, kPointerSizeLog2); ++ __ Sd(kScratchReg, MemOperand(a5)); ++ __ Add64(a0, a0, Operand(1)); ++ __ Branch(&loop); ++ __ bind(&done_loop); ++ } ++ ++ // Call the [[BoundTargetFunction]] via the Call builtin. ++ __ Ld(a1, FieldMemOperand(a1, JSBoundFunction::kBoundTargetFunctionOffset)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), Call_ReceiverIsAny), ++ RelocInfo::CODE_TARGET); ++} ++ ++// static ++void Builtins::Generate_Call(MacroAssembler* masm, ConvertReceiverMode mode) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the target to call (can be any Object). ++ // ----------------------------------- ++ ++ Label non_callable, non_smi; ++ __ JumpIfSmi(a1, &non_callable); ++ __ bind(&non_smi); ++ __ GetObjectType(a1, t1, t2); ++ __ Jump(masm->isolate()->builtins()->CallFunction(mode), ++ RelocInfo::CODE_TARGET, eq, t2, Operand(JS_FUNCTION_TYPE)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), CallBoundFunction), ++ RelocInfo::CODE_TARGET, eq, t2, Operand(JS_BOUND_FUNCTION_TYPE)); ++ ++ // Check if target has a [[Call]] internal method. ++ __ Lbu(t1, FieldMemOperand(t1, Map::kBitFieldOffset)); ++ __ And(t1, t1, Operand(Map::Bits1::IsCallableBit::kMask)); ++ __ Branch(&non_callable, eq, t1, Operand(zero_reg)); ++ ++ __ Jump(BUILTIN_CODE(masm->isolate(), CallProxy), RelocInfo::CODE_TARGET, eq, ++ t2, Operand(JS_PROXY_TYPE)); ++ ++ // 2. Call to something else, which might have a [[Call]] internal method (if ++ // not we raise an exception). ++ // Overwrite the original receiver with the (original) target. ++ __ CalcScaledAddress(kScratchReg, sp, a0, kPointerSizeLog2); ++ __ Sd(a1, MemOperand(kScratchReg)); ++ // Let the "call_as_function_delegate" take care of the rest. ++ __ LoadNativeContextSlot(Context::CALL_AS_FUNCTION_DELEGATE_INDEX, a1); ++ __ Jump(masm->isolate()->builtins()->CallFunction( ++ ConvertReceiverMode::kNotNullOrUndefined), ++ RelocInfo::CODE_TARGET); ++ ++ // 3. Call to something that is not callable. ++ __ bind(&non_callable); ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ Push(a1); ++ __ CallRuntime(Runtime::kThrowCalledNonCallable); ++ } ++} ++ ++void Builtins::Generate_ConstructFunction(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the constructor to call (checked to be a JSFunction) ++ // -- a3 : the new target (checked to be a constructor) ++ // ----------------------------------- ++ __ AssertConstructor(a1); ++ __ AssertFunction(a1); ++ ++ // Calling convention for function specific ConstructStubs require ++ // a2 to contain either an AllocationSite or undefined. ++ __ LoadRoot(a2, RootIndex::kUndefinedValue); ++ ++ Label call_generic_stub; ++ ++ // Jump to JSBuiltinsConstructStub or JSConstructStubGeneric. ++ __ Ld(a4, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lwu(a4, FieldMemOperand(a4, SharedFunctionInfo::kFlagsOffset)); ++ __ And(a4, a4, Operand(SharedFunctionInfo::ConstructAsBuiltinBit::kMask)); ++ __ Branch(&call_generic_stub, eq, a4, Operand(zero_reg)); ++ ++ __ Jump(BUILTIN_CODE(masm->isolate(), JSBuiltinsConstructStub), ++ RelocInfo::CODE_TARGET); ++ ++ __ bind(&call_generic_stub); ++ __ Jump(BUILTIN_CODE(masm->isolate(), JSConstructStubGeneric), ++ RelocInfo::CODE_TARGET); ++} ++ ++// static ++void Builtins::Generate_ConstructBoundFunction(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSBoundFunction) ++ // -- a3 : the new target (checked to be a constructor) ++ // ----------------------------------- ++ __ AssertConstructor(a1); ++ __ AssertBoundFunction(a1); ++ ++ // Load [[BoundArguments]] into a2 and length of that into a4. ++ __ Ld(a2, FieldMemOperand(a1, JSBoundFunction::kBoundArgumentsOffset)); ++ __ SmiUntag(a4, FieldMemOperand(a2, FixedArray::kLengthOffset)); ++ ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the function to call (checked to be a JSBoundFunction) ++ // -- a2 : the [[BoundArguments]] (implemented as FixedArray) ++ // -- a3 : the new target (checked to be a constructor) ++ // -- a4 : the number of [[BoundArguments]] ++ // ----------------------------------- ++ ++ // Reserve stack space for the [[BoundArguments]]. ++ { ++ Label done; ++ __ Sll64(a5, a4, kPointerSizeLog2); ++ __ Sub64(sp, sp, Operand(a5)); ++ // Check the stack for overflow. We are not trying to catch interruptions ++ // (i.e. debug break and preemption) here, so check the "real stack limit". ++ LoadStackLimit(masm, kScratchReg, StackLimitKind::kRealStackLimit); ++ __ Branch(&done, Ugreater_equal, sp, Operand(kScratchReg)); ++ // Restore the stack pointer. ++ __ Add64(sp, sp, Operand(a5)); ++ { ++ FrameScope scope(masm, StackFrame::MANUAL); ++ __ EnterFrame(StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ } ++ __ bind(&done); ++ } ++ ++ // Relocate arguments down the stack. ++ { ++ Label loop, done_loop; ++ __ Move(a5, zero_reg); ++ __ bind(&loop); ++ __ Branch(&done_loop, ge, a5, Operand(a0)); ++ __ CalcScaledAddress(a6, sp, a4, kPointerSizeLog2); ++ __ Ld(kScratchReg, MemOperand(a6)); ++ __ CalcScaledAddress(a6, sp, a5, kPointerSizeLog2); ++ __ Sd(kScratchReg, MemOperand(a6)); ++ __ Add64(a4, a4, Operand(1)); ++ __ Add64(a5, a5, Operand(1)); ++ __ Branch(&loop); ++ __ bind(&done_loop); ++ } ++ ++ // Copy [[BoundArguments]] to the stack (below the arguments). ++ { ++ Label loop, done_loop; ++ __ SmiUntag(a4, FieldMemOperand(a2, FixedArray::kLengthOffset)); ++ __ Add64(a2, a2, Operand(FixedArray::kHeaderSize - kHeapObjectTag)); ++ __ bind(&loop); ++ __ Sub64(a4, a4, Operand(1)); ++ __ Branch(&done_loop, lt, a4, Operand(zero_reg)); ++ __ CalcScaledAddress(a5, a2, a4, kPointerSizeLog2); ++ __ Ld(kScratchReg, MemOperand(a5)); ++ __ CalcScaledAddress(a5, sp, a0, kPointerSizeLog2); ++ __ Sd(kScratchReg, MemOperand(a5)); ++ __ Add64(a0, a0, Operand(1)); ++ __ Branch(&loop); ++ __ bind(&done_loop); ++ } ++ ++ // Patch new.target to [[BoundTargetFunction]] if new.target equals target. ++ { ++ Label skip_load; ++ __ Branch(&skip_load, ne, a1, Operand(a3)); ++ __ Ld(a3, FieldMemOperand(a1, JSBoundFunction::kBoundTargetFunctionOffset)); ++ __ bind(&skip_load); ++ } ++ ++ // Construct the [[BoundTargetFunction]] via the Construct builtin. ++ __ Ld(a1, FieldMemOperand(a1, JSBoundFunction::kBoundTargetFunctionOffset)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), Construct), RelocInfo::CODE_TARGET); ++} ++ ++// static ++void Builtins::Generate_Construct(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- a0 : the number of arguments (not including the receiver) ++ // -- a1 : the constructor to call (can be any Object) ++ // -- a3 : the new target (either the same as the constructor or ++ // the JSFunction on which new was invoked initially) ++ // ----------------------------------- ++ ++ // Check if target is a Smi. ++ Label non_constructor, non_proxy; ++ __ JumpIfSmi(a1, &non_constructor); ++ ++ // Check if target has a [[Construct]] internal method. ++ __ Ld(t1, FieldMemOperand(a1, HeapObject::kMapOffset)); ++ __ Lbu(t4, FieldMemOperand(t1, Map::kBitFieldOffset)); ++ __ And(t4, t4, Operand(Map::Bits1::IsConstructorBit::kMask)); ++ __ Branch(&non_constructor, eq, t4, Operand(zero_reg)); ++ ++ // Dispatch based on instance type. ++ __ Lhu(t2, FieldMemOperand(t1, Map::kInstanceTypeOffset)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructFunction), ++ RelocInfo::CODE_TARGET, eq, t2, Operand(JS_FUNCTION_TYPE)); ++ ++ // Only dispatch to bound functions after checking whether they are ++ // constructors. ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructBoundFunction), ++ RelocInfo::CODE_TARGET, eq, t2, Operand(JS_BOUND_FUNCTION_TYPE)); ++ ++ // Only dispatch to proxies after checking whether they are constructors. ++ __ Branch(&non_proxy, ne, t2, Operand(JS_PROXY_TYPE)); ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructProxy), ++ RelocInfo::CODE_TARGET); ++ ++ // Called Construct on an exotic Object with a [[Construct]] internal method. ++ __ bind(&non_proxy); ++ { ++ // Overwrite the original receiver with the (original) target. ++ __ CalcScaledAddress(kScratchReg, sp, a0, kPointerSizeLog2); ++ __ Sd(a1, MemOperand(kScratchReg)); ++ // Let the "call_as_constructor_delegate" take care of the rest. ++ __ LoadNativeContextSlot(Context::CALL_AS_CONSTRUCTOR_DELEGATE_INDEX, a1); ++ __ Jump(masm->isolate()->builtins()->CallFunction(), ++ RelocInfo::CODE_TARGET); ++ } ++ ++ // Called Construct on an Object that doesn't have a [[Construct]] internal ++ // method. ++ __ bind(&non_constructor); ++ __ Jump(BUILTIN_CODE(masm->isolate(), ConstructedNonConstructable), ++ RelocInfo::CODE_TARGET); ++} ++ ++void Builtins::Generate_ArgumentsAdaptorTrampoline(MacroAssembler* masm) { ++ // State setup as expected by MacroAssembler::InvokePrologue. ++ // ----------- S t a t e ------------- ++ // -- a0: actual arguments count ++ // -- a1: function (passed through to callee) ++ // -- a2: expected arguments count ++ // -- a3: new target (passed through to callee) ++ // ----------------------------------- ++ ++ Label invoke, dont_adapt_arguments, stack_overflow; ++ ++ Label enough, too_few; ++ __ Branch(&dont_adapt_arguments, eq, a2, ++ Operand(kDontAdaptArgumentsSentinel)); ++ // We use Uless as the number of argument should always be greater than 0. ++ __ Branch(&too_few, Uless, a0, Operand(a2)); ++ ++ { // Enough parameters: actual >= expected. ++ // a0: actual number of arguments as a smi ++ // a1: function ++ // a2: expected number of arguments ++ // a3: new target (passed through to callee) ++ __ bind(&enough); ++ EnterArgumentsAdaptorFrame(masm); ++ Generate_StackOverflowCheck(masm, a2, a5, kScratchReg, &stack_overflow); ++ ++ // Calculate copy start address into a0 and copy end address into a4. ++ __ SmiScale(a0, a0, kPointerSizeLog2); ++ __ Add64(a0, fp, a0); ++ // Adjust for return address and receiver. ++ __ Add64(a0, a0, Operand(2 * kPointerSize)); ++ // Compute copy end address. ++ __ Sll64(a4, a2, kPointerSizeLog2); ++ __ Sub64(a4, a0, a4); ++ ++ // Copy the arguments (including the receiver) to the new stack frame. ++ // a0: copy start address ++ // a1: function ++ // a2: expected number of arguments ++ // a3: new target (passed through to callee) ++ // a4: copy end address ++ ++ Label copy; ++ __ bind(©); ++ __ Ld(a5, MemOperand(a0)); ++ __ push(a5); ++ __ Add64(a0, a0, -kPointerSize); ++ __ Branch(©, ge, a0, Operand(a4)); ++ ++ __ Branch(&invoke); ++ } ++ ++ { // Too few parameters: Actual < expected. ++ __ bind(&too_few); ++ EnterArgumentsAdaptorFrame(masm); ++ Generate_StackOverflowCheck(masm, a2, a5, kScratchReg, &stack_overflow); ++ ++ // Calculate copy start address into a0 and copy end address into a7. ++ // a0: actual number of arguments as a smi ++ // a1: function ++ // a2: expected number of arguments ++ // a3: new target (passed through to callee) ++ __ SmiScale(a0, a0, kPointerSizeLog2); ++ __ Add64(a0, fp, a0); ++ // Adjust for return address and receiver. ++ __ Add64(a0, a0, Operand(2 * kPointerSize)); ++ // Compute copy end address. Also adjust for return address. ++ __ Add64(a7, fp, kPointerSize); ++ ++ // Copy the arguments (including the receiver) to the new stack frame. ++ // a0: copy start address ++ // a1: function ++ // a2: expected number of arguments ++ // a3: new target (passed through to callee) ++ // a7: copy end address ++ Label copy; ++ __ bind(©); ++ __ Ld(a4, MemOperand(a0)); // Adjusted above for return addr and receiver. ++ __ Sub64(sp, sp, kPointerSize); ++ __ Sub64(a0, a0, kPointerSize); ++ __ Sd(a4, MemOperand(sp)); ++ __ Branch(©, ne, a0, Operand(a7)); ++ ++ // Fill the remaining expected arguments with undefined. ++ // a1: function ++ // a2: expected number of arguments ++ // a3: new target (passed through to callee) ++ __ LoadRoot(a5, RootIndex::kUndefinedValue); ++ __ Sll64(a6, a2, kPointerSizeLog2); ++ __ Sub64(a4, fp, Operand(a6)); ++ // Adjust for frame. ++ __ Sub64(a4, a4, ++ Operand(ArgumentsAdaptorFrameConstants::kFixedFrameSizeFromFp + ++ kPointerSize)); ++ ++ Label fill; ++ __ bind(&fill); ++ __ Sub64(sp, sp, kPointerSize); ++ __ Sd(a5, MemOperand(sp)); ++ __ Branch(&fill, ne, sp, Operand(a4)); ++ } ++ ++ // Call the entry point. ++ __ bind(&invoke); ++ __ Move(a0, a2); ++ // a0 : expected number of arguments ++ // a1 : function (passed through to callee) ++ // a3: new target (passed through to callee) ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Ld(a2, FieldMemOperand(a1, JSFunction::kCodeOffset)); ++ __ Add64(a2, a2, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Call(a2); ++ ++ // Store offset of return address for deoptimizer. ++ masm->isolate()->heap()->SetArgumentsAdaptorDeoptPCOffset(masm->pc_offset()); ++ ++ // Exit frame and return. ++ LeaveArgumentsAdaptorFrame(masm); ++ __ Ret(); ++ ++ // ------------------------------------------- ++ // Don't adapt arguments. ++ // ------------------------------------------- ++ __ bind(&dont_adapt_arguments); ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Ld(a2, FieldMemOperand(a1, JSFunction::kCodeOffset)); ++ __ Add64(a2, a2, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Jump(a2); ++ ++ __ bind(&stack_overflow); ++ { ++ FrameScope frame(masm, StackFrame::MANUAL); ++ __ CallRuntime(Runtime::kThrowStackOverflow); ++ __ break_(0xCC); ++ } ++} ++ ++void Builtins::Generate_WasmCompileLazy(MacroAssembler* masm) { ++ // The function index was put in t0 by the jump table trampoline. ++ // Convert to Smi for the runtime call ++ __ SmiTag(kWasmCompileLazyFuncIndexRegister); ++ { ++ HardAbortScope hard_abort(masm); // Avoid calls to Abort. ++ FrameScope scope(masm, StackFrame::WASM_COMPILE_LAZY); ++ ++ // Save all parameter registers (see kGpParamRegisters in wasm-linkage.cc). ++ // They might be overwritten in the runtime call below. We don't have any ++ // callee-saved registers in wasm, so no need to store anything else. ++ constexpr RegList gp_regs = Register::ListOf(a0, a2, a3, a4, a5, a6, a7); ++ constexpr RegList fp_regs = ++ DoubleRegister::ListOf(fa0, fa1, fa2, fa3, fa4, fa5, fa6); ++ static_assert(WasmCompileLazyFrameConstants::kNumberOfSavedGpParamRegs == ++ arraysize(wasm::kGpParamRegisters), ++ "frame size mismatch"); ++ static_assert(WasmCompileLazyFrameConstants::kNumberOfSavedFpParamRegs == ++ arraysize(wasm::kFpParamRegisters), ++ "frame size mismatch"); ++ __ MultiPush(gp_regs); ++ __ MultiPushFPU(fp_regs); ++ ++ // Pass instance and function index as an explicit arguments to the runtime ++ // function. ++ __ Push(kWasmInstanceRegister, kWasmCompileLazyFuncIndexRegister); ++ // Initialize the JavaScript context with 0. CEntry will use it to ++ // set the current context on the isolate. ++ __ Move(kContextRegister, Smi::zero()); ++ __ CallRuntime(Runtime::kWasmCompileLazy, 2); ++ ++ __ Move(s1, a0); // move return value to s1 since a0 will be restored to ++ // the value before the call ++ ++ // Restore registers. ++ __ MultiPopFPU(fp_regs); ++ __ MultiPop(gp_regs); ++ } ++ // Finally, jump to the entrypoint. ++ __ Jump(s1); ++} ++ ++void Builtins::Generate_WasmDebugBreak(MacroAssembler* masm) { ++ HardAbortScope hard_abort(masm); // Avoid calls to Abort. ++ { ++ FrameScope scope(masm, StackFrame::WASM_DEBUG_BREAK); ++ ++ // Save all parameter registers. They might hold live values, we restore ++ // them after the runtime call. ++ __ MultiPush(WasmDebugBreakFrameConstants::kPushedGpRegs); ++ __ MultiPushFPU(WasmDebugBreakFrameConstants::kPushedFpRegs); ++ ++ // Initialize the JavaScript context with 0. CEntry will use it to ++ // set the current context on the isolate. ++ __ Move(cp, Smi::zero()); ++ __ CallRuntime(Runtime::kWasmDebugBreak, 0); ++ ++ // Restore registers. ++ __ MultiPopFPU(WasmDebugBreakFrameConstants::kPushedFpRegs); ++ __ MultiPop(WasmDebugBreakFrameConstants::kPushedGpRegs); ++ } ++ __ Ret(); ++} ++ ++void Builtins::Generate_CEntry(MacroAssembler* masm, int result_size, ++ SaveFPRegsMode save_doubles, ArgvMode argv_mode, ++ bool builtin_exit_frame) { ++ // Called from JavaScript; parameters are on stack as if calling JS function ++ // a0: number of arguments including receiver ++ // a1: pointer to builtin function ++ // fp: frame pointer (restored after C call) ++ // sp: stack pointer (restored as callee's sp after C call) ++ // cp: current context (C callee-saved) ++ // ++ // If argv_mode == kArgvInRegister: ++ // a2: pointer to the first argument ++ ++ if (argv_mode == kArgvInRegister) { ++ // Move argv into the correct register. ++ __ Move(s1, a2); ++ } else { ++ // Compute the argv pointer in a callee-saved register. ++ __ CalcScaledAddress(s1, sp, a0, kPointerSizeLog2); ++ __ Sub64(s1, s1, kPointerSize); ++ } ++ ++ // Enter the exit frame that transitions from JavaScript to C++. ++ FrameScope scope(masm, StackFrame::MANUAL); ++ __ EnterExitFrame( ++ save_doubles == kSaveFPRegs, 0, ++ builtin_exit_frame ? StackFrame::BUILTIN_EXIT : StackFrame::EXIT); ++ ++ // s3: number of arguments including receiver (C callee-saved) ++ // s1: pointer to first argument (C callee-saved) ++ // s2: pointer to builtin function (C callee-saved) ++ ++ // Prepare arguments for C routine. ++ // a0 = argc ++ __ Move(s3, a0); ++ __ Move(s2, a1); ++ ++ // We are calling compiled C/C++ code. a0 and a1 hold our two arguments. We ++ // also need to reserve the 4 argument slots on the stack. ++ ++ __ AssertStackIsAligned(); ++ ++ // a0 = argc, a1 = argv, a2 = isolate ++ __ li(a2, ExternalReference::isolate_address(masm->isolate())); ++ __ Move(a1, s1); ++ ++ __ StoreReturnAddressAndCall(s2); ++ ++ // Result returned in a0 or a1:a0 - do not destroy these registers! ++ ++ // Check result for exception sentinel. ++ Label exception_returned; ++ __ LoadRoot(a4, RootIndex::kException); ++ __ Branch(&exception_returned, eq, a4, Operand(a0)); ++ ++ // Check that there is no pending exception, otherwise we ++ // should have returned the exception sentinel. ++ if (FLAG_debug_code) { ++ Label okay; ++ ExternalReference pending_exception_address = ExternalReference::Create( ++ IsolateAddressId::kPendingExceptionAddress, masm->isolate()); ++ __ li(a2, pending_exception_address); ++ __ Ld(a2, MemOperand(a2)); ++ __ LoadRoot(a4, RootIndex::kTheHoleValue); ++ // Cannot use check here as it attempts to generate call into runtime. ++ __ Branch(&okay, eq, a4, Operand(a2)); ++ __ stop(); ++ __ bind(&okay); ++ } ++ ++ // Exit C frame and return. ++ // a0:a1: result ++ // sp: stack pointer ++ // fp: frame pointer ++ Register argc = argv_mode == kArgvInRegister ++ // We don't want to pop arguments so set argc to no_reg. ++ ? no_reg ++ // s3: still holds argc (callee-saved). ++ : s3; ++ __ LeaveExitFrame(save_doubles == kSaveFPRegs, argc, EMIT_RETURN); ++ ++ // Handling of exception. ++ __ bind(&exception_returned); ++ ++ ExternalReference pending_handler_context_address = ExternalReference::Create( ++ IsolateAddressId::kPendingHandlerContextAddress, masm->isolate()); ++ ExternalReference pending_handler_entrypoint_address = ++ ExternalReference::Create( ++ IsolateAddressId::kPendingHandlerEntrypointAddress, masm->isolate()); ++ ExternalReference pending_handler_fp_address = ExternalReference::Create( ++ IsolateAddressId::kPendingHandlerFPAddress, masm->isolate()); ++ ExternalReference pending_handler_sp_address = ExternalReference::Create( ++ IsolateAddressId::kPendingHandlerSPAddress, masm->isolate()); ++ ++ // Ask the runtime for help to determine the handler. This will set a0 to ++ // contain the current pending exception, don't clobber it. ++ ExternalReference find_handler = ++ ExternalReference::Create(Runtime::kUnwindAndFindExceptionHandler); ++ { ++ FrameScope scope(masm, StackFrame::MANUAL); ++ __ PrepareCallCFunction(3, 0, a0); ++ __ Move(a0, zero_reg); ++ __ Move(a1, zero_reg); ++ __ li(a2, ExternalReference::isolate_address(masm->isolate())); ++ __ CallCFunction(find_handler, 3); ++ } ++ ++ // Retrieve the handler context, SP and FP. ++ __ li(cp, pending_handler_context_address); ++ __ Ld(cp, MemOperand(cp)); ++ __ li(sp, pending_handler_sp_address); ++ __ Ld(sp, MemOperand(sp)); ++ __ li(fp, pending_handler_fp_address); ++ __ Ld(fp, MemOperand(fp)); ++ ++ // If the handler is a JS frame, restore the context to the frame. Note that ++ // the context will be set to (cp == 0) for non-JS frames. ++ Label zero; ++ __ Branch(&zero, eq, cp, Operand(zero_reg)); ++ __ Sd(cp, MemOperand(fp, StandardFrameConstants::kContextOffset)); ++ __ bind(&zero); ++ ++ // Reset the masking register. This is done independent of the underlying ++ // feature flag {FLAG_untrusted_code_mitigations} to make the snapshot work ++ // with both configurations. It is safe to always do this, because the ++ // underlying register is caller-saved and can be arbitrarily clobbered. ++ __ ResetSpeculationPoisonRegister(); ++ ++ // Compute the handler entry address and jump to it. ++ __ li(t6, pending_handler_entrypoint_address); ++ __ Ld(t6, MemOperand(t6)); ++ __ Jump(t6); ++} ++ ++void Builtins::Generate_DoubleToI(MacroAssembler* masm) { ++ Label done; ++ Register result_reg = t0; ++ ++ Register scratch = GetRegisterThatIsNotOneOf(result_reg); ++ Register scratch2 = GetRegisterThatIsNotOneOf(result_reg, scratch); ++ Register scratch3 = GetRegisterThatIsNotOneOf(result_reg, scratch, scratch2); ++ DoubleRegister double_scratch = kScratchDoubleReg; ++ ++ // Account for saved regs. ++ const int kArgumentOffset = 4 * kPointerSize; ++ ++ __ Push(result_reg); ++ __ Push(scratch, scratch2, scratch3); ++ ++ // Load double input. ++ __ LoadDouble(double_scratch, MemOperand(sp, kArgumentOffset)); ++ ++ // Try a conversion to a signed integer, if exception occurs, scratch is ++ // set to 0 ++ __ Trunc_w_d(scratch3, double_scratch, scratch); ++ ++ // If we had no exceptions then set result_reg and we are done. ++ Label error; ++ __ Branch(&error, eq, scratch, Operand(zero_reg)); ++ __ Move(result_reg, scratch3); ++ __ Branch(&done); ++ __ bind(&error); ++ ++ // Load the double value and perform a manual truncation. ++ Register input_high = scratch2; ++ Register input_low = scratch3; ++ ++ __ Lw(input_low, MemOperand(sp, kArgumentOffset + Register::kMantissaOffset)); ++ __ Lw(input_high, ++ MemOperand(sp, kArgumentOffset + Register::kExponentOffset)); ++ ++ Label normal_exponent; ++ // Extract the biased exponent in result. ++ __ ExtractBits(result_reg, input_high, HeapNumber::kExponentShift, ++ HeapNumber::kExponentBits); ++ ++ // Check for Infinity and NaNs, which should return 0. ++ __ Sub32(scratch, result_reg, HeapNumber::kExponentMask); ++ __ LoadZeroIfConditionZero( ++ result_reg, ++ scratch); // result_reg = scratch == 0 ? 0 : result_reg ++ __ Branch(&done, eq, scratch, Operand(zero_reg)); ++ ++ // Express exponent as delta to (number of mantissa bits + 31). ++ __ Sub32(result_reg, result_reg, ++ Operand(HeapNumber::kExponentBias + HeapNumber::kMantissaBits + 31)); ++ ++ // If the delta is strictly positive, all bits would be shifted away, ++ // which means that we can return 0. ++ __ Branch(&normal_exponent, le, result_reg, Operand(zero_reg)); ++ __ Move(result_reg, zero_reg); ++ __ Branch(&done); ++ ++ __ bind(&normal_exponent); ++ const int kShiftBase = HeapNumber::kNonMantissaBitsInTopWord - 1; ++ // Calculate shift. ++ __ Add32(scratch, result_reg, ++ Operand(kShiftBase + HeapNumber::kMantissaBits)); ++ ++ // Save the sign. ++ Register sign = result_reg; ++ result_reg = no_reg; ++ __ And(sign, input_high, Operand(HeapNumber::kSignMask)); ++ ++ // We must specially handle shifts greater than 31. ++ Label high_shift_needed, high_shift_done; ++ __ Branch(&high_shift_needed, lt, scratch, Operand(32)); ++ __ Move(input_high, zero_reg); ++ __ Branch(&high_shift_done); ++ __ bind(&high_shift_needed); ++ ++ // Set the implicit 1 before the mantissa part in input_high. ++ __ Or(input_high, input_high, ++ Operand(1 << HeapNumber::kMantissaBitsInTopWord)); ++ // Shift the mantissa bits to the correct position. ++ // We don't need to clear non-mantissa bits as they will be shifted away. ++ // If they weren't, it would mean that the answer is in the 32bit range. ++ __ Sll32(input_high, input_high, scratch); ++ ++ __ bind(&high_shift_done); ++ ++ // Replace the shifted bits with bits from the lower mantissa word. ++ Label pos_shift, shift_done, sign_negative; ++ __ li(kScratchReg, 32); ++ __ subw(scratch, kScratchReg, scratch); ++ __ Branch(&pos_shift, ge, scratch, Operand(zero_reg)); ++ ++ // Negate scratch. ++ __ Sub32(scratch, zero_reg, scratch); ++ __ Sll32(input_low, input_low, scratch); ++ __ Branch(&shift_done); ++ ++ __ bind(&pos_shift); ++ __ srlw(input_low, input_low, scratch); ++ ++ __ bind(&shift_done); ++ __ Or(input_high, input_high, Operand(input_low)); ++ // Restore sign if necessary. ++ __ Move(scratch, sign); ++ result_reg = sign; ++ sign = no_reg; ++ __ Sub32(result_reg, zero_reg, input_high); ++ __ Branch(&sign_negative, ne, scratch, Operand(zero_reg)); ++ __ Move(result_reg, input_high); ++ __ bind(&sign_negative); ++ ++ __ bind(&done); ++ ++ __ Sd(result_reg, MemOperand(sp, kArgumentOffset)); ++ __ Pop(scratch, scratch2, scratch3); ++ __ Pop(result_reg); ++ __ Ret(); ++} ++ ++void Builtins::Generate_GenericJSToWasmWrapper(MacroAssembler* masm) { ++ // TODO(v8:10701): Implement for this platform. ++ __ Trap(); ++} ++ ++namespace { ++ ++int AddressOffset(ExternalReference ref0, ExternalReference ref1) { ++ int64_t offset = (ref0.address() - ref1.address()); ++ DCHECK(static_cast(offset) == offset); ++ return static_cast(offset); ++} ++ ++// Calls an API function. Allocates HandleScope, extracts returned value ++// from handle and propagates exceptions. Restores context. stack_space ++// - space to be unwound on exit (includes the call JS arguments space and ++// the additional space allocated for the fast call). ++void CallApiFunctionAndReturn(MacroAssembler* masm, Register function_address, ++ ExternalReference thunk_ref, int stack_space, ++ MemOperand* stack_space_operand, ++ MemOperand return_value_operand) { ++ Isolate* isolate = masm->isolate(); ++ ExternalReference next_address = ++ ExternalReference::handle_scope_next_address(isolate); ++ const int kNextOffset = 0; ++ const int kLimitOffset = AddressOffset( ++ ExternalReference::handle_scope_limit_address(isolate), next_address); ++ const int kLevelOffset = AddressOffset( ++ ExternalReference::handle_scope_level_address(isolate), next_address); ++ ++ DCHECK(function_address == a1 || function_address == a2); ++ ++ Label profiler_enabled, end_profiler_check; ++ __ li(t6, ExternalReference::is_profiling_address(isolate)); ++ __ Lb(t6, MemOperand(t6, 0)); ++ __ Branch(&profiler_enabled, ne, t6, Operand(zero_reg)); ++ __ li(t6, ExternalReference::address_of_runtime_stats_flag()); ++ __ Lw(t6, MemOperand(t6, 0)); ++ __ Branch(&profiler_enabled, ne, t6, Operand(zero_reg)); ++ { ++ // Call the api function directly. ++ __ Move(t6, function_address); ++ __ Branch(&end_profiler_check); ++ } ++ ++ __ bind(&profiler_enabled); ++ { ++ // Additional parameter is the address of the actual callback. ++ __ li(t6, thunk_ref); ++ } ++ __ bind(&end_profiler_check); ++ ++ // Allocate HandleScope in callee-save registers. ++ __ li(s5, next_address); ++ __ Ld(s3, MemOperand(s5, kNextOffset)); ++ __ Ld(s1, MemOperand(s5, kLimitOffset)); ++ __ Lw(s2, MemOperand(s5, kLevelOffset)); ++ __ Add32(s2, s2, Operand(1)); ++ __ Sw(s2, MemOperand(s5, kLevelOffset)); ++ ++ __ StoreReturnAddressAndCall(t6); ++ ++ Label promote_scheduled_exception; ++ Label delete_allocated_handles; ++ Label leave_exit_frame; ++ Label return_value_loaded; ++ ++ // Load value from ReturnValue. ++ __ Ld(a0, return_value_operand); ++ __ bind(&return_value_loaded); ++ ++ // No more valid handles (the result handle was the last one). Restore ++ // previous handle scope. ++ __ Sd(s3, MemOperand(s5, kNextOffset)); ++ if (__ emit_debug_code()) { ++ __ Lw(a1, MemOperand(s5, kLevelOffset)); ++ __ Check(eq, AbortReason::kUnexpectedLevelAfterReturnFromApiCall, a1, ++ Operand(s2)); ++ } ++ __ Sub32(s2, s2, Operand(1)); ++ __ Sw(s2, MemOperand(s5, kLevelOffset)); ++ __ Ld(kScratchReg, MemOperand(s5, kLimitOffset)); ++ __ Branch(&delete_allocated_handles, ne, s1, Operand(kScratchReg)); ++ ++ // Leave the API exit frame. ++ __ bind(&leave_exit_frame); ++ ++ if (stack_space_operand == nullptr) { ++ DCHECK_NE(stack_space, 0); ++ __ li(s3, Operand(stack_space)); ++ } else { ++ DCHECK_EQ(stack_space, 0); ++ STATIC_ASSERT(kCArgSlotCount == 0); ++ __ Ld(s3, *stack_space_operand); ++ } ++ ++ static constexpr bool kDontSaveDoubles = false; ++ static constexpr bool kRegisterContainsSlotCount = false; ++ __ LeaveExitFrame(kDontSaveDoubles, s3, NO_EMIT_RETURN, ++ kRegisterContainsSlotCount); ++ ++ // Check if the function scheduled an exception. ++ __ LoadRoot(a4, RootIndex::kTheHoleValue); ++ __ li(kScratchReg, ExternalReference::scheduled_exception_address(isolate)); ++ __ Ld(a5, MemOperand(kScratchReg)); ++ __ Branch(&promote_scheduled_exception, ne, a4, Operand(a5)); ++ ++ __ Ret(); ++ ++ // Re-throw by promoting a scheduled exception. ++ __ bind(&promote_scheduled_exception); ++ __ TailCallRuntime(Runtime::kPromoteScheduledException); ++ ++ // HandleScope limit has changed. Delete allocated extensions. ++ __ bind(&delete_allocated_handles); ++ __ Sd(s1, MemOperand(s5, kLimitOffset)); ++ __ Move(s3, a0); ++ __ PrepareCallCFunction(1, s1); ++ __ li(a0, ExternalReference::isolate_address(isolate)); ++ __ CallCFunction(ExternalReference::delete_handle_scope_extensions(), 1); ++ __ Move(a0, s3); ++ __ Branch(&leave_exit_frame); ++} ++ ++} // namespace ++ ++void Builtins::Generate_CallApiCallback(MacroAssembler* masm) { ++ // ----------- S t a t e ------------- ++ // -- cp : context ++ // -- a1 : api function address ++ // -- a2 : arguments count (not including the receiver) ++ // -- a3 : call data ++ // -- a0 : holder ++ // -- ++ // -- sp[0] : last argument ++ // -- ... ++ // -- sp[(argc - 1) * 8] : first argument ++ // -- sp[(argc + 0) * 8] : receiver ++ // ----------------------------------- ++ ++ Register api_function_address = a1; ++ Register argc = a2; ++ Register call_data = a3; ++ Register holder = a0; ++ Register scratch = t0; ++ Register base = t1; // For addressing MemOperands on the stack. ++ ++ DCHECK(!AreAliased(api_function_address, argc, call_data, holder, scratch, ++ base)); ++ ++ using FCA = FunctionCallbackArguments; ++ ++ STATIC_ASSERT(FCA::kArgsLength == 6); ++ STATIC_ASSERT(FCA::kNewTargetIndex == 5); ++ STATIC_ASSERT(FCA::kDataIndex == 4); ++ STATIC_ASSERT(FCA::kReturnValueOffset == 3); ++ STATIC_ASSERT(FCA::kReturnValueDefaultValueIndex == 2); ++ STATIC_ASSERT(FCA::kIsolateIndex == 1); ++ STATIC_ASSERT(FCA::kHolderIndex == 0); ++ ++ // Set up FunctionCallbackInfo's implicit_args on the stack as follows: ++ // ++ // Target state: ++ // sp[0 * kPointerSize]: kHolder ++ // sp[1 * kPointerSize]: kIsolate ++ // sp[2 * kPointerSize]: undefined (kReturnValueDefaultValue) ++ // sp[3 * kPointerSize]: undefined (kReturnValue) ++ // sp[4 * kPointerSize]: kData ++ // sp[5 * kPointerSize]: undefined (kNewTarget) ++ ++ // Set up the base register for addressing through MemOperands. It will point ++ // at the receiver (located at sp + argc * kPointerSize). ++ __ CalcScaledAddress(base, sp, argc, kPointerSizeLog2); ++ ++ // Reserve space on the stack. ++ __ Sub64(sp, sp, Operand(FCA::kArgsLength * kPointerSize)); ++ ++ // kHolder. ++ __ Sd(holder, MemOperand(sp, 0 * kPointerSize)); ++ ++ // kIsolate. ++ __ li(scratch, ExternalReference::isolate_address(masm->isolate())); ++ __ Sd(scratch, MemOperand(sp, 1 * kPointerSize)); ++ ++ // kReturnValueDefaultValue and kReturnValue. ++ __ LoadRoot(scratch, RootIndex::kUndefinedValue); ++ __ Sd(scratch, MemOperand(sp, 2 * kPointerSize)); ++ __ Sd(scratch, MemOperand(sp, 3 * kPointerSize)); ++ ++ // kData. ++ __ Sd(call_data, MemOperand(sp, 4 * kPointerSize)); ++ ++ // kNewTarget. ++ __ Sd(scratch, MemOperand(sp, 5 * kPointerSize)); ++ ++ // Keep a pointer to kHolder (= implicit_args) in a scratch register. ++ // We use it below to set up the FunctionCallbackInfo object. ++ __ Move(scratch, sp); ++ ++ // Allocate the v8::Arguments structure in the arguments' space since ++ // it's not controlled by GC. ++ static constexpr int kApiStackSpace = 4; ++ static constexpr bool kDontSaveDoubles = false; ++ FrameScope frame_scope(masm, StackFrame::MANUAL); ++ __ EnterExitFrame(kDontSaveDoubles, kApiStackSpace); ++ ++ // EnterExitFrame may align the sp. ++ ++ // FunctionCallbackInfo::implicit_args_ (points at kHolder as set up above). ++ // Arguments are after the return address (pushed by EnterExitFrame()). ++ __ Sd(scratch, MemOperand(sp, 1 * kPointerSize)); ++ ++ // FunctionCallbackInfo::values_ (points at the first varargs argument passed ++ // on the stack). ++ __ Sub64(scratch, base, Operand(1 * kPointerSize)); ++ __ Sd(scratch, MemOperand(sp, 2 * kPointerSize)); ++ ++ // FunctionCallbackInfo::length_. ++ // Stored as int field, 32-bit integers within struct on stack always left ++ // justified by n64 ABI. ++ __ Sw(argc, MemOperand(sp, 3 * kPointerSize)); ++ ++ // We also store the number of bytes to drop from the stack after returning ++ // from the API function here. ++ // Note: Unlike on other architectures, this stores the number of slots to ++ // drop, not the number of bytes. ++ __ Add64(scratch, argc, Operand(FCA::kArgsLength + 1 /* receiver */)); ++ __ Sd(scratch, MemOperand(sp, 4 * kPointerSize)); ++ ++ // v8::InvocationCallback's argument. ++ DCHECK(!AreAliased(api_function_address, scratch, a0)); ++ __ Add64(a0, sp, Operand(1 * kPointerSize)); ++ ++ ExternalReference thunk_ref = ExternalReference::invoke_function_callback(); ++ ++ // There are two stack slots above the arguments we constructed on the stack. ++ // TODO(jgruber): Document what these arguments are. ++ static constexpr int kStackSlotsAboveFCA = 2; ++ MemOperand return_value_operand( ++ fp, (kStackSlotsAboveFCA + FCA::kReturnValueOffset) * kPointerSize); ++ ++ static constexpr int kUseStackSpaceOperand = 0; ++ MemOperand stack_space_operand(sp, 4 * kPointerSize); ++ ++ AllowExternalCallThatCantCauseGC scope(masm); ++ CallApiFunctionAndReturn(masm, api_function_address, thunk_ref, ++ kUseStackSpaceOperand, &stack_space_operand, ++ return_value_operand); ++} ++ ++void Builtins::Generate_CallApiGetter(MacroAssembler* masm) { ++ // Build v8::PropertyCallbackInfo::args_ array on the stack and push property ++ // name below the exit frame to make GC aware of them. ++ STATIC_ASSERT(PropertyCallbackArguments::kShouldThrowOnErrorIndex == 0); ++ STATIC_ASSERT(PropertyCallbackArguments::kHolderIndex == 1); ++ STATIC_ASSERT(PropertyCallbackArguments::kIsolateIndex == 2); ++ STATIC_ASSERT(PropertyCallbackArguments::kReturnValueDefaultValueIndex == 3); ++ STATIC_ASSERT(PropertyCallbackArguments::kReturnValueOffset == 4); ++ STATIC_ASSERT(PropertyCallbackArguments::kDataIndex == 5); ++ STATIC_ASSERT(PropertyCallbackArguments::kThisIndex == 6); ++ STATIC_ASSERT(PropertyCallbackArguments::kArgsLength == 7); ++ ++ Register receiver = ApiGetterDescriptor::ReceiverRegister(); ++ Register holder = ApiGetterDescriptor::HolderRegister(); ++ Register callback = ApiGetterDescriptor::CallbackRegister(); ++ Register scratch = a4; ++ DCHECK(!AreAliased(receiver, holder, callback, scratch)); ++ ++ Register api_function_address = a2; ++ ++ // Here and below +1 is for name() pushed after the args_ array. ++ using PCA = PropertyCallbackArguments; ++ __ Sub64(sp, sp, (PCA::kArgsLength + 1) * kPointerSize); ++ __ Sd(receiver, MemOperand(sp, (PCA::kThisIndex + 1) * kPointerSize)); ++ __ Ld(scratch, FieldMemOperand(callback, AccessorInfo::kDataOffset)); ++ __ Sd(scratch, MemOperand(sp, (PCA::kDataIndex + 1) * kPointerSize)); ++ __ LoadRoot(scratch, RootIndex::kUndefinedValue); ++ __ Sd(scratch, MemOperand(sp, (PCA::kReturnValueOffset + 1) * kPointerSize)); ++ __ Sd(scratch, MemOperand(sp, (PCA::kReturnValueDefaultValueIndex + 1) * ++ kPointerSize)); ++ __ li(scratch, ExternalReference::isolate_address(masm->isolate())); ++ __ Sd(scratch, MemOperand(sp, (PCA::kIsolateIndex + 1) * kPointerSize)); ++ __ Sd(holder, MemOperand(sp, (PCA::kHolderIndex + 1) * kPointerSize)); ++ // should_throw_on_error -> false ++ DCHECK_EQ(0, Smi::zero().ptr()); ++ __ Sd(zero_reg, ++ MemOperand(sp, (PCA::kShouldThrowOnErrorIndex + 1) * kPointerSize)); ++ __ Ld(scratch, FieldMemOperand(callback, AccessorInfo::kNameOffset)); ++ __ Sd(scratch, MemOperand(sp, 0 * kPointerSize)); ++ ++ // v8::PropertyCallbackInfo::args_ array and name handle. ++ const int kStackUnwindSpace = PropertyCallbackArguments::kArgsLength + 1; ++ ++ // Load address of v8::PropertyAccessorInfo::args_ array and name handle. ++ __ Move(a0, sp); // a0 = Handle ++ __ Add64(a1, a0, Operand(1 * kPointerSize)); // a1 = v8::PCI::args_ ++ ++ const int kApiStackSpace = 1; ++ FrameScope frame_scope(masm, StackFrame::MANUAL); ++ __ EnterExitFrame(false, kApiStackSpace); ++ ++ // Create v8::PropertyCallbackInfo object on the stack and initialize ++ // it's args_ field. ++ __ Sd(a1, MemOperand(sp, 1 * kPointerSize)); ++ __ Add64(a1, sp, Operand(1 * kPointerSize)); ++ // a1 = v8::PropertyCallbackInfo& ++ ++ ExternalReference thunk_ref = ++ ExternalReference::invoke_accessor_getter_callback(); ++ ++ __ Ld(scratch, FieldMemOperand(callback, AccessorInfo::kJsGetterOffset)); ++ __ Ld(api_function_address, ++ FieldMemOperand(scratch, Foreign::kForeignAddressOffset)); ++ ++ // +3 is to skip prolog, return address and name handle. ++ MemOperand return_value_operand( ++ fp, (PropertyCallbackArguments::kReturnValueOffset + 3) * kPointerSize); ++ MemOperand* const kUseStackSpaceConstant = nullptr; ++ CallApiFunctionAndReturn(masm, api_function_address, thunk_ref, ++ kStackUnwindSpace, kUseStackSpaceConstant, ++ return_value_operand); ++} ++ ++void Builtins::Generate_DirectCEntry(MacroAssembler* masm) { ++ // The sole purpose of DirectCEntry is for movable callers (e.g. any general ++ // purpose Code object) to be able to call into C functions that may trigger ++ // GC and thus move the caller. ++ // ++ // DirectCEntry places the return address on the stack (updated by the GC), ++ // making the call GC safe. The irregexp backend relies on this. ++ ++ // Make place for arguments to fit C calling convention. Callers use ++ // EnterExitFrame/LeaveExitFrame so they handle stack restoring and we don't ++ // have to do that here. Any caller must drop kCArgsSlotsSize stack space ++ // after the call. ++ __ Add64(sp, sp, -kCArgsSlotsSize); ++ ++ __ Sd(ra, MemOperand(sp, kCArgsSlotsSize)); // Store the return address. ++ __ Call(t6); // Call the C++ function. ++ __ Ld(t6, MemOperand(sp, kCArgsSlotsSize)); // Return to calling code. ++ ++ if (FLAG_debug_code && FLAG_enable_slow_asserts) { ++ // In case of an error the return address may point to a memory area ++ // filled with kZapValue by the GC. Dereference the address and check for ++ // this. ++ __ Uld(a4, MemOperand(t6)); ++ __ Assert(ne, AbortReason::kReceivedInvalidReturnAddress, a4, ++ Operand(reinterpret_cast(kZapValue))); ++ } ++ ++ __ Jump(t6); ++} ++ ++#undef __ ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/assembler-arch.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/assembler-arch.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/assembler-arch.h +@@ -23,6 +23,10 @@ + #include "src/codegen/mips64/assembler-mips64.h" + #elif V8_TARGET_ARCH_S390 + #include "src/codegen/s390/assembler-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/codegen/riscv64/assembler-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/codegen/riscv/assembler-riscv.h" + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/assembler-inl.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/assembler-inl.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/assembler-inl.h +@@ -23,6 +23,10 @@ + #include "src/codegen/mips64/assembler-mips64-inl.h" + #elif V8_TARGET_ARCH_S390 + #include "src/codegen/s390/assembler-s390-inl.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/codegen/riscv64/assembler-riscv64-inl.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/codegen/riscv/assembler-riscv-inl.h" + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/constants-arch.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/constants-arch.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/constants-arch.h +@@ -21,6 +21,10 @@ + #include "src/codegen/s390/constants-s390.h" // NOLINT + #elif V8_TARGET_ARCH_X64 + #include "src/codegen/x64/constants-x64.h" // NOLINT ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/codegen/riscv64/constants-riscv64.h" // NOLINT ++#elif V8_TARGET_ARCH_RISCV ++#include "src/codegen/riscv64/constants-riscv.h" // NOLINT + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/cpu-features.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/cpu-features.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/cpu-features.h +@@ -67,6 +67,12 @@ enum CpuFeature { + VECTOR_ENHANCE_FACILITY_1, + VECTOR_ENHANCE_FACILITY_2, + MISC_INSTR_EXT2, ++ ++// FIXME (RISCV): add features for RISCV ++#elif V8_TARGET_ARCH_RISCV64 ++ FPU, ++ FP64FPU, ++ RISCV_SIMD, + #endif + + NUMBER_OF_CPU_FEATURES +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/external-reference.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/external-reference.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/external-reference.cc +@@ -502,6 +502,8 @@ ExternalReference ExternalReference::inv + #define re_stack_check_func RegExpMacroAssemblerMIPS::CheckStackGuardState + #elif V8_TARGET_ARCH_S390 + #define re_stack_check_func RegExpMacroAssemblerS390::CheckStackGuardState ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++#define re_stack_check_func RegExpMacroAssemblerRISCV::CheckStackGuardState + #else + UNREACHABLE(); + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/interface-descriptors.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/interface-descriptors.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/interface-descriptors.cc +@@ -397,7 +397,9 @@ void WasmFloat64ToNumberDescriptor::Init + } + #endif // !V8_TARGET_ARCH_IA32 + +-#if !defined(V8_TARGET_ARCH_MIPS) && !defined(V8_TARGET_ARCH_MIPS64) ++// FIXME(RISCV): Review this once atomics are added ++#if !defined(V8_TARGET_ARCH_MIPS) && !defined(V8_TARGET_ARCH_MIPS64) && \ ++ !defined(V8_TARGET_ARCH_RISCV64) && !defined(V8_TARGET_ARCH_RISCV) + void WasmI32AtomicWait32Descriptor::InitializePlatformSpecific( + CallInterfaceDescriptorData* data) { + DefaultInitializePlatformSpecific(data, kParameterCount); +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/macro-assembler.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/macro-assembler.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/macro-assembler.h +@@ -52,6 +52,12 @@ enum AllocationFlags { + #elif V8_TARGET_ARCH_S390 + #include "src/codegen/s390/constants-s390.h" + #include "src/codegen/s390/macro-assembler-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/codegen/riscv64/macro-assembler-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/codegen/riscv/constants-riscv.h" ++#include "src/codegen/riscv/macro-assembler-riscv.h" + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/register-arch.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/register-arch.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/register-arch.h +@@ -24,6 +24,10 @@ + #include "src/codegen/mips64/register-mips64.h" + #elif V8_TARGET_ARCH_S390 + #include "src/codegen/s390/register-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/codegen/riscv64/register-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/codegen/riscv/register-riscv.h" + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/register-configuration.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/register-configuration.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/register-configuration.cc +@@ -64,6 +64,8 @@ static int get_num_allocatable_double_re + kMaxAllocatableDoubleRegisterCount; + #elif V8_TARGET_ARCH_S390 + kMaxAllocatableDoubleRegisterCount; ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ kMaxAllocatableDoubleRegisterCount; + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/reloc-info.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/reloc-info.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/reloc-info.cc +@@ -330,7 +330,8 @@ bool RelocInfo::OffHeapTargetIsCodedSpec + return false; + #elif defined(V8_TARGET_ARCH_IA32) || defined(V8_TARGET_ARCH_MIPS) || \ + defined(V8_TARGET_ARCH_MIPS64) || defined(V8_TARGET_ARCH_PPC) || \ +- defined(V8_TARGET_ARCH_PPC64) || defined(V8_TARGET_ARCH_S390) ++ defined(V8_TARGET_ARCH_PPC64) || defined(V8_TARGET_ARCH_S390) || \ ++ defined(V8_TARGET_ARCH_RISCV64) || defined(V8_TARGET_ARCH_RISCV) + return true; + #endif + } +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/reloc-info.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/codegen/reloc-info.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/reloc-info.h +@@ -69,7 +69,7 @@ class RelocInfo { + EXTERNAL_REFERENCE, // The address of an external C++ function. + INTERNAL_REFERENCE, // An address inside the same function. + +- // Encoded internal reference, used only on MIPS, MIPS64 and PPC. ++ // Encoded internal reference, used only on RISCV64, MIPS, MIPS64 and PPC. + INTERNAL_REFERENCE_ENCODED, + + // An off-heap instruction stream target. See http://goo.gl/Z2HUiM. +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64-inl.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64-inl.h +@@ -0,0 +1,247 @@ ++ ++// Copyright (c) 1994-2006 Sun Microsystems Inc. ++// All Rights Reserved. ++// ++// Redistribution and use in source and binary forms, with or without ++// modification, are permitted provided that the following conditions are ++// met: ++// ++// - Redistributions of source code must retain the above copyright notice, ++// this list of conditions and the following disclaimer. ++// ++// - Redistribution in binary form must reproduce the above copyright ++// notice, this list of conditions and the following disclaimer in the ++// documentation and/or other materials provided with the distribution. ++// ++// - Neither the name of Sun Microsystems or the names of contributors may ++// be used to endorse or promote products derived from this software without ++// specific prior written permission. ++// ++// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++// The original source code covered by the above license above has been ++// modified significantly by Google Inc. ++// Copyright 2012 the V8 project authors. All rights reserved. ++ ++#ifndef V8_CODEGEN_RISCV_ASSEMBLER_RISCV_INL_H_ ++#define V8_CODEGEN_RISCV_ASSEMBLER_RISCV_INL_H_ ++ ++#include "src/codegen/assembler.h" ++#include "src/codegen/riscv64/assembler-riscv64.h" ++#include "src/debug/debug.h" ++#include "src/objects/objects-inl.h" ++ ++namespace v8 { ++namespace internal { ++ ++bool CpuFeatures::SupportsOptimizer() { return IsSupported(FPU); } ++ ++bool CpuFeatures::SupportsWasmSimd128() { return IsSupported(RISCV_SIMD); } ++ ++// ----------------------------------------------------------------------------- ++// Operand and MemOperand. ++ ++bool Operand::is_reg() const { return rm_.is_valid(); } ++ ++int64_t Operand::immediate() const { ++ DCHECK(!is_reg()); ++ DCHECK(!IsHeapObjectRequest()); ++ return value_.immediate; ++} ++ ++// ----------------------------------------------------------------------------- ++// RelocInfo. ++ ++void RelocInfo::apply(intptr_t delta) { ++ if (IsInternalReference(rmode_) || IsInternalReferenceEncoded(rmode_)) { ++ // Absolute code pointer inside code object moves with the code object. ++ Assembler::RelocateInternalReference(rmode_, pc_, delta); ++ } ++} ++ ++Address RelocInfo::target_address() { ++ DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_) || IsWasmCall(rmode_)); ++ return Assembler::target_address_at(pc_, constant_pool_); ++} ++ ++Address RelocInfo::target_address_address() { ++ DCHECK(HasTargetAddressAddress()); ++ // Read the address of the word containing the target_address in an ++ // instruction stream. ++ // The only architecture-independent user of this function is the serializer. ++ // The serializer uses it to find out how many raw bytes of instruction to ++ // output before the next target. ++ // For an instruction like LUI/ORI where the target bits are mixed into the ++ // instruction bits, the size of the target will be zero, indicating that the ++ // serializer should not step forward in memory after a target is resolved ++ // and written. In this case the target_address_address function should ++ // return the end of the instructions to be patched, allowing the ++ // deserializer to deserialize the instructions as raw bytes and put them in ++ // place, ready to be patched with the target. After jump optimization, ++ // that is the address of the instruction that follows J/JAL/JR/JALR ++ // instruction. ++ return pc_ + Assembler::kInstructionsFor64BitConstant * kInstrSize; ++} ++ ++Address RelocInfo::constant_pool_entry_address() { UNREACHABLE(); } ++ ++int RelocInfo::target_address_size() { return Assembler::kSpecialTargetSize; } ++ ++void Assembler::deserialization_set_special_target_at( ++ Address instruction_payload, Code code, Address target) { ++ set_target_address_at(instruction_payload, ++ !code.is_null() ? code.constant_pool() : kNullAddress, ++ target); ++} ++ ++int Assembler::deserialization_special_target_size( ++ Address instruction_payload) { ++ return kSpecialTargetSize; ++} ++ ++void Assembler::set_target_internal_reference_encoded_at(Address pc, ++ Address target) { ++ set_target_value_at(pc, static_cast(target)); ++} ++ ++void Assembler::deserialization_set_target_internal_reference_at( ++ Address pc, Address target, RelocInfo::Mode mode) { ++ if (RelocInfo::IsInternalReferenceEncoded(mode)) { ++ DCHECK(IsLui(instr_at(pc))); ++ set_target_internal_reference_encoded_at(pc, target); ++ } else { ++ DCHECK(RelocInfo::IsInternalReference(mode)); ++ Memory
(pc) = target; ++ } ++} ++ ++HeapObject RelocInfo::target_object() { ++ DCHECK(IsCodeTarget(rmode_) || IsFullEmbeddedObject(rmode_)); ++ return HeapObject::cast( ++ Object(Assembler::target_address_at(pc_, constant_pool_))); ++} ++ ++HeapObject RelocInfo::target_object_no_host(Isolate* isolate) { ++ return target_object(); ++} ++ ++Handle RelocInfo::target_object_handle(Assembler* origin) { ++ DCHECK(IsCodeTarget(rmode_) || IsFullEmbeddedObject(rmode_)); ++ return Handle(reinterpret_cast( ++ Assembler::target_address_at(pc_, constant_pool_))); ++} ++ ++void RelocInfo::set_target_object(Heap* heap, HeapObject target, ++ WriteBarrierMode write_barrier_mode, ++ ICacheFlushMode icache_flush_mode) { ++ DCHECK(IsCodeTarget(rmode_) || IsFullEmbeddedObject(rmode_)); ++ Assembler::set_target_address_at(pc_, constant_pool_, target.ptr(), ++ icache_flush_mode); ++ if (write_barrier_mode == UPDATE_WRITE_BARRIER && !host().is_null() && ++ !FLAG_disable_write_barriers) { ++ WriteBarrierForCode(host(), this, target); ++ } ++} ++ ++Address RelocInfo::target_external_reference() { ++ DCHECK(rmode_ == EXTERNAL_REFERENCE); ++ return Assembler::target_address_at(pc_, constant_pool_); ++} ++ ++void RelocInfo::set_target_external_reference( ++ Address target, ICacheFlushMode icache_flush_mode) { ++ DCHECK(rmode_ == RelocInfo::EXTERNAL_REFERENCE); ++ Assembler::set_target_address_at(pc_, constant_pool_, target, ++ icache_flush_mode); ++} ++ ++Address RelocInfo::target_internal_reference() { ++ if (rmode_ == INTERNAL_REFERENCE) { ++ return Memory
(pc_); ++ } else { ++ // Encoded internal references are j/jal instructions. ++ DCHECK(rmode_ == INTERNAL_REFERENCE_ENCODED); ++ DCHECK(Assembler::IsLui(Assembler::instr_at(pc_ + 0 * kInstrSize))); ++ Address address = Assembler::target_address_at(pc_); ++ return address; ++ } ++} ++ ++Address RelocInfo::target_internal_reference_address() { ++ DCHECK(rmode_ == INTERNAL_REFERENCE || rmode_ == INTERNAL_REFERENCE_ENCODED); ++ return pc_; ++} ++ ++Address RelocInfo::target_runtime_entry(Assembler* origin) { ++ DCHECK(IsRuntimeEntry(rmode_)); ++ return target_address(); ++} ++ ++void RelocInfo::set_target_runtime_entry(Address target, ++ WriteBarrierMode write_barrier_mode, ++ ICacheFlushMode icache_flush_mode) { ++ DCHECK(IsRuntimeEntry(rmode_)); ++ if (target_address() != target) ++ set_target_address(target, write_barrier_mode, icache_flush_mode); ++} ++ ++Address RelocInfo::target_off_heap_target() { ++ DCHECK(IsOffHeapTarget(rmode_)); ++ return Assembler::target_address_at(pc_, constant_pool_); ++} ++ ++void RelocInfo::WipeOut() { ++ DCHECK(IsFullEmbeddedObject(rmode_) || IsCodeTarget(rmode_) || ++ IsRuntimeEntry(rmode_) || IsExternalReference(rmode_) || ++ IsInternalReference(rmode_) || IsInternalReferenceEncoded(rmode_) || ++ IsOffHeapTarget(rmode_)); ++ if (IsInternalReference(rmode_)) { ++ Memory
(pc_) = kNullAddress; ++ } else if (IsInternalReferenceEncoded(rmode_)) { ++ Assembler::set_target_internal_reference_encoded_at(pc_, kNullAddress); ++ } else { ++ Assembler::set_target_address_at(pc_, constant_pool_, kNullAddress); ++ } ++} ++ ++// ----------------------------------------------------------------------------- ++// Assembler. ++ ++void Assembler::CheckBuffer() { ++ if (buffer_space() <= kGap) { ++ GrowBuffer(); ++ } ++} ++ ++template ++void Assembler::EmitHelper(T x) { ++ DEBUG_PRINTF("%p: ", pc_); ++ disassembleInstr((int)x); ++ *reinterpret_cast(pc_) = x; ++ pc_ += sizeof(x); ++ CheckTrampolinePoolQuick(); ++} ++ ++void Assembler::emit(Instr x) { ++ if (!is_buffer_growth_blocked()) { ++ CheckBuffer(); ++ } ++ EmitHelper(x); ++} ++ ++EnsureSpace::EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_CODEGEN_RISCV_ASSEMBLER_RISCV_INL_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64.cc +@@ -0,0 +1,2342 @@ ++// Copyright (c) 1994-2006 Sun Microsystems Inc. ++// All Rights Reserved. ++// ++// Redistribution and use in source and binary forms, with or without ++// modification, are permitted provided that the following conditions are ++// met: ++// ++// - Redistributions of source code must retain the above copyright notice, ++// this list of conditions and the following disclaimer. ++// ++// - Redistribution in binary form must reproduce the above copyright ++// notice, this list of conditions and the following disclaimer in the ++// documentation and/or other materials provided with the distribution. ++// ++// - Neither the name of Sun Microsystems or the names of contributors may ++// be used to endorse or promote products derived from this software without ++// specific prior written permission. ++// ++// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++// The original source code covered by the above license above has been ++// modified significantly by Google Inc. ++// Copyright 2012 the V8 project authors. All rights reserved. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/riscv64/assembler-riscv64.h" ++ ++#include "src/base/cpu.h" ++#include "src/codegen/riscv64/assembler-riscv64-inl.h" ++#include "src/codegen/safepoint-table.h" ++#include "src/codegen/string-constants.h" ++#include "src/deoptimizer/deoptimizer.h" ++#include "src/diagnostics/disasm.h" ++#include "src/diagnostics/disassembler.h" ++#include "src/objects/heap-number-inl.h" ++ ++namespace v8 { ++namespace internal { ++// Get the CPU features enabled by the build. For cross compilation the ++// preprocessor symbols CAN_USE_FPU_INSTRUCTIONS ++// can be defined to enable FPU instructions when building the ++// snapshot. ++static unsigned CpuFeaturesImpliedByCompiler() { ++ unsigned answer = 0; ++#ifdef CAN_USE_FPU_INSTRUCTIONS ++ answer |= 1u << FPU; ++#endif // def CAN_USE_FPU_INSTRUCTIONS ++ ++ return answer; ++} ++ ++void CpuFeatures::ProbeImpl(bool cross_compile) { ++ supported_ |= CpuFeaturesImpliedByCompiler(); ++ ++ // Only use statically determined features for cross compile (snapshot). ++ if (cross_compile) return; ++ ++ // Probe for additional features at runtime. ++ base::CPU cpu; ++ if (cpu.has_fpu()) supported_ |= 1u << FPU; ++} ++ ++void CpuFeatures::PrintTarget() {} ++void CpuFeatures::PrintFeatures() {} ++ ++int ToNumber(Register reg) { ++ DCHECK(reg.is_valid()); ++ const int kNumbers[] = { ++ 0, // zero_reg ++ 1, // ra ++ 2, // sp ++ 3, // gp ++ 4, // tp ++ 5, // t0 ++ 6, // t1 ++ 7, // t2 ++ 8, // s0/fp ++ 9, // s1 ++ 10, // a0 ++ 11, // a1 ++ 12, // a2 ++ 13, // a3 ++ 14, // a4 ++ 15, // a5 ++ 16, // a6 ++ 17, // a7 ++ 18, // s2 ++ 19, // s3 ++ 20, // s4 ++ 21, // s5 ++ 22, // s6 ++ 23, // s7 ++ 24, // s8 ++ 25, // s9 ++ 26, // s10 ++ 27, // s11 ++ 28, // t3 ++ 29, // t4 ++ 30, // t5 ++ 31, // t6 ++ }; ++ return kNumbers[reg.code()]; ++} ++ ++Register ToRegister(int num) { ++ DCHECK(num >= 0 && num < kNumRegisters); ++ const Register kRegisters[] = { ++ zero_reg, ra, sp, gp, tp, t0, t1, t2, fp, s1, a0, a1, a2, a3, a4, a5, ++ a6, a7, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, t3, t4, t5, t6}; ++ return kRegisters[num]; ++} ++ ++// ----------------------------------------------------------------------------- ++// Implementation of RelocInfo. ++ ++const int RelocInfo::kApplyMask = ++ RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE) | ++ RelocInfo::ModeMask(RelocInfo::INTERNAL_REFERENCE_ENCODED); ++ ++bool RelocInfo::IsCodedSpecially() { ++ // The deserializer needs to know whether a pointer is specially coded. Being ++ // specially coded on RISC-V means that it is a lui/addi instruction, and that ++ // is always the case inside code objects. ++ return true; ++} ++ ++bool RelocInfo::IsInConstantPool() { return false; } ++ ++uint32_t RelocInfo::wasm_call_tag() const { ++ DCHECK(rmode_ == WASM_CALL || rmode_ == WASM_STUB_CALL); ++ return static_cast( ++ Assembler::target_address_at(pc_, constant_pool_)); ++} ++ ++// ----------------------------------------------------------------------------- ++// Implementation of Operand and MemOperand. ++// See assembler-riscv64-inl.h for inlined constructors. ++ ++Operand::Operand(Handle handle) ++ : rm_(no_reg), rmode_(RelocInfo::FULL_EMBEDDED_OBJECT) { ++ value_.immediate = static_cast(handle.address()); ++} ++ ++Operand Operand::EmbeddedNumber(double value) { ++ int32_t smi; ++ if (DoubleToSmiInteger(value, &smi)) return Operand(Smi::FromInt(smi)); ++ Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT); ++ result.is_heap_object_request_ = true; ++ result.value_.heap_object_request = HeapObjectRequest(value); ++ return result; ++} ++ ++Operand Operand::EmbeddedStringConstant(const StringConstantBase* str) { ++ Operand result(0, RelocInfo::FULL_EMBEDDED_OBJECT); ++ result.is_heap_object_request_ = true; ++ result.value_.heap_object_request = HeapObjectRequest(str); ++ return result; ++} ++ ++MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { ++ offset_ = offset; ++} ++ ++MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier, ++ OffsetAddend offset_addend) ++ : Operand(rm) { ++ offset_ = unit * multiplier + offset_addend; ++} ++ ++void Assembler::AllocateAndInstallRequestedHeapObjects(Isolate* isolate) { ++ DCHECK_IMPLIES(isolate == nullptr, heap_object_requests_.empty()); ++ for (auto& request : heap_object_requests_) { ++ Handle object; ++ switch (request.kind()) { ++ case HeapObjectRequest::kHeapNumber: ++ object = isolate->factory()->NewHeapNumber( ++ request.heap_number()); ++ break; ++ case HeapObjectRequest::kStringConstant: ++ const StringConstantBase* str = request.string(); ++ CHECK_NOT_NULL(str); ++ object = str->AllocateStringConstant(isolate); ++ break; ++ } ++ Address pc = reinterpret_cast
(buffer_start_) + request.offset(); ++ set_target_value_at(pc, reinterpret_cast(object.location())); ++ } ++} ++ ++// ----------------------------------------------------------------------------- ++// Specific instructions, constants, and masks. ++ ++Assembler::Assembler(const AssemblerOptions& options, ++ std::unique_ptr buffer) ++ : AssemblerBase(options, std::move(buffer)), ++ scratch_register_list_(t3.bit()) { ++ reloc_info_writer.Reposition(buffer_start_ + buffer_->size(), pc_); ++ ++ last_trampoline_pool_end_ = 0; ++ no_trampoline_pool_before_ = 0; ++ trampoline_pool_blocked_nesting_ = 0; ++ // We leave space (16 * kTrampolineSlotsSize) ++ // for BlockTrampolinePoolScope buffer. ++ next_buffer_check_ = FLAG_force_long_branches ++ ? kMaxInt ++ : kMaxBranchOffset - kTrampolineSlotsSize * 16; ++ internal_trampoline_exception_ = false; ++ last_bound_pos_ = 0; ++ ++ trampoline_emitted_ = FLAG_force_long_branches; ++ unbound_labels_count_ = 0; ++ block_buffer_growth_ = false; ++} ++ ++void Assembler::GetCode(Isolate* isolate, CodeDesc* desc, ++ SafepointTableBuilder* safepoint_table_builder, ++ int handler_table_offset) { ++ int code_comments_size = WriteCodeComments(); ++ ++ DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap. ++ ++ AllocateAndInstallRequestedHeapObjects(isolate); ++ ++ // Set up code descriptor. ++ // TODO(jgruber): Reconsider how these offsets and sizes are maintained up to ++ // this point to make CodeDesc initialization less fiddly. ++ ++ static constexpr int kConstantPoolSize = 0; ++ const int instruction_size = pc_offset(); ++ const int code_comments_offset = instruction_size - code_comments_size; ++ const int constant_pool_offset = code_comments_offset - kConstantPoolSize; ++ const int handler_table_offset2 = (handler_table_offset == kNoHandlerTable) ++ ? constant_pool_offset ++ : handler_table_offset; ++ const int safepoint_table_offset = ++ (safepoint_table_builder == kNoSafepointTable) ++ ? handler_table_offset2 ++ : safepoint_table_builder->GetCodeOffset(); ++ const int reloc_info_offset = ++ static_cast(reloc_info_writer.pos() - buffer_->start()); ++ CodeDesc::Initialize(desc, this, safepoint_table_offset, ++ handler_table_offset2, constant_pool_offset, ++ code_comments_offset, reloc_info_offset); ++} ++ ++void Assembler::Align(int m) { ++ DCHECK(m >= 4 && base::bits::IsPowerOfTwo(m)); ++ while ((pc_offset() & (m - 1)) != 0) { ++ nop(); ++ } ++} ++ ++void Assembler::CodeTargetAlign() { ++ // No advantage to aligning branch/call targets to more than ++ // single instruction, that I am aware of. ++ Align(4); ++} ++ ++// Labels refer to positions in the (to be) generated code. ++// There are bound, linked, and unused labels. ++// ++// Bound labels refer to known positions in the already ++// generated code. pos() is the position the label refers to. ++// ++// Linked labels refer to unknown positions in the code ++// to be generated; pos() is the position of the last ++// instruction using the label. ++ ++// The link chain is terminated by a value in the instruction of 0, ++// which is an otherwise illegal value (branch 0 is inf loop). ++ ++const int kEndOfChain = 0; ++ ++// Determines the end of the Jump chain (a subset of the label link chain). ++const int kEndOfJumpChain = 0; ++ ++bool Assembler::IsBranch(Instr instr) { ++ return (instr & kBaseOpcodeMask) == BRANCH; ++} ++ ++bool Assembler::IsJump(Instr instr) { ++ int Op = instr & kBaseOpcodeMask; ++ return Op == JAL || Op == JALR; ++} ++ ++bool Assembler::IsJal(Instr instr) { return (instr & kBaseOpcodeMask) == JAL; } ++ ++bool Assembler::IsJalr(Instr instr) { ++ return (instr & kBaseOpcodeMask) == JALR; ++} ++ ++bool Assembler::IsLui(Instr instr) { return (instr & kBaseOpcodeMask) == LUI; } ++bool Assembler::IsAuipc(Instr instr) { return (instr & kBaseOpcodeMask) == AUIPC; } ++bool Assembler::IsAddiw(Instr instr) { ++ return (instr & (kBaseOpcodeMask | kFunct3Mask)) == RO_ADDIW; ++} ++bool Assembler::IsAddi(Instr instr) { ++ return (instr & (kBaseOpcodeMask | kFunct3Mask)) == RO_ADDI; ++} ++bool Assembler::IsSlli(Instr instr) { ++ return (instr & (kBaseOpcodeMask | kFunct3Mask)) == RO_SLLI; ++} ++int Assembler::target_at(int pos, bool is_internal) { ++ if (is_internal) { ++ int64_t* p = reinterpret_cast(buffer_start_ + pos); ++ int64_t address = *p; ++ if (address == kEndOfJumpChain) { ++ return kEndOfChain; ++ } else { ++ int64_t instr_address = reinterpret_cast(p); ++ DCHECK(instr_address - address < INT_MAX); ++ int delta = static_cast(instr_address - address); ++ DCHECK(pos > delta); ++ return pos - delta; ++ } ++ } ++ Instr instr = instr_at(pos); ++ DEBUG_PRINTF("target_at: %p (%d)\n\t", ++ reinterpret_cast(buffer_start_ + pos), pos); ++ disassembleInstr(instr); ++ if (IsBranch(instr)) { ++ int32_t imm13 = BranchOffset(instr); ++ if (imm13 == kEndOfJumpChain) { ++ // EndOfChain sentinel is returned directly, not relative to pc or pos. ++ return kEndOfChain; ++ } else { ++ return pos + imm13; ++ } ++ } else if (IsJal(instr)) { ++ int32_t imm21 = JumpOffset(instr); ++ if (imm21 == kEndOfJumpChain) { ++ // EndOfChain sentinel is returned directly, not relative to pc or pos. ++ return kEndOfChain; ++ } else { ++ return pos + imm21; ++ } ++ } else if (IsJalr(instr)) { ++ int32_t imm12 = instr >> 20; ++ if (imm12 == kEndOfJumpChain) { ++ // EndOfChain sentinel is returned directly, not relative to pc or pos. ++ return kEndOfChain; ++ } else { ++ return pos + imm12; ++ } ++ } else if (IsLui(instr)) { ++ Address pc = reinterpret_cast
(buffer_start_ + pos); ++ pc = target_address_at(pc); ++ uint64_t instr_address = reinterpret_cast(buffer_start_ + pos); ++ uint64_t imm = reinterpret_cast(pc); ++ if(imm == kEndOfJumpChain) { ++ return kEndOfChain; ++ } else { ++ DCHECK(instr_address - imm < INT_MAX); ++ int32_t delta = static_cast(instr_address - imm); ++ DCHECK(pos > delta); ++ return pos - delta; ++ } ++ } else if (IsAuipc(instr)) { ++ Instr instr_auipc = instr; ++ Instr instr_jalr = instr_at(pos + 4); ++ DCHECK(IsJalr(instr_jalr)); ++ int32_t offset = BrachlongOffset(instr_auipc, instr_jalr); ++ if(offset == kEndOfJumpChain) ++ return kEndOfChain; ++ return offset + pos; ++ } else { ++ // Emitted label constant, not part of a branch. ++ if (instr == 0) { ++ return kEndOfChain; ++ } else { ++ int32_t imm18 = ((instr & static_cast(kImm16Mask)) << 16) >> 14; ++ return (imm18 + pos); ++ } ++ } ++} ++ ++static inline Instr SetBranchOffset(int32_t pos, int32_t target_pos, ++ Instr instr) { ++ int32_t imm = target_pos - pos; ++ DCHECK_EQ(imm & 1, 0); ++ DCHECK(is_intn(imm, Assembler::kBranchOffsetBits)); ++ ++ instr &= ~kBImm12Mask; ++ int32_t imm12 = ((imm & 0x800) >> 4) | // bit 11 ++ ((imm & 0x1e) << 7) | // bits 4-1 ++ ((imm & 0x7e0) << 20) | // bits 10-5 ++ ((imm & 0x1000) << 19); // bit 12 ++ ++ return instr | (imm12 & kBImm12Mask); ++} ++ ++static inline Instr SetJalOffset(int32_t pos, int32_t target_pos, Instr instr) { ++ int32_t imm = target_pos - pos; ++ DCHECK_EQ(imm & 1, 0); ++ DCHECK(is_intn(imm, Assembler::kJumpOffsetBits)); ++ ++ instr &= ~kImm20Mask; ++ int32_t imm20 = (imm & 0xff000) | // bits 19-12 ++ ((imm & 0x800) << 9) | // bit 11 ++ ((imm & 0x7fe) << 20) | // bits 10-1 ++ ((imm & 0x100000) << 11); // bit 20 ++ ++ return instr | (imm20 & kImm20Mask); ++} ++ ++void Assembler::target_at_put(int pos, int target_pos, bool is_internal) { ++ if (is_internal) { ++ uint64_t imm = reinterpret_cast(buffer_start_) + target_pos; ++ *reinterpret_cast(buffer_start_ + pos) = imm; ++ return; ++ } ++ DEBUG_PRINTF("target_at_put: %p (%d) to %p (%d)\n", ++ reinterpret_cast(buffer_start_ + pos), pos, ++ reinterpret_cast(buffer_start_ + target_pos), ++ target_pos); ++ Instr instr = instr_at(pos); ++ ++ if (IsBranch(instr)) { ++ instr = SetBranchOffset(pos, target_pos, instr); ++ instr_at_put(pos, instr); ++ } else if (IsJal(instr)) { ++ instr = SetJalOffset(pos, target_pos, instr); ++ instr_at_put(pos, instr); ++ } else if (IsLui(instr)) { ++ Address pc = reinterpret_cast
(buffer_start_ + pos); ++ set_target_value_at(pc, reinterpret_cast(buffer_start_ + target_pos)); ++ } else if (IsAuipc(instr)) { ++ Instr instr_auipc = instr; ++ Instr instr_jalr = instr_at(pos + 4); ++ DCHECK(IsJalr(instr_jalr)); ++ ++ int64_t offset = target_pos - pos; ++ DCHECK(is_int32(offset)); ++ ++ int32_t Hi20 = (((int32_t)offset + 0x800) >> 12); ++ int32_t Lo12 = (int32_t)offset << 20 >> 20; ++ ++ const int kImm31_12Mask = ((1 << 20) - 1) << 12; ++ const int kImm19_0Mask = ((1 << 20) - 1); ++ instr_auipc = (instr_auipc & ~kImm31_12Mask) | ++ ((Hi20 & kImm19_0Mask) << 12); ++ instr_at_put(pos, instr_auipc); ++ ++ const int kImm31_20Mask = ((1 << 12) - 1) << 20; ++ const int kImm11_0Mask = ((1 << 12) - 1); ++ instr_jalr = (instr_jalr & ~kImm31_20Mask) | ++ ((Lo12 & kImm11_0Mask) << 20); ++ instr_at_put(pos + 4, instr_jalr); ++ } else { ++ // Emitted label constant, not part of a branch. ++ // Make label relative to Code pointer of generated Code object. ++ instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); ++ } ++ disassembleInstr(instr); ++} ++ ++void Assembler::print(const Label* L) { ++ if (L->is_unused()) { ++ PrintF("unused label\n"); ++ } else if (L->is_bound()) { ++ PrintF("bound label to %d\n", L->pos()); ++ } else if (L->is_linked()) { ++ Label l; ++ l.link_to(L->pos()); ++ PrintF("unbound label"); ++ while (l.is_linked()) { ++ PrintF("@ %d ", l.pos()); ++ Instr instr = instr_at(l.pos()); ++ if ((instr & ~kImm16Mask) == 0) { ++ PrintF("value\n"); ++ } else { ++ PrintF("%d\n", instr); ++ } ++ next(&l, is_internal_reference(&l)); ++ } ++ } else { ++ PrintF("label in inconsistent state (pos = %d)\n", L->pos_); ++ } ++} ++ ++void Assembler::bind_to(Label* L, int pos) { ++ DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position. ++ DEBUG_PRINTF("binding %d to label %p\n", pos, L); ++ int trampoline_pos = kInvalidSlotPos; ++ bool is_internal = false; ++ if (L->is_linked() && !trampoline_emitted_) { ++ unbound_labels_count_--; ++ if (!is_internal_reference(L)) { ++ next_buffer_check_ += kTrampolineSlotsSize; ++ } ++ } ++ ++ while (L->is_linked()) { ++ int fixup_pos = L->pos(); ++ int dist = pos - fixup_pos; ++ is_internal = is_internal_reference(L); ++ next(L, is_internal); // Call next before overwriting link with target ++ // at fixup_pos. ++ Instr instr = instr_at(fixup_pos); ++ DEBUG_PRINTF("\tfixup: %d to %d\n", fixup_pos, dist); ++ if (is_internal) { ++ target_at_put(fixup_pos, pos, is_internal); ++ } else { ++ if (IsBranch(instr)) { ++ if (dist > kMaxBranchOffset) { ++ if (trampoline_pos == kInvalidSlotPos) { ++ trampoline_pos = get_trampoline_entry(fixup_pos); ++ CHECK_NE(trampoline_pos, kInvalidSlotPos); ++ } ++ CHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset); ++ DEBUG_PRINTF("\t\ttrampolining: %d\n", trampoline_pos); ++ target_at_put(fixup_pos, trampoline_pos, false); ++ fixup_pos = trampoline_pos; ++ } ++ target_at_put(fixup_pos, pos, false); ++ } else if (IsJal(instr)) { ++ if (dist > kMaxJumpOffset) { ++ if (trampoline_pos == kInvalidSlotPos) { ++ trampoline_pos = get_trampoline_entry(fixup_pos); ++ CHECK_NE(trampoline_pos, kInvalidSlotPos); ++ } ++ CHECK((trampoline_pos - fixup_pos) <= kMaxJumpOffset); ++ DEBUG_PRINTF("\t\ttrampolining: %d\n", trampoline_pos); ++ target_at_put(fixup_pos, trampoline_pos, false); ++ fixup_pos = trampoline_pos; ++ } ++ target_at_put(fixup_pos, pos, false); ++ } else { ++ target_at_put(fixup_pos, pos, false); ++ } ++ } ++ } ++ L->bind_to(pos); ++ ++ // Keep track of the last bound label so we don't eliminate any instructions ++ // before a bound label. ++ if (pos > last_bound_pos_) last_bound_pos_ = pos; ++} ++ ++void Assembler::bind(Label* L) { ++ DCHECK(!L->is_bound()); // Label can only be bound once. ++ bind_to(L, pc_offset()); ++} ++ ++void Assembler::next(Label* L, bool is_internal) { ++ DCHECK(L->is_linked()); ++ int link = target_at(L->pos(), is_internal); ++ if (link == kEndOfChain) { ++ L->Unuse(); ++ } else { ++ DCHECK_GT(link, 0); ++ DEBUG_PRINTF("next: %p to %p (%d)\n", L, ++ reinterpret_cast(buffer_start_ + link), link); ++ L->link_to(link); ++ } ++} ++ ++bool Assembler::is_near(Label* L) { ++ DCHECK(L->is_bound()); ++ return is_intn((pc_offset() - L->pos()), kJumpOffsetBits); ++} ++ ++bool Assembler::is_near(Label* L, OffsetSize bits) { ++ if (L == nullptr || !L->is_bound()) return true; ++ return is_intn((pc_offset() - L->pos()), bits); ++} ++ ++bool Assembler::is_near_branch(Label* L) { ++ DCHECK(L->is_bound()); ++ return is_intn((pc_offset() - L->pos()), kBranchOffsetBits); ++} ++ ++int Assembler::BranchOffset(Instr instr) { ++ // | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode | ++ // 31 25 11 7 ++ int32_t imm13 = ((instr & 0xf00) >> 7) | ((instr & 0x7e000000) >> 20) | ++ ((instr & 0x80) << 4) | ((instr & 0x80000000) >> 19); ++ imm13 = imm13 << 19 >> 19; ++ return imm13; ++} ++ ++int Assembler::JumpOffset(Instr instr) { ++ int32_t imm21 = ((instr & 0x7fe00000) >> 20) | ((instr & 0x100000) >> 9) | ++ (instr & 0xff000) | ((instr & 0x80000000) >> 11); ++ imm21 = imm21 << 11 >> 11; ++ return imm21; ++} ++ ++int Assembler::BrachlongOffset(Instr auipc, Instr jalr) { ++ const int kImm19_0Mask = ((1 << 20) - 1); ++ int32_t imm_auipc = auipc & (kImm19_0Mask << 12); ++ int32_t imm_jalr = jalr >> 20; ++ int32_t offset = imm_jalr + imm_auipc; ++ return offset; ++} ++ ++// We have to use a temporary register for things that can be relocated even ++// if they can be encoded in RISC-V's 12 bits of immediate-offset instruction ++// space. There is no guarantee that the relocated location can be similarly ++// encoded. ++bool Assembler::MustUseReg(RelocInfo::Mode rmode) { ++ return !RelocInfo::IsNone(rmode); ++} ++ ++void Assembler::disassembleInstr(Instr instr) { ++ if (!FLAG_debug_riscv) return; ++ disasm::NameConverter converter; ++ disasm::Disassembler disasm(converter); ++ EmbeddedVector disasm_buffer; ++ ++ disasm.InstructionDecode(disasm_buffer, reinterpret_cast(&instr)); ++ DEBUG_PRINTF("%s\n", disasm_buffer.begin()); ++} ++ ++// ----- Top-level instruction formats match those in the ISA manual ++// (R, I, S, B, U, J). These match the formats defined in the compiler ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ Register rd, Register rs1, Register rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ Register rd, FPURegister rs1, Register rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ FPURegister rd, Register rs1, Register rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ FPURegister rd, FPURegister rs1, Register rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, ++ Register rd, FPURegister rs1, FPURegister rs2) { ++ DCHECK(is_uint7(funct7) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, Register rd, ++ Register rs1, Register rs2, Register rs3, ++ RoundingMode frm) { ++ DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() && ++ rs2.is_valid() && rs3.is_valid() && is_uint3(frm)); ++ Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct2 << kFunct2Shift) | (rs3.code() << kRs3Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd, ++ FPURegister rs1, FPURegister rs2, FPURegister rs3, ++ RoundingMode frm) { ++ DCHECK(is_uint2(funct2) && rd.is_valid() && rs1.is_valid() && ++ rs2.is_valid() && rs3.is_valid() && is_uint3(frm)); ++ Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct2 << kFunct2Shift) | (rs3.code() << kRs3Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrRAtomic(uint8_t funct5, bool aq, bool rl, ++ uint8_t funct3, Register rd, Register rs1, ++ Register rs2) { ++ DCHECK(is_uint5(funct5) && is_uint3(funct3) && rd.is_valid() && ++ rs1.is_valid() && rs2.is_valid()); ++ Instr instr = AMO | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (rl << kRlShift) | (aq << kAqShift) | (funct5 << kFunct5Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd, ++ Register rs1, Register rs2, RoundingMode frm) { ++ DCHECK(rd.is_valid() && rs1.is_valid() && rs2.is_valid() && is_uint3(frm)); ++ Instr instr = opcode | (rd.code() << kRdShift) | (frm << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (rs2.code() << kRs2Shift) | ++ (funct7 << kFunct7Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, Register rd, ++ Register rs1, int16_t imm12) { ++ DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() && ++ (is_uint12(imm12) || is_int12(imm12))); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd, ++ Register rs1, int16_t imm12) { ++ DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() && ++ (is_uint12(imm12) || is_int12(imm12))); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (imm12 << kImm12Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrIShift(bool arithshift, uint8_t funct3, Opcode opcode, ++ Register rd, Register rs1, uint8_t shamt) { ++ DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() && ++ is_uint6(shamt)); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (shamt << kShamtShift) | ++ (arithshift << kArithShiftShift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrIShiftW(bool arithshift, uint8_t funct3, Opcode opcode, ++ Register rd, Register rs1, uint8_t shamt) { ++ DCHECK(is_uint3(funct3) && rd.is_valid() && rs1.is_valid() && ++ is_uint5(shamt)); ++ Instr instr = opcode | (rd.code() << kRdShift) | (funct3 << kFunct3Shift) | ++ (rs1.code() << kRs1Shift) | (shamt << kShamtWShift) | ++ (arithshift << kArithShiftShift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, ++ Register rs2, int16_t imm12) { ++ DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() && ++ is_int12(imm12)); ++ Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0 ++ (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) | ++ (rs2.code() << kRs2Shift) | ++ ((imm12 & 0xfe0) << 20); // bits 11-5 ++ emit(instr); ++} ++ ++void Assembler::GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, ++ FPURegister rs2, int16_t imm12) { ++ DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() && ++ is_int12(imm12)); ++ Instr instr = opcode | ((imm12 & 0x1f) << 7) | // bits 4-0 ++ (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) | ++ (rs2.code() << kRs2Shift) | ++ ((imm12 & 0xfe0) << 20); // bits 11-5 ++ emit(instr); ++} ++ ++void Assembler::GenInstrB(uint8_t funct3, Opcode opcode, Register rs1, ++ Register rs2, int16_t imm13) { ++ DCHECK(is_uint3(funct3) && rs1.is_valid() && rs2.is_valid() && ++ is_int13(imm13) && ((imm13 & 1) == 0)); ++ Instr instr = opcode | ((imm13 & 0x800) >> 4) | // bit 11 ++ ((imm13 & 0x1e) << 7) | // bits 4-1 ++ (funct3 << kFunct3Shift) | (rs1.code() << kRs1Shift) | ++ (rs2.code() << kRs2Shift) | ++ ((imm13 & 0x7e0) << 20) | // bits 10-5 ++ ((imm13 & 0x1000) << 19); // bit 12 ++ emit(instr); ++} ++ ++void Assembler::GenInstrU(Opcode opcode, Register rd, int32_t imm20) { ++ DCHECK(rd.is_valid() && (is_int20(imm20) || is_uint20(imm20))); ++ Instr instr = opcode | (rd.code() << kRdShift) | (imm20 << kImm20Shift); ++ emit(instr); ++} ++ ++void Assembler::GenInstrJ(Opcode opcode, Register rd, int32_t imm21) { ++ DCHECK(rd.is_valid() && is_int21(imm21) && ((imm21 & 1) == 0)); ++ Instr instr = opcode | (rd.code() << kRdShift) | ++ (imm21 & 0xff000) | // bits 19-12 ++ ((imm21 & 0x800) << 9) | // bit 11 ++ ((imm21 & 0x7fe) << 20) | // bits 10-1 ++ ((imm21 & 0x100000) << 11); // bit 20 ++ emit(instr); ++} ++ ++// ----- Instruction class templates match those in the compiler ++ ++void Assembler::GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2, ++ int16_t imm13) { ++ GenInstrB(funct3, BRANCH, rs1, rs2, imm13); ++} ++ ++void Assembler::GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1, ++ int16_t imm12) { ++ GenInstrI(funct3, LOAD, rd, rs1, imm12); ++} ++ ++void Assembler::GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2, ++ int16_t imm12) { ++ GenInstrS(funct3, STORE, rs1, rs2, imm12); ++} ++ ++void Assembler::GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1, ++ int16_t imm12) { ++ GenInstrI(funct3, OP_IMM, rd, rs1, imm12); ++} ++ ++void Assembler::GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd, ++ Register rs1, uint8_t shamt) { ++ DCHECK(is_uint6(shamt)); ++ GenInstrI(funct3, OP_IMM, rd, rs1, (arithshift << 10) | shamt); ++} ++ ++void Assembler::GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ Register rs1, Register rs2) { ++ GenInstrR(funct7, funct3, OP, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrCSR_ir(uint8_t funct3, Register rd, ++ ControlStatusReg csr, Register rs1) { ++ GenInstrI(funct3, SYSTEM, rd, rs1, csr); ++} ++ ++void Assembler::GenInstrCSR_ii(uint8_t funct3, Register rd, ++ ControlStatusReg csr, uint8_t imm5) { ++ GenInstrI(funct3, SYSTEM, rd, ToRegister(imm5), csr); ++} ++ ++void Assembler::GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd, ++ Register rs1, uint8_t shamt) { ++ GenInstrIShiftW(arithshift, funct3, OP_IMM_32, rd, rs1, shamt); ++} ++ ++void Assembler::GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ Register rs1, Register rs2) { ++ GenInstrR(funct7, funct3, OP_32, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrPriv(uint8_t funct7, Register rs1, Register rs2) { ++ GenInstrR(funct7, 0b000, SYSTEM, ToRegister(0), rs1, rs2); ++} ++ ++void Assembler::GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1, ++ int16_t imm12) { ++ GenInstrI(funct3, LOAD_FP, rd, rs1, imm12); ++} ++ ++void Assembler::GenInstrStoreFP_rri(uint8_t funct3, Register rs1, ++ FPURegister rs2, int16_t imm12) { ++ GenInstrS(funct3, STORE_FP, rs1, rs2, imm12); ++} ++ ++void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ FPURegister rs1, FPURegister rs2) { ++ GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ Register rs1, Register rs2) { ++ GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ FPURegister rs1, Register rs2) { ++ GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ FPURegister rs1, Register rs2) { ++ GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2); ++} ++ ++void Assembler::GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ FPURegister rs1, FPURegister rs2) { ++ GenInstrR(funct7, funct3, OP_FP, rd, rs1, rs2); ++} ++ ++// Returns the next free trampoline entry. ++int32_t Assembler::get_trampoline_entry(int32_t pos) { ++ int32_t trampoline_entry = kInvalidSlotPos; ++ if (!internal_trampoline_exception_) { ++ if (trampoline_.start() > pos) { ++ trampoline_entry = trampoline_.take_slot(); ++ } ++ ++ if (kInvalidSlotPos == trampoline_entry) { ++ internal_trampoline_exception_ = true; ++ } ++ } ++ return trampoline_entry; ++} ++ ++uint64_t Assembler::jump_address(Label* L) { ++ int64_t target_pos; ++ DEBUG_PRINTF("jump_address: %p to %p (%d)\n", L, ++ reinterpret_cast(buffer_start_ + pc_offset()), ++ pc_offset()); ++ if (L->is_bound()) { ++ target_pos = L->pos(); ++ } else { ++ if (L->is_linked()) { ++ target_pos = L->pos(); // L's link. ++ L->link_to(pc_offset()); ++ } else { ++ L->link_to(pc_offset()); ++ if (!trampoline_emitted_) { ++ unbound_labels_count_++; ++ next_buffer_check_ -= kTrampolineSlotsSize; ++ } ++ DEBUG_PRINTF("\tstarted link\n"); ++ return kEndOfJumpChain; ++ } ++ } ++ uint64_t imm = reinterpret_cast(buffer_start_) + target_pos; ++ DCHECK_EQ(imm & 3, 0); ++ ++ return imm; ++} ++ ++uint64_t Assembler::branch_long_offset(Label* L) { ++ int64_t target_pos; ++ ++ DEBUG_PRINTF("branch_long_offset: %p to %p (%d)\n", L, ++ reinterpret_cast(buffer_start_ + pc_offset()), ++ pc_offset()); ++ if (L->is_bound()) { ++ target_pos = L->pos(); ++ } else { ++ if (L->is_linked()) { ++ target_pos = L->pos(); // L's link. ++ L->link_to(pc_offset()); ++ } else { ++ L->link_to(pc_offset()); ++ if (!trampoline_emitted_) { ++ unbound_labels_count_++; ++ next_buffer_check_ -= kTrampolineSlotsSize; ++ } ++ DEBUG_PRINTF("\tstarted link\n"); ++ return kEndOfJumpChain; ++ } ++ } ++ int64_t offset = target_pos - pc_offset(); ++ DCHECK_EQ(offset & 3, 0); ++ ++ return static_cast(offset); ++} ++ ++int32_t Assembler::branch_offset_helper(Label* L, OffsetSize bits) { ++ int32_t target_pos; ++ ++ DEBUG_PRINTF("branch_offset_helper: %p to %p (%d)\n", L, ++ reinterpret_cast(buffer_start_ + pc_offset()), ++ pc_offset()); ++ if (L->is_bound()) { ++ target_pos = L->pos(); ++ DEBUG_PRINTF("\tbound: %d", target_pos); ++ } else { ++ if (L->is_linked()) { ++ target_pos = L->pos(); ++ L->link_to(pc_offset()); ++ DEBUG_PRINTF("\tadded to link: %d\n", target_pos); ++ } else { ++ L->link_to(pc_offset()); ++ if (!trampoline_emitted_) { ++ unbound_labels_count_++; ++ next_buffer_check_ -= kTrampolineSlotsSize; ++ } ++ DEBUG_PRINTF("\tstarted link\n"); ++ return kEndOfChain; ++ } ++ } ++ ++ int32_t offset = target_pos - pc_offset(); ++ DCHECK(is_intn(offset, bits)); ++ DCHECK_EQ(offset & 1, 0); ++ DEBUG_PRINTF("\toffset = %d\n", offset); ++ return offset; ++} ++ ++void Assembler::label_at_put(Label* L, int at_offset) { ++ int target_pos; ++ DEBUG_PRINTF("label_at_put: %p @ %p (%d)\n", L, ++ reinterpret_cast(buffer_start_ + at_offset), at_offset); ++ if (L->is_bound()) { ++ target_pos = L->pos(); ++ instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); ++ } else { ++ if (L->is_linked()) { ++ target_pos = L->pos(); // L's link. ++ int32_t imm18 = target_pos - at_offset; ++ DCHECK_EQ(imm18 & 3, 0); ++ int32_t imm16 = imm18 >> 2; ++ DCHECK(is_int16(imm16)); ++ instr_at_put(at_offset, (imm16 & kImm16Mask)); ++ } else { ++ target_pos = kEndOfChain; ++ instr_at_put(at_offset, 0); ++ if (!trampoline_emitted_) { ++ unbound_labels_count_++; ++ next_buffer_check_ -= kTrampolineSlotsSize; ++ } ++ } ++ L->link_to(at_offset); ++ } ++} ++ ++//===----------------------------------------------------------------------===// ++// Instructions ++//===----------------------------------------------------------------------===// ++ ++void Assembler::lui(Register rd, int32_t imm20) { GenInstrU(LUI, rd, imm20); } ++ ++void Assembler::auipc(Register rd, int32_t imm20) { ++ GenInstrU(AUIPC, rd, imm20); ++} ++ ++// Jumps ++ ++void Assembler::jal(Register rd, int32_t imm21) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ GenInstrJ(JAL, rd, imm21); ++ BlockTrampolinePoolFor(1); ++} ++ ++void Assembler::jalr(Register rd, Register rs1, int16_t imm12) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ GenInstrI(0b000, JALR, rd, rs1, imm12); ++ BlockTrampolinePoolFor(1); ++} ++ ++// Branches ++ ++void Assembler::beq(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b000, rs1, rs2, imm13); ++} ++ ++void Assembler::bne(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b001, rs1, rs2, imm13); ++} ++ ++void Assembler::blt(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b100, rs1, rs2, imm13); ++} ++ ++void Assembler::bge(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b101, rs1, rs2, imm13); ++} ++ ++void Assembler::bltu(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b110, rs1, rs2, imm13); ++} ++ ++void Assembler::bgeu(Register rs1, Register rs2, int16_t imm13) { ++ GenInstrBranchCC_rri(0b111, rs1, rs2, imm13); ++} ++ ++// Loads ++ ++void Assembler::lb(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b000, rd, rs1, imm12); ++} ++ ++void Assembler::lh(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b001, rd, rs1, imm12); ++} ++ ++void Assembler::lw(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b010, rd, rs1, imm12); ++} ++ ++void Assembler::lbu(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b100, rd, rs1, imm12); ++} ++ ++void Assembler::lhu(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b101, rd, rs1, imm12); ++} ++ ++// Stores ++ ++void Assembler::sb(Register source, Register base, int16_t imm12) { ++ GenInstrStore_rri(0b000, base, source, imm12); ++} ++ ++void Assembler::sh(Register source, Register base, int16_t imm12) { ++ GenInstrStore_rri(0b001, base, source, imm12); ++} ++ ++void Assembler::sw(Register source, Register base, int16_t imm12) { ++ GenInstrStore_rri(0b010, base, source, imm12); ++} ++ ++// Arithmetic with immediate ++ ++void Assembler::addi(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b000, rd, rs1, imm12); ++} ++ ++void Assembler::slti(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b010, rd, rs1, imm12); ++} ++ ++void Assembler::sltiu(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b011, rd, rs1, imm12); ++} ++ ++void Assembler::xori(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b100, rd, rs1, imm12); ++} ++ ++void Assembler::ori(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b110, rd, rs1, imm12); ++} ++ ++void Assembler::andi(Register rd, Register rs1, int16_t imm12) { ++ GenInstrALU_ri(0b111, rd, rs1, imm12); ++} ++ ++void Assembler::slli(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShift_ri(0, 0b001, rd, rs1, shamt & 0x3f); ++} ++ ++void Assembler::srli(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShift_ri(0, 0b101, rd, rs1, shamt & 0x3f); ++} ++ ++void Assembler::srai(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShift_ri(1, 0b101, rd, rs1, shamt & 0x3f); ++} ++ ++// Arithmetic ++ ++void Assembler::add(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::sub(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0100000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::sll(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::slt(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::sltu(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::xor_(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b100, rd, rs1, rs2); ++} ++ ++void Assembler::srl(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b101, rd, rs1, rs2); ++} ++ ++void Assembler::sra(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0100000, 0b101, rd, rs1, rs2); ++} ++ ++void Assembler::or_(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b110, rd, rs1, rs2); ++} ++ ++void Assembler::and_(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000000, 0b111, rd, rs1, rs2); ++} ++ ++// Memory fences ++ ++void Assembler::fence(uint8_t pred, uint8_t succ) { ++ DCHECK(is_uint4(pred) && is_uint4(succ)); ++ uint16_t imm12 = succ | (pred << 4) | (0b0000 << 8); ++ GenInstrI(0b000, MISC_MEM, ToRegister(0), ToRegister(0), imm12); ++} ++ ++void Assembler::fence_tso() { ++ uint16_t imm12 = (0b0011) | (0b0011 << 4) | (0b1000 << 8); ++ GenInstrI(0b000, MISC_MEM, ToRegister(0), ToRegister(0), imm12); ++} ++ ++// Environment call / break ++ ++void Assembler::ecall() { ++ GenInstrI(0b000, SYSTEM, ToRegister(0), ToRegister(0), 0); ++} ++ ++void Assembler::ebreak() { ++ GenInstrI(0b000, SYSTEM, ToRegister(0), ToRegister(0), 1); ++} ++ ++// This is a de facto standard (as set by GNU binutils) 32-bit unimplemented ++// instruction (i.e., it should always trap, if your implementation has invalid ++// instruction traps). ++void Assembler::unimp() { ++ GenInstrI(0b001, SYSTEM, ToRegister(0), ToRegister(0), 0b110000000000); ++} ++ ++// CSR ++ ++void Assembler::csrrw(Register rd, ControlStatusReg csr, Register rs1) { ++ GenInstrCSR_ir(0b001, rd, csr, rs1); ++} ++ ++void Assembler::csrrs(Register rd, ControlStatusReg csr, Register rs1) { ++ GenInstrCSR_ir(0b010, rd, csr, rs1); ++} ++ ++void Assembler::csrrc(Register rd, ControlStatusReg csr, Register rs1) { ++ GenInstrCSR_ir(0b011, rd, csr, rs1); ++} ++ ++void Assembler::csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5) { ++ GenInstrCSR_ii(0b101, rd, csr, imm5); ++} ++ ++void Assembler::csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5) { ++ GenInstrCSR_ii(0b110, rd, csr, imm5); ++} ++ ++void Assembler::csrrci(Register rd, ControlStatusReg csr, uint8_t imm5) { ++ GenInstrCSR_ii(0b111, rd, csr, imm5); ++} ++ ++// RV64I ++ ++void Assembler::lwu(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b110, rd, rs1, imm12); ++} ++ ++void Assembler::ld(Register rd, Register rs1, int16_t imm12) { ++ GenInstrLoad_ri(0b011, rd, rs1, imm12); ++} ++ ++void Assembler::sd(Register source, Register base, int16_t imm12) { ++ GenInstrStore_rri(0b011, base, source, imm12); ++} ++ ++void Assembler::addiw(Register rd, Register rs1, int16_t imm12) { ++ GenInstrI(0b000, OP_IMM_32, rd, rs1, imm12); ++} ++ ++void Assembler::slliw(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShiftW_ri(0, 0b001, rd, rs1, shamt & 0x1f); ++} ++ ++void Assembler::srliw(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShiftW_ri(0, 0b101, rd, rs1, shamt & 0x1f); ++} ++ ++void Assembler::sraiw(Register rd, Register rs1, uint8_t shamt) { ++ GenInstrShiftW_ri(1, 0b101, rd, rs1, shamt & 0x1f); ++} ++ ++void Assembler::addw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::subw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0100000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::sllw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000000, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::srlw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000000, 0b101, rd, rs1, rs2); ++} ++ ++void Assembler::sraw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0100000, 0b101, rd, rs1, rs2); ++} ++ ++// RV32M Standard Extension ++ ++void Assembler::mul(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::mulh(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::mulhsu(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::mulhu(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::div(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2); ++} ++ ++void Assembler::divu(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2); ++} ++ ++void Assembler::rem(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2); ++} ++ ++void Assembler::remu(Register rd, Register rs1, Register rs2) { ++ GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2); ++} ++ ++// RV64M Standard Extension (in addition to RV32M) ++ ++void Assembler::mulw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::divw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2); ++} ++ ++void Assembler::divuw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2); ++} ++ ++void Assembler::remw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2); ++} ++ ++void Assembler::remuw(Register rd, Register rs1, Register rs2) { ++ GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2); ++} ++ ++// RV32A Standard Extension ++ ++void Assembler::lr_w(bool aq, bool rl, Register rd, Register rs1) { ++ GenInstrRAtomic(0b00010, aq, rl, 0b010, rd, rs1, zero_reg); ++} ++ ++void Assembler::sc_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00011, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amoswap_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00001, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amoadd_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00000, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amoxor_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00100, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amoand_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b01100, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amoor_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b01000, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amomin_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b10000, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amomax_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b10100, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amominu_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b11000, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::amomaxu_w(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b11100, aq, rl, 0b010, rd, rs1, rs2); ++} ++ ++// RV64A Standard Extension (in addition to RV32A) ++ ++void Assembler::lr_d(bool aq, bool rl, Register rd, Register rs1) { ++ GenInstrRAtomic(0b00010, aq, rl, 0b011, rd, rs1, zero_reg); ++} ++ ++void Assembler::sc_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00011, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amoswap_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00001, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amoadd_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00000, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amoxor_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b00100, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amoand_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b01100, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amoor_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b01000, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amomin_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b10000, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amomax_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b10100, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amominu_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b11000, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++void Assembler::amomaxu_d(bool aq, bool rl, Register rd, Register rs1, ++ Register rs2) { ++ GenInstrRAtomic(0b11100, aq, rl, 0b011, rd, rs1, rs2); ++} ++ ++// RV32F Standard Extension ++ ++void Assembler::flw(FPURegister rd, Register rs1, int16_t imm12) { ++ GenInstrLoadFP_ri(0b010, rd, rs1, imm12); ++} ++ ++void Assembler::fsw(FPURegister source, Register base, int16_t imm12) { ++ GenInstrStoreFP_rri(0b010, base, source, imm12); ++} ++ ++void Assembler::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b0101100, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010000, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010000, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010100, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100000, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(1)); ++} ++ ++void Assembler::fmv_x_w(Register rd, FPURegister rs1) { ++ GenInstrALUFP_rr(0b1110000, 0b000, rd, rs1, zero_reg); ++} ++ ++void Assembler::feq_s(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010000, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::flt_s(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010000, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fle_s(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010000, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fclass_s(Register rd, FPURegister rs1) { ++ GenInstrALUFP_rr(0b1110000, 0b001, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101000, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(1)); ++} ++ ++void Assembler::fmv_w_x(FPURegister rd, Register rs1) { ++ GenInstrALUFP_rr(0b1111000, 0b000, rd, rs1, zero_reg); ++} ++ ++// RV64F Standard Extension (in addition to RV32F) ++ ++void Assembler::fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(2)); ++} ++ ++void Assembler::fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(3)); ++} ++ ++void Assembler::fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(2)); ++} ++ ++void Assembler::fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(3)); ++} ++ ++// RV32D Standard Extension ++ ++void Assembler::fld(FPURegister rd, Register rs1, int16_t imm12) { ++ GenInstrLoadFP_ri(0b011, rd, rs1, imm12); ++} ++ ++void Assembler::fsd(FPURegister source, Register base, int16_t imm12) { ++ GenInstrStoreFP_rri(0b011, base, source, imm12); ++} ++ ++void Assembler::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm) { ++ GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm); ++} ++ ++void Assembler::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm) { ++ GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2); ++} ++ ++void Assembler::fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b0101101, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010001, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010001, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010001, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010101, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b0100000, frm, rd, rs1, ToRegister(1)); ++} ++ ++void Assembler::fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b0100001, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::feq_d(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010001, 0b010, rd, rs1, rs2); ++} ++ ++void Assembler::flt_d(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010001, 0b001, rd, rs1, rs2); ++} ++ ++void Assembler::fle_d(Register rd, FPURegister rs1, FPURegister rs2) { ++ GenInstrALUFP_rr(0b1010001, 0b000, rd, rs1, rs2); ++} ++ ++void Assembler::fclass_d(Register rd, FPURegister rs1) { ++ GenInstrALUFP_rr(0b1110001, 0b001, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100001, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(1)); ++} ++ ++void Assembler::fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101001, frm, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(1)); ++} ++ ++// RV64D Standard Extension (in addition to RV32D) ++ ++void Assembler::fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(2)); ++} ++ ++void Assembler::fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(3)); ++} ++ ++void Assembler::fmv_x_d(Register rd, FPURegister rs1) { ++ GenInstrALUFP_rr(0b1110001, 0b000, rd, rs1, zero_reg); ++} ++ ++void Assembler::fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(2)); ++} ++ ++void Assembler::fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm) { ++ GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(3)); ++} ++ ++void Assembler::fmv_d_x(FPURegister rd, Register rs1) { ++ GenInstrALUFP_rr(0b1111001, 0b000, rd, rs1, zero_reg); ++} ++ ++// Privileged ++ ++void Assembler::uret() { ++ GenInstrPriv(0b0000000, ToRegister(0), ToRegister(0b00010)); ++} ++ ++void Assembler::sret() { ++ GenInstrPriv(0b0001000, ToRegister(0), ToRegister(0b00010)); ++} ++ ++void Assembler::mret() { ++ GenInstrPriv(0b0011000, ToRegister(0), ToRegister(0b00010)); ++} ++ ++void Assembler::wfi() { ++ GenInstrPriv(0b0001000, ToRegister(0), ToRegister(0b00101)); ++} ++ ++void Assembler::sfence_vma(Register rs1, Register rs2) { ++ GenInstrR(0b0001001, 0b000, SYSTEM, ToRegister(0), rs1, rs2); ++} ++ ++// Assembler Pseudo Instructions (Tables 25.2 and 25.3, RISC-V Unprivileged ISA) ++ ++void Assembler::nop() { addi(ToRegister(0), ToRegister(0), 0); } ++ ++void Assembler::RV_li(Register rd, int64_t imm) { ++ // 64-bit imm is put in the register rd. ++ // In most cases the imm is 32 bit and 2 instructions are generated. If a ++ // temporary register is available, in the worst case, 6 instructions are ++ // generated for a full 64-bit immediate. If temporay register is not ++ // available the maximum will be 8 instructions. If imm is more than 32 bits ++ // and a temp register is available, imm is divided into two 32-bit parts, ++ // low_32 and up_32. Each part is built in a separate register. low_32 is ++ // built before up_32. If low_32 is negative (upper 32 bits are 1), 0xffffffff ++ // is subtracted from up_32 before up_32 is built. This compensates for 32 ++ // bits of 1's in the lower when the two registers are added. If no temp is ++ // available, the upper 32 bit is built in rd, and the lower 32 bits are ++ // devided to 3 parts (11, 11, and 10 bits). The parts are shifted and added ++ // to the upper part built in rd. ++ if (is_int32(imm + 0x800)) { ++ // 32-bit case. Maximum of 2 instructions generated ++ int64_t high_20 = ((imm + 0x800) >> 12); ++ int64_t low_12 = imm << 52 >> 52; ++ if (high_20) { ++ lui(rd, (int32_t)high_20); ++ if (low_12) { ++ addi(rd, rd, low_12); ++ } ++ } else { ++ addi(rd, zero_reg, low_12); ++ } ++ return; ++ } else { ++ // 64-bit case: divide imm into two 32-bit parts, upper and lower ++ int64_t up_32 = imm >> 32; ++ int64_t low_32 = imm & 0xffffffffull; ++ Register temp_reg = rd; ++ // Check if a temporary register is available ++ if (up_32 == 0 || low_32 == 0) { ++ // No temp register is needed ++ } else { ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ temp_reg = temps.hasAvailable() ? temps.Acquire() : no_reg; ++ } ++ if (temp_reg != no_reg) { ++ // keep track of hardware behavior for lower part in sim_low ++ int64_t sim_low = 0; ++ // Build lower part ++ if (low_32 != 0) { ++ int64_t high_20 = ((low_32 + 0x800) >> 12); ++ int64_t low_12 = low_32 & 0xfff; ++ if (high_20) { ++ // Adjust to 20 bits for the case of overflow ++ high_20 &= 0xfffff; ++ sim_low = ((high_20 << 12) << 32) >> 32; ++ lui(rd, (int32_t)high_20); ++ if (low_12) { ++ sim_low += (low_12 << 52 >> 52) | low_12; ++ addi(rd, rd, low_12); ++ } ++ } else { ++ sim_low = low_12; ++ ori(rd, zero_reg, low_12); ++ } ++ } ++ if (sim_low & 0x100000000) { ++ // Bit 31 is 1. Either an overflow or a negative 64 bit ++ if (up_32 == 0) { ++ // Positive number, but overflow because of the add 0x800 ++ slli(rd, rd, 32); ++ srli(rd, rd, 32); ++ return; ++ } ++ // low_32 is a negative 64 bit after the build ++ up_32 = (up_32 - 0xffffffff) & 0xffffffff; ++ } ++ if (up_32 == 0) { ++ return; ++ } ++ // Build upper part in a temporary register ++ if (low_32 == 0) { ++ // Build upper part in rd ++ temp_reg = rd; ++ } ++ int64_t high_20 = (up_32 + 0x800) >> 12; ++ int64_t low_12 = up_32 & 0xfff; ++ if (high_20) { ++ // Adjust to 20 bits for the case of overflow ++ high_20 &= 0xfffff; ++ lui(temp_reg, (int32_t)high_20); ++ if (low_12) { ++ addi(temp_reg, temp_reg, low_12); ++ } ++ } else { ++ ori(temp_reg, zero_reg, low_12); ++ } ++ // Put it at the bgining of register ++ slli(temp_reg, temp_reg, 32); ++ if (low_32 != 0) { ++ add(rd, rd, temp_reg); ++ } ++ return; ++ } ++ // No temp register. Build imm in rd. ++ // Build upper 32 bits first in rd. Divide lower 32 bits parts and add ++ // parts to the upper part by doing shift and add. ++ // First build upper part in rd. ++ int64_t high_20 = (up_32 + 0x800) >> 12; ++ int64_t low_12 = up_32 & 0xfff; ++ if (high_20) { ++ // Adjust to 20 bits for the case of overflow ++ high_20 &= 0xfffff; ++ lui(rd, (int32_t)high_20); ++ if (low_12) { ++ addi(rd, rd, low_12); ++ } ++ } else { ++ ori(rd, zero_reg, low_12); ++ } ++ // upper part already in rd. Each part to be added to rd, has maximum of 11 ++ // bits, and always starts with a 1. rd is shifted by the size of the part ++ // plus the number of zeros between the parts. Each part is added after the ++ // left shift. ++ uint32_t mask = 0x80000000; ++ int32_t shift_val = 0; ++ int32_t i; ++ for (i = 0; i < 32; i++) { ++ if ((low_32 & mask) == 0) { ++ mask >>= 1; ++ shift_val++; ++ if (i == 31) { ++ // rest is zero ++ slli(rd, rd, shift_val); ++ } ++ continue; ++ } ++ // The first 1 seen ++ int32_t part; ++ if ((i + 11) < 32) { ++ // Pick 11 bits ++ part = ((uint32_t)(low_32 << i) >> i) >> (32 - (i + 11)); ++ slli(rd, rd, shift_val + 11); ++ ori(rd, rd, part); ++ i += 10; ++ mask >>= 11; ++ } else { ++ part = (uint32_t)(low_32 << i) >> i; ++ slli(rd, rd, shift_val + (32 - i)); ++ ori(rd, rd, part); ++ break; ++ } ++ shift_val = 0; ++ } ++ } ++} ++ ++int Assembler::li_count(int64_t imm) { ++ int count = 0; ++ if (is_int32(imm + 0x800)) { ++ int64_t Hi20 = ((imm + 0x800) >> 12); ++ int64_t Lo12 = imm << 52 >> 52; ++ ++ if (Hi20) count++; ++ ++ if (Lo12 || Hi20 == 0) count++; ++ return count; ++ } ++ ++ int64_t Lo12 = imm << 52 >> 52; ++ int64_t Hi52 = ((uint64_t)imm + 0x800ull) >> 12; ++ int FirstBit = 0; ++ uint64_t Val = Hi52; ++ while ((Val & 1) == 0) { ++ Val = Val >> 1; ++ FirstBit++; ++ } ++ int ShiftAmount = 12 + FirstBit; ++ Hi52 = (Hi52 >> (ShiftAmount - 12)) << ShiftAmount >> ShiftAmount; ++ ++ count += li_count(Hi52); ++ ++ count++; ++ if (Lo12) count++; ++ ++ return count; ++} ++ ++void Assembler::li_constant(Register rd, int64_t imm) { ++ DEBUG_PRINTF("li_constant(%d, %lx <%ld>)\n", ToNumber(rd), imm, imm); ++ lui(rd, (imm + (1LL << 47) + (1LL << 35) + (1LL << 23) + (1LL << 11)) >> ++ 48); // Bits 63:48 ++ addiw(rd, rd, ++ (imm + (1LL << 35) + (1LL << 23) + (1LL << 11)) << 16 >> ++ 52); // Bits 47:36 ++ slli(rd, rd, 12); ++ addi(rd, rd, (imm + (1LL << 23) + (1LL << 11)) << 28 >> 52); // Bits 35:24 ++ slli(rd, rd, 12); ++ addi(rd, rd, (imm + (1LL << 11)) << 40 >> 52); // Bits 23:12 ++ slli(rd, rd, 12); ++ addi(rd, rd, imm << 52 >> 52); // Bits 11:0 ++} ++ ++// Break / Trap instructions. ++void Assembler::break_(uint32_t code, bool break_as_stop) { ++ // We need to invalidate breaks that could be stops as well because the ++ // simulator expects a char pointer after the stop instruction. ++ // See constants-mips.h for explanation. ++ DCHECK( ++ (break_as_stop && code <= kMaxStopCode && code > kMaxWatchpointCode) || ++ (!break_as_stop && (code > kMaxStopCode || code <= kMaxWatchpointCode))); ++ ++ // since ebreak does not allow additional immediate field, we use the ++ // immediate field of lui instruction immediately following the ebreak to ++ // encode the "code" info ++ ebreak(); ++ DCHECK(is_uint20(code)); ++ lui(zero_reg, code); ++} ++ ++void Assembler::stop(uint32_t code) { ++ DCHECK_GT(code, kMaxWatchpointCode); ++ DCHECK_LE(code, kMaxStopCode); ++#if defined(V8_HOST_ARCH_RISCV64) ++ // FIXME: does RISCV expect a special value? ++ break_(0x54321); ++#else // V8_HOST_ARCH_RISCV64 ++ break_(code, true); ++#endif ++} ++ ++// Original MIPS Instructions ++ ++// ------------Memory-instructions------------- ++ ++bool Assembler::NeedAdjustBaseAndOffset(const MemOperand& src, ++ OffsetAccessType access_type, ++ int second_access_add_to_offset) { ++ bool two_accesses = static_cast(access_type); ++ DCHECK_LE(second_access_add_to_offset, 7); // Must be <= 7. ++ ++ // is_int12 must be passed a signed value, hence the static cast below. ++ if (is_int12(src.offset()) && ++ (!two_accesses || is_int12(static_cast( ++ src.offset() + second_access_add_to_offset)))) { ++ // Nothing to do: 'offset' (and, if needed, 'offset + 4', or other specified ++ // value) fits into int12. ++ return false; ++ } ++ return true; ++} ++ ++void Assembler::AdjustBaseAndOffset(MemOperand* src, Register scratch, ++ OffsetAccessType access_type, ++ int second_Access_add_to_offset) { ++ // This method is used to adjust the base register and offset pair ++ // for a load/store when the offset doesn't fit into int12. ++ ++ // Must not overwrite the register 'base' while loading 'offset'. ++ DCHECK(src->rm() != scratch); ++ ++ // FIXME(RISC-V): There may be a more optimal way to do this ++ RV_li(scratch, src->offset()); ++ add(scratch, scratch, src->rm()); ++ src->offset_ = 0; ++ src->rm_ = scratch; ++} ++ ++// FIXME (RISCV): not yet ported (or not used?) ++int Assembler::RelocateInternalReference(RelocInfo::Mode rmode, Address pc, ++ intptr_t pc_delta) { ++ if (RelocInfo::IsInternalReference(rmode)) { ++ int64_t* p = reinterpret_cast(pc); ++ if (*p == kEndOfJumpChain) { ++ return 0; // Number of instructions patched. ++ } ++ *p += pc_delta; ++ return 2; // Number of instructions patched. ++ } ++ Instr instr = instr_at(pc); ++ DCHECK(RelocInfo::IsInternalReferenceEncoded(rmode)); ++ if (IsLui(instr)) { ++ uint64_t target_address = target_address_at(pc) + pc_delta; ++ DEBUG_PRINTF("target_address 0x%lx\n", target_address); ++ set_target_value_at(pc, target_address); ++ return 8; // Number of instructions patched. ++ } else { ++ UNIMPLEMENTED(); ++ return 1; ++ } ++} ++ ++void Assembler::GrowBuffer() { ++ DEBUG_PRINTF("GrowBuffer: %p -> ", buffer_start_); ++ // Compute new buffer size. ++ int old_size = buffer_->size(); ++ int new_size = std::min(2 * old_size, old_size + 1 * MB); ++ ++ // Some internal data structures overflow for very large buffers, ++ // they must ensure that kMaximalBufferSize is not too large. ++ if (new_size > kMaximalBufferSize) { ++ V8::FatalProcessOutOfMemory(nullptr, "Assembler::GrowBuffer"); ++ } ++ ++ // Set up new buffer. ++ std::unique_ptr new_buffer = buffer_->Grow(new_size); ++ DCHECK_EQ(new_size, new_buffer->size()); ++ byte* new_start = new_buffer->start(); ++ ++ // Copy the data. ++ intptr_t pc_delta = new_start - buffer_start_; ++ intptr_t rc_delta = (new_start + new_size) - (buffer_start_ + old_size); ++ size_t reloc_size = (buffer_start_ + old_size) - reloc_info_writer.pos(); ++ MemMove(new_start, buffer_start_, pc_offset()); ++ MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(), ++ reloc_size); ++ ++ // Switch buffers. ++ buffer_ = std::move(new_buffer); ++ buffer_start_ = new_start; ++ DEBUG_PRINTF("%p\n", buffer_start_); ++ pc_ += pc_delta; ++ reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, ++ reloc_info_writer.last_pc() + pc_delta); ++ ++ // Relocate runtime entries. ++ Vector instructions{buffer_start_, (size_t)pc_offset()}; ++ Vector reloc_info{reloc_info_writer.pos(), reloc_size}; ++ for (RelocIterator it(instructions, reloc_info, 0); !it.done(); it.next()) { ++ RelocInfo::Mode rmode = it.rinfo()->rmode(); ++ if (rmode == RelocInfo::INTERNAL_REFERENCE) { ++ RelocateInternalReference(rmode, it.rinfo()->pc(), pc_delta); ++ } ++ } ++ DCHECK(!overflow()); ++} ++ ++void Assembler::db(uint8_t data) { ++ if (!is_buffer_growth_blocked()) CheckBuffer(); ++ EmitHelper(data); ++} ++ ++void Assembler::dd(uint32_t data) { ++ if (!is_buffer_growth_blocked()) CheckBuffer(); ++ EmitHelper(data); ++} ++ ++void Assembler::dq(uint64_t data) { ++ if (!is_buffer_growth_blocked()) CheckBuffer(); ++ EmitHelper(data); ++} ++ ++void Assembler::dd(Label* label) { ++ uint64_t data; ++ if (!is_buffer_growth_blocked()) CheckBuffer(); ++ if (label->is_bound()) { ++ data = reinterpret_cast(buffer_start_ + label->pos()); ++ } else { ++ data = jump_address(label); ++ internal_reference_positions_.insert(label->pos()); ++ } ++ RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE); ++ EmitHelper(data); ++} ++ ++void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { ++ if (!ShouldRecordRelocInfo(rmode)) return; ++ // We do not try to reuse pool constants. ++ RelocInfo rinfo(reinterpret_cast
(pc_), rmode, data, Code()); ++ DCHECK_GE(buffer_space(), kMaxRelocSize); // Too late to grow buffer here. ++ reloc_info_writer.Write(&rinfo); ++} ++ ++void Assembler::BlockTrampolinePoolFor(int instructions) { ++ CheckTrampolinePoolQuick(instructions); ++ BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize); ++} ++ ++void Assembler::CheckTrampolinePool() { ++ // Some small sequences of instructions must not be broken up by the ++ // insertion of a trampoline pool; such sequences are protected by setting ++ // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_, ++ // which are both checked here. Also, recursive calls to CheckTrampolinePool ++ // are blocked by trampoline_pool_blocked_nesting_. ++ if ((trampoline_pool_blocked_nesting_ > 0) || ++ (pc_offset() < no_trampoline_pool_before_)) { ++ // Emission is currently blocked; make sure we try again as soon as ++ // possible. ++ if (trampoline_pool_blocked_nesting_ > 0) { ++ next_buffer_check_ = pc_offset() + kInstrSize; ++ } else { ++ next_buffer_check_ = no_trampoline_pool_before_; ++ } ++ return; ++ } ++ ++ DCHECK(!trampoline_emitted_); ++ DCHECK_GE(unbound_labels_count_, 0); ++ if (unbound_labels_count_ > 0) { ++ // First we emit jump, then we emit trampoline pool. ++ { ++ DEBUG_PRINTF("inserting trampoline pool at %p (%d)\n", ++ reinterpret_cast(buffer_start_ + pc_offset()), ++ pc_offset()); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Label after_pool; ++ j(&after_pool); ++ ++ int pool_start = pc_offset(); ++ for (int i = 0; i < unbound_labels_count_; i++) { ++ int64_t imm64; ++ imm64 = branch_long_offset(&after_pool); ++ DCHECK(is_int32(imm64)); ++ int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12); ++ int32_t Lo12 = (int32_t)imm64 << 20 >> 20; ++ auipc(t5, Hi20); // Read PC + Hi20 into t5. ++ jr(t5, Lo12); // jump PC + Hi20 + Lo12 ++ } ++ // If unbound_labels_count_ is big enough, label after_pool will ++ // need a trampoline too, so we must create the trampoline before ++ // the bind operation to make sure function 'bind' can get this ++ // information. ++ trampoline_ = Trampoline(pool_start, unbound_labels_count_); ++ bind(&after_pool); ++ ++ trampoline_emitted_ = true; ++ // As we are only going to emit trampoline once, we need to prevent any ++ // further emission. ++ next_buffer_check_ = kMaxInt; ++ } ++ } else { ++ // Number of branches to unbound label at this point is zero, so we can ++ // move next buffer check to maximum. ++ next_buffer_check_ = ++ pc_offset() + kMaxBranchOffset - kTrampolineSlotsSize * 16; ++ } ++ return; ++} ++ ++Address Assembler::target_address_at(Address pc) { ++ DEBUG_PRINTF("target_address_at: pc: %lx\t", pc); ++ Instruction* instr0 = Instruction::At((unsigned char*)pc); ++ Instruction* instr1 = Instruction::At((unsigned char*)(pc + 1 * kInstrSize)); ++ Instruction* instr3 = Instruction::At((unsigned char*)(pc + 3 * kInstrSize)); ++ Instruction* instr5 = Instruction::At((unsigned char*)(pc + 5 * kInstrSize)); ++ Instruction* instr7 = Instruction::At((unsigned char*)(pc + 7 * kInstrSize)); ++ ++ // Interpret 5 instructions for address generated by li: See listing in ++ // Assembler::set_target_address_at() just below. ++ if (IsLui(*reinterpret_cast(instr0)) && ++ IsAddiw(*reinterpret_cast(instr1)) && ++ IsAddi(*reinterpret_cast(instr3)) && ++ IsAddi(*reinterpret_cast(instr5)) && ++ IsAddi(*reinterpret_cast(instr7))) { ++ // Assemble the 64 bit value. ++ int64_t addr = (int64_t)(instr0->Imm20UValue() << kImm20Shift) + ++ (int64_t)instr1->Imm12Value(); ++ addr <<= 12; ++ addr += (int64_t)instr3->Imm12Value(); ++ addr <<= 12; ++ addr += (int64_t)instr5->Imm12Value(); ++ addr <<= 12; ++ addr += (int64_t)instr7->Imm12Value(); ++ ++ DEBUG_PRINTF("addr: %lx\n", addr); ++ return static_cast
(addr); ++ } ++ // We should never get here, force a bad address if we do. ++ UNREACHABLE(); ++} ++ ++// On RISC-V, a 64-bit target address is stored in an 8-instruction sequence: ++// 0: lui(rd, (j.imm64_ + (1LL << 47) + (1LL << 35) + ++// (1LL << 23) + (1LL << 11)) >> 48); ++// 1: addiw(rd, rd, (j.imm64_ + (1LL << 35) + (1LL << 23) + (1LL << 11)) ++// << 16 >> 52); ++// 2: slli(rd, rd, 12); ++// 3: addi(rd, rd, (j.imm64_ + (1LL << 23) + (1LL << 11)) << 28 >> 52); ++// 4: slli(rd, rd, 12); ++// 5: addi(rd, rd, (j.imm64_ + (1 << 11)) << 40 >> 52); ++// 6: slli(rd, rd, 12); ++// 7: addi(rd, rd, j.imm64_ << 52 >> 52); ++// ++// Patching the address must replace all the lui & addi instructions, ++// and flush the i-cache. ++void Assembler::set_target_value_at(Address pc, uint64_t target, ++ ICacheFlushMode icache_flush_mode) { ++ // FIXME(RISC-V): Does the below statement apply to RISC-V? If so, we do not ++ // need all 8 instructions. ++ // There is an optimization where only 4 instructions are used to load address ++ // in code on MIP64 because only 48-bits of address is effectively used. ++ // It relies on fact the upper [63:48] bits are not used for virtual address ++ // translation and they have to be set according to value of bit 47 in order ++ // get canonical address. ++ Instruction* instr0 = Instruction::At((unsigned char*)pc); ++ DEBUG_PRINTF("set_target_value_at: pc: %lx\ttarget: %lx\n", pc, target); ++ int rd_code = instr0->RdValue(); ++ uint32_t* p = reinterpret_cast(pc); ++ ++#ifdef DEBUG ++ // Check we have the result from a li macro-instruction. ++ Instruction* instr1 = Instruction::At((unsigned char*)(pc + 1 * kInstrSize)); ++ Instruction* instr3 = Instruction::At((unsigned char*)(pc + 3 * kInstrSize)); ++ Instruction* instr5 = Instruction::At((unsigned char*)(pc + 5 * kInstrSize)); ++ Instruction* instr7 = Instruction::At((unsigned char*)(pc + 7 * kInstrSize)); ++ DCHECK(IsLui(*reinterpret_cast(instr0)) && ++ IsAddiw(*reinterpret_cast(instr1)) && ++ IsAddi(*reinterpret_cast(instr3)) && ++ IsAddi(*reinterpret_cast(instr5)) && ++ IsAddi(*reinterpret_cast(instr7))); ++#endif ++ ++ // Must use 8 instructions to insure patchable code (see above comment). ++ *p = LUI | (rd_code << kRdShift) | ++ ((uint32_t)( ++ (target + (1LL << 47) + (1LL << 35) + (1LL << 23) + (1LL << 11)) >> ++ 48) ++ << kImm20Shift); ++ *(p + 1) = ++ OP_IMM_32 | (rd_code << kRdShift) | (0b000 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | ++ ((uint32_t)((target + (1LL << 35) + (1LL << 23) + (1LL << 11)) << 16 >> ++ 52) ++ << kImm12Shift); ++ *(p + 2) = OP_IMM | (rd_code << kRdShift) | (0b001 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | (12 << kImm12Shift); ++ *(p + 3) = OP_IMM | (rd_code << kRdShift) | (0b000 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | ++ ((uint32_t)((target + (1LL << 23) + (1LL << 11)) << 28 >> 52) ++ << kImm12Shift); ++ *(p + 4) = OP_IMM | (rd_code << kRdShift) | (0b001 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | (12 << kImm12Shift); ++ *(p + 5) = OP_IMM | (rd_code << kRdShift) | (0b000 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | ++ ((uint32_t)((target + (1LL << 11)) << 40 >> 52) << kImm12Shift); ++ *(p + 6) = OP_IMM | (rd_code << kRdShift) | (0b001 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | (12 << kImm12Shift); ++ *(p + 7) = OP_IMM | (rd_code << kRdShift) | (0b000 << kFunct3Shift) | ++ (rd_code << kRs1Shift) | ++ ((uint32_t)(target << 52 >> 52) << kImm12Shift); ++ ++ if (icache_flush_mode != SKIP_ICACHE_FLUSH) { ++ FlushInstructionCache(pc, 8 * kInstrSize); ++ } ++ DCHECK_EQ(target_address_at(pc), target); ++} ++ ++UseScratchRegisterScope::UseScratchRegisterScope(Assembler* assembler) ++ : available_(assembler->GetScratchRegisterList()), ++ old_available_(*available_) {} ++ ++UseScratchRegisterScope::~UseScratchRegisterScope() { ++ *available_ = old_available_; ++} ++ ++Register UseScratchRegisterScope::Acquire() { ++ DCHECK_NOT_NULL(available_); ++ DCHECK_NE(*available_, 0); ++ int index = static_cast(base::bits::CountTrailingZeros32(*available_)); ++ *available_ &= ~(1UL << index); ++ ++ return Register::from_code(index); ++} ++ ++bool UseScratchRegisterScope::hasAvailable() const { return *available_ != 0; } ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/assembler-riscv64.h +@@ -0,0 +1,1110 @@ ++// Copyright (c) 1994-2006 Sun Microsystems Inc. ++// All Rights Reserved. ++// ++// Redistribution and use in source and binary forms, with or without ++// modification, are permitted provided that the following conditions are ++// met: ++// ++// - Redistributions of source code must retain the above copyright notice, ++// this list of conditions and the following disclaimer. ++// ++// - Redistribution in binary form must reproduce the above copyright ++// notice, this list of conditions and the following disclaimer in the ++// documentation and/or other materials provided with the distribution. ++// ++// - Neither the name of Sun Microsystems or the names of contributors may ++// be used to endorse or promote products derived from this software without ++// specific prior written permission. ++// ++// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ ++// The original source code covered by the above license above has been ++// modified significantly by Google Inc. ++// Copyright 2012 the V8 project authors. All rights reserved. ++ ++#ifndef V8_CODEGEN_RISCV_ASSEMBLER_RISCV_H_ ++#define V8_CODEGEN_RISCV_ASSEMBLER_RISCV_H_ ++ ++#include ++ ++#include ++#include ++ ++#include "src/codegen/assembler.h" ++#include "src/codegen/external-reference.h" ++#include "src/codegen/label.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/codegen/riscv64/register-riscv64.h" ++#include "src/objects/contexts.h" ++#include "src/objects/smi.h" ++ ++namespace v8 { ++namespace internal { ++ ++class SafepointTableBuilder; ++ ++// ----------------------------------------------------------------------------- ++// Machine instruction Operands. ++constexpr int kSmiShift = kSmiTagSize + kSmiShiftSize; ++constexpr uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1; ++// Class Operand represents a shifter operand in data processing instructions. ++class Operand { ++ public: ++ // Immediate. ++ V8_INLINE explicit Operand(int64_t immediate, ++ RelocInfo::Mode rmode = RelocInfo::NONE) ++ : rm_(no_reg), rmode_(rmode) { ++ value_.immediate = immediate; ++ } ++ V8_INLINE explicit Operand(const ExternalReference& f) ++ : rm_(no_reg), rmode_(RelocInfo::EXTERNAL_REFERENCE) { ++ value_.immediate = static_cast(f.address()); ++ } ++ V8_INLINE explicit Operand(const char* s); ++ explicit Operand(Handle handle); ++ V8_INLINE explicit Operand(Smi value) : rm_(no_reg), rmode_(RelocInfo::NONE) { ++ value_.immediate = static_cast(value.ptr()); ++ } ++ ++ static Operand EmbeddedNumber(double number); // Smi or HeapNumber. ++ static Operand EmbeddedStringConstant(const StringConstantBase* str); ++ ++ // Register. ++ V8_INLINE explicit Operand(Register rm) : rm_(rm) {} ++ ++ // Return true if this is a register operand. ++ V8_INLINE bool is_reg() const; ++ ++ inline int64_t immediate() const; ++ ++ bool IsImmediate() const { return !rm_.is_valid(); } ++ ++ HeapObjectRequest heap_object_request() const { ++ DCHECK(IsHeapObjectRequest()); ++ return value_.heap_object_request; ++ } ++ ++ bool IsHeapObjectRequest() const { ++ DCHECK_IMPLIES(is_heap_object_request_, IsImmediate()); ++ DCHECK_IMPLIES(is_heap_object_request_, ++ rmode_ == RelocInfo::FULL_EMBEDDED_OBJECT || ++ rmode_ == RelocInfo::CODE_TARGET); ++ return is_heap_object_request_; ++ } ++ ++ Register rm() const { return rm_; } ++ ++ RelocInfo::Mode rmode() const { return rmode_; } ++ ++ private: ++ Register rm_; ++ union Value { ++ Value() {} ++ HeapObjectRequest heap_object_request; // if is_heap_object_request_ ++ int64_t immediate; // otherwise ++ } value_; // valid if rm_ == no_reg ++ bool is_heap_object_request_ = false; ++ RelocInfo::Mode rmode_; ++ ++ friend class Assembler; ++ friend class MacroAssembler; ++}; ++ ++// On RISC-V we have only one addressing mode with base_reg + offset. ++// Class MemOperand represents a memory operand in load and store instructions. ++class V8_EXPORT_PRIVATE MemOperand : public Operand { ++ public: ++ // Immediate value attached to offset. ++ enum OffsetAddend { offset_minus_one = -1, offset_zero = 0 }; ++ ++ explicit MemOperand(Register rn, int32_t offset = 0); ++ explicit MemOperand(Register rn, int32_t unit, int32_t multiplier, ++ OffsetAddend offset_addend = offset_zero); ++ int32_t offset() const { return offset_; } ++ ++ bool OffsetIsInt12Encodable() const { return is_int12(offset_); } ++ ++ private: ++ int32_t offset_; ++ ++ friend class Assembler; ++}; ++ ++class V8_EXPORT_PRIVATE Assembler : public AssemblerBase { ++ public: ++ // Create an assembler. Instructions and relocation information are emitted ++ // into a buffer, with the instructions starting from the beginning and the ++ // relocation information starting from the end of the buffer. See CodeDesc ++ // for a detailed comment on the layout (globals.h). ++ // ++ // If the provided buffer is nullptr, the assembler allocates and grows its ++ // own buffer. Otherwise it takes ownership of the provided buffer. ++ explicit Assembler(const AssemblerOptions&, ++ std::unique_ptr = {}); ++ ++ virtual ~Assembler() {} ++ ++ // GetCode emits any pending (non-emitted) code and fills the descriptor desc. ++ static constexpr int kNoHandlerTable = 0; ++ static constexpr SafepointTableBuilder* kNoSafepointTable = nullptr; ++ void GetCode(Isolate* isolate, CodeDesc* desc, ++ SafepointTableBuilder* safepoint_table_builder, ++ int handler_table_offset); ++ ++ // Convenience wrapper for code without safepoint or handler tables. ++ void GetCode(Isolate* isolate, CodeDesc* desc) { ++ GetCode(isolate, desc, kNoSafepointTable, kNoHandlerTable); ++ } ++ ++ // Unused on this architecture. ++ void MaybeEmitOutOfLineConstantPool() {} ++ ++ // Label operations & relative jumps (PPUM Appendix D). ++ // ++ // Takes a branch opcode (cc) and a label (L) and generates ++ // either a backward branch or a forward branch and links it ++ // to the label fixup chain. Usage: ++ // ++ // Label L; // unbound label ++ // j(cc, &L); // forward branch to unbound label ++ // bind(&L); // bind label to the current pc ++ // j(cc, &L); // backward branch to bound label ++ // bind(&L); // illegal: a label may be bound only once ++ // ++ // Note: The same Label can be used for forward and backward branches ++ // but it may be bound only once. ++ void bind(Label* L); // Binds an unbound label L to current code position. ++ ++ enum OffsetSize : int { ++ kOffset21 = 21, // RISCV jal ++ kOffset12 = 12, // RISCV imm12 ++ kOffset20 = 20, // RISCV imm20 ++ kOffset13 = 13 // RISCV branch ++ }; ++ ++ // Determines if Label is bound and near enough so that branch instruction ++ // can be used to reach it, instead of jump instruction. ++ bool is_near(Label* L); ++ bool is_near(Label* L, OffsetSize bits); ++ bool is_near_branch(Label* L); ++ ++ //Get offset from instr. ++ int BranchOffset(Instr instr); ++ int BrachlongOffset(Instr auipc, Instr jalr); ++ int JumpOffset(Instr instr); ++ ++ // Returns the branch offset to the given label from the current code ++ // position. Links the label to the current position if it is still unbound. ++ // Manages the jump elimination optimization if the second parameter is true. ++ int32_t branch_offset_helper(Label* L, OffsetSize bits); ++ inline int32_t branch_offset(Label* L) { ++ return branch_offset_helper(L, OffsetSize::kOffset13); ++ } ++ inline int32_t jump_offset(Label* L) { ++ return branch_offset_helper(L, OffsetSize::kOffset21); ++ } ++ ++ uint64_t jump_address(Label* L); ++ uint64_t branch_long_offset(Label* L); ++ ++ // Puts a labels target address at the given position. ++ // The high 8 bits are set to zero. ++ void label_at_put(Label* L, int at_offset); ++ ++ // Read/Modify the code target address in the branch/call instruction at pc. ++ // The isolate argument is unused (and may be nullptr) when skipping flushing. ++ static Address target_address_at(Address pc); ++ V8_INLINE static void set_target_address_at( ++ Address pc, Address target, ++ ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { ++ set_target_value_at(pc, target, icache_flush_mode); ++ } ++ // On RISC-V there is no Constant Pool so we skip that parameter. ++ V8_INLINE static Address target_address_at(Address pc, ++ Address constant_pool) { ++ return target_address_at(pc); ++ } ++ V8_INLINE static void set_target_address_at( ++ Address pc, Address constant_pool, Address target, ++ ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED) { ++ set_target_address_at(pc, target, icache_flush_mode); ++ } ++ ++ static void set_target_value_at( ++ Address pc, uint64_t target, ++ ICacheFlushMode icache_flush_mode = FLUSH_ICACHE_IF_NEEDED); ++ ++ static void JumpLabelToJumpRegister(Address pc); ++ ++ // This sets the branch destination (which gets loaded at the call address). ++ // This is for calls and branches within generated code. The serializer ++ // has already deserialized the lui/ori instructions etc. ++ inline static void deserialization_set_special_target_at( ++ Address instruction_payload, Code code, Address target); ++ ++ // Get the size of the special target encoded at 'instruction_payload'. ++ inline static int deserialization_special_target_size( ++ Address instruction_payload); ++ ++ // This sets the internal reference at the pc. ++ inline static void deserialization_set_target_internal_reference_at( ++ Address pc, Address target, ++ RelocInfo::Mode mode = RelocInfo::INTERNAL_REFERENCE); ++ ++ // Difference between address of current opcode and target address offset. ++ static constexpr int kBranchPCOffset = kInstrSize; ++ ++ // Difference between address of current opcode and target address offset, ++ // when we are generatinga sequence of instructions for long relative PC ++ // branches ++ static constexpr int kLongBranchPCOffset = 3 * kInstrSize; ++ ++ // Adjust ra register in branch delay slot of bal instruction so to skip ++ // instructions not needed after optimization of PIC in ++ // TurboAssembler::BranchAndLink method. ++ ++ static constexpr int kOptimizedBranchAndLinkLongReturnOffset = 4 * kInstrSize; ++ ++ // Here we are patching the address in the LUI/ADDI instruction pair. ++ // These values are used in the serialization process and must be zero for ++ // RISC-V platform, as Code, Embedded Object or External-reference pointers ++ // are split across two consecutive instructions and don't exist separately ++ // in the code, so the serializer should not step forwards in memory after ++ // a target is resolved and written. ++ static constexpr int kSpecialTargetSize = 0; ++ ++ // Number of consecutive instructions used to store 32bit/64bit constant. ++ // This constant was used in RelocInfo::target_address_address() function ++ // to tell serializer address of the instruction that follows ++ // LUI/ADDI instruction pair. ++ static constexpr int kInstructionsFor32BitConstant = 2; ++ static constexpr int kInstructionsFor64BitConstant = 8; ++ ++ // Difference between address of current opcode and value read from pc ++ // register. ++ static constexpr int kPcLoadDelta = 4; ++ ++ // Bits available for offset field in branches ++ static constexpr int kBranchOffsetBits = 13; ++ ++ // Bits available for offset field in jump ++ static constexpr int kJumpOffsetBits = 21; ++ ++ // Max offset for b instructions with 12-bit offset field (multiple of 2) ++ static constexpr int kMaxBranchOffset = (1 << (13 - 1)) - 1; ++ ++ // Max offset for jal instruction with 20-bit offset field (multiple of 2) ++ static constexpr int kMaxJumpOffset = (1 << (21 - 1)) - 1; ++ ++ static constexpr int kTrampolineSlotsSize = 2 * kInstrSize; ++ ++ RegList* GetScratchRegisterList() { return &scratch_register_list_; } ++ ++ // --------------------------------------------------------------------------- ++ // Code generation. ++ ++ // Insert the smallest number of nop instructions ++ // possible to align the pc offset to a multiple ++ // of m. m must be a power of 2 (>= 4). ++ void Align(int m); ++ // Insert the smallest number of zero bytes possible to align the pc offset ++ // to a mulitple of m. m must be a power of 2 (>= 2). ++ void DataAlign(int m); ++ // Aligns code to something that's optimal for a jump target for the platform. ++ void CodeTargetAlign(); ++ ++ // Different nop operations are used by the code generator to detect certain ++ // states of the generated code. ++ enum NopMarkerTypes { ++ NON_MARKING_NOP = 0, ++ DEBUG_BREAK_NOP, ++ // IC markers. ++ PROPERTY_ACCESS_INLINED, ++ PROPERTY_ACCESS_INLINED_CONTEXT, ++ PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE, ++ // Helper values. ++ LAST_CODE_MARKER, ++ FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED, ++ }; ++ ++ // RISC-V Instructions Emited to a buffer ++ ++ void lui(Register rd, int32_t imm20); ++ void auipc(Register rd, int32_t imm20); ++ ++ // Jumps ++ void jal(Register rd, int32_t imm20); ++ void jalr(Register rd, Register rs1, int16_t imm12); ++ ++ // Branches ++ void beq(Register rs1, Register rs2, int16_t imm12); ++ inline void beq(Register rs1, Register rs2, Label* L) { ++ beq(rs1, rs2, branch_offset(L)); ++ } ++ void bne(Register rs1, Register rs2, int16_t imm12); ++ inline void bne(Register rs1, Register rs2, Label* L) { ++ bne(rs1, rs2, branch_offset(L)); ++ } ++ void blt(Register rs1, Register rs2, int16_t imm12); ++ inline void blt(Register rs1, Register rs2, Label* L) { ++ blt(rs1, rs2, branch_offset(L)); ++ } ++ void bge(Register rs1, Register rs2, int16_t imm12); ++ inline void bge(Register rs1, Register rs2, Label* L) { ++ bge(rs1, rs2, branch_offset(L)); ++ } ++ void bltu(Register rs1, Register rs2, int16_t imm12); ++ inline void bltu(Register rs1, Register rs2, Label* L) { ++ bltu(rs1, rs2, branch_offset(L)); ++ } ++ void bgeu(Register rs1, Register rs2, int16_t imm12); ++ inline void bgeu(Register rs1, Register rs2, Label* L) { ++ bgeu(rs1, rs2, branch_offset(L)); ++ } ++ ++ // Loads ++ void lb(Register rd, Register rs1, int16_t imm12); ++ void lh(Register rd, Register rs1, int16_t imm12); ++ void lw(Register rd, Register rs1, int16_t imm12); ++ void lbu(Register rd, Register rs1, int16_t imm12); ++ void lhu(Register rd, Register rs1, int16_t imm12); ++ ++ // Stores ++ void sb(Register source, Register base, int16_t imm12); ++ void sh(Register source, Register base, int16_t imm12); ++ void sw(Register source, Register base, int16_t imm12); ++ ++ // Arithmetic with immediate ++ void addi(Register rd, Register rs1, int16_t imm12); ++ void slti(Register rd, Register rs1, int16_t imm12); ++ void sltiu(Register rd, Register rs1, int16_t imm12); ++ void xori(Register rd, Register rs1, int16_t imm12); ++ void ori(Register rd, Register rs1, int16_t imm12); ++ void andi(Register rd, Register rs1, int16_t imm12); ++ void slli(Register rd, Register rs1, uint8_t shamt); ++ void srli(Register rd, Register rs1, uint8_t shamt); ++ void srai(Register rd, Register rs1, uint8_t shamt); ++ ++ // Arithmetic ++ void add(Register rd, Register rs1, Register rs2); ++ void sub(Register rd, Register rs1, Register rs2); ++ void sll(Register rd, Register rs1, Register rs2); ++ void slt(Register rd, Register rs1, Register rs2); ++ void sltu(Register rd, Register rs1, Register rs2); ++ void xor_(Register rd, Register rs1, Register rs2); ++ void srl(Register rd, Register rs1, Register rs2); ++ void sra(Register rd, Register rs1, Register rs2); ++ void or_(Register rd, Register rs1, Register rs2); ++ void and_(Register rd, Register rs1, Register rs2); ++ ++ // Memory fences ++ void fence(uint8_t pred, uint8_t succ); ++ void fence_tso(); ++ ++ // Environment call / break ++ void ecall(); ++ void ebreak(); ++ ++ // This is a de facto standard (as set by GNU binutils) 32-bit unimplemented ++ // instruction (i.e., it should always trap, if your implementation has ++ // invalid instruction traps). ++ void unimp(); ++ ++ // CSR ++ void csrrw(Register rd, ControlStatusReg csr, Register rs1); ++ void csrrs(Register rd, ControlStatusReg csr, Register rs1); ++ void csrrc(Register rd, ControlStatusReg csr, Register rs1); ++ void csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5); ++ void csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5); ++ void csrrci(Register rd, ControlStatusReg csr, uint8_t imm5); ++ ++ // RV64I ++ void lwu(Register rd, Register rs1, int16_t imm12); ++ void ld(Register rd, Register rs1, int16_t imm12); ++ void sd(Register source, Register base, int16_t imm12); ++ void addiw(Register rd, Register rs1, int16_t imm12); ++ void slliw(Register rd, Register rs1, uint8_t shamt); ++ void srliw(Register rd, Register rs1, uint8_t shamt); ++ void sraiw(Register rd, Register rs1, uint8_t shamt); ++ void addw(Register rd, Register rs1, Register rs2); ++ void subw(Register rd, Register rs1, Register rs2); ++ void sllw(Register rd, Register rs1, Register rs2); ++ void srlw(Register rd, Register rs1, Register rs2); ++ void sraw(Register rd, Register rs1, Register rs2); ++ ++ // RV32M Standard Extension ++ void mul(Register rd, Register rs1, Register rs2); ++ void mulh(Register rd, Register rs1, Register rs2); ++ void mulhsu(Register rd, Register rs1, Register rs2); ++ void mulhu(Register rd, Register rs1, Register rs2); ++ void div(Register rd, Register rs1, Register rs2); ++ void divu(Register rd, Register rs1, Register rs2); ++ void rem(Register rd, Register rs1, Register rs2); ++ void remu(Register rd, Register rs1, Register rs2); ++ ++ // RV64M Standard Extension (in addition to RV32M) ++ void mulw(Register rd, Register rs1, Register rs2); ++ void divw(Register rd, Register rs1, Register rs2); ++ void divuw(Register rd, Register rs1, Register rs2); ++ void remw(Register rd, Register rs1, Register rs2); ++ void remuw(Register rd, Register rs1, Register rs2); ++ ++ // RV32A Standard Extension ++ void lr_w(bool aq, bool rl, Register rd, Register rs1); ++ void sc_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoswap_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoadd_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoxor_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoand_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoor_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomin_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomax_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amominu_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomaxu_w(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ ++ // RV64A Standard Extension (in addition to RV32A) ++ void lr_d(bool aq, bool rl, Register rd, Register rs1); ++ void sc_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoswap_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoadd_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoxor_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoand_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amoor_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomin_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomax_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amominu_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ void amomaxu_d(bool aq, bool rl, Register rd, Register rs1, Register rs2); ++ ++ // RV32F Standard Extension ++ void flw(FPURegister rd, Register rs1, int16_t imm12); ++ void fsw(FPURegister source, Register base, int16_t imm12); ++ void fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fsqrt_s(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fcvt_w_s(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_wu_s(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fmv_x_w(Register rd, FPURegister rs1); ++ void feq_s(Register rd, FPURegister rs1, FPURegister rs2); ++ void flt_s(Register rd, FPURegister rs1, FPURegister rs2); ++ void fle_s(Register rd, FPURegister rs1, FPURegister rs2); ++ void fclass_s(Register rd, FPURegister rs1); ++ void fcvt_s_w(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fcvt_s_wu(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fmv_w_x(FPURegister rd, Register rs1); ++ ++ // RV64F Standard Extension (in addition to RV32F) ++ void fcvt_l_s(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_lu_s(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_s_l(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fcvt_s_lu(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ ++ // RV32D Standard Extension ++ void fld(FPURegister rd, Register rs1, int16_t imm12); ++ void fsd(FPURegister source, Register base, int16_t imm12); ++ void fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ FPURegister rs3, RoundingMode frm = RNE); ++ void fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2, ++ RoundingMode frm = RNE); ++ void fsqrt_d(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2); ++ void fcvt_s_d(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_d_s(FPURegister rd, FPURegister rs1, RoundingMode frm = RNE); ++ void feq_d(Register rd, FPURegister rs1, FPURegister rs2); ++ void flt_d(Register rd, FPURegister rs1, FPURegister rs2); ++ void fle_d(Register rd, FPURegister rs1, FPURegister rs2); ++ void fclass_d(Register rd, FPURegister rs1); ++ void fcvt_w_d(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_wu_d(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_d_w(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fcvt_d_wu(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ ++ // RV64D Standard Extension (in addition to RV32D) ++ void fcvt_l_d(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fcvt_lu_d(Register rd, FPURegister rs1, RoundingMode frm = RNE); ++ void fmv_x_d(Register rd, FPURegister rs1); ++ void fcvt_d_l(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fcvt_d_lu(FPURegister rd, Register rs1, RoundingMode frm = RNE); ++ void fmv_d_x(FPURegister rd, Register rs1); ++ ++ // Privileged ++ void uret(); ++ void sret(); ++ void mret(); ++ void wfi(); ++ void sfence_vma(Register rs1, Register rs2); ++ ++ // Assembler Pseudo Instructions (Tables 25.2, 25.3, RISC-V Unprivileged ISA) ++ void nop(); ++ void RV_li(Register rd, int64_t imm); ++ // Returns the number of instructions required to load the immediate ++ static int li_count(int64_t imm); ++ // Loads an immediate, always using 8 instructions, regardless of the value, ++ // so that it can be modified later. ++ void li_constant(Register rd, int64_t imm); ++ ++ void mv(Register rd, Register rs) { addi(rd, rs, 0); } ++ void not_(Register rd, Register rs) { xori(rd, rs, -1); } ++ void neg(Register rd, Register rs) { sub(rd, zero_reg, rs); } ++ void negw(Register rd, Register rs) { subw(rd, zero_reg, rs); } ++ void sext_w(Register rd, Register rs) { addiw(rd, rs, 0); } ++ void seqz(Register rd, Register rs) { sltiu(rd, rs, 1); } ++ void snez(Register rd, Register rs) { sltu(rd, zero_reg, rs); } ++ void sltz(Register rd, Register rs) { slt(rd, rs, zero_reg); } ++ void sgtz(Register rd, Register rs) { slt(rd, zero_reg, rs); } ++ ++ void fmv_s(FPURegister rd, FPURegister rs) { fsgnj_s(rd, rs, rs); } ++ void fabs_s(FPURegister rd, FPURegister rs) { fsgnjx_s(rd, rs, rs); } ++ void fneg_s(FPURegister rd, FPURegister rs) { fsgnjn_s(rd, rs, rs); } ++ void fmv_d(FPURegister rd, FPURegister rs) { fsgnj_d(rd, rs, rs); } ++ void fabs_d(FPURegister rd, FPURegister rs) { fsgnjx_d(rd, rs, rs); } ++ void fneg_d(FPURegister rd, FPURegister rs) { fsgnjn_d(rd, rs, rs); } ++ ++ void beqz(Register rs, int16_t imm13) { beq(rs, zero_reg, imm13); } ++ inline void beqz(Register rs1, Label* L) { beqz(rs1, branch_offset(L)); } ++ void bnez(Register rs, int16_t imm13) { bne(rs, zero_reg, imm13); } ++ inline void bnez(Register rs1, Label* L) { bnez(rs1, branch_offset(L)); } ++ void blez(Register rs, int16_t imm13) { bge(zero_reg, rs, imm13); } ++ inline void blez(Register rs1, Label* L) { blez(rs1, branch_offset(L)); } ++ void bgez(Register rs, int16_t imm13) { bge(rs, zero_reg, imm13); } ++ inline void bgez(Register rs1, Label* L) { bgez(rs1, branch_offset(L)); } ++ void bltz(Register rs, int16_t imm13) { blt(rs, zero_reg, imm13); } ++ inline void bltz(Register rs1, Label* L) { bltz(rs1, branch_offset(L)); } ++ void bgtz(Register rs, int16_t imm13) { blt(zero_reg, rs, imm13); } ++ ++ inline void bgtz(Register rs1, Label* L) { bgtz(rs1, branch_offset(L)); } ++ void bgt(Register rs1, Register rs2, int16_t imm13) { blt(rs2, rs1, imm13); } ++ inline void bgt(Register rs1, Register rs2, Label* L) { ++ bgt(rs1, rs2, branch_offset(L)); ++ } ++ void ble(Register rs1, Register rs2, int16_t imm13) { bge(rs2, rs1, imm13); } ++ inline void ble(Register rs1, Register rs2, Label* L) { ++ ble(rs1, rs2, branch_offset(L)); ++ } ++ void bgtu(Register rs1, Register rs2, int16_t imm13) { ++ bltu(rs2, rs1, imm13); ++ } ++ inline void bgtu(Register rs1, Register rs2, Label* L) { ++ bgtu(rs1, rs2, branch_offset(L)); ++ } ++ void bleu(Register rs1, Register rs2, int16_t imm13) { ++ bgeu(rs2, rs1, imm13); ++ } ++ inline void bleu(Register rs1, Register rs2, Label* L) { ++ bleu(rs1, rs2, branch_offset(L)); ++ } ++ ++ // TODO: Replace uses of ToRegister with names once they are properly defined ++ void j(int32_t imm21) { jal(zero_reg, imm21); } ++ inline void j(Label* L) { j(jump_offset(L)); } ++ void jal(int32_t imm21) { jal(ToRegister(1), imm21); } ++ inline void jal(Label* L) { jal(jump_offset(L)); } ++ void jr(Register rs) { jalr(zero_reg, rs, 0); } ++ void jr(Register rs, int32_t imm12) { jalr(zero_reg, rs, imm12); } ++ void jalr(Register rs, int32_t imm12) { jalr(ToRegister(1), rs, imm12); } ++ void jalr(Register rs) { jalr(ToRegister(1), rs, 0); } ++ void ret() { jalr(zero_reg, ToRegister(1), 0); } ++ void call(int32_t offset) { ++ auipc(ToRegister(1), (offset >> 12) + ((offset & 0x800) >> 11)); ++ jalr(ToRegister(1), ToRegister(1), offset << 20 >> 20); ++ } ++ ++ // Read instructions-retired counter ++ void rdinstret(Register rd) { csrrs(rd, csr_instret, zero_reg); } ++ void rdinstreth(Register rd) { csrrs(rd, csr_instreth, zero_reg); } ++ void rdcycle(Register rd) { csrrs(rd, csr_cycle, zero_reg); } ++ void rdcycleh(Register rd) { csrrs(rd, csr_cycleh, zero_reg); } ++ void rdtime(Register rd) { csrrs(rd, csr_time, zero_reg); } ++ void rdtimeh(Register rd) { csrrs(rd, csr_timeh, zero_reg); } ++ ++ void csrr(Register rd, ControlStatusReg csr) { csrrs(rd, csr, zero_reg); } ++ void csrw(ControlStatusReg csr, Register rs) { csrrw(zero_reg, csr, rs); } ++ void csrs(ControlStatusReg csr, Register rs) { csrrs(zero_reg, csr, rs); } ++ void csrc(ControlStatusReg csr, Register rs) { csrrc(zero_reg, csr, rs); } ++ ++ void csrwi(ControlStatusReg csr, uint8_t imm) { csrrwi(zero_reg, csr, imm); } ++ void csrsi(ControlStatusReg csr, uint8_t imm) { csrrsi(zero_reg, csr, imm); } ++ void csrci(ControlStatusReg csr, uint8_t imm) { csrrci(zero_reg, csr, imm); } ++ ++ void frcsr(Register rd) { csrrs(rd, csr_fcsr, zero_reg); } ++ void fscsr(Register rd, Register rs) { csrrw(rd, csr_fcsr, rs); } ++ void fscsr(Register rs) { csrrw(zero_reg, csr_fcsr, rs); } ++ ++ void frrm(Register rd) { csrrs(rd, csr_frm, zero_reg); } ++ void fsrm(Register rd, Register rs) { csrrw(rd, csr_frm, rs); } ++ void fsrm(Register rs) { csrrw(zero_reg, csr_frm, rs); } ++ ++ void frflags(Register rd) { csrrs(rd, csr_fflags, zero_reg); } ++ void fsflags(Register rd, Register rs) { csrrw(rd, csr_fflags, rs); } ++ void fsflags(Register rs) { csrrw(zero_reg, csr_fflags, rs); } ++ ++ // Other pseudo instructions that are not part of RISCV pseudo assemly ++ void nor(Register rd, Register rs, Register rt) { ++ or_(rd, rs, rt); ++ not_(rd, rd); ++ } ++ ++ void sync() { fence(0b1111, 0b1111); } ++ void break_(uint32_t code, bool break_as_stop = false); ++ void stop(uint32_t code = kMaxStopCode); ++ ++ // Check the code size generated from label to here. ++ int SizeOfCodeGeneratedSince(Label* label) { ++ return pc_offset() - label->pos(); ++ } ++ ++ // Check the number of instructions generated from label to here. ++ int InstructionsGeneratedSince(Label* label) { ++ return SizeOfCodeGeneratedSince(label) / kInstrSize; ++ } ++ ++ // Class for scoping postponing the trampoline pool generation. ++ class BlockTrampolinePoolScope { ++ public: ++ explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) { ++ assem_->StartBlockTrampolinePool(); ++ } ++ ~BlockTrampolinePoolScope() { assem_->EndBlockTrampolinePool(); } ++ ++ private: ++ Assembler* assem_; ++ ++ DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope); ++ }; ++ ++ // Class for postponing the assembly buffer growth. Typically used for ++ // sequences of instructions that must be emitted as a unit, before ++ // buffer growth (and relocation) can occur. ++ // This blocking scope is not nestable. ++ class BlockGrowBufferScope { ++ public: ++ explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) { ++ assem_->StartBlockGrowBuffer(); ++ } ++ ~BlockGrowBufferScope() { assem_->EndBlockGrowBuffer(); } ++ ++ private: ++ Assembler* assem_; ++ ++ DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope); ++ }; ++ ++ // Record a deoptimization reason that can be used by a log or cpu profiler. ++ // Use --trace-deopt to enable. ++ void RecordDeoptReason(DeoptimizeReason reason, SourcePosition position, ++ int id); ++ ++ static int RelocateInternalReference(RelocInfo::Mode rmode, Address pc, ++ intptr_t pc_delta); ++ ++ // Writes a single byte or word of data in the code stream. Used for ++ // inline tables, e.g., jump-tables. ++ void db(uint8_t data); ++ void dd(uint32_t data); ++ void dq(uint64_t data); ++ void dp(uintptr_t data) { dq(data); } ++ void dd(Label* label); ++ ++ // Postpone the generation of the trampoline pool for the specified number of ++ // instructions. ++ void BlockTrampolinePoolFor(int instructions); ++ ++ // Check if there is less than kGap bytes available in the buffer. ++ // If this is the case, we need to grow the buffer before emitting ++ // an instruction or relocation information. ++ inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; } ++ ++ // Get the number of bytes available in the buffer. ++ inline intptr_t available_space() const { ++ return reloc_info_writer.pos() - pc_; ++ } ++ ++ // Read/patch instructions. ++ static Instr instr_at(Address pc) { return *reinterpret_cast(pc); } ++ static void instr_at_put(Address pc, Instr instr) { ++ *reinterpret_cast(pc) = instr; ++ } ++ Instr instr_at(int pos) { ++ return *reinterpret_cast(buffer_start_ + pos); ++ } ++ void instr_at_put(int pos, Instr instr) { ++ *reinterpret_cast(buffer_start_ + pos) = instr; ++ } ++ ++ // Check if an instruction is a branch of some kind. ++ static bool IsBranch(Instr instr); ++ static bool IsJump(Instr instr); ++ static bool IsJal(Instr instr); ++ static bool IsJalr(Instr instr); ++ static bool IsLui(Instr instr); ++ static bool IsAuipc(Instr instr); ++ static bool IsAddiw(Instr instr); ++ static bool IsAddi(Instr instr); ++ static bool IsSlli(Instr instr); ++ ++ void CheckTrampolinePool(); ++ ++ inline int UnboundLabelsCount() { return unbound_labels_count_; } ++ ++ protected: ++ // Readable constants for base and offset adjustment helper, these indicate if ++ // aside from offset, another value like offset + 4 should fit into int16. ++ enum class OffsetAccessType : bool { ++ SINGLE_ACCESS = false, ++ TWO_ACCESSES = true ++ }; ++ ++ // Determine whether need to adjust base and offset of memroy load/store ++ bool NeedAdjustBaseAndOffset( ++ const MemOperand& src, OffsetAccessType = OffsetAccessType::SINGLE_ACCESS, ++ int second_Access_add_to_offset = 4); ++ ++ // Helper function for memory load/store using base register and offset. ++ void AdjustBaseAndOffset( ++ MemOperand* src, Register scratch, ++ OffsetAccessType access_type = OffsetAccessType::SINGLE_ACCESS, ++ int second_access_add_to_offset = 4); ++ ++ inline static void set_target_internal_reference_encoded_at(Address pc, ++ Address target); ++ ++ int64_t buffer_space() const { return reloc_info_writer.pos() - pc_; } ++ ++ // Decode branch instruction at pos and return branch target pos. ++ int target_at(int pos, bool is_internal); ++ ++ // Patch branch instruction at pos to branch to given branch target pos. ++ void target_at_put(int pos, int target_pos, bool is_internal); ++ ++ // Say if we need to relocate with this mode. ++ bool MustUseReg(RelocInfo::Mode rmode); ++ ++ // Record reloc info for current pc_. ++ void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); ++ ++ // Block the emission of the trampoline pool before pc_offset. ++ void BlockTrampolinePoolBefore(int pc_offset) { ++ if (no_trampoline_pool_before_ < pc_offset) ++ no_trampoline_pool_before_ = pc_offset; ++ } ++ ++ void StartBlockTrampolinePool() { trampoline_pool_blocked_nesting_++; } ++ ++ void EndBlockTrampolinePool() { ++ trampoline_pool_blocked_nesting_--; ++ if (trampoline_pool_blocked_nesting_ == 0) { ++ CheckTrampolinePoolQuick(1); ++ } ++ } ++ ++ bool is_trampoline_pool_blocked() const { ++ return trampoline_pool_blocked_nesting_ > 0; ++ } ++ ++ bool has_exception() const { return internal_trampoline_exception_; } ++ ++ bool is_trampoline_emitted() const { return trampoline_emitted_; } ++ ++ // Temporarily block automatic assembly buffer growth. ++ void StartBlockGrowBuffer() { ++ DCHECK(!block_buffer_growth_); ++ block_buffer_growth_ = true; ++ } ++ ++ void EndBlockGrowBuffer() { ++ DCHECK(block_buffer_growth_); ++ block_buffer_growth_ = false; ++ } ++ ++ bool is_buffer_growth_blocked() const { return block_buffer_growth_; } ++ ++ void CheckTrampolinePoolQuick(int extra_instructions = 0) { ++ if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) { ++ CheckTrampolinePool(); ++ } ++ } ++ ++ private: ++ // Avoid overflows for displacements etc. ++ static const int kMaximalBufferSize = 512 * MB; ++ ++ // Buffer size and constant pool distance are checked together at regular ++ // intervals of kBufferCheckInterval emitted bytes. ++ static constexpr int kBufferCheckInterval = 1 * KB / 2; ++ ++ // Code generation. ++ // The relocation writer's position is at least kGap bytes below the end of ++ // the generated instructions. This is so that multi-instruction sequences do ++ // not have to check for overflow. The same is true for writes of large ++ // relocation info entries. ++ static constexpr int kGap = 64; ++ STATIC_ASSERT(AssemblerBase::kMinimalBufferSize >= 2 * kGap); ++ ++ // Repeated checking whether the trampoline pool should be emitted is rather ++ // expensive. By default we only check again once a number of instructions ++ // has been generated. ++ static constexpr int kCheckConstIntervalInst = 32; ++ static constexpr int kCheckConstInterval = ++ kCheckConstIntervalInst * kInstrSize; ++ ++ int next_buffer_check_; // pc offset of next buffer check. ++ ++ // Emission of the trampoline pool may be blocked in some code sequences. ++ int trampoline_pool_blocked_nesting_; // Block emission if this is not zero. ++ int no_trampoline_pool_before_; // Block emission before this pc offset. ++ ++ // Keep track of the last emitted pool to guarantee a maximal distance. ++ int last_trampoline_pool_end_; // pc offset of the end of the last pool. ++ ++ // Automatic growth of the assembly buffer may be blocked for some sequences. ++ bool block_buffer_growth_; // Block growth when true. ++ ++ // Relocation information generation. ++ // Each relocation is encoded as a variable size value. ++ static constexpr int kMaxRelocSize = RelocInfoWriter::kMaxSize; ++ RelocInfoWriter reloc_info_writer; ++ ++ // The bound position, before this we cannot do instruction elimination. ++ int last_bound_pos_; ++ ++ // Code emission. ++ inline void CheckBuffer(); ++ void GrowBuffer(); ++ inline void emit(Instr x); ++ inline void emit(uint64_t x); ++ template ++ inline void EmitHelper(T x); ++ ++ static void disassembleInstr(Instr instr); ++ ++ // Instruction generation. ++ ++ // ----- Top-level instruction formats match those in the ISA manual ++ // (R, I, S, B, U, J). These match the formats defined in LLVM's ++ // RISCVInstrFormats.td. ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, Register rd, ++ Register rs1, Register rs2); ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, FPURegister rd, ++ FPURegister rs1, FPURegister rs2); ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, Register rd, ++ FPURegister rs1, Register rs2); ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, FPURegister rd, ++ Register rs1, Register rs2); ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, FPURegister rd, ++ FPURegister rs1, Register rs2); ++ void GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, Register rd, ++ FPURegister rs1, FPURegister rs2); ++ void GenInstrR4(uint8_t funct2, Opcode opcode, Register rd, Register rs1, ++ Register rs2, Register rs3, RoundingMode frm); ++ void GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd, ++ FPURegister rs1, FPURegister rs2, FPURegister rs3, ++ RoundingMode frm); ++ void GenInstrRAtomic(uint8_t funct5, bool aq, bool rl, uint8_t funct3, ++ Register rd, Register rs1, Register rs2); ++ void GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd, Register rs1, ++ Register rs2, RoundingMode frm); ++ void GenInstrI(uint8_t funct3, Opcode opcode, Register rd, Register rs1, ++ int16_t imm12); ++ void GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd, Register rs1, ++ int16_t imm12); ++ void GenInstrIShift(bool arithshift, uint8_t funct3, Opcode opcode, ++ Register rd, Register rs1, uint8_t shamt); ++ void GenInstrIShiftW(bool arithshift, uint8_t funct3, Opcode opcode, ++ Register rd, Register rs1, uint8_t shamt); ++ void GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, Register rs2, ++ int16_t imm12); ++ void GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, FPURegister rs2, ++ int16_t imm12); ++ void GenInstrB(uint8_t funct3, Opcode opcode, Register rs1, Register rs2, ++ int16_t imm12); ++ void GenInstrU(Opcode opcode, Register rd, int32_t imm20); ++ void GenInstrJ(Opcode opcode, Register rd, int32_t imm20); ++ ++ // ----- Instruction class templates match those in LLVM's RISCVInstrInfo.td ++ void GenInstrBranchCC_rri(uint8_t funct3, Register rs1, Register rs2, ++ int16_t imm12); ++ void GenInstrLoad_ri(uint8_t funct3, Register rd, Register rs1, ++ int16_t imm12); ++ void GenInstrStore_rri(uint8_t funct3, Register rs1, Register rs2, ++ int16_t imm12); ++ void GenInstrALU_ri(uint8_t funct3, Register rd, Register rs1, int16_t imm12); ++ void GenInstrShift_ri(bool arithshift, uint8_t funct3, Register rd, ++ Register rs1, uint8_t shamt); ++ void GenInstrALU_rr(uint8_t funct7, uint8_t funct3, Register rd, Register rs1, ++ Register rs2); ++ void GenInstrCSR_ir(uint8_t funct3, Register rd, ControlStatusReg csr, ++ Register rs1); ++ void GenInstrCSR_ii(uint8_t funct3, Register rd, ControlStatusReg csr, ++ uint8_t rs1); ++ void GenInstrShiftW_ri(bool arithshift, uint8_t funct3, Register rd, ++ Register rs1, uint8_t shamt); ++ void GenInstrALUW_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ Register rs1, Register rs2); ++ void GenInstrPriv(uint8_t funct7, Register rs1, Register rs2); ++ void GenInstrLoadFP_ri(uint8_t funct3, FPURegister rd, Register rs1, ++ int16_t imm12); ++ void GenInstrStoreFP_rri(uint8_t funct3, Register rs1, FPURegister rs2, ++ int16_t imm12); ++ void GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ FPURegister rs1, FPURegister rs2); ++ void GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ Register rs1, Register rs2); ++ void GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, FPURegister rd, ++ FPURegister rs1, Register rs2); ++ void GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ FPURegister rs1, Register rs2); ++ void GenInstrALUFP_rr(uint8_t funct7, uint8_t funct3, Register rd, ++ FPURegister rs1, FPURegister rs2); ++ ++ // Labels. ++ void print(const Label* L); ++ void bind_to(Label* L, int pos); ++ void next(Label* L, bool is_internal); ++ ++ // One trampoline consists of: ++ // - space for trampoline slots, ++ // - space for labels. ++ // ++ // Space for trampoline slots is equal to slot_count * 2 * kInstrSize. ++ // Space for trampoline slots precedes space for labels. Each label is of one ++ // instruction size, so total amount for labels is equal to ++ // label_count * kInstrSize. ++ class Trampoline { ++ public: ++ Trampoline() { ++ start_ = 0; ++ next_slot_ = 0; ++ free_slot_count_ = 0; ++ end_ = 0; ++ } ++ Trampoline(int start, int slot_count) { ++ start_ = start; ++ next_slot_ = start; ++ free_slot_count_ = slot_count; ++ end_ = start + slot_count * kTrampolineSlotsSize; ++ } ++ int start() { return start_; } ++ int end() { return end_; } ++ int take_slot() { ++ int trampoline_slot = kInvalidSlotPos; ++ if (free_slot_count_ <= 0) { ++ // We have run out of space on trampolines. ++ // Make sure we fail in debug mode, so we become aware of each case ++ // when this happens. ++ DCHECK(0); ++ // Internal exception will be caught. ++ } else { ++ trampoline_slot = next_slot_; ++ free_slot_count_--; ++ next_slot_ += kTrampolineSlotsSize; ++ } ++ return trampoline_slot; ++ } ++ ++ private: ++ int start_; ++ int end_; ++ int next_slot_; ++ int free_slot_count_; ++ }; ++ ++ int32_t get_trampoline_entry(int32_t pos); ++ int unbound_labels_count_; ++ // After trampoline is emitted, long branches are used in generated code for ++ // the forward branches whose target offsets could be beyond reach of branch ++ // instruction. We use this information to trigger different mode of ++ // branch instruction generation, where we use jump instructions rather ++ // than regular branch instructions. ++ bool trampoline_emitted_ = false; ++ static constexpr int kInvalidSlotPos = -1; ++ ++ // Internal reference positions, required for unbounded internal reference ++ // labels. ++ std::set internal_reference_positions_; ++ bool is_internal_reference(Label* L) { ++ return internal_reference_positions_.find(L->pos()) != ++ internal_reference_positions_.end(); ++ } ++ ++ Trampoline trampoline_; ++ bool internal_trampoline_exception_; ++ ++ RegList scratch_register_list_; ++ ++ private: ++ void AllocateAndInstallRequestedHeapObjects(Isolate* isolate); ++ ++ int WriteCodeComments(); ++ ++ friend class RegExpMacroAssemblerRISCV; ++ friend class RelocInfo; ++ friend class BlockTrampolinePoolScope; ++ friend class EnsureSpace; ++}; ++ ++class EnsureSpace { ++ public: ++ explicit inline EnsureSpace(Assembler* assembler); ++}; ++ ++class V8_EXPORT_PRIVATE UseScratchRegisterScope { ++ public: ++ explicit UseScratchRegisterScope(Assembler* assembler); ++ ~UseScratchRegisterScope(); ++ ++ Register Acquire(); ++ bool hasAvailable() const; ++ ++ private: ++ RegList* available_; ++ RegList old_available_; ++}; ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_CODEGEN_RISCV_ASSEMBLER_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/constants-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/constants-riscv64.cc +@@ -0,0 +1,111 @@ ++// Copyright 2011 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/riscv64/constants-riscv64.h" ++ ++namespace v8 { ++namespace internal { ++ ++// ----------------------------------------------------------------------------- ++// Registers. ++ ++// These register names are defined in a way to match the native disassembler ++// formatting. See for example the command "objdump -d ". ++const char* Registers::names_[kNumSimuRegisters] = { ++ "zero_reg", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1", "a0", ++ "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", ++ "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", "pc"}; ++ ++// List of alias names which can be used when referring to RISC-V registers. ++const Registers::RegisterAlias Registers::aliases_[] = { ++ {0, "zero"}, ++ {33, "pc"}, ++ {8, "s0"}, ++ {8, "s0_fp"}, ++ {kInvalidRegister, nullptr}}; ++ ++const char* Registers::Name(int reg) { ++ const char* result; ++ if ((0 <= reg) && (reg < kNumSimuRegisters)) { ++ result = names_[reg]; ++ } else { ++ result = "noreg"; ++ } ++ return result; ++} ++ ++int Registers::Number(const char* name) { ++ // Look through the canonical names. ++ for (int i = 0; i < kNumSimuRegisters; i++) { ++ if (strcmp(names_[i], name) == 0) { ++ return i; ++ } ++ } ++ ++ // Look through the alias names. ++ int i = 0; ++ while (aliases_[i].reg != kInvalidRegister) { ++ if (strcmp(aliases_[i].name, name) == 0) { ++ return aliases_[i].reg; ++ } ++ i++; ++ } ++ ++ // No register with the reguested name found. ++ return kInvalidRegister; ++} ++ ++/* ++const char* FPURegisters::names_[kNumFPURegisters] = { ++ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", ++ "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", ++ "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; ++*/ ++const char* FPURegisters::names_[kNumFPURegisters] = { ++ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", ++ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", ++ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", ++ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"}; ++ ++// List of alias names which can be used when referring to RISC-V FP registers. ++const FPURegisters::RegisterAlias FPURegisters::aliases_[] = { ++ {kInvalidRegister, nullptr}}; ++ ++const char* FPURegisters::Name(int creg) { ++ const char* result; ++ if ((0 <= creg) && (creg < kNumFPURegisters)) { ++ result = names_[creg]; ++ } else { ++ result = "nocreg"; ++ } ++ return result; ++} ++ ++int FPURegisters::Number(const char* name) { ++ // Look through the canonical names. ++ for (int i = 0; i < kNumFPURegisters; i++) { ++ if (strcmp(names_[i], name) == 0) { ++ return i; ++ } ++ } ++ ++ // Look through the alias names. ++ int i = 0; ++ while (aliases_[i].creg != kInvalidRegister) { ++ if (strcmp(aliases_[i].name, name) == 0) { ++ return aliases_[i].creg; ++ } ++ i++; ++ } ++ ++ // No Cregister with the reguested name found. ++ return kInvalidFPURegister; ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/constants-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/constants-riscv64.h +@@ -0,0 +1,947 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_CODEGEN_RISCV_CONSTANTS_RISCV_H_ ++#define V8_CODEGEN_RISCV_CONSTANTS_RISCV_H_ ++ ++#include "src/base/logging.h" ++#include "src/base/macros.h" ++#include "src/common/globals.h" ++ ++// UNIMPLEMENTED_ macro for RISCV. ++#ifdef DEBUG ++#define UNIMPLEMENTED_RISCV() \ ++ v8::internal::PrintF("%s, \tline %d: \tfunction %s not implemented. \n", \ ++ __FILE__, __LINE__, __func__) ++#else ++#define UNIMPLEMENTED_RISCV() ++#endif ++ ++#define UNSUPPORTED_RISCV() v8::internal::PrintF("Unsupported instruction.\n") ++ ++enum Endianness { kLittle, kBig }; ++ ++#if defined(V8_TARGET_LITTLE_ENDIAN) ++static const Endianness kArchEndian = kLittle; ++#elif defined(V8_TARGET_BIG_ENDIAN) ++static const Endianness kArchEndian = kBig; ++#else ++#error Unknown endianness ++#endif ++ ++#if defined(V8_TARGET_LITTLE_ENDIAN) ++const uint32_t kLeastSignificantByteInInt32Offset = 0; ++const uint32_t kLessSignificantWordInDoublewordOffset = 0; ++#elif defined(V8_TARGET_BIG_ENDIAN) ++const uint32_t kLeastSignificantByteInInt32Offset = 3; ++const uint32_t kLessSignificantWordInDoublewordOffset = 4; ++#else ++#error Unknown endianness ++#endif ++ ++#ifndef __STDC_FORMAT_MACROS ++#define __STDC_FORMAT_MACROS ++#endif ++#include ++ ++// Defines constants and accessor classes to assemble, disassemble and ++// simulate RISC-V instructions. ++// ++// See: The RISC-V Instruction Set Manual ++// Volume I: User-Level ISA ++// Try https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf. ++ ++namespace v8 { ++namespace internal { ++ ++// TODO(sigurds): Change this value once we use relative jumps. ++constexpr size_t kMaxPCRelativeCodeRangeInMB = 0; ++ ++// ----------------------------------------------------------------------------- ++// Registers and FPURegisters. ++ ++// Number of general purpose registers. ++const int kNumRegisters = 32; ++const int kInvalidRegister = -1; ++ ++// Number of registers with pc. ++const int kNumSimuRegisters = 33; ++ ++// In the simulator, the PC register is simulated as the 34th register. ++const int kPCRegister = 34; ++ ++// Number coprocessor registers. ++const int kNumFPURegisters = 32; ++const int kInvalidFPURegister = -1; ++ ++// 'pref' instruction hints ++const int32_t kPrefHintLoad = 0; ++const int32_t kPrefHintStore = 1; ++const int32_t kPrefHintLoadStreamed = 4; ++const int32_t kPrefHintStoreStreamed = 5; ++const int32_t kPrefHintLoadRetained = 6; ++const int32_t kPrefHintStoreRetained = 7; ++const int32_t kPrefHintWritebackInvalidate = 25; ++const int32_t kPrefHintPrepareForStore = 30; ++ ++// Actual value of root register is offset from the root array's start ++// to take advantage of negative displacement values. ++// TODO(sigurds): Choose best value. ++constexpr int kRootRegisterBias = 256; ++ ++// Helper functions for converting between register numbers and names. ++class Registers { ++ public: ++ // Return the name of the register. ++ static const char* Name(int reg); ++ ++ // Lookup the register number for the name provided. ++ static int Number(const char* name); ++ ++ struct RegisterAlias { ++ int reg; ++ const char* name; ++ }; ++ ++ static const int64_t kMaxValue = 0x7fffffffffffffffl; ++ static const int64_t kMinValue = 0x8000000000000000l; ++ ++ private: ++ static const char* names_[kNumSimuRegisters]; ++ static const RegisterAlias aliases_[]; ++}; ++ ++// Helper functions for converting between register numbers and names. ++class FPURegisters { ++ public: ++ // Return the name of the register. ++ static const char* Name(int reg); ++ ++ // Lookup the register number for the name provided. ++ static int Number(const char* name); ++ ++ struct RegisterAlias { ++ int creg; ++ const char* name; ++ }; ++ ++ private: ++ static const char* names_[kNumFPURegisters]; ++ static const RegisterAlias aliases_[]; ++}; ++ ++// ----------------------------------------------------------------------------- ++// Instructions encoding constants. ++ ++// On RISCV all instructions are 32 bits. ++using Instr = int32_t; ++ ++// Special Software Interrupt codes when used in the presence of the RISC-V ++// simulator. ++enum SoftwareInterruptCodes { ++ // Transition to C code. ++ call_rt_redirected = 0xfffff ++}; ++ ++// On RISC-V Simulator breakpoints can have different codes: ++// - Breaks between 0 and kMaxWatchpointCode are treated as simple watchpoints, ++// the simulator will run through them and print the registers. ++// - Breaks between kMaxWatchpointCode and kMaxStopCode are treated as stop() ++// instructions (see Assembler::stop()). ++// - Breaks larger than kMaxStopCode are simple breaks, dropping you into the ++// debugger. ++const uint32_t kMaxWatchpointCode = 31; ++const uint32_t kMaxStopCode = 127; ++STATIC_ASSERT(kMaxWatchpointCode < kMaxStopCode); ++ ++// ----- Fields offset and length. ++// RISCV constants ++const int kBaseOpcodeShift = 0; ++const int kBaseOpcodeBits = 7; ++const int kFunct7Shift = 25; ++const int kFunct7Bits = 7; ++const int kFunct5Shift = 27; ++const int kFunct5Bits = 5; ++const int kFunct3Shift = 12; ++const int kFunct3Bits = 3; ++const int kFunct2Shift = 25; ++const int kFunct2Bits = 2; ++const int kRs1Shift = 15; ++const int kRs1Bits = 5; ++const int kRs2Shift = 20; ++const int kRs2Bits = 5; ++const int kRs3Shift = 27; ++const int kRs3Bits = 5; ++const int kRdShift = 7; ++const int kRdBits = 5; ++const int kRlShift = 25; ++const int kAqShift = 26; ++const int kImm12Shift = 20; ++const int kImm12Bits = 12; ++const int kShamtShift = 20; ++const int kShamtBits = 5; ++const int kShamtWShift = 20; ++const int kShamtWBits = 6; ++const int kArithShiftShift = 30; ++const int kImm20Shift = 12; ++const int kImm20Bits = 20; ++const int kCsrShift = 20; ++const int kCsrBits = 12; ++const int kMemOrderBits = 4; ++const int kPredOrderShift = 24; ++const int kSuccOrderShift = 20; ++ ++// RISCV Instruction bit masks ++const uint32_t kBaseOpcodeMask = ((1 << kBaseOpcodeBits) - 1) << kBaseOpcodeShift; ++const uint32_t kFunct3Mask = ((1 << kFunct3Bits) - 1) << kFunct3Shift; ++const uint32_t kFunct5Mask = ((1 << kFunct5Bits) - 1) << kFunct5Shift; ++const uint32_t kFunct7Mask = ((1 << kFunct7Bits) - 1) << kFunct7Shift; ++const uint32_t kFunct2Mask = 0b11 << kFunct7Shift; ++const uint32_t kRTypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct7Mask; ++const uint32_t kRATypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct5Mask; ++const uint32_t kRFPTypeMask = kBaseOpcodeMask | kFunct7Mask; ++const uint32_t kR4TypeMask = kBaseOpcodeMask | kFunct3Mask | kFunct2Mask; ++const uint32_t kITypeMask = kBaseOpcodeMask | kFunct3Mask; ++const uint32_t kSTypeMask = kBaseOpcodeMask | kFunct3Mask; ++const uint32_t kBTypeMask = kBaseOpcodeMask | kFunct3Mask; ++const uint32_t kUTypeMask = kBaseOpcodeMask; ++const uint32_t kJTypeMask = kBaseOpcodeMask; ++const uint32_t kRs1FieldMask = ((1 << kRs1Bits) - 1) << kRs1Shift; ++const uint32_t kRs2FieldMask = ((1 << kRs2Bits) - 1) << kRs2Shift; ++const uint32_t kRs3FieldMask = ((1 << kRs3Bits) - 1) << kRs3Shift; ++const uint32_t kRdFieldMask = ((1 << kRdBits) - 1) << kRdShift; ++const uint32_t kBImm12Mask = kFunct7Mask | kRdFieldMask; ++const uint32_t kImm20Mask = ((1 << kImm20Bits) - 1) << kImm20Shift; ++const uint32_t kImm12Mask = ((1 << kImm12Bits) - 1) << kImm12Shift; ++ ++// RISCV CSR related bit mask and shift ++const uint32_t kFcsrFlagsBits = 5; ++const uint32_t kFcsrFlagsMask = (1 << kFcsrFlagsBits) - 1; ++const uint32_t kFcsrFrmBits = 3; ++const uint32_t kFcsrFrmShift = kFcsrFlagsBits; ++const uint32_t kFcsrFrmMask = ((1 << kFcsrFrmBits) - 1) << kFcsrFrmShift; ++const uint32_t kFcsrBits = kFcsrFlagsBits + kFcsrFrmBits; ++const uint32_t kFcsrMask = kFcsrFlagsMask | kFcsrFrmMask; ++ ++// Original MIPS constants ++// FIXME (RISCV): to be cleaned up ++const uint32_t kImm16Shift = 0; ++const uint32_t kImm16Bits = 16; ++const uint32_t kImm16Mask = ((1 << kImm16Bits) - 1) << kImm16Shift; ++// end of FIXME (RISCV): to be cleaned up ++ ++// ----- RISCV Base Opcodes ++ ++enum BaseOpcode : uint32_t { ++ ++}; ++ ++// ----- RISC-V Opcodes and Function Fields. ++enum Opcode : uint32_t { ++ LOAD = 0b0000011, // I form: LB LH LW LBU LHU ++ LOAD_FP = 0b0000111, // I form: FLW FLD FLQ ++ MISC_MEM = 0b0001111, // I special form: FENCE FENCE.I ++ OP_IMM = 0b0010011, // I form: ADDI SLTI SLTIU XORI ORI ANDI SLLI SRLI SARI ++ // Note: SLLI/SRLI/SRAI I form first, then func3 001/101 => R type ++ AUIPC = 0b0010111, // U form: AUIPC ++ OP_IMM_32 = 0b0011011, // I form: ADDIW SLLIW SRLIW SRAIW ++ // Note: SRLIW SRAIW I form first, then func3 101 special shift encoding ++ STORE = 0b0100011, // S form: SB SH SW SD ++ STORE_FP = 0b0100111, // S form: FSW FSD FSQ ++ AMO = 0b0101111, // R form: All A instructions ++ OP = 0b0110011, // R: ADD SUB SLL SLT SLTU XOR SRL SRA OR AND and 32M set ++ LUI = 0b0110111, // U form: LUI ++ OP_32 = 0b0111011, // R: ADDW SUBW SLLW SRLW SRAW MULW DIVW DIVUW REMW REMUW ++ MADD = 0b1000011, // R4 type: FMADD.S FMADD.D FMADD.Q ++ MSUB = 0b1000111, // R4 type: FMSUB.S FMSUB.D FMSUB.Q ++ NMSUB = 0b1001011, // R4 type: FNMSUB.S FNMSUB.D FNMSUB.Q ++ NMADD = 0b1001111, // R4 type: FNMADD.S FNMADD.D FNMADD.Q ++ OP_FP = 0b1010011, // R type: Q ext ++ BRANCH = 0b1100011, // B form: BEQ BNE, BLT, BGE, BLTU BGEU ++ JALR = 0b1100111, // I form: JALR ++ JAL = 0b1101111, // J form: JAL ++ SYSTEM = 0b1110011, // I form: ECALL EBREAK Zicsr ext ++ ++ // Note use RO (RiscV Opcode) prefix ++ // RV32I Base Instruction Set ++ RO_LUI = LUI, ++ RO_AUIPC = AUIPC, ++ RO_JAL = JAL, ++ RO_JALR = JALR | (0b000 << kFunct3Shift), ++ RO_BEQ = BRANCH | (0b000 << kFunct3Shift), ++ RO_BNE = BRANCH | (0b001 << kFunct3Shift), ++ RO_BLT = BRANCH | (0b100 << kFunct3Shift), ++ RO_BGE = BRANCH | (0b101 << kFunct3Shift), ++ RO_BLTU = BRANCH | (0b110 << kFunct3Shift), ++ RO_BGEU = BRANCH | (0b111 << kFunct3Shift), ++ RO_LB = LOAD | (0b000 << kFunct3Shift), ++ RO_LH = LOAD | (0b001 << kFunct3Shift), ++ RO_LW = LOAD | (0b010 << kFunct3Shift), ++ RO_LBU = LOAD | (0b100 << kFunct3Shift), ++ RO_LHU = LOAD | (0b101 << kFunct3Shift), ++ RO_SB = STORE | (0b000 << kFunct3Shift), ++ RO_SH = STORE | (0b001 << kFunct3Shift), ++ RO_SW = STORE | (0b010 << kFunct3Shift), ++ RO_ADDI = OP_IMM | (0b000 << kFunct3Shift), ++ RO_SLTI = OP_IMM | (0b010 << kFunct3Shift), ++ RO_SLTIU = OP_IMM | (0b011 << kFunct3Shift), ++ RO_XORI = OP_IMM | (0b100 << kFunct3Shift), ++ RO_ORI = OP_IMM | (0b110 << kFunct3Shift), ++ RO_ANDI = OP_IMM | (0b111 << kFunct3Shift), ++ RO_SLLI = OP_IMM | (0b001 << kFunct3Shift), ++ RO_SRLI = OP_IMM | (0b101 << kFunct3Shift), ++ // RO_SRAI = OP_IMM | (0b101 << kFunct3Shift), // Same as SRLI, use func7 ++ RO_ADD = OP | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SUB = OP | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift), ++ RO_SLL = OP | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SLT = OP | (0b010 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SLTU = OP | (0b011 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_XOR = OP | (0b100 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SRL = OP | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SRA = OP | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift), ++ RO_OR = OP | (0b110 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_AND = OP | (0b111 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_FENCE = MISC_MEM | (0b000 << kFunct3Shift), ++ RO_ECALL = SYSTEM | (0b000 << kFunct3Shift), ++ // RO_EBREAK = SYSTEM | (0b000 << kFunct3Shift), // Same as ECALL, use imm12 ++ ++ // RV64I Base Instruction Set (in addition to RV32I) ++ RO_LWU = LOAD | (0b110 << kFunct3Shift), ++ RO_LD = LOAD | (0b011 << kFunct3Shift), ++ RO_SD = STORE | (0b011 << kFunct3Shift), ++ RO_ADDIW = OP_IMM_32 | (0b000 << kFunct3Shift), ++ RO_SLLIW = OP_IMM_32 | (0b001 << kFunct3Shift), ++ RO_SRLIW = OP_IMM_32 | (0b101 << kFunct3Shift), ++ // RO_SRAIW = OP_IMM_32 | (0b101 << kFunct3Shift), // Same as SRLIW, use func7 ++ RO_ADDW = OP_32 | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SUBW = OP_32 | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift), ++ RO_SLLW = OP_32 | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SRLW = OP_32 | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift), ++ RO_SRAW = OP_32 | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift), ++ ++ // RV32/RV64 Zifencei Standard Extension ++ RO_FENCE_I = MISC_MEM | (0b001 << kFunct3Shift), ++ ++ // RV32/RV64 Zicsr Standard Extension ++ RO_CSRRW = SYSTEM | (0b001 << kFunct3Shift), ++ RO_CSRRS = SYSTEM | (0b010 << kFunct3Shift), ++ RO_CSRRC = SYSTEM | (0b011 << kFunct3Shift), ++ RO_CSRRWI = SYSTEM | (0b101 << kFunct3Shift), ++ RO_CSRRSI = SYSTEM | (0b110 << kFunct3Shift), ++ RO_CSRRCI = SYSTEM | (0b111 << kFunct3Shift), ++ ++ // RV32M Standard Extension ++ RO_MUL = OP | (0b000 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_MULH = OP | (0b001 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_MULHSU = OP | (0b010 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_MULHU = OP | (0b011 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_DIV = OP | (0b100 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_DIVU = OP | (0b101 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_REM = OP | (0b110 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_REMU = OP | (0b111 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ ++ // RV64M Standard Extension (in addition to RV32M) ++ RO_MULW = OP_32 | (0b000 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_DIVW = OP_32 | (0b100 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_DIVUW = OP_32 | (0b101 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_REMW = OP_32 | (0b110 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ RO_REMUW = OP_32 | (0b111 << kFunct3Shift) | (0b0000001 << kFunct7Shift), ++ ++ // RV32A Standard Extension ++ RO_LR_W = AMO | (0b010 << kFunct3Shift) | (0b00010 << kFunct5Shift), ++ RO_SC_W = AMO | (0b010 << kFunct3Shift) | (0b00011 << kFunct5Shift), ++ RO_AMOSWAP_W = AMO | (0b010 << kFunct3Shift) | (0b00001 << kFunct5Shift), ++ RO_AMOADD_W = AMO | (0b010 << kFunct3Shift) | (0b00000 << kFunct5Shift), ++ RO_AMOXOR_W = AMO | (0b010 << kFunct3Shift) | (0b00100 << kFunct5Shift), ++ RO_AMOAND_W = AMO | (0b010 << kFunct3Shift) | (0b01100 << kFunct5Shift), ++ RO_AMOOR_W = AMO | (0b010 << kFunct3Shift) | (0b01000 << kFunct5Shift), ++ RO_AMOMIN_W = AMO | (0b010 << kFunct3Shift) | (0b10000 << kFunct5Shift), ++ RO_AMOMAX_W = AMO | (0b010 << kFunct3Shift) | (0b10100 << kFunct5Shift), ++ RO_AMOMINU_W = AMO | (0b010 << kFunct3Shift) | (0b11000 << kFunct5Shift), ++ RO_AMOMAXU_W = AMO | (0b010 << kFunct3Shift) | (0b11100 << kFunct5Shift), ++ ++ // RV64A Standard Extension (in addition to RV32A) ++ RO_LR_D = AMO | (0b011 << kFunct3Shift) | (0b00010 << kFunct5Shift), ++ RO_SC_D = AMO | (0b011 << kFunct3Shift) | (0b00011 << kFunct5Shift), ++ RO_AMOSWAP_D = AMO | (0b011 << kFunct3Shift) | (0b00001 << kFunct5Shift), ++ RO_AMOADD_D = AMO | (0b011 << kFunct3Shift) | (0b00000 << kFunct5Shift), ++ RO_AMOXOR_D = AMO | (0b011 << kFunct3Shift) | (0b00100 << kFunct5Shift), ++ RO_AMOAND_D = AMO | (0b011 << kFunct3Shift) | (0b01100 << kFunct5Shift), ++ RO_AMOOR_D = AMO | (0b011 << kFunct3Shift) | (0b01000 << kFunct5Shift), ++ RO_AMOMIN_D = AMO | (0b011 << kFunct3Shift) | (0b10000 << kFunct5Shift), ++ RO_AMOMAX_D = AMO | (0b011 << kFunct3Shift) | (0b10100 << kFunct5Shift), ++ RO_AMOMINU_D = AMO | (0b011 << kFunct3Shift) | (0b11000 << kFunct5Shift), ++ RO_AMOMAXU_D = AMO | (0b011 << kFunct3Shift) | (0b11100 << kFunct5Shift), ++ ++ // RV32F Standard Extension ++ RO_FLW = LOAD_FP | (0b010 << kFunct3Shift), ++ RO_FSW = STORE_FP | (0b010 << kFunct3Shift), ++ RO_FMADD_S = MADD | (0b00 << kFunct2Shift), ++ RO_FMSUB_S = MSUB | (0b00 << kFunct2Shift), ++ RO_FNMSUB_S = NMSUB | (0b00 << kFunct2Shift), ++ RO_FNMADD_S = NMADD | (0b00 << kFunct2Shift), ++ RO_FADD_S = OP_FP | (0b0000000 << kFunct7Shift), ++ RO_FSUB_S = OP_FP | (0b0000100 << kFunct7Shift), ++ RO_FMUL_S = OP_FP | (0b0001000 << kFunct7Shift), ++ RO_FDIV_S = OP_FP | (0b0001100 << kFunct7Shift), ++ RO_FSQRT_S = OP_FP | (0b0101100 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FSGNJ_S = OP_FP | (0b000 << kFunct3Shift) | (0b0010000 << kFunct7Shift), ++ RO_FSGNJN_S = OP_FP | (0b001 << kFunct3Shift) | (0b0010000 << kFunct7Shift), ++ RO_FSQNJX_S = OP_FP | (0b010 << kFunct3Shift) | (0b0010000 << kFunct7Shift), ++ RO_FMIN_S = OP_FP | (0b000 << kFunct3Shift) | (0b0010100 << kFunct7Shift), ++ RO_FMAX_S = OP_FP | (0b001 << kFunct3Shift) | (0b0010100 << kFunct7Shift), ++ RO_FCVT_W_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FCVT_WU_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00001 << kRs2Shift), ++ RO_FMV = OP_FP | (0b1110000 << kFunct7Shift) | (0b000 << kFunct3Shift) | ++ (0b00000 << kRs2Shift), ++ RO_FEQ_S = OP_FP | (0b010 << kFunct3Shift) | (0b1010000 << kFunct7Shift), ++ RO_FLT_S = OP_FP | (0b001 << kFunct3Shift) | (0b1010000 << kFunct7Shift), ++ RO_FLE_S = OP_FP | (0b000 << kFunct3Shift) | (0b1010000 << kFunct7Shift), ++ RO_FCLASS_S = OP_FP | (0b001 << kFunct3Shift) | (0b1110000 << kFunct7Shift), ++ RO_FCVT_S_W = OP_FP | (0b1101000 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FCVT_S_WU = OP_FP | (0b1101000 << kFunct7Shift) | (0b00001 << kRs2Shift), ++ RO_FMV_W_X = OP_FP | (0b000 << kFunct3Shift) | (0b1111000 << kFunct7Shift), ++ ++ // RV64F Standard Extension (in addition to RV32F) ++ RO_FCVT_L_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00010 << kRs2Shift), ++ RO_FCVT_LU_S = OP_FP | (0b1100000 << kFunct7Shift) | (0b00011 << kRs2Shift), ++ RO_FCVT_S_L = OP_FP | (0b1101000 << kFunct7Shift) | (0b00010 << kRs2Shift), ++ RO_FCVT_S_LU = OP_FP | (0b1101000 << kFunct7Shift) | (0b00011 << kRs2Shift), ++ ++ // RV32D Standard Extension ++ RO_FLD = LOAD_FP | (0b011 << kFunct3Shift), ++ RO_FSD = STORE_FP | (0b011 << kFunct3Shift), ++ RO_FMADD_D = MADD | (0b01 << kFunct2Shift), ++ RO_FMSUB_D = MSUB | (0b01 << kFunct2Shift), ++ RO_FNMSUB_D = NMSUB | (0b01 << kFunct2Shift), ++ RO_FNMADD_D = NMADD | (0b01 << kFunct2Shift), ++ RO_FADD_D = OP_FP | (0b0000001 << kFunct7Shift), ++ RO_FSUB_D = OP_FP | (0b0000101 << kFunct7Shift), ++ RO_FMUL_D = OP_FP | (0b0001001 << kFunct7Shift), ++ RO_FDIV_D = OP_FP | (0b0001101 << kFunct7Shift), ++ RO_FSQRT_D = OP_FP | (0b0101101 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FSGNJ_D = OP_FP | (0b000 << kFunct3Shift) | (0b0010001 << kFunct7Shift), ++ RO_FSGNJN_D = OP_FP | (0b001 << kFunct3Shift) | (0b0010001 << kFunct7Shift), ++ RO_FSQNJX_D = OP_FP | (0b010 << kFunct3Shift) | (0b0010001 << kFunct7Shift), ++ RO_FMIN_D = OP_FP | (0b000 << kFunct3Shift) | (0b0010101 << kFunct7Shift), ++ RO_FMAX_D = OP_FP | (0b001 << kFunct3Shift) | (0b0010101 << kFunct7Shift), ++ RO_FCVT_S_D = OP_FP | (0b0100000 << kFunct7Shift) | (0b00001 << kRs2Shift), ++ RO_FCVT_D_S = OP_FP | (0b0100001 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FEQ_D = OP_FP | (0b010 << kFunct3Shift) | (0b1010001 << kFunct7Shift), ++ RO_FLT_D = OP_FP | (0b001 << kFunct3Shift) | (0b1010001 << kFunct7Shift), ++ RO_FLE_D = OP_FP | (0b000 << kFunct3Shift) | (0b1010001 << kFunct7Shift), ++ RO_FCLASS_D = OP_FP | (0b001 << kFunct3Shift) | (0b1110001 << kFunct7Shift) | ++ (0b00000 << kRs2Shift), ++ RO_FCVT_W_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FCVT_WU_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00001 << kRs2Shift), ++ RO_FCVT_D_W = OP_FP | (0b1101001 << kFunct7Shift) | (0b00000 << kRs2Shift), ++ RO_FCVT_D_WU = OP_FP | (0b1101001 << kFunct7Shift) | (0b00001 << kRs2Shift), ++ ++ // RV64D Standard Extension (in addition to RV32D) ++ RO_FCVT_L_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00010 << kRs2Shift), ++ RO_FCVT_LU_D = OP_FP | (0b1100001 << kFunct7Shift) | (0b00011 << kRs2Shift), ++ RO_FMV_X_D = OP_FP | (0b000 << kFunct3Shift) | (0b1110001 << kFunct7Shift) | ++ (0b00000 << kRs2Shift), ++ RO_FCVT_D_L = OP_FP | (0b1101001 << kFunct7Shift) | (0b00010 << kRs2Shift), ++ RO_FCVT_D_LU = OP_FP | (0b1101001 << kFunct7Shift) | (0b00011 << kRs2Shift), ++ RO_FMV_D_X = OP_FP | (0b000 << kFunct3Shift) | (0b1111001 << kFunct7Shift) | ++ (0b00000 << kRs2Shift), ++}; ++ ++// ----- Emulated conditions. ++// On RISC-V we use this enum to abstract from conditional branch instructions. ++// The 'U' prefix is used to specify unsigned comparisons. ++// Opposite conditions must be paired as odd/even numbers ++// because 'NegateCondition' function flips LSB to negate condition. ++enum Condition { // Any value < 0 is considered no_condition. ++ kNoCondition = -1, ++ overflow = 0, ++ no_overflow = 1, ++ Uless = 2, ++ Ugreater_equal = 3, ++ Uless_equal = 4, ++ Ugreater = 5, ++ equal = 6, ++ not_equal = 7, // Unordered or Not Equal. ++ less = 8, ++ greater_equal = 9, ++ less_equal = 10, ++ greater = 11, ++ cc_always = 12, ++ ++ // Aliases. ++ eq = equal, ++ ne = not_equal, ++ ge = greater_equal, ++ lt = less, ++ gt = greater, ++ le = less_equal, ++ al = cc_always, ++ ult = Uless, ++ uge = Ugreater_equal, ++ ule = Uless_equal, ++ ugt = Ugreater, ++}; ++ ++// Returns the equivalent of !cc. ++// Negation of the default kNoCondition (-1) results in a non-default ++// no_condition value (-2). As long as tests for no_condition check ++// for condition < 0, this will work as expected. ++inline Condition NegateCondition(Condition cc) { ++ DCHECK(cc != cc_always); ++ return static_cast(cc ^ 1); ++} ++ ++inline Condition NegateFpuCondition(Condition cc) { ++ DCHECK(cc != cc_always); ++ switch (cc) { ++ case ult: ++ return ge; ++ case ugt: ++ return le; ++ case uge: ++ return lt; ++ case ule: ++ return gt; ++ case lt: ++ return uge; ++ case gt: ++ return ule; ++ case ge: ++ return ult; ++ case le: ++ return ugt; ++ case eq: ++ return ne; ++ case ne: ++ return eq; ++ default: ++ return cc; ++ } ++} ++ ++// ----- Coprocessor conditions. ++enum FPUCondition { ++ kNoFPUCondition = -1, ++ EQ = 0x02, // Ordered and Equal ++ NE = 0x03, // Unordered or Not Equal ++ LT = 0x04, // Ordered and Less Than ++ GE = 0x05, // Ordered and Greater Than or Equal ++ LE = 0x06, // Ordered and Less Than or Equal ++ GT = 0x07, // Ordered and Greater Than ++}; ++ ++enum CheckForInexactConversion { ++ kCheckForInexactConversion, ++ kDontCheckForInexactConversion ++}; ++ ++enum class MaxMinKind : int { kMin = 0, kMax = 1 }; ++ ++// ---------------------------------------------------------------------------- ++// RISCV flags ++ ++enum ControlStatusReg { ++ csr_fflags = 0x001, // Floating-Point Accrued Exceptions (RW) ++ csr_frm = 0x002, // Floating-Point Dynamic Rounding Mode (RW) ++ csr_fcsr = 0x003, // Floating-Point Control and Status Register (RW) ++ csr_cycle = 0xc00, // Cycle counter for RDCYCLE instruction (RO) ++ csr_time = 0xc01, // Timer for RDTIME instruction (RO) ++ csr_instret = 0xc02, // Insns-retired counter for RDINSTRET instruction (RO) ++ csr_cycleh = 0xc80, // Upper 32 bits of cycle, RV32I only (RO) ++ csr_timeh = 0xc81, // Upper 32 bits of time, RV32I only (RO) ++ csr_instreth = 0xc82 // Upper 32 bits of instret, RV32I only (RO) ++}; ++ ++enum FFlagsMask { ++ kInvalidOperation = 0b10000, // NV: Invalid ++ kDivideByZero = 0b1000, // DZ: Divide by Zero ++ kOverflow = 0b100, // OF: Overflow ++ kUnderflow = 0b10, // UF: Underflow ++ kInexact = 0b1 // NX: Inexact ++}; ++ ++enum RoundingMode { ++ RNE = 0b000, // Round to Nearest, ties to Even ++ RTZ = 0b001, // Round towards Zero ++ RDN = 0b010, // Round Down (towards -infinity) ++ RUP = 0b011, // Round Up (towards +infinity) ++ RMM = 0b100, // Round to Nearest, tiest to Max Magnitude ++ DYN = 0b111 // In instruction's rm field, selects dynamic rounding mode; ++ // In Rounding Mode register, Invalid ++}; ++ ++enum MemoryOdering { ++ PSI = 0b1000, // PI or SI ++ PSO = 0b0100, // PO or SO ++ PSR = 0b0010, // PR or SR ++ PSW = 0b0001, // PW or SW ++ PSIORW = PSI | PSO | PSR | PSW ++}; ++ ++enum FClassFlag { ++ kNegativeInfinity = 1, ++ kNegativeNormalNumber = 1 << 1, ++ kNegativeSubnormalNumber = 1 << 2, ++ kNegativeZero = 1 << 3, ++ kPositiveZero = 1 << 4, ++ kPositiveSubnormalNumber = 1 << 5, ++ kPositiveNormalNumber = 1 << 6, ++ kPositiveInfinity = 1 << 7, ++ kSignalingNaN = 1 << 8, ++ kQuietNaN = 1 << 9 ++}; ++ ++// ----------------------------------------------------------------------------- ++// Hints. ++ ++// Branch hints are not used on RISC-V. They are defined so that they can ++// appear in shared function signatures, but will be ignored in RISC-V ++// implementations. ++enum Hint { no_hint = 0 }; ++ ++inline Hint NegateHint(Hint hint) { return no_hint; } ++ ++// ----------------------------------------------------------------------------- ++// Specific instructions, constants, and masks. ++// These constants are declared in assembler-riscv64.cc, as they use named ++// registers and other constants. ++ ++// An ECALL instruction, used for redirected real time call ++const Instr rtCallRedirInstr = SYSTEM; // All other bits are 0s (i.e., ecall) ++// An EBreak instruction, used for debugging and semi-hosting ++const Instr kBreakInstr = SYSTEM | 1 << kImm12Shift; // ebreak ++ ++constexpr uint8_t kInstrSize = 4; ++constexpr uint8_t kInstrSizeLog2 = 2; ++ ++class InstructionBase { ++ public: ++ enum { ++ // On RISC-V, PC cannot actually be directly accessed. We behave as if PC ++ // was always the value of the current instruction being executed. ++ kPCReadOffset = 0 ++ }; ++ ++ // Instruction type. ++ enum Type { ++ kRType, ++ kR4Type, // Special R4 for Q extension ++ kIType, ++ kSType, ++ kBType, ++ kUType, ++ kJType, ++ kUnsupported = -1 ++ }; ++ ++ // Get the raw instruction bits. ++ inline Instr InstructionBits() const { ++ return *reinterpret_cast(this); ++ } ++ ++ // Set the raw instruction bits to value. ++ inline void SetInstructionBits(Instr value) { ++ *reinterpret_cast(this) = value; ++ } ++ ++ // Read one particular bit out of the instruction bits. ++ inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } ++ ++ // Read a bit field out of the instruction bits. ++ inline int Bits(int hi, int lo) const { ++ return (InstructionBits() >> lo) & ((2U << (hi - lo)) - 1); ++ } ++ ++ // Accessors for the different named fields used in the RISC-V encoding. ++ inline Opcode BaseOpcodeValue() const { ++ return static_cast( ++ Bits(kBaseOpcodeShift + kBaseOpcodeBits - 1, kBaseOpcodeShift)); ++ } ++ ++ // Return the fields at their original place in the instruction encoding. ++ inline Opcode BaseOpcodeFieldRaw() const { ++ return static_cast(InstructionBits() & kBaseOpcodeMask); ++ } ++ ++ // Safe to call within R-type instructions ++ inline int Funct7FieldRaw() const { return InstructionBits() & kFunct7Mask; } ++ ++ // Safe to call within R-, I-, S-, or B-type instructions ++ inline int Funct3FieldRaw() const { return InstructionBits() & kFunct3Mask; } ++ ++ // Safe to call within R-, I-, S-, or B-type instructions ++ inline int Rs1FieldRawNoAssert() const { ++ return InstructionBits() & kRs1FieldMask; ++ } ++ ++ // Safe to call within R-, S-, or B-type instructions ++ inline int Rs2FieldRawNoAssert() const { ++ return InstructionBits() & kRs2FieldMask; ++ } ++ ++ // Safe to call within R4-type instructions ++ inline int Rs3FieldRawNoAssert() const { ++ return InstructionBits() & kRs3FieldMask; ++ } ++ ++ inline int32_t ITypeBits() const { return InstructionBits() & kITypeMask; } ++ ++ // Get the encoding type of the instruction. ++ inline Type InstructionType() const; ++ ++ protected: ++ InstructionBase() {} ++}; ++ ++template ++class InstructionGetters : public T { ++ public: ++ inline int BaseOpcode() const { ++ return this->InstructionBits() & kBaseOpcodeMask; ++ } ++ ++ inline int Rs1Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType || ++ this->InstructionType() == InstructionBase::kR4Type || ++ this->InstructionType() == InstructionBase::kIType || ++ this->InstructionType() == InstructionBase::kSType || ++ this->InstructionType() == InstructionBase::kBType); ++ return this->Bits(kRs1Shift + kRs1Bits - 1, kRs1Shift); ++ } ++ ++ inline int Rs2Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType || ++ this->InstructionType() == InstructionBase::kR4Type || ++ this->InstructionType() == InstructionBase::kSType || ++ this->InstructionType() == InstructionBase::kBType); ++ return this->Bits(kRs2Shift + kRs2Bits - 1, kRs2Shift); ++ } ++ ++ inline int Rs3Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kR4Type); ++ return this->Bits(kRs3Shift + kRs3Bits - 1, kRs3Shift); ++ } ++ ++ inline int RdValue() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType || ++ this->InstructionType() == InstructionBase::kR4Type || ++ this->InstructionType() == InstructionBase::kIType || ++ this->InstructionType() == InstructionBase::kUType || ++ this->InstructionType() == InstructionBase::kJType); ++ return this->Bits(kRdShift + kRdBits - 1, kRdShift); ++ } ++ ++ inline int Funct7Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType); ++ return this->Bits(kFunct7Shift + kFunct7Bits - 1, kFunct7Shift); ++ } ++ ++ inline int Funct3Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType || ++ this->InstructionType() == InstructionBase::kIType || ++ this->InstructionType() == InstructionBase::kSType || ++ this->InstructionType() == InstructionBase::kBType); ++ return this->Bits(kFunct3Shift + kFunct3Bits - 1, kFunct3Shift); ++ } ++ ++ inline int Funct5Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kRType && ++ this->BaseOpcode() == OP_FP); ++ return this->Bits(kFunct5Shift + kFunct5Bits - 1, kFunct5Shift); ++ } ++ ++ inline int CsrValue() const { ++ DCHECK(this->InstructionType() == InstructionBase::kIType && ++ this->BaseOpcode() == SYSTEM); ++ return (this->Bits(kCsrShift + kCsrBits - 1, kCsrShift)); ++ } ++ ++ inline int RoundMode() const { ++ DCHECK((this->InstructionType() == InstructionBase::kRType || ++ this->InstructionType() == InstructionBase::kR4Type) && ++ this->BaseOpcode() == OP_FP); ++ return this->Bits(kFunct3Shift + kFunct3Bits - 1, kFunct3Shift); ++ } ++ ++ inline int MemoryOrder(bool is_pred) const { ++ DCHECK((this->InstructionType() == InstructionBase::kIType && ++ this->BaseOpcode() == MISC_MEM)); ++ if (is_pred) { ++ return this->Bits(kPredOrderShift + kMemOrderBits - 1, kPredOrderShift); ++ } else { ++ return this->Bits(kSuccOrderShift + kMemOrderBits - 1, kSuccOrderShift); ++ } ++ } ++ ++ inline int Imm12Value() const { ++ DCHECK(this->InstructionType() == InstructionBase::kIType); ++ int Value = this->Bits(kImm12Shift + kImm12Bits - 1, kImm12Shift); ++ return Value << 20 >> 20; ++ } ++ ++ inline int32_t Imm12SExtValue() const { ++ int32_t Value = this->Imm12Value() << 20 >> 20; ++ return Value; ++ } ++ ++ inline int BranchOffset() const { ++ DCHECK(this->InstructionType() == InstructionBase::kBType); ++ // | imm[12|10:5] | rs2 | rs1 | funct3 | imm[4:1|11] | opcode | ++ // 31 25 11 7 ++ uint32_t Bits = this->InstructionBits(); ++ int16_t imm13 = ((Bits & 0xf00) >> 7) | ((Bits & 0x7e000000) >> 20) | ++ ((Bits & 0x80) << 4) | ((Bits & 0x80000000) >> 19); ++ return imm13 << 19 >> 19; ++ } ++ ++ inline int StoreOffset() const { ++ DCHECK(this->InstructionType() == InstructionBase::kSType); ++ // | imm[11:5] | rs2 | rs1 | funct3 | imm[4:0] | opcode | ++ // 31 25 11 7 ++ uint32_t Bits = this->InstructionBits(); ++ int16_t imm12 = ((Bits & 0xf80) >> 7) | ((Bits & 0xfe000000) >> 20); ++ return imm12 << 20 >> 20; ++ } ++ ++ inline int Imm20UValue() const { ++ DCHECK(this->InstructionType() == InstructionBase::kUType); ++ // | imm[31:12] | rd | opcode | ++ // 31 12 ++ int32_t Bits = this->InstructionBits(); ++ return Bits >> 12; ++ } ++ ++ inline int Imm20JValue() const { ++ DCHECK(this->InstructionType() == InstructionBase::kJType); ++ // | imm[20|10:1|11|19:12] | rd | opcode | ++ // 31 12 ++ uint32_t Bits = this->InstructionBits(); ++ int32_t imm20 = ((Bits & 0x7fe00000) >> 20) | ((Bits & 0x100000) >> 9) | ++ (Bits & 0xff000) | ((Bits & 0x80000000) >> 11); ++ return imm20 << 11 >> 11; ++ } ++ ++ inline bool IsArithShift() const { ++ // Valid only for right shift operations ++ DCHECK((this->BaseOpcode() == OP || this->BaseOpcode() == OP_32 || ++ this->BaseOpcode() == OP_IMM || this->BaseOpcode() == OP_IMM_32) && ++ this->Funct3Value() == 0b101); ++ return this->InstructionBits() & 0x40000000; ++ } ++ ++ inline int Shamt() const { ++ // Valid only for shift instructions (SLLI, SRLI, SRAI) ++ DCHECK((this->InstructionBits() & kBaseOpcodeMask) == OP_IMM && ++ (this->Funct3Value() == 0b001 || this->Funct3Value() == 0b101)); ++ // | 0A0000 | shamt | rs1 | funct3 | rd | opcode | ++ // 31 25 20 ++ return this->Bits(kImm12Shift + 5, kImm12Shift); ++ } ++ ++ inline int Shamt32() const { ++ // Valid only for shift instructions (SLLIW, SRLIW, SRAIW) ++ DCHECK((this->InstructionBits() & kBaseOpcodeMask) == OP_IMM_32 && ++ (this->Funct3Value() == 0b001 || this->Funct3Value() == 0b101)); ++ // | 0A00000 | shamt | rs1 | funct3 | rd | opcode | ++ // 31 24 20 ++ return this->Bits(kImm12Shift + 4, kImm12Shift); ++ } ++ ++ inline bool AqValue() const { return this->Bits(kAqShift, kAqShift); } ++ ++ inline bool RlValue() const { return this->Bits(kRlShift, kRlShift); } ++ ++ // Say if the instruction is a break or a trap. ++ bool IsTrap() const; ++}; ++ ++class Instruction : public InstructionGetters { ++ public: ++ // Instructions are read of out a code stream. The only way to get a ++ // reference to an instruction is to convert a pointer. There is no way ++ // to allocate or create instances of class Instruction. ++ // Use the At(pc) function to create references to Instruction. ++ static Instruction* At(byte* pc) { ++ return reinterpret_cast(pc); ++ } ++ ++ private: ++ // We need to prevent the creation of instances of class Instruction. ++ DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction); ++}; ++ ++// ----------------------------------------------------------------------------- ++// RISC-V assembly various constants. ++ ++// C/C++ argument slots size. ++const int kCArgSlotCount = 0; ++ ++// TODO(plind): below should be based on kPointerSize ++// TODO(plind): find all usages and remove the needless instructions for n64. ++const int kCArgsSlotsSize = kCArgSlotCount * kInstrSize * 2; ++ ++const int kInvalidStackOffset = -1; ++const int kBranchReturnOffset = 2 * kInstrSize; ++ ++static const int kNegOffset = 0x00008000; ++ ++InstructionBase::Type InstructionBase::InstructionType() const { ++ // RISCV routine ++ switch (InstructionBits() & kBaseOpcodeMask) { ++ case LOAD: ++ return kIType; ++ case LOAD_FP: ++ return kIType; ++ case MISC_MEM: ++ return kIType; ++ case OP_IMM: ++ return kIType; ++ case AUIPC: ++ return kUType; ++ case OP_IMM_32: ++ return kIType; ++ case STORE: ++ return kSType; ++ case STORE_FP: ++ return kSType; ++ case AMO: ++ return kRType; ++ case OP: ++ return kRType; ++ case LUI: ++ return kUType; ++ case OP_32: ++ return kRType; ++ case MADD: ++ case MSUB: ++ case NMSUB: ++ case NMADD: ++ return kR4Type; ++ case OP_FP: ++ return kRType; ++ case BRANCH: ++ return kBType; ++ case JALR: ++ return kIType; ++ case JAL: ++ return kJType; ++ case SYSTEM: ++ return kIType; ++ } ++ return kUnsupported; ++} ++ ++// ----------------------------------------------------------------------------- ++// Instructions. ++ ++template ++bool InstructionGetters

::IsTrap() const { ++ return (this->InstructionBits() == kBreakInstr); ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_CODEGEN_RISCV_CONSTANTS_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/cpu-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/cpu-riscv64.cc +@@ -0,0 +1,28 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++// CPU specific code for arm independent of OS goes here. ++ ++#include ++#include ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/cpu-features.h" ++ ++namespace v8 { ++namespace internal { ++ ++void CpuFeatures::FlushICache(void* start, size_t size) { ++#if !defined(USE_SIMULATOR) ++ // FIXME(RISCV): builtin_clear_cache doesn't work yet, so use `fence.i` for now ++ // __builtin___clear_cache(start, (char *)start + size); ++ asm volatile("fence.i" ::: "memory"); ++#endif // !USE_SIMULATOR. ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/interface-descriptors-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/interface-descriptors-riscv64.cc +@@ -0,0 +1,348 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/interface-descriptors.h" ++#include "src/execution/frames.h" ++ ++namespace v8 { ++namespace internal { ++ ++const Register CallInterfaceDescriptor::ContextRegister() { return cp; } ++ ++void CallInterfaceDescriptor::DefaultInitializePlatformSpecific( ++ CallInterfaceDescriptorData* data, int register_parameter_count) { ++ const Register default_stub_registers[] = {a0, a1, a2, a3, a4}; ++ CHECK_LE(static_cast(register_parameter_count), ++ arraysize(default_stub_registers)); ++ data->InitializePlatformSpecific(register_parameter_count, ++ default_stub_registers); ++} ++ ++void WasmI32AtomicWait32Descriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ const Register default_stub_registers[] = {a0, a1, a2, a3}; ++ CHECK_EQ(static_cast(kParameterCount), ++ arraysize(default_stub_registers)); ++ data->InitializePlatformSpecific(kParameterCount, default_stub_registers); ++} ++ ++void WasmI64AtomicWait32Descriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ const Register default_stub_registers[] = {a0, a1, a2, a3, a4}; ++ CHECK_EQ(static_cast(kParameterCount - kStackArgumentsCount), ++ arraysize(default_stub_registers)); ++ data->InitializePlatformSpecific(kParameterCount - kStackArgumentsCount, ++ default_stub_registers); ++} ++ ++void RecordWriteDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ const Register default_stub_registers[] = {a0, a1, a2, a3, kReturnRegister0}; ++ ++ data->RestrictAllocatableRegisters(default_stub_registers, ++ arraysize(default_stub_registers)); ++ ++ CHECK_LE(static_cast(kParameterCount), ++ arraysize(default_stub_registers)); ++ data->InitializePlatformSpecific(kParameterCount, default_stub_registers); ++} ++ ++void EphemeronKeyBarrierDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ const Register default_stub_registers[] = {a0, a1, a2, a3, kReturnRegister0}; ++ ++ data->RestrictAllocatableRegisters(default_stub_registers, ++ arraysize(default_stub_registers)); ++ ++ CHECK_LE(static_cast(kParameterCount), ++ arraysize(default_stub_registers)); ++ data->InitializePlatformSpecific(kParameterCount, default_stub_registers); ++} ++ ++const Register LoadDescriptor::ReceiverRegister() { return a1; } ++const Register LoadDescriptor::NameRegister() { return a2; } ++const Register LoadDescriptor::SlotRegister() { return a0; } ++ ++const Register LoadWithVectorDescriptor::VectorRegister() { return a3; } ++ ++const Register ++LoadWithReceiverAndVectorDescriptor::LookupStartObjectRegister() { ++ return a4; ++} ++ ++const Register StoreDescriptor::ReceiverRegister() { return a1; } ++const Register StoreDescriptor::NameRegister() { return a2; } ++const Register StoreDescriptor::ValueRegister() { return a0; } ++const Register StoreDescriptor::SlotRegister() { return a4; } ++ ++const Register StoreWithVectorDescriptor::VectorRegister() { return a3; } ++ ++const Register StoreTransitionDescriptor::SlotRegister() { return a4; } ++const Register StoreTransitionDescriptor::VectorRegister() { return a3; } ++const Register StoreTransitionDescriptor::MapRegister() { return a5; } ++ ++const Register ApiGetterDescriptor::HolderRegister() { return a0; } ++const Register ApiGetterDescriptor::CallbackRegister() { return a3; } ++ ++const Register GrowArrayElementsDescriptor::ObjectRegister() { return a0; } ++const Register GrowArrayElementsDescriptor::KeyRegister() { return a3; } ++ ++// static ++const Register TypeConversionDescriptor::ArgumentRegister() { return a0; } ++ ++void TypeofDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = {a3}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallTrampolineDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1: target ++ // a0: number of arguments ++ Register registers[] = {a1, a0}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallVarargsDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a0 : number of arguments (on the stack, not including receiver) ++ // a1 : the target to call ++ // a4 : arguments list length (untagged) ++ // a2 : arguments list (FixedArray) ++ Register registers[] = {a1, a0, a4, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallForwardVarargsDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1: the target to call ++ // a0: number of arguments ++ // a2: start index (to support rest parameters) ++ Register registers[] = {a1, a0, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallFunctionTemplateDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1 : function template info ++ // a0 : number of arguments (on the stack, not including receiver) ++ Register registers[] = {a1, a0}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallWithSpreadDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a0 : number of arguments (on the stack, not including receiver) ++ // a1 : the target to call ++ // a2 : the object to spread ++ Register registers[] = {a1, a0, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CallWithArrayLikeDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1 : the target to call ++ // a2 : the arguments list ++ Register registers[] = {a1, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ConstructVarargsDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a0 : number of arguments (on the stack, not including receiver) ++ // a1 : the target to call ++ // a3 : the new target ++ // a4 : arguments list length (untagged) ++ // a2 : arguments list (FixedArray) ++ Register registers[] = {a1, a3, a0, a4, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ConstructForwardVarargsDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1: the target to call ++ // a3: new target ++ // a0: number of arguments ++ // a2: start index (to support rest parameters) ++ Register registers[] = {a1, a3, a0, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ConstructWithSpreadDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a0 : number of arguments (on the stack, not including receiver) ++ // a1 : the target to call ++ // a3 : the new target ++ // a2 : the object to spread ++ Register registers[] = {a1, a3, a0, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ConstructWithArrayLikeDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1 : the target to call ++ // a3 : the new target ++ // a2 : the arguments list ++ Register registers[] = {a1, a3, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ConstructStubDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // a1: target ++ // a3: new target ++ // a0: number of arguments ++ // a2: allocation site or undefined ++ Register registers[] = {a1, a3, a0, a2}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void AbortDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = {a0}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void CompareDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = {a1, a0}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void BinaryOpDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = {a1, a0}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ArgumentsAdaptorDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a1, // JSFunction ++ a3, // the new target ++ a0, // actual number of arguments ++ a2, // expected number of arguments ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ApiCallbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a1, // kApiFunctionAddress ++ a2, // kArgc ++ a3, // kCallData ++ a0, // kHolder ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void InterpreterDispatchDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ kInterpreterAccumulatorRegister, kInterpreterBytecodeOffsetRegister, ++ kInterpreterBytecodeArrayRegister, kInterpreterDispatchTableRegister}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void InterpreterPushArgsThenCallDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a0, // argument count (not including receiver) ++ a2, // address of first argument ++ a1 // the target callable to be call ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void InterpreterPushArgsThenConstructDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a0, // argument count (not including receiver) ++ a4, // address of the first argument ++ a1, // constructor to call ++ a3, // new target ++ a2, // allocation site feedback if available, undefined otherwise ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void ResumeGeneratorDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a0, // the value to pass to the generator ++ a1 // the JSGeneratorObject to resume ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void FrameDropperTrampolineDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = { ++ a1, // loaded new FP ++ }; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void RunMicrotasksEntryDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ Register registers[] = {a0, a1}; ++ data->InitializePlatformSpecific(arraysize(registers), registers); ++} ++ ++void BinaryOp_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void CallTrampoline_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void CallWithArrayLike_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void CallWithSpread_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void ConstructWithArrayLike_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void ConstructWithSpread_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void Compare_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 4); ++} ++ ++void UnaryOp_WithFeedbackDescriptor::InitializePlatformSpecific( ++ CallInterfaceDescriptorData* data) { ++ // TODO(v8:8888): Implement on this platform. ++ DefaultInitializePlatformSpecific(data, 3); ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/macro-assembler-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/macro-assembler-riscv64.cc +@@ -0,0 +1,4336 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#include // For LONG_MIN, LONG_MAX. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/base/bits.h" ++#include "src/base/division-by-constant.h" ++#include "src/codegen/assembler-inl.h" ++#include "src/codegen/callable.h" ++#include "src/codegen/code-factory.h" ++#include "src/codegen/external-reference-table.h" ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/register-configuration.h" ++#include "src/debug/debug.h" ++#include "src/execution/frames-inl.h" ++#include "src/heap/memory-chunk.h" ++#include "src/init/bootstrapper.h" ++#include "src/logging/counters.h" ++#include "src/objects/heap-number.h" ++#include "src/runtime/runtime.h" ++#include "src/snapshot/embedded/embedded-data.h" ++#include "src/snapshot/snapshot.h" ++#include "src/wasm/wasm-code-manager.h" ++ ++// Satisfy cpplint check, but don't include platform-specific header. It is ++// included recursively via macro-assembler.h. ++#if 0 ++#include "src/codegen/riscv64/macro-assembler-riscv64.h" ++#endif ++ ++namespace v8 { ++namespace internal { ++ ++static inline bool IsZero(const Operand& rt) { ++ if (rt.is_reg()) { ++ return rt.rm() == zero_reg; ++ } else { ++ return rt.immediate() == 0; ++ } ++} ++ ++int TurboAssembler::RequiredStackSizeForCallerSaved(SaveFPRegsMode fp_mode, ++ Register exclusion1, ++ Register exclusion2, ++ Register exclusion3) const { ++ int bytes = 0; ++ RegList exclusions = 0; ++ if (exclusion1 != no_reg) { ++ exclusions |= exclusion1.bit(); ++ if (exclusion2 != no_reg) { ++ exclusions |= exclusion2.bit(); ++ if (exclusion3 != no_reg) { ++ exclusions |= exclusion3.bit(); ++ } ++ } ++ } ++ ++ RegList list = kJSCallerSaved & ~exclusions; ++ bytes += NumRegs(list) * kPointerSize; ++ ++ if (fp_mode == kSaveFPRegs) { ++ bytes += NumRegs(kCallerSavedFPU) * kDoubleSize; ++ } ++ ++ return bytes; ++} ++ ++int TurboAssembler::PushCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1, ++ Register exclusion2, Register exclusion3) { ++ int bytes = 0; ++ RegList exclusions = 0; ++ if (exclusion1 != no_reg) { ++ exclusions |= exclusion1.bit(); ++ if (exclusion2 != no_reg) { ++ exclusions |= exclusion2.bit(); ++ if (exclusion3 != no_reg) { ++ exclusions |= exclusion3.bit(); ++ } ++ } ++ } ++ ++ RegList list = kJSCallerSaved & ~exclusions; ++ MultiPush(list); ++ bytes += NumRegs(list) * kPointerSize; ++ ++ if (fp_mode == kSaveFPRegs) { ++ MultiPushFPU(kCallerSavedFPU); ++ bytes += NumRegs(kCallerSavedFPU) * kDoubleSize; ++ } ++ ++ return bytes; ++} ++ ++int TurboAssembler::PopCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1, ++ Register exclusion2, Register exclusion3) { ++ int bytes = 0; ++ if (fp_mode == kSaveFPRegs) { ++ MultiPopFPU(kCallerSavedFPU); ++ bytes += NumRegs(kCallerSavedFPU) * kDoubleSize; ++ } ++ ++ RegList exclusions = 0; ++ if (exclusion1 != no_reg) { ++ exclusions |= exclusion1.bit(); ++ if (exclusion2 != no_reg) { ++ exclusions |= exclusion2.bit(); ++ if (exclusion3 != no_reg) { ++ exclusions |= exclusion3.bit(); ++ } ++ } ++ } ++ ++ RegList list = kJSCallerSaved & ~exclusions; ++ MultiPop(list); ++ bytes += NumRegs(list) * kPointerSize; ++ ++ return bytes; ++} ++ ++void TurboAssembler::LoadRoot(Register destination, RootIndex index) { ++ Ld(destination, MemOperand(s6, RootRegisterOffsetForRootIndex(index))); ++} ++ ++void TurboAssembler::LoadRoot(Register destination, RootIndex index, ++ Condition cond, Register src1, ++ const Operand& src2) { ++ Label skip; ++ Branch(&skip, NegateCondition(cond), src1, src2); ++ Ld(destination, MemOperand(s6, RootRegisterOffsetForRootIndex(index))); ++ bind(&skip); ++} ++ ++void TurboAssembler::PushCommonFrame(Register marker_reg) { ++ if (marker_reg.is_valid()) { ++ Push(ra, fp, marker_reg); ++ Add64(fp, sp, Operand(kPointerSize)); ++ } else { ++ Push(ra, fp); ++ mv(fp, sp); ++ } ++} ++ ++void TurboAssembler::PushStandardFrame(Register function_reg) { ++ int offset = -StandardFrameConstants::kContextOffset; ++ if (function_reg.is_valid()) { ++ Push(ra, fp, cp, function_reg); ++ offset += kPointerSize; ++ } else { ++ Push(ra, fp, cp); ++ } ++ Add64(fp, sp, Operand(offset)); ++} ++ ++int MacroAssembler::SafepointRegisterStackIndex(int reg_code) { ++ // The registers are pushed starting with the highest encoding, ++ // which means that lowest encodings are closest to the stack pointer. ++ return kSafepointRegisterStackIndexMap[reg_code]; ++} ++ ++// Clobbers object, dst, value, and ra, if (ra_status == kRAHasBeenSaved) ++// The register 'object' contains a heap object pointer. The heap object ++// tag is shifted away. ++void MacroAssembler::RecordWriteField(Register object, int offset, ++ Register value, Register dst, ++ RAStatus ra_status, ++ SaveFPRegsMode save_fp, ++ RememberedSetAction remembered_set_action, ++ SmiCheck smi_check) { ++ DCHECK(!AreAliased(value, dst, t5, object)); ++ // First, check if a write barrier is even needed. The tests below ++ // catch stores of Smis. ++ Label done; ++ ++ // Skip barrier if writing a smi. ++ if (smi_check == INLINE_SMI_CHECK) { ++ JumpIfSmi(value, &done); ++ } ++ ++ // Although the object register is tagged, the offset is relative to the start ++ // of the object, so so offset must be a multiple of kPointerSize. ++ DCHECK(IsAligned(offset, kPointerSize)); ++ ++ Add64(dst, object, Operand(offset - kHeapObjectTag)); ++ if (emit_debug_code()) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Label ok; ++ And(t5, dst, Operand(kPointerSize - 1)); ++ Branch(&ok, eq, t5, Operand(zero_reg)); ++ ebreak(); ++ bind(&ok); ++ } ++ ++ RecordWrite(object, dst, value, ra_status, save_fp, remembered_set_action, ++ OMIT_SMI_CHECK); ++ ++ bind(&done); ++ ++ // Clobber clobbered input registers when running with the debug-code flag ++ // turned on to provoke errors. ++ if (emit_debug_code()) { ++ li(value, Operand(bit_cast(kZapValue + 4))); ++ li(dst, Operand(bit_cast(kZapValue + 8))); ++ } ++} ++ ++void TurboAssembler::SaveRegisters(RegList registers) { ++ DCHECK_GT(NumRegs(registers), 0); ++ RegList regs = 0; ++ for (int i = 0; i < Register::kNumRegisters; ++i) { ++ if ((registers >> i) & 1u) { ++ regs |= Register::from_code(i).bit(); ++ } ++ } ++ MultiPush(regs); ++} ++ ++void TurboAssembler::RestoreRegisters(RegList registers) { ++ DCHECK_GT(NumRegs(registers), 0); ++ RegList regs = 0; ++ for (int i = 0; i < Register::kNumRegisters; ++i) { ++ if ((registers >> i) & 1u) { ++ regs |= Register::from_code(i).bit(); ++ } ++ } ++ MultiPop(regs); ++} ++ ++void TurboAssembler::CallEphemeronKeyBarrier(Register object, Register address, ++ SaveFPRegsMode fp_mode) { ++ EphemeronKeyBarrierDescriptor descriptor; ++ RegList registers = descriptor.allocatable_registers(); ++ ++ SaveRegisters(registers); ++ ++ Register object_parameter( ++ descriptor.GetRegisterParameter(EphemeronKeyBarrierDescriptor::kObject)); ++ Register slot_parameter(descriptor.GetRegisterParameter( ++ EphemeronKeyBarrierDescriptor::kSlotAddress)); ++ Register fp_mode_parameter( ++ descriptor.GetRegisterParameter(EphemeronKeyBarrierDescriptor::kFPMode)); ++ ++ Push(object); ++ Push(address); ++ ++ Pop(slot_parameter); ++ Pop(object_parameter); ++ ++ Move(fp_mode_parameter, Smi::FromEnum(fp_mode)); ++ Call(isolate()->builtins()->builtin_handle(Builtins::kEphemeronKeyBarrier), ++ RelocInfo::CODE_TARGET); ++ RestoreRegisters(registers); ++} ++ ++void TurboAssembler::CallRecordWriteStub( ++ Register object, Register address, ++ RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode) { ++ CallRecordWriteStub( ++ object, address, remembered_set_action, fp_mode, ++ isolate()->builtins()->builtin_handle(Builtins::kRecordWrite), ++ kNullAddress); ++} ++ ++void TurboAssembler::CallRecordWriteStub( ++ Register object, Register address, ++ RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ Address wasm_target) { ++ CallRecordWriteStub(object, address, remembered_set_action, fp_mode, ++ Handle::null(), wasm_target); ++} ++ ++void TurboAssembler::CallRecordWriteStub( ++ Register object, Register address, ++ RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode, ++ Handle code_target, Address wasm_target) { ++ DCHECK_NE(code_target.is_null(), wasm_target == kNullAddress); ++ // TODO(albertnetymk): For now we ignore remembered_set_action and fp_mode, ++ // i.e. always emit remember set and save FP registers in RecordWriteStub. If ++ // large performance regression is observed, we should use these values to ++ // avoid unnecessary work. ++ ++ RecordWriteDescriptor descriptor; ++ RegList registers = descriptor.allocatable_registers(); ++ ++ SaveRegisters(registers); ++ Register object_parameter( ++ descriptor.GetRegisterParameter(RecordWriteDescriptor::kObject)); ++ Register slot_parameter( ++ descriptor.GetRegisterParameter(RecordWriteDescriptor::kSlot)); ++ Register remembered_set_parameter( ++ descriptor.GetRegisterParameter(RecordWriteDescriptor::kRememberedSet)); ++ Register fp_mode_parameter( ++ descriptor.GetRegisterParameter(RecordWriteDescriptor::kFPMode)); ++ ++ Push(object); ++ Push(address); ++ ++ Pop(slot_parameter); ++ Pop(object_parameter); ++ ++ Move(remembered_set_parameter, Smi::FromEnum(remembered_set_action)); ++ Move(fp_mode_parameter, Smi::FromEnum(fp_mode)); ++ if (code_target.is_null()) { ++ Call(wasm_target, RelocInfo::WASM_STUB_CALL); ++ } else { ++ Call(code_target, RelocInfo::CODE_TARGET); ++ } ++ ++ RestoreRegisters(registers); ++} ++ ++// Clobbers object, address, value, and ra, if (ra_status == kRAHasBeenSaved) ++// The register 'object' contains a heap object pointer. The heap object ++// tag is shifted away. ++void MacroAssembler::RecordWrite(Register object, Register address, ++ Register value, RAStatus ra_status, ++ SaveFPRegsMode fp_mode, ++ RememberedSetAction remembered_set_action, ++ SmiCheck smi_check) { ++ DCHECK(!AreAliased(object, address, value, t5)); ++ DCHECK(!AreAliased(object, address, value, t6)); ++ ++ if (emit_debug_code()) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Ld(scratch, MemOperand(address)); ++ Assert(eq, AbortReason::kWrongAddressOrValuePassedToRecordWrite, scratch, ++ Operand(value)); ++ } ++ ++ if ((remembered_set_action == OMIT_REMEMBERED_SET && ++ !FLAG_incremental_marking) || ++ FLAG_disable_write_barriers) { ++ return; ++ } ++ ++ // First, check if a write barrier is even needed. The tests below ++ // catch stores of smis and stores into the young generation. ++ Label done; ++ ++ if (smi_check == INLINE_SMI_CHECK) { ++ DCHECK_EQ(0, kSmiTag); ++ JumpIfSmi(value, &done); ++ } ++ ++ CheckPageFlag(value, ++ value, // Used as scratch. ++ MemoryChunk::kPointersToHereAreInterestingMask, eq, &done); ++ CheckPageFlag(object, ++ value, // Used as scratch. ++ MemoryChunk::kPointersFromHereAreInterestingMask, eq, &done); ++ ++ // Record the actual write. ++ if (ra_status == kRAHasNotBeenSaved) { ++ push(ra); ++ } ++ CallRecordWriteStub(object, address, remembered_set_action, fp_mode); ++ if (ra_status == kRAHasNotBeenSaved) { ++ pop(ra); ++ } ++ ++ bind(&done); ++ ++ // Clobber clobbered registers when running with the debug-code flag ++ // turned on to provoke errors. ++ if (emit_debug_code()) { ++ li(address, Operand(bit_cast(kZapValue + 12))); ++ li(value, Operand(bit_cast(kZapValue + 16))); ++ } ++} ++ ++// --------------------------------------------------------------------------- ++// Instruction macros. ++ ++void TurboAssembler::Add32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ addw(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ addiw(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ addw(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Add64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ add(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ addi(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ // Register scratch = temps.Acquire(); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ add(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Sub32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ subw(rd, rs, rt.rm()); ++ } else { ++ DCHECK(is_int32(rt.immediate())); ++ if (is_int12(-rt.immediate()) && !MustUseReg(rt.rmode())) { ++ addiw(rd, rs, ++ static_cast( ++ -rt.immediate())); // No subiw instr, use addiw(x, y, -imm). ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ if (-rt.immediate() >> 12 == 0 && !MustUseReg(rt.rmode())) { ++ // Use load -imm and addu when loading -imm generates one instruction. ++ RV_li(scratch, -rt.immediate()); ++ addw(rd, rs, scratch); ++ } else { ++ // li handles the relocation. ++ RV_li(scratch, rt.immediate()); ++ subw(rd, rs, scratch); ++ } ++ } ++ } ++} ++ ++void TurboAssembler::Sub64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ sub(rd, rs, rt.rm()); ++ } else if (is_int12(-rt.immediate()) && !MustUseReg(rt.rmode())) { ++ addi(rd, rs, ++ static_cast( ++ -rt.immediate())); // No subi instr, use addi(x, y, -imm). ++ } else { ++ DCHECK(rs != t3); ++ int li_count = InstrCountForLi64Bit(rt.immediate()); ++ int li_neg_count = InstrCountForLi64Bit(-rt.immediate()); ++ if (li_neg_count < li_count && !MustUseReg(rt.rmode())) { ++ // Use load -imm and add when loading -imm generates one instruction. ++ DCHECK(rt.immediate() != std::numeric_limits::min()); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ RV_li(scratch, -rt.immediate()); ++ add(rd, rs, scratch); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ RV_li(scratch, rt.immediate()); ++ sub(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Mul32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ mulw(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ mulw(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Mulh32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ mul(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ mul(rd, rs, scratch); ++ } ++ srai(rd, rd, 32); ++} ++ ++void TurboAssembler::Mulhu32(Register rd, Register rs, const Operand& rt, ++ Register rsz, Register rtz) { ++ slli(rsz, rs, 32); ++ if (rt.is_reg()) ++ slli(rtz, rt.rm(), 32); ++ else ++ RV_li(rtz, rt.immediate() << 32); ++ mulhu(rd, rsz, rtz); ++ srai(rd, rd, 32); ++} ++ ++void TurboAssembler::Mul64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ mul(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ mul(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Mulh64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ mulh(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ mulh(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Div32(Register res, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ divw(res, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ divw(res, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Mod32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ remw(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ remw(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Modu32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ remuw(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ remuw(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Div64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ div(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ div(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Divu32(Register res, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ divuw(res, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ divuw(res, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Divu64(Register res, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ divu(res, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ divu(res, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Mod64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ rem(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ rem(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::Modu64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ remu(rd, rs, rt.rm()); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ remu(rd, rs, scratch); ++ } ++} ++ ++void TurboAssembler::And(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ and_(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ andi(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ and_(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Or(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ or_(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ ori(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ or_(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Xor(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ xor_(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ xori(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ xor_(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Nor(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ or_(rd, rs, rt.rm()); ++ not_(rd, rd); ++ } else { ++ Or(rd, rs, rt); ++ not_(rd, rd); ++ } ++} ++ ++void TurboAssembler::Neg(Register rs, const Operand& rt) { ++ DCHECK(rt.is_reg()); ++ neg(rs, rt.rm()); ++} ++ ++void TurboAssembler::Seqz(Register rd, const Operand& rt) { ++ if (rt.is_reg()) { ++ seqz(rd, rt.rm()); ++ } else { ++ li(rd, rt.immediate() == 0); ++ } ++} ++ ++void TurboAssembler::Snez(Register rd, const Operand& rt) { ++ if (rt.is_reg()) { ++ snez(rd, rt.rm()); ++ } else { ++ li(rd, rt.immediate() != 0); ++ } ++} ++ ++void TurboAssembler::Seq(Register rd, Register rs, const Operand& rt) { ++ if (rs == zero_reg) { ++ Seqz(rd, rt); ++ } else if (IsZero(rt)) { ++ seqz(rd, rs); ++ } else { ++ Sub64(rd, rs, rt); ++ seqz(rd, rd); ++ } ++} ++ ++void TurboAssembler::Sne(Register rd, Register rs, const Operand& rt) { ++ if (rs == zero_reg) { ++ Snez(rd, rt); ++ } else if (IsZero(rt)) { ++ snez(rd, rs); ++ } else { ++ Sub64(rd, rs, rt); ++ snez(rd, rd); ++ } ++} ++ ++void TurboAssembler::Slt(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ slt(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ slti(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ slt(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Sltu(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ sltu(rd, rs, rt.rm()); ++ } else { ++ if (is_int12(rt.immediate()) && !MustUseReg(rt.rmode())) { ++ sltiu(rd, rs, static_cast(rt.immediate())); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ sltu(rd, rs, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::Sle(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ slt(rd, rt.rm(), rs); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ slt(rd, scratch, rs); ++ } ++ xori(rd, rd, 1); ++} ++ ++void TurboAssembler::Sleu(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ sltu(rd, rt.rm(), rs); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ sltu(rd, scratch, rs); ++ } ++ xori(rd, rd, 1); ++} ++ ++void TurboAssembler::Sge(Register rd, Register rs, const Operand& rt) { ++ Slt(rd, rs, rt); ++ xori(rd, rd, 1); ++} ++ ++void TurboAssembler::Sgeu(Register rd, Register rs, const Operand& rt) { ++ Sltu(rd, rs, rt); ++ xori(rd, rd, 1); ++} ++ ++void TurboAssembler::Sgt(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ slt(rd, rt.rm(), rs); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ slt(rd, scratch, rs); ++ } ++} ++ ++void TurboAssembler::Sgtu(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) { ++ sltu(rd, rt.rm(), rs); ++ } else { ++ // li handles the relocation. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ DCHECK(rs != scratch); ++ RV_li(scratch, rt.immediate()); ++ sltu(rd, scratch, rs); ++ } ++} ++ ++void TurboAssembler::Sll32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ sllw(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ slliw(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Sra32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ sraw(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ sraiw(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Srl32(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ srlw(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ srliw(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Sra64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ sra(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ srai(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Srl64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ srl(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ srli(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Sll64(Register rd, Register rs, const Operand& rt) { ++ if (rt.is_reg()) ++ sll(rd, rs, rt.rm()); ++ else { ++ uint8_t shamt = static_cast(rt.immediate()); ++ slli(rd, rs, shamt); ++ } ++} ++ ++void TurboAssembler::Ror(Register rd, Register rs, const Operand& rt) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ if (rt.is_reg()) { ++ negw(scratch, rt.rm()); ++ sllw(scratch, rs, scratch); ++ srlw(rd, rs, rt.rm()); ++ or_(rd, scratch, rd); ++ sext_w(rd, rd); ++ } else { ++ int64_t ror_value = rt.immediate() % 32; ++ if (ror_value == 0) { ++ mv(rd, rs); ++ return; ++ } else if (ror_value < 0) { ++ ror_value += 32; ++ } ++ srliw(scratch, rs, ror_value); ++ slliw(rd, rs, 32 - ror_value); ++ or_(rd, scratch, rd); ++ sext_w(rd, rd); ++ } ++} ++ ++void TurboAssembler::Dror(Register rd, Register rs, const Operand& rt) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ DCHECK(rs != scratch); ++ if (rt.is_reg()) { ++ negw(scratch, rt.rm()); ++ sll(scratch, rs, scratch); ++ srl(rd, rs, rt.rm()); ++ or_(rd, scratch, rd); ++ } else { ++ int64_t dror_value = rt.immediate() % 64; ++ if (dror_value == 0) { ++ mv(rd, rs); ++ return; ++ } else if (dror_value < 0) { ++ dror_value += 64; ++ } ++ srli(scratch, rs, dror_value); ++ slli(rd, rs, 64 - dror_value); ++ or_(rd, scratch, rd); ++ } ++} ++ ++void TurboAssembler::CalcScaledAddress(Register rd, Register rt, Register rs, ++ uint8_t sa, Register scratch) { ++ DCHECK(sa >= 1 && sa <= 31); ++ Register tmp = rd == rt ? scratch : rd; ++ DCHECK(tmp != rt); ++ slli(tmp, rs, sa); ++ Add64(rd, rt, tmp); ++} ++ ++// ------------Pseudo-instructions------------- ++// Change endianness ++void TurboAssembler::ByteSwap(Register rd, Register rs, int operand_size) { ++ DCHECK(operand_size == 4 || operand_size == 8); ++ DCHECK(rd != t5 && rd != t6); ++ if (operand_size == 4) { ++ // Uint32_t t5 = 0x00FF00FF; ++ // x = (x << 16 | x >> 16); ++ // x = (((x & t5) << 8) | ((x & (t5 << 8)) >> 8)); ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register x = temps.Acquire(); ++ li(t5, 0x00FF00FF); ++ slliw(x, rs, 16); ++ srliw(rd, rs, 16); ++ or_(x, rd, x); // x <- x << 16 | x >> 16 ++ and_(t6, x, t5); // t <- x & 0x00FF00FF ++ slliw(t6, t6, 8); // t <- (x & t5) << 8 ++ slliw(t5, t5, 8); // t5 <- 0xFF00FF00 ++ and_(rd, x, t5); // x & 0xFF00FF00 ++ srliw(rd, rd, 8); ++ or_(rd, rd, t6); // (((x & t5) << 8) | ((x & (t5 << 8)) >> 8)) ++ } else { ++ // uint64_t t5 = 0x0000FFFF0000FFFFl; ++ // uint64_t t5 = 0x00FF00FF00FF00FFl; ++ // x = (x << 32 | x >> 32); ++ // x = (x & t5) << 16 | (x & (t5 << 16)) >> 16; ++ // x = (x & t5) << 8 | (x & (t5 << 8)) >> 8; ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register x = temps.Acquire(); ++ li(t5, 0x0000FFFF0000FFFFl); ++ slli(x, rs, 32); ++ srli(rd, rs, 32); ++ or_(x, rd, x); // x <- x << 32 | x >> 32 ++ and_(t6, x, t5); // t <- x & 0x0000FFFF0000FFFF ++ slli(t6, t6, 16); // t <- (x & 0x0000FFFF0000FFFF) << 16 ++ slli(t5, t5, 16); // t5 <- 0xFFFF0000FFFF0000 ++ and_(rd, x, t5); // rd <- x & 0xFFFF0000FFFF0000 ++ srli(rd, rd, 16); // rd <- x & (t5 << 16)) >> 16 ++ or_(x, rd, t6); // (x & t5) << 16 | (x & (t5 << 16)) >> 16; ++ li(t5, 0x00FF00FF00FF00FFl); ++ and_(t6, x, t5); // t <- x & 0x00FF00FF00FF00FF ++ slli(t6, t6, 8); // t <- (x & t5) << 8 ++ slli(t5, t5, 8); // t5 <- 0xFF00FF00FF00FF00 ++ and_(rd, x, t5); ++ srli(rd, rd, 8); // rd <- (x & (t5 << 8)) >> 8 ++ or_(rd, rd, t6); // (((x & t5) << 8) | ((x & (t5 << 8)) >> 8)) ++ } ++} ++ ++template ++void TurboAssembler::LoadNBytes(Register rd, const MemOperand& rs, ++ Register scratch) { ++ DCHECK(rd != rs.rm() && rd != scratch); ++ DCHECK(NBYTES <= 8); ++ ++ // load the most significant byte ++ if (LOAD_SIGNED) { ++ lb(rd, rs.rm(), rs.offset() + (NBYTES - 1)); ++ } else { ++ lbu(rd, rs.rm(), rs.offset() + (NBYTES - 1)); ++ } ++ ++ // load remaining (nbytes-1) bytes from higher to lower ++ slli(rd, rd, 8 * (NBYTES - 1)); ++ for (int i = (NBYTES - 2); i >= 0; i--) { ++ lbu(scratch, rs.rm(), rs.offset() + i); ++ if (i) slli(scratch, scratch, i * 8); ++ or_(rd, rd, scratch); ++ } ++} ++ ++template ++void TurboAssembler::LoadNBytesOverwritingBaseReg(const MemOperand& rs, ++ Register scratch0, ++ Register scratch1) { ++ // This function loads nbytes from memory specified by rs and into rs.rm() ++ DCHECK(rs.rm() != scratch0 && rs.rm() != scratch1 && scratch0 != scratch1); ++ DCHECK(NBYTES <= 8); ++ ++ // load the most significant byte ++ if (LOAD_SIGNED) { ++ lb(scratch0, rs.rm(), rs.offset() + (NBYTES - 1)); ++ } else { ++ lbu(scratch0, rs.rm(), rs.offset() + (NBYTES - 1)); ++ } ++ ++ // load remaining (nbytes-1) bytes from higher to lower ++ slli(scratch0, scratch0, 8 * (NBYTES - 1)); ++ for (int i = (NBYTES - 2); i >= 0; i--) { ++ lbu(scratch1, rs.rm(), rs.offset() + i); ++ if (i) { ++ slli(scratch1, scratch1, i * 8); ++ or_(scratch0, scratch0, scratch1); ++ } else { ++ // write to rs.rm() when processing the last byte ++ or_(rs.rm(), scratch0, scratch1); ++ } ++ } ++} ++ ++template ++void TurboAssembler::UnalignedLoadHelper(Register rd, const MemOperand& rs) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ UseScratchRegisterScope temps(this); ++ ++ if (NeedAdjustBaseAndOffset(rs, OffsetAccessType::TWO_ACCESSES, NBYTES - 1)) { ++ // Adjust offset for two accesses and check if offset + 3 fits into int12. ++ MemOperand source = rs; ++ Register scratch_base = temps.Acquire(); ++ DCHECK(scratch_base != rs.rm()); ++ AdjustBaseAndOffset(&source, scratch_base, OffsetAccessType::TWO_ACCESSES, ++ NBYTES - 1); ++ ++ // Since source.rm() is scratch_base, assume rd != source.rm() ++ DCHECK(rd != source.rm()); ++ Register scratch_other = t5; ++ LoadNBytes(rd, source, scratch_other); ++ } else { ++ // no need to adjust base-and-offset ++ if (rd != rs.rm()) { ++ Register scratch = temps.Acquire(); ++ LoadNBytes(rd, rs, scratch); ++ } else { // rd == rs.rm() ++ Register scratch0 = temps.Acquire(); ++ Register scratch1 = t5; ++ LoadNBytesOverwritingBaseReg(rs, scratch0, scratch1); ++ } ++ } ++} ++ ++template ++void TurboAssembler::UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs, ++ Register scratch) { ++ DCHECK(scratch != rs.rm()); ++ DCHECK(NBYTES == 4 || NBYTES == 8); ++ ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ UseScratchRegisterScope temps(this); ++ MemOperand source = rs; ++ if (NeedAdjustBaseAndOffset(rs, OffsetAccessType::TWO_ACCESSES, NBYTES - 1)) { ++ // Adjust offset for two accesses and check if offset + 3 fits into int12. ++ Register scratch_base = temps.Acquire(); ++ DCHECK(scratch_base != scratch && scratch_base != rs.rm()); ++ AdjustBaseAndOffset(&source, scratch_base, OffsetAccessType::TWO_ACCESSES, ++ NBYTES - 1); ++ } ++ ++ Register scratch_other = temps.hasAvailable() ? temps.Acquire() : t5; ++ DCHECK(scratch_other != scratch && scratch_other != rs.rm()); ++ LoadNBytes(scratch, source, scratch_other); ++ if (NBYTES == 4) ++ fmv_w_x(frd, scratch); ++ else ++ fmv_d_x(frd, scratch); ++} ++ ++template ++void TurboAssembler::UnalignedStoreHelper(Register rd, const MemOperand& rs, ++ Register scratch_other) { ++ DCHECK(scratch_other != rs.rm()); ++ DCHECK(NBYTES <= 8); ++ ++ UseScratchRegisterScope temps(this); ++ MemOperand source = rs; ++ // Adjust offset for two accesses and check if offset + 3 fits into int12. ++ if (NeedAdjustBaseAndOffset(rs, OffsetAccessType::TWO_ACCESSES, NBYTES - 1)) { ++ Register scratch_base = temps.Acquire(); ++ DCHECK(scratch_base != rd && scratch_base != rs.rm()); ++ AdjustBaseAndOffset(&source, scratch_base, OffsetAccessType::TWO_ACCESSES, ++ NBYTES - 1); ++ } ++ ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (scratch_other == no_reg) ++ scratch_other = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ DCHECK(scratch_other != rd && scratch_other != rs.rm() && ++ scratch_other != source.rm()); ++ ++ sb(rd, source.rm(), source.offset()); ++ for (size_t i = 1; i <= (NBYTES - 1); i++) { ++ srli(scratch_other, rd, i * 8); ++ sb(scratch_other, source.rm(), source.offset() + i); ++ } ++} ++ ++template ++void TurboAssembler::UnalignedFStoreHelper(FPURegister frd, ++ const MemOperand& rs, ++ Register scratch) { ++ DCHECK(scratch != rs.rm()); ++ DCHECK(NBYTES == 8 || NBYTES == 4); ++ ++ if (NBYTES == 4) { ++ fmv_x_w(scratch, frd); ++ } else { ++ fmv_x_d(scratch, frd); ++ } ++ UnalignedStoreHelper(scratch, rs); ++} ++ ++template ++void TurboAssembler::AlignedLoadHelper(Reg_T target, const MemOperand& rs, ++ Func generator) { ++ MemOperand source = rs; ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (NeedAdjustBaseAndOffset(source)) { ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ DCHECK(scratch != rs.rm()); ++ AdjustBaseAndOffset(&source, scratch); ++ } ++ generator(target, source); ++} ++ ++template ++void TurboAssembler::AlignedStoreHelper(Reg_T value, const MemOperand& rs, ++ Func generator) { ++ MemOperand source = rs; ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (NeedAdjustBaseAndOffset(source)) { ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ // make sure scratch does not overwrite value ++ if (std::is_same::value) ++ DCHECK(scratch.code() != value.code()); ++ DCHECK(scratch != rs.rm()); ++ AdjustBaseAndOffset(&source, scratch); ++ } ++ generator(value, source); ++} ++ ++void TurboAssembler::Ulw(Register rd, const MemOperand& rs) { ++ UnalignedLoadHelper<4, true>(rd, rs); ++} ++ ++void TurboAssembler::Ulwu(Register rd, const MemOperand& rs) { ++ UnalignedLoadHelper<4, false>(rd, rs); ++} ++ ++void TurboAssembler::Usw(Register rd, const MemOperand& rs) { ++ UnalignedStoreHelper<4>(rd, rs); ++} ++ ++void TurboAssembler::Ulh(Register rd, const MemOperand& rs) { ++ UnalignedLoadHelper<2, true>(rd, rs); ++} ++ ++void TurboAssembler::Ulhu(Register rd, const MemOperand& rs) { ++ UnalignedLoadHelper<2, false>(rd, rs); ++} ++ ++void TurboAssembler::Ush(Register rd, const MemOperand& rs) { ++ UnalignedStoreHelper<2>(rd, rs); ++} ++ ++void TurboAssembler::Uld(Register rd, const MemOperand& rs) { ++ UnalignedLoadHelper<8, true>(rd, rs); ++} ++ ++// Load consequent 32-bit word pair in 64-bit reg. and put first word in low ++// bits, ++// second word in high bits. ++void MacroAssembler::LoadWordPair(Register rd, const MemOperand& rs, ++ Register scratch) { ++ Lwu(rd, rs); ++ Lw(scratch, MemOperand(rs.rm(), rs.offset() + kPointerSize / 2)); ++ slli(scratch, scratch, 32); ++ Add64(rd, rd, scratch); ++} ++ ++void TurboAssembler::Usd(Register rd, const MemOperand& rs) { ++ UnalignedStoreHelper<8>(rd, rs); ++} ++ ++// Do 64-bit store as two consequent 32-bit stores to unaligned address. ++void MacroAssembler::StoreWordPair(Register rd, const MemOperand& rs, ++ Register scratch) { ++ Sw(rd, rs); ++ srai(scratch, rd, 32); ++ Sw(scratch, MemOperand(rs.rm(), rs.offset() + kPointerSize / 2)); ++} ++ ++void TurboAssembler::ULoadFloat(FPURegister fd, const MemOperand& rs, ++ Register scratch) { ++ UnalignedFLoadHelper<4>(fd, rs, scratch); ++} ++ ++void TurboAssembler::UStoreFloat(FPURegister fd, const MemOperand& rs, ++ Register scratch) { ++ UnalignedFStoreHelper<4>(fd, rs, scratch); ++} ++ ++void TurboAssembler::ULoadDouble(FPURegister fd, const MemOperand& rs, ++ Register scratch) { ++ UnalignedFLoadHelper<8>(fd, rs, scratch); ++} ++ ++void TurboAssembler::UStoreDouble(FPURegister fd, const MemOperand& rs, ++ Register scratch) { ++ UnalignedFStoreHelper<8>(fd, rs, scratch); ++} ++ ++void TurboAssembler::Lb(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lb(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Lbu(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lbu(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Sb(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register value, const MemOperand& source) { ++ this->sb(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Lh(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lh(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Lhu(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lhu(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Sh(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register value, const MemOperand& source) { ++ this->sh(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Lw(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lw(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Lwu(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->lwu(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Sw(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register value, const MemOperand& source) { ++ this->sw(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Ld(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register target, const MemOperand& source) { ++ this->ld(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::Sd(Register rd, const MemOperand& rs) { ++ auto fn = [this](Register value, const MemOperand& source) { ++ this->sd(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(rd, rs, fn); ++} ++ ++void TurboAssembler::LoadFloat(FPURegister fd, const MemOperand& src) { ++ auto fn = [this](FPURegister target, const MemOperand& source) { ++ this->flw(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(fd, src, fn); ++} ++ ++void TurboAssembler::StoreFloat(FPURegister fs, const MemOperand& src) { ++ auto fn = [this](FPURegister value, const MemOperand& source) { ++ this->fsw(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(fs, src, fn); ++} ++ ++void TurboAssembler::LoadDouble(FPURegister fd, const MemOperand& src) { ++ auto fn = [this](FPURegister target, const MemOperand& source) { ++ this->fld(target, source.rm(), source.offset()); ++ }; ++ AlignedLoadHelper(fd, src, fn); ++} ++ ++void TurboAssembler::StoreDouble(FPURegister fs, const MemOperand& src) { ++ auto fn = [this](FPURegister value, const MemOperand& source) { ++ this->fsd(value, source.rm(), source.offset()); ++ }; ++ AlignedStoreHelper(fs, src, fn); ++} ++ ++void TurboAssembler::Ll(Register rd, const MemOperand& rs) { ++ bool is_one_instruction = rs.offset() == 0; ++ if (is_one_instruction) { ++ lr_w(false, false, rd, rs.rm()); ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Add64(scratch, rs.rm(), rs.offset()); ++ lr_w(false, false, rd, scratch); ++ } ++} ++ ++void TurboAssembler::Lld(Register rd, const MemOperand& rs) { ++ bool is_one_instruction = rs.offset() == 0; ++ if (is_one_instruction) { ++ lr_d(false, false, rd, rs.rm()); ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Add64(scratch, rs.rm(), rs.offset()); ++ lr_d(false, false, rd, scratch); ++ } ++} ++ ++void TurboAssembler::Sc(Register rd, const MemOperand& rs) { ++ bool is_one_instruction = rs.offset() == 0; ++ if (is_one_instruction) { ++ sc_w(false, false, rd, rs.rm(), rd); ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Add64(scratch, rs.rm(), rs.offset()); ++ sc_w(false, false, rd, scratch, rd); ++ } ++} ++ ++void TurboAssembler::Scd(Register rd, const MemOperand& rs) { ++ bool is_one_instruction = rs.offset() == 0; ++ if (is_one_instruction) { ++ sc_d(false, false, rd, rs.rm(), rd); ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Add64(scratch, rs.rm(), rs.offset()); ++ sc_d(false, false, rd, scratch, rd); ++ } ++} ++ ++void TurboAssembler::li(Register dst, Handle value, LiFlags mode) { ++ // TODO(jgruber,v8:8887): Also consider a root-relative load when generating ++ // non-isolate-independent code. In many cases it might be cheaper than ++ // embedding the relocatable value. ++ if (root_array_available_ && options().isolate_independent_code) { ++ IndirectLoadConstant(dst, value); ++ return; ++ } ++ li(dst, Operand(value), mode); ++} ++ ++void TurboAssembler::li(Register dst, ExternalReference value, LiFlags mode) { ++ // TODO(jgruber,v8:8887): Also consider a root-relative load when generating ++ // non-isolate-independent code. In many cases it might be cheaper than ++ // embedding the relocatable value. ++ if (root_array_available_ && options().isolate_independent_code) { ++ IndirectLoadExternalReference(dst, value); ++ return; ++ } ++ li(dst, Operand(value), mode); ++} ++ ++void TurboAssembler::li(Register dst, const StringConstantBase* string, ++ LiFlags mode) { ++ li(dst, Operand::EmbeddedStringConstant(string), mode); ++} ++ ++static inline int InstrCountForLiLower32Bit(int64_t value) { ++ int64_t Hi20 = ((value + 0x800) >> 12); ++ int64_t Lo12 = value << 52 >> 52; ++ if (Hi20 == 0 || Lo12 == 0) { ++ return 1; ++ } ++ return 2; ++} ++ ++int TurboAssembler::InstrCountForLi64Bit(int64_t value) { ++ if (is_int32(value)) { ++ return InstrCountForLiLower32Bit(value); ++ } else { ++ return li_count(value); ++ } ++ UNREACHABLE(); ++ return INT_MAX; ++} ++ ++void TurboAssembler::li_optimized(Register rd, Operand j, LiFlags mode) { ++ DCHECK(!j.is_reg()); ++ DCHECK(!MustUseReg(j.rmode())); ++ DCHECK(mode == OPTIMIZE_SIZE); ++ RV_li(rd, j.immediate()); ++} ++ ++void TurboAssembler::li(Register rd, Operand j, LiFlags mode) { ++ DCHECK(!j.is_reg()); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (!MustUseReg(j.rmode()) && mode == OPTIMIZE_SIZE) { ++ RV_li(rd, j.immediate()); ++ } else if (MustUseReg(j.rmode())) { ++ int64_t immediate; ++ if (j.IsHeapObjectRequest()) { ++ RequestHeapObject(j.heap_object_request()); ++ immediate = 0; ++ } else { ++ immediate = j.immediate(); ++ } ++ ++ RecordRelocInfo(j.rmode(), immediate); ++ // FIXME(RISC_V): Does this case need to be constant size? ++ li_constant(rd, immediate); ++ } else if (mode == ADDRESS_LOAD) { ++ // We always need the same number of instructions as we may need to patch ++ // this code to load another value which may need all 8 instructions. ++ RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE_ENCODED); ++ li_constant(rd, j.immediate()); ++ } else { // mode == CONSTANT_SIZE - always emit the same instruction ++ // sequence. ++ li_constant(rd, j.immediate()); ++ } ++} ++ ++static RegList t_regs = Register::ListOf(t0, t1, t2, t3, t4, t5, t6); ++static RegList a_regs = Register::ListOf(a0, a1, a2, a3, a4, a5, a6, a7); ++static RegList s_regs = ++ Register::ListOf(s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11); ++ ++void TurboAssembler::MultiPush(RegList regs) { ++ int16_t num_to_push = base::bits::CountPopulation(regs); ++ int16_t stack_offset = num_to_push * kPointerSize; ++ ++#define TEST_AND_PUSH_REG(reg) \ ++ if ((regs & reg.bit()) != 0) { \ ++ stack_offset -= kPointerSize; \ ++ Sd(reg, MemOperand(sp, stack_offset)); \ ++ regs &= ~reg.bit(); \ ++ } ++ ++#define T_REGS(V) V(t6) V(t5) V(t4) V(t3) V(t2) V(t1) V(t0) ++#define A_REGS(V) V(a7) V(a6) V(a5) V(a4) V(a3) V(a2) V(a1) V(a0) ++#define S_REGS(V) \ ++ V(s11) V(s10) V(s9) V(s8) V(s7) V(s6) V(s5) V(s4) V(s3) V(s2) V(s1) ++ ++ Sub64(sp, sp, Operand(stack_offset)); ++ ++ // Certain usage of MultiPush requires that registers are pushed onto the ++ // stack in a particular: ra, fp, sp, gp, .... (basically in the decreasing ++ // order of register numbers according to MIPS register numbers) ++ TEST_AND_PUSH_REG(ra); ++ TEST_AND_PUSH_REG(fp); ++ TEST_AND_PUSH_REG(sp); ++ TEST_AND_PUSH_REG(gp); ++ TEST_AND_PUSH_REG(tp); ++ if ((regs & s_regs) != 0) { ++ S_REGS(TEST_AND_PUSH_REG) ++ } ++ if ((regs & a_regs) != 0) { ++ A_REGS(TEST_AND_PUSH_REG) ++ } ++ if ((regs & t_regs) != 0) { ++ T_REGS(TEST_AND_PUSH_REG) ++ } ++ ++ DCHECK(regs == 0); ++ ++#undef TEST_AND_PUSH_REG ++#undef T_REGS ++#undef A_REGS ++#undef S_REGS ++} ++ ++void TurboAssembler::MultiPop(RegList regs) { ++ int16_t stack_offset = 0; ++ ++#define TEST_AND_POP_REG(reg) \ ++ if ((regs & reg.bit()) != 0) { \ ++ Ld(reg, MemOperand(sp, stack_offset)); \ ++ stack_offset += kPointerSize; \ ++ regs &= ~reg.bit(); \ ++ } ++ ++#define T_REGS(V) V(t0) V(t1) V(t2) V(t3) V(t4) V(t5) V(t6) ++#define A_REGS(V) V(a0) V(a1) V(a2) V(a3) V(a4) V(a5) V(a6) V(a7) ++#define S_REGS(V) \ ++ V(s1) V(s2) V(s3) V(s4) V(s5) V(s6) V(s7) V(s8) V(s9) V(s10) V(s11) ++ ++ // MultiPop pops from the stack in reverse order as MultiPush ++ if ((regs & t_regs) != 0) { ++ T_REGS(TEST_AND_POP_REG) ++ } ++ if ((regs & a_regs) != 0) { ++ A_REGS(TEST_AND_POP_REG) ++ } ++ if ((regs & s_regs) != 0) { ++ S_REGS(TEST_AND_POP_REG) ++ } ++ TEST_AND_POP_REG(tp); ++ TEST_AND_POP_REG(gp); ++ TEST_AND_POP_REG(sp); ++ TEST_AND_POP_REG(fp); ++ TEST_AND_POP_REG(ra); ++ ++ DCHECK(regs == 0); ++ ++ addi(sp, sp, stack_offset); ++ ++#undef TEST_AND_POP_REG ++#undef T_REGS ++#undef S_REGS ++#undef A_REGS ++} ++ ++void TurboAssembler::MultiPushFPU(RegList regs) { ++ int16_t num_to_push = base::bits::CountPopulation(regs); ++ int16_t stack_offset = num_to_push * kDoubleSize; ++ ++ Sub64(sp, sp, Operand(stack_offset)); ++ for (int16_t i = kNumRegisters - 1; i >= 0; i--) { ++ if ((regs & (1 << i)) != 0) { ++ stack_offset -= kDoubleSize; ++ StoreDouble(FPURegister::from_code(i), MemOperand(sp, stack_offset)); ++ } ++ } ++} ++ ++void TurboAssembler::MultiPopFPU(RegList regs) { ++ int16_t stack_offset = 0; ++ ++ for (int16_t i = 0; i < kNumRegisters; i++) { ++ if ((regs & (1 << i)) != 0) { ++ LoadDouble(FPURegister::from_code(i), MemOperand(sp, stack_offset)); ++ stack_offset += kDoubleSize; ++ } ++ } ++ addi(sp, sp, stack_offset); ++} ++ ++void TurboAssembler::ExtractBits(Register rt, Register rs, uint16_t pos, ++ uint16_t size, bool sign_extend) { ++ DCHECK(pos < 64 && 0 < size && size <= 64 && 0 < pos + size && ++ pos + size <= 64); ++ slli(rt, rs, 64 - (pos + size)); ++ if (sign_extend) { ++ srai(rt, rt, 64 - size); ++ } else { ++ srli(rt, rt, 64 - size); ++ } ++} ++ ++void TurboAssembler::InsertBits(Register dest, Register source, Register pos, ++ int size) { ++ DCHECK(size < 64); ++ UseScratchRegisterScope temps(this); ++ Register mask = temps.Acquire(); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register source_ = temps.hasAvailable() ? temps.Acquire() : t5; ++ // Create a mask of the length=size. ++ li(mask, 1); ++ slli(mask, mask, size); ++ addi(mask, mask, -1); ++ and_(source_, mask, source); ++ sll(source_, source_, pos); ++ // Make a mask containing 0's. 0's start at "pos" with length=size. ++ sll(mask, mask, pos); ++ not_(mask, mask); ++ // cut area for insertion of source. ++ and_(dest, mask, dest); ++ // insert source ++ or_(dest, dest, source_); ++} ++ ++void TurboAssembler::Neg_s(FPURegister fd, FPURegister fs) { fneg_s(fd, fs); } ++ ++void TurboAssembler::Neg_d(FPURegister fd, FPURegister fs) { fneg_d(fd, fs); } ++ ++void TurboAssembler::Cvt_d_uw(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_d_wu(fd, rs); ++} ++ ++void TurboAssembler::Cvt_d_w(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_d_w(fd, rs); ++} ++ ++void TurboAssembler::Cvt_d_ul(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_d_lu(fd, rs); ++} ++ ++void TurboAssembler::Cvt_s_uw(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_s_wu(fd, rs); ++} ++ ++void TurboAssembler::Cvt_s_w(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_s_w(fd, rs); ++} ++ ++void TurboAssembler::Cvt_s_ul(FPURegister fd, Register rs) { ++ // Convert rs to a FP value in fd. ++ fcvt_s_lu(fd, rs); ++} ++ ++template ++void TurboAssembler::RoundFloatingPointToInteger(Register rd, FPURegister fs, ++ Register result, ++ CvtFunc fcvt_generator) { ++ // Save csr_fflags to scratch & clear exception flags ++ if (result.is_valid()) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ int exception_flags = kInvalidOperation; ++ csrrci(scratch, csr_fflags, exception_flags); ++ ++ // actual conversion instruction ++ fcvt_generator(this, rd, fs); ++ ++ // check kInvalidOperation flag (out-of-range, NaN) ++ // set result to 1 if normal, otherwise set result to 0 for abnormal ++ frflags(result); ++ andi(result, result, exception_flags); ++ seqz(result, result); // result <-- 1 (normal), result <-- 0 (abnormal) ++ ++ // restore csr_fflags ++ csrw(csr_fflags, scratch); ++ } else { ++ // actual conversion instruction ++ fcvt_generator(this, rd, fs); ++ } ++} ++ ++void TurboAssembler::Trunc_uw_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_wu_d(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_w_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_d(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_uw_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_wu_s(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_w_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_s(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_ul_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_lu_d(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_l_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_l_d(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_ul_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_lu_s(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Trunc_l_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_l_s(dst, src, RTZ); ++ }); ++} ++ ++void TurboAssembler::Round_w_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_s(dst, src, RNE); ++ }); ++} ++ ++void TurboAssembler::Round_w_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_d(dst, src, RNE); ++ }); ++} ++ ++void TurboAssembler::Ceil_w_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_s(dst, src, RUP); ++ }); ++} ++ ++void TurboAssembler::Ceil_w_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_d(dst, src, RUP); ++ }); ++} ++ ++void TurboAssembler::Floor_w_s(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_s(dst, src, RDN); ++ }); ++} ++ ++void TurboAssembler::Floor_w_d(Register rd, FPURegister fs, Register result) { ++ RoundFloatingPointToInteger( ++ rd, fs, result, [](TurboAssembler* tasm, Register dst, FPURegister src) { ++ tasm->fcvt_w_d(dst, src, RDN); ++ }); ++} ++ ++// According to JS ECMA specification, for floating-point round operations, if ++// the input is NaN, +/-infinity, or +/-0, the same input is returned as the ++// rounded result; this differs from behavior of RISCV fcvt instructions (which ++// round out-of-range values to the nearest max or min value), therefore special ++// handling is needed by NaN, +/-Infinity, +/-0 ++template ++void TurboAssembler::RoundHelper(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch, RoundingMode frm) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ DCHECK((std::is_same::value) || (std::is_same::value)); ++ // Need at least two FPRs, so check against dst == src == fpu_scratch ++ DCHECK(!(dst == src && dst == fpu_scratch)); ++ ++ const int kFloat32ExponentBias = 127; ++ const int kFloat32MantissaBits = 23; ++ const int kFloat32ExponentBits = 8; ++ const int kFloat64ExponentBias = 1023; ++ const int kFloat64MantissaBits = 52; ++ const int kFloat64ExponentBits = 11; ++ const int kFloatMantissaBits = ++ sizeof(F) == 4 ? kFloat32MantissaBits : kFloat64MantissaBits; ++ const int kFloatExponentBits = ++ sizeof(F) == 4 ? kFloat32ExponentBits : kFloat64ExponentBits; ++ const int kFloatExponentBias = ++ sizeof(F) == 4 ? kFloat32ExponentBias : kFloat64ExponentBias; ++ ++ Label done; ++ ++ // extract exponent value of the source floating-point to t6 ++ if (std::is_same::value) { ++ fmv_x_d(scratch, src); ++ } else { ++ fmv_x_w(scratch, src); ++ } ++ ExtractBits(t6, scratch, kFloatMantissaBits, kFloatExponentBits); ++ ++ // if src is NaN/+-Infinity/+-Zero or if the exponent is larger than # of bits ++ // in mantissa, the result is the same as src, so move src to dest (to avoid ++ // generating another branch) ++ if (dst != src) { ++ if (std::is_same::value) { ++ fmv_d(dst, src); ++ } else { ++ fmv_s(dst, src); ++ } ++ } ++ ++ // If real exponent (i.e., t6 - kFloatExponentBias) is greater than ++ // kFloat32MantissaBits, it means the floating-point value has no fractional ++ // part, thus the input is already rounded, jump to done. Note that, NaN and ++ // Infinity in floating-point representation sets maximal exponent value, so ++ // they also satisfy (t6-kFloatExponentBias >= kFloatMantissaBits), and JS ++ // round semantics specify that rounding of NaN (Infinity) returns NaN ++ // (Infinity), so NaN and Infinity are considered rounded value too. ++ Branch(&done, greater_equal, t6, ++ Operand(kFloatExponentBias + kFloatMantissaBits)); ++ ++ // Actual rounding is needed along this path ++ ++ // old_src holds the original input, needed for the case of src == dst ++ FPURegister old_src = src; ++ if (src == dst) { ++ DCHECK(fpu_scratch != dst); ++ Move(fpu_scratch, src); ++ old_src = fpu_scratch; ++ } ++ ++ // Since only input whose real exponent value is less than kMantissaBits ++ // (i.e., 23 or 52-bits) falls into this path, the value range of the input ++ // falls into that of 23- or 53-bit integers. So we round the input to integer ++ // values, then convert them back to floating-point. ++ if (std::is_same::value) { ++ fcvt_l_d(scratch, src, frm); ++ fcvt_d_l(dst, scratch, frm); ++ } else { ++ fcvt_w_s(scratch, src, frm); ++ fcvt_s_w(dst, scratch, frm); ++ } ++ ++ // A special handling is needed if the input is a very small positive/negative ++ // number that rounds to zero. JS semantics requires that the rounded result ++ // retains the sign of the input, so a very small positive (negative) ++ // floating-point number should be rounded to positive (negative) 0. ++ // Therefore, we use sign-bit injection to produce +/-0 correctly. Instead of ++ // testing for zero w/ a branch, we just insert sign-bit for everyone on this ++ // path (this is where old_src is needed) ++ if (std::is_same::value) { ++ fsgnj_d(dst, dst, old_src); ++ } else { ++ fsgnj_s(dst, dst, old_src); ++ } ++ ++ bind(&done); ++} ++ ++void TurboAssembler::Floor_d_d(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RDN); ++} ++ ++void TurboAssembler::Ceil_d_d(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RUP); ++} ++ ++void TurboAssembler::Trunc_d_d(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RTZ); ++} ++ ++void TurboAssembler::Round_d_d(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RNE); ++} ++ ++void TurboAssembler::Floor_s_s(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RDN); ++} ++ ++void TurboAssembler::Ceil_s_s(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RUP); ++} ++ ++void TurboAssembler::Trunc_s_s(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RTZ); ++} ++ ++void TurboAssembler::Round_s_s(FPURegister dst, FPURegister src, ++ FPURegister fpu_scratch) { ++ RoundHelper(dst, src, fpu_scratch, RNE); ++} ++ ++void MacroAssembler::Madd_s(FPURegister fd, FPURegister fr, FPURegister fs, ++ FPURegister ft) { ++ fmadd_s(fd, fs, ft, fr); ++} ++ ++void MacroAssembler::Madd_d(FPURegister fd, FPURegister fr, FPURegister fs, ++ FPURegister ft) { ++ fmadd_d(fd, fs, ft, fr); ++} ++ ++void MacroAssembler::Msub_s(FPURegister fd, FPURegister fr, FPURegister fs, ++ FPURegister ft) { ++ fmsub_s(fd, fs, ft, fr); ++} ++ ++void MacroAssembler::Msub_d(FPURegister fd, FPURegister fr, FPURegister fs, ++ FPURegister ft) { ++ fmsub_d(fd, fs, ft, fr); ++} ++ ++void TurboAssembler::CompareF32(Register rd, FPUCondition cc, FPURegister cmp1, ++ FPURegister cmp2) { ++ switch (cc) { ++ case EQ: ++ feq_s(rd, cmp1, cmp2); ++ break; ++ case NE: ++ feq_s(rd, cmp1, cmp2); ++ NegateBool(rd, rd); ++ break; ++ case LT: ++ flt_s(rd, cmp1, cmp2); ++ break; ++ case GE: ++ fle_s(rd, cmp2, cmp1); ++ break; ++ case LE: ++ fle_s(rd, cmp1, cmp2); ++ break; ++ case GT: ++ flt_s(rd, cmp2, cmp1); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void TurboAssembler::CompareF64(Register rd, FPUCondition cc, FPURegister cmp1, ++ FPURegister cmp2) { ++ switch (cc) { ++ case EQ: ++ feq_d(rd, cmp1, cmp2); ++ break; ++ case NE: ++ feq_d(rd, cmp1, cmp2); ++ NegateBool(rd, rd); ++ break; ++ case LT: ++ flt_d(rd, cmp1, cmp2); ++ break; ++ case GE: ++ fle_d(rd, cmp2, cmp1); ++ break; ++ case LE: ++ fle_d(rd, cmp1, cmp2); ++ break; ++ case GT: ++ flt_d(rd, cmp2, cmp1); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void TurboAssembler::CompareIsNanF32(Register rd, FPURegister cmp1, ++ FPURegister cmp2) { ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ feq_s(rd, cmp1, cmp1); // rd <- !isNan(cmp1) ++ feq_s(scratch, cmp2, cmp2); // scratch <- !isNaN(cmp2) ++ And(rd, rd, scratch); // rd <- !isNan(cmp1) && !isNan(cmp2) ++ Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2) ++} ++ ++void TurboAssembler::CompareIsNanF64(Register rd, FPURegister cmp1, ++ FPURegister cmp2) { ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ feq_d(rd, cmp1, cmp1); // rd <- !isNan(cmp1) ++ feq_d(scratch, cmp2, cmp2); // scratch <- !isNaN(cmp2) ++ And(rd, rd, scratch); // rd <- !isNan(cmp1) && !isNan(cmp2) ++ Xor(rd, rd, 1); // rd <- isNan(cmp1) || isNan(cmp2) ++} ++ ++void TurboAssembler::BranchTrueShortF(Register rs, Label* target) { ++ Branch(target, not_equal, rs, Operand(zero_reg)); ++} ++ ++void TurboAssembler::BranchFalseShortF(Register rs, Label* target) { ++ Branch(target, equal, rs, Operand(zero_reg)); ++} ++ ++void TurboAssembler::BranchTrueF(Register rs, Label* target) { ++ bool long_branch = ++ target->is_bound() ? !is_near(target) : is_trampoline_emitted(); ++ if (long_branch) { ++ Label skip; ++ BranchFalseShortF(rs, &skip); ++ BranchLong(target); ++ bind(&skip); ++ } else { ++ BranchTrueShortF(rs, target); ++ } ++} ++ ++void TurboAssembler::BranchFalseF(Register rs, Label* target) { ++ bool long_branch = ++ target->is_bound() ? !is_near(target) : is_trampoline_emitted(); ++ if (long_branch) { ++ Label skip; ++ BranchTrueShortF(rs, &skip); ++ BranchLong(target); ++ bind(&skip); ++ } else { ++ BranchFalseShortF(rs, target); ++ } ++} ++ ++void TurboAssembler::InsertHighWordF64(FPURegister dst, Register src_high) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ ++ DCHECK(src_high != t5 && src_high != scratch); ++ ++ fmv_x_d(scratch, dst); ++ slli(t5, src_high, 32); ++ slli(scratch, scratch, 32); ++ srli(scratch, scratch, 32); ++ or_(scratch, scratch, t5); ++ fmv_d_x(dst, scratch); ++} ++ ++void TurboAssembler::InsertLowWordF64(FPURegister dst, Register src_low) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ UseScratchRegisterScope block_trampoline_pool(this); ++ ++ DCHECK(src_low != scratch && src_low != t5); ++ fmv_x_d(scratch, dst); ++ slli(t5, src_low, 32); ++ srli(t5, t5, 32); ++ srli(scratch, scratch, 32); ++ slli(scratch, scratch, 32); ++ or_(scratch, scratch, t5); ++ fmv_d_x(dst, scratch); ++} ++ ++void TurboAssembler::LoadFPRImmediate(FPURegister dst, uint32_t src) { ++ // Handle special values first. ++ if (src == bit_cast(0.0f) && has_single_zero_reg_set_) { ++ if (dst != kDoubleRegZero) fmv_s(dst, kDoubleRegZero); ++ } else if (src == bit_cast(-0.0f) && has_single_zero_reg_set_) { ++ Neg_s(dst, kDoubleRegZero); ++ } else { ++ if (dst == kDoubleRegZero) { ++ DCHECK(src == bit_cast(0.0f)); ++ fmv_w_x(dst, zero_reg); ++ has_single_zero_reg_set_ = true; ++ has_double_zero_reg_set_ = false; ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(static_cast(src))); ++ fmv_w_x(dst, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::LoadFPRImmediate(FPURegister dst, uint64_t src) { ++ // Handle special values first. ++ if (src == bit_cast(0.0) && has_double_zero_reg_set_) { ++ if (dst != kDoubleRegZero) fmv_d(dst, kDoubleRegZero); ++ } else if (src == bit_cast(-0.0) && has_double_zero_reg_set_) { ++ Neg_d(dst, kDoubleRegZero); ++ } else { ++ if (dst == kDoubleRegZero) { ++ DCHECK(src == bit_cast(0.0)); ++ fmv_d_x(dst, zero_reg); ++ has_double_zero_reg_set_ = true; ++ has_single_zero_reg_set_ = false; ++ } else { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(src)); ++ fmv_d_x(dst, scratch); ++ } ++ } ++} ++ ++void TurboAssembler::CompareI(Register rd, Register rs, const Operand& rt, ++ Condition cond) { ++ switch (cond) { ++ case eq: ++ Seq(rd, rs, rt); ++ break; ++ case ne: ++ Sne(rd, rs, rt); ++ break; ++ ++ // Signed comparison. ++ case greater: ++ Sgt(rd, rs, rt); ++ break; ++ case greater_equal: ++ Sge(rd, rs, rt); // rs >= rt ++ break; ++ case less: ++ Slt(rd, rs, rt); // rs < rt ++ break; ++ case less_equal: ++ Sle(rd, rs, rt); // rs <= rt ++ break; ++ ++ // Unsigned comparison. ++ case Ugreater: ++ Sgtu(rd, rs, rt); // rs > rt ++ break; ++ case Ugreater_equal: ++ Sgeu(rd, rs, rt); // rs >= rt ++ break; ++ case Uless: ++ Sltu(rd, rs, rt); // rs < rt ++ break; ++ case Uless_equal: ++ Sleu(rd, rs, rt); // rs <= rt ++ break; ++ case cc_always: ++ UNREACHABLE(); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++// dest <- (condition != 0 ? zero : dest) ++void TurboAssembler::LoadZeroIfConditionNotZero(Register dest, ++ Register condition) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ seqz(scratch, condition); ++ // neg + and may be more efficient than mul(dest, dest, scratch) ++ neg(scratch, scratch); // 0 is still 0, 1 becomes all 1s ++ and_(dest, dest, scratch); ++} ++ ++// dest <- (condition == 0 ? 0 : dest) ++void TurboAssembler::LoadZeroIfConditionZero(Register dest, ++ Register condition) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ snez(scratch, condition); ++ // neg + and may be more efficient than mul(dest, dest, scratch); ++ neg(scratch, scratch); // 0 is still 0, 1 becomes all 1s ++ and_(dest, dest, scratch); ++} ++ ++void TurboAssembler::Clz32(Register rd, Register xx) { ++ // 32 bit unsigned in lower word: count number of leading zeros. ++ // int n = 32; ++ // unsigned y; ++ ++ // y = x >>16; if (y != 0) { n = n -16; x = y; } ++ // y = x >> 8; if (y != 0) { n = n - 8; x = y; } ++ // y = x >> 4; if (y != 0) { n = n - 4; x = y; } ++ // y = x >> 2; if (y != 0) { n = n - 2; x = y; } ++ // y = x >> 1; if (y != 0) {rd = n - 2; return;} ++ // rd = n - x; ++ ++ Label L0, L1, L2, L3, L4; ++ DCHECK(xx != t5 && xx != t6); ++ UseScratchRegisterScope temps(this); ++ UseScratchRegisterScope block_trampoline_pool(this); ++ Register x = rd; ++ Register y = t5; ++ Register n = t6; ++ Move(x, xx); ++ li(n, Operand(32)); ++ srliw(y, x, 16); ++ Branch(&L0, eq, y, Operand(zero_reg)); ++ Move(x, y); ++ addiw(n, n, -16); ++ bind(&L0); ++ srliw(y, x, 8); ++ Branch(&L1, eq, y, Operand(zero_reg)); ++ addiw(n, n, -8); ++ Move(x, y); ++ bind(&L1); ++ srliw(y, x, 4); ++ Branch(&L2, eq, y, Operand(zero_reg)); ++ addiw(n, n, -4); ++ Move(x, y); ++ bind(&L2); ++ srliw(y, x, 2); ++ Branch(&L3, eq, y, Operand(zero_reg)); ++ addiw(n, n, -2); ++ Move(x, y); ++ bind(&L3); ++ srliw(y, x, 1); ++ subw(rd, n, x); ++ Branch(&L4, eq, y, Operand(zero_reg)); ++ addiw(rd, n, -2); ++ bind(&L4); ++} ++ ++void TurboAssembler::Clz64(Register rd, Register xx) { ++ // 64 bit: count number of leading zeros. ++ // int n = 64; ++ // unsigned y; ++ ++ // y = x >>32; if (y != 0) { n = n - 32; x = y; } ++ // y = x >>16; if (y != 0) { n = n - 16; x = y; } ++ // y = x >> 8; if (y != 0) { n = n - 8; x = y; } ++ // y = x >> 4; if (y != 0) { n = n - 4; x = y; } ++ // y = x >> 2; if (y != 0) { n = n - 2; x = y; } ++ // y = x >> 1; if (y != 0) {rd = n - 2; return;} ++ // rd = n - x; ++ ++ DCHECK(xx != t5 && xx != t6); ++ Label L0, L1, L2, L3, L4, L5; ++ UseScratchRegisterScope temps(this); ++ UseScratchRegisterScope block_trampoline_pool(this); ++ Register x = rd; ++ Register y = t5; ++ Register n = t6; ++ Move(x, xx); ++ li(n, Operand(64)); ++ srli(y, x, 32); ++ Branch(&L0, eq, y, Operand(zero_reg)); ++ addiw(n, n, -32); ++ Move(x, y); ++ bind(&L0); ++ srli(y, x, 16); ++ Branch(&L1, eq, y, Operand(zero_reg)); ++ addiw(n, n, -16); ++ Move(x, y); ++ bind(&L1); ++ srli(y, x, 8); ++ Branch(&L2, eq, y, Operand(zero_reg)); ++ addiw(n, n, -8); ++ Move(x, y); ++ bind(&L2); ++ srli(y, x, 4); ++ Branch(&L3, eq, y, Operand(zero_reg)); ++ addiw(n, n, -4); ++ Move(x, y); ++ bind(&L3); ++ srli(y, x, 2); ++ Branch(&L4, eq, y, Operand(zero_reg)); ++ addiw(n, n, -2); ++ Move(x, y); ++ bind(&L4); ++ srli(y, x, 1); ++ subw(rd, n, x); ++ Branch(&L5, eq, y, Operand(zero_reg)); ++ addiw(rd, n, -2); ++ bind(&L5); ++} ++ ++void TurboAssembler::Ctz32(Register rd, Register rs) { ++ // Convert trailing zeroes to trailing ones, and bits to their left ++ // to zeroes. ++ UseScratchRegisterScope temps(this); ++ UseScratchRegisterScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ Add64(scratch, rs, -1); ++ Xor(rd, scratch, rs); ++ And(rd, rd, scratch); ++ // Count number of leading zeroes. ++ Clz32(rd, rd); ++ // Subtract number of leading zeroes from 32 to get number of trailing ++ // ones. Remember that the trailing ones were formerly trailing zeroes. ++ li(scratch, 32); ++ Sub32(rd, scratch, rd); ++} ++ ++void TurboAssembler::Ctz64(Register rd, Register rs) { ++ // Convert trailing zeroes to trailing ones, and bits to their left ++ // to zeroes. ++ UseScratchRegisterScope temps(this); ++ UseScratchRegisterScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ Add64(scratch, rs, -1); ++ Xor(rd, scratch, rs); ++ And(rd, rd, scratch); ++ // Count number of leading zeroes. ++ Clz64(rd, rd); ++ // Subtract number of leading zeroes from 64 to get number of trailing ++ // ones. Remember that the trailing ones were formerly trailing zeroes. ++ li(scratch, 64); ++ Sub64(rd, scratch, rd); ++} ++ ++void TurboAssembler::Popcnt32(Register rd, Register rs) { ++ // https://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel ++ // ++ // A generalization of the best bit counting method to integers of ++ // bit-widths up to 128 (parameterized by type T) is this: ++ // ++ // v = v - ((v >> 1) & (T)~(T)0/3); // temp ++ // v = (v & (T)~(T)0/15*3) + ((v >> 2) & (T)~(T)0/15*3); // temp ++ // v = (v + (v >> 4)) & (T)~(T)0/255*15; // temp ++ // c = (T)(v * ((T)~(T)0/255)) >> (sizeof(T) - 1) * BITS_PER_BYTE; //count ++ // ++ // There are algorithms which are faster in the cases where very few ++ // bits are set but the algorithm here attempts to minimize the total ++ // number of instructions executed even when a large number of bits ++ // are set. ++ // The number of instruction is 20. ++ // uint32_t B0 = 0x55555555; // (T)~(T)0/3 ++ // uint32_t B1 = 0x33333333; // (T)~(T)0/15*3 ++ // uint32_t B2 = 0x0F0F0F0F; // (T)~(T)0/255*15 ++ // uint32_t value = 0x01010101; // (T)~(T)0/255 ++ ++ DCHECK(rd != t5 && rd != t6 && rs != t5 && rs != t6); ++ uint32_t shift = 24; ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.Acquire(); ++ Register scratch2 = t5; ++ Register value = t6; ++ li(value, 0x01010101); // value = 0x01010101; ++ li(scratch2, 0x55555555); // B0 = 0x55555555; ++ Srl32(scratch, rs, 1); ++ And(scratch, scratch, scratch2); ++ Sub32(scratch, rs, scratch); ++ li(scratch2, 0x33333333); // B1 = 0x33333333; ++ slli(rd, scratch2, 4); ++ or_(scratch2, scratch2, rd); ++ And(rd, scratch, scratch2); ++ Srl32(scratch, scratch, 2); ++ And(scratch, scratch, scratch2); ++ Add32(scratch, rd, scratch); ++ srliw(rd, scratch, 4); ++ Add32(rd, rd, scratch); ++ li(scratch2, 0xF); ++ Mul32(scratch2, value, scratch2); // B2 = 0x0F0F0F0F; ++ And(rd, rd, scratch2); ++ Mul32(rd, rd, value); ++ Srl32(rd, rd, shift); ++} ++ ++void TurboAssembler::Popcnt64(Register rd, Register rs) { ++ // uint64_t B0 = 0x5555555555555555l; // (T)~(T)0/3 ++ // uint64_t B1 = 0x3333333333333333l; // (T)~(T)0/15*3 ++ // uint64_t B2 = 0x0F0F0F0F0F0F0F0Fl; // (T)~(T)0/255*15 ++ // uint64_t value = 0x0101010101010101l; // (T)~(T)0/255 ++ // uint64_t shift = 24; // (sizeof(T) - 1) * BITS_PER_BYTE ++ ++ DCHECK(rd != t5 && rd != t6 && rs != t5 && rs != t6); ++ uint64_t shift = 24; ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.Acquire(); ++ Register scratch2 = t5; ++ Register value = t6; ++ li(value, 0x1111111111111111l); // value = 0x1111111111111111l; ++ li(scratch2, 5); ++ Mul64(scratch2, value, scratch2); // B0 = 0x5555555555555555l; ++ Srl64(scratch, rs, 1); ++ And(scratch, scratch, scratch2); ++ Sub64(scratch, rs, scratch); ++ li(scratch2, 3); ++ Mul64(scratch2, value, scratch2); // B1 = 0x3333333333333333l; ++ And(rd, scratch, scratch2); ++ Srl64(scratch, scratch, 2); ++ And(scratch, scratch, scratch2); ++ Add64(scratch, rd, scratch); ++ Srl64(rd, scratch, 4); ++ Add64(rd, rd, scratch); ++ li(scratch2, 0xF); ++ li(value, 0x0101010101010101l); // value = 0x0101010101010101l; ++ Mul64(scratch2, value, scratch2); // B2 = 0x0F0F0F0F0F0F0F0Fl; ++ And(rd, rd, scratch2); ++ Mul64(rd, rd, value); ++ srli(rd, rd, 32 + shift); ++} ++ ++void TurboAssembler::TryInlineTruncateDoubleToI(Register result, ++ DoubleRegister double_input, ++ Label* done) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ // if scratch == 1, exception happens during truncation ++ Trunc_w_d(result, double_input, scratch); ++ // If we had no exceptions (i.e., scratch==1) we are done. ++ Branch(done, eq, scratch, Operand(1)); ++} ++ ++void TurboAssembler::TruncateDoubleToI(Isolate* isolate, Zone* zone, ++ Register result, ++ DoubleRegister double_input, ++ StubCallMode stub_mode) { ++ Label done; ++ ++ TryInlineTruncateDoubleToI(result, double_input, &done); ++ ++ // If we fell through then inline version didn't succeed - call stub ++ // instead. ++ push(ra); ++ Sub64(sp, sp, Operand(kDoubleSize)); // Put input on stack. ++ fsd(double_input, sp, 0); ++ ++ if (stub_mode == StubCallMode::kCallWasmRuntimeStub) { ++ Call(wasm::WasmCode::kDoubleToI, RelocInfo::WASM_STUB_CALL); ++ } else { ++ Call(BUILTIN_CODE(isolate, DoubleToI), RelocInfo::CODE_TARGET); ++ } ++ ld(result, sp, 0); ++ ++ Add64(sp, sp, Operand(kDoubleSize)); ++ pop(ra); ++ ++ bind(&done); ++} ++ ++// BRANCH_ARGS_CHECK checks that conditional jump arguments are correct. ++#define BRANCH_ARGS_CHECK(cond, rs, rt) \ ++ DCHECK((cond == cc_always && rs == zero_reg && rt.rm() == zero_reg) || \ ++ (cond != cc_always && (rs != zero_reg || rt.rm() != zero_reg))) ++ ++void TurboAssembler::Branch(int32_t offset) { ++ DCHECK(is_int21(offset)); ++ BranchShort(offset); ++} ++ ++void TurboAssembler::Branch(int32_t offset, Condition cond, Register rs, ++ const Operand& rt) { ++ bool is_near = BranchShortCheck(offset, nullptr, cond, rs, rt); ++ DCHECK(is_near); ++ USE(is_near); ++} ++ ++void TurboAssembler::Branch(Label* L) { ++ if (L->is_bound()) { ++ if (is_near(L)) { ++ BranchShort(L); ++ } else { ++ BranchLong(L); ++ } ++ } else { ++ if (is_trampoline_emitted()) { ++ BranchLong(L); ++ } else { ++ BranchShort(L); ++ } ++ } ++} ++ ++void TurboAssembler::Branch(Label* L, Condition cond, Register rs, ++ const Operand& rt) { ++ if (L->is_bound()) { ++ if (!BranchShortCheck(0, L, cond, rs, rt)) { ++ if (cond != cc_always) { ++ Label skip; ++ Condition neg_cond = NegateCondition(cond); ++ BranchShort(&skip, neg_cond, rs, rt); ++ BranchLong(L); ++ bind(&skip); ++ } else { ++ BranchLong(L); ++ } ++ } ++ } else { ++ if (is_trampoline_emitted()) { ++ if (cond != cc_always) { ++ Label skip; ++ Condition neg_cond = NegateCondition(cond); ++ BranchShort(&skip, neg_cond, rs, rt); ++ BranchLong(L); ++ bind(&skip); ++ } else { ++ BranchLong(L); ++ } ++ } else { ++ BranchShort(L, cond, rs, rt); ++ } ++ } ++} ++ ++void TurboAssembler::Branch(Label* L, Condition cond, Register rs, ++ RootIndex index) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ LoadRoot(scratch, index); ++ Branch(L, cond, rs, Operand(scratch)); ++} ++ ++void TurboAssembler::BranchShortHelper(int32_t offset, Label* L) { ++ DCHECK(L == nullptr || offset == 0); ++ offset = GetOffset(offset, L, OffsetSize::kOffset21); ++ j(offset); ++} ++ ++void TurboAssembler::BranchShort(int32_t offset) { ++ DCHECK(is_int21(offset)); ++ BranchShortHelper(offset, nullptr); ++} ++ ++void TurboAssembler::BranchShort(Label* L) { BranchShortHelper(0, L); } ++ ++int32_t TurboAssembler::GetOffset(int32_t offset, Label* L, OffsetSize bits) { ++ if (L) { ++ offset = branch_offset_helper(L, bits); ++ } else { ++ DCHECK(is_intn(offset, bits)); ++ } ++ return offset; ++} ++ ++Register TurboAssembler::GetRtAsRegisterHelper(const Operand& rt, ++ Register scratch) { ++ Register r2 = no_reg; ++ if (rt.is_reg()) { ++ r2 = rt.rm(); ++ } else { ++ r2 = scratch; ++ li(r2, rt); ++ } ++ ++ return r2; ++} ++ ++bool TurboAssembler::CalculateOffset(Label* L, int32_t* offset, ++ OffsetSize bits) { ++ if (!is_near(L, bits)) return false; ++ *offset = GetOffset(*offset, L, bits); ++ return true; ++} ++ ++bool TurboAssembler::CalculateOffset(Label* L, int32_t* offset, OffsetSize bits, ++ Register* scratch, const Operand& rt) { ++ if (!is_near(L, bits)) return false; ++ *scratch = GetRtAsRegisterHelper(rt, *scratch); ++ *offset = GetOffset(*offset, L, bits); ++ return true; ++} ++ ++bool TurboAssembler::BranchShortHelper(int32_t offset, Label* L, Condition cond, ++ Register rs, const Operand& rt) { ++ DCHECK(L == nullptr || offset == 0); ++ UseScratchRegisterScope temps(this); ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register scratch = temps.hasAvailable() ? temps.Acquire() : t5; ++ ++ { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ switch (cond) { ++ case cc_always: ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ break; ++ case eq: ++ // rs == rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ beq(rs, scratch, offset); ++ } ++ break; ++ case ne: ++ // rs != rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ break; // No code needs to be emitted ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bne(rs, scratch, offset); ++ } ++ break; ++ ++ // Signed comparison. ++ case greater: ++ // rs > rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ break; // No code needs to be emitted. ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bgt(rs, scratch, offset); ++ } ++ break; ++ case greater_equal: ++ // rs >= rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bge(rs, scratch, offset); ++ } ++ break; ++ case less: ++ // rs < rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ break; // No code needs to be emitted. ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ blt(rs, scratch, offset); ++ } ++ break; ++ case less_equal: ++ // rs <= rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ ble(rs, scratch, offset); ++ } ++ break; ++ ++ // Unsigned comparison. ++ case Ugreater: ++ // rs > rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ break; // No code needs to be emitted. ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bgtu(rs, scratch, offset); ++ } ++ break; ++ case Ugreater_equal: ++ // rs >= rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bgeu(rs, scratch, offset); ++ } ++ break; ++ case Uless: ++ // rs < rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ break; // No code needs to be emitted. ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bltu(rs, scratch, offset); ++ } ++ break; ++ case Uless_equal: ++ // rs <= rt ++ if (rt.is_reg() && rs == rt.rm()) { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset21)) return false; ++ j(offset); ++ } else { ++ if (!CalculateOffset(L, &offset, OffsetSize::kOffset13, &scratch, rt)) ++ return false; ++ DCHECK(rs != scratch); ++ bleu(rs, scratch, offset); ++ } ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++ ++ CheckTrampolinePoolQuick(1); ++ return true; ++} ++ ++bool TurboAssembler::BranchShortCheck(int32_t offset, Label* L, Condition cond, ++ Register rs, const Operand& rt) { ++ BRANCH_ARGS_CHECK(cond, rs, rt); ++ ++ if (!L) { ++ DCHECK(is_int13(offset)); ++ return BranchShortHelper(offset, nullptr, cond, rs, rt); ++ } else { ++ DCHECK_EQ(offset, 0); ++ return BranchShortHelper(0, L, cond, rs, rt); ++ } ++ return false; ++} ++ ++void TurboAssembler::BranchShort(int32_t offset, Condition cond, Register rs, ++ const Operand& rt) { ++ BranchShortCheck(offset, nullptr, cond, rs, rt); ++} ++ ++void TurboAssembler::BranchShort(Label* L, Condition cond, Register rs, ++ const Operand& rt) { ++ BranchShortCheck(0, L, cond, rs, rt); ++} ++ ++void TurboAssembler::BranchAndLink(int32_t offset) { ++ BranchAndLinkShort(offset); ++} ++ ++void TurboAssembler::BranchAndLink(int32_t offset, Condition cond, Register rs, ++ const Operand& rt) { ++ bool is_near = BranchAndLinkShortCheck(offset, nullptr, cond, rs, rt); ++ DCHECK(is_near); ++ USE(is_near); ++} ++ ++void TurboAssembler::BranchAndLink(Label* L) { ++ if (L->is_bound()) { ++ if (is_near(L)) { ++ BranchAndLinkShort(L); ++ } else { ++ BranchAndLinkLong(L); ++ } ++ } else { ++ if (is_trampoline_emitted()) { ++ BranchAndLinkLong(L); ++ } else { ++ BranchAndLinkShort(L); ++ } ++ } ++} ++ ++void TurboAssembler::BranchAndLink(Label* L, Condition cond, Register rs, ++ const Operand& rt) { ++ if (L->is_bound()) { ++ if (!BranchAndLinkShortCheck(0, L, cond, rs, rt)) { ++ Label skip; ++ Condition neg_cond = NegateCondition(cond); ++ BranchShort(&skip, neg_cond, rs, rt); ++ BranchAndLinkLong(L); ++ bind(&skip); ++ } ++ } else { ++ if (is_trampoline_emitted()) { ++ Label skip; ++ Condition neg_cond = NegateCondition(cond); ++ BranchShort(&skip, neg_cond, rs, rt); ++ BranchAndLinkLong(L); ++ bind(&skip); ++ } else { ++ BranchAndLinkShortCheck(0, L, cond, rs, rt); ++ } ++ } ++} ++ ++void TurboAssembler::BranchAndLinkShortHelper(int32_t offset, Label* L) { ++ DCHECK(L == nullptr || offset == 0); ++ offset = GetOffset(offset, L, OffsetSize::kOffset21); ++ jal(offset); ++} ++ ++void TurboAssembler::BranchAndLinkShort(int32_t offset) { ++ DCHECK(is_int21(offset)); ++ BranchAndLinkShortHelper(offset, nullptr); ++} ++ ++void TurboAssembler::BranchAndLinkShort(Label* L) { ++ BranchAndLinkShortHelper(0, L); ++} ++ ++// Pre r6 we need to use a bgezal or bltzal, but they can't be used directly ++// with the slt instructions. We could use sub or add instead but we would miss ++// overflow cases, so we keep slt and add an intermediate third instruction. ++bool TurboAssembler::BranchAndLinkShortHelper(int32_t offset, Label* L, ++ Condition cond, Register rs, ++ const Operand& rt) { ++ DCHECK(L == nullptr || offset == 0); ++ if (!is_near(L, OffsetSize::kOffset21)) return false; ++ ++ Register scratch = t5; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ ++ if (cond == cc_always) { ++ offset = GetOffset(offset, L, OffsetSize::kOffset21); ++ jal(offset); ++ } else { ++ Branch(kInstrSize * 2, NegateCondition(cond), rs, ++ Operand(GetRtAsRegisterHelper(rt, scratch))); ++ offset = GetOffset(offset, L, OffsetSize::kOffset21); ++ jal(offset); ++ } ++ ++ return true; ++} ++ ++bool TurboAssembler::BranchAndLinkShortCheck(int32_t offset, Label* L, ++ Condition cond, Register rs, ++ const Operand& rt) { ++ BRANCH_ARGS_CHECK(cond, rs, rt); ++ ++ if (!L) { ++ DCHECK(is_int21(offset)); ++ return BranchAndLinkShortHelper(offset, nullptr, cond, rs, rt); ++ } else { ++ DCHECK_EQ(offset, 0); ++ return BranchAndLinkShortHelper(0, L, cond, rs, rt); ++ } ++ return false; ++} ++ ++void TurboAssembler::LoadFromConstantsTable(Register destination, ++ int constant_index) { ++ DCHECK(RootsTable::IsImmortalImmovable(RootIndex::kBuiltinsConstantsTable)); ++ LoadRoot(destination, RootIndex::kBuiltinsConstantsTable); ++ Ld(destination, ++ FieldMemOperand(destination, ++ FixedArray::kHeaderSize + constant_index * kPointerSize)); ++} ++ ++void TurboAssembler::LoadRootRelative(Register destination, int32_t offset) { ++ Ld(destination, MemOperand(kRootRegister, offset)); ++} ++ ++void TurboAssembler::LoadRootRegisterOffset(Register destination, ++ intptr_t offset) { ++ if (offset == 0) { ++ Move(destination, kRootRegister); ++ } else { ++ Add64(destination, kRootRegister, Operand(offset)); ++ } ++} ++ ++void TurboAssembler::Jump(Register target, Condition cond, Register rs, ++ const Operand& rt) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (cond == cc_always) { ++ jr(target); ++ } else { ++ BRANCH_ARGS_CHECK(cond, rs, rt); ++ Branch(kInstrSize * 2, NegateCondition(cond), rs, rt); ++ jr(target); ++ } ++} ++ ++void TurboAssembler::Jump(intptr_t target, RelocInfo::Mode rmode, ++ Condition cond, Register rs, const Operand& rt) { ++ Label skip; ++ if (cond != cc_always) { ++ Branch(&skip, NegateCondition(cond), rs, rt); ++ } ++ { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ li(t6, Operand(target, rmode)); ++ Jump(t6, al, zero_reg, Operand(zero_reg)); ++ bind(&skip); ++ } ++} ++ ++void TurboAssembler::Jump(Address target, RelocInfo::Mode rmode, Condition cond, ++ Register rs, const Operand& rt) { ++ DCHECK(!RelocInfo::IsCodeTarget(rmode)); ++ Jump(static_cast(target), rmode, cond, rs, rt); ++} ++ ++void TurboAssembler::Jump(Handle code, RelocInfo::Mode rmode, ++ Condition cond, Register rs, const Operand& rt) { ++ DCHECK(RelocInfo::IsCodeTarget(rmode)); ++ ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (root_array_available_ && options().isolate_independent_code) { ++ IndirectLoadConstant(t6, code); ++ Add64(t6, t6, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ Jump(t6, cond, rs, rt); ++ return; ++ } else if (options().inline_offheap_trampolines) { ++ int builtin_index = Builtins::kNoBuiltinId; ++ if (isolate()->builtins()->IsBuiltinHandle(code, &builtin_index) && ++ Builtins::IsIsolateIndependent(builtin_index)) { ++ // Inline the trampoline. ++ RecordCommentForOffHeapTrampoline(builtin_index); ++ CHECK_NE(builtin_index, Builtins::kNoBuiltinId); ++ EmbeddedData d = EmbeddedData::FromBlob(); ++ Address entry = d.InstructionStartOfBuiltin(builtin_index); ++ li(t6, Operand(entry, RelocInfo::OFF_HEAP_TARGET)); ++ Jump(t6, cond, rs, rt); ++ return; ++ } ++ } ++ ++ Jump(static_cast(code.address()), rmode, cond, rs, rt); ++} ++ ++void TurboAssembler::Jump(const ExternalReference& reference) { ++ li(t6, reference); ++ Jump(t6); ++} ++ ++// FIXME (RISCV): the comment does not make sense, where is t6 used? ++// Note: To call gcc-compiled C code on riscv64, you must call through t6. ++void TurboAssembler::Call(Register target, Condition cond, Register rs, ++ const Operand& rt) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (cond == cc_always) { ++ jalr(ra, target, 0); ++ } else { ++ BRANCH_ARGS_CHECK(cond, rs, rt); ++ Branch(kInstrSize * 2, NegateCondition(cond), rs, rt); ++ jalr(ra, target, 0); ++ } ++} ++ ++void MacroAssembler::JumpIfIsInRange(Register value, unsigned lower_limit, ++ unsigned higher_limit, ++ Label* on_in_range) { ++ if (lower_limit != 0) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Sub64(scratch, value, Operand(lower_limit)); ++ Branch(on_in_range, Uless_equal, scratch, ++ Operand(higher_limit - lower_limit)); ++ } else { ++ Branch(on_in_range, Uless_equal, value, ++ Operand(higher_limit - lower_limit)); ++ } ++} ++ ++void TurboAssembler::Call(Address target, RelocInfo::Mode rmode, Condition cond, ++ Register rs, const Operand& rt) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ li(t6, Operand(static_cast(target), rmode), ADDRESS_LOAD); ++ Call(t6, cond, rs, rt); ++} ++ ++void TurboAssembler::Call(Handle code, RelocInfo::Mode rmode, ++ Condition cond, Register rs, const Operand& rt) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ ++ if (root_array_available_ && options().isolate_independent_code) { ++ IndirectLoadConstant(t6, code); ++ Add64(t6, t6, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ Call(t6, cond, rs, rt); ++ return; ++ } else if (options().inline_offheap_trampolines) { ++ int builtin_index = Builtins::kNoBuiltinId; ++ if (isolate()->builtins()->IsBuiltinHandle(code, &builtin_index) && ++ Builtins::IsIsolateIndependent(builtin_index)) { ++ // Inline the trampoline. ++ RecordCommentForOffHeapTrampoline(builtin_index); ++ CHECK_NE(builtin_index, Builtins::kNoBuiltinId); ++ EmbeddedData d = EmbeddedData::FromBlob(); ++ Address entry = d.InstructionStartOfBuiltin(builtin_index); ++ li(t6, Operand(entry, RelocInfo::OFF_HEAP_TARGET)); ++ Call(t6, cond, rs, rt); ++ return; ++ } ++ } ++ ++ DCHECK(RelocInfo::IsCodeTarget(rmode)); ++ DCHECK(code->IsExecutable()); ++ Call(code.address(), rmode, cond, rs, rt); ++} ++ ++void TurboAssembler::LoadEntryFromBuiltinIndex(Register builtin_index) { ++ STATIC_ASSERT(kSystemPointerSize == 8); ++ STATIC_ASSERT(kSmiTagSize == 1); ++ STATIC_ASSERT(kSmiTag == 0); ++ ++ // The builtin_index register contains the builtin index as a Smi. ++ SmiUntag(builtin_index, builtin_index); ++ CalcScaledAddress(builtin_index, kRootRegister, builtin_index, ++ kSystemPointerSizeLog2); ++ Ld(builtin_index, ++ MemOperand(builtin_index, IsolateData::builtin_entry_table_offset())); ++} ++ ++void TurboAssembler::CallBuiltinByIndex(Register builtin_index) { ++ LoadEntryFromBuiltinIndex(builtin_index); ++ Call(builtin_index); ++} ++ ++void TurboAssembler::PatchAndJump(Address target) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ auipc(scratch, 0); // Load PC into scratch ++ Ld(t6, MemOperand(scratch, kInstrSize * 4)); ++ jr(t6); ++ nop(); // For alignment ++ DCHECK_EQ(reinterpret_cast(pc_) % 8, 0); ++ *reinterpret_cast(pc_) = target; // pc_ should be align. ++ pc_ += sizeof(uint64_t); ++} ++ ++void TurboAssembler::StoreReturnAddressAndCall(Register target) { ++ // This generates the final instruction sequence for calls to C functions ++ // once an exit frame has been constructed. ++ // ++ // Note that this assumes the caller code (i.e. the Code object currently ++ // being generated) is immovable or that the callee function cannot trigger ++ // GC, since the callee function will return to it. ++ ++ // Compute the return address in lr to return to after the jump below. The ++ // pc is already at '+ 8' from the current instruction; but return is after ++ // three instructions, so add another 4 to pc to get the return address. ++ ++ Assembler::BlockTrampolinePoolScope block_trampoline_pool(this); ++ static constexpr int kNumInstructionsToJump = 5; ++ Label find_ra; ++ // Adjust the value in ra to point to the correct return location, one ++ // instruction past the real call into C code (the jalr(t6)), and push it. ++ // This is the return address of the exit frame. ++ auipc(ra, 0); // Set ra the current PC ++ bind(&find_ra); ++ addi(ra, ra, ++ (kNumInstructionsToJump + 1) * ++ kInstrSize); // Set ra to insn after the call ++ ++ // This spot was reserved in EnterExitFrame. ++ Sd(ra, MemOperand(sp)); ++ addi(sp, sp, -kCArgsSlotsSize); ++ // Stack is still aligned. ++ ++ // Call the C routine. ++ mv(t6, target); // Function pointer to t6 to conform to ABI for PIC. ++ jalr(t6); ++ // Make sure the stored 'ra' points to this position. ++ DCHECK_EQ(kNumInstructionsToJump, InstructionsGeneratedSince(&find_ra)); ++} ++ ++void TurboAssembler::Ret(Condition cond, Register rs, const Operand& rt) { ++ Jump(ra, cond, rs, rt); ++} ++ ++void TurboAssembler::BranchLong(Label* L) { ++ // Generate position independent long branch. ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ int64_t imm64; ++ imm64 = branch_long_offset(L); ++ DCHECK(is_int32(imm64)); ++ int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12); ++ int32_t Lo12 = (int32_t)imm64 << 20 >> 20; ++ auipc(t5, Hi20); // Read PC + Hi20 into t5. ++ jr(t5, Lo12); // jump PC + Hi20 + Lo12 ++} ++ ++void TurboAssembler::BranchAndLinkLong(Label* L) { ++ // Generate position independent long branch and link. ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ int64_t imm64; ++ imm64 = branch_long_offset(L); ++ DCHECK(is_int32(imm64)); ++ int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12); ++ int32_t Lo12 = (int32_t)imm64 << 20 >> 20; ++ auipc(t5, Hi20); // Read PC + Hi20 into t5. ++ jalr(t5, Lo12); // jump PC + Hi20 + Lo12 and read PC + 4 to ra ++} ++ ++void TurboAssembler::DropAndRet(int drop) { ++ Add64(sp, sp, drop * kPointerSize); ++ Ret(); ++} ++ ++void TurboAssembler::DropAndRet(int drop, Condition cond, Register r1, ++ const Operand& r2) { ++ // Both Drop and Ret need to be conditional. ++ Label skip; ++ if (cond != cc_always) { ++ Branch(&skip, NegateCondition(cond), r1, r2); ++ } ++ ++ Drop(drop); ++ Ret(); ++ ++ if (cond != cc_always) { ++ bind(&skip); ++ } ++} ++ ++void TurboAssembler::Drop(int count, Condition cond, Register reg, ++ const Operand& op) { ++ if (count <= 0) { ++ return; ++ } ++ ++ Label skip; ++ ++ if (cond != al) { ++ Branch(&skip, NegateCondition(cond), reg, op); ++ } ++ ++ Add64(sp, sp, Operand(count * kPointerSize)); ++ ++ if (cond != al) { ++ bind(&skip); ++ } ++} ++ ++void MacroAssembler::Swap(Register reg1, Register reg2, Register scratch) { ++ if (scratch == no_reg) { ++ Xor(reg1, reg1, Operand(reg2)); ++ Xor(reg2, reg2, Operand(reg1)); ++ Xor(reg1, reg1, Operand(reg2)); ++ } else { ++ mv(scratch, reg1); ++ mv(reg1, reg2); ++ mv(reg2, scratch); ++ } ++} ++ ++void TurboAssembler::Call(Label* target) { BranchAndLink(target); } ++ ++void TurboAssembler::LoadAddress(Register dst, Label* target) { ++ uint64_t address = jump_address(target); ++ li(dst, address, ADDRESS_LOAD); ++} ++ ++void TurboAssembler::Push(Smi smi) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(smi)); ++ push(scratch); ++} ++ ++void TurboAssembler::Push(Handle handle) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(handle)); ++ push(scratch); ++} ++ ++void MacroAssembler::MaybeDropFrames() { ++ // Check whether we need to drop frames to restart a function on the stack. ++ li(a1, ExternalReference::debug_restart_fp_address(isolate())); ++ Ld(a1, MemOperand(a1)); ++ Jump(BUILTIN_CODE(isolate(), FrameDropperTrampoline), RelocInfo::CODE_TARGET, ++ ne, a1, Operand(zero_reg)); ++} ++ ++// --------------------------------------------------------------------------- ++// Exception handling. ++ ++void MacroAssembler::PushStackHandler() { ++ // Adjust this code if not the case. ++ STATIC_ASSERT(StackHandlerConstants::kSize == 2 * kPointerSize); ++ STATIC_ASSERT(StackHandlerConstants::kNextOffset == 0 * kPointerSize); ++ ++ Push(Smi::zero()); // Padding. ++ ++ // Link the current handler as the next handler. ++ li(t2, ++ ExternalReference::Create(IsolateAddressId::kHandlerAddress, isolate())); ++ Ld(t1, MemOperand(t2)); ++ push(t1); ++ ++ // Set this new handler as the current one. ++ Sd(sp, MemOperand(t2)); ++} ++ ++void MacroAssembler::PopStackHandler() { ++ STATIC_ASSERT(StackHandlerConstants::kNextOffset == 0); ++ pop(a1); ++ Add64(sp, sp, ++ Operand( ++ static_cast(StackHandlerConstants::kSize - kPointerSize))); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, ++ ExternalReference::Create(IsolateAddressId::kHandlerAddress, isolate())); ++ Sd(a1, MemOperand(scratch)); ++} ++ ++void TurboAssembler::FPUCanonicalizeNaN(const DoubleRegister dst, ++ const DoubleRegister src) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ Label NotNaN; ++ ++ fmv_d(dst, src); ++ feq_d(scratch, src, src); ++ bne(scratch, zero_reg, &NotNaN); ++ RV_li(scratch, 0x7ff8000000000000ULL); // This is the canonical NaN ++ fmv_d_x(dst, scratch); ++ bind(&NotNaN); ++} ++ ++void TurboAssembler::MovFromFloatResult(const DoubleRegister dst) { ++ Move(dst, fa0); // Reg fa0 is FP return value. ++} ++ ++void TurboAssembler::MovFromFloatParameter(const DoubleRegister dst) { ++ Move(dst, fa0); // Reg fa0 is FP first argument value. ++} ++ ++void TurboAssembler::MovToFloatParameter(DoubleRegister src) { Move(fa0, src); } ++ ++void TurboAssembler::MovToFloatResult(DoubleRegister src) { Move(fa0, src); } ++ ++void TurboAssembler::MovToFloatParameters(DoubleRegister src1, ++ DoubleRegister src2) { ++ const DoubleRegister fparg2 = fa1; ++ if (src2 == fa0) { ++ DCHECK(src1 != fparg2); ++ Move(fparg2, src2); ++ Move(fa0, src1); ++ } else { ++ Move(fa0, src1); ++ Move(fparg2, src2); ++ } ++} ++ ++// ----------------------------------------------------------------------------- ++// JavaScript invokes. ++ ++void TurboAssembler::PrepareForTailCall(Register callee_args_count, ++ Register caller_args_count, ++ Register scratch0, Register scratch1) { ++ // Calculate the end of destination area where we will put the arguments ++ // after we drop current frame. We add kPointerSize to count the receiver ++ // argument which is not included into formal parameters count. ++ Register dst_reg = scratch0; ++ CalcScaledAddress(dst_reg, fp, caller_args_count, kPointerSizeLog2); ++ Add64(dst_reg, dst_reg, ++ Operand(StandardFrameConstants::kCallerSPOffset + kPointerSize)); ++ ++ Register src_reg = caller_args_count; ++ // Calculate the end of source area. +kPointerSize is for the receiver. ++ CalcScaledAddress(src_reg, sp, callee_args_count, kPointerSizeLog2); ++ Add64(src_reg, src_reg, Operand(kPointerSize)); ++ ++ if (FLAG_debug_code) { ++ Check(Uless, AbortReason::kStackAccessBelowStackPointer, src_reg, ++ Operand(dst_reg)); ++ } ++ ++ // Restore caller's frame pointer and return address now as they will be ++ // overwritten by the copying loop. ++ Ld(ra, MemOperand(fp, StandardFrameConstants::kCallerPCOffset)); ++ Ld(fp, MemOperand(fp, StandardFrameConstants::kCallerFPOffset)); ++ ++ // Now copy callee arguments to the caller frame going backwards to avoid ++ // callee arguments corruption (source and destination areas could overlap). ++ ++ // Both src_reg and dst_reg are pointing to the word after the one to copy, ++ // so they must be pre-decremented in the loop. ++ Register tmp_reg = scratch1; ++ Label loop, entry; ++ Branch(&entry); ++ bind(&loop); ++ Sub64(src_reg, src_reg, Operand(kPointerSize)); ++ Sub64(dst_reg, dst_reg, Operand(kPointerSize)); ++ Ld(tmp_reg, MemOperand(src_reg)); ++ Sd(tmp_reg, MemOperand(dst_reg)); ++ bind(&entry); ++ Branch(&loop, ne, sp, Operand(src_reg)); ++ ++ // Leave current frame. ++ mv(sp, dst_reg); ++} ++ ++void MacroAssembler::InvokePrologue(Register expected_parameter_count, ++ Register actual_parameter_count, ++ Label* done, InvokeFlag flag) { ++ Label regular_invoke; ++ ++ // Check whether the expected and actual arguments count match. The ++ // registers are set up according to contract with ++ // ArgumentsAdaptorTrampoline: ++ // a0: actual arguments count ++ // a1: function (passed through to callee) ++ // a2: expected arguments count ++ ++ // The code below is made a lot easier because the calling code already sets ++ // up actual and expected registers according to the contract. ++ ++ DCHECK_EQ(actual_parameter_count, a0); ++ DCHECK_EQ(expected_parameter_count, a2); ++ ++ Branch(®ular_invoke, eq, expected_parameter_count, ++ Operand(actual_parameter_count)); ++ ++ Handle adaptor = BUILTIN_CODE(isolate(), ArgumentsAdaptorTrampoline); ++ if (flag == CALL_FUNCTION) { ++ Call(adaptor); ++ Branch(done); ++ } else { ++ Jump(adaptor, RelocInfo::CODE_TARGET); ++ } ++ ++ bind(®ular_invoke); ++} ++ ++void MacroAssembler::CheckDebugHook(Register fun, Register new_target, ++ Register expected_parameter_count, ++ Register actual_parameter_count) { ++ Label skip_hook; ++ ++ li(t0, ExternalReference::debug_hook_on_function_call_address(isolate())); ++ Lb(t0, MemOperand(t0)); ++ Branch(&skip_hook, eq, t0, Operand(zero_reg)); ++ ++ { ++ // Load receiver to pass it later to DebugOnFunctionCall hook. ++ CalcScaledAddress(t0, sp, actual_parameter_count, kPointerSizeLog2); ++ Ld(t0, MemOperand(t0)); ++ FrameScope frame(this, ++ has_frame() ? StackFrame::NONE : StackFrame::INTERNAL); ++ SmiTag(expected_parameter_count); ++ Push(expected_parameter_count); ++ ++ SmiTag(actual_parameter_count); ++ Push(actual_parameter_count); ++ ++ if (new_target.is_valid()) { ++ Push(new_target); ++ } ++ Push(fun); ++ Push(fun); ++ Push(t0); ++ CallRuntime(Runtime::kDebugOnFunctionCall); ++ Pop(fun); ++ if (new_target.is_valid()) { ++ Pop(new_target); ++ } ++ ++ Pop(actual_parameter_count); ++ SmiUntag(actual_parameter_count); ++ ++ Pop(expected_parameter_count); ++ SmiUntag(expected_parameter_count); ++ } ++ bind(&skip_hook); ++} ++ ++void MacroAssembler::InvokeFunctionCode(Register function, Register new_target, ++ Register expected_parameter_count, ++ Register actual_parameter_count, ++ InvokeFlag flag) { ++ // You can't call a function without a valid frame. ++ DCHECK_IMPLIES(flag == CALL_FUNCTION, has_frame()); ++ DCHECK_EQ(function, a1); ++ DCHECK_IMPLIES(new_target.is_valid(), new_target == a3); ++ ++ // On function call, call into the debugger if necessary. ++ CheckDebugHook(function, new_target, expected_parameter_count, ++ actual_parameter_count); ++ ++ // Clear the new.target register if not given. ++ if (!new_target.is_valid()) { ++ LoadRoot(a3, RootIndex::kUndefinedValue); ++ } ++ ++ Label done; ++ InvokePrologue(expected_parameter_count, actual_parameter_count, &done, flag); ++ // We call indirectly through the code field in the function to ++ // allow recompilation to take effect without changing any of the ++ // call sites. ++ Register code = kJavaScriptCallCodeStartRegister; ++ Ld(code, FieldMemOperand(function, JSFunction::kCodeOffset)); ++ if (flag == CALL_FUNCTION) { ++ Add64(code, code, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ Call(code); ++ } else { ++ DCHECK(flag == JUMP_FUNCTION); ++ Add64(code, code, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ Jump(code); ++ } ++ ++ // Continue here if InvokePrologue does handle the invocation due to ++ // mismatched parameter counts. ++ bind(&done); ++} ++ ++void MacroAssembler::InvokeFunctionWithNewTarget( ++ Register function, Register new_target, Register actual_parameter_count, ++ InvokeFlag flag) { ++ // You can't call a function without a valid frame. ++ DCHECK_IMPLIES(flag == CALL_FUNCTION, has_frame()); ++ ++ // Contract with called JS functions requires that function is passed in a1. ++ DCHECK_EQ(function, a1); ++ Register expected_parameter_count = a2; ++ Register temp_reg = t0; ++ Ld(temp_reg, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ Ld(cp, FieldMemOperand(a1, JSFunction::kContextOffset)); ++ // The argument count is stored as uint16_t ++ Lhu(expected_parameter_count, ++ FieldMemOperand(temp_reg, ++ SharedFunctionInfo::kFormalParameterCountOffset)); ++ ++ InvokeFunctionCode(a1, new_target, expected_parameter_count, ++ actual_parameter_count, flag); ++} ++ ++void MacroAssembler::InvokeFunction(Register function, ++ Register expected_parameter_count, ++ Register actual_parameter_count, ++ InvokeFlag flag) { ++ // You can't call a function without a valid frame. ++ DCHECK_IMPLIES(flag == CALL_FUNCTION, has_frame()); ++ ++ // Contract with called JS functions requires that function is passed in a1. ++ DCHECK_EQ(function, a1); ++ ++ // Get the function and setup the context. ++ Ld(cp, FieldMemOperand(a1, JSFunction::kContextOffset)); ++ ++ InvokeFunctionCode(a1, no_reg, expected_parameter_count, ++ actual_parameter_count, flag); ++} ++ ++// --------------------------------------------------------------------------- ++// Support functions. ++ ++void MacroAssembler::GetObjectType(Register object, Register map, ++ Register type_reg) { ++ LoadMap(map, object); ++ Lhu(type_reg, FieldMemOperand(map, Map::kInstanceTypeOffset)); ++} ++ ++// ----------------------------------------------------------------------------- ++// Runtime calls. ++ ++void TurboAssembler::AddOverflow64(Register dst, Register left, ++ const Operand& right, Register overflow) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register right_reg = no_reg; ++ Register scratch = t5; ++ if (!right.is_reg()) { ++ li(t3, Operand(right)); ++ right_reg = t3; ++ } else { ++ right_reg = right.rm(); ++ } ++ DCHECK(left != scratch && right_reg != scratch && dst != scratch && ++ overflow != scratch); ++ DCHECK(overflow != left && overflow != right_reg); ++ if (dst == left || dst == right_reg) { ++ add(scratch, left, right_reg); ++ xor_(overflow, scratch, left); ++ xor_(t3, scratch, right_reg); ++ and_(overflow, overflow, t3); ++ mv(dst, scratch); ++ } else { ++ add(dst, left, right_reg); ++ xor_(overflow, dst, left); ++ xor_(t3, dst, right_reg); ++ and_(overflow, overflow, t3); ++ } ++} ++ ++void TurboAssembler::SubOverflow64(Register dst, Register left, ++ const Operand& right, Register overflow) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register right_reg = no_reg; ++ Register scratch = t5; ++ if (!right.is_reg()) { ++ li(t3, Operand(right)); ++ right_reg = t3; ++ } else { ++ right_reg = right.rm(); ++ } ++ ++ DCHECK(left != scratch && right_reg != scratch && dst != scratch && ++ overflow != scratch); ++ DCHECK(overflow != left && overflow != right_reg); ++ ++ if (dst == left || dst == right_reg) { ++ sub(scratch, left, right_reg); ++ xor_(overflow, left, scratch); ++ xor_(t3, left, right_reg); ++ and_(overflow, overflow, t3); ++ mv(dst, scratch); ++ } else { ++ sub(dst, left, right_reg); ++ xor_(overflow, left, dst); ++ xor_(t3, left, right_reg); ++ and_(overflow, overflow, t3); ++ } ++} ++ ++void TurboAssembler::MulOverflow32(Register dst, Register left, ++ const Operand& right, Register overflow) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ Register right_reg = no_reg; ++ Register scratch = t5; ++ if (!right.is_reg()) { ++ li(t3, Operand(right)); ++ right_reg = t3; ++ } else { ++ right_reg = right.rm(); ++ } ++ ++ DCHECK(left != scratch && right_reg != scratch && dst != scratch && ++ overflow != scratch); ++ DCHECK(overflow != left && overflow != right_reg); ++ sext_w(overflow, left); ++ sext_w(scratch, right_reg); ++ ++ mul(overflow, overflow, scratch); ++ sext_w(dst, overflow); ++ xor_(overflow, overflow, dst); ++} ++ ++void MacroAssembler::CallRuntime(const Runtime::Function* f, int num_arguments, ++ SaveFPRegsMode save_doubles) { ++ // All parameters are on the stack. a0 has the return value after call. ++ ++ // If the expected number of arguments of the runtime function is ++ // constant, we check that the actual number of arguments match the ++ // expectation. ++ CHECK(f->nargs < 0 || f->nargs == num_arguments); ++ ++ // TODO(1236192): Most runtime routines don't need the number of ++ // arguments passed in because it is constant. At some point we ++ // should remove this need and make the runtime routine entry code ++ // smarter. ++ PrepareCEntryArgs(num_arguments); ++ PrepareCEntryFunction(ExternalReference::Create(f)); ++ Handle code = ++ CodeFactory::CEntry(isolate(), f->result_size, save_doubles); ++ Call(code, RelocInfo::CODE_TARGET); ++} ++ ++void MacroAssembler::TailCallRuntime(Runtime::FunctionId fid) { ++ const Runtime::Function* function = Runtime::FunctionForId(fid); ++ DCHECK_EQ(1, function->result_size); ++ if (function->nargs >= 0) { ++ PrepareCEntryArgs(function->nargs); ++ } ++ JumpToExternalReference(ExternalReference::Create(fid)); ++} ++ ++void MacroAssembler::JumpToExternalReference(const ExternalReference& builtin, ++ bool builtin_exit_frame) { ++ PrepareCEntryFunction(builtin); ++ Handle code = CodeFactory::CEntry(isolate(), 1, kDontSaveFPRegs, ++ kArgvOnStack, builtin_exit_frame); ++ Jump(code, RelocInfo::CODE_TARGET, al, zero_reg, Operand(zero_reg)); ++} ++ ++void MacroAssembler::JumpToInstructionStream(Address entry) { ++ li(kOffHeapTrampolineRegister, Operand(entry, RelocInfo::OFF_HEAP_TARGET)); ++ Jump(kOffHeapTrampolineRegister); ++} ++ ++void MacroAssembler::LoadWeakValue(Register out, Register in, ++ Label* target_if_cleared) { ++ Branch(target_if_cleared, eq, in, Operand(kClearedWeakHeapObjectLower32)); ++ ++ And(out, in, Operand(~kWeakHeapObjectMask)); ++} ++ ++void MacroAssembler::IncrementCounter(StatsCounter* counter, int value, ++ Register scratch1, Register scratch2) { ++ DCHECK_GT(value, 0); ++ if (FLAG_native_code_counters && counter->Enabled()) { ++ // This operation has to be exactly 32-bit wide in case the external ++ // reference table redirects the counter to a uint32_t ++ // dummy_stats_counter_ field. ++ li(scratch2, ExternalReference::Create(counter)); ++ Lw(scratch1, MemOperand(scratch2)); ++ Add32(scratch1, scratch1, Operand(value)); ++ Sw(scratch1, MemOperand(scratch2)); ++ } ++} ++ ++void MacroAssembler::DecrementCounter(StatsCounter* counter, int value, ++ Register scratch1, Register scratch2) { ++ DCHECK_GT(value, 0); ++ if (FLAG_native_code_counters && counter->Enabled()) { ++ // This operation has to be exactly 32-bit wide in case the external ++ // reference table redirects the counter to a uint32_t ++ // dummy_stats_counter_ field. ++ li(scratch2, ExternalReference::Create(counter)); ++ Lw(scratch1, MemOperand(scratch2)); ++ Sub32(scratch1, scratch1, Operand(value)); ++ Sw(scratch1, MemOperand(scratch2)); ++ } ++} ++ ++// ----------------------------------------------------------------------------- ++// Debugging. ++ ++void TurboAssembler::Trap() { stop(); } ++void TurboAssembler::DebugBreak() { stop(); } ++ ++void TurboAssembler::Assert(Condition cc, AbortReason reason, Register rs, ++ Operand rt) { ++ if (emit_debug_code()) Check(cc, reason, rs, rt); ++} ++ ++void TurboAssembler::Check(Condition cc, AbortReason reason, Register rs, ++ Operand rt) { ++ Label L; ++ Branch(&L, cc, rs, rt); ++ Abort(reason); ++ // Will not return here. ++ bind(&L); ++} ++ ++void TurboAssembler::Abort(AbortReason reason) { ++ Label abort_start; ++ bind(&abort_start); ++#ifdef DEBUG ++ const char* msg = GetAbortReason(reason); ++ RecordComment("Abort message: "); ++ RecordComment(msg); ++#endif ++ ++ // Avoid emitting call to builtin if requested. ++ if (trap_on_abort()) { ++ ebreak(); ++ return; ++ } ++ ++ if (should_abort_hard()) { ++ // We don't care if we constructed a frame. Just pretend we did. ++ FrameScope assume_frame(this, StackFrame::NONE); ++ PrepareCallCFunction(0, a0); ++ li(a0, Operand(static_cast(reason))); ++ CallCFunction(ExternalReference::abort_with_reason(), 1); ++ return; ++ } ++ ++ Move(a0, Smi::FromInt(static_cast(reason))); ++ ++ // Disable stub call restrictions to always allow calls to abort. ++ if (!has_frame()) { ++ // We don't actually want to generate a pile of code for this, so just ++ // claim there is a stack frame, without generating one. ++ FrameScope scope(this, StackFrame::NONE); ++ Call(BUILTIN_CODE(isolate(), Abort), RelocInfo::CODE_TARGET); ++ } else { ++ Call(BUILTIN_CODE(isolate(), Abort), RelocInfo::CODE_TARGET); ++ } ++ // Will not return here. ++ if (is_trampoline_pool_blocked()) { ++ // If the calling code cares about the exact number of ++ // instructions generated, we insert padding here to keep the size ++ // of the Abort macro constant. ++ // Currently in debug mode with debug_code enabled the number of ++ // generated instructions is 10, so we use this as a maximum value. ++ static const int kExpectedAbortInstructions = 10; ++ int abort_instructions = InstructionsGeneratedSince(&abort_start); ++ DCHECK_LE(abort_instructions, kExpectedAbortInstructions); ++ while (abort_instructions++ < kExpectedAbortInstructions) { ++ nop(); ++ } ++ } ++} ++ ++void MacroAssembler::LoadMap(Register destination, Register object) { ++ Ld(destination, FieldMemOperand(object, HeapObject::kMapOffset)); ++} ++ ++void MacroAssembler::LoadNativeContextSlot(int index, Register dst) { ++ LoadMap(dst, cp); ++ Ld(dst, ++ FieldMemOperand(dst, Map::kConstructorOrBackPointerOrNativeContextOffset)); ++ Ld(dst, MemOperand(dst, Context::SlotOffset(index))); ++} ++ ++void TurboAssembler::StubPrologue(StackFrame::Type type) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(StackFrame::TypeToMarker(type))); ++ PushCommonFrame(scratch); ++} ++ ++void TurboAssembler::Prologue() { PushStandardFrame(a1); } ++ ++void TurboAssembler::EnterFrame(StackFrame::Type type) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ int stack_offset = -3 * kPointerSize; ++ const int fp_offset = 1 * kPointerSize; ++ addi(sp, sp, stack_offset); ++ stack_offset = -stack_offset - kPointerSize; ++ Sd(ra, MemOperand(sp, stack_offset)); ++ stack_offset -= kPointerSize; ++ Sd(fp, MemOperand(sp, stack_offset)); ++ stack_offset -= kPointerSize; ++ li(t6, Operand(StackFrame::TypeToMarker(type))); ++ Sd(t6, MemOperand(sp, stack_offset)); ++ // Adjust FP to point to saved FP. ++ DCHECK_EQ(stack_offset, 0); ++ Add64(fp, sp, Operand(fp_offset)); ++} ++ ++void TurboAssembler::LeaveFrame(StackFrame::Type type) { ++ addi(sp, fp, 2 * kPointerSize); ++ Ld(ra, MemOperand(fp, 1 * kPointerSize)); ++ Ld(fp, MemOperand(fp, 0 * kPointerSize)); ++} ++ ++void MacroAssembler::EnterExitFrame(bool save_doubles, int stack_space, ++ StackFrame::Type frame_type) { ++ DCHECK(frame_type == StackFrame::EXIT || ++ frame_type == StackFrame::BUILTIN_EXIT); ++ ++ // Set up the frame structure on the stack. ++ STATIC_ASSERT(2 * kPointerSize == ExitFrameConstants::kCallerSPDisplacement); ++ STATIC_ASSERT(1 * kPointerSize == ExitFrameConstants::kCallerPCOffset); ++ STATIC_ASSERT(0 * kPointerSize == ExitFrameConstants::kCallerFPOffset); ++ ++ // This is how the stack will look: ++ // fp + 2 (==kCallerSPDisplacement) - old stack's end ++ // [fp + 1 (==kCallerPCOffset)] - saved old ra ++ // [fp + 0 (==kCallerFPOffset)] - saved old fp ++ // [fp - 1 StackFrame::EXIT Smi ++ // [fp - 2 (==kSPOffset)] - sp of the called function ++ // fp - (2 + stack_space + alignment) == sp == [fp - kSPOffset] - top of the ++ // new stack (will contain saved ra) ++ ++ // Save registers and reserve room for saved entry sp. ++ addi(sp, sp, -2 * kPointerSize - ExitFrameConstants::kFixedFrameSizeFromFp); ++ Sd(ra, MemOperand(sp, 3 * kPointerSize)); ++ Sd(fp, MemOperand(sp, 2 * kPointerSize)); ++ { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ li(scratch, Operand(StackFrame::TypeToMarker(frame_type))); ++ Sd(scratch, MemOperand(sp, 1 * kPointerSize)); ++ } ++ // Set up new frame pointer. ++ addi(fp, sp, ExitFrameConstants::kFixedFrameSizeFromFp); ++ ++ if (emit_debug_code()) { ++ Sd(zero_reg, MemOperand(fp, ExitFrameConstants::kSPOffset)); ++ } ++ ++ { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ // Save the frame pointer and the context in top. ++ li(t5, ExternalReference::Create(IsolateAddressId::kCEntryFPAddress, ++ isolate())); ++ Sd(fp, MemOperand(t5)); ++ li(t5, ++ ExternalReference::Create(IsolateAddressId::kContextAddress, isolate())); ++ Sd(cp, MemOperand(t5)); ++ } ++ ++ const int frame_alignment = MacroAssembler::ActivationFrameAlignment(); ++ if (save_doubles) { ++ // The stack is already aligned to 0 modulo 8 for stores with sdc1. ++ int kNumOfSavedRegisters = FPURegister::kNumRegisters; ++ int space = kNumOfSavedRegisters * kDoubleSize; ++ Sub64(sp, sp, Operand(space)); ++ for (int i = 0; i < kNumOfSavedRegisters; i++) { ++ FPURegister reg = FPURegister::from_code(i); ++ StoreDouble(reg, MemOperand(sp, i * kDoubleSize)); ++ } ++ } ++ ++ // Reserve place for the return address, stack space and an optional slot ++ // (used by DirectCEntry to hold the return value if a struct is ++ // returned) and align the frame preparing for calling the runtime function. ++ DCHECK_GE(stack_space, 0); ++ Sub64(sp, sp, Operand((stack_space + 2) * kPointerSize)); ++ if (frame_alignment > 0) { ++ DCHECK(base::bits::IsPowerOfTwo(frame_alignment)); ++ And(sp, sp, Operand(-frame_alignment)); // Align stack. ++ } ++ ++ // Set the exit frame sp value to point just before the return address ++ // location. ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ addi(scratch, sp, kPointerSize); ++ Sd(scratch, MemOperand(fp, ExitFrameConstants::kSPOffset)); ++} ++ ++void MacroAssembler::LeaveExitFrame(bool save_doubles, Register argument_count, ++ bool do_return, ++ bool argument_count_is_length) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ // Optionally restore all double registers. ++ if (save_doubles) { ++ // Remember: we only need to restore every 2nd double FPU value. ++ int kNumOfSavedRegisters = FPURegister::kNumRegisters / 2; ++ Sub64(t5, fp, ++ Operand(ExitFrameConstants::kFixedFrameSizeFromFp + ++ kNumOfSavedRegisters * kDoubleSize)); ++ for (int i = 0; i < kNumOfSavedRegisters; i++) { ++ FPURegister reg = FPURegister::from_code(2 * i); ++ LoadDouble(reg, MemOperand(t5, i * kDoubleSize)); ++ } ++ } ++ ++ // Clear top frame. ++ li(t5, ++ ExternalReference::Create(IsolateAddressId::kCEntryFPAddress, isolate())); ++ Sd(zero_reg, MemOperand(t5)); ++ ++ // Restore current context from top and clear it in debug mode. ++ li(t5, ++ ExternalReference::Create(IsolateAddressId::kContextAddress, isolate())); ++ Ld(cp, MemOperand(t5)); ++ ++#ifdef DEBUG ++ li(t5, ++ ExternalReference::Create(IsolateAddressId::kContextAddress, isolate())); ++ Sd(a3, MemOperand(t5)); ++#endif ++ ++ // Pop the arguments, restore registers, and return. ++ mv(sp, fp); // Respect ABI stack constraint. ++ Ld(fp, MemOperand(sp, ExitFrameConstants::kCallerFPOffset)); ++ Ld(ra, MemOperand(sp, ExitFrameConstants::kCallerPCOffset)); ++ ++ if (argument_count.is_valid()) { ++ if (argument_count_is_length) { ++ add(sp, sp, argument_count); ++ } else { ++ CalcScaledAddress(sp, sp, argument_count, kPointerSizeLog2, t5); ++ } ++ } ++ ++ addi(sp, sp, 2 * kPointerSize); ++ ++ if (do_return) { ++ Ret(); ++ } ++} ++ ++int TurboAssembler::ActivationFrameAlignment() { ++#if V8_HOST_ARCH_RISCV64 ++ // Running on the real platform. Use the alignment as mandated by the local ++ // environment. ++ // Note: This will break if we ever start generating snapshots on one RISC-V ++ // platform for another RISC-V platform with a different alignment. ++ return base::OS::ActivationFrameAlignment(); ++#else // V8_HOST_ARCH_RISCV64 ++ // If we are using the simulator then we should always align to the expected ++ // alignment. As the simulator is used to generate snapshots we do not know ++ // if the target platform will need alignment, so this is controlled from a ++ // flag. ++ return FLAG_sim_stack_alignment; ++#endif // V8_HOST_ARCH_RISCV64 ++} ++ ++void MacroAssembler::AssertStackIsAligned() { ++ if (emit_debug_code()) { ++ const int frame_alignment = ActivationFrameAlignment(); ++ const int frame_alignment_mask = frame_alignment - 1; ++ ++ if (frame_alignment > kPointerSize) { ++ Label alignment_as_expected; ++ DCHECK(base::bits::IsPowerOfTwo(frame_alignment)); ++ { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ andi(scratch, sp, frame_alignment_mask); ++ Branch(&alignment_as_expected, eq, scratch, Operand(zero_reg)); ++ } ++ // Don't use Check here, as it will call Runtime_Abort re-entering here. ++ ebreak(); ++ bind(&alignment_as_expected); ++ } ++ } ++} ++ ++void TurboAssembler::SmiUntag(Register dst, const MemOperand& src) { ++ if (SmiValuesAre32Bits()) { ++ Lw(dst, MemOperand(src.rm(), SmiWordOffset(src.offset()))); ++ } else { ++ DCHECK(SmiValuesAre31Bits()); ++ Lw(dst, src); ++ SmiUntag(dst); ++ } ++} ++ ++void TurboAssembler::JumpIfSmi(Register value, Label* smi_label, ++ Register scratch) { ++ DCHECK_EQ(0, kSmiTag); ++ andi(scratch, value, kSmiTagMask); ++ Branch(smi_label, eq, scratch, Operand(zero_reg)); ++} ++ ++void MacroAssembler::JumpIfNotSmi(Register value, Label* not_smi_label, ++ Register scratch) { ++ DCHECK_EQ(0, kSmiTag); ++ andi(scratch, value, kSmiTagMask); ++ Branch(not_smi_label, ne, scratch, Operand(zero_reg)); ++} ++ ++void MacroAssembler::AssertNotSmi(Register object) { ++ if (emit_debug_code()) { ++ STATIC_ASSERT(kSmiTag == 0); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ andi(scratch, object, kSmiTagMask); ++ Check(ne, AbortReason::kOperandIsASmi, scratch, Operand(zero_reg)); ++ } ++} ++ ++void MacroAssembler::AssertSmi(Register object) { ++ if (emit_debug_code()) { ++ STATIC_ASSERT(kSmiTag == 0); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ andi(scratch, object, kSmiTagMask); ++ Check(eq, AbortReason::kOperandIsASmi, scratch, Operand(zero_reg)); ++ } ++} ++ ++void MacroAssembler::AssertConstructor(Register object) { ++ if (emit_debug_code()) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ STATIC_ASSERT(kSmiTag == 0); ++ SmiTst(object, t5); ++ Check(ne, AbortReason::kOperandIsASmiAndNotAConstructor, t5, ++ Operand(zero_reg)); ++ ++ LoadMap(t5, object); ++ Lbu(t5, FieldMemOperand(t5, Map::kBitFieldOffset)); ++ And(t5, t5, Operand(Map::Bits1::IsConstructorBit::kMask)); ++ Check(ne, AbortReason::kOperandIsNotAConstructor, t5, Operand(zero_reg)); ++ } ++} ++ ++void MacroAssembler::AssertFunction(Register object) { ++ if (emit_debug_code()) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ STATIC_ASSERT(kSmiTag == 0); ++ SmiTst(object, t5); ++ Check(ne, AbortReason::kOperandIsASmiAndNotAFunction, t5, ++ Operand(zero_reg)); ++ GetObjectType(object, t5, t5); ++ Check(eq, AbortReason::kOperandIsNotAFunction, t5, ++ Operand(JS_FUNCTION_TYPE)); ++ } ++} ++ ++void MacroAssembler::AssertBoundFunction(Register object) { ++ if (emit_debug_code()) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ STATIC_ASSERT(kSmiTag == 0); ++ SmiTst(object, t5); ++ Check(ne, AbortReason::kOperandIsASmiAndNotABoundFunction, t5, ++ Operand(zero_reg)); ++ GetObjectType(object, t5, t5); ++ Check(eq, AbortReason::kOperandIsNotABoundFunction, t5, ++ Operand(JS_BOUND_FUNCTION_TYPE)); ++ } ++} ++ ++void MacroAssembler::AssertGeneratorObject(Register object) { ++ if (!emit_debug_code()) return; ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ STATIC_ASSERT(kSmiTag == 0); ++ SmiTst(object, t5); ++ Check(ne, AbortReason::kOperandIsASmiAndNotAGeneratorObject, t5, ++ Operand(zero_reg)); ++ ++ GetObjectType(object, t5, t5); ++ ++ Label done; ++ ++ // Check if JSGeneratorObject ++ Branch(&done, eq, t5, Operand(JS_GENERATOR_OBJECT_TYPE)); ++ ++ // Check if JSAsyncFunctionObject (See MacroAssembler::CompareInstanceType) ++ Branch(&done, eq, t5, Operand(JS_ASYNC_FUNCTION_OBJECT_TYPE)); ++ ++ // Check if JSAsyncGeneratorObject ++ Branch(&done, eq, t5, Operand(JS_ASYNC_GENERATOR_OBJECT_TYPE)); ++ ++ Abort(AbortReason::kOperandIsNotAGeneratorObject); ++ ++ bind(&done); ++} ++ ++void MacroAssembler::AssertUndefinedOrAllocationSite(Register object, ++ Register scratch) { ++ if (emit_debug_code()) { ++ Label done_checking; ++ AssertNotSmi(object); ++ LoadRoot(scratch, RootIndex::kUndefinedValue); ++ Branch(&done_checking, eq, object, Operand(scratch)); ++ GetObjectType(object, scratch, scratch); ++ Assert(eq, AbortReason::kExpectedUndefinedOrCell, scratch, ++ Operand(ALLOCATION_SITE_TYPE)); ++ bind(&done_checking); ++ } ++} ++ ++template ++void TurboAssembler::FloatMinMaxHelper(FPURegister dst, FPURegister src1, ++ FPURegister src2, MaxMinKind kind) { ++ DCHECK((std::is_same::value) || ++ (std::is_same::value)); ++ ++ if (src1 == src2 && dst != src1) { ++ if (std::is_same::value) { ++ fmv_s(dst, src1); ++ } else { ++ fmv_d(dst, src1); ++ } ++ return; ++ } ++ ++ Label done, nan; ++ ++ // For RISCV, fmin_s returns the other non-NaN operand as result if only one ++ // operand is NaN; but for JS, if any operand is NaN, result is Nan. The ++ // following handles the discrepency between handling of NaN between ISA and ++ // JS semantics ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ if (std::is_same::value) { ++ CompareIsNanF32(scratch, src1, src2); ++ } else { ++ CompareIsNanF64(scratch, src1, src2); ++ } ++ BranchTrueF(scratch, &nan); ++ ++ if (kind == MaxMinKind::kMax) { ++ if (std::is_same::value) { ++ fmax_s(dst, src1, src2); ++ } else { ++ fmax_d(dst, src1, src2); ++ } ++ } else { ++ if (std::is_same::value) { ++ fmin_s(dst, src1, src2); ++ } else { ++ fmin_d(dst, src1, src2); ++ } ++ } ++ j(&done); ++ ++ bind(&nan); ++ // if any operand is NaN, return NaN (fadd returns NaN if any operand is NaN) ++ if (std::is_same::value) { ++ fadd_s(dst, src1, src2); ++ } else { ++ fadd_d(dst, src1, src2); ++ } ++ ++ bind(&done); ++} ++ ++void TurboAssembler::Float32Max(FPURegister dst, FPURegister src1, ++ FPURegister src2) { ++ FloatMinMaxHelper(dst, src1, src2, MaxMinKind::kMax); ++} ++ ++void TurboAssembler::Float32Min(FPURegister dst, FPURegister src1, ++ FPURegister src2) { ++ FloatMinMaxHelper(dst, src1, src2, MaxMinKind::kMin); ++} ++ ++void TurboAssembler::Float64Max(FPURegister dst, FPURegister src1, ++ FPURegister src2) { ++ FloatMinMaxHelper(dst, src1, src2, MaxMinKind::kMax); ++} ++ ++void TurboAssembler::Float64Min(FPURegister dst, FPURegister src1, ++ FPURegister src2) { ++ FloatMinMaxHelper(dst, src1, src2, MaxMinKind::kMin); ++} ++ ++static const int kRegisterPassedArguments = 8; ++ ++int TurboAssembler::CalculateStackPassedDWords(int num_gp_arguments, ++ int num_fp_arguments) { ++ int stack_passed_dwords = 0; ++ ++ // Up to eight integer arguments are passed in registers a0..a7 and ++ // up to eight floating point arguments are passed in registers fa0..fa7 ++ if (num_gp_arguments > kRegisterPassedArguments) { ++ stack_passed_dwords += num_gp_arguments - kRegisterPassedArguments; ++ } ++ if (num_fp_arguments > kRegisterPassedArguments) { ++ stack_passed_dwords += num_fp_arguments - kRegisterPassedArguments; ++ } ++ stack_passed_dwords += kCArgSlotCount; ++ return stack_passed_dwords; ++} ++ ++void TurboAssembler::PrepareCallCFunction(int num_reg_arguments, ++ int num_double_arguments, ++ Register scratch) { ++ int frame_alignment = ActivationFrameAlignment(); ++ ++ // Up to eight simple arguments in a0..a7, fa0..fa7. ++ // Remaining arguments are pushed on the stack (arg slot calculation handled ++ // by CalculateStackPassedDWords()). ++ int stack_passed_arguments = ++ CalculateStackPassedDWords(num_reg_arguments, num_double_arguments); ++ if (frame_alignment > kPointerSize) { ++ // Make stack end at alignment and make room for stack arguments and the ++ // original value of sp. ++ mv(scratch, sp); ++ Sub64(sp, sp, Operand((stack_passed_arguments + 1) * kPointerSize)); ++ DCHECK(base::bits::IsPowerOfTwo(frame_alignment)); ++ And(sp, sp, Operand(-frame_alignment)); ++ Sd(scratch, MemOperand(sp, stack_passed_arguments * kPointerSize)); ++ } else { ++ Sub64(sp, sp, Operand(stack_passed_arguments * kPointerSize)); ++ } ++} ++ ++void TurboAssembler::PrepareCallCFunction(int num_reg_arguments, ++ Register scratch) { ++ PrepareCallCFunction(num_reg_arguments, 0, scratch); ++} ++ ++void TurboAssembler::CallCFunction(ExternalReference function, ++ int num_reg_arguments, ++ int num_double_arguments) { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ li(t6, function); ++ CallCFunctionHelper(t6, num_reg_arguments, num_double_arguments); ++} ++ ++void TurboAssembler::CallCFunction(Register function, int num_reg_arguments, ++ int num_double_arguments) { ++ CallCFunctionHelper(function, num_reg_arguments, num_double_arguments); ++} ++ ++void TurboAssembler::CallCFunction(ExternalReference function, ++ int num_arguments) { ++ CallCFunction(function, num_arguments, 0); ++} ++ ++void TurboAssembler::CallCFunction(Register function, int num_arguments) { ++ CallCFunction(function, num_arguments, 0); ++} ++ ++void TurboAssembler::CallCFunctionHelper(Register function, ++ int num_reg_arguments, ++ int num_double_arguments) { ++ DCHECK_LE(num_reg_arguments + num_double_arguments, kMaxCParameters); ++ DCHECK(has_frame()); ++ // Make sure that the stack is aligned before calling a C function unless ++ // running in the simulator. The simulator has its own alignment check which ++ // provides more information. ++ // The argument stots are presumed to have been set up by ++ // PrepareCallCFunction. ++ ++#if V8_HOST_ARCH_RISCV64 ++ if (emit_debug_code()) { ++ int frame_alignment = base::OS::ActivationFrameAlignment(); ++ int frame_alignment_mask = frame_alignment - 1; ++ if (frame_alignment > kPointerSize) { ++ DCHECK(base::bits::IsPowerOfTwo(frame_alignment)); ++ Label alignment_as_expected; ++ { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ And(scratch, sp, Operand(frame_alignment_mask)); ++ Branch(&alignment_as_expected, eq, scratch, Operand(zero_reg)); ++ } ++ // Don't use Check here, as it will call Runtime_Abort possibly ++ // re-entering here. ++ ebreak(); ++ bind(&alignment_as_expected); ++ } ++ } ++#endif // V8_HOST_ARCH_RISCV64 ++ ++ // Just call directly. The function called cannot cause a GC, or ++ // allow preemption, so the return address in the link register ++ // stays correct. ++ { ++ BlockTrampolinePoolScope block_trampoline_pool(this); ++ if (function != t6) { ++ mv(t6, function); ++ function = t6; ++ } ++ ++ // Save the frame pointer and PC so that the stack layout remains ++ // iterable, even without an ExitFrame which normally exists between JS ++ // and C frames. ++ // 't' registers are caller-saved so this is safe as a scratch register. ++ Register pc_scratch = t1; ++ Register scratch = t2; ++ DCHECK(!AreAliased(pc_scratch, scratch, function)); ++ ++ auipc(pc_scratch, 0); ++ // FIXME(RISCV): Does this need an offset? It seems like this should be the ++ // PC of the call, but MIPS does not seem to do that. ++ ++ // See x64 code for reasoning about how to address the isolate data fields. ++ if (root_array_available()) { ++ Sd(pc_scratch, MemOperand(kRootRegister, ++ IsolateData::fast_c_call_caller_pc_offset())); ++ Sd(fp, MemOperand(kRootRegister, ++ IsolateData::fast_c_call_caller_fp_offset())); ++ } else { ++ DCHECK_NOT_NULL(isolate()); ++ li(scratch, ExternalReference::fast_c_call_caller_pc_address(isolate())); ++ Sd(pc_scratch, MemOperand(scratch)); ++ li(scratch, ExternalReference::fast_c_call_caller_fp_address(isolate())); ++ Sd(fp, MemOperand(scratch)); ++ } ++ ++ Call(function); ++ ++ if (isolate() != nullptr) { ++ // We don't unset the PC; the FP is the source of truth. ++ Register scratch = t1; ++ li(scratch, ExternalReference::fast_c_call_caller_fp_address(isolate())); ++ Sd(zero_reg, MemOperand(scratch)); ++ } ++ } ++ ++ int stack_passed_arguments = ++ CalculateStackPassedDWords(num_reg_arguments, num_double_arguments); ++ ++ if (base::OS::ActivationFrameAlignment() > kPointerSize) { ++ Ld(sp, MemOperand(sp, stack_passed_arguments * kPointerSize)); ++ } else { ++ Add64(sp, sp, Operand(stack_passed_arguments * kPointerSize)); ++ } ++} ++ ++#undef BRANCH_ARGS_CHECK ++ ++void TurboAssembler::CheckPageFlag(Register object, Register scratch, int mask, ++ Condition cc, Label* condition_met) { ++ And(scratch, object, Operand(~kPageAlignmentMask)); ++ Ld(scratch, MemOperand(scratch, BasicMemoryChunk::kFlagsOffset)); ++ And(scratch, scratch, Operand(mask)); ++ Branch(condition_met, cc, scratch, Operand(zero_reg)); ++} ++ ++Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, ++ Register reg4, Register reg5, ++ Register reg6) { ++ RegList regs = 0; ++ if (reg1.is_valid()) regs |= reg1.bit(); ++ if (reg2.is_valid()) regs |= reg2.bit(); ++ if (reg3.is_valid()) regs |= reg3.bit(); ++ if (reg4.is_valid()) regs |= reg4.bit(); ++ if (reg5.is_valid()) regs |= reg5.bit(); ++ if (reg6.is_valid()) regs |= reg6.bit(); ++ ++ const RegisterConfiguration* config = RegisterConfiguration::Default(); ++ for (int i = 0; i < config->num_allocatable_general_registers(); ++i) { ++ int code = config->GetAllocatableGeneralCode(i); ++ Register candidate = Register::from_code(code); ++ if (regs & candidate.bit()) continue; ++ return candidate; ++ } ++ UNREACHABLE(); ++} ++ ++void TurboAssembler::ComputeCodeStartAddress(Register dst) { ++ // This push on ra and the pop below together ensure that we restore the ++ // register ra, which is needed while computing the code start address. ++ push(ra); ++ ++ auipc(ra, 0); ++ addi(ra, ra, kInstrSize * 2); // ra = address of li ++ int pc = pc_offset(); ++ li(dst, Operand(pc)); ++ Sub64(dst, ra, dst); ++ ++ pop(ra); // Restore ra ++} ++ ++void TurboAssembler::ResetSpeculationPoisonRegister() { ++ li(kSpeculationPoisonRegister, -1); ++} ++ ++void TurboAssembler::CallForDeoptimization(Address target, int deopt_id, ++ Label* exit, DeoptimizeKind kind) { ++ USE(exit, kind); ++ NoRootArrayScope no_root_array(this); ++ ++ // Save the deopt id in kRootRegister (we don't need the roots array from ++ // now on). ++ DCHECK_LE(deopt_id, 0xFFFF); ++ li(kRootRegister, deopt_id); ++ Call(target, RelocInfo::RUNTIME_ENTRY); ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/macro-assembler-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/macro-assembler-riscv64.h +@@ -0,0 +1,1181 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef INCLUDED_FROM_MACRO_ASSEMBLER_H ++#error This header must be included via macro-assembler.h ++#endif ++ ++#ifndef V8_CODEGEN_RISCV_MACRO_ASSEMBLER_RISCV_H_ ++#define V8_CODEGEN_RISCV_MACRO_ASSEMBLER_RISCV_H_ ++ ++#include "src/codegen/assembler.h" ++#include "src/codegen/riscv64/assembler-riscv64.h" ++#include "src/common/globals.h" ++ ++namespace v8 { ++namespace internal { ++ ++// Forward declarations. ++enum class AbortReason : uint8_t; ++ ++// Reserved Register Usage Summary. ++// ++// Registers t5, t6, and t3 are reserved for use by the MacroAssembler. ++// ++// The programmer should know that the MacroAssembler may clobber these three, ++// but won't touch other registers except in special cases. ++// ++// FIXME(RISCV): Cannot find info about this ABI. We chose t6 for now. ++// Per the RISC-V ABI, register t6 must be used for indirect function call ++// via 'jalr t6' or 'jr t6' instructions. This is relied upon by gcc when ++// trying to update gp register for position-independent-code. Whenever ++// RISC-V generated code calls C code, it must be via t6 register. ++ ++// Flags used for LeaveExitFrame function. ++enum LeaveExitFrameMode { EMIT_RETURN = true, NO_EMIT_RETURN = false }; ++ ++// Flags used for the li macro-assembler function. ++enum LiFlags { ++ // If the constant value can be represented in just 16 bits, then ++ // optimize the li to use a single instruction, rather than lui/ori/slli ++ // sequence. A number of other optimizations that emits less than ++ // maximum number of instructions exists. ++ OPTIMIZE_SIZE = 0, ++ // Always use 8 instructions (lui/addi/slliw sequence), even if the ++ // constant ++ // could be loaded with just one, so that this value is patchable later. ++ CONSTANT_SIZE = 1, ++ // For address loads 8 instruction are required. Used to mark ++ // constant load that will be used as address without relocation ++ // information. It ensures predictable code size, so specific sites ++ // in code are patchable. ++ ADDRESS_LOAD = 2 ++}; ++ ++enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET }; ++enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK }; ++enum RAStatus { kRAHasNotBeenSaved, kRAHasBeenSaved }; ++ ++Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2 = no_reg, ++ Register reg3 = no_reg, ++ Register reg4 = no_reg, ++ Register reg5 = no_reg, ++ Register reg6 = no_reg); ++ ++// ----------------------------------------------------------------------------- ++// Static helper functions. ++ ++#if defined(V8_TARGET_LITTLE_ENDIAN) ++#define SmiWordOffset(offset) (offset + kPointerSize / 2) ++#else ++#define SmiWordOffset(offset) offset ++#endif ++ ++// Generate a MemOperand for loading a field from an object. ++inline MemOperand FieldMemOperand(Register object, int offset) { ++ return MemOperand(object, offset - kHeapObjectTag); ++} ++ ++// Generate a MemOperand for storing arguments 5..N on the stack ++// when calling CallCFunction(). ++// TODO(plind): Currently ONLY used for O32. Should be fixed for ++// n64, and used in RegExp code, and other places ++// with more than 8 arguments. ++inline MemOperand CFunctionArgumentOperand(int index) { ++ DCHECK_GT(index, kCArgSlotCount); ++ // Argument 5 takes the slot just past the four Arg-slots. ++ int offset = (index - 5) * kPointerSize + kCArgsSlotsSize; ++ return MemOperand(sp, offset); ++} ++ ++class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase { ++ public: ++ using TurboAssemblerBase::TurboAssemblerBase; ++ ++ // Activation support. ++ void EnterFrame(StackFrame::Type type); ++ void EnterFrame(StackFrame::Type type, bool load_constant_pool_pointer_reg) { ++ // Out-of-line constant pool not implemented on RISC-V. ++ UNREACHABLE(); ++ } ++ void LeaveFrame(StackFrame::Type type); ++ ++ // Generates function and stub prologue code. ++ void StubPrologue(StackFrame::Type type); ++ void Prologue(); ++ ++ void InitializeRootRegister() { ++ ExternalReference isolate_root = ExternalReference::isolate_root(isolate()); ++ li(kRootRegister, Operand(isolate_root)); ++ } ++ ++ // Jump unconditionally to given label. ++ void jmp(Label* L) { Branch(L); } ++ ++ // ------------------------------------------------------------------------- ++ // Debugging. ++ ++ void Trap() override; ++ void DebugBreak() override; ++ ++ // Calls Abort(msg) if the condition cc is not satisfied. ++ // Use --debug_code to enable. ++ void Assert(Condition cc, AbortReason reason, Register rs, Operand rt); ++ ++ // Like Assert(), but always enabled. ++ void Check(Condition cc, AbortReason reason, Register rs, Operand rt); ++ ++ // Print a message to stdout and abort execution. ++ void Abort(AbortReason msg); ++ ++ // Arguments macros. ++#define COND_TYPED_ARGS Condition cond, Register r1, const Operand &r2 ++#define COND_ARGS cond, r1, r2 ++ ++ // Cases when relocation is not needed. ++#define DECLARE_NORELOC_PROTOTYPE(Name, target_type) \ ++ void Name(target_type target); \ ++ void Name(target_type target, COND_TYPED_ARGS); ++ ++#define DECLARE_BRANCH_PROTOTYPES(Name) \ ++ DECLARE_NORELOC_PROTOTYPE(Name, Label*) \ ++ DECLARE_NORELOC_PROTOTYPE(Name, int32_t) ++ ++ DECLARE_BRANCH_PROTOTYPES(Branch) ++ DECLARE_BRANCH_PROTOTYPES(BranchAndLink) ++ DECLARE_BRANCH_PROTOTYPES(BranchShort) ++ ++#undef DECLARE_BRANCH_PROTOTYPES ++#undef COND_TYPED_ARGS ++#undef COND_ARGS ++ ++ inline void NegateBool(Register rd, Register rs) { Xor(rd, rs, 1); } ++ ++ // Compare float, if any operand is NaN, result is false except for NE ++ void CompareF32(Register rd, FPUCondition cc, FPURegister cmp1, ++ FPURegister cmp2); ++ // Compare double, if any operand is NaN, result is false except for NE ++ void CompareF64(Register rd, FPUCondition cc, FPURegister cmp1, ++ FPURegister cmp2); ++ void CompareIsNanF32(Register rd, FPURegister cmp1, FPURegister cmp2); ++ void CompareIsNanF64(Register rd, FPURegister cmp1, FPURegister cmp2); ++ ++ // Floating point branches ++ void BranchTrueShortF(Register rs, Label* target); ++ void BranchFalseShortF(Register rs, Label* target); ++ ++ void BranchTrueF(Register rs, Label* target); ++ void BranchFalseF(Register rs, Label* target); ++ ++ void Branch(Label* L, Condition cond, Register rs, RootIndex index); ++ ++ static int InstrCountForLi64Bit(int64_t value); ++ inline void LiLower32BitHelper(Register rd, Operand j); ++ void li_optimized(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE); ++ // Load int32 in the rd register. ++ void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE); ++ inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) { ++ li(rd, Operand(j), mode); ++ } ++ ++ void li(Register dst, Handle value, LiFlags mode = OPTIMIZE_SIZE); ++ void li(Register dst, ExternalReference value, LiFlags mode = OPTIMIZE_SIZE); ++ void li(Register dst, const StringConstantBase* string, ++ LiFlags mode = OPTIMIZE_SIZE); ++ ++ void LoadFromConstantsTable(Register destination, ++ int constant_index) override; ++ void LoadRootRegisterOffset(Register destination, intptr_t offset) override; ++ void LoadRootRelative(Register destination, int32_t offset) override; ++ ++// Jump, Call, and Ret pseudo instructions implementing inter-working. ++#define COND_ARGS \ ++ Condition cond = al, Register rs = zero_reg, \ ++ const Operand &rt = Operand(zero_reg) ++ ++ void Jump(Register target, COND_ARGS); ++ void Jump(intptr_t target, RelocInfo::Mode rmode, COND_ARGS); ++ void Jump(Address target, RelocInfo::Mode rmode, COND_ARGS); ++ // Deffer from li, this method save target to the memory, and then load ++ // it to register use ld, it can be used in wasm jump table for concurrent ++ // patching. ++ void PatchAndJump(Address target); ++ void Jump(Handle code, RelocInfo::Mode rmode, COND_ARGS); ++ void Jump(const ExternalReference& reference) override; ++ void Call(Register target, COND_ARGS); ++ void Call(Address target, RelocInfo::Mode rmode, COND_ARGS); ++ void Call(Handle code, RelocInfo::Mode rmode = RelocInfo::CODE_TARGET, ++ COND_ARGS); ++ void Call(Label* target); ++ void LoadAddress(Register dst, Label* target); ++ ++ // Load the builtin given by the Smi in |builtin_index| into the same ++ // register. ++ void LoadEntryFromBuiltinIndex(Register builtin_index); ++ void CallBuiltinByIndex(Register builtin_index) override; ++ ++ void LoadCodeObjectEntry(Register destination, ++ Register code_object) override { ++ // TODO(RISCV): Implement. ++ UNIMPLEMENTED(); ++ } ++ void CallCodeObject(Register code_object) override { ++ // TODO(RISCV): Implement. ++ UNIMPLEMENTED(); ++ } ++ void JumpCodeObject(Register code_object) override { ++ // TODO(RISCV): Implement. ++ UNIMPLEMENTED(); ++ } ++ ++ // Generates an instruction sequence s.t. the return address points to the ++ // instruction following the call. ++ // The return address on the stack is used by frame iteration. ++ void StoreReturnAddressAndCall(Register target); ++ ++ void CallForDeoptimization(Address target, int deopt_id, Label* exit, ++ DeoptimizeKind kind); ++ ++ void Ret(COND_ARGS); ++ ++ // Emit code to discard a non-negative number of pointer-sized elements ++ // from the stack, clobbering only the sp register. ++ void Drop(int count, Condition cond = cc_always, Register reg = no_reg, ++ const Operand& op = Operand(no_reg)); ++ ++ // Trivial case of DropAndRet that only emits 2 instructions. ++ void DropAndRet(int drop); ++ ++ void DropAndRet(int drop, Condition cond, Register reg, const Operand& op); ++ ++ void Ld(Register rd, const MemOperand& rs); ++ void Sd(Register rd, const MemOperand& rs); ++ ++ void push(Register src) { ++ Add64(sp, sp, Operand(-kPointerSize)); ++ Sd(src, MemOperand(sp, 0)); ++ } ++ void Push(Register src) { push(src); } ++ void Push(Handle handle); ++ void Push(Smi smi); ++ ++ // Push two registers. Pushes leftmost register first (to highest address). ++ void Push(Register src1, Register src2) { ++ Sub64(sp, sp, Operand(2 * kPointerSize)); ++ Sd(src1, MemOperand(sp, 1 * kPointerSize)); ++ Sd(src2, MemOperand(sp, 0 * kPointerSize)); ++ } ++ ++ // Push three registers. Pushes leftmost register first (to highest address). ++ void Push(Register src1, Register src2, Register src3) { ++ Sub64(sp, sp, Operand(3 * kPointerSize)); ++ Sd(src1, MemOperand(sp, 2 * kPointerSize)); ++ Sd(src2, MemOperand(sp, 1 * kPointerSize)); ++ Sd(src3, MemOperand(sp, 0 * kPointerSize)); ++ } ++ ++ // Push four registers. Pushes leftmost register first (to highest address). ++ void Push(Register src1, Register src2, Register src3, Register src4) { ++ Sub64(sp, sp, Operand(4 * kPointerSize)); ++ Sd(src1, MemOperand(sp, 3 * kPointerSize)); ++ Sd(src2, MemOperand(sp, 2 * kPointerSize)); ++ Sd(src3, MemOperand(sp, 1 * kPointerSize)); ++ Sd(src4, MemOperand(sp, 0 * kPointerSize)); ++ } ++ ++ // Push five registers. Pushes leftmost register first (to highest address). ++ void Push(Register src1, Register src2, Register src3, Register src4, ++ Register src5) { ++ Sub64(sp, sp, Operand(5 * kPointerSize)); ++ Sd(src1, MemOperand(sp, 4 * kPointerSize)); ++ Sd(src2, MemOperand(sp, 3 * kPointerSize)); ++ Sd(src3, MemOperand(sp, 2 * kPointerSize)); ++ Sd(src4, MemOperand(sp, 1 * kPointerSize)); ++ Sd(src5, MemOperand(sp, 0 * kPointerSize)); ++ } ++ ++ void Push(Register src, Condition cond, Register tst1, Register tst2) { ++ // Since we don't have conditional execution we use a Branch. ++ Branch(3, cond, tst1, Operand(tst2)); ++ Sub64(sp, sp, Operand(kPointerSize)); ++ Sd(src, MemOperand(sp, 0)); ++ } ++ ++ void SaveRegisters(RegList registers); ++ void RestoreRegisters(RegList registers); ++ ++ void CallRecordWriteStub(Register object, Register address, ++ RememberedSetAction remembered_set_action, ++ SaveFPRegsMode fp_mode); ++ void CallRecordWriteStub(Register object, Register address, ++ RememberedSetAction remembered_set_action, ++ SaveFPRegsMode fp_mode, Address wasm_target); ++ void CallEphemeronKeyBarrier(Register object, Register address, ++ SaveFPRegsMode fp_mode); ++ ++ // Push multiple registers on the stack. ++ // Registers are saved in numerical order, with higher numbered registers ++ // saved in higher memory addresses. ++ void MultiPush(RegList regs); ++ void MultiPushFPU(RegList regs); ++ ++ // Calculate how much stack space (in bytes) are required to store caller ++ // registers excluding those specified in the arguments. ++ int RequiredStackSizeForCallerSaved(SaveFPRegsMode fp_mode, ++ Register exclusion1 = no_reg, ++ Register exclusion2 = no_reg, ++ Register exclusion3 = no_reg) const; ++ ++ // Push caller saved registers on the stack, and return the number of bytes ++ // stack pointer is adjusted. ++ int PushCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1 = no_reg, ++ Register exclusion2 = no_reg, ++ Register exclusion3 = no_reg); ++ // Restore caller saved registers from the stack, and return the number of ++ // bytes stack pointer is adjusted. ++ int PopCallerSaved(SaveFPRegsMode fp_mode, Register exclusion1 = no_reg, ++ Register exclusion2 = no_reg, ++ Register exclusion3 = no_reg); ++ ++ void pop(Register dst) { ++ Ld(dst, MemOperand(sp, 0)); ++ Add64(sp, sp, Operand(kPointerSize)); ++ } ++ void Pop(Register dst) { pop(dst); } ++ ++ // Pop two registers. Pops rightmost register first (from lower address). ++ void Pop(Register src1, Register src2) { ++ DCHECK(src1 != src2); ++ Ld(src2, MemOperand(sp, 0 * kPointerSize)); ++ Ld(src1, MemOperand(sp, 1 * kPointerSize)); ++ Add64(sp, sp, 2 * kPointerSize); ++ } ++ ++ // Pop three registers. Pops rightmost register first (from lower address). ++ void Pop(Register src1, Register src2, Register src3) { ++ Ld(src3, MemOperand(sp, 0 * kPointerSize)); ++ Ld(src2, MemOperand(sp, 1 * kPointerSize)); ++ Ld(src1, MemOperand(sp, 2 * kPointerSize)); ++ Add64(sp, sp, 3 * kPointerSize); ++ } ++ ++ void Pop(uint32_t count = 1) { Add64(sp, sp, Operand(count * kPointerSize)); } ++ ++ // Pops multiple values from the stack and load them in the ++ // registers specified in regs. Pop order is the opposite as in MultiPush. ++ void MultiPop(RegList regs); ++ void MultiPopFPU(RegList regs); ++ ++#define DEFINE_INSTRUCTION(instr) \ ++ void instr(Register rd, Register rs, const Operand& rt); \ ++ void instr(Register rd, Register rs, Register rt) { \ ++ instr(rd, rs, Operand(rt)); \ ++ } \ ++ void instr(Register rs, Register rt, int32_t j) { instr(rs, rt, Operand(j)); } ++ ++#define DEFINE_INSTRUCTION2(instr) \ ++ void instr(Register rs, const Operand& rt); \ ++ void instr(Register rs, Register rt) { instr(rs, Operand(rt)); } \ ++ void instr(Register rs, int32_t j) { instr(rs, Operand(j)); } ++ ++ DEFINE_INSTRUCTION(Add32) ++ DEFINE_INSTRUCTION(Add64) ++ DEFINE_INSTRUCTION(Div32) ++ DEFINE_INSTRUCTION(Divu32) ++ DEFINE_INSTRUCTION(Divu64) ++ DEFINE_INSTRUCTION(Mod32) ++ DEFINE_INSTRUCTION(Modu32) ++ DEFINE_INSTRUCTION(Div64) ++ DEFINE_INSTRUCTION(Sub32) ++ DEFINE_INSTRUCTION(Sub64) ++ DEFINE_INSTRUCTION(Mod64) ++ DEFINE_INSTRUCTION(Modu64) ++ DEFINE_INSTRUCTION(Mul32) ++ DEFINE_INSTRUCTION(Mulh32) ++ DEFINE_INSTRUCTION(Mul64) ++ DEFINE_INSTRUCTION(Mulh64) ++ DEFINE_INSTRUCTION2(Div32) ++ DEFINE_INSTRUCTION2(Div64) ++ DEFINE_INSTRUCTION2(Divu32) ++ DEFINE_INSTRUCTION2(Divu64) ++ ++ DEFINE_INSTRUCTION(And) ++ DEFINE_INSTRUCTION(Or) ++ DEFINE_INSTRUCTION(Xor) ++ DEFINE_INSTRUCTION(Nor) ++ DEFINE_INSTRUCTION2(Neg) ++ ++ DEFINE_INSTRUCTION(Slt) ++ DEFINE_INSTRUCTION(Sltu) ++ DEFINE_INSTRUCTION(Sle) ++ DEFINE_INSTRUCTION(Sleu) ++ DEFINE_INSTRUCTION(Sgt) ++ DEFINE_INSTRUCTION(Sgtu) ++ DEFINE_INSTRUCTION(Sge) ++ DEFINE_INSTRUCTION(Sgeu) ++ DEFINE_INSTRUCTION(Seq) ++ DEFINE_INSTRUCTION(Sne) ++ ++ DEFINE_INSTRUCTION(Sll64) ++ DEFINE_INSTRUCTION(Sra64) ++ DEFINE_INSTRUCTION(Srl64) ++ DEFINE_INSTRUCTION(Sll32) ++ DEFINE_INSTRUCTION(Sra32) ++ DEFINE_INSTRUCTION(Srl32) ++ ++ DEFINE_INSTRUCTION2(Seqz) ++ DEFINE_INSTRUCTION2(Snez) ++ ++ DEFINE_INSTRUCTION(Ror) ++ DEFINE_INSTRUCTION(Dror) ++#undef DEFINE_INSTRUCTION ++#undef DEFINE_INSTRUCTION2 ++#undef DEFINE_INSTRUCTION3 ++ ++ void SmiUntag(Register dst, const MemOperand& src); ++ void SmiUntag(Register dst, Register src) { ++ if (SmiValuesAre32Bits()) { ++ srai(dst, src, kSmiShift); ++ } else { ++ DCHECK(SmiValuesAre31Bits()); ++ sraiw(dst, src, kSmiShift); ++ } ++ } ++ ++ void SmiUntag(Register reg) { SmiUntag(reg, reg); } ++ ++ // Removes current frame and its arguments from the stack preserving ++ // the arguments and a return address pushed to the stack for the next call. ++ // Both |callee_args_count| and |caller_args_count| do not include ++ // receiver. |callee_args_count| is not modified. |caller_args_count| ++ // is trashed. ++ void PrepareForTailCall(Register callee_args_count, ++ Register caller_args_count, Register scratch0, ++ Register scratch1); ++ ++ int CalculateStackPassedDWords(int num_gp_arguments, int num_fp_arguments); ++ ++ // Before calling a C-function from generated code, align arguments on stack. ++ // After aligning the frame, non-register arguments must be stored on the ++ // stack, using helper: CFunctionArgumentOperand(). ++ // The argument count assumes all arguments are word sized. ++ // Some compilers/platforms require the stack to be aligned when calling ++ // C++ code. ++ // Needs a scratch register to do some arithmetic. This register will be ++ // trashed. ++ void PrepareCallCFunction(int num_reg_arguments, int num_double_registers, ++ Register scratch); ++ void PrepareCallCFunction(int num_reg_arguments, Register scratch); ++ ++ // Arguments 1-8 are placed in registers a0 through a7 respectively. ++ // Arguments 9..n are stored to stack ++ ++ // Calls a C function and cleans up the space for arguments allocated ++ // by PrepareCallCFunction. The called function is not allowed to trigger a ++ // garbage collection, since that might move the code and invalidate the ++ // return address (unless this is somehow accounted for by the called ++ // function). ++ void CallCFunction(ExternalReference function, int num_arguments); ++ void CallCFunction(Register function, int num_arguments); ++ void CallCFunction(ExternalReference function, int num_reg_arguments, ++ int num_double_arguments); ++ void CallCFunction(Register function, int num_reg_arguments, ++ int num_double_arguments); ++ void MovFromFloatResult(DoubleRegister dst); ++ void MovFromFloatParameter(DoubleRegister dst); ++ ++ // These functions abstract parameter passing for the three different ways ++ // we call C functions from generated code. ++ void MovToFloatParameter(DoubleRegister src); ++ void MovToFloatParameters(DoubleRegister src1, DoubleRegister src2); ++ void MovToFloatResult(DoubleRegister src); ++ ++ // See comments at the beginning of Builtins::Generate_CEntry. ++ inline void PrepareCEntryArgs(int num_args) { li(a0, num_args); } ++ inline void PrepareCEntryFunction(const ExternalReference& ref) { ++ li(a1, ref); ++ } ++ ++ void CheckPageFlag(Register object, Register scratch, int mask, Condition cc, ++ Label* condition_met); ++#undef COND_ARGS ++ ++ // Performs a truncating conversion of a floating point number as used by ++ // the JS bitwise operations. See ECMA-262 9.5: ToInt32. ++ // Exits with 'result' holding the answer. ++ void TruncateDoubleToI(Isolate* isolate, Zone* zone, Register result, ++ DoubleRegister double_input, StubCallMode stub_mode); ++ ++ void CompareI(Register rd, Register rs, const Operand& rt, Condition cond); ++ ++ void LoadZeroIfConditionNotZero(Register dest, Register condition); ++ void LoadZeroIfConditionZero(Register dest, Register condition); ++ ++ void SignExtendByte(Register rd, Register rs) { ++ slli(rd, rs, 64 - 8); ++ srai(rd, rd, 64 - 8); ++ } ++ ++ void SignExtendShort(Register rd, Register rs) { ++ slli(rd, rs, 64 - 16); ++ srai(rd, rd, 64 - 16); ++ } ++ ++ void SignExtendWord(Register rd, Register rs) { sext_w(rd, rs); } ++ void ZeroExtendWord(Register rd, Register rs) { ++ slli(rd, rs, 32); ++ srli(rd, rd, 32); ++ } ++ ++ void Clz32(Register rd, Register rs); ++ void Clz64(Register rd, Register rs); ++ void Ctz32(Register rd, Register rs); ++ void Ctz64(Register rd, Register rs); ++ void Popcnt32(Register rd, Register rs); ++ void Popcnt64(Register rd, Register rs); ++ ++ // Bit field starts at bit pos and extending for size bits is extracted from ++ // rs and stored zero/sign-extended and right-justified in rt ++ void ExtractBits(Register rt, Register rs, uint16_t pos, uint16_t size, ++ bool sign_extend = false); ++ void ExtractBits(Register dest, Register source, Register pos, int size, ++ bool sign_extend = false) { ++ sra(dest, source, pos); ++ ExtractBits(dest, dest, 0, size, sign_extend); ++ } ++ ++ // Insert bits [0, size) of source to bits [pos, pos+size) of dest ++ void InsertBits(Register dest, Register source, Register pos, int size); ++ ++ void Neg_s(FPURegister fd, FPURegister fs); ++ void Neg_d(FPURegister fd, FPURegister fs); ++ ++ // Change endianness ++ void ByteSwap(Register dest, Register src, int operand_size); ++ ++ // Convert single to unsigned word. ++ void Trunc_uw_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // helper functions for unaligned load/store ++ template ++ void UnalignedLoadHelper(Register rd, const MemOperand& rs); ++ template ++ void UnalignedStoreHelper(Register rd, const MemOperand& rs, ++ Register scratch_other = no_reg); ++ ++ template ++ void UnalignedFLoadHelper(FPURegister frd, const MemOperand& rs, ++ Register scratch); ++ template ++ void UnalignedFStoreHelper(FPURegister frd, const MemOperand& rs, ++ Register scratch); ++ ++ template ++ void AlignedLoadHelper(Reg_T target, const MemOperand& rs, Func generator); ++ template ++ void AlignedStoreHelper(Reg_T value, const MemOperand& rs, Func generator); ++ ++ template ++ void LoadNBytes(Register rd, const MemOperand& rs, Register scratch); ++ template ++ void LoadNBytesOverwritingBaseReg(const MemOperand& rs, Register scratch0, ++ Register scratch1); ++ // load/store macros ++ void Ulh(Register rd, const MemOperand& rs); ++ void Ulhu(Register rd, const MemOperand& rs); ++ void Ush(Register rd, const MemOperand& rs); ++ ++ void Ulw(Register rd, const MemOperand& rs); ++ void Ulwu(Register rd, const MemOperand& rs); ++ void Usw(Register rd, const MemOperand& rs); ++ ++ void Uld(Register rd, const MemOperand& rs); ++ void Usd(Register rd, const MemOperand& rs); ++ ++ void ULoadFloat(FPURegister fd, const MemOperand& rs, Register scratch); ++ void UStoreFloat(FPURegister fd, const MemOperand& rs, Register scratch); ++ ++ void ULoadDouble(FPURegister fd, const MemOperand& rs, Register scratch); ++ void UStoreDouble(FPURegister fd, const MemOperand& rs, Register scratch); ++ ++ void Lb(Register rd, const MemOperand& rs); ++ void Lbu(Register rd, const MemOperand& rs); ++ void Sb(Register rd, const MemOperand& rs); ++ ++ void Lh(Register rd, const MemOperand& rs); ++ void Lhu(Register rd, const MemOperand& rs); ++ void Sh(Register rd, const MemOperand& rs); ++ ++ void Lw(Register rd, const MemOperand& rs); ++ void Lwu(Register rd, const MemOperand& rs); ++ void Sw(Register rd, const MemOperand& rs); ++ ++ void LoadFloat(FPURegister fd, const MemOperand& src); ++ void StoreFloat(FPURegister fs, const MemOperand& dst); ++ ++ void LoadDouble(FPURegister fd, const MemOperand& src); ++ void StoreDouble(FPURegister fs, const MemOperand& dst); ++ ++ void Ll(Register rd, const MemOperand& rs); ++ void Sc(Register rd, const MemOperand& rs); ++ ++ void Lld(Register rd, const MemOperand& rs); ++ void Scd(Register rd, const MemOperand& rs); ++ ++ void Float32Max(FPURegister dst, FPURegister src1, FPURegister src2); ++ void Float32Min(FPURegister dst, FPURegister src1, FPURegister src2); ++ void Float64Max(FPURegister dst, FPURegister src1, FPURegister src2); ++ void Float64Min(FPURegister dst, FPURegister src1, FPURegister src2); ++ template ++ void FloatMinMaxHelper(FPURegister dst, FPURegister src1, FPURegister src2, ++ MaxMinKind kind); ++ ++ bool IsDoubleZeroRegSet() { return has_double_zero_reg_set_; } ++ bool IsSingleZeroRegSet() { return has_single_zero_reg_set_; } ++ ++ inline void Move(Register dst, Smi smi) { li(dst, Operand(smi)); } ++ ++ inline void Move(Register dst, Register src) { ++ if (dst != src) { ++ mv(dst, src); ++ } ++ } ++ ++ inline void Move(FPURegister dst, FPURegister src) { ++ if (dst != src) fmv_d(dst, src); ++ } ++ ++ inline void Move(Register dst_low, Register dst_high, FPURegister src) { ++ fmv_x_d(dst_high, src); ++ fmv_x_w(dst_low, src); ++ srli(dst_high, dst_high, 32); ++ } ++ ++ inline void Move(Register dst, FPURegister src) { fmv_x_d(dst, src); } ++ ++ inline void Move(FPURegister dst, Register src) { fmv_d_x(dst, src); } ++ ++ // Extract sign-extended word from high-half of FPR to GPR ++ inline void ExtractHighWordFromF64(Register dst_high, FPURegister src) { ++ fmv_x_d(dst_high, src); ++ srai(dst_high, dst_high, 32); ++ } ++ ++ // Insert low-word from GPR (src_high) to the high-half of FPR (dst) ++ void InsertHighWordF64(FPURegister dst, Register src_high); ++ ++ // Extract sign-extended word from low-half of FPR to GPR ++ inline void ExtractLowWordFromF64(Register dst_low, FPURegister src) { ++ fmv_x_w(dst_low, src); ++ } ++ ++ // Insert low-word from GPR (src_high) to the low-half of FPR (dst) ++ void InsertLowWordF64(FPURegister dst, Register src_low); ++ ++ void LoadFPRImmediate(FPURegister dst, float imm) { ++ LoadFPRImmediate(dst, bit_cast(imm)); ++ } ++ void LoadFPRImmediate(FPURegister dst, double imm) { ++ LoadFPRImmediate(dst, bit_cast(imm)); ++ } ++ void LoadFPRImmediate(FPURegister dst, uint32_t src); ++ void LoadFPRImmediate(FPURegister dst, uint64_t src); ++ ++ // AddOverflow64 sets overflow register to a negative value if ++ // overflow occured, otherwise it is zero or positive ++ void AddOverflow64(Register dst, Register left, const Operand& right, ++ Register overflow); ++ // SubOverflow64 sets overflow register to a negative value if ++ // overflow occured, otherwise it is zero or positive ++ void SubOverflow64(Register dst, Register left, const Operand& right, ++ Register overflow); ++ // MulOverflow32 sets overflow register to zero if no overflow occured ++ void MulOverflow32(Register dst, Register left, const Operand& right, ++ Register overflow); ++ ++ // MIPS-style 32-bit unsigned mulh ++ void Mulhu32(Register dst, Register left, const Operand& right, ++ Register left_zero, Register right_zero); ++ ++ // Number of instructions needed for calculation of switch table entry address ++ static const int kSwitchTablePrologueSize = 6; ++ ++ // GetLabelFunction must be lambda '[](size_t index) -> Label*' or a ++ // functor/function with 'Label *func(size_t index)' declaration. ++ template ++ void GenerateSwitchTable(Register index, size_t case_count, ++ Func GetLabelFunction); ++ ++ // Load an object from the root table. ++ void LoadRoot(Register destination, RootIndex index) override; ++ void LoadRoot(Register destination, RootIndex index, Condition cond, ++ Register src1, const Operand& src2); ++ ++ // If the value is a NaN, canonicalize the value else, do nothing. ++ void FPUCanonicalizeNaN(const DoubleRegister dst, const DoubleRegister src); ++ ++ // --------------------------------------------------------------------------- ++ // FPU macros. These do not handle special cases like NaN or +- inf. ++ ++ // Convert unsigned word to double. ++ void Cvt_d_uw(FPURegister fd, Register rs); ++ ++ // convert signed word to double. ++ void Cvt_d_w(FPURegister fd, Register rs); ++ ++ // Convert unsigned long to double. ++ void Cvt_d_ul(FPURegister fd, Register rs); ++ ++ // Convert unsigned word to float. ++ void Cvt_s_uw(FPURegister fd, Register rs); ++ ++ // convert signed word to float. ++ void Cvt_s_w(FPURegister fd, Register rs); ++ ++ // Convert unsigned long to float. ++ void Cvt_s_ul(FPURegister fd, Register rs); ++ ++ // Convert double to unsigned word. ++ void Trunc_uw_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert double to signed word. ++ void Trunc_w_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert single to signed word. ++ void Trunc_w_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert double to unsigned long. ++ void Trunc_ul_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert singled to signed long. ++ void Trunc_l_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert single to unsigned long. ++ void Trunc_ul_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Convert singled to signed long. ++ void Trunc_l_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Round single to signed word. ++ void Round_w_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Round double to signed word. ++ void Round_w_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Ceil single to signed word. ++ void Ceil_w_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Ceil double to signed word. ++ void Ceil_w_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Floor single to signed word. ++ void Floor_w_s(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Floor double to signed word. ++ void Floor_w_d(Register rd, FPURegister fs, Register result = no_reg); ++ ++ // Round double functions ++ void Trunc_d_d(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Round_d_d(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Floor_d_d(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Ceil_d_d(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ ++ // Round float functions ++ void Trunc_s_s(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Round_s_s(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Floor_s_s(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ void Ceil_s_s(FPURegister fd, FPURegister fs, FPURegister fpu_scratch); ++ ++ // Jump the register contains a smi. ++ void JumpIfSmi(Register value, Label* smi_label, Register scratch = t3); ++ ++ void JumpIfEqual(Register a, int32_t b, Label* dest) { ++ Branch(dest, eq, a, Operand(b)); ++ } ++ ++ void JumpIfLessThan(Register a, int32_t b, Label* dest) { ++ Branch(dest, lt, a, Operand(b)); ++ } ++ ++ // Push a standard frame, consisting of ra, fp, context and JS function. ++ void PushStandardFrame(Register function_reg); ++ ++ // Get the actual activation frame alignment for target environment. ++ static int ActivationFrameAlignment(); ++ ++ // Calculated scaled address (rd) as rt + rs << sa ++ void CalcScaledAddress(Register rd, Register rs, Register rt, uint8_t sa, ++ Register scratch = t3); ++ ++ // Compute the start of the generated instruction stream from the current PC. ++ // This is an alternative to embedding the {CodeObject} handle as a reference. ++ void ComputeCodeStartAddress(Register dst); ++ ++ void ResetSpeculationPoisonRegister(); ++ ++ // Control-flow integrity: ++ ++ // Define a function entrypoint. This doesn't emit any code for this ++ // architecture, as control-flow integrity is not supported for it. ++ void CodeEntry() {} ++ // Define an exception handler. ++ void ExceptionHandler() {} ++ // Define an exception handler and bind a label. ++ void BindExceptionHandler(Label* label) { bind(label); } ++ ++ protected: ++ inline Register GetRtAsRegisterHelper(const Operand& rt, Register scratch); ++ inline int32_t GetOffset(int32_t offset, Label* L, OffsetSize bits); ++ ++ private: ++ bool has_double_zero_reg_set_ = false; ++ bool has_single_zero_reg_set_ = false; ++ ++ // Performs a truncating conversion of a floating point number as used by ++ // the JS bitwise operations. See ECMA-262 9.5: ToInt32. Goes to 'done' if it ++ // succeeds, otherwise falls through if result is saturated. On return ++ // 'result' either holds answer, or is clobbered on fall through. ++ void TryInlineTruncateDoubleToI(Register result, DoubleRegister input, ++ Label* done); ++ ++ void CallCFunctionHelper(Register function, int num_reg_arguments, ++ int num_double_arguments); ++ ++ // TODO(RISCV) Reorder parameters so out parameters come last. ++ bool CalculateOffset(Label* L, int32_t* offset, OffsetSize bits); ++ bool CalculateOffset(Label* L, int32_t* offset, OffsetSize bits, ++ Register* scratch, const Operand& rt); ++ ++ void BranchShortHelper(int32_t offset, Label* L); ++ bool BranchShortHelper(int32_t offset, Label* L, Condition cond, Register rs, ++ const Operand& rt); ++ bool BranchShortCheck(int32_t offset, Label* L, Condition cond, Register rs, ++ const Operand& rt); ++ ++ void BranchAndLinkShortHelper(int32_t offset, Label* L); ++ void BranchAndLinkShort(int32_t offset); ++ void BranchAndLinkShort(Label* L); ++ bool BranchAndLinkShortHelper(int32_t offset, Label* L, Condition cond, ++ Register rs, const Operand& rt); ++ bool BranchAndLinkShortCheck(int32_t offset, Label* L, Condition cond, ++ Register rs, const Operand& rt); ++ void BranchLong(Label* L); ++ void BranchAndLinkLong(Label* L); ++ ++ template ++ void RoundHelper(FPURegister dst, FPURegister src, FPURegister fpu_scratch, ++ RoundingMode mode); ++ ++ template ++ void RoundFloatingPointToInteger(Register rd, FPURegister fs, Register result, ++ TruncFunc trunc); ++ ++ // Push a fixed frame, consisting of ra, fp. ++ void PushCommonFrame(Register marker_reg = no_reg); ++ ++ void CallRecordWriteStub(Register object, Register address, ++ RememberedSetAction remembered_set_action, ++ SaveFPRegsMode fp_mode, Handle code_target, ++ Address wasm_target); ++}; ++ ++// MacroAssembler implements a collection of frequently used macros. ++class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler { ++ public: ++ using TurboAssembler::TurboAssembler; ++ ++ bool IsNear(Label* L, Condition cond, int rs_reg); ++ ++ // Swap two registers. If the scratch register is omitted then a slightly ++ // less efficient form using xor instead of mov is emitted. ++ void Swap(Register reg1, Register reg2, Register scratch = no_reg); ++ ++ void PushRoot(RootIndex index) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ LoadRoot(scratch, index); ++ Push(scratch); ++ } ++ ++ // Compare the object in a register to a value and jump if they are equal. ++ void JumpIfRoot(Register with, RootIndex index, Label* if_equal) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ LoadRoot(scratch, index); ++ Branch(if_equal, eq, with, Operand(scratch)); ++ } ++ ++ // Compare the object in a register to a value and jump if they are not equal. ++ void JumpIfNotRoot(Register with, RootIndex index, Label* if_not_equal) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ LoadRoot(scratch, index); ++ Branch(if_not_equal, ne, with, Operand(scratch)); ++ } ++ ++ // Checks if value is in range [lower_limit, higher_limit] using a single ++ // comparison. ++ void JumpIfIsInRange(Register value, unsigned lower_limit, ++ unsigned higher_limit, Label* on_in_range); ++ ++ // --------------------------------------------------------------------------- ++ // GC Support ++ ++ // Notify the garbage collector that we wrote a pointer into an object. ++ // |object| is the object being stored into, |value| is the object being ++ // stored. value and scratch registers are clobbered by the operation. ++ // The offset is the offset from the start of the object, not the offset from ++ // the tagged HeapObject pointer. For use with FieldOperand(reg, off). ++ void RecordWriteField( ++ Register object, int offset, Register value, Register scratch, ++ RAStatus ra_status, SaveFPRegsMode save_fp, ++ RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET, ++ SmiCheck smi_check = INLINE_SMI_CHECK); ++ ++ // For a given |object| notify the garbage collector that the slot |address| ++ // has been written. |value| is the object being stored. The value and ++ // address registers are clobbered by the operation. ++ void RecordWrite( ++ Register object, Register address, Register value, RAStatus ra_status, ++ SaveFPRegsMode save_fp, ++ RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET, ++ SmiCheck smi_check = INLINE_SMI_CHECK); ++ ++ // void Pref(int32_t hint, const MemOperand& rs); ++ ++ // --------------------------------------------------------------------------- ++ // Pseudo-instructions. ++ ++ void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = t3); ++ void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = t3); ++ ++ void Madd_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); ++ void Madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); ++ void Msub_s(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); ++ void Msub_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft); ++ ++ // Enter exit frame. ++ // argc - argument count to be dropped by LeaveExitFrame. ++ // save_doubles - saves FPU registers on stack, currently disabled. ++ // stack_space - extra stack space. ++ void EnterExitFrame(bool save_doubles, int stack_space = 0, ++ StackFrame::Type frame_type = StackFrame::EXIT); ++ ++ // Leave the current exit frame. ++ void LeaveExitFrame(bool save_doubles, Register arg_count, ++ bool do_return = NO_EMIT_RETURN, ++ bool argument_count_is_length = false); ++ ++ void LoadMap(Register destination, Register object); ++ ++ // Make sure the stack is aligned. Only emits code in debug mode. ++ void AssertStackIsAligned(); ++ ++ // Load the global proxy from the current context. ++ void LoadGlobalProxy(Register dst) { ++ LoadNativeContextSlot(Context::GLOBAL_PROXY_INDEX, dst); ++ } ++ ++ void LoadNativeContextSlot(int index, Register dst); ++ ++ // Load the initial map from the global function. The registers ++ // function and map can be the same, function is then overwritten. ++ void LoadGlobalFunctionInitialMap(Register function, Register map, ++ Register scratch); ++ ++ // ------------------------------------------------------------------------- ++ // JavaScript invokes. ++ ++ // Invoke the JavaScript function code by either calling or jumping. ++ void InvokeFunctionCode(Register function, Register new_target, ++ Register expected_parameter_count, ++ Register actual_parameter_count, InvokeFlag flag); ++ ++ // On function call, call into the debugger if necessary. ++ void CheckDebugHook(Register fun, Register new_target, ++ Register expected_parameter_count, ++ Register actual_parameter_count); ++ ++ // Invoke the JavaScript function in the given register. Changes the ++ // current context to the context in the function before invoking. ++ void InvokeFunctionWithNewTarget(Register function, Register new_target, ++ Register actual_parameter_count, ++ InvokeFlag flag); ++ void InvokeFunction(Register function, Register expected_parameter_count, ++ Register actual_parameter_count, InvokeFlag flag); ++ ++ // Frame restart support. ++ void MaybeDropFrames(); ++ ++ // Exception handling. ++ ++ // Push a new stack handler and link into stack handler chain. ++ void PushStackHandler(); ++ ++ // Unlink the stack handler on top of the stack from the stack handler chain. ++ // Must preserve the result register. ++ void PopStackHandler(); ++ ++ // ------------------------------------------------------------------------- ++ // Support functions. ++ ++ void GetObjectType(Register function, Register map, Register type_reg); ++ ++ // ------------------------------------------------------------------------- ++ // Runtime calls. ++ ++ // Call a runtime routine. ++ void CallRuntime(const Runtime::Function* f, int num_arguments, ++ SaveFPRegsMode save_doubles = kDontSaveFPRegs); ++ ++ // Convenience function: Same as above, but takes the fid instead. ++ void CallRuntime(Runtime::FunctionId fid, ++ SaveFPRegsMode save_doubles = kDontSaveFPRegs) { ++ const Runtime::Function* function = Runtime::FunctionForId(fid); ++ CallRuntime(function, function->nargs, save_doubles); ++ } ++ ++ // Convenience function: Same as above, but takes the fid instead. ++ void CallRuntime(Runtime::FunctionId fid, int num_arguments, ++ SaveFPRegsMode save_doubles = kDontSaveFPRegs) { ++ CallRuntime(Runtime::FunctionForId(fid), num_arguments, save_doubles); ++ } ++ ++ // Convenience function: tail call a runtime routine (jump). ++ void TailCallRuntime(Runtime::FunctionId fid); ++ ++ // Jump to the builtin routine. ++ void JumpToExternalReference(const ExternalReference& builtin, ++ bool builtin_exit_frame = false); ++ ++ // Generates a trampoline to jump to the off-heap instruction stream. ++ void JumpToInstructionStream(Address entry); ++ ++ // --------------------------------------------------------------------------- ++ // In-place weak references. ++ void LoadWeakValue(Register out, Register in, Label* target_if_cleared); ++ ++ // ------------------------------------------------------------------------- ++ // StatsCounter support. ++ ++ void IncrementCounter(StatsCounter* counter, int value, Register scratch1, ++ Register scratch2); ++ void DecrementCounter(StatsCounter* counter, int value, Register scratch1, ++ Register scratch2); ++ ++ // ------------------------------------------------------------------------- ++ // Smi utilities. ++ ++ void SmiTag(Register dst, Register src) { ++ STATIC_ASSERT(kSmiTag == 0); ++ if (SmiValuesAre32Bits()) { ++ // FIXME(RISCV): do not understand the logic here ++ slli(dst, src, 32); ++ } else { ++ DCHECK(SmiValuesAre31Bits()); ++ Add32(dst, src, src); ++ } ++ } ++ ++ void SmiTag(Register reg) { SmiTag(reg, reg); } ++ ++ // Left-shifted from int32 equivalent of Smi. ++ void SmiScale(Register dst, Register src, int scale) { ++ if (SmiValuesAre32Bits()) { ++ // The int portion is upper 32-bits of 64-bit word. ++ srai(dst, src, (kSmiShift - scale) & 0x3F); ++ } else { ++ DCHECK(SmiValuesAre31Bits()); ++ DCHECK_GE(scale, kSmiTagSize); ++ slliw(dst, src, scale - kSmiTagSize); ++ } ++ } ++ ++ // Test if the register contains a smi. ++ inline void SmiTst(Register value, Register scratch) { ++ And(scratch, value, Operand(kSmiTagMask)); ++ } ++ ++ // Jump if the register contains a non-smi. ++ void JumpIfNotSmi(Register value, Label* not_smi_label, ++ Register scratch = t3); ++ ++ // Abort execution if argument is a smi, enabled via --debug-code. ++ void AssertNotSmi(Register object); ++ void AssertSmi(Register object); ++ ++ // Abort execution if argument is not a Constructor, enabled via --debug-code. ++ void AssertConstructor(Register object); ++ ++ // Abort execution if argument is not a JSFunction, enabled via --debug-code. ++ void AssertFunction(Register object); ++ ++ // Abort execution if argument is not a JSBoundFunction, ++ // enabled via --debug-code. ++ void AssertBoundFunction(Register object); ++ ++ // Abort execution if argument is not a JSGeneratorObject (or subclass), ++ // enabled via --debug-code. ++ void AssertGeneratorObject(Register object); ++ ++ // Abort execution if argument is not undefined or an AllocationSite, enabled ++ // via --debug-code. ++ void AssertUndefinedOrAllocationSite(Register object, Register scratch); ++ ++ template ++ void DecodeField(Register dst, Register src) { ++ ExtractBits(dst, src, Field::kShift, Field::kSize); ++ } ++ ++ template ++ void DecodeField(Register reg) { ++ DecodeField(reg, reg); ++ } ++ ++ private: ++ // Helper functions for generating invokes. ++ void InvokePrologue(Register expected_parameter_count, ++ Register actual_parameter_count, Label* done, ++ InvokeFlag flag); ++ ++ // Compute memory operands for safepoint stack slots. ++ static int SafepointRegisterStackIndex(int reg_code); ++ ++ // Needs access to SafepointRegisterStackIndex for compiled frame ++ // traversal. ++ friend class StandardFrame; ++ ++ DISALLOW_IMPLICIT_CONSTRUCTORS(MacroAssembler); ++}; ++ ++template ++void TurboAssembler::GenerateSwitchTable(Register index, size_t case_count, ++ Func GetLabelFunction) { ++ // Ensure that dd-ed labels following this instruction use 8 bytes aligned ++ // addresses. ++ BlockTrampolinePoolFor(static_cast(case_count) * 2 + ++ kSwitchTablePrologueSize); ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ ++ Align(8); ++ // Load the address from the jump table at index and jump to it ++ auipc(scratch, 0); // Load the current PC into scratch ++ slli(t5, index, kPointerSizeLog2); // t5 = offset of indexth entry ++ add(t5, t5, scratch); // t5 = (saved PC) + (offset of indexth entry) ++ ld(t5, t5, 6 * kInstrSize); // Add the size of these 6 instructions to the ++ // offset, then load ++ jr(t5); // Jump to the address loaded from the table ++ nop(); // For 16-byte alignment ++ for (size_t index = 0; index < case_count; ++index) { ++ dd(GetLabelFunction(index)); ++ } ++} ++ ++#define ACCESS_MASM(masm) masm-> ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_CODEGEN_RISCV_MACRO_ASSEMBLER_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/register-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/codegen/riscv64/register-riscv64.h +@@ -0,0 +1,345 @@ ++// Copyright 2018 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_CODEGEN_RISCV_REGISTER_RISCV_H_ ++#define V8_CODEGEN_RISCV_REGISTER_RISCV_H_ ++ ++#include "src/codegen/register.h" ++#include "src/codegen/reglist.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++ ++namespace v8 { ++namespace internal { ++ ++// clang-format off ++#define GENERAL_REGISTERS(V) \ ++ V(zero_reg) V(ra) V(sp) V(gp) V(tp) V(t0) V(t1) V(t2) \ ++ V(fp) V(s1) V(a0) V(a1) V(a2) V(a3) V(a4) V(a5) \ ++ V(a6) V(a7) V(s2) V(s3) V(s4) V(s5) V(s6) V(s7) V(s8) V(s9) \ ++ V(s10) V(s11) V(t3) V(t4) V(t5) V(t6) ++ ++#define ALLOCATABLE_GENERAL_REGISTERS(V) \ ++ V(a0) V(a1) V(a2) V(a3) \ ++ V(a4) V(a5) V(a6) V(a7) V(t0) V(t1) V(t2) V(s7) V(t4) ++ ++#define DOUBLE_REGISTERS(V) \ ++ V(ft0) V(ft1) V(ft2) V(ft3) V(ft4) V(ft5) V(ft6) V(ft7) \ ++ V(fs0) V(fs1) V(fa0) V(fa1) V(fa2) V(fa3) V(fa4) V(fa5) \ ++ V(fa6) V(fa7) V(fs2) V(fs3) V(fs4) V(fs5) V(fs6) V(fs7) \ ++ V(fs8) V(fs9) V(fs10) V(fs11) V(ft8) V(ft9) V(ft10) V(ft11) ++ ++#define FLOAT_REGISTERS DOUBLE_REGISTERS ++#define SIMD128_REGISTERS(V) \ ++ V(w0) V(w1) V(w2) V(w3) V(w4) V(w5) V(w6) V(w7) \ ++ V(w8) V(w9) V(w10) V(w11) V(w12) V(w13) V(w14) V(w15) \ ++ V(w16) V(w17) V(w18) V(w19) V(w20) V(w21) V(w22) V(w23) \ ++ V(w24) V(w25) V(w26) V(w27) V(w28) V(w29) V(w30) V(w31) ++ ++#define ALLOCATABLE_DOUBLE_REGISTERS(V) \ ++ V(ft0) V(ft1) V(ft2) V(ft3) \ ++ V(ft4) V(ft5) V(ft6) V(ft7) V(fa0) V(fa1) V(fa2) V(fa3) V(fa4) V(fa5) \ ++ V(fa6) V(fa7) ++ ++// clang-format on ++ ++// Note that the bit values must match those used in actual instruction ++// encoding. ++const int kNumRegs = 32; ++ ++const RegList kJSCallerSaved = 1 << 5 | // t0 ++ 1 << 6 | // t1 ++ 1 << 7 | // t2 ++ 1 << 10 | // a0 ++ 1 << 11 | // a1 ++ 1 << 12 | // a2 ++ 1 << 13 | // a3 ++ 1 << 14 | // a4 ++ 1 << 15 | // a5 ++ 1 << 16 | // a6 ++ 1 << 17 | // a7 ++ 1 << 29; // t4 ++ ++const int kNumJSCallerSaved = 12; ++ ++// Callee-saved registers preserved when switching from C to JavaScript. ++const RegList kCalleeSaved = 1 << 8 | // fp/s0 ++ 1 << 9 | // s1 ++ 1 << 18 | // s2 ++ 1 << 19 | // s3 ++ 1 << 20 | // s4 ++ 1 << 21 | // s5 ++ 1 << 22 | // s6 (roots in Javascript code) ++ 1 << 23 | // s7 (cp in Javascript code) ++ 1 << 24 | // s8 ++ 1 << 25 | // s9 ++ 1 << 26 | // s10 ++ 1 << 27; // s11 ++ ++const int kNumCalleeSaved = 12; ++ ++const RegList kCalleeSavedFPU = 1 << 8 | // fs0 ++ 1 << 9 | // fs1 ++ 1 << 18 | // fs2 ++ 1 << 19 | // fs3 ++ 1 << 20 | // fs4 ++ 1 << 21 | // fs5 ++ 1 << 22 | // fs6 ++ 1 << 23 | // fs7 ++ 1 << 24 | // fs8 ++ 1 << 25 | // fs9 ++ 1 << 26 | // fs10 ++ 1 << 27; // fs11 ++ ++const int kNumCalleeSavedFPU = 12; ++ ++const RegList kCallerSavedFPU = 1 << 0 | // ft0 ++ 1 << 1 | // ft1 ++ 1 << 2 | // ft2 ++ 1 << 3 | // ft3 ++ 1 << 4 | // ft4 ++ 1 << 5 | // ft5 ++ 1 << 6 | // ft6 ++ 1 << 7 | // ft7 ++ 1 << 10 | // fa0 ++ 1 << 11 | // fa1 ++ 1 << 12 | // fa2 ++ 1 << 13 | // fa3 ++ 1 << 14 | // fa4 ++ 1 << 15 | // fa5 ++ 1 << 16 | // fa6 ++ 1 << 17 | // fa7 ++ 1 << 28 | // ft8 ++ 1 << 29 | // ft9 ++ 1 << 30 | // ft10 ++ 1 << 31; // ft11 ++ ++// Number of registers for which space is reserved in safepoints. Must be a ++// multiple of 8. ++const int kNumSafepointRegisters = 32; ++ ++// Define the list of registers actually saved at safepoints. ++// Note that the number of saved registers may be smaller than the reserved ++// space, i.e. kNumSafepointSavedRegisters <= kNumSafepointRegisters. ++const RegList kSafepointSavedRegisters = kJSCallerSaved | kCalleeSaved; ++const int kNumSafepointSavedRegisters = kNumJSCallerSaved + kNumCalleeSaved; ++ ++const int kUndefIndex = -1; ++// Map with indexes on stack that corresponds to codes of saved registers. ++const int kSafepointRegisterStackIndexMap[kNumRegs] = {kUndefIndex, // zero_reg ++ kUndefIndex, // ra ++ kUndefIndex, // sp ++ kUndefIndex, // gp ++ kUndefIndex, // tp ++ 0, // t0 ++ 1, // t1 ++ 2, // t2 ++ 3, // s0/fp ++ 4, // s1 ++ 5, // a0 ++ 6, // a1 ++ 7, // a2 ++ 8, // a3 ++ 9, // a4 ++ 10, // a5 ++ 11, // a6 ++ 12, // a7 ++ 13, // s2 ++ 14, // s3 ++ 15, // s4 ++ 16, // s5 ++ 17, // s6 ++ 18, // s7 ++ 19, // s8 ++ 10, // s9 ++ 21, // s10 ++ 22, // s11 ++ kUndefIndex, // t3 ++ 23, // t4 ++ kUndefIndex, // t5 ++ kUndefIndex}; // t6 ++// CPU Registers. ++// ++// 1) We would prefer to use an enum, but enum values are assignment- ++// compatible with int, which has caused code-generation bugs. ++// ++// 2) We would prefer to use a class instead of a struct but we don't like ++// the register initialization to depend on the particular initialization ++// order (which appears to be different on OS X, Linux, and Windows for the ++// installed versions of C++ we tried). Using a struct permits C-style ++// "initialization". Also, the Register objects cannot be const as this ++// forces initialization stubs in MSVC, making us dependent on initialization ++// order. ++// ++// 3) By not using an enum, we are possibly preventing the compiler from ++// doing certain constant folds, which may significantly reduce the ++// code generated for some assembly instructions (because they boil down ++// to a few constants). If this is a problem, we could change the code ++// such that we use an enum in optimized mode, and the struct in debug ++// mode. This way we get the compile-time error checking in debug mode ++// and best performance in optimized code. ++ ++// ----------------------------------------------------------------------------- ++// Implementation of Register and FPURegister. ++ ++enum RegisterCode { ++#define REGISTER_CODE(R) kRegCode_##R, ++ GENERAL_REGISTERS(REGISTER_CODE) ++#undef REGISTER_CODE ++ kRegAfterLast ++}; ++ ++class Register : public RegisterBase { ++ public: ++#if defined(V8_TARGET_LITTLE_ENDIAN) ++ static constexpr int kMantissaOffset = 0; ++ static constexpr int kExponentOffset = 4; ++#elif defined(V8_TARGET_BIG_ENDIAN) ++ static constexpr int kMantissaOffset = 4; ++ static constexpr int kExponentOffset = 0; ++#else ++#error Unknown endianness ++#endif ++ ++ private: ++ friend class RegisterBase; ++ explicit constexpr Register(int code) : RegisterBase(code) {} ++}; ++ ++// s7: context register ++// s3: scratch register ++// s4: scratch register 2 ++#define DECLARE_REGISTER(R) \ ++ constexpr Register R = Register::from_code(kRegCode_##R); ++GENERAL_REGISTERS(DECLARE_REGISTER) ++#undef DECLARE_REGISTER ++ ++constexpr Register no_reg = Register::no_reg(); ++ ++int ToNumber(Register reg); ++ ++Register ToRegister(int num); ++ ++constexpr bool kPadArguments = false; ++constexpr bool kSimpleFPAliasing = true; ++constexpr bool kSimdMaskRegisters = false; ++ ++enum DoubleRegisterCode { ++#define REGISTER_CODE(R) kDoubleCode_##R, ++ DOUBLE_REGISTERS(REGISTER_CODE) ++#undef REGISTER_CODE ++ kDoubleAfterLast ++}; ++ ++// Coprocessor register. ++class FPURegister : public RegisterBase { ++ public: ++ // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers ++ // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to ++ // number of Double regs (64-bit regs, or FPU-reg-pairs). ++ ++ FPURegister low() const { ++ // TODO(plind): Create DCHECK for FR=0 mode. This usage suspect for FR=1. ++ // Find low reg of a Double-reg pair, which is the reg itself. ++ return FPURegister::from_code(code()); ++ } ++ FPURegister high() const { ++ // TODO(plind): Create DCHECK for FR=0 mode. This usage illegal in FR=1. ++ // Find high reg of a Doubel-reg pair, which is reg + 1. ++ return FPURegister::from_code(code() + 1); ++ } ++ ++ private: ++ friend class RegisterBase; ++ explicit constexpr FPURegister(int code) : RegisterBase(code) {} ++}; ++ ++enum MSARegisterCode { ++#define REGISTER_CODE(R) kMsaCode_##R, ++ SIMD128_REGISTERS(REGISTER_CODE) ++#undef REGISTER_CODE ++ kMsaAfterLast ++}; ++ ++// MIPS SIMD (MSA) register ++// FIXME (RISCV) ++class MSARegister : public RegisterBase { ++ friend class RegisterBase; ++ explicit constexpr MSARegister(int code) : RegisterBase(code) {} ++}; ++ ++// A few double registers are reserved: one as a scratch register and one to ++// hold 0.0. ++// fs9: 0.0 ++// fs11: scratch register. ++ ++// For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers. ++using FloatRegister = FPURegister; ++ ++using DoubleRegister = FPURegister; ++ ++#define DECLARE_DOUBLE_REGISTER(R) \ ++ constexpr DoubleRegister R = DoubleRegister::from_code(kDoubleCode_##R); ++DOUBLE_REGISTERS(DECLARE_DOUBLE_REGISTER) ++#undef DECLARE_DOUBLE_REGISTER ++ ++constexpr DoubleRegister no_dreg = DoubleRegister::no_reg(); ++ ++// SIMD registers. ++using Simd128Register = MSARegister; ++ ++#define DECLARE_SIMD128_REGISTER(R) \ ++ constexpr Simd128Register R = Simd128Register::from_code(kMsaCode_##R); ++SIMD128_REGISTERS(DECLARE_SIMD128_REGISTER) ++#undef DECLARE_SIMD128_REGISTER ++ ++const Simd128Register no_msareg = Simd128Register::no_reg(); ++ ++// Register aliases. ++// cp is assumed to be a callee saved register. ++constexpr Register kRootRegister = s6; ++constexpr Register cp = s7; ++constexpr Register kScratchReg = s3; ++constexpr Register kScratchReg2 = s4; ++ ++constexpr DoubleRegister kScratchDoubleReg = fs11; ++ ++constexpr DoubleRegister kDoubleRegZero = fs9; ++ ++// Define {RegisterName} methods for the register types. ++DEFINE_REGISTER_NAMES(Register, GENERAL_REGISTERS) ++DEFINE_REGISTER_NAMES(FPURegister, DOUBLE_REGISTERS) ++DEFINE_REGISTER_NAMES(MSARegister, SIMD128_REGISTERS) ++ ++// Give alias names to registers for calling conventions. ++constexpr Register kReturnRegister0 = a0; ++constexpr Register kReturnRegister1 = a1; ++constexpr Register kReturnRegister2 = a2; ++constexpr Register kJSFunctionRegister = a1; ++constexpr Register kContextRegister = s7; ++constexpr Register kAllocateSizeRegister = a1; ++constexpr Register kSpeculationPoisonRegister = a7; ++constexpr Register kInterpreterAccumulatorRegister = a0; ++constexpr Register kInterpreterBytecodeOffsetRegister = t0; ++constexpr Register kInterpreterBytecodeArrayRegister = t1; ++constexpr Register kInterpreterDispatchTableRegister = t2; ++ ++constexpr Register kJavaScriptCallArgCountRegister = a0; ++constexpr Register kJavaScriptCallCodeStartRegister = a2; ++constexpr Register kJavaScriptCallTargetRegister = kJSFunctionRegister; ++constexpr Register kJavaScriptCallNewTargetRegister = a3; ++constexpr Register kJavaScriptCallExtraArg1Register = a2; ++ ++constexpr Register kOffHeapTrampolineRegister = t3; ++constexpr Register kRuntimeCallFunctionRegister = a1; ++constexpr Register kRuntimeCallArgCountRegister = a0; ++constexpr Register kRuntimeCallArgvRegister = a2; ++constexpr Register kWasmInstanceRegister = a0; ++constexpr Register kWasmCompileLazyFuncIndexRegister = t0; ++ ++constexpr DoubleRegister kFPReturnRegister0 = fa0; ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_CODEGEN_RISCV_REGISTER_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/common/globals.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/common/globals.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/common/globals.h +@@ -58,6 +58,12 @@ constexpr int GB = MB * 1024; + #if (V8_TARGET_ARCH_S390 && !V8_HOST_ARCH_S390) + #define USE_SIMULATOR 1 + #endif ++#if (V8_TARGET_ARCH_RISCV64 && !V8_HOST_ARCH_RISCV64) ++#define USE_SIMULATOR 1 ++#endif ++#if (V8_TARGET_ARCH_RISCV && !V8_HOST_ARCH_RISCV && !V8_HOST_ARCH_RISCV64) ++#define USE_SIMULATOR 1 ++#endif + #endif + + // Determine whether the architecture uses an embedded constant pool +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/instruction-codes.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/compiler/backend/instruction-codes.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/instruction-codes.h +@@ -23,6 +23,10 @@ + #include "src/compiler/backend/ppc/instruction-codes-ppc.h" + #elif V8_TARGET_ARCH_S390 + #include "src/compiler/backend/s390/instruction-codes-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/compiler/backend/riscv64/instruction-codes-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/compiler/backend/riscv/instruction-codes-riscv.h" + #else + #define TARGET_ARCH_OPCODE_LIST(V) + #define TARGET_ADDRESSING_MODE_LIST(V) +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/instruction-selector.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/compiler/backend/instruction-selector.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/instruction-selector.cc +@@ -2623,7 +2623,8 @@ void InstructionSelector::VisitWord32Ato + #endif // !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_MIPS + + #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS64 && \ +- !V8_TARGET_ARCH_S390 && !V8_TARGET_ARCH_PPC64 ++ !V8_TARGET_ARCH_S390 && !V8_TARGET_ARCH_PPC64 && \ ++ !V8_TARGET_ARCH_RISCV64 && !V8_TARGET_ARCH_RISCV + void InstructionSelector::VisitWord64AtomicLoad(Node* node) { UNIMPLEMENTED(); } + + void InstructionSelector::VisitWord64AtomicStore(Node* node) { +@@ -2648,7 +2649,8 @@ void InstructionSelector::VisitWord64Ato + UNIMPLEMENTED(); + } + #endif // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_PPC64 +- // !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_S390 ++ // !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_S390 && ++ // !V8_TARGET_ARCH_RISCV64 && !V8_TARGET_ARCH_RISCV + + #if !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM + // This is only needed on 32-bit to split the 64-bit value into two operands. +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/code-generator-riscv64.cc +@@ -0,0 +1,2759 @@ ++// Copyright 2014 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#include "src/codegen/assembler-inl.h" ++#include "src/codegen/callable.h" ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/optimized-compilation-info.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/compiler/backend/code-generator-impl.h" ++#include "src/compiler/backend/code-generator.h" ++#include "src/compiler/backend/gap-resolver.h" ++#include "src/compiler/node-matchers.h" ++#include "src/compiler/osr.h" ++#include "src/heap/memory-chunk.h" ++#include "src/wasm/wasm-code-manager.h" ++ ++namespace v8 { ++namespace internal { ++namespace compiler { ++ ++#define __ tasm()-> ++ ++// TODO(plind): consider renaming these macros. ++#define TRACE_MSG(msg) \ ++ PrintF("code_gen: \'%s\' in function %s at line %d\n", msg, __FUNCTION__, \ ++ __LINE__) ++ ++#define TRACE_UNIMPL() \ ++ PrintF("UNIMPLEMENTED code_generator_riscv64: %s at line %d\n", \ ++ __FUNCTION__, __LINE__) ++ ++// Adds RISC-V-specific methods to convert InstructionOperands. ++class RiscvOperandConverter final : public InstructionOperandConverter { ++ public: ++ RiscvOperandConverter(CodeGenerator* gen, Instruction* instr) ++ : InstructionOperandConverter(gen, instr) {} ++ ++ FloatRegister OutputSingleRegister(size_t index = 0) { ++ return ToSingleRegister(instr_->OutputAt(index)); ++ } ++ ++ FloatRegister InputSingleRegister(size_t index) { ++ return ToSingleRegister(instr_->InputAt(index)); ++ } ++ ++ FloatRegister ToSingleRegister(InstructionOperand* op) { ++ // Single (Float) and Double register namespace is same on RISC-V, ++ // both are typedefs of FPURegister. ++ return ToDoubleRegister(op); ++ } ++ ++ Register InputOrZeroRegister(size_t index) { ++ if (instr_->InputAt(index)->IsImmediate()) { ++ DCHECK_EQ(0, InputInt32(index)); ++ return zero_reg; ++ } ++ return InputRegister(index); ++ } ++ ++ DoubleRegister InputOrZeroDoubleRegister(size_t index) { ++ if (instr_->InputAt(index)->IsImmediate()) return kDoubleRegZero; ++ ++ return InputDoubleRegister(index); ++ } ++ ++ DoubleRegister InputOrZeroSingleRegister(size_t index) { ++ if (instr_->InputAt(index)->IsImmediate()) return kDoubleRegZero; ++ ++ return InputSingleRegister(index); ++ } ++ ++ Operand InputImmediate(size_t index) { ++ Constant constant = ToConstant(instr_->InputAt(index)); ++ switch (constant.type()) { ++ case Constant::kInt32: ++ return Operand(constant.ToInt32()); ++ case Constant::kInt64: ++ return Operand(constant.ToInt64()); ++ case Constant::kFloat32: ++ return Operand::EmbeddedNumber(constant.ToFloat32()); ++ case Constant::kFloat64: ++ return Operand::EmbeddedNumber(constant.ToFloat64().value()); ++ case Constant::kExternalReference: ++ case Constant::kCompressedHeapObject: ++ case Constant::kHeapObject: ++ // TODO(plind): Maybe we should handle ExtRef & HeapObj here? ++ // maybe not done on arm due to const pool ?? ++ break; ++ case Constant::kDelayedStringConstant: ++ return Operand::EmbeddedStringConstant( ++ constant.ToDelayedStringConstant()); ++ case Constant::kRpoNumber: ++ UNREACHABLE(); // TODO(titzer): RPO immediates ++ break; ++ } ++ UNREACHABLE(); ++ } ++ ++ Operand InputOperand(size_t index) { ++ InstructionOperand* op = instr_->InputAt(index); ++ if (op->IsRegister()) { ++ return Operand(ToRegister(op)); ++ } ++ return InputImmediate(index); ++ } ++ ++ MemOperand MemoryOperand(size_t* first_index) { ++ const size_t index = *first_index; ++ switch (AddressingModeField::decode(instr_->opcode())) { ++ case kMode_None: ++ break; ++ case kMode_MRI: ++ *first_index += 2; ++ return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); ++ case kMode_MRR: ++ // TODO(plind): r6 address mode, to be implemented ... ++ UNREACHABLE(); ++ } ++ UNREACHABLE(); ++ } ++ ++ MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); } ++ ++ MemOperand ToMemOperand(InstructionOperand* op) const { ++ DCHECK_NOT_NULL(op); ++ DCHECK(op->IsStackSlot() || op->IsFPStackSlot()); ++ return SlotToMemOperand(AllocatedOperand::cast(op)->index()); ++ } ++ ++ MemOperand SlotToMemOperand(int slot) const { ++ FrameOffset offset = frame_access_state()->GetFrameOffset(slot); ++ return MemOperand(offset.from_stack_pointer() ? sp : fp, offset.offset()); ++ } ++}; ++ ++static inline bool HasRegisterInput(Instruction* instr, size_t index) { ++ return instr->InputAt(index)->IsRegister(); ++} ++ ++namespace { ++ ++class OutOfLineRecordWrite final : public OutOfLineCode { ++ public: ++ OutOfLineRecordWrite(CodeGenerator* gen, Register object, Register index, ++ Register value, Register scratch0, Register scratch1, ++ RecordWriteMode mode, StubCallMode stub_mode) ++ : OutOfLineCode(gen), ++ object_(object), ++ index_(index), ++ value_(value), ++ scratch0_(scratch0), ++ scratch1_(scratch1), ++ mode_(mode), ++ stub_mode_(stub_mode), ++ must_save_lr_(!gen->frame_access_state()->has_frame()), ++ zone_(gen->zone()) {} ++ ++ void Generate() final { ++ if (mode_ > RecordWriteMode::kValueIsPointer) { ++ __ JumpIfSmi(value_, exit()); ++ } ++ __ CheckPageFlag(value_, scratch0_, ++ MemoryChunk::kPointersToHereAreInterestingMask, eq, ++ exit()); ++ __ Add64(scratch1_, object_, index_); ++ RememberedSetAction const remembered_set_action = ++ mode_ > RecordWriteMode::kValueIsMap ? EMIT_REMEMBERED_SET ++ : OMIT_REMEMBERED_SET; ++ SaveFPRegsMode const save_fp_mode = ++ frame()->DidAllocateDoubleRegisters() ? kSaveFPRegs : kDontSaveFPRegs; ++ if (must_save_lr_) { ++ // We need to save and restore ra if the frame was elided. ++ __ Push(ra); ++ } ++ if (mode_ == RecordWriteMode::kValueIsEphemeronKey) { ++ __ CallEphemeronKeyBarrier(object_, scratch1_, save_fp_mode); ++ } else if (stub_mode_ == StubCallMode::kCallWasmRuntimeStub) { ++ // A direct call to a wasm runtime stub defined in this module. ++ // Just encode the stub index. This will be patched when the code ++ // is added to the native module and copied into wasm code space. ++ __ CallRecordWriteStub(object_, scratch1_, remembered_set_action, ++ save_fp_mode, wasm::WasmCode::kRecordWrite); ++ } else { ++ __ CallRecordWriteStub(object_, scratch1_, remembered_set_action, ++ save_fp_mode); ++ } ++ if (must_save_lr_) { ++ __ Pop(ra); ++ } ++ } ++ ++ private: ++ Register const object_; ++ Register const index_; ++ Register const value_; ++ Register const scratch0_; ++ Register const scratch1_; ++ RecordWriteMode const mode_; ++ StubCallMode const stub_mode_; ++ bool must_save_lr_; ++ Zone* zone_; ++}; ++ ++Condition FlagsConditionToConditionCmp(FlagsCondition condition) { ++ switch (condition) { ++ case kEqual: ++ return eq; ++ case kNotEqual: ++ return ne; ++ case kSignedLessThan: ++ return lt; ++ case kSignedGreaterThanOrEqual: ++ return ge; ++ case kSignedLessThanOrEqual: ++ return le; ++ case kSignedGreaterThan: ++ return gt; ++ case kUnsignedLessThan: ++ return Uless; ++ case kUnsignedGreaterThanOrEqual: ++ return Ugreater_equal; ++ case kUnsignedLessThanOrEqual: ++ return Uless_equal; ++ case kUnsignedGreaterThan: ++ return Ugreater; ++ case kUnorderedEqual: ++ case kUnorderedNotEqual: ++ break; ++ default: ++ break; ++ } ++ UNREACHABLE(); ++} ++ ++Condition FlagsConditionToConditionTst(FlagsCondition condition) { ++ switch (condition) { ++ case kNotEqual: ++ return ne; ++ case kEqual: ++ return eq; ++ default: ++ break; ++ } ++ UNREACHABLE(); ++} ++ ++Condition FlagsConditionToConditionOvf(FlagsCondition condition) { ++ switch (condition) { ++ case kOverflow: ++ return ne; ++ case kNotOverflow: ++ return eq; ++ default: ++ break; ++ } ++ UNREACHABLE(); ++} ++ ++FPUCondition FlagsConditionToConditionCmpFPU(bool* predicate, ++ FlagsCondition condition) { ++ switch (condition) { ++ case kEqual: ++ *predicate = true; ++ return EQ; ++ case kNotEqual: ++ *predicate = false; ++ return EQ; ++ case kUnsignedLessThan: ++ *predicate = true; ++ return LT; ++ case kUnsignedGreaterThanOrEqual: ++ *predicate = false; ++ return LT; ++ case kUnsignedLessThanOrEqual: ++ *predicate = true; ++ return LE; ++ case kUnsignedGreaterThan: ++ *predicate = false; ++ return LE; ++ case kUnorderedEqual: ++ case kUnorderedNotEqual: ++ *predicate = true; ++ break; ++ default: ++ *predicate = true; ++ break; ++ } ++ UNREACHABLE(); ++} ++ ++void EmitWordLoadPoisoningIfNeeded(CodeGenerator* codegen, ++ InstructionCode opcode, Instruction* instr, ++ RiscvOperandConverter const& i) { ++ const MemoryAccessMode access_mode = ++ static_cast(MiscField::decode(opcode)); ++ if (access_mode == kMemoryAccessPoisoned) { ++ Register value = i.OutputRegister(); ++ codegen->tasm()->And(value, value, kSpeculationPoisonRegister); ++ } ++} ++ ++} // namespace ++ ++#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr) \ ++ do { \ ++ __ asm_instr(i.OutputRegister(), i.MemoryOperand()); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_STORE_INTEGER(asm_instr) \ ++ do { \ ++ __ sync(); \ ++ __ asm_instr(i.InputOrZeroRegister(2), i.MemoryOperand()); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_BINOP(load_linked, store_conditional, bin_instr) \ ++ do { \ ++ Label binop; \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ __ sync(); \ ++ __ bind(&binop); \ ++ __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \ ++ __ bin_instr(i.TempRegister(1), i.OutputRegister(0), \ ++ Operand(i.InputRegister(2))); \ ++ __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&binop, ne, i.TempRegister(1), Operand(zero_reg)); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_BINOP_EXT(load_linked, store_conditional, sign_extend, \ ++ size, bin_instr, representation) \ ++ do { \ ++ Label binop; \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ if (representation == 32) { \ ++ __ And(i.TempRegister(3), i.TempRegister(0), 0x3); \ ++ } else { \ ++ DCHECK_EQ(representation, 64); \ ++ __ And(i.TempRegister(3), i.TempRegister(0), 0x7); \ ++ } \ ++ __ Sub64(i.TempRegister(0), i.TempRegister(0), \ ++ Operand(i.TempRegister(3))); \ ++ __ Sll32(i.TempRegister(3), i.TempRegister(3), 3); \ ++ __ sync(); \ ++ __ bind(&binop); \ ++ __ load_linked(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \ ++ __ ExtractBits(i.OutputRegister(0), i.TempRegister(1), i.TempRegister(3), \ ++ size, sign_extend); \ ++ __ bin_instr(i.TempRegister(2), i.OutputRegister(0), \ ++ Operand(i.InputRegister(2))); \ ++ __ InsertBits(i.TempRegister(1), i.TempRegister(2), i.TempRegister(3), \ ++ size); \ ++ __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&binop, ne, i.TempRegister(1), Operand(zero_reg)); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(load_linked, store_conditional) \ ++ do { \ ++ Label exchange; \ ++ __ sync(); \ ++ __ bind(&exchange); \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \ ++ __ Move(i.TempRegister(1), i.InputRegister(2)); \ ++ __ store_conditional(i.TempRegister(1), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&exchange, ne, i.TempRegister(1), Operand(zero_reg)); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT( \ ++ load_linked, store_conditional, sign_extend, size, representation) \ ++ do { \ ++ Label exchange; \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ if (representation == 32) { \ ++ __ And(i.TempRegister(1), i.TempRegister(0), 0x3); \ ++ } else { \ ++ DCHECK_EQ(representation, 64); \ ++ __ And(i.TempRegister(1), i.TempRegister(0), 0x7); \ ++ } \ ++ __ Sub64(i.TempRegister(0), i.TempRegister(0), \ ++ Operand(i.TempRegister(1))); \ ++ __ Sll32(i.TempRegister(1), i.TempRegister(1), 3); \ ++ __ sync(); \ ++ __ bind(&exchange); \ ++ __ load_linked(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \ ++ __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \ ++ size, sign_extend); \ ++ __ InsertBits(i.TempRegister(2), i.InputRegister(2), i.TempRegister(1), \ ++ size); \ ++ __ store_conditional(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&exchange, ne, i.TempRegister(2), Operand(zero_reg)); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(load_linked, \ ++ store_conditional) \ ++ do { \ ++ Label compareExchange; \ ++ Label exit; \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ __ sync(); \ ++ __ bind(&compareExchange); \ ++ __ load_linked(i.OutputRegister(0), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&exit, ne, i.InputRegister(2), \ ++ Operand(i.OutputRegister(0))); \ ++ __ Move(i.TempRegister(2), i.InputRegister(3)); \ ++ __ store_conditional(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&compareExchange, ne, i.TempRegister(2), \ ++ Operand(zero_reg)); \ ++ __ bind(&exit); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT( \ ++ load_linked, store_conditional, sign_extend, size, representation) \ ++ do { \ ++ Label compareExchange; \ ++ Label exit; \ ++ __ Add64(i.TempRegister(0), i.InputRegister(0), i.InputRegister(1)); \ ++ if (representation == 32) { \ ++ __ And(i.TempRegister(1), i.TempRegister(0), 0x3); \ ++ } else { \ ++ DCHECK_EQ(representation, 64); \ ++ __ And(i.TempRegister(1), i.TempRegister(0), 0x7); \ ++ } \ ++ __ Sub64(i.TempRegister(0), i.TempRegister(0), \ ++ Operand(i.TempRegister(1))); \ ++ __ Sll32(i.TempRegister(1), i.TempRegister(1), 3); \ ++ __ sync(); \ ++ __ bind(&compareExchange); \ ++ __ load_linked(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \ ++ __ ExtractBits(i.OutputRegister(0), i.TempRegister(2), i.TempRegister(1), \ ++ size, sign_extend); \ ++ __ ExtractBits(i.InputRegister(2), i.InputRegister(2), i.TempRegister(1), \ ++ size, sign_extend); \ ++ __ BranchShort(&exit, ne, i.InputRegister(2), \ ++ Operand(i.OutputRegister(0))); \ ++ __ InsertBits(i.TempRegister(2), i.InputRegister(3), i.TempRegister(1), \ ++ size); \ ++ __ store_conditional(i.TempRegister(2), MemOperand(i.TempRegister(0), 0)); \ ++ __ BranchShort(&compareExchange, ne, i.TempRegister(2), \ ++ Operand(zero_reg)); \ ++ __ bind(&exit); \ ++ __ sync(); \ ++ } while (0) ++ ++#define ASSEMBLE_IEEE754_BINOP(name) \ ++ do { \ ++ FrameScope scope(tasm(), StackFrame::MANUAL); \ ++ __ PrepareCallCFunction(0, 2, kScratchReg); \ ++ __ MovToFloatParameters(i.InputDoubleRegister(0), \ ++ i.InputDoubleRegister(1)); \ ++ __ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 2); \ ++ /* Move the result in the double result register. */ \ ++ __ MovFromFloatResult(i.OutputDoubleRegister()); \ ++ } while (0) ++ ++#define ASSEMBLE_IEEE754_UNOP(name) \ ++ do { \ ++ FrameScope scope(tasm(), StackFrame::MANUAL); \ ++ __ PrepareCallCFunction(0, 1, kScratchReg); \ ++ __ MovToFloatParameter(i.InputDoubleRegister(0)); \ ++ __ CallCFunction(ExternalReference::ieee754_##name##_function(), 0, 1); \ ++ /* Move the result in the double result register. */ \ ++ __ MovFromFloatResult(i.OutputDoubleRegister()); \ ++ } while (0) ++ ++#define ASSEMBLE_F64X2_ARITHMETIC_BINOP(op) \ ++ do { \ ++ __ op(i.OutputSimd128Register(), i.InputSimd128Register(0), \ ++ i.InputSimd128Register(1)); \ ++ } while (0) ++ ++void CodeGenerator::AssembleDeconstructFrame() { ++ __ Move(sp, fp); ++ __ Pop(ra, fp); ++} ++ ++void CodeGenerator::AssemblePrepareTailCall() { ++ if (frame_access_state()->has_frame()) { ++ __ Ld(ra, MemOperand(fp, StandardFrameConstants::kCallerPCOffset)); ++ __ Ld(fp, MemOperand(fp, StandardFrameConstants::kCallerFPOffset)); ++ } ++ frame_access_state()->SetFrameAccessToSP(); ++} ++ ++void CodeGenerator::AssemblePopArgumentsAdaptorFrame(Register args_reg, ++ Register scratch1, ++ Register scratch2, ++ Register scratch3) { ++ DCHECK(!AreAliased(args_reg, scratch1, scratch2, scratch3)); ++ Label done; ++ ++ // Check if current frame is an arguments adaptor frame. ++ __ Ld(scratch3, MemOperand(fp, StandardFrameConstants::kContextOffset)); ++ __ Branch(&done, ne, scratch3, ++ Operand(StackFrame::TypeToMarker(StackFrame::ARGUMENTS_ADAPTOR))); ++ ++ // Load arguments count from current arguments adaptor frame (note, it ++ // does not include receiver). ++ Register caller_args_count_reg = scratch1; ++ __ Ld(caller_args_count_reg, ++ MemOperand(fp, ArgumentsAdaptorFrameConstants::kLengthOffset)); ++ __ SmiUntag(caller_args_count_reg); ++ ++ __ PrepareForTailCall(args_reg, caller_args_count_reg, scratch2, scratch3); ++ __ bind(&done); ++} ++ ++namespace { ++ ++void AdjustStackPointerForTailCall(TurboAssembler* tasm, ++ FrameAccessState* state, ++ int new_slot_above_sp, ++ bool allow_shrinkage = true) { ++ int current_sp_offset = state->GetSPToFPSlotCount() + ++ StandardFrameConstants::kFixedSlotCountAboveFp; ++ int stack_slot_delta = new_slot_above_sp - current_sp_offset; ++ if (stack_slot_delta > 0) { ++ tasm->Sub64(sp, sp, stack_slot_delta * kSystemPointerSize); ++ state->IncreaseSPDelta(stack_slot_delta); ++ } else if (allow_shrinkage && stack_slot_delta < 0) { ++ tasm->Add64(sp, sp, -stack_slot_delta * kSystemPointerSize); ++ state->IncreaseSPDelta(stack_slot_delta); ++ } ++} ++ ++} // namespace ++ ++void CodeGenerator::AssembleTailCallBeforeGap(Instruction* instr, ++ int first_unused_stack_slot) { ++ AdjustStackPointerForTailCall(tasm(), frame_access_state(), ++ first_unused_stack_slot, false); ++} ++ ++void CodeGenerator::AssembleTailCallAfterGap(Instruction* instr, ++ int first_unused_stack_slot) { ++ AdjustStackPointerForTailCall(tasm(), frame_access_state(), ++ first_unused_stack_slot); ++} ++ ++// Check that {kJavaScriptCallCodeStartRegister} is correct. ++void CodeGenerator::AssembleCodeStartRegisterCheck() { ++ __ ComputeCodeStartAddress(kScratchReg); ++ __ Assert(eq, AbortReason::kWrongFunctionCodeStart, ++ kJavaScriptCallCodeStartRegister, Operand(kScratchReg)); ++} ++ ++// Check if the code object is marked for deoptimization. If it is, then it ++// jumps to the CompileLazyDeoptimizedCode builtin. In order to do this we need ++// to: ++// 1. read from memory the word that contains that bit, which can be found in ++// the flags in the referenced {CodeDataContainer} object; ++// 2. test kMarkedForDeoptimizationBit in those flags; and ++// 3. if it is not zero then it jumps to the builtin. ++void CodeGenerator::BailoutIfDeoptimized() { ++ int offset = Code::kCodeDataContainerOffset - Code::kHeaderSize; ++ __ Ld(kScratchReg, MemOperand(kJavaScriptCallCodeStartRegister, offset)); ++ __ Lw(kScratchReg, ++ FieldMemOperand(kScratchReg, ++ CodeDataContainer::kKindSpecificFlagsOffset)); ++ __ And(kScratchReg, kScratchReg, ++ Operand(1 << Code::kMarkedForDeoptimizationBit)); ++ __ Jump(BUILTIN_CODE(isolate(), CompileLazyDeoptimizedCode), ++ RelocInfo::CODE_TARGET, ne, kScratchReg, Operand(zero_reg)); ++} ++ ++void CodeGenerator::GenerateSpeculationPoisonFromCodeStartRegister() { ++ // Calculate a mask which has all bits set in the normal case, but has all ++ // bits cleared if we are speculatively executing the wrong PC. ++ // difference = (current - expected) | (expected - current) ++ // poison = ~(difference >> (kBitsPerSystemPointer - 1)) ++ __ ComputeCodeStartAddress(kScratchReg); ++ __ Move(kSpeculationPoisonRegister, kScratchReg); ++ __ Sub32(kSpeculationPoisonRegister, kSpeculationPoisonRegister, ++ kJavaScriptCallCodeStartRegister); ++ __ Sub32(kJavaScriptCallCodeStartRegister, kJavaScriptCallCodeStartRegister, ++ kScratchReg); ++ __ or_(kSpeculationPoisonRegister, kSpeculationPoisonRegister, ++ kJavaScriptCallCodeStartRegister); ++ __ Sra64(kSpeculationPoisonRegister, kSpeculationPoisonRegister, ++ kBitsPerSystemPointer - 1); ++ __ Nor(kSpeculationPoisonRegister, kSpeculationPoisonRegister, ++ kSpeculationPoisonRegister); ++} ++ ++void CodeGenerator::AssembleRegisterArgumentPoisoning() { ++ __ And(kJSFunctionRegister, kJSFunctionRegister, kSpeculationPoisonRegister); ++ __ And(kContextRegister, kContextRegister, kSpeculationPoisonRegister); ++ __ And(sp, sp, kSpeculationPoisonRegister); ++} ++ ++// Assembles an instruction after register allocation, producing machine code. ++CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ++ Instruction* instr) { ++ RiscvOperandConverter i(this, instr); ++ InstructionCode opcode = instr->opcode(); ++ ArchOpcode arch_opcode = ArchOpcodeField::decode(opcode); ++ switch (arch_opcode) { ++ case kArchCallCodeObject: { ++ if (instr->InputAt(0)->IsImmediate()) { ++ __ Call(i.InputCode(0), RelocInfo::CODE_TARGET); ++ } else { ++ Register reg = i.InputRegister(0); ++ DCHECK_IMPLIES( ++ HasCallDescriptorFlag(instr, CallDescriptor::kFixedTargetRegister), ++ reg == kJavaScriptCallCodeStartRegister); ++ __ Add64(reg, reg, Code::kHeaderSize - kHeapObjectTag); ++ __ Call(reg); ++ } ++ RecordCallPosition(instr); ++ frame_access_state()->ClearSPDelta(); ++ break; ++ } ++ case kArchCallBuiltinPointer: { ++ DCHECK(!instr->InputAt(0)->IsImmediate()); ++ Register builtin_index = i.InputRegister(0); ++ __ CallBuiltinByIndex(builtin_index); ++ RecordCallPosition(instr); ++ frame_access_state()->ClearSPDelta(); ++ break; ++ } ++ case kArchCallWasmFunction: { ++ // FIXME (RISCV): isnt this test deadcode? ++ if (arch_opcode == kArchTailCallCodeObjectFromJSFunction) { ++ AssemblePopArgumentsAdaptorFrame(kJavaScriptCallArgCountRegister, ++ i.TempRegister(0), i.TempRegister(1), ++ i.TempRegister(2)); ++ } ++ if (instr->InputAt(0)->IsImmediate()) { ++ Constant constant = i.ToConstant(instr->InputAt(0)); ++ Address wasm_code = static_cast

(constant.ToInt64()); ++ __ Call(wasm_code, constant.rmode()); ++ } else { ++ __ Add64(kScratchReg, i.InputRegister(0), 0); ++ __ Call(kScratchReg); ++ } ++ RecordCallPosition(instr); ++ frame_access_state()->ClearSPDelta(); ++ break; ++ } ++ case kArchTailCallCodeObjectFromJSFunction: ++ case kArchTailCallCodeObject: { ++ if (arch_opcode == kArchTailCallCodeObjectFromJSFunction) { ++ AssemblePopArgumentsAdaptorFrame(kJavaScriptCallArgCountRegister, ++ i.TempRegister(0), i.TempRegister(1), ++ i.TempRegister(2)); ++ } ++ if (instr->InputAt(0)->IsImmediate()) { ++ __ Jump(i.InputCode(0), RelocInfo::CODE_TARGET); ++ } else { ++ Register reg = i.InputRegister(0); ++ DCHECK_IMPLIES( ++ HasCallDescriptorFlag(instr, CallDescriptor::kFixedTargetRegister), ++ reg == kJavaScriptCallCodeStartRegister); ++ __ Add64(reg, reg, Code::kHeaderSize - kHeapObjectTag); ++ __ Jump(reg); ++ } ++ frame_access_state()->ClearSPDelta(); ++ frame_access_state()->SetFrameAccessToDefault(); ++ break; ++ } ++ case kArchTailCallWasm: { ++ if (instr->InputAt(0)->IsImmediate()) { ++ Constant constant = i.ToConstant(instr->InputAt(0)); ++ Address wasm_code = static_cast
(constant.ToInt64()); ++ __ Jump(wasm_code, constant.rmode()); ++ } else { ++ __ Add64(kScratchReg, i.InputRegister(0), 0); ++ __ Jump(kScratchReg); ++ } ++ frame_access_state()->ClearSPDelta(); ++ frame_access_state()->SetFrameAccessToDefault(); ++ break; ++ } ++ case kArchTailCallAddress: { ++ CHECK(!instr->InputAt(0)->IsImmediate()); ++ Register reg = i.InputRegister(0); ++ DCHECK_IMPLIES( ++ HasCallDescriptorFlag(instr, CallDescriptor::kFixedTargetRegister), ++ reg == kJavaScriptCallCodeStartRegister); ++ __ Jump(reg); ++ frame_access_state()->ClearSPDelta(); ++ frame_access_state()->SetFrameAccessToDefault(); ++ break; ++ } ++ case kArchCallJSFunction: { ++ Register func = i.InputRegister(0); ++ if (FLAG_debug_code) { ++ // Check the function's context matches the context argument. ++ __ Ld(kScratchReg, FieldMemOperand(func, JSFunction::kContextOffset)); ++ __ Assert(eq, AbortReason::kWrongFunctionContext, cp, ++ Operand(kScratchReg)); ++ } ++ static_assert(kJavaScriptCallCodeStartRegister == a2, "ABI mismatch"); ++ __ Ld(a2, FieldMemOperand(func, JSFunction::kCodeOffset)); ++ __ Add64(a2, a2, Operand(Code::kHeaderSize - kHeapObjectTag)); ++ __ Call(a2); ++ RecordCallPosition(instr); ++ frame_access_state()->ClearSPDelta(); ++ break; ++ } ++ case kArchPrepareCallCFunction: { ++ int const num_parameters = MiscField::decode(instr->opcode()); ++ __ PrepareCallCFunction(num_parameters, kScratchReg); ++ // Frame alignment requires using FP-relative frame addressing. ++ frame_access_state()->SetFrameAccessToFP(); ++ break; ++ } ++ case kArchSaveCallerRegisters: { ++ fp_mode_ = ++ static_cast(MiscField::decode(instr->opcode())); ++ DCHECK(fp_mode_ == kDontSaveFPRegs || fp_mode_ == kSaveFPRegs); ++ // kReturnRegister0 should have been saved before entering the stub. ++ int bytes = __ PushCallerSaved(fp_mode_, kReturnRegister0); ++ DCHECK(IsAligned(bytes, kSystemPointerSize)); ++ DCHECK_EQ(0, frame_access_state()->sp_delta()); ++ frame_access_state()->IncreaseSPDelta(bytes / kSystemPointerSize); ++ DCHECK(!caller_registers_saved_); ++ caller_registers_saved_ = true; ++ break; ++ } ++ case kArchRestoreCallerRegisters: { ++ DCHECK(fp_mode_ == ++ static_cast(MiscField::decode(instr->opcode()))); ++ DCHECK(fp_mode_ == kDontSaveFPRegs || fp_mode_ == kSaveFPRegs); ++ // Don't overwrite the returned value. ++ int bytes = __ PopCallerSaved(fp_mode_, kReturnRegister0); ++ frame_access_state()->IncreaseSPDelta(-(bytes / kSystemPointerSize)); ++ DCHECK_EQ(0, frame_access_state()->sp_delta()); ++ DCHECK(caller_registers_saved_); ++ caller_registers_saved_ = false; ++ break; ++ } ++ case kArchPrepareTailCall: ++ AssemblePrepareTailCall(); ++ break; ++ case kArchCallCFunction: { ++ int const num_parameters = MiscField::decode(instr->opcode()); ++ Label start_call; ++ bool isWasmCapiFunction = ++ linkage()->GetIncomingDescriptor()->IsWasmCapiFunction(); ++ // from start_call to return address. ++ // FIXME (RISC_V): is the same number of instructions generated from ++ // &start_call to after __CallCFunction()? This code seems quite brittle. ++ // Better to use label and PC-relative addressing to generate the return ++ // address ++ int offset = __ root_array_available() ? 64 : 72; ++#if V8_HOST_ARCH_RISCV64 ++ if (__ emit_debug_code()) { ++ offset += 16; ++ } ++#endif ++ if (isWasmCapiFunction) { ++ // Put the return address in a stack slot. ++ __ bind(&start_call); ++ __ auipc(kScratchReg, 0); ++ __ Add64(kScratchReg, kScratchReg, offset); ++ __ Sd(kScratchReg, ++ MemOperand(fp, WasmExitFrameConstants::kCallingPCOffset)); ++ } ++ if (instr->InputAt(0)->IsImmediate()) { ++ ExternalReference ref = i.InputExternalReference(0); ++ __ CallCFunction(ref, num_parameters); ++ } else { ++ Register func = i.InputRegister(0); ++ __ CallCFunction(func, num_parameters); ++ } ++ if (isWasmCapiFunction) { ++ CHECK_EQ(offset, __ SizeOfCodeGeneratedSince(&start_call)); ++ RecordSafepoint(instr->reference_map(), Safepoint::kNoLazyDeopt); ++ } ++ ++ frame_access_state()->SetFrameAccessToDefault(); ++ // Ideally, we should decrement SP delta to match the change of stack ++ // pointer in CallCFunction. However, for certain architectures (e.g. ++ // ARM), there may be more strict alignment requirement, causing old SP ++ // to be saved on the stack. In those cases, we can not calculate the SP ++ // delta statically. ++ frame_access_state()->ClearSPDelta(); ++ if (caller_registers_saved_) { ++ // Need to re-sync SP delta introduced in kArchSaveCallerRegisters. ++ // Here, we assume the sequence to be: ++ // kArchSaveCallerRegisters; ++ // kArchCallCFunction; ++ // kArchRestoreCallerRegisters; ++ int bytes = ++ __ RequiredStackSizeForCallerSaved(fp_mode_, kReturnRegister0); ++ frame_access_state()->IncreaseSPDelta(bytes / kSystemPointerSize); ++ } ++ break; ++ } ++ case kArchJmp: ++ AssembleArchJump(i.InputRpo(0)); ++ break; ++ case kArchBinarySearchSwitch: ++ AssembleArchBinarySearchSwitch(instr); ++ break; ++ case kArchTableSwitch: ++ AssembleArchTableSwitch(instr); ++ break; ++ case kArchAbortCSAAssert: ++ DCHECK(i.InputRegister(0) == a0); ++ { ++ // We don't actually want to generate a pile of code for this, so just ++ // claim there is a stack frame, without generating one. ++ FrameScope scope(tasm(), StackFrame::NONE); ++ __ Call( ++ isolate()->builtins()->builtin_handle(Builtins::kAbortCSAAssert), ++ RelocInfo::CODE_TARGET); ++ } ++ __ stop(); ++ break; ++ case kArchDebugBreak: ++ __ DebugBreak(); ++ break; ++ case kArchComment: ++ __ RecordComment(reinterpret_cast(i.InputInt64(0))); ++ break; ++ case kArchNop: ++ case kArchThrowTerminator: ++ // don't emit code for nops. ++ break; ++ case kArchDeoptimize: { ++ DeoptimizationExit* exit = ++ BuildTranslation(instr, -1, 0, OutputFrameStateCombine::Ignore()); ++ CodeGenResult result = AssembleDeoptimizerCall(exit); ++ if (result != kSuccess) return result; ++ break; ++ } ++ case kArchRet: ++ AssembleReturn(instr->InputAt(0)); ++ break; ++ case kArchStackPointerGreaterThan: ++ // Pseudo-instruction used for cmp/branch. No opcode emitted here. ++ break; ++ case kArchStackCheckOffset: ++ __ Move(i.OutputRegister(), Smi::FromInt(GetStackCheckOffset())); ++ break; ++ case kArchFramePointer: ++ __ Move(i.OutputRegister(), fp); ++ break; ++ case kArchParentFramePointer: ++ if (frame_access_state()->has_frame()) { ++ __ Ld(i.OutputRegister(), MemOperand(fp, 0)); ++ } else { ++ __ Move(i.OutputRegister(), fp); ++ } ++ break; ++ case kArchTruncateDoubleToI: ++ __ TruncateDoubleToI(isolate(), zone(), i.OutputRegister(), ++ i.InputDoubleRegister(0), DetermineStubCallMode()); ++ break; ++ case kArchStoreWithWriteBarrier: { ++ RecordWriteMode mode = ++ static_cast(MiscField::decode(instr->opcode())); ++ Register object = i.InputRegister(0); ++ Register index = i.InputRegister(1); ++ Register value = i.InputRegister(2); ++ Register scratch0 = i.TempRegister(0); ++ Register scratch1 = i.TempRegister(1); ++ auto ool = zone()->New(this, object, index, value, ++ scratch0, scratch1, mode, ++ DetermineStubCallMode()); ++ __ Add64(kScratchReg, object, index); ++ __ Sd(value, MemOperand(kScratchReg)); ++ __ CheckPageFlag(object, scratch0, ++ MemoryChunk::kPointersFromHereAreInterestingMask, ne, ++ ool->entry()); ++ __ bind(ool->exit()); ++ break; ++ } ++ case kArchStackSlot: { ++ FrameOffset offset = ++ frame_access_state()->GetFrameOffset(i.InputInt32(0)); ++ Register base_reg = offset.from_stack_pointer() ? sp : fp; ++ __ Add64(i.OutputRegister(), base_reg, Operand(offset.offset())); ++ int alignment = i.InputInt32(1); ++ DCHECK(alignment == 0 || alignment == 4 || alignment == 8 || ++ alignment == 16); ++ if (FLAG_debug_code && alignment > 0) { ++ // Verify that the output_register is properly aligned ++ __ And(kScratchReg, i.OutputRegister(), ++ Operand(kSystemPointerSize - 1)); ++ __ Assert(eq, AbortReason::kAllocationIsNotDoubleAligned, kScratchReg, ++ Operand(zero_reg)); ++ } ++ if (alignment == 2 * kSystemPointerSize) { ++ Label done; ++ __ Add64(kScratchReg, base_reg, Operand(offset.offset())); ++ __ And(kScratchReg, kScratchReg, Operand(alignment - 1)); ++ __ BranchShort(&done, eq, kScratchReg, Operand(zero_reg)); ++ __ Add64(i.OutputRegister(), i.OutputRegister(), kSystemPointerSize); ++ __ bind(&done); ++ } else if (alignment > 2 * kSystemPointerSize) { ++ Label done; ++ __ Add64(kScratchReg, base_reg, Operand(offset.offset())); ++ __ And(kScratchReg, kScratchReg, Operand(alignment - 1)); ++ __ BranchShort(&done, eq, kScratchReg, Operand(zero_reg)); ++ __ li(kScratchReg2, alignment); ++ __ Sub64(kScratchReg2, kScratchReg2, Operand(kScratchReg)); ++ __ Add64(i.OutputRegister(), i.OutputRegister(), kScratchReg2); ++ __ bind(&done); ++ } ++ ++ break; ++ } ++ case kArchWordPoisonOnSpeculation: ++ __ And(i.OutputRegister(), i.InputRegister(0), ++ kSpeculationPoisonRegister); ++ break; ++ case kIeee754Float64Acos: ++ ASSEMBLE_IEEE754_UNOP(acos); ++ break; ++ case kIeee754Float64Acosh: ++ ASSEMBLE_IEEE754_UNOP(acosh); ++ break; ++ case kIeee754Float64Asin: ++ ASSEMBLE_IEEE754_UNOP(asin); ++ break; ++ case kIeee754Float64Asinh: ++ ASSEMBLE_IEEE754_UNOP(asinh); ++ break; ++ case kIeee754Float64Atan: ++ ASSEMBLE_IEEE754_UNOP(atan); ++ break; ++ case kIeee754Float64Atanh: ++ ASSEMBLE_IEEE754_UNOP(atanh); ++ break; ++ case kIeee754Float64Atan2: ++ ASSEMBLE_IEEE754_BINOP(atan2); ++ break; ++ case kIeee754Float64Cos: ++ ASSEMBLE_IEEE754_UNOP(cos); ++ break; ++ case kIeee754Float64Cosh: ++ ASSEMBLE_IEEE754_UNOP(cosh); ++ break; ++ case kIeee754Float64Cbrt: ++ ASSEMBLE_IEEE754_UNOP(cbrt); ++ break; ++ case kIeee754Float64Exp: ++ ASSEMBLE_IEEE754_UNOP(exp); ++ break; ++ case kIeee754Float64Expm1: ++ ASSEMBLE_IEEE754_UNOP(expm1); ++ break; ++ case kIeee754Float64Log: ++ ASSEMBLE_IEEE754_UNOP(log); ++ break; ++ case kIeee754Float64Log1p: ++ ASSEMBLE_IEEE754_UNOP(log1p); ++ break; ++ case kIeee754Float64Log2: ++ ASSEMBLE_IEEE754_UNOP(log2); ++ break; ++ case kIeee754Float64Log10: ++ ASSEMBLE_IEEE754_UNOP(log10); ++ break; ++ case kIeee754Float64Pow: ++ ASSEMBLE_IEEE754_BINOP(pow); ++ break; ++ case kIeee754Float64Sin: ++ ASSEMBLE_IEEE754_UNOP(sin); ++ break; ++ case kIeee754Float64Sinh: ++ ASSEMBLE_IEEE754_UNOP(sinh); ++ break; ++ case kIeee754Float64Tan: ++ ASSEMBLE_IEEE754_UNOP(tan); ++ break; ++ case kIeee754Float64Tanh: ++ ASSEMBLE_IEEE754_UNOP(tanh); ++ break; ++ case kRiscvAdd32: ++ __ Add32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvAdd64: ++ __ Add64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvAddOvf64: ++ __ AddOverflow64(i.OutputRegister(), i.InputRegister(0), ++ i.InputOperand(1), kScratchReg); ++ break; ++ case kRiscvSub32: ++ __ Sub32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvSub64: ++ __ Sub64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvSubOvf64: ++ __ SubOverflow64(i.OutputRegister(), i.InputRegister(0), ++ i.InputOperand(1), kScratchReg); ++ break; ++ case kRiscvMul32: ++ __ Mul32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvMulOvf32: ++ __ MulOverflow32(i.OutputRegister(), i.InputRegister(0), ++ i.InputOperand(1), kScratchReg); ++ break; ++ case kRiscvMulHigh32: ++ __ Mulh32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvMulHighU32: ++ __ Mulhu32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1), ++ kScratchReg, kScratchReg2); ++ break; ++ case kRiscvMulHigh64: ++ __ Mulh64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvDiv32: { ++ __ Div32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ // Set ouput to zero if divisor == 0 ++ __ LoadZeroIfConditionZero(i.OutputRegister(), i.InputRegister(1)); ++ break; ++ } ++ case kRiscvDivU32: { ++ __ Divu32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ // Set ouput to zero if divisor == 0 ++ __ LoadZeroIfConditionZero(i.OutputRegister(), i.InputRegister(1)); ++ break; ++ } ++ case kRiscvMod32: ++ __ Mod32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvModU32: ++ __ Modu32(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvMul64: ++ __ Mul64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvDiv64: { ++ __ Div64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ // Set ouput to zero if divisor == 0 ++ __ LoadZeroIfConditionZero(i.OutputRegister(), i.InputRegister(1)); ++ break; ++ } ++ case kRiscvDivU64: { ++ __ Divu64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ // Set ouput to zero if divisor == 0 ++ __ LoadZeroIfConditionZero(i.OutputRegister(), i.InputRegister(1)); ++ break; ++ } ++ case kRiscvMod64: ++ __ Mod64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvModU64: ++ __ Modu64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvAnd: ++ __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvAnd32: ++ __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ __ Sll32(i.OutputRegister(), i.OutputRegister(), 0x0); ++ break; ++ case kRiscvOr: ++ __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvOr32: ++ __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ __ Sll32(i.OutputRegister(), i.OutputRegister(), 0x0); ++ break; ++ case kRiscvNor: ++ if (instr->InputAt(1)->IsRegister()) { ++ __ Nor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ } else { ++ DCHECK_EQ(0, i.InputOperand(1).immediate()); ++ __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg); ++ } ++ break; ++ case kRiscvNor32: ++ if (instr->InputAt(1)->IsRegister()) { ++ __ Nor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ __ Sll32(i.OutputRegister(), i.OutputRegister(), 0x0); ++ } else { ++ DCHECK_EQ(0, i.InputOperand(1).immediate()); ++ __ Nor(i.OutputRegister(), i.InputRegister(0), zero_reg); ++ __ Sll32(i.OutputRegister(), i.OutputRegister(), 0x0); ++ } ++ break; ++ case kRiscvXor: ++ __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvXor32: ++ __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ __ Sll32(i.OutputRegister(), i.OutputRegister(), 0x0); ++ break; ++ case kRiscvClz32: ++ __ Clz32(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvClz64: ++ __ Clz64(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvCtz32: { ++ Register src = i.InputRegister(0); ++ Register dst = i.OutputRegister(); ++ __ Ctz32(dst, src); ++ } break; ++ case kRiscvCtz64: { ++ Register src = i.InputRegister(0); ++ Register dst = i.OutputRegister(); ++ __ Ctz64(dst, src); ++ } break; ++ case kRiscvPopcnt32: { ++ Register src = i.InputRegister(0); ++ Register dst = i.OutputRegister(); ++ __ Popcnt32(dst, src); ++ } break; ++ case kRiscvPopcnt64: { ++ Register src = i.InputRegister(0); ++ Register dst = i.OutputRegister(); ++ __ Popcnt64(dst, src); ++ } break; ++ case kRiscvShl32: ++ if (instr->InputAt(1)->IsRegister()) { ++ __ Sll32(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); ++ } else { ++ int64_t imm = i.InputOperand(1).immediate(); ++ __ Sll32(i.OutputRegister(), i.InputRegister(0), ++ static_cast(imm)); ++ } ++ break; ++ case kRiscvShr32: ++ if (instr->InputAt(1)->IsRegister()) { ++ __ Srl32(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); ++ } else { ++ int64_t imm = i.InputOperand(1).immediate(); ++ __ Srl32(i.OutputRegister(), i.InputRegister(0), ++ static_cast(imm)); ++ } ++ break; ++ case kRiscvSar32: ++ if (instr->InputAt(1)->IsRegister()) { ++ __ Sra32(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); ++ } else { ++ int64_t imm = i.InputOperand(1).immediate(); ++ __ Sra32(i.OutputRegister(), i.InputRegister(0), ++ static_cast(imm)); ++ } ++ break; ++ case kRiscvZeroExtendWord: { ++ __ ZeroExtendWord(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvSignExtendWord: { ++ __ SignExtendWord(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvShl64: ++ __ Sll64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvShr64: ++ __ Srl64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvSar64: ++ __ Sra64(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvRor32: ++ __ Ror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvRor64: ++ __ Dror(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1)); ++ break; ++ case kRiscvTst: ++ __ And(kScratchReg, i.InputRegister(0), i.InputOperand(1)); ++ // Pseudo-instruction used for cmp/branch. No opcode emitted here. ++ break; ++ case kRiscvCmp: ++ // Pseudo-instruction used for cmp/branch. No opcode emitted here. ++ break; ++ case kRiscvMov: ++ // TODO(plind): Should we combine mov/li like this, or use separate instr? ++ // - Also see x64 ASSEMBLE_BINOP & RegisterOrOperandType ++ if (HasRegisterInput(instr, 0)) { ++ __ Move(i.OutputRegister(), i.InputRegister(0)); ++ } else { ++ __ li(i.OutputRegister(), i.InputOperand(0)); ++ } ++ break; ++ ++ case kRiscvCmpS: { ++ FPURegister left = i.InputOrZeroSingleRegister(0); ++ FPURegister right = i.InputOrZeroSingleRegister(1); ++ bool predicate; ++ FPUCondition cc = ++ FlagsConditionToConditionCmpFPU(&predicate, instr->flags_condition()); ++ ++ if ((left == kDoubleRegZero || right == kDoubleRegZero) && ++ !__ IsSingleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0f); ++ } ++ // compare result set to kScratchReg ++ __ CompareF32(kScratchReg, cc, left, right); ++ } break; ++ case kRiscvAddS: ++ // TODO(plind): add special case: combine mult & add. ++ __ fadd_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvSubS: ++ __ fsub_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvMulS: ++ // TODO(plind): add special case: right op is -1.0, see arm port. ++ __ fmul_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvDivS: ++ __ fdiv_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvModS: { ++ // TODO(bmeurer): We should really get rid of this special instruction, ++ // and generate a CallAddress instruction instead. ++ FrameScope scope(tasm(), StackFrame::MANUAL); ++ __ PrepareCallCFunction(0, 2, kScratchReg); ++ __ MovToFloatParameters(i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ // TODO(balazs.kilvady): implement mod_two_floats_operation(isolate()) ++ __ CallCFunction(ExternalReference::mod_two_doubles_operation(), 0, 2); ++ // Move the result in the double result register. ++ __ MovFromFloatResult(i.OutputSingleRegister()); ++ break; ++ } ++ case kRiscvAbsS: ++ __ fabs_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); ++ break; ++ case kRiscvNegS: ++ __ Neg_s(i.OutputSingleRegister(), i.InputSingleRegister(0)); ++ break; ++ case kRiscvSqrtS: { ++ __ fsqrt_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); ++ break; ++ } ++ case kRiscvMaxS: ++ __ fmax_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvMinS: ++ __ fmin_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvCmpD: { ++ FPURegister left = i.InputOrZeroDoubleRegister(0); ++ FPURegister right = i.InputOrZeroDoubleRegister(1); ++ bool predicate; ++ FPUCondition cc = ++ FlagsConditionToConditionCmpFPU(&predicate, instr->flags_condition()); ++ if ((left == kDoubleRegZero || right == kDoubleRegZero) && ++ !__ IsDoubleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0); ++ } ++ // compare result set to kScratchReg ++ __ CompareF64(kScratchReg, cc, left, right); ++ } break; ++ case kRiscvAddD: ++ // TODO(plind): add special case: combine mult & add. ++ __ fadd_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvSubD: ++ __ fsub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvMulD: ++ // TODO(plind): add special case: right op is -1.0, see arm port. ++ __ fmul_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvDivD: ++ __ fdiv_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvModD: { ++ // TODO(bmeurer): We should really get rid of this special instruction, ++ // and generate a CallAddress instruction instead. ++ FrameScope scope(tasm(), StackFrame::MANUAL); ++ __ PrepareCallCFunction(0, 2, kScratchReg); ++ __ MovToFloatParameters(i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ __ CallCFunction(ExternalReference::mod_two_doubles_operation(), 0, 2); ++ // Move the result in the double result register. ++ __ MovFromFloatResult(i.OutputDoubleRegister()); ++ break; ++ } ++ case kRiscvAbsD: ++ __ fabs_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvNegD: ++ __ Neg_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvSqrtD: { ++ __ fsqrt_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); ++ break; ++ } ++ case kRiscvMaxD: ++ __ fmax_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvMinD: ++ __ fmin_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ i.InputDoubleRegister(1)); ++ break; ++ case kRiscvFloat64RoundDown: { ++ __ Floor_d_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat32RoundDown: { ++ __ Floor_s_s(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat64RoundTruncate: { ++ __ Trunc_d_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat32RoundTruncate: { ++ __ Trunc_s_s(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat64RoundUp: { ++ __ Ceil_d_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat32RoundUp: { ++ __ Ceil_s_s(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat64RoundTiesEven: { ++ __ Round_d_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat32RoundTiesEven: { ++ __ Round_s_s(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ kScratchDoubleReg); ++ break; ++ } ++ case kRiscvFloat32Max: { ++ __ Float32Max(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ i.InputSingleRegister(1)); ++ break; ++ } ++ case kRiscvFloat64Max: { ++ __ Float64Max(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ i.InputSingleRegister(1)); ++ break; ++ } ++ case kRiscvFloat32Min: { ++ __ Float32Min(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ i.InputSingleRegister(1)); ++ break; ++ } ++ case kRiscvFloat64Min: { ++ __ Float64Min(i.OutputSingleRegister(), i.InputSingleRegister(0), ++ i.InputSingleRegister(1)); ++ break; ++ } ++ case kRiscvFloat64SilenceNaN: ++ __ FPUCanonicalizeNaN(i.OutputDoubleRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvCvtSD: ++ __ fcvt_s_d(i.OutputSingleRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvCvtDS: ++ __ fcvt_d_s(i.OutputDoubleRegister(), i.InputSingleRegister(0)); ++ break; ++ case kRiscvCvtDW: { ++ __ fcvt_d_w(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtSW: { ++ __ fcvt_s_w(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtSUw: { ++ __ Cvt_s_uw(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtSL: { ++ __ fcvt_s_l(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtDL: { ++ __ fcvt_d_l(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtDUw: { ++ __ Cvt_d_uw(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtDUl: { ++ __ Cvt_d_ul(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvCvtSUl: { ++ __ Cvt_s_ul(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ } ++ case kRiscvFloorWD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Floor_w_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvCeilWD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Ceil_w_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvRoundWD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Round_w_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncWD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_w_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvFloorWS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Floor_w_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvCeilWS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Ceil_w_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvRoundWS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Round_w_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncWS: { ++ Label done; ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_w_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ ++ // On RISCV, if the input value exceeds INT32_MAX, the result of fcvt ++ // is INT32_MAX. Note that, since INT32_MAX means the lower 31-bits are ++ // all 1s, INT32_MAX cannot be represented precisely as a float, so an ++ // fcvt result of INT32_MAX always indicate overflow. ++ // ++ // In wasm_compiler, to detect overflow in converting a FP value, fval, to ++ // integer, V8 checks whether I2F(F2I(fval)) equals fval. However, if fval ++ // == INT32_MAX+1, the value of I2F(F2I(fval)) happens to be fval. So, ++ // INT32_MAX is not a good value to indicate overflow. Instead, we will ++ // use INT32_MIN as the converted result of an out-of-range FP value, ++ // exploiting the fact that INT32_MAX+1 is INT32_MIN. ++ // ++ // If the result of conversion overflow, the result will be set to ++ // INT32_MIN. Here we detect overflow by testing whether output + 1 < ++ // output (i.e., kScratchReg < output) ++ __ Add32(kScratchReg, i.OutputRegister(), 1); ++ __ Branch(&done, lt, i.OutputRegister(), Operand(kScratchReg)); ++ __ Move(i.OutputRegister(), kScratchReg); ++ __ bind(&done); ++ break; ++ } ++ case kRiscvTruncLS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_l_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncLD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_l_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncUwD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_uw_d(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncUwS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_uw_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ ++ // On RISCV, if the input value exceeds UINT32_MAX, the result of fcvt ++ // is UINT32_MAX. Note that, since UINT32_MAX means all 32-bits are 1s, ++ // UINT32_MAX cannot be represented precisely as float, so an fcvt result ++ // of UINT32_MAX always indicates overflow. ++ // ++ // In wasm_compiler.cc, to detect overflow in converting a FP value, fval, ++ // to integer, V8 checks whether I2F(F2I(fval)) equals fval. However, if ++ // fval == UINT32_MAX+1, the value of I2F(F2I(fval)) happens to be fval. ++ // So, UINT32_MAX is not a good value to indicate overflow. Instead, we ++ // will use 0 as the converted result of an out-of-range FP value, ++ // exploiting the fact that UINT32_MAX+1 is 0. ++ __ Add32(kScratchReg, i.OutputRegister(), 1); ++ // Set ouput to zero if result overflows (i.e., UINT32_MAX) ++ __ LoadZeroIfConditionZero(i.OutputRegister(), kScratchReg); ++ break; ++ } ++ case kRiscvTruncUlS: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_ul_s(i.OutputRegister(), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvTruncUlD: { ++ Register result = instr->OutputCount() > 1 ? i.OutputRegister(1) : no_reg; ++ __ Trunc_ul_d(i.OutputRegister(0), i.InputDoubleRegister(0), result); ++ break; ++ } ++ case kRiscvBitcastDL: ++ __ fmv_x_d(i.OutputRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvBitcastLD: ++ __ fmv_d_x(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvBitcastInt32ToFloat32: ++ __ fmv_w_x(i.OutputDoubleRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvBitcastFloat32ToInt32: ++ __ fmv_x_w(i.OutputRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvFloat64ExtractLowWord32: ++ __ ExtractLowWordFromF64(i.OutputRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvFloat64ExtractHighWord32: ++ __ ExtractHighWordFromF64(i.OutputRegister(), i.InputDoubleRegister(0)); ++ break; ++ case kRiscvFloat64InsertLowWord32: ++ __ InsertLowWordF64(i.OutputDoubleRegister(), i.InputRegister(1)); ++ break; ++ case kRiscvFloat64InsertHighWord32: ++ __ InsertHighWordF64(i.OutputDoubleRegister(), i.InputRegister(1)); ++ break; ++ // ... more basic instructions ... ++ ++ case kRiscvSignExtendByte: ++ __ SignExtendByte(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvSignExtendShort: ++ __ SignExtendShort(i.OutputRegister(), i.InputRegister(0)); ++ break; ++ case kRiscvLbu: ++ __ Lbu(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvLb: ++ __ Lb(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvSb: ++ __ Sb(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvLhu: ++ __ Lhu(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvUlhu: ++ __ Ulhu(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvLh: ++ __ Lh(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvUlh: ++ __ Ulh(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvSh: ++ __ Sh(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvUsh: ++ __ Ush(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvLw: ++ __ Lw(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvUlw: ++ __ Ulw(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvLwu: ++ __ Lwu(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvUlwu: ++ __ Ulwu(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvLd: ++ __ Ld(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvUld: ++ __ Uld(i.OutputRegister(), i.MemoryOperand()); ++ EmitWordLoadPoisoningIfNeeded(this, opcode, instr, i); ++ break; ++ case kRiscvSw: ++ __ Sw(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvUsw: ++ __ Usw(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvSd: ++ __ Sd(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvUsd: ++ __ Usd(i.InputOrZeroRegister(2), i.MemoryOperand()); ++ break; ++ case kRiscvLoadFloat: { ++ __ LoadFloat(i.OutputSingleRegister(), i.MemoryOperand()); ++ break; ++ } ++ case kRiscvULoadFloat: { ++ __ ULoadFloat(i.OutputSingleRegister(), i.MemoryOperand(), kScratchReg); ++ break; ++ } ++ case kRiscvStoreFloat: { ++ size_t index = 0; ++ MemOperand operand = i.MemoryOperand(&index); ++ FPURegister ft = i.InputOrZeroSingleRegister(index); ++ if (ft == kDoubleRegZero && !__ IsSingleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0f); ++ } ++ __ StoreFloat(ft, operand); ++ break; ++ } ++ case kRiscvUStoreFloat: { ++ size_t index = 0; ++ MemOperand operand = i.MemoryOperand(&index); ++ FPURegister ft = i.InputOrZeroSingleRegister(index); ++ if (ft == kDoubleRegZero && !__ IsSingleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0f); ++ } ++ __ UStoreFloat(ft, operand, kScratchReg); ++ break; ++ } ++ case kRiscvLoadDouble: ++ __ LoadDouble(i.OutputDoubleRegister(), i.MemoryOperand()); ++ break; ++ case kRiscvULoadDouble: ++ __ ULoadDouble(i.OutputDoubleRegister(), i.MemoryOperand(), kScratchReg); ++ break; ++ case kRiscvStoreDouble: { ++ FPURegister ft = i.InputOrZeroDoubleRegister(2); ++ if (ft == kDoubleRegZero && !__ IsDoubleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0); ++ } ++ __ StoreDouble(ft, i.MemoryOperand()); ++ break; ++ } ++ case kRiscvUStoreDouble: { ++ FPURegister ft = i.InputOrZeroDoubleRegister(2); ++ if (ft == kDoubleRegZero && !__ IsDoubleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0); ++ } ++ __ UStoreDouble(ft, i.MemoryOperand(), kScratchReg); ++ break; ++ } ++ case kRiscvSync: { ++ __ sync(); ++ break; ++ } ++ case kRiscvPush: ++ if (instr->InputAt(0)->IsFPRegister()) { ++ __ StoreDouble(i.InputDoubleRegister(0), MemOperand(sp, -kDoubleSize)); ++ __ Sub32(sp, sp, Operand(kDoubleSize)); ++ frame_access_state()->IncreaseSPDelta(kDoubleSize / kSystemPointerSize); ++ } else { ++ __ Push(i.InputRegister(0)); ++ frame_access_state()->IncreaseSPDelta(1); ++ } ++ break; ++ case kRiscvPeek: { ++ // The incoming value is 0-based, but we need a 1-based value. ++ int reverse_slot = i.InputInt32(0) + 1; ++ int offset = ++ FrameSlotToFPOffset(frame()->GetTotalFrameSlotCount() - reverse_slot); ++ if (instr->OutputAt(0)->IsFPRegister()) { ++ LocationOperand* op = LocationOperand::cast(instr->OutputAt(0)); ++ if (op->representation() == MachineRepresentation::kFloat64) { ++ __ LoadDouble(i.OutputDoubleRegister(), MemOperand(fp, offset)); ++ } else { ++ DCHECK_EQ(op->representation(), MachineRepresentation::kFloat32); ++ __ LoadFloat( ++ i.OutputSingleRegister(0), ++ MemOperand(fp, offset + kLessSignificantWordInDoublewordOffset)); ++ } ++ } else { ++ __ Ld(i.OutputRegister(0), MemOperand(fp, offset)); ++ } ++ break; ++ } ++ case kRiscvStackClaim: { ++ __ Sub64(sp, sp, Operand(i.InputInt32(0))); ++ frame_access_state()->IncreaseSPDelta(i.InputInt32(0) / ++ kSystemPointerSize); ++ break; ++ } ++ case kRiscvStoreToStackSlot: { ++ if (instr->InputAt(0)->IsFPRegister()) { ++ if (instr->InputAt(0)->IsSimd128Register()) { ++ UNREACHABLE(); ++ } else { ++ __ StoreDouble(i.InputDoubleRegister(0), ++ MemOperand(sp, i.InputInt32(1))); ++ } ++ } else { ++ __ Sd(i.InputRegister(0), MemOperand(sp, i.InputInt32(1))); ++ } ++ break; ++ } ++ case kRiscvByteSwap64: { ++ __ ByteSwap(i.OutputRegister(0), i.InputRegister(0), 8); ++ break; ++ } ++ case kRiscvByteSwap32: { ++ __ ByteSwap(i.OutputRegister(0), i.InputRegister(0), 4); ++ break; ++ } ++ case kWord32AtomicLoadInt8: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lb); ++ break; ++ case kWord32AtomicLoadUint8: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lbu); ++ break; ++ case kWord32AtomicLoadInt16: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lh); ++ break; ++ case kWord32AtomicLoadUint16: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lhu); ++ break; ++ case kWord32AtomicLoadWord32: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lw); ++ break; ++ case kRiscvWord64AtomicLoadUint8: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lbu); ++ break; ++ case kRiscvWord64AtomicLoadUint16: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lhu); ++ break; ++ case kRiscvWord64AtomicLoadUint32: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Lwu); ++ break; ++ case kRiscvWord64AtomicLoadUint64: ++ ASSEMBLE_ATOMIC_LOAD_INTEGER(Ld); ++ break; ++ case kWord32AtomicStoreWord8: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sb); ++ break; ++ case kWord32AtomicStoreWord16: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sh); ++ break; ++ case kWord32AtomicStoreWord32: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sw); ++ break; ++ case kRiscvWord64AtomicStoreWord8: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sb); ++ break; ++ case kRiscvWord64AtomicStoreWord16: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sh); ++ break; ++ case kRiscvWord64AtomicStoreWord32: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sw); ++ break; ++ case kRiscvWord64AtomicStoreWord64: ++ ASSEMBLE_ATOMIC_STORE_INTEGER(Sd); ++ break; ++ case kWord32AtomicExchangeInt8: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Ll, Sc, true, 8, 32); ++ break; ++ case kWord32AtomicExchangeUint8: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Ll, Sc, false, 8, 32); ++ break; ++ case kWord32AtomicExchangeInt16: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Ll, Sc, true, 16, 32); ++ break; ++ case kWord32AtomicExchangeUint16: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Ll, Sc, false, 16, 32); ++ break; ++ case kWord32AtomicExchangeWord32: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(Ll, Sc); ++ break; ++ case kRiscvWord64AtomicExchangeUint8: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 8, 64); ++ break; ++ case kRiscvWord64AtomicExchangeUint16: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 16, 64); ++ break; ++ case kRiscvWord64AtomicExchangeUint32: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 32, 64); ++ break; ++ case kRiscvWord64AtomicExchangeUint64: ++ ASSEMBLE_ATOMIC_EXCHANGE_INTEGER(Lld, Scd); ++ break; ++ case kWord32AtomicCompareExchangeInt8: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Ll, Sc, true, 8, 32); ++ break; ++ case kWord32AtomicCompareExchangeUint8: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Ll, Sc, false, 8, 32); ++ break; ++ case kWord32AtomicCompareExchangeInt16: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Ll, Sc, true, 16, 32); ++ break; ++ case kWord32AtomicCompareExchangeUint16: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Ll, Sc, false, 16, 32); ++ break; ++ case kWord32AtomicCompareExchangeWord32: ++ __ Sll32(i.InputRegister(2), i.InputRegister(2), 0); ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(Ll, Sc); ++ break; ++ case kRiscvWord64AtomicCompareExchangeUint8: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 8, 64); ++ break; ++ case kRiscvWord64AtomicCompareExchangeUint16: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 16, 64); ++ break; ++ case kRiscvWord64AtomicCompareExchangeUint32: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT(Lld, Scd, false, 32, 64); ++ break; ++ case kRiscvWord64AtomicCompareExchangeUint64: ++ ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(Lld, Scd); ++ break; ++#define ATOMIC_BINOP_CASE(op, inst) \ ++ case kWord32Atomic##op##Int8: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Ll, Sc, true, 8, inst, 32); \ ++ break; \ ++ case kWord32Atomic##op##Uint8: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Ll, Sc, false, 8, inst, 32); \ ++ break; \ ++ case kWord32Atomic##op##Int16: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Ll, Sc, true, 16, inst, 32); \ ++ break; \ ++ case kWord32Atomic##op##Uint16: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Ll, Sc, false, 16, inst, 32); \ ++ break; \ ++ case kWord32Atomic##op##Word32: \ ++ ASSEMBLE_ATOMIC_BINOP(Ll, Sc, inst); \ ++ break; ++ ATOMIC_BINOP_CASE(Add, Add32) ++ ATOMIC_BINOP_CASE(Sub, Sub32) ++ ATOMIC_BINOP_CASE(And, And) ++ ATOMIC_BINOP_CASE(Or, Or) ++ ATOMIC_BINOP_CASE(Xor, Xor) ++#undef ATOMIC_BINOP_CASE ++#define ATOMIC_BINOP_CASE(op, inst) \ ++ case kRiscvWord64Atomic##op##Uint8: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Lld, Scd, false, 8, inst, 64); \ ++ break; \ ++ case kRiscvWord64Atomic##op##Uint16: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Lld, Scd, false, 16, inst, 64); \ ++ break; \ ++ case kRiscvWord64Atomic##op##Uint32: \ ++ ASSEMBLE_ATOMIC_BINOP_EXT(Lld, Scd, false, 32, inst, 64); \ ++ break; \ ++ case kRiscvWord64Atomic##op##Uint64: \ ++ ASSEMBLE_ATOMIC_BINOP(Lld, Scd, inst); \ ++ break; ++ ATOMIC_BINOP_CASE(Add, Add64) ++ ATOMIC_BINOP_CASE(Sub, Sub64) ++ ATOMIC_BINOP_CASE(And, And) ++ ATOMIC_BINOP_CASE(Or, Or) ++ ATOMIC_BINOP_CASE(Xor, Xor) ++#undef ATOMIC_BINOP_CASE ++ case kRiscvAssertEqual: ++ __ Assert(eq, static_cast(i.InputOperand(2).immediate()), ++ i.InputRegister(0), Operand(i.InputRegister(1))); ++ break; ++ ++ default: ++ UNIMPLEMENTED(); ++ } ++ return kSuccess; ++} // NOLINT(readability/fn_size) ++ ++#define UNSUPPORTED_COND(opcode, condition) \ ++ StdoutStream{} << "Unsupported " << #opcode << " condition: \"" << condition \ ++ << "\""; \ ++ UNIMPLEMENTED(); ++ ++void AssembleBranchToLabels(CodeGenerator* gen, TurboAssembler* tasm, ++ Instruction* instr, FlagsCondition condition, ++ Label* tlabel, Label* flabel, bool fallthru) { ++#undef __ ++#define __ tasm-> ++ RiscvOperandConverter i(gen, instr); ++ ++ Condition cc = kNoCondition; ++ // RISC-V does not have condition code flags, so compare and branch are ++ // implemented differently than on the other arch's. The compare operations ++ // emit riscv64 pseudo-instructions, which are handled here by branch ++ // instructions that do the actual comparison. Essential that the input ++ // registers to compare pseudo-op are not modified before this branch op, as ++ // they are tested here. ++ ++ if (instr->arch_opcode() == kRiscvTst) { ++ cc = FlagsConditionToConditionTst(condition); ++ __ Branch(tlabel, cc, kScratchReg, Operand(zero_reg)); ++ } else if (instr->arch_opcode() == kRiscvAdd64 || ++ instr->arch_opcode() == kRiscvSub64) { ++ cc = FlagsConditionToConditionOvf(condition); ++ __ Sra64(kScratchReg, i.OutputRegister(), 32); ++ __ Sra64(kScratchReg2, i.OutputRegister(), 31); ++ __ Branch(tlabel, cc, kScratchReg2, Operand(kScratchReg)); ++ } else if (instr->arch_opcode() == kRiscvAddOvf64 || ++ instr->arch_opcode() == kRiscvSubOvf64) { ++ switch (condition) { ++ // Overflow occurs if overflow register is negative ++ case kOverflow: ++ __ Branch(tlabel, lt, kScratchReg, Operand(zero_reg)); ++ break; ++ case kNotOverflow: ++ __ Branch(tlabel, ge, kScratchReg, Operand(zero_reg)); ++ break; ++ default: ++ UNSUPPORTED_COND(instr->arch_opcode(), condition); ++ break; ++ } ++ } else if (instr->arch_opcode() == kRiscvMulOvf32) { ++ // Overflow occurs if overflow register is not zero ++ switch (condition) { ++ case kOverflow: ++ __ Branch(tlabel, ne, kScratchReg, Operand(zero_reg)); ++ break; ++ case kNotOverflow: ++ __ Branch(tlabel, eq, kScratchReg, Operand(zero_reg)); ++ break; ++ default: ++ UNSUPPORTED_COND(kRiscvMulOvf32, condition); ++ break; ++ } ++ } else if (instr->arch_opcode() == kRiscvCmp) { ++ cc = FlagsConditionToConditionCmp(condition); ++ __ Branch(tlabel, cc, i.InputRegister(0), i.InputOperand(1)); ++ } else if (instr->arch_opcode() == kArchStackPointerGreaterThan) { ++ cc = FlagsConditionToConditionCmp(condition); ++ Register lhs_register = sp; ++ uint32_t offset; ++ if (gen->ShouldApplyOffsetToStackCheck(instr, &offset)) { ++ lhs_register = i.TempRegister(0); ++ __ Sub64(lhs_register, sp, offset); ++ } ++ __ Branch(tlabel, cc, lhs_register, Operand(i.InputRegister(0))); ++ } else if (instr->arch_opcode() == kRiscvCmpS || ++ instr->arch_opcode() == kRiscvCmpD) { ++ bool predicate; ++ FlagsConditionToConditionCmpFPU(&predicate, condition); ++ // floating-point compare result is set in kScratchReg ++ if (predicate) { ++ __ BranchTrueF(kScratchReg, tlabel); ++ } else { ++ __ BranchFalseF(kScratchReg, tlabel); ++ } ++ } else { ++ PrintF("AssembleArchBranch Unimplemented arch_opcode: %d\n", ++ instr->arch_opcode()); ++ UNIMPLEMENTED(); ++ } ++ if (!fallthru) __ Branch(flabel); // no fallthru to flabel. ++#undef __ ++#define __ tasm()-> ++} ++ ++// Assembles branches after an instruction. ++void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) { ++ Label* tlabel = branch->true_label; ++ Label* flabel = branch->false_label; ++ ++ AssembleBranchToLabels(this, tasm(), instr, branch->condition, tlabel, flabel, ++ branch->fallthru); ++} ++ ++void CodeGenerator::AssembleBranchPoisoning(FlagsCondition condition, ++ Instruction* instr) { ++ // TODO(jarin) Handle float comparisons (kUnordered[Not]Equal). ++ if (condition == kUnorderedEqual || condition == kUnorderedNotEqual) { ++ return; ++ } ++ ++ RiscvOperandConverter i(this, instr); ++ condition = NegateFlagsCondition(condition); ++ ++ switch (instr->arch_opcode()) { ++ case kRiscvCmp: { ++ __ CompareI(kScratchReg, i.InputRegister(0), i.InputOperand(1), ++ FlagsConditionToConditionCmp(condition)); ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, kScratchReg); ++ } ++ return; ++ case kRiscvTst: { ++ switch (condition) { ++ case kEqual: ++ __ LoadZeroIfConditionZero(kSpeculationPoisonRegister, kScratchReg); ++ break; ++ case kNotEqual: ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, ++ kScratchReg); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++ return; ++ case kRiscvAdd64: ++ case kRiscvSub64: { ++ // Check for overflow creates 1 or 0 for result. ++ __ Srl64(kScratchReg, i.OutputRegister(), 63); ++ __ Srl32(kScratchReg2, i.OutputRegister(), 31); ++ __ Xor(kScratchReg2, kScratchReg, kScratchReg2); ++ switch (condition) { ++ case kOverflow: ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, ++ kScratchReg2); ++ break; ++ case kNotOverflow: ++ __ LoadZeroIfConditionZero(kSpeculationPoisonRegister, kScratchReg2); ++ break; ++ default: ++ UNSUPPORTED_COND(instr->arch_opcode(), condition); ++ } ++ } ++ return; ++ case kRiscvAddOvf64: ++ case kRiscvSubOvf64: { ++ // Overflow occurs if overflow register is negative ++ __ Slt(kScratchReg2, kScratchReg, zero_reg); ++ switch (condition) { ++ case kOverflow: ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, ++ kScratchReg2); ++ break; ++ case kNotOverflow: ++ __ LoadZeroIfConditionZero(kSpeculationPoisonRegister, kScratchReg2); ++ break; ++ default: ++ UNSUPPORTED_COND(instr->arch_opcode(), condition); ++ } ++ } ++ return; ++ case kRiscvMulOvf32: { ++ // Overflow occurs if overflow register is not zero ++ switch (condition) { ++ case kOverflow: ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, ++ kScratchReg); ++ break; ++ case kNotOverflow: ++ __ LoadZeroIfConditionZero(kSpeculationPoisonRegister, kScratchReg); ++ break; ++ default: ++ UNSUPPORTED_COND(instr->arch_opcode(), condition); ++ } ++ } ++ return; ++ case kRiscvCmpS: ++ case kRiscvCmpD: { ++ bool predicate; ++ FlagsConditionToConditionCmpFPU(&predicate, condition); ++ if (predicate) { ++ __ LoadZeroIfConditionNotZero(kSpeculationPoisonRegister, kScratchReg); ++ } else { ++ __ LoadZeroIfConditionZero(kSpeculationPoisonRegister, kScratchReg); ++ } ++ } ++ return; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++#undef UNSUPPORTED_COND ++ ++void CodeGenerator::AssembleArchDeoptBranch(Instruction* instr, ++ BranchInfo* branch) { ++ AssembleArchBranch(instr, branch); ++} ++ ++void CodeGenerator::AssembleArchJump(RpoNumber target) { ++ if (!IsNextInAssemblyOrder(target)) __ Branch(GetLabel(target)); ++} ++ ++void CodeGenerator::AssembleArchTrap(Instruction* instr, ++ FlagsCondition condition) { ++ class OutOfLineTrap final : public OutOfLineCode { ++ public: ++ OutOfLineTrap(CodeGenerator* gen, Instruction* instr) ++ : OutOfLineCode(gen), instr_(instr), gen_(gen) {} ++ void Generate() final { ++ RiscvOperandConverter i(gen_, instr_); ++ TrapId trap_id = ++ static_cast(i.InputInt32(instr_->InputCount() - 1)); ++ GenerateCallToTrap(trap_id); ++ } ++ ++ private: ++ void GenerateCallToTrap(TrapId trap_id) { ++ if (trap_id == TrapId::kInvalid) { ++ // We cannot test calls to the runtime in cctest/test-run-wasm. ++ // Therefore we emit a call to C here instead of a call to the runtime. ++ // We use the context register as the scratch register, because we do ++ // not have a context here. ++ __ PrepareCallCFunction(0, 0, cp); ++ __ CallCFunction( ++ ExternalReference::wasm_call_trap_callback_for_testing(), 0); ++ __ LeaveFrame(StackFrame::WASM); ++ auto call_descriptor = gen_->linkage()->GetIncomingDescriptor(); ++ int pop_count = ++ static_cast(call_descriptor->StackParameterCount()); ++ pop_count += (pop_count & 1); // align ++ __ Drop(pop_count); ++ __ Ret(); ++ } else { ++ gen_->AssembleSourcePosition(instr_); ++ // A direct call to a wasm runtime stub defined in this module. ++ // Just encode the stub index. This will be patched when the code ++ // is added to the native module and copied into wasm code space. ++ __ Call(static_cast
(trap_id), RelocInfo::WASM_STUB_CALL); ++ ReferenceMap* reference_map = ++ gen_->zone()->New(gen_->zone()); ++ gen_->RecordSafepoint(reference_map, Safepoint::kNoLazyDeopt); ++ if (FLAG_debug_code) { ++ __ stop(); ++ } ++ } ++ } ++ Instruction* instr_; ++ CodeGenerator* gen_; ++ }; ++ auto ool = zone()->New(this, instr); ++ Label* tlabel = ool->entry(); ++ AssembleBranchToLabels(this, tasm(), instr, condition, tlabel, nullptr, true); ++} ++ ++// Assembles boolean materializations after an instruction. ++void CodeGenerator::AssembleArchBoolean(Instruction* instr, ++ FlagsCondition condition) { ++ RiscvOperandConverter i(this, instr); ++ ++ // Materialize a full 32-bit 1 or 0 value. The result register is always the ++ // last output of the instruction. ++ DCHECK_NE(0u, instr->OutputCount()); ++ Register result = i.OutputRegister(instr->OutputCount() - 1); ++ Condition cc = kNoCondition; ++ // RISC-V does not have condition code flags, so compare and branch are ++ // implemented differently than on the other arch's. The compare operations ++ // emit riscv64 pseudo-instructions, which are checked and handled here. ++ ++ if (instr->arch_opcode() == kRiscvTst) { ++ cc = FlagsConditionToConditionTst(condition); ++ if (cc == eq) { ++ __ Sltu(result, kScratchReg, 1); ++ } else { ++ __ Sltu(result, zero_reg, kScratchReg); ++ } ++ return; ++ } else if (instr->arch_opcode() == kRiscvAdd64 || ++ instr->arch_opcode() == kRiscvSub64) { ++ cc = FlagsConditionToConditionOvf(condition); ++ // Check for overflow creates 1 or 0 for result. ++ __ Srl64(kScratchReg, i.OutputRegister(), 63); ++ __ Srl32(kScratchReg2, i.OutputRegister(), 31); ++ __ Xor(result, kScratchReg, kScratchReg2); ++ if (cc == eq) // Toggle result for not overflow. ++ __ Xor(result, result, 1); ++ return; ++ } else if (instr->arch_opcode() == kRiscvAddOvf64 || ++ instr->arch_opcode() == kRiscvSubOvf64) { ++ // Overflow occurs if overflow register is negative ++ __ Slt(result, kScratchReg, zero_reg); ++ } else if (instr->arch_opcode() == kRiscvMulOvf32) { ++ // Overflow occurs if overflow register is not zero ++ __ Sgtu(result, kScratchReg, zero_reg); ++ } else if (instr->arch_opcode() == kRiscvCmp) { ++ cc = FlagsConditionToConditionCmp(condition); ++ switch (cc) { ++ case eq: ++ case ne: { ++ Register left = i.InputRegister(0); ++ Operand right = i.InputOperand(1); ++ if (instr->InputAt(1)->IsImmediate()) { ++ if (is_int12(-right.immediate())) { ++ if (right.immediate() == 0) { ++ if (cc == eq) { ++ __ Sltu(result, left, 1); ++ } else { ++ __ Sltu(result, zero_reg, left); ++ } ++ } else { ++ __ Add64(result, left, Operand(-right.immediate())); ++ if (cc == eq) { ++ __ Sltu(result, result, 1); ++ } else { ++ __ Sltu(result, zero_reg, result); ++ } ++ } ++ } else { ++ if (is_uint12(right.immediate())) { ++ __ Xor(result, left, right); ++ } else { ++ __ li(kScratchReg, right); ++ __ Xor(result, left, kScratchReg); ++ } ++ if (cc == eq) { ++ __ Sltu(result, result, 1); ++ } else { ++ __ Sltu(result, zero_reg, result); ++ } ++ } ++ } else { ++ __ Xor(result, left, right); ++ if (cc == eq) { ++ __ Sltu(result, result, 1); ++ } else { ++ __ Sltu(result, zero_reg, result); ++ } ++ } ++ } break; ++ case lt: ++ case ge: { ++ Register left = i.InputRegister(0); ++ Operand right = i.InputOperand(1); ++ __ Slt(result, left, right); ++ if (cc == ge) { ++ __ Xor(result, result, 1); ++ } ++ } break; ++ case gt: ++ case le: { ++ Register left = i.InputRegister(1); ++ Operand right = i.InputOperand(0); ++ __ Slt(result, left, right); ++ if (cc == le) { ++ __ Xor(result, result, 1); ++ } ++ } break; ++ case Uless: ++ case Ugreater_equal: { ++ Register left = i.InputRegister(0); ++ Operand right = i.InputOperand(1); ++ __ Sltu(result, left, right); ++ if (cc == Ugreater_equal) { ++ __ Xor(result, result, 1); ++ } ++ } break; ++ case Ugreater: ++ case Uless_equal: { ++ Register left = i.InputRegister(1); ++ Operand right = i.InputOperand(0); ++ __ Sltu(result, left, right); ++ if (cc == Uless_equal) { ++ __ Xor(result, result, 1); ++ } ++ } break; ++ default: ++ UNREACHABLE(); ++ } ++ return; ++ } else if (instr->arch_opcode() == kRiscvCmpD || ++ instr->arch_opcode() == kRiscvCmpS) { ++ FPURegister left = i.InputOrZeroDoubleRegister(0); ++ FPURegister right = i.InputOrZeroDoubleRegister(1); ++ if ((instr->arch_opcode() == kRiscvCmpD) && ++ (left == kDoubleRegZero || right == kDoubleRegZero) && ++ !__ IsDoubleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0); ++ } else if ((instr->arch_opcode() == kRiscvCmpS) && ++ (left == kDoubleRegZero || right == kDoubleRegZero) && ++ !__ IsSingleZeroRegSet()) { ++ __ LoadFPRImmediate(kDoubleRegZero, 0.0f); ++ } ++ bool predicate; ++ FlagsConditionToConditionCmpFPU(&predicate, condition); ++ // RISCV compare returns 0 or 1, do nothing when predicate; otherwise ++ // toggle kScratchReg (i.e., 0 -> 1, 1 -> 0) ++ if (predicate) { ++ __ Move(result, kScratchReg); ++ } else { ++ __ Xor(result, kScratchReg, 1); ++ } ++ return; ++ } else { ++ PrintF("AssembleArchBranch Unimplemented arch_opcode is : %d\n", ++ instr->arch_opcode()); ++ TRACE_UNIMPL(); ++ UNIMPLEMENTED(); ++ } ++} ++ ++void CodeGenerator::AssembleArchBinarySearchSwitch(Instruction* instr) { ++ RiscvOperandConverter i(this, instr); ++ Register input = i.InputRegister(0); ++ std::vector> cases; ++ for (size_t index = 2; index < instr->InputCount(); index += 2) { ++ cases.push_back({i.InputInt32(index + 0), GetLabel(i.InputRpo(index + 1))}); ++ } ++ AssembleArchBinarySearchSwitchRange(input, i.InputRpo(1), cases.data(), ++ cases.data() + cases.size()); ++} ++ ++void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) { ++ RiscvOperandConverter i(this, instr); ++ Register input = i.InputRegister(0); ++ size_t const case_count = instr->InputCount() - 2; ++ ++ __ Branch(GetLabel(i.InputRpo(1)), Ugreater_equal, input, ++ Operand(case_count)); ++ __ GenerateSwitchTable(input, case_count, [&i, this](size_t index) { ++ return GetLabel(i.InputRpo(index + 2)); ++ }); ++} ++ ++void CodeGenerator::FinishFrame(Frame* frame) { ++ auto call_descriptor = linkage()->GetIncomingDescriptor(); ++ ++ const RegList saves_fpu = call_descriptor->CalleeSavedFPRegisters(); ++ if (saves_fpu != 0) { ++ int count = base::bits::CountPopulation(saves_fpu); ++ DCHECK_EQ(kNumCalleeSavedFPU, count); ++ frame->AllocateSavedCalleeRegisterSlots(count * ++ (kDoubleSize / kSystemPointerSize)); ++ } ++ ++ const RegList saves = call_descriptor->CalleeSavedRegisters(); ++ if (saves != 0) { ++ int count = base::bits::CountPopulation(saves); ++ DCHECK_EQ(kNumCalleeSaved, count + 1); ++ frame->AllocateSavedCalleeRegisterSlots(count); ++ } ++} ++ ++void CodeGenerator::AssembleConstructFrame() { ++ auto call_descriptor = linkage()->GetIncomingDescriptor(); ++ ++ if (frame_access_state()->has_frame()) { ++ if (call_descriptor->IsCFunctionCall()) { ++ if (info()->GetOutputStackFrameType() == StackFrame::C_WASM_ENTRY) { ++ __ StubPrologue(StackFrame::C_WASM_ENTRY); ++ // Reserve stack space for saving the c_entry_fp later. ++ __ Sub64(sp, sp, Operand(kSystemPointerSize)); ++ } else { ++ __ Push(ra, fp); ++ __ Move(fp, sp); ++ } ++ } else if (call_descriptor->IsJSFunctionCall()) { ++ __ Prologue(); ++ } else { ++ __ StubPrologue(info()->GetOutputStackFrameType()); ++ if (call_descriptor->IsWasmFunctionCall()) { ++ __ Push(kWasmInstanceRegister); ++ } else if (call_descriptor->IsWasmImportWrapper() || ++ call_descriptor->IsWasmCapiFunction()) { ++ // Wasm import wrappers are passed a tuple in the place of the instance. ++ // Unpack the tuple into the instance and the target callable. ++ // This must be done here in the codegen because it cannot be expressed ++ // properly in the graph. ++ __ Ld(kJSFunctionRegister, ++ FieldMemOperand(kWasmInstanceRegister, Tuple2::kValue2Offset)); ++ __ Ld(kWasmInstanceRegister, ++ FieldMemOperand(kWasmInstanceRegister, Tuple2::kValue1Offset)); ++ __ Push(kWasmInstanceRegister); ++ if (call_descriptor->IsWasmCapiFunction()) { ++ // Reserve space for saving the PC later. ++ __ Sub64(sp, sp, Operand(kSystemPointerSize)); ++ } ++ } ++ } ++ } ++ ++ int required_slots = ++ frame()->GetTotalFrameSlotCount() - frame()->GetFixedSlotCount(); ++ ++ if (info()->is_osr()) { ++ // TurboFan OSR-compiled functions cannot be entered directly. ++ __ Abort(AbortReason::kShouldNotDirectlyEnterOsrFunction); ++ ++ // Unoptimized code jumps directly to this entrypoint while the unoptimized ++ // frame is still on the stack. Optimized code uses OSR values directly from ++ // the unoptimized frame. Thus, all that needs to be done is to allocate the ++ // remaining stack slots. ++ if (FLAG_code_comments) __ RecordComment("-- OSR entrypoint --"); ++ osr_pc_offset_ = __ pc_offset(); ++ required_slots -= osr_helper()->UnoptimizedFrameSlots(); ++ ResetSpeculationPoison(); ++ } ++ ++ const RegList saves = call_descriptor->CalleeSavedRegisters(); ++ const RegList saves_fpu = call_descriptor->CalleeSavedFPRegisters(); ++ ++ if (required_slots > 0) { ++ DCHECK(frame_access_state()->has_frame()); ++ if (info()->IsWasm() && required_slots > 128) { ++ // For WebAssembly functions with big frames we have to do the stack ++ // overflow check before we construct the frame. Otherwise we may not ++ // have enough space on the stack to call the runtime for the stack ++ // overflow. ++ Label done; ++ ++ // If the frame is bigger than the stack, we throw the stack overflow ++ // exception unconditionally. Thereby we can avoid the integer overflow ++ // check in the condition code. ++ if ((required_slots * kSystemPointerSize) < (FLAG_stack_size * 1024)) { ++ __ Ld( ++ kScratchReg, ++ FieldMemOperand(kWasmInstanceRegister, ++ WasmInstanceObject::kRealStackLimitAddressOffset)); ++ __ Ld(kScratchReg, MemOperand(kScratchReg)); ++ __ Add64(kScratchReg, kScratchReg, ++ Operand(required_slots * kSystemPointerSize)); ++ __ Branch(&done, uge, sp, Operand(kScratchReg)); ++ } ++ ++ __ Call(wasm::WasmCode::kWasmStackOverflow, RelocInfo::WASM_STUB_CALL); ++ // We come from WebAssembly, there are no references for the GC. ++ ReferenceMap* reference_map = zone()->New(zone()); ++ RecordSafepoint(reference_map, Safepoint::kNoLazyDeopt); ++ if (FLAG_debug_code) { ++ __ stop(); ++ } ++ ++ __ bind(&done); ++ } ++ } ++ ++ const int returns = frame()->GetReturnSlotCount(); ++ ++ // Skip callee-saved and return slots, which are pushed below. ++ required_slots -= base::bits::CountPopulation(saves); ++ required_slots -= base::bits::CountPopulation(saves_fpu); ++ required_slots -= returns; ++ if (required_slots > 0) { ++ __ Sub64(sp, sp, Operand(required_slots * kSystemPointerSize)); ++ } ++ ++ if (saves_fpu != 0) { ++ // Save callee-saved FPU registers. ++ __ MultiPushFPU(saves_fpu); ++ DCHECK_EQ(kNumCalleeSavedFPU, base::bits::CountPopulation(saves_fpu)); ++ } ++ ++ if (saves != 0) { ++ // Save callee-saved registers. ++ __ MultiPush(saves); ++ DCHECK_EQ(kNumCalleeSaved, base::bits::CountPopulation(saves) + 1); ++ } ++ ++ if (returns != 0) { ++ // Create space for returns. ++ __ Sub64(sp, sp, Operand(returns * kSystemPointerSize)); ++ } ++} ++ ++void CodeGenerator::AssembleReturn(InstructionOperand* pop) { ++ auto call_descriptor = linkage()->GetIncomingDescriptor(); ++ ++ const int returns = frame()->GetReturnSlotCount(); ++ if (returns != 0) { ++ __ Add64(sp, sp, Operand(returns * kSystemPointerSize)); ++ } ++ ++ // Restore GP registers. ++ const RegList saves = call_descriptor->CalleeSavedRegisters(); ++ if (saves != 0) { ++ __ MultiPop(saves); ++ } ++ ++ // Restore FPU registers. ++ const RegList saves_fpu = call_descriptor->CalleeSavedFPRegisters(); ++ if (saves_fpu != 0) { ++ __ MultiPopFPU(saves_fpu); ++ } ++ ++ RiscvOperandConverter g(this, nullptr); ++ if (call_descriptor->IsCFunctionCall()) { ++ AssembleDeconstructFrame(); ++ } else if (frame_access_state()->has_frame()) { ++ // Canonicalize JSFunction return sites for now unless they have an variable ++ // number of stack slot pops. ++ if (pop->IsImmediate() && g.ToConstant(pop).ToInt32() == 0) { ++ if (return_label_.is_bound()) { ++ __ Branch(&return_label_); ++ return; ++ } else { ++ __ bind(&return_label_); ++ AssembleDeconstructFrame(); ++ } ++ } else { ++ AssembleDeconstructFrame(); ++ } ++ } ++ int pop_count = static_cast(call_descriptor->StackParameterCount()); ++ if (pop->IsImmediate()) { ++ pop_count += g.ToConstant(pop).ToInt32(); ++ } else { ++ Register pop_reg = g.ToRegister(pop); ++ __ Sll64(pop_reg, pop_reg, kSystemPointerSizeLog2); ++ __ Add64(sp, sp, pop_reg); ++ } ++ if (pop_count != 0) { ++ __ DropAndRet(pop_count); ++ } else { ++ __ Ret(); ++ } ++} ++ ++void CodeGenerator::FinishCode() {} ++ ++void CodeGenerator::PrepareForDeoptimizationExits(int deopt_count) {} ++ ++void CodeGenerator::AssembleMove(InstructionOperand* source, ++ InstructionOperand* destination) { ++ RiscvOperandConverter g(this, nullptr); ++ // Dispatch on the source and destination operand kinds. Not all ++ // combinations are possible. ++ if (source->IsRegister()) { ++ DCHECK(destination->IsRegister() || destination->IsStackSlot()); ++ Register src = g.ToRegister(source); ++ if (destination->IsRegister()) { ++ __ Move(g.ToRegister(destination), src); ++ } else { ++ __ Sd(src, g.ToMemOperand(destination)); ++ } ++ } else if (source->IsStackSlot()) { ++ DCHECK(destination->IsRegister() || destination->IsStackSlot()); ++ MemOperand src = g.ToMemOperand(source); ++ if (destination->IsRegister()) { ++ __ Ld(g.ToRegister(destination), src); ++ } else { ++ Register temp = kScratchReg; ++ __ Ld(temp, src); ++ __ Sd(temp, g.ToMemOperand(destination)); ++ } ++ } else if (source->IsConstant()) { ++ Constant src = g.ToConstant(source); ++ if (destination->IsRegister() || destination->IsStackSlot()) { ++ Register dst = ++ destination->IsRegister() ? g.ToRegister(destination) : kScratchReg; ++ switch (src.type()) { ++ case Constant::kInt32: ++ __ li(dst, Operand(src.ToInt32())); ++ break; ++ case Constant::kFloat32: ++ __ li(dst, Operand::EmbeddedNumber(src.ToFloat32())); ++ break; ++ case Constant::kInt64: ++ if (RelocInfo::IsWasmReference(src.rmode())) { ++ __ li(dst, Operand(src.ToInt64(), src.rmode())); ++ } else { ++ __ li(dst, Operand(src.ToInt64())); ++ } ++ break; ++ case Constant::kFloat64: ++ __ li(dst, Operand::EmbeddedNumber(src.ToFloat64().value())); ++ break; ++ case Constant::kExternalReference: ++ __ li(dst, src.ToExternalReference()); ++ break; ++ case Constant::kDelayedStringConstant: ++ __ li(dst, src.ToDelayedStringConstant()); ++ break; ++ case Constant::kHeapObject: { ++ Handle src_object = src.ToHeapObject(); ++ RootIndex index; ++ if (IsMaterializableFromRoot(src_object, &index)) { ++ __ LoadRoot(dst, index); ++ } else { ++ __ li(dst, src_object); ++ } ++ break; ++ } ++ case Constant::kCompressedHeapObject: ++ UNREACHABLE(); ++ case Constant::kRpoNumber: ++ UNREACHABLE(); // TODO(titzer): loading RPO numbers ++ break; ++ } ++ if (destination->IsStackSlot()) __ Sd(dst, g.ToMemOperand(destination)); ++ } else if (src.type() == Constant::kFloat32) { ++ if (destination->IsFPStackSlot()) { ++ MemOperand dst = g.ToMemOperand(destination); ++ if (bit_cast(src.ToFloat32()) == 0) { ++ __ Sw(zero_reg, dst); ++ } else { ++ __ li(kScratchReg, Operand(bit_cast(src.ToFloat32()))); ++ __ Sw(kScratchReg, dst); ++ } ++ } else { ++ DCHECK(destination->IsFPRegister()); ++ FloatRegister dst = g.ToSingleRegister(destination); ++ __ LoadFPRImmediate(dst, src.ToFloat32()); ++ } ++ } else { ++ DCHECK_EQ(Constant::kFloat64, src.type()); ++ DoubleRegister dst = destination->IsFPRegister() ++ ? g.ToDoubleRegister(destination) ++ : kScratchDoubleReg; ++ __ LoadFPRImmediate(dst, src.ToFloat64().value()); ++ if (destination->IsFPStackSlot()) { ++ __ StoreDouble(dst, g.ToMemOperand(destination)); ++ } ++ } ++ } else if (source->IsFPRegister()) { ++ MachineRepresentation rep = LocationOperand::cast(source)->representation(); ++ if (rep == MachineRepresentation::kSimd128) { ++ UNIMPLEMENTED(); ++ } else { ++ FPURegister src = g.ToDoubleRegister(source); ++ if (destination->IsFPRegister()) { ++ FPURegister dst = g.ToDoubleRegister(destination); ++ __ Move(dst, src); ++ } else { ++ DCHECK(destination->IsFPStackSlot()); ++ if (rep == MachineRepresentation::kFloat32) { ++ __ StoreFloat(src, g.ToMemOperand(destination)); ++ } else { ++ DCHECK_EQ(rep, MachineRepresentation::kFloat64); ++ __ StoreDouble(src, g.ToMemOperand(destination)); ++ } ++ } ++ } ++ } else if (source->IsFPStackSlot()) { ++ DCHECK(destination->IsFPRegister() || destination->IsFPStackSlot()); ++ MemOperand src = g.ToMemOperand(source); ++ MachineRepresentation rep = LocationOperand::cast(source)->representation(); ++ if (rep == MachineRepresentation::kSimd128) { ++ UNIMPLEMENTED(); ++ } else { ++ if (destination->IsFPRegister()) { ++ if (rep == MachineRepresentation::kFloat32) { ++ __ LoadFloat(g.ToDoubleRegister(destination), src); ++ } else { ++ DCHECK_EQ(rep, MachineRepresentation::kFloat64); ++ __ LoadDouble(g.ToDoubleRegister(destination), src); ++ } ++ } else { ++ DCHECK(destination->IsFPStackSlot()); ++ FPURegister temp = kScratchDoubleReg; ++ if (rep == MachineRepresentation::kFloat32) { ++ __ LoadFloat(temp, src); ++ __ StoreFloat(temp, g.ToMemOperand(destination)); ++ } else { ++ DCHECK_EQ(rep, MachineRepresentation::kFloat64); ++ __ LoadDouble(temp, src); ++ __ StoreDouble(temp, g.ToMemOperand(destination)); ++ } ++ } ++ } ++ } else { ++ UNREACHABLE(); ++ } ++} ++ ++void CodeGenerator::AssembleSwap(InstructionOperand* source, ++ InstructionOperand* destination) { ++ RiscvOperandConverter g(this, nullptr); ++ // Dispatch on the source and destination operand kinds. Not all ++ // combinations are possible. ++ if (source->IsRegister()) { ++ // Register-register. ++ Register temp = kScratchReg; ++ Register src = g.ToRegister(source); ++ if (destination->IsRegister()) { ++ Register dst = g.ToRegister(destination); ++ __ Move(temp, src); ++ __ Move(src, dst); ++ __ Move(dst, temp); ++ } else { ++ DCHECK(destination->IsStackSlot()); ++ MemOperand dst = g.ToMemOperand(destination); ++ __ Move(temp, src); ++ __ Ld(src, dst); ++ __ Sd(temp, dst); ++ } ++ } else if (source->IsStackSlot()) { ++ DCHECK(destination->IsStackSlot()); ++ Register temp_0 = kScratchReg; ++ Register temp_1 = kScratchReg2; ++ MemOperand src = g.ToMemOperand(source); ++ MemOperand dst = g.ToMemOperand(destination); ++ __ Ld(temp_0, src); ++ __ Ld(temp_1, dst); ++ __ Sd(temp_0, dst); ++ __ Sd(temp_1, src); ++ } else if (source->IsFPRegister()) { ++ MachineRepresentation rep = LocationOperand::cast(source)->representation(); ++ if (rep == MachineRepresentation::kSimd128) { ++ UNIMPLEMENTED(); ++ } else { ++ FPURegister temp = kScratchDoubleReg; ++ FPURegister src = g.ToDoubleRegister(source); ++ if (destination->IsFPRegister()) { ++ FPURegister dst = g.ToDoubleRegister(destination); ++ __ Move(temp, src); ++ __ Move(src, dst); ++ __ Move(dst, temp); ++ } else { ++ DCHECK(destination->IsFPStackSlot()); ++ MemOperand dst = g.ToMemOperand(destination); ++ __ Move(temp, src); ++ __ LoadDouble(src, dst); ++ __ StoreDouble(temp, dst); ++ } ++ } ++ } else if (source->IsFPStackSlot()) { ++ DCHECK(destination->IsFPStackSlot()); ++ Register temp_0 = kScratchReg; ++ MemOperand src0 = g.ToMemOperand(source); ++ MemOperand src1(src0.rm(), src0.offset() + kIntSize); ++ MemOperand dst0 = g.ToMemOperand(destination); ++ MemOperand dst1(dst0.rm(), dst0.offset() + kIntSize); ++ MachineRepresentation rep = LocationOperand::cast(source)->representation(); ++ if (rep == MachineRepresentation::kSimd128) { ++ UNIMPLEMENTED(); ++ } else { ++ FPURegister temp_1 = kScratchDoubleReg; ++ __ LoadDouble(temp_1, dst0); // Save destination in temp_1. ++ __ Lw(temp_0, src0); // Then use temp_0 to copy source to destination. ++ __ Sw(temp_0, dst0); ++ __ Lw(temp_0, src1); ++ __ Sw(temp_0, dst1); ++ __ StoreDouble(temp_1, src0); ++ } ++ } else { ++ // No other combinations are possible. ++ UNREACHABLE(); ++ } ++} ++ ++void CodeGenerator::AssembleJumpTable(Label** targets, size_t target_count) { ++ // On 64-bit RISC-V we emit the jump tables inline. ++ UNREACHABLE(); ++} ++ ++#undef ASSEMBLE_ATOMIC_LOAD_INTEGER ++#undef ASSEMBLE_ATOMIC_STORE_INTEGER ++#undef ASSEMBLE_ATOMIC_BINOP ++#undef ASSEMBLE_ATOMIC_BINOP_EXT ++#undef ASSEMBLE_ATOMIC_EXCHANGE_INTEGER ++#undef ASSEMBLE_ATOMIC_EXCHANGE_INTEGER_EXT ++#undef ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER ++#undef ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER_EXT ++#undef ASSEMBLE_IEEE754_BINOP ++#undef ASSEMBLE_IEEE754_UNOP ++ ++#undef TRACE_MSG ++#undef TRACE_UNIMPL ++#undef __ ++ ++} // namespace compiler ++} // namespace internal ++} // namespace v8 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-codes-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-codes-riscv64.h +@@ -0,0 +1,432 @@ ++// Copyright 2014 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_COMPILER_BACKEND_RISCV_INSTRUCTION_CODES_RISCV_H_ ++#define V8_COMPILER_BACKEND_RISCV_INSTRUCTION_CODES_RISCV_H_ ++ ++namespace v8 { ++namespace internal { ++namespace compiler { ++ ++// RISC-V-specific opcodes that specify which assembly sequence to emit. ++// Most opcodes specify a single instruction. ++#define TARGET_ARCH_OPCODE_LIST(V) \ ++ V(RiscvAdd32) \ ++ V(RiscvAdd64) \ ++ V(RiscvAddOvf64) \ ++ V(RiscvSub32) \ ++ V(RiscvSub64) \ ++ V(RiscvSubOvf64) \ ++ V(RiscvMul32) \ ++ V(RiscvMulOvf32) \ ++ V(RiscvMulHigh32) \ ++ V(RiscvMulHigh64) \ ++ V(RiscvMulHighU32) \ ++ V(RiscvMul64) \ ++ V(RiscvDiv32) \ ++ V(RiscvDiv64) \ ++ V(RiscvDivU32) \ ++ V(RiscvDivU64) \ ++ V(RiscvMod32) \ ++ V(RiscvMod64) \ ++ V(RiscvModU32) \ ++ V(RiscvModU64) \ ++ V(RiscvAnd) \ ++ V(RiscvAnd32) \ ++ V(RiscvOr) \ ++ V(RiscvOr32) \ ++ V(RiscvNor) \ ++ V(RiscvNor32) \ ++ V(RiscvXor) \ ++ V(RiscvXor32) \ ++ V(RiscvClz32) \ ++ V(RiscvShl32) \ ++ V(RiscvShr32) \ ++ V(RiscvSar32) \ ++ V(RiscvZeroExtendWord) \ ++ V(RiscvSignExtendWord) \ ++ V(RiscvClz64) \ ++ V(RiscvCtz32) \ ++ V(RiscvCtz64) \ ++ V(RiscvPopcnt32) \ ++ V(RiscvPopcnt64) \ ++ V(RiscvShl64) \ ++ V(RiscvShr64) \ ++ V(RiscvSar64) \ ++ V(RiscvRor32) \ ++ V(RiscvRor64) \ ++ V(RiscvMov) \ ++ V(RiscvTst) \ ++ V(RiscvCmp) \ ++ V(RiscvCmpS) \ ++ V(RiscvAddS) \ ++ V(RiscvSubS) \ ++ V(RiscvMulS) \ ++ V(RiscvDivS) \ ++ V(RiscvModS) \ ++ V(RiscvAbsS) \ ++ V(RiscvNegS) \ ++ V(RiscvSqrtS) \ ++ V(RiscvMaxS) \ ++ V(RiscvMinS) \ ++ V(RiscvCmpD) \ ++ V(RiscvAddD) \ ++ V(RiscvSubD) \ ++ V(RiscvMulD) \ ++ V(RiscvDivD) \ ++ V(RiscvModD) \ ++ V(RiscvAbsD) \ ++ V(RiscvNegD) \ ++ V(RiscvSqrtD) \ ++ V(RiscvMaxD) \ ++ V(RiscvMinD) \ ++ V(RiscvFloat64RoundDown) \ ++ V(RiscvFloat64RoundTruncate) \ ++ V(RiscvFloat64RoundUp) \ ++ V(RiscvFloat64RoundTiesEven) \ ++ V(RiscvFloat32RoundDown) \ ++ V(RiscvFloat32RoundTruncate) \ ++ V(RiscvFloat32RoundUp) \ ++ V(RiscvFloat32RoundTiesEven) \ ++ V(RiscvCvtSD) \ ++ V(RiscvCvtDS) \ ++ V(RiscvTruncWD) \ ++ V(RiscvRoundWD) \ ++ V(RiscvFloorWD) \ ++ V(RiscvCeilWD) \ ++ V(RiscvTruncWS) \ ++ V(RiscvRoundWS) \ ++ V(RiscvFloorWS) \ ++ V(RiscvCeilWS) \ ++ V(RiscvTruncLS) \ ++ V(RiscvTruncLD) \ ++ V(RiscvTruncUwD) \ ++ V(RiscvTruncUwS) \ ++ V(RiscvTruncUlS) \ ++ V(RiscvTruncUlD) \ ++ V(RiscvCvtDW) \ ++ V(RiscvCvtSL) \ ++ V(RiscvCvtSW) \ ++ V(RiscvCvtSUw) \ ++ V(RiscvCvtSUl) \ ++ V(RiscvCvtDL) \ ++ V(RiscvCvtDUw) \ ++ V(RiscvCvtDUl) \ ++ V(RiscvLb) \ ++ V(RiscvLbu) \ ++ V(RiscvSb) \ ++ V(RiscvLh) \ ++ V(RiscvUlh) \ ++ V(RiscvLhu) \ ++ V(RiscvUlhu) \ ++ V(RiscvSh) \ ++ V(RiscvUsh) \ ++ V(RiscvLd) \ ++ V(RiscvUld) \ ++ V(RiscvLw) \ ++ V(RiscvUlw) \ ++ V(RiscvLwu) \ ++ V(RiscvUlwu) \ ++ V(RiscvSw) \ ++ V(RiscvUsw) \ ++ V(RiscvSd) \ ++ V(RiscvUsd) \ ++ V(RiscvLoadFloat) \ ++ V(RiscvULoadFloat) \ ++ V(RiscvStoreFloat) \ ++ V(RiscvUStoreFloat) \ ++ V(RiscvLoadDouble) \ ++ V(RiscvULoadDouble) \ ++ V(RiscvStoreDouble) \ ++ V(RiscvUStoreDouble) \ ++ V(RiscvBitcastDL) \ ++ V(RiscvBitcastLD) \ ++ V(RiscvBitcastInt32ToFloat32) \ ++ V(RiscvBitcastFloat32ToInt32) \ ++ V(RiscvFloat64ExtractLowWord32) \ ++ V(RiscvFloat64ExtractHighWord32) \ ++ V(RiscvFloat64InsertLowWord32) \ ++ V(RiscvFloat64InsertHighWord32) \ ++ V(RiscvFloat32Max) \ ++ V(RiscvFloat64Max) \ ++ V(RiscvFloat32Min) \ ++ V(RiscvFloat64Min) \ ++ V(RiscvFloat64SilenceNaN) \ ++ V(RiscvPush) \ ++ V(RiscvPeek) \ ++ V(RiscvByteSwap64) \ ++ V(RiscvByteSwap32) \ ++ V(RiscvStoreToStackSlot) \ ++ V(RiscvStackClaim) \ ++ V(RiscvSignExtendByte) \ ++ V(RiscvSignExtendShort) \ ++ V(RiscvSync) \ ++ V(RiscvAssertEqual) \ ++ V(RiscvS128Const) \ ++ V(RiscvS128Zero) \ ++ V(RiscvS128AllOnes) \ ++ V(RiscvI32x4Splat) \ ++ V(RiscvI32x4ExtractLane) \ ++ V(RiscvI32x4ReplaceLane) \ ++ V(RiscvI32x4Add) \ ++ V(RiscvI32x4AddHoriz) \ ++ V(RiscvI32x4Sub) \ ++ V(RiscvF64x2Abs) \ ++ V(RiscvF64x2Neg) \ ++ V(RiscvF32x4Splat) \ ++ V(RiscvF32x4ExtractLane) \ ++ V(RiscvF32x4ReplaceLane) \ ++ V(RiscvF32x4SConvertI32x4) \ ++ V(RiscvF32x4UConvertI32x4) \ ++ V(RiscvI32x4Mul) \ ++ V(RiscvI32x4MaxS) \ ++ V(RiscvI32x4MinS) \ ++ V(RiscvI32x4Eq) \ ++ V(RiscvI32x4Ne) \ ++ V(RiscvI32x4Shl) \ ++ V(RiscvI32x4ShrS) \ ++ V(RiscvI32x4ShrU) \ ++ V(RiscvI32x4MaxU) \ ++ V(RiscvI32x4MinU) \ ++ V(RiscvF64x2Sqrt) \ ++ V(RiscvF64x2Add) \ ++ V(RiscvF64x2Sub) \ ++ V(RiscvF64x2Mul) \ ++ V(RiscvF64x2Div) \ ++ V(RiscvF64x2Min) \ ++ V(RiscvF64x2Max) \ ++ V(RiscvF64x2Eq) \ ++ V(RiscvF64x2Ne) \ ++ V(RiscvF64x2Lt) \ ++ V(RiscvF64x2Le) \ ++ V(RiscvF64x2Splat) \ ++ V(RiscvF64x2ExtractLane) \ ++ V(RiscvF64x2ReplaceLane) \ ++ V(RiscvF64x2Pmin) \ ++ V(RiscvF64x2Pmax) \ ++ V(RiscvF64x2Ceil) \ ++ V(RiscvF64x2Floor) \ ++ V(RiscvF64x2Trunc) \ ++ V(RiscvF64x2NearestInt) \ ++ V(RiscvI64x2Splat) \ ++ V(RiscvI64x2ExtractLane) \ ++ V(RiscvI64x2ReplaceLane) \ ++ V(RiscvI64x2Add) \ ++ V(RiscvI64x2Sub) \ ++ V(RiscvI64x2Mul) \ ++ V(RiscvI64x2Neg) \ ++ V(RiscvI64x2Shl) \ ++ V(RiscvI64x2ShrS) \ ++ V(RiscvI64x2ShrU) \ ++ V(RiscvF32x4Abs) \ ++ V(RiscvF32x4Neg) \ ++ V(RiscvF32x4Sqrt) \ ++ V(RiscvF32x4RecipApprox) \ ++ V(RiscvF32x4RecipSqrtApprox) \ ++ V(RiscvF32x4Add) \ ++ V(RiscvF32x4AddHoriz) \ ++ V(RiscvF32x4Sub) \ ++ V(RiscvF32x4Mul) \ ++ V(RiscvF32x4Div) \ ++ V(RiscvF32x4Max) \ ++ V(RiscvF32x4Min) \ ++ V(RiscvF32x4Eq) \ ++ V(RiscvF32x4Ne) \ ++ V(RiscvF32x4Lt) \ ++ V(RiscvF32x4Le) \ ++ V(RiscvF32x4Pmin) \ ++ V(RiscvF32x4Pmax) \ ++ V(RiscvF32x4Ceil) \ ++ V(RiscvF32x4Floor) \ ++ V(RiscvF32x4Trunc) \ ++ V(RiscvF32x4NearestInt) \ ++ V(RiscvI32x4SConvertF32x4) \ ++ V(RiscvI32x4UConvertF32x4) \ ++ V(RiscvI32x4Neg) \ ++ V(RiscvI32x4GtS) \ ++ V(RiscvI32x4GeS) \ ++ V(RiscvI32x4GtU) \ ++ V(RiscvI32x4GeU) \ ++ V(RiscvI32x4Abs) \ ++ V(RiscvI32x4BitMask) \ ++ V(RiscvI16x8Splat) \ ++ V(RiscvI16x8ExtractLaneU) \ ++ V(RiscvI16x8ExtractLaneS) \ ++ V(RiscvI16x8ReplaceLane) \ ++ V(RiscvI16x8Neg) \ ++ V(RiscvI16x8Shl) \ ++ V(RiscvI16x8ShrS) \ ++ V(RiscvI16x8ShrU) \ ++ V(RiscvI16x8Add) \ ++ V(RiscvI16x8AddSaturateS) \ ++ V(RiscvI16x8AddHoriz) \ ++ V(RiscvI16x8Sub) \ ++ V(RiscvI16x8SubSaturateS) \ ++ V(RiscvI16x8Mul) \ ++ V(RiscvI16x8MaxS) \ ++ V(RiscvI16x8MinS) \ ++ V(RiscvI16x8Eq) \ ++ V(RiscvI16x8Ne) \ ++ V(RiscvI16x8GtS) \ ++ V(RiscvI16x8GeS) \ ++ V(RiscvI16x8AddSaturateU) \ ++ V(RiscvI16x8SubSaturateU) \ ++ V(RiscvI16x8MaxU) \ ++ V(RiscvI16x8MinU) \ ++ V(RiscvI16x8GtU) \ ++ V(RiscvI16x8GeU) \ ++ V(RiscvI16x8RoundingAverageU) \ ++ V(RiscvI16x8Abs) \ ++ V(RiscvI16x8BitMask) \ ++ V(RiscvI8x16Splat) \ ++ V(RiscvI8x16ExtractLaneU) \ ++ V(RiscvI8x16ExtractLaneS) \ ++ V(RiscvI8x16ReplaceLane) \ ++ V(RiscvI8x16Neg) \ ++ V(RiscvI8x16Shl) \ ++ V(RiscvI8x16ShrS) \ ++ V(RiscvI8x16Add) \ ++ V(RiscvI8x16AddSaturateS) \ ++ V(RiscvI8x16Sub) \ ++ V(RiscvI8x16SubSaturateS) \ ++ V(RiscvI8x16Mul) \ ++ V(RiscvI8x16MaxS) \ ++ V(RiscvI8x16MinS) \ ++ V(RiscvI8x16Eq) \ ++ V(RiscvI8x16Ne) \ ++ V(RiscvI8x16GtS) \ ++ V(RiscvI8x16GeS) \ ++ V(RiscvI8x16ShrU) \ ++ V(RiscvI8x16AddSaturateU) \ ++ V(RiscvI8x16SubSaturateU) \ ++ V(RiscvI8x16MaxU) \ ++ V(RiscvI8x16MinU) \ ++ V(RiscvI8x16GtU) \ ++ V(RiscvI8x16GeU) \ ++ V(RiscvI8x16RoundingAverageU) \ ++ V(RiscvI8x16Abs) \ ++ V(RiscvI8x16BitMask) \ ++ V(RiscvS128And) \ ++ V(RiscvS128Or) \ ++ V(RiscvS128Xor) \ ++ V(RiscvS128Not) \ ++ V(RiscvS128Select) \ ++ V(RiscvS128AndNot) \ ++ V(RiscvV32x4AnyTrue) \ ++ V(RiscvV32x4AllTrue) \ ++ V(RiscvV16x8AnyTrue) \ ++ V(RiscvV16x8AllTrue) \ ++ V(RiscvV8x16AnyTrue) \ ++ V(RiscvV8x16AllTrue) \ ++ V(RiscvS32x4InterleaveRight) \ ++ V(RiscvS32x4InterleaveLeft) \ ++ V(RiscvS32x4PackEven) \ ++ V(RiscvS32x4PackOdd) \ ++ V(RiscvS32x4InterleaveEven) \ ++ V(RiscvS32x4InterleaveOdd) \ ++ V(RiscvS32x4Shuffle) \ ++ V(RiscvS16x8InterleaveRight) \ ++ V(RiscvS16x8InterleaveLeft) \ ++ V(RiscvS16x8PackEven) \ ++ V(RiscvS16x8PackOdd) \ ++ V(RiscvS16x8InterleaveEven) \ ++ V(RiscvS16x8InterleaveOdd) \ ++ V(RiscvS16x4Reverse) \ ++ V(RiscvS16x2Reverse) \ ++ V(RiscvS8x16InterleaveRight) \ ++ V(RiscvS8x16InterleaveLeft) \ ++ V(RiscvS8x16PackEven) \ ++ V(RiscvS8x16PackOdd) \ ++ V(RiscvS8x16InterleaveEven) \ ++ V(RiscvS8x16InterleaveOdd) \ ++ V(RiscvI8x16Shuffle) \ ++ V(RiscvI8x16Swizzle) \ ++ V(RiscvS8x16Concat) \ ++ V(RiscvS8x8Reverse) \ ++ V(RiscvS8x4Reverse) \ ++ V(RiscvS8x2Reverse) \ ++ V(RiscvS8x16LoadSplat) \ ++ V(RiscvS16x8LoadSplat) \ ++ V(RiscvS32x4LoadSplat) \ ++ V(RiscvS64x2LoadSplat) \ ++ V(RiscvI16x8Load8x8S) \ ++ V(RiscvI16x8Load8x8U) \ ++ V(RiscvI32x4Load16x4S) \ ++ V(RiscvI32x4Load16x4U) \ ++ V(RiscvI64x2Load32x2S) \ ++ V(RiscvI64x2Load32x2U) \ ++ V(RiscvMsaLd) \ ++ V(RiscvMsaSt) \ ++ V(RiscvI32x4SConvertI16x8Low) \ ++ V(RiscvI32x4SConvertI16x8High) \ ++ V(RiscvI32x4UConvertI16x8Low) \ ++ V(RiscvI32x4UConvertI16x8High) \ ++ V(RiscvI16x8SConvertI8x16Low) \ ++ V(RiscvI16x8SConvertI8x16High) \ ++ V(RiscvI16x8SConvertI32x4) \ ++ V(RiscvI16x8UConvertI32x4) \ ++ V(RiscvI16x8UConvertI8x16Low) \ ++ V(RiscvI16x8UConvertI8x16High) \ ++ V(RiscvI8x16SConvertI16x8) \ ++ V(RiscvI8x16UConvertI16x8) \ ++ V(RiscvWord64AtomicLoadUint8) \ ++ V(RiscvWord64AtomicLoadUint16) \ ++ V(RiscvWord64AtomicLoadUint32) \ ++ V(RiscvWord64AtomicLoadUint64) \ ++ V(RiscvWord64AtomicStoreWord8) \ ++ V(RiscvWord64AtomicStoreWord16) \ ++ V(RiscvWord64AtomicStoreWord32) \ ++ V(RiscvWord64AtomicStoreWord64) \ ++ V(RiscvWord64AtomicAddUint8) \ ++ V(RiscvWord64AtomicAddUint16) \ ++ V(RiscvWord64AtomicAddUint32) \ ++ V(RiscvWord64AtomicAddUint64) \ ++ V(RiscvWord64AtomicSubUint8) \ ++ V(RiscvWord64AtomicSubUint16) \ ++ V(RiscvWord64AtomicSubUint32) \ ++ V(RiscvWord64AtomicSubUint64) \ ++ V(RiscvWord64AtomicAndUint8) \ ++ V(RiscvWord64AtomicAndUint16) \ ++ V(RiscvWord64AtomicAndUint32) \ ++ V(RiscvWord64AtomicAndUint64) \ ++ V(RiscvWord64AtomicOrUint8) \ ++ V(RiscvWord64AtomicOrUint16) \ ++ V(RiscvWord64AtomicOrUint32) \ ++ V(RiscvWord64AtomicOrUint64) \ ++ V(RiscvWord64AtomicXorUint8) \ ++ V(RiscvWord64AtomicXorUint16) \ ++ V(RiscvWord64AtomicXorUint32) \ ++ V(RiscvWord64AtomicXorUint64) \ ++ V(RiscvWord64AtomicExchangeUint8) \ ++ V(RiscvWord64AtomicExchangeUint16) \ ++ V(RiscvWord64AtomicExchangeUint32) \ ++ V(RiscvWord64AtomicExchangeUint64) \ ++ V(RiscvWord64AtomicCompareExchangeUint8) \ ++ V(RiscvWord64AtomicCompareExchangeUint16) \ ++ V(RiscvWord64AtomicCompareExchangeUint32) \ ++ V(RiscvWord64AtomicCompareExchangeUint64) ++ ++// Addressing modes represent the "shape" of inputs to an instruction. ++// Many instructions support multiple addressing modes. Addressing modes ++// are encoded into the InstructionCode of the instruction and tell the ++// code generator after register allocation which assembler method to call. ++// ++// We use the following local notation for addressing modes: ++// ++// R = register ++// O = register or stack slot ++// D = double register ++// I = immediate (handle, external, int32) ++// MRI = [register + immediate] ++// MRR = [register + register] ++// TODO(plind): Add the new r6 address modes. ++#define TARGET_ADDRESSING_MODE_LIST(V) \ ++ V(MRI) /* [%r0 + K] */ \ ++ V(MRR) /* [%r0 + %r1] */ ++ ++} // namespace compiler ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_COMPILER_BACKEND_RISCV_INSTRUCTION_CODES_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-scheduler-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-scheduler-riscv64.cc +@@ -0,0 +1,1571 @@ ++// Copyright 2015 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#include "src/codegen/macro-assembler.h" ++#include "src/compiler/backend/instruction-scheduler.h" ++ ++namespace v8 { ++namespace internal { ++namespace compiler { ++ ++bool InstructionScheduler::SchedulerSupported() { return true; } ++ ++int InstructionScheduler::GetTargetInstructionFlags( ++ const Instruction* instr) const { ++ switch (instr->arch_opcode()) { ++ case kRiscvAbsD: ++ case kRiscvAbsS: ++ case kRiscvAdd32: ++ case kRiscvAddD: ++ case kRiscvAddS: ++ case kRiscvAnd: ++ case kRiscvAnd32: ++ case kRiscvAssertEqual: ++ case kRiscvBitcastDL: ++ case kRiscvBitcastLD: ++ case kRiscvBitcastInt32ToFloat32: ++ case kRiscvBitcastFloat32ToInt32: ++ case kRiscvByteSwap32: ++ case kRiscvByteSwap64: ++ case kRiscvCeilWD: ++ case kRiscvCeilWS: ++ case kRiscvClz32: ++ case kRiscvCmp: ++ case kRiscvCmpD: ++ case kRiscvCmpS: ++ case kRiscvCtz32: ++ case kRiscvCvtDL: ++ case kRiscvCvtDS: ++ case kRiscvCvtDUl: ++ case kRiscvCvtDUw: ++ case kRiscvCvtDW: ++ case kRiscvCvtSD: ++ case kRiscvCvtSL: ++ case kRiscvCvtSUl: ++ case kRiscvCvtSUw: ++ case kRiscvCvtSW: ++ case kRiscvMulHigh64: ++ case kRiscvMulHighU32: ++ case kRiscvAdd64: ++ case kRiscvAddOvf64: ++ case kRiscvClz64: ++ case kRiscvCtz64: ++ case kRiscvDiv64: ++ case kRiscvDivU64: ++ case kRiscvZeroExtendWord: ++ case kRiscvSignExtendWord: ++ case kRiscvDiv32: ++ case kRiscvDivD: ++ case kRiscvDivS: ++ case kRiscvDivU32: ++ case kRiscvMod64: ++ case kRiscvModU64: ++ case kRiscvMul64: ++ case kRiscvPopcnt64: ++ case kRiscvRor64: ++ case kRiscvSar64: ++ case kRiscvShl64: ++ case kRiscvShr64: ++ case kRiscvSub64: ++ case kRiscvSubOvf64: ++ case kRiscvF64x2Abs: ++ case kRiscvF64x2Neg: ++ case kRiscvF64x2Sqrt: ++ case kRiscvF64x2Add: ++ case kRiscvF64x2Sub: ++ case kRiscvF64x2Mul: ++ case kRiscvF64x2Div: ++ case kRiscvF64x2Min: ++ case kRiscvF64x2Max: ++ case kRiscvF64x2Eq: ++ case kRiscvF64x2Ne: ++ case kRiscvF64x2Lt: ++ case kRiscvF64x2Le: ++ case kRiscvF64x2Pmin: ++ case kRiscvF64x2Pmax: ++ case kRiscvF64x2Ceil: ++ case kRiscvF64x2Floor: ++ case kRiscvF64x2Trunc: ++ case kRiscvF64x2NearestInt: ++ case kRiscvI64x2Splat: ++ case kRiscvI64x2ExtractLane: ++ case kRiscvI64x2ReplaceLane: ++ case kRiscvI64x2Add: ++ case kRiscvI64x2Sub: ++ case kRiscvI64x2Mul: ++ case kRiscvI64x2Neg: ++ case kRiscvI64x2Shl: ++ case kRiscvI64x2ShrS: ++ case kRiscvI64x2ShrU: ++ case kRiscvF32x4Abs: ++ case kRiscvF32x4Add: ++ case kRiscvF32x4AddHoriz: ++ case kRiscvF32x4Eq: ++ case kRiscvF32x4ExtractLane: ++ case kRiscvF32x4Lt: ++ case kRiscvF32x4Le: ++ case kRiscvF32x4Max: ++ case kRiscvF32x4Min: ++ case kRiscvF32x4Mul: ++ case kRiscvF32x4Div: ++ case kRiscvF32x4Ne: ++ case kRiscvF32x4Neg: ++ case kRiscvF32x4Sqrt: ++ case kRiscvF32x4RecipApprox: ++ case kRiscvF32x4RecipSqrtApprox: ++ case kRiscvF32x4ReplaceLane: ++ case kRiscvF32x4SConvertI32x4: ++ case kRiscvF32x4Splat: ++ case kRiscvF32x4Sub: ++ case kRiscvF32x4UConvertI32x4: ++ case kRiscvF32x4Pmin: ++ case kRiscvF32x4Pmax: ++ case kRiscvF32x4Ceil: ++ case kRiscvF32x4Floor: ++ case kRiscvF32x4Trunc: ++ case kRiscvF32x4NearestInt: ++ case kRiscvF64x2Splat: ++ case kRiscvF64x2ExtractLane: ++ case kRiscvF64x2ReplaceLane: ++ case kRiscvFloat32Max: ++ case kRiscvFloat32Min: ++ case kRiscvFloat32RoundDown: ++ case kRiscvFloat32RoundTiesEven: ++ case kRiscvFloat32RoundTruncate: ++ case kRiscvFloat32RoundUp: ++ case kRiscvFloat64ExtractLowWord32: ++ case kRiscvFloat64ExtractHighWord32: ++ case kRiscvFloat64InsertLowWord32: ++ case kRiscvFloat64InsertHighWord32: ++ case kRiscvFloat64Max: ++ case kRiscvFloat64Min: ++ case kRiscvFloat64RoundDown: ++ case kRiscvFloat64RoundTiesEven: ++ case kRiscvFloat64RoundTruncate: ++ case kRiscvFloat64RoundUp: ++ case kRiscvFloat64SilenceNaN: ++ case kRiscvFloorWD: ++ case kRiscvFloorWS: ++ case kRiscvI16x8Add: ++ case kRiscvI16x8AddHoriz: ++ case kRiscvI16x8AddSaturateS: ++ case kRiscvI16x8AddSaturateU: ++ case kRiscvI16x8Eq: ++ case kRiscvI16x8ExtractLaneU: ++ case kRiscvI16x8ExtractLaneS: ++ case kRiscvI16x8GeS: ++ case kRiscvI16x8GeU: ++ case kRiscvI16x8GtS: ++ case kRiscvI16x8GtU: ++ case kRiscvI16x8MaxS: ++ case kRiscvI16x8MaxU: ++ case kRiscvI16x8MinS: ++ case kRiscvI16x8MinU: ++ case kRiscvI16x8Mul: ++ case kRiscvI16x8Ne: ++ case kRiscvI16x8Neg: ++ case kRiscvI16x8ReplaceLane: ++ case kRiscvI8x16SConvertI16x8: ++ case kRiscvI16x8SConvertI32x4: ++ case kRiscvI16x8SConvertI8x16High: ++ case kRiscvI16x8SConvertI8x16Low: ++ case kRiscvI16x8Shl: ++ case kRiscvI16x8ShrS: ++ case kRiscvI16x8ShrU: ++ case kRiscvI16x8Splat: ++ case kRiscvI16x8Sub: ++ case kRiscvI16x8SubSaturateS: ++ case kRiscvI16x8SubSaturateU: ++ case kRiscvI8x16UConvertI16x8: ++ case kRiscvI16x8UConvertI32x4: ++ case kRiscvI16x8UConvertI8x16High: ++ case kRiscvI16x8UConvertI8x16Low: ++ case kRiscvI16x8RoundingAverageU: ++ case kRiscvI16x8Abs: ++ case kRiscvI16x8BitMask: ++ case kRiscvI32x4Add: ++ case kRiscvI32x4AddHoriz: ++ case kRiscvI32x4Eq: ++ case kRiscvI32x4ExtractLane: ++ case kRiscvI32x4GeS: ++ case kRiscvI32x4GeU: ++ case kRiscvI32x4GtS: ++ case kRiscvI32x4GtU: ++ case kRiscvI32x4MaxS: ++ case kRiscvI32x4MaxU: ++ case kRiscvI32x4MinS: ++ case kRiscvI32x4MinU: ++ case kRiscvI32x4Mul: ++ case kRiscvI32x4Ne: ++ case kRiscvI32x4Neg: ++ case kRiscvI32x4ReplaceLane: ++ case kRiscvI32x4SConvertF32x4: ++ case kRiscvI32x4SConvertI16x8High: ++ case kRiscvI32x4SConvertI16x8Low: ++ case kRiscvI32x4Shl: ++ case kRiscvI32x4ShrS: ++ case kRiscvI32x4ShrU: ++ case kRiscvI32x4Splat: ++ case kRiscvI32x4Sub: ++ case kRiscvI32x4UConvertF32x4: ++ case kRiscvI32x4UConvertI16x8High: ++ case kRiscvI32x4UConvertI16x8Low: ++ case kRiscvI32x4Abs: ++ case kRiscvI32x4BitMask: ++ case kRiscvI8x16Add: ++ case kRiscvI8x16AddSaturateS: ++ case kRiscvI8x16AddSaturateU: ++ case kRiscvI8x16Eq: ++ case kRiscvI8x16ExtractLaneU: ++ case kRiscvI8x16ExtractLaneS: ++ case kRiscvI8x16GeS: ++ case kRiscvI8x16GeU: ++ case kRiscvI8x16GtS: ++ case kRiscvI8x16GtU: ++ case kRiscvI8x16MaxS: ++ case kRiscvI8x16MaxU: ++ case kRiscvI8x16MinS: ++ case kRiscvI8x16MinU: ++ case kRiscvI8x16Mul: ++ case kRiscvI8x16Ne: ++ case kRiscvI8x16Neg: ++ case kRiscvI8x16ReplaceLane: ++ case kRiscvI8x16Shl: ++ case kRiscvI8x16ShrS: ++ case kRiscvI8x16ShrU: ++ case kRiscvI8x16Splat: ++ case kRiscvI8x16Sub: ++ case kRiscvI8x16SubSaturateS: ++ case kRiscvI8x16SubSaturateU: ++ case kRiscvI8x16RoundingAverageU: ++ case kRiscvI8x16Abs: ++ case kRiscvI8x16BitMask: ++ case kRiscvMaxD: ++ case kRiscvMaxS: ++ case kRiscvMinD: ++ case kRiscvMinS: ++ case kRiscvMod32: ++ case kRiscvModU32: ++ case kRiscvMov: ++ case kRiscvMul32: ++ case kRiscvMulD: ++ case kRiscvMulHigh32: ++ case kRiscvMulOvf32: ++ case kRiscvMulS: ++ case kRiscvNegD: ++ case kRiscvNegS: ++ case kRiscvNor: ++ case kRiscvNor32: ++ case kRiscvOr: ++ case kRiscvOr32: ++ case kRiscvPopcnt32: ++ case kRiscvRor32: ++ case kRiscvRoundWD: ++ case kRiscvRoundWS: ++ case kRiscvS128And: ++ case kRiscvS128Or: ++ case kRiscvS128Not: ++ case kRiscvS128Select: ++ case kRiscvS128AndNot: ++ case kRiscvS128Xor: ++ case kRiscvS128Const: ++ case kRiscvS128Zero: ++ case kRiscvS128AllOnes: ++ case kRiscvS16x8InterleaveEven: ++ case kRiscvS16x8InterleaveOdd: ++ case kRiscvS16x8InterleaveLeft: ++ case kRiscvS16x8InterleaveRight: ++ case kRiscvS16x8PackEven: ++ case kRiscvS16x8PackOdd: ++ case kRiscvS16x2Reverse: ++ case kRiscvS16x4Reverse: ++ case kRiscvV8x16AllTrue: ++ case kRiscvV8x16AnyTrue: ++ case kRiscvV32x4AllTrue: ++ case kRiscvV32x4AnyTrue: ++ case kRiscvV16x8AllTrue: ++ case kRiscvV16x8AnyTrue: ++ case kRiscvS32x4InterleaveEven: ++ case kRiscvS32x4InterleaveOdd: ++ case kRiscvS32x4InterleaveLeft: ++ case kRiscvS32x4InterleaveRight: ++ case kRiscvS32x4PackEven: ++ case kRiscvS32x4PackOdd: ++ case kRiscvS32x4Shuffle: ++ case kRiscvS8x16Concat: ++ case kRiscvS8x16InterleaveEven: ++ case kRiscvS8x16InterleaveOdd: ++ case kRiscvS8x16InterleaveLeft: ++ case kRiscvS8x16InterleaveRight: ++ case kRiscvS8x16PackEven: ++ case kRiscvS8x16PackOdd: ++ case kRiscvS8x2Reverse: ++ case kRiscvS8x4Reverse: ++ case kRiscvS8x8Reverse: ++ case kRiscvI8x16Shuffle: ++ case kRiscvI8x16Swizzle: ++ case kRiscvSar32: ++ case kRiscvSignExtendByte: ++ case kRiscvSignExtendShort: ++ case kRiscvShl32: ++ case kRiscvShr32: ++ case kRiscvSqrtD: ++ case kRiscvSqrtS: ++ case kRiscvSub32: ++ case kRiscvSubD: ++ case kRiscvSubS: ++ case kRiscvTruncLD: ++ case kRiscvTruncLS: ++ case kRiscvTruncUlD: ++ case kRiscvTruncUlS: ++ case kRiscvTruncUwD: ++ case kRiscvTruncUwS: ++ case kRiscvTruncWD: ++ case kRiscvTruncWS: ++ case kRiscvTst: ++ case kRiscvXor: ++ case kRiscvXor32: ++ return kNoOpcodeFlags; ++ ++ case kRiscvLb: ++ case kRiscvLbu: ++ case kRiscvLd: ++ case kRiscvLoadDouble: ++ case kRiscvLh: ++ case kRiscvLhu: ++ case kRiscvLw: ++ case kRiscvLoadFloat: ++ case kRiscvLwu: ++ case kRiscvMsaLd: ++ case kRiscvPeek: ++ case kRiscvUld: ++ case kRiscvULoadDouble: ++ case kRiscvUlh: ++ case kRiscvUlhu: ++ case kRiscvUlw: ++ case kRiscvUlwu: ++ case kRiscvULoadFloat: ++ case kRiscvS8x16LoadSplat: ++ case kRiscvS16x8LoadSplat: ++ case kRiscvS32x4LoadSplat: ++ case kRiscvS64x2LoadSplat: ++ case kRiscvI16x8Load8x8S: ++ case kRiscvI16x8Load8x8U: ++ case kRiscvI32x4Load16x4S: ++ case kRiscvI32x4Load16x4U: ++ case kRiscvI64x2Load32x2S: ++ case kRiscvI64x2Load32x2U: ++ case kRiscvWord64AtomicLoadUint8: ++ case kRiscvWord64AtomicLoadUint16: ++ case kRiscvWord64AtomicLoadUint32: ++ case kRiscvWord64AtomicLoadUint64: ++ ++ return kIsLoadOperation; ++ ++ case kRiscvModD: ++ case kRiscvModS: ++ case kRiscvMsaSt: ++ case kRiscvPush: ++ case kRiscvSb: ++ case kRiscvSd: ++ case kRiscvStoreDouble: ++ case kRiscvSh: ++ case kRiscvStackClaim: ++ case kRiscvStoreToStackSlot: ++ case kRiscvSw: ++ case kRiscvStoreFloat: ++ case kRiscvUsd: ++ case kRiscvUStoreDouble: ++ case kRiscvUsh: ++ case kRiscvUsw: ++ case kRiscvUStoreFloat: ++ case kRiscvSync: ++ case kRiscvWord64AtomicStoreWord8: ++ case kRiscvWord64AtomicStoreWord16: ++ case kRiscvWord64AtomicStoreWord32: ++ case kRiscvWord64AtomicStoreWord64: ++ case kRiscvWord64AtomicAddUint8: ++ case kRiscvWord64AtomicAddUint16: ++ case kRiscvWord64AtomicAddUint32: ++ case kRiscvWord64AtomicAddUint64: ++ case kRiscvWord64AtomicSubUint8: ++ case kRiscvWord64AtomicSubUint16: ++ case kRiscvWord64AtomicSubUint32: ++ case kRiscvWord64AtomicSubUint64: ++ case kRiscvWord64AtomicAndUint8: ++ case kRiscvWord64AtomicAndUint16: ++ case kRiscvWord64AtomicAndUint32: ++ case kRiscvWord64AtomicAndUint64: ++ case kRiscvWord64AtomicOrUint8: ++ case kRiscvWord64AtomicOrUint16: ++ case kRiscvWord64AtomicOrUint32: ++ case kRiscvWord64AtomicOrUint64: ++ case kRiscvWord64AtomicXorUint8: ++ case kRiscvWord64AtomicXorUint16: ++ case kRiscvWord64AtomicXorUint32: ++ case kRiscvWord64AtomicXorUint64: ++ case kRiscvWord64AtomicExchangeUint8: ++ case kRiscvWord64AtomicExchangeUint16: ++ case kRiscvWord64AtomicExchangeUint32: ++ case kRiscvWord64AtomicExchangeUint64: ++ case kRiscvWord64AtomicCompareExchangeUint8: ++ case kRiscvWord64AtomicCompareExchangeUint16: ++ case kRiscvWord64AtomicCompareExchangeUint32: ++ case kRiscvWord64AtomicCompareExchangeUint64: ++ return kHasSideEffect; ++ ++#define CASE(Name) case k##Name: ++ COMMON_ARCH_OPCODE_LIST(CASE) ++#undef CASE ++ // Already covered in architecture independent code. ++ UNREACHABLE(); ++ } ++ ++ UNREACHABLE(); ++} ++ ++enum Latency { ++ BRANCH = 4, // Estimated max. ++ RINT_S = 4, // Estimated. ++ RINT_D = 4, // Estimated. ++ ++ // FIXME (RISCV): remove MULT instructions (MIPS legacy) ++ MULT = 4, ++ MULTU = 4, ++ DMULT = 4, ++ ++ MUL32 = 7, ++ ++ DIV32 = 50, // Min:11 Max:50 ++ DIV64 = 50, ++ DIVU32 = 50, ++ DIVU64 = 50, ++ ++ ABS_S = 4, ++ ABS_D = 4, ++ NEG_S = 4, ++ NEG_D = 4, ++ ADD_S = 4, ++ ADD_D = 4, ++ SUB_S = 4, ++ SUB_D = 4, ++ MAX_S = 4, // Estimated. ++ MIN_S = 4, ++ MAX_D = 4, // Estimated. ++ MIN_D = 4, ++ C_cond_S = 4, ++ C_cond_D = 4, ++ MUL_S = 4, ++ ++ MADD_S = 4, ++ MSUB_S = 4, ++ NMADD_S = 4, ++ NMSUB_S = 4, ++ ++ CABS_cond_S = 4, ++ CABS_cond_D = 4, ++ ++ CVT_D_S = 4, ++ CVT_PS_PW = 4, ++ ++ CVT_S_W = 4, ++ CVT_S_L = 4, ++ CVT_D_W = 4, ++ CVT_D_L = 4, ++ ++ CVT_S_D = 4, ++ ++ CVT_W_S = 4, ++ CVT_W_D = 4, ++ CVT_L_S = 4, ++ CVT_L_D = 4, ++ ++ CEIL_W_S = 4, ++ CEIL_W_D = 4, ++ CEIL_L_S = 4, ++ CEIL_L_D = 4, ++ ++ FLOOR_W_S = 4, ++ FLOOR_W_D = 4, ++ FLOOR_L_S = 4, ++ FLOOR_L_D = 4, ++ ++ ROUND_W_S = 4, ++ ROUND_W_D = 4, ++ ROUND_L_S = 4, ++ ROUND_L_D = 4, ++ ++ TRUNC_W_S = 4, ++ TRUNC_W_D = 4, ++ TRUNC_L_S = 4, ++ TRUNC_L_D = 4, ++ ++ MOV_S = 4, ++ MOV_D = 4, ++ ++ MOVF_S = 4, ++ MOVF_D = 4, ++ ++ MOVN_S = 4, ++ MOVN_D = 4, ++ ++ MOVT_S = 4, ++ MOVT_D = 4, ++ ++ MOVZ_S = 4, ++ MOVZ_D = 4, ++ ++ MUL_D = 5, ++ MADD_D = 5, ++ MSUB_D = 5, ++ NMADD_D = 5, ++ NMSUB_D = 5, ++ ++ RECIP_S = 13, ++ RECIP_D = 26, ++ ++ RSQRT_S = 17, ++ RSQRT_D = 36, ++ ++ DIV_S = 17, ++ SQRT_S = 17, ++ ++ DIV_D = 32, ++ SQRT_D = 32, ++ ++ MOVT_FREG = 4, ++ MOVT_HIGH_FREG = 4, ++ MOVT_DREG = 4, ++ LOAD_FLOAT = 4, ++ LOAD_DOUBLE = 4, ++ ++ MOVF_FREG = 1, ++ MOVF_HIGH_FREG = 1, ++ MOVF_HIGH_DREG = 1, ++ MOVF_HIGH = 1, ++ MOVF_LOW = 1, ++ STORE_FLOAT = 1, ++ STORE_DOUBLE = 1, ++}; ++ ++int Add64Latency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return 1; ++ } else { ++ return 2; // Estimated max. ++ } ++} ++ ++int Sub64Latency(bool is_operand_register = true) { ++ return Add64Latency(is_operand_register); ++} ++ ++int AndLatency(bool is_operand_register = true) { ++ return Add64Latency(is_operand_register); ++} ++ ++int OrLatency(bool is_operand_register = true) { ++ return Add64Latency(is_operand_register); ++} ++ ++int NorLatency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return 1; ++ } else { ++ return 2; // Estimated max. ++ } ++} ++ ++int XorLatency(bool is_operand_register = true) { ++ return Add64Latency(is_operand_register); ++} ++ ++int Mul32Latency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return Latency::MUL32; ++ } else { ++ return Latency::MUL32 + 1; ++ } ++} ++ ++int Mul64Latency(bool is_operand_register = true) { ++ int latency = Latency::DMULT + Latency::MOVF_LOW; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Mulh32Latency(bool is_operand_register = true) { ++ int latency = Latency::MULT + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Mulhu32Latency(bool is_operand_register = true) { ++ int latency = Latency::MULTU + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Mulh64Latency(bool is_operand_register = true) { ++ int latency = Latency::DMULT + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Div32Latency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return Latency::DIV32; ++ } else { ++ return Latency::DIV32 + 1; ++ } ++} ++ ++int Divu32Latency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return Latency::DIVU32; ++ } else { ++ return Latency::DIVU32 + 1; ++ } ++} ++ ++int Div64Latency(bool is_operand_register = true) { ++ int latency = Latency::DIV64 + Latency::MOVF_LOW; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Divu64Latency(bool is_operand_register = true) { ++ int latency = Latency::DIVU64 + Latency::MOVF_LOW; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Mod32Latency(bool is_operand_register = true) { ++ int latency = Latency::DIV32 + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Modu32Latency(bool is_operand_register = true) { ++ int latency = Latency::DIVU32 + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Mod64Latency(bool is_operand_register = true) { ++ int latency = Latency::DIV64 + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int Modu64Latency(bool is_operand_register = true) { ++ int latency = Latency::DIV64 + Latency::MOVF_HIGH; ++ if (!is_operand_register) { ++ latency += 1; ++ } ++ return latency; ++} ++ ++int MovzLatency() { return 1; } ++ ++int MovnLatency() { return 1; } ++ ++int CallLatency() { ++ // Estimated. ++ return Add64Latency(false) + Latency::BRANCH + 5; ++} ++ ++int JumpLatency() { ++ // Estimated max. ++ return 1 + Add64Latency() + Latency::BRANCH + 2; ++} ++ ++int SmiUntagLatency() { return 1; } ++ ++int PrepareForTailCallLatency() { ++ // Estimated max. ++ return 2 * (Add64Latency() + 1 + Add64Latency(false)) + 2 + Latency::BRANCH + ++ Latency::BRANCH + 2 * Sub64Latency(false) + 2 + Latency::BRANCH + 1; ++} ++ ++int AssemblePopArgumentsAdoptFrameLatency() { ++ return 1 + Latency::BRANCH + 1 + SmiUntagLatency() + ++ PrepareForTailCallLatency(); ++} ++ ++int AssertLatency() { return 1; } ++ ++int PrepareCallCFunctionLatency() { ++ int frame_alignment = TurboAssembler::ActivationFrameAlignment(); ++ if (frame_alignment > kSystemPointerSize) { ++ return 1 + Sub64Latency(false) + AndLatency(false) + 1; ++ } else { ++ return Sub64Latency(false); ++ } ++} ++ ++int AdjustBaseAndOffsetLatency() { ++ return 3; // Estimated max. ++} ++ ++int AlignedMemoryLatency() { return AdjustBaseAndOffsetLatency() + 1; } ++ ++int UlhuLatency() { ++ return AdjustBaseAndOffsetLatency() + 2 * AlignedMemoryLatency() + 2; ++} ++ ++int UlwLatency() { ++ // Estimated max. ++ return AdjustBaseAndOffsetLatency() + 3; ++} ++ ++int UlwuLatency() { return UlwLatency() + 1; } ++ ++int UldLatency() { ++ // Estimated max. ++ return AdjustBaseAndOffsetLatency() + 3; ++} ++ ++int ULoadFloatLatency() { return UlwLatency() + Latency::MOVT_FREG; } ++ ++int ULoadDoubleLatency() { return UldLatency() + Latency::MOVT_DREG; } ++ ++int UshLatency() { ++ // Estimated max. ++ return AdjustBaseAndOffsetLatency() + 2 + 2 * AlignedMemoryLatency(); ++} ++ ++int UswLatency() { return AdjustBaseAndOffsetLatency() + 2; } ++ ++int UsdLatency() { return AdjustBaseAndOffsetLatency() + 2; } ++ ++int UStoreFloatLatency() { return Latency::MOVF_FREG + UswLatency(); } ++ ++int UStoreDoubleLatency() { return Latency::MOVF_HIGH_DREG + UsdLatency(); } ++ ++int LoadFloatLatency() { ++ return AdjustBaseAndOffsetLatency() + Latency::LOAD_FLOAT; ++} ++ ++int StoreFloatLatency() { ++ return AdjustBaseAndOffsetLatency() + Latency::STORE_FLOAT; ++} ++ ++int StoreDoubleLatency() { ++ return AdjustBaseAndOffsetLatency() + Latency::STORE_DOUBLE; ++} ++ ++int LoadDoubleLatency() { ++ return AdjustBaseAndOffsetLatency() + Latency::LOAD_DOUBLE; ++} ++ ++int MultiPushLatency() { ++ int latency = Sub64Latency(false); ++ for (int16_t i = kNumRegisters - 1; i >= 0; i--) { ++ latency++; ++ } ++ return latency; ++} ++ ++int MultiPushFPULatency() { ++ int latency = Sub64Latency(false); ++ for (int16_t i = kNumRegisters - 1; i >= 0; i--) { ++ latency += StoreDoubleLatency(); ++ } ++ return latency; ++} ++ ++int PushCallerSavedLatency(SaveFPRegsMode fp_mode) { ++ int latency = MultiPushLatency(); ++ if (fp_mode == kSaveFPRegs) { ++ latency += MultiPushFPULatency(); ++ } ++ return latency; ++} ++ ++int MultiPopLatency() { ++ int latency = Add64Latency(false); ++ for (int16_t i = 0; i < kNumRegisters; i++) { ++ latency++; ++ } ++ return latency; ++} ++ ++int MultiPopFPULatency() { ++ int latency = Add64Latency(false); ++ for (int16_t i = 0; i < kNumRegisters; i++) { ++ latency += LoadDoubleLatency(); ++ } ++ return latency; ++} ++ ++int PopCallerSavedLatency(SaveFPRegsMode fp_mode) { ++ int latency = MultiPopLatency(); ++ if (fp_mode == kSaveFPRegs) { ++ latency += MultiPopFPULatency(); ++ } ++ return latency; ++} ++ ++int CallCFunctionHelperLatency() { ++ // Estimated. ++ int latency = AndLatency(false) + Latency::BRANCH + 2 + CallLatency(); ++ if (base::OS::ActivationFrameAlignment() > kSystemPointerSize) { ++ latency++; ++ } else { ++ latency += Add64Latency(false); ++ } ++ return latency; ++} ++ ++int CallCFunctionLatency() { return 1 + CallCFunctionHelperLatency(); } ++ ++int AssembleArchJumpLatency() { ++ // Estimated max. ++ return Latency::BRANCH; ++} ++ ++int GenerateSwitchTableLatency() { ++ int latency = 6; ++ latency += 2; ++ return latency; ++} ++ ++int AssembleArchTableSwitchLatency() { ++ return Latency::BRANCH + GenerateSwitchTableLatency(); ++} ++ ++int DropAndRetLatency() { ++ // Estimated max. ++ return Add64Latency(false) + JumpLatency(); ++} ++ ++int AssemblerReturnLatency() { ++ // Estimated max. ++ return Add64Latency(false) + MultiPopLatency() + MultiPopFPULatency() + ++ Latency::BRANCH + Add64Latency() + 1 + DropAndRetLatency(); ++} ++ ++int TryInlineTruncateDoubleToILatency() { ++ return 2 + Latency::TRUNC_W_D + Latency::MOVF_FREG + 2 + AndLatency(false) + ++ Latency::BRANCH; ++} ++ ++int CallStubDelayedLatency() { return 1 + CallLatency(); } ++ ++int TruncateDoubleToIDelayedLatency() { ++ // TODO(riscv): This no longer reflects how TruncateDoubleToI is called. ++ return TryInlineTruncateDoubleToILatency() + 1 + Sub64Latency(false) + ++ StoreDoubleLatency() + CallStubDelayedLatency() + Add64Latency(false) + ++ 1; ++} ++ ++int CheckPageFlagLatency() { ++ return AndLatency(false) + AlignedMemoryLatency() + AndLatency(false) + ++ Latency::BRANCH; ++} ++ ++int SltuLatency(bool is_operand_register = true) { ++ if (is_operand_register) { ++ return 1; ++ } else { ++ return 2; // Estimated max. ++ } ++} ++ ++int BranchShortHelperLatency() { ++ return SltuLatency() + 2; // Estimated max. ++} ++ ++int BranchShortLatency() { return BranchShortHelperLatency(); } ++ ++int MoveLatency() { return 1; } ++ ++int MovToFloatParametersLatency() { return 2 * MoveLatency(); } ++ ++int MovFromFloatResultLatency() { return MoveLatency(); } ++ ++int AddOverflow64Latency() { ++ // Estimated max. ++ return 6; ++} ++ ++int SubOverflow64Latency() { ++ // Estimated max. ++ return 6; ++} ++ ++int MulOverflow32Latency() { ++ // Estimated max. ++ return Mul32Latency() + Mulh32Latency() + 2; ++} ++ ++// FIXME (RISCV): need update ++int Clz64Latency() { return 1; } ++ ++int Ctz32Latency() { ++ return Add64Latency(false) + XorLatency() + AndLatency() + Clz64Latency() + ++ 1 + Sub64Latency(); ++} ++ ++int Ctz64Latency() { ++ return Add64Latency(false) + XorLatency() + AndLatency() + 1 + Sub64Latency(); ++} ++ ++int Popcnt32Latency() { ++ return 2 + AndLatency() + Sub64Latency() + 1 + AndLatency() + 1 + ++ AndLatency() + Add64Latency() + 1 + Add64Latency() + 1 + AndLatency() + ++ 1 + Mul32Latency() + 1; ++} ++ ++int Popcnt64Latency() { ++ return 2 + AndLatency() + Sub64Latency() + 1 + AndLatency() + 1 + ++ AndLatency() + Add64Latency() + 1 + Add64Latency() + 1 + AndLatency() + ++ 1 + Mul64Latency() + 1; ++} ++ ++int CompareFLatency() { return Latency::C_cond_S; } ++ ++int CompareF32Latency() { return CompareFLatency(); } ++ ++int CompareF64Latency() { return CompareFLatency(); } ++ ++int CompareIsNanFLatency() { return CompareFLatency(); } ++ ++int CompareIsNanF32Latency() { return CompareIsNanFLatency(); } ++ ++int CompareIsNanF64Latency() { return CompareIsNanFLatency(); } ++ ++int NegsLatency() { ++ // Estimated. ++ return CompareIsNanF32Latency() + 2 * Latency::BRANCH + Latency::NEG_S + ++ Latency::MOVF_FREG + 1 + XorLatency() + Latency::MOVT_FREG; ++} ++ ++int NegdLatency() { ++ // Estimated. ++ return CompareIsNanF64Latency() + 2 * Latency::BRANCH + Latency::NEG_D + ++ Latency::MOVF_HIGH_DREG + 1 + XorLatency() + Latency::MOVT_DREG; ++} ++ ++int Float64RoundLatency() { ++ // For ceil_l_d, floor_l_d, round_l_d, trunc_l_d latency is 4. ++ return Latency::MOVF_HIGH_DREG + 1 + Latency::BRANCH + Latency::MOV_D + 4 + ++ Latency::MOVF_HIGH_DREG + Latency::BRANCH + Latency::CVT_D_L + 2 + ++ Latency::MOVT_HIGH_FREG; ++} ++ ++int Float32RoundLatency() { ++ // For ceil_w_s, floor_w_s, round_w_s, trunc_w_s latency is 4. ++ return Latency::MOVF_FREG + 1 + Latency::BRANCH + Latency::MOV_S + 4 + ++ Latency::MOVF_FREG + Latency::BRANCH + Latency::CVT_S_W + 2 + ++ Latency::MOVT_FREG; ++} ++ ++int Float32MaxLatency() { ++ // Estimated max. ++ int latency = CompareIsNanF32Latency() + Latency::BRANCH; ++ return latency + 5 * Latency::BRANCH + 2 * CompareF32Latency() + ++ Latency::MOVF_FREG + 1 + Latency::MOV_S; ++} ++ ++int Float64MaxLatency() { ++ // Estimated max. ++ int latency = CompareIsNanF64Latency() + Latency::BRANCH; ++ return latency + 5 * Latency::BRANCH + 2 * CompareF64Latency() + ++ Latency::MOVF_HIGH_DREG + Latency::MOV_D; ++} ++ ++int Float32MinLatency() { ++ // Estimated max. ++ int latency = CompareIsNanF32Latency() + Latency::BRANCH; ++ return latency + 5 * Latency::BRANCH + 2 * CompareF32Latency() + ++ Latency::MOVF_FREG + 1 + Latency::MOV_S; ++} ++ ++int Float64MinLatency() { ++ // Estimated max. ++ int latency = CompareIsNanF64Latency() + Latency::BRANCH; ++ return latency + 5 * Latency::BRANCH + 2 * CompareF32Latency() + ++ Latency::MOVF_HIGH_DREG + Latency::MOV_D; ++} ++ ++int TruncLSLatency(bool load_status) { ++ int latency = Latency::TRUNC_L_S + Latency::MOVF_HIGH_DREG; ++ if (load_status) { ++ latency += SltuLatency() + 7; ++ } ++ return latency; ++} ++ ++int TruncLDLatency(bool load_status) { ++ int latency = Latency::TRUNC_L_D + Latency::MOVF_HIGH_DREG; ++ if (load_status) { ++ latency += SltuLatency() + 7; ++ } ++ return latency; ++} ++ ++int TruncUlSLatency() { ++ // Estimated max. ++ return 2 * CompareF32Latency() + CompareIsNanF32Latency() + ++ 4 * Latency::BRANCH + Latency::SUB_S + 2 * Latency::TRUNC_L_S + ++ 3 * Latency::MOVF_HIGH_DREG + OrLatency() + Latency::MOVT_FREG + ++ Latency::MOV_S + SltuLatency() + 4; ++} ++ ++int TruncUlDLatency() { ++ // Estimated max. ++ return 2 * CompareF64Latency() + CompareIsNanF64Latency() + ++ 4 * Latency::BRANCH + Latency::SUB_D + 2 * Latency::TRUNC_L_D + ++ 3 * Latency::MOVF_HIGH_DREG + OrLatency() + Latency::MOVT_DREG + ++ Latency::MOV_D + SltuLatency() + 4; ++} ++ ++int PushLatency() { return Add64Latency() + AlignedMemoryLatency(); } ++ ++int ByteSwapSignedLatency() { return 2; } ++ ++int LlLatency(int offset) { ++ bool is_one_instruction = is_int12(offset); ++ if (is_one_instruction) { ++ return 1; ++ } else { ++ return 3; ++ } ++} ++ ++int ExtractBitsLatency(bool sign_extend, int size) { ++ int latency = 2; ++ if (sign_extend) { ++ switch (size) { ++ case 8: ++ case 16: ++ case 32: ++ latency += 1; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++ return latency; ++} ++ ++int InsertBitsLatency() { return 2 + Sub64Latency(false) + 2; } ++ ++int ScLatency(int offset) { return 3; } ++ ++int Word32AtomicExchangeLatency(bool sign_extend, int size) { ++ return Add64Latency(false) + 1 + Sub64Latency() + 2 + LlLatency(0) + ++ ExtractBitsLatency(sign_extend, size) + InsertBitsLatency() + ++ ScLatency(0) + BranchShortLatency() + 1; ++} ++ ++int Word32AtomicCompareExchangeLatency(bool sign_extend, int size) { ++ return 2 + Sub64Latency() + 2 + LlLatency(0) + ++ ExtractBitsLatency(sign_extend, size) + InsertBitsLatency() + ++ ScLatency(0) + BranchShortLatency() + 1; ++} ++ ++int InstructionScheduler::GetInstructionLatency(const Instruction* instr) { ++ // FIXME(RISCV): Verify these latencies for RISC-V (currently using MIPS ++ // numbers) ++ switch (instr->arch_opcode()) { ++ case kArchCallCodeObject: ++ case kArchCallWasmFunction: ++ return CallLatency(); ++ case kArchTailCallCodeObjectFromJSFunction: ++ case kArchTailCallCodeObject: { ++ int latency = 0; ++ if (instr->arch_opcode() == kArchTailCallCodeObjectFromJSFunction) { ++ latency = AssemblePopArgumentsAdoptFrameLatency(); ++ } ++ return latency + JumpLatency(); ++ } ++ case kArchTailCallWasm: ++ case kArchTailCallAddress: ++ return JumpLatency(); ++ case kArchCallJSFunction: { ++ int latency = 0; ++ if (FLAG_debug_code) { ++ latency = 1 + AssertLatency(); ++ } ++ return latency + 1 + Add64Latency(false) + CallLatency(); ++ } ++ case kArchPrepareCallCFunction: ++ return PrepareCallCFunctionLatency(); ++ case kArchSaveCallerRegisters: { ++ auto fp_mode = ++ static_cast(MiscField::decode(instr->opcode())); ++ return PushCallerSavedLatency(fp_mode); ++ } ++ case kArchRestoreCallerRegisters: { ++ auto fp_mode = ++ static_cast(MiscField::decode(instr->opcode())); ++ return PopCallerSavedLatency(fp_mode); ++ } ++ case kArchPrepareTailCall: ++ return 2; ++ case kArchCallCFunction: ++ return CallCFunctionLatency(); ++ case kArchJmp: ++ return AssembleArchJumpLatency(); ++ case kArchTableSwitch: ++ return AssembleArchTableSwitchLatency(); ++ case kArchAbortCSAAssert: ++ return CallLatency() + 1; ++ case kArchDebugBreak: ++ return 1; ++ case kArchComment: ++ case kArchNop: ++ case kArchThrowTerminator: ++ case kArchDeoptimize: ++ return 0; ++ case kArchRet: ++ return AssemblerReturnLatency(); ++ case kArchFramePointer: ++ return 1; ++ case kArchParentFramePointer: ++ // Estimated max. ++ return AlignedMemoryLatency(); ++ case kArchTruncateDoubleToI: ++ return TruncateDoubleToIDelayedLatency(); ++ case kArchStoreWithWriteBarrier: ++ return Add64Latency() + 1 + CheckPageFlagLatency(); ++ case kArchStackSlot: ++ // Estimated max. ++ return Add64Latency(false) + AndLatency(false) + AssertLatency() + ++ Add64Latency(false) + AndLatency(false) + BranchShortLatency() + ++ 1 + Sub64Latency() + Add64Latency(); ++ case kArchWordPoisonOnSpeculation: ++ return AndLatency(); ++ case kIeee754Float64Acos: ++ case kIeee754Float64Acosh: ++ case kIeee754Float64Asin: ++ case kIeee754Float64Asinh: ++ case kIeee754Float64Atan: ++ case kIeee754Float64Atanh: ++ case kIeee754Float64Atan2: ++ case kIeee754Float64Cos: ++ case kIeee754Float64Cosh: ++ case kIeee754Float64Cbrt: ++ case kIeee754Float64Exp: ++ case kIeee754Float64Expm1: ++ case kIeee754Float64Log: ++ case kIeee754Float64Log1p: ++ case kIeee754Float64Log10: ++ case kIeee754Float64Log2: ++ case kIeee754Float64Pow: ++ case kIeee754Float64Sin: ++ case kIeee754Float64Sinh: ++ case kIeee754Float64Tan: ++ case kIeee754Float64Tanh: ++ return PrepareCallCFunctionLatency() + MovToFloatParametersLatency() + ++ CallCFunctionLatency() + MovFromFloatResultLatency(); ++ case kRiscvAdd32: ++ case kRiscvAdd64: ++ return Add64Latency(instr->InputAt(1)->IsRegister()); ++ case kRiscvAddOvf64: ++ return AddOverflow64Latency(); ++ case kRiscvSub32: ++ case kRiscvSub64: ++ return Sub64Latency(instr->InputAt(1)->IsRegister()); ++ case kRiscvSubOvf64: ++ return SubOverflow64Latency(); ++ case kRiscvMul32: ++ return Mul32Latency(); ++ case kRiscvMulOvf32: ++ return MulOverflow32Latency(); ++ case kRiscvMulHigh32: ++ return Mulh32Latency(); ++ case kRiscvMulHighU32: ++ return Mulhu32Latency(); ++ case kRiscvMulHigh64: ++ return Mulh64Latency(); ++ case kRiscvDiv32: { ++ int latency = Div32Latency(instr->InputAt(1)->IsRegister()); ++ return latency + MovzLatency(); ++ } ++ case kRiscvDivU32: { ++ int latency = Divu32Latency(instr->InputAt(1)->IsRegister()); ++ return latency + MovzLatency(); ++ } ++ case kRiscvMod32: ++ return Mod32Latency(); ++ case kRiscvModU32: ++ return Modu32Latency(); ++ case kRiscvMul64: ++ return Mul64Latency(); ++ case kRiscvDiv64: { ++ int latency = Div64Latency(); ++ return latency + MovzLatency(); ++ } ++ case kRiscvDivU64: { ++ int latency = Divu64Latency(); ++ return latency + MovzLatency(); ++ } ++ case kRiscvMod64: ++ return Mod64Latency(); ++ case kRiscvModU64: ++ return Modu64Latency(); ++ case kRiscvAnd: ++ return AndLatency(instr->InputAt(1)->IsRegister()); ++ case kRiscvAnd32: { ++ bool is_operand_register = instr->InputAt(1)->IsRegister(); ++ int latency = AndLatency(is_operand_register); ++ if (is_operand_register) { ++ return latency + 2; ++ } else { ++ return latency + 1; ++ } ++ } ++ case kRiscvOr: ++ return OrLatency(instr->InputAt(1)->IsRegister()); ++ case kRiscvOr32: { ++ bool is_operand_register = instr->InputAt(1)->IsRegister(); ++ int latency = OrLatency(is_operand_register); ++ if (is_operand_register) { ++ return latency + 2; ++ } else { ++ return latency + 1; ++ } ++ } ++ case kRiscvNor: ++ return NorLatency(instr->InputAt(1)->IsRegister()); ++ case kRiscvNor32: { ++ bool is_operand_register = instr->InputAt(1)->IsRegister(); ++ int latency = NorLatency(is_operand_register); ++ if (is_operand_register) { ++ return latency + 2; ++ } else { ++ return latency + 1; ++ } ++ } ++ case kRiscvXor: ++ return XorLatency(instr->InputAt(1)->IsRegister()); ++ case kRiscvXor32: { ++ bool is_operand_register = instr->InputAt(1)->IsRegister(); ++ int latency = XorLatency(is_operand_register); ++ if (is_operand_register) { ++ return latency + 2; ++ } else { ++ return latency + 1; ++ } ++ } ++ case kRiscvClz32: ++ case kRiscvClz64: ++ return Clz64Latency(); ++ case kRiscvCtz32: ++ return Ctz32Latency(); ++ case kRiscvCtz64: ++ return Ctz64Latency(); ++ case kRiscvPopcnt32: ++ return Popcnt32Latency(); ++ case kRiscvPopcnt64: ++ return Popcnt64Latency(); ++ case kRiscvShl32: ++ return 1; ++ case kRiscvShr32: ++ case kRiscvSar32: ++ case kRiscvZeroExtendWord: ++ return 2; ++ case kRiscvSignExtendWord: ++ case kRiscvShl64: ++ case kRiscvShr64: ++ case kRiscvSar64: ++ case kRiscvRor32: ++ case kRiscvRor64: ++ return 1; ++ case kRiscvTst: ++ return AndLatency(instr->InputAt(1)->IsRegister()); ++ case kRiscvMov: ++ return 1; ++ case kRiscvCmpS: ++ return MoveLatency() + CompareF32Latency(); ++ case kRiscvAddS: ++ return Latency::ADD_S; ++ case kRiscvSubS: ++ return Latency::SUB_S; ++ case kRiscvMulS: ++ return Latency::MUL_S; ++ case kRiscvDivS: ++ return Latency::DIV_S; ++ case kRiscvModS: ++ return PrepareCallCFunctionLatency() + MovToFloatParametersLatency() + ++ CallCFunctionLatency() + MovFromFloatResultLatency(); ++ case kRiscvAbsS: ++ return Latency::ABS_S; ++ case kRiscvNegS: ++ return NegdLatency(); ++ case kRiscvSqrtS: ++ return Latency::SQRT_S; ++ case kRiscvMaxS: ++ return Latency::MAX_S; ++ case kRiscvMinS: ++ return Latency::MIN_S; ++ case kRiscvCmpD: ++ return MoveLatency() + CompareF64Latency(); ++ case kRiscvAddD: ++ return Latency::ADD_D; ++ case kRiscvSubD: ++ return Latency::SUB_D; ++ case kRiscvMulD: ++ return Latency::MUL_D; ++ case kRiscvDivD: ++ return Latency::DIV_D; ++ case kRiscvModD: ++ return PrepareCallCFunctionLatency() + MovToFloatParametersLatency() + ++ CallCFunctionLatency() + MovFromFloatResultLatency(); ++ case kRiscvAbsD: ++ return Latency::ABS_D; ++ case kRiscvNegD: ++ return NegdLatency(); ++ case kRiscvSqrtD: ++ return Latency::SQRT_D; ++ case kRiscvMaxD: ++ return Latency::MAX_D; ++ case kRiscvMinD: ++ return Latency::MIN_D; ++ case kRiscvFloat64RoundDown: ++ case kRiscvFloat64RoundTruncate: ++ case kRiscvFloat64RoundUp: ++ case kRiscvFloat64RoundTiesEven: ++ return Float64RoundLatency(); ++ case kRiscvFloat32RoundDown: ++ case kRiscvFloat32RoundTruncate: ++ case kRiscvFloat32RoundUp: ++ case kRiscvFloat32RoundTiesEven: ++ return Float32RoundLatency(); ++ case kRiscvFloat32Max: ++ return Float32MaxLatency(); ++ case kRiscvFloat64Max: ++ return Float64MaxLatency(); ++ case kRiscvFloat32Min: ++ return Float32MinLatency(); ++ case kRiscvFloat64Min: ++ return Float64MinLatency(); ++ case kRiscvFloat64SilenceNaN: ++ return Latency::SUB_D; ++ case kRiscvCvtSD: ++ return Latency::CVT_S_D; ++ case kRiscvCvtDS: ++ return Latency::CVT_D_S; ++ case kRiscvCvtDW: ++ return Latency::MOVT_FREG + Latency::CVT_D_W; ++ case kRiscvCvtSW: ++ return Latency::MOVT_FREG + Latency::CVT_S_W; ++ case kRiscvCvtSUw: ++ return 1 + Latency::MOVT_DREG + Latency::CVT_S_L; ++ case kRiscvCvtSL: ++ return Latency::MOVT_DREG + Latency::CVT_S_L; ++ case kRiscvCvtDL: ++ return Latency::MOVT_DREG + Latency::CVT_D_L; ++ case kRiscvCvtDUw: ++ return 1 + Latency::MOVT_DREG + Latency::CVT_D_L; ++ case kRiscvCvtDUl: ++ return 2 * Latency::BRANCH + 3 + 2 * Latency::MOVT_DREG + ++ 2 * Latency::CVT_D_L + Latency::ADD_D; ++ case kRiscvCvtSUl: ++ return 2 * Latency::BRANCH + 3 + 2 * Latency::MOVT_DREG + ++ 2 * Latency::CVT_S_L + Latency::ADD_S; ++ case kRiscvFloorWD: ++ return Latency::FLOOR_W_D + Latency::MOVF_FREG; ++ case kRiscvCeilWD: ++ return Latency::CEIL_W_D + Latency::MOVF_FREG; ++ case kRiscvRoundWD: ++ return Latency::ROUND_W_D + Latency::MOVF_FREG; ++ case kRiscvTruncWD: ++ return Latency::TRUNC_W_D + Latency::MOVF_FREG; ++ case kRiscvFloorWS: ++ return Latency::FLOOR_W_S + Latency::MOVF_FREG; ++ case kRiscvCeilWS: ++ return Latency::CEIL_W_S + Latency::MOVF_FREG; ++ case kRiscvRoundWS: ++ return Latency::ROUND_W_S + Latency::MOVF_FREG; ++ case kRiscvTruncWS: ++ return Latency::TRUNC_W_S + Latency::MOVF_FREG + 2 + MovnLatency(); ++ case kRiscvTruncLS: ++ return TruncLSLatency(instr->OutputCount() > 1); ++ case kRiscvTruncLD: ++ return TruncLDLatency(instr->OutputCount() > 1); ++ case kRiscvTruncUwD: ++ // Estimated max. ++ return CompareF64Latency() + 2 * Latency::BRANCH + ++ 2 * Latency::TRUNC_W_D + Latency::SUB_D + OrLatency() + ++ Latency::MOVT_FREG + Latency::MOVF_FREG + Latency::MOVT_HIGH_FREG + ++ 1; ++ case kRiscvTruncUwS: ++ // Estimated max. ++ return CompareF32Latency() + 2 * Latency::BRANCH + ++ 2 * Latency::TRUNC_W_S + Latency::SUB_S + OrLatency() + ++ Latency::MOVT_FREG + 2 * Latency::MOVF_FREG + 2 + MovzLatency(); ++ case kRiscvTruncUlS: ++ return TruncUlSLatency(); ++ case kRiscvTruncUlD: ++ return TruncUlDLatency(); ++ case kRiscvBitcastDL: ++ return Latency::MOVF_HIGH_DREG; ++ case kRiscvBitcastLD: ++ return Latency::MOVT_DREG; ++ case kRiscvFloat64ExtractLowWord32: ++ return Latency::MOVF_FREG; ++ case kRiscvFloat64InsertLowWord32: ++ return Latency::MOVF_HIGH_FREG + Latency::MOVT_FREG + ++ Latency::MOVT_HIGH_FREG; ++ case kRiscvFloat64ExtractHighWord32: ++ return Latency::MOVF_HIGH_FREG; ++ case kRiscvFloat64InsertHighWord32: ++ return Latency::MOVT_HIGH_FREG; ++ case kRiscvSignExtendByte: ++ case kRiscvSignExtendShort: ++ return 1; ++ case kRiscvLbu: ++ case kRiscvLb: ++ case kRiscvLhu: ++ case kRiscvLh: ++ case kRiscvLwu: ++ case kRiscvLw: ++ case kRiscvLd: ++ case kRiscvSb: ++ case kRiscvSh: ++ case kRiscvSw: ++ case kRiscvSd: ++ return AlignedMemoryLatency(); ++ case kRiscvLoadFloat: ++ return ULoadFloatLatency(); ++ case kRiscvLoadDouble: ++ return LoadDoubleLatency(); ++ case kRiscvStoreFloat: ++ return StoreFloatLatency(); ++ case kRiscvStoreDouble: ++ return StoreDoubleLatency(); ++ case kRiscvUlhu: ++ case kRiscvUlh: ++ return UlhuLatency(); ++ case kRiscvUlwu: ++ return UlwuLatency(); ++ case kRiscvUlw: ++ return UlwLatency(); ++ case kRiscvUld: ++ return UldLatency(); ++ case kRiscvULoadFloat: ++ return ULoadFloatLatency(); ++ case kRiscvULoadDouble: ++ return ULoadDoubleLatency(); ++ case kRiscvUsh: ++ return UshLatency(); ++ case kRiscvUsw: ++ return UswLatency(); ++ case kRiscvUsd: ++ return UsdLatency(); ++ case kRiscvUStoreFloat: ++ return UStoreFloatLatency(); ++ case kRiscvUStoreDouble: ++ return UStoreDoubleLatency(); ++ case kRiscvPush: { ++ int latency = 0; ++ if (instr->InputAt(0)->IsFPRegister()) { ++ latency = StoreDoubleLatency() + Sub64Latency(false); ++ } else { ++ latency = PushLatency(); ++ } ++ return latency; ++ } ++ case kRiscvPeek: { ++ int latency = 0; ++ if (instr->OutputAt(0)->IsFPRegister()) { ++ auto op = LocationOperand::cast(instr->OutputAt(0)); ++ switch (op->representation()) { ++ case MachineRepresentation::kFloat64: ++ latency = LoadDoubleLatency(); ++ break; ++ case MachineRepresentation::kFloat32: ++ latency = Latency::LOAD_FLOAT; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } else { ++ latency = AlignedMemoryLatency(); ++ } ++ return latency; ++ } ++ case kRiscvStackClaim: ++ return Sub64Latency(false); ++ case kRiscvStoreToStackSlot: { ++ int latency = 0; ++ if (instr->InputAt(0)->IsFPRegister()) { ++ if (instr->InputAt(0)->IsSimd128Register()) { ++ latency = 1; // Estimated value. ++ } else { ++ latency = StoreDoubleLatency(); ++ } ++ } else { ++ latency = AlignedMemoryLatency(); ++ } ++ return latency; ++ } ++ case kRiscvByteSwap64: ++ return ByteSwapSignedLatency(); ++ case kRiscvByteSwap32: ++ return ByteSwapSignedLatency(); ++ case kWord32AtomicLoadInt8: ++ case kWord32AtomicLoadUint8: ++ case kWord32AtomicLoadInt16: ++ case kWord32AtomicLoadUint16: ++ case kWord32AtomicLoadWord32: ++ return 2; ++ case kWord32AtomicStoreWord8: ++ case kWord32AtomicStoreWord16: ++ case kWord32AtomicStoreWord32: ++ return 3; ++ case kWord32AtomicExchangeInt8: ++ return Word32AtomicExchangeLatency(true, 8); ++ case kWord32AtomicExchangeUint8: ++ return Word32AtomicExchangeLatency(false, 8); ++ case kWord32AtomicExchangeInt16: ++ return Word32AtomicExchangeLatency(true, 16); ++ case kWord32AtomicExchangeUint16: ++ return Word32AtomicExchangeLatency(false, 16); ++ case kWord32AtomicExchangeWord32: ++ return 2 + LlLatency(0) + 1 + ScLatency(0) + BranchShortLatency() + 1; ++ case kWord32AtomicCompareExchangeInt8: ++ return Word32AtomicCompareExchangeLatency(true, 8); ++ case kWord32AtomicCompareExchangeUint8: ++ return Word32AtomicCompareExchangeLatency(false, 8); ++ case kWord32AtomicCompareExchangeInt16: ++ return Word32AtomicCompareExchangeLatency(true, 16); ++ case kWord32AtomicCompareExchangeUint16: ++ return Word32AtomicCompareExchangeLatency(false, 16); ++ case kWord32AtomicCompareExchangeWord32: ++ return 3 + LlLatency(0) + BranchShortLatency() + 1 + ScLatency(0) + ++ BranchShortLatency() + 1; ++ case kRiscvAssertEqual: ++ return AssertLatency(); ++ default: ++ return 1; ++ } ++} ++ ++} // namespace compiler ++} // namespace internal ++} // namespace v8 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-selector-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/backend/riscv64/instruction-selector-riscv64.cc +@@ -0,0 +1,2985 @@ ++// Copyright 2014 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#include "src/base/bits.h" ++#include "src/compiler/backend/instruction-selector-impl.h" ++#include "src/compiler/node-matchers.h" ++#include "src/compiler/node-properties.h" ++ ++namespace v8 { ++namespace internal { ++namespace compiler { ++ ++#define TRACE_UNIMPL() \ ++ PrintF("UNIMPLEMENTED instr_sel: %s at line %d\n", __FUNCTION__, __LINE__) ++ ++#define TRACE() PrintF("instr_sel: %s at line %d\n", __FUNCTION__, __LINE__) ++ ++// Adds RISC-V-specific methods for generating InstructionOperands. ++class RiscvOperandGenerator final : public OperandGenerator { ++ public: ++ explicit RiscvOperandGenerator(InstructionSelector* selector) ++ : OperandGenerator(selector) {} ++ ++ InstructionOperand UseOperand(Node* node, InstructionCode opcode) { ++ if (CanBeImmediate(node, opcode)) { ++ return UseImmediate(node); ++ } ++ return UseRegister(node); ++ } ++ ++ // Use the zero register if the node has the immediate value zero, otherwise ++ // assign a register. ++ InstructionOperand UseRegisterOrImmediateZero(Node* node) { ++ if ((IsIntegerConstant(node) && (GetIntegerConstantValue(node) == 0)) || ++ (IsFloatConstant(node) && ++ (bit_cast(GetFloatConstantValue(node)) == 0))) { ++ return UseImmediate(node); ++ } ++ return UseRegister(node); ++ } ++ ++ bool IsIntegerConstant(Node* node) { ++ return (node->opcode() == IrOpcode::kInt32Constant) || ++ (node->opcode() == IrOpcode::kInt64Constant); ++ } ++ ++ int64_t GetIntegerConstantValue(Node* node) { ++ if (node->opcode() == IrOpcode::kInt32Constant) { ++ return OpParameter(node->op()); ++ } ++ DCHECK_EQ(IrOpcode::kInt64Constant, node->opcode()); ++ return OpParameter(node->op()); ++ } ++ ++ bool IsFloatConstant(Node* node) { ++ return (node->opcode() == IrOpcode::kFloat32Constant) || ++ (node->opcode() == IrOpcode::kFloat64Constant); ++ } ++ ++ double GetFloatConstantValue(Node* node) { ++ if (node->opcode() == IrOpcode::kFloat32Constant) { ++ return OpParameter(node->op()); ++ } ++ DCHECK_EQ(IrOpcode::kFloat64Constant, node->opcode()); ++ return OpParameter(node->op()); ++ } ++ ++ bool CanBeImmediate(Node* node, InstructionCode mode) { ++ return IsIntegerConstant(node) && ++ CanBeImmediate(GetIntegerConstantValue(node), mode); ++ } ++ ++ bool CanBeImmediate(int64_t value, InstructionCode opcode) { ++ switch (ArchOpcodeField::decode(opcode)) { ++ case kRiscvShl32: ++ case kRiscvSar32: ++ case kRiscvShr32: ++ return is_uint5(value); ++ case kRiscvShl64: ++ case kRiscvSar64: ++ case kRiscvShr64: ++ return is_uint6(value); ++ case kRiscvAdd32: ++ case kRiscvAnd32: ++ case kRiscvAnd: ++ case kRiscvAdd64: ++ case kRiscvOr32: ++ case kRiscvOr: ++ case kRiscvTst: ++ case kRiscvXor: ++ return is_int12(value); ++ case kRiscvLb: ++ case kRiscvLbu: ++ case kRiscvSb: ++ case kRiscvLh: ++ case kRiscvLhu: ++ case kRiscvSh: ++ case kRiscvLw: ++ case kRiscvSw: ++ case kRiscvLd: ++ case kRiscvSd: ++ case kRiscvLoadFloat: ++ case kRiscvStoreFloat: ++ case kRiscvLoadDouble: ++ case kRiscvStoreDouble: ++ return is_int32(value); ++ default: ++ return is_int12(value); ++ } ++ } ++ ++ private: ++ bool ImmediateFitsAddrMode1Instruction(int32_t imm) const { ++ TRACE_UNIMPL(); ++ return false; ++ } ++}; ++ ++static void VisitRR(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++static void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ int32_t imm = OpParameter(node->op()); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseImmediate(imm)); ++} ++ ++static void VisitSimdShift(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ if (g.IsIntegerConstant(node->InputAt(1))) { ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), ++ g.UseImmediate(node->InputAt(1))); ++ } else { ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), ++ g.UseRegister(node->InputAt(1))); ++ } ++} ++ ++static void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ int32_t imm = OpParameter(node->op()); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseImmediate(imm), ++ g.UseRegister(node->InputAt(1))); ++} ++ ++static void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), ++ g.UseRegister(node->InputAt(1))); ++} ++ ++static void VisitUniqueRRR(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseUniqueRegister(node->InputAt(0)), ++ g.UseUniqueRegister(node->InputAt(1))); ++} ++ ++void VisitRRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) { ++ RiscvOperandGenerator g(selector); ++ selector->Emit( ++ opcode, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), ++ g.UseRegister(node->InputAt(1)), g.UseRegister(node->InputAt(2))); ++} ++ ++static void VisitRRO(InstructionSelector* selector, ArchOpcode opcode, ++ Node* node) { ++ RiscvOperandGenerator g(selector); ++ selector->Emit(opcode, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), ++ g.UseOperand(node->InputAt(1), opcode)); ++} ++ ++struct ExtendingLoadMatcher { ++ ExtendingLoadMatcher(Node* node, InstructionSelector* selector) ++ : matches_(false), selector_(selector), base_(nullptr), immediate_(0) { ++ Initialize(node); ++ } ++ ++ bool Matches() const { return matches_; } ++ ++ Node* base() const { ++ DCHECK(Matches()); ++ return base_; ++ } ++ int64_t immediate() const { ++ DCHECK(Matches()); ++ return immediate_; ++ } ++ ArchOpcode opcode() const { ++ DCHECK(Matches()); ++ return opcode_; ++ } ++ ++ private: ++ bool matches_; ++ InstructionSelector* selector_; ++ Node* base_; ++ int64_t immediate_; ++ ArchOpcode opcode_; ++ ++ void Initialize(Node* node) { ++ Int64BinopMatcher m(node); ++ // When loading a 64-bit value and shifting by 32, we should ++ // just load and sign-extend the interesting 4 bytes instead. ++ // This happens, for example, when we're loading and untagging SMIs. ++ DCHECK(m.IsWord64Sar()); ++ if (m.left().IsLoad() && m.right().Is(32) && ++ selector_->CanCover(m.node(), m.left().node())) { ++ DCHECK_EQ(selector_->GetEffectLevel(node), ++ selector_->GetEffectLevel(m.left().node())); ++ MachineRepresentation rep = ++ LoadRepresentationOf(m.left().node()->op()).representation(); ++ DCHECK_EQ(3, ElementSizeLog2Of(rep)); ++ if (rep != MachineRepresentation::kTaggedSigned && ++ rep != MachineRepresentation::kTaggedPointer && ++ rep != MachineRepresentation::kTagged && ++ rep != MachineRepresentation::kWord64) { ++ return; ++ } ++ ++ RiscvOperandGenerator g(selector_); ++ Node* load = m.left().node(); ++ Node* offset = load->InputAt(1); ++ base_ = load->InputAt(0); ++ opcode_ = kRiscvLw; ++ if (g.CanBeImmediate(offset, opcode_)) { ++#if defined(V8_TARGET_LITTLE_ENDIAN) ++ immediate_ = g.GetIntegerConstantValue(offset) + 4; ++#elif defined(V8_TARGET_BIG_ENDIAN) ++ immediate_ = g.GetIntegerConstantValue(offset); ++#endif ++ matches_ = g.CanBeImmediate(immediate_, kRiscvLw); ++ } ++ } ++ } ++}; ++ ++bool TryEmitExtendingLoad(InstructionSelector* selector, Node* node, ++ Node* output_node) { ++ ExtendingLoadMatcher m(node, selector); ++ RiscvOperandGenerator g(selector); ++ if (m.Matches()) { ++ InstructionOperand inputs[2]; ++ inputs[0] = g.UseRegister(m.base()); ++ InstructionCode opcode = ++ m.opcode() | AddressingModeField::encode(kMode_MRI); ++ DCHECK(is_int32(m.immediate())); ++ inputs[1] = g.TempImmediate(static_cast(m.immediate())); ++ InstructionOperand outputs[] = {g.DefineAsRegister(output_node)}; ++ selector->Emit(opcode, arraysize(outputs), outputs, arraysize(inputs), ++ inputs); ++ return true; ++ } ++ return false; ++} ++ ++bool TryMatchImmediate(InstructionSelector* selector, ++ InstructionCode* opcode_return, Node* node, ++ size_t* input_count_return, InstructionOperand* inputs) { ++ RiscvOperandGenerator g(selector); ++ if (g.CanBeImmediate(node, *opcode_return)) { ++ *opcode_return |= AddressingModeField::encode(kMode_MRI); ++ inputs[0] = g.UseImmediate(node); ++ *input_count_return = 1; ++ return true; ++ } ++ return false; ++} ++ ++static void VisitBinop(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, bool has_reverse_opcode, ++ InstructionCode reverse_opcode, ++ FlagsContinuation* cont) { ++ RiscvOperandGenerator g(selector); ++ Int32BinopMatcher m(node); ++ InstructionOperand inputs[2]; ++ size_t input_count = 0; ++ InstructionOperand outputs[1]; ++ size_t output_count = 0; ++ ++ if (TryMatchImmediate(selector, &opcode, m.right().node(), &input_count, ++ &inputs[1])) { ++ inputs[0] = g.UseRegister(m.left().node()); ++ input_count++; ++ } else if (has_reverse_opcode && ++ TryMatchImmediate(selector, &reverse_opcode, m.left().node(), ++ &input_count, &inputs[1])) { ++ inputs[0] = g.UseRegister(m.right().node()); ++ opcode = reverse_opcode; ++ input_count++; ++ } else { ++ inputs[input_count++] = g.UseRegister(m.left().node()); ++ inputs[input_count++] = g.UseOperand(m.right().node(), opcode); ++ } ++ ++ if (cont->IsDeoptimize()) { ++ // If we can deoptimize as a result of the binop, we need to make sure that ++ // the deopt inputs are not overwritten by the binop result. One way ++ // to achieve that is to declare the output register as same-as-first. ++ outputs[output_count++] = g.DefineSameAsFirst(node); ++ } else { ++ outputs[output_count++] = g.DefineAsRegister(node); ++ } ++ ++ DCHECK_NE(0u, input_count); ++ DCHECK_EQ(1u, output_count); ++ DCHECK_GE(arraysize(inputs), input_count); ++ DCHECK_GE(arraysize(outputs), output_count); ++ ++ selector->EmitWithContinuation(opcode, output_count, outputs, input_count, ++ inputs, cont); ++} ++ ++static void VisitBinop(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, bool has_reverse_opcode, ++ InstructionCode reverse_opcode) { ++ FlagsContinuation cont; ++ VisitBinop(selector, node, opcode, has_reverse_opcode, reverse_opcode, &cont); ++} ++ ++static void VisitBinop(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, FlagsContinuation* cont) { ++ VisitBinop(selector, node, opcode, false, kArchNop, cont); ++} ++ ++static void VisitBinop(InstructionSelector* selector, Node* node, ++ InstructionCode opcode) { ++ VisitBinop(selector, node, opcode, false, kArchNop); ++} ++ ++void InstructionSelector::VisitStackSlot(Node* node) { ++ StackSlotRepresentation rep = StackSlotRepresentationOf(node->op()); ++ int alignment = rep.alignment(); ++ int slot = frame_->AllocateSpillSlot(rep.size(), alignment); ++ OperandGenerator g(this); ++ ++ Emit(kArchStackSlot, g.DefineAsRegister(node), ++ sequence()->AddImmediate(Constant(slot)), ++ sequence()->AddImmediate(Constant(alignment)), 0, nullptr); ++} ++ ++void InstructionSelector::VisitAbortCSAAssert(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kArchAbortCSAAssert, g.NoOutput(), g.UseFixed(node->InputAt(0), a0)); ++} ++ ++void EmitLoad(InstructionSelector* selector, Node* node, InstructionCode opcode, ++ Node* output = nullptr) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ ++ if (g.CanBeImmediate(index, opcode)) { ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(output == nullptr ? node : output), ++ g.UseRegister(base), g.UseImmediate(index)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ selector->Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), ++ addr_reg, g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired load opcode, using temp addr_reg. ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(output == nullptr ? node : output), ++ addr_reg, g.TempImmediate(0)); ++ } ++} ++ ++void InstructionSelector::VisitLoadTransform(Node* node) { ++ LoadTransformParameters params = LoadTransformParametersOf(node->op()); ++ ++ InstructionCode opcode = kArchNop; ++ switch (params.transformation) { ++ case LoadTransformation::kS8x16LoadSplat: ++ opcode = kRiscvS8x16LoadSplat; ++ break; ++ case LoadTransformation::kS16x8LoadSplat: ++ opcode = kRiscvS16x8LoadSplat; ++ break; ++ case LoadTransformation::kS32x4LoadSplat: ++ opcode = kRiscvS32x4LoadSplat; ++ break; ++ case LoadTransformation::kS64x2LoadSplat: ++ opcode = kRiscvS64x2LoadSplat; ++ break; ++ case LoadTransformation::kI16x8Load8x8S: ++ opcode = kRiscvI16x8Load8x8S; ++ break; ++ case LoadTransformation::kI16x8Load8x8U: ++ opcode = kRiscvI16x8Load8x8U; ++ break; ++ case LoadTransformation::kI32x4Load16x4S: ++ opcode = kRiscvI32x4Load16x4S; ++ break; ++ case LoadTransformation::kI32x4Load16x4U: ++ opcode = kRiscvI32x4Load16x4U; ++ break; ++ case LoadTransformation::kI64x2Load32x2S: ++ opcode = kRiscvI64x2Load32x2S; ++ break; ++ case LoadTransformation::kI64x2Load32x2U: ++ opcode = kRiscvI64x2Load32x2U; ++ break; ++ default: ++ UNIMPLEMENTED(); ++ } ++ ++ EmitLoad(this, node, opcode); ++} ++ ++void InstructionSelector::VisitLoad(Node* node) { ++ LoadRepresentation load_rep = LoadRepresentationOf(node->op()); ++ ++ InstructionCode opcode = kArchNop; ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kFloat32: ++ opcode = kRiscvLoadFloat; ++ break; ++ case MachineRepresentation::kFloat64: ++ opcode = kRiscvLoadDouble; ++ break; ++ case MachineRepresentation::kBit: // Fall through. ++ case MachineRepresentation::kWord8: ++ opcode = load_rep.IsUnsigned() ? kRiscvLbu : kRiscvLb; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = load_rep.IsUnsigned() ? kRiscvLhu : kRiscvLh; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = load_rep.IsUnsigned() ? kRiscvLwu : kRiscvLw; ++ break; ++ case MachineRepresentation::kTaggedSigned: // Fall through. ++ case MachineRepresentation::kTaggedPointer: // Fall through. ++ case MachineRepresentation::kTagged: // Fall through. ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvLd; ++ break; ++ case MachineRepresentation::kSimd128: ++ opcode = kRiscvMsaLd; ++ break; ++ case MachineRepresentation::kCompressedPointer: // Fall through. ++ case MachineRepresentation::kCompressed: // Fall through. ++ case MachineRepresentation::kNone: ++ UNREACHABLE(); ++ } ++ if (node->opcode() == IrOpcode::kPoisonedLoad) { ++ CHECK_NE(poisoning_level_, PoisoningMitigationLevel::kDontPoison); ++ opcode |= MiscField::encode(kMemoryAccessPoisoned); ++ } ++ ++ EmitLoad(this, node, opcode); ++} ++ ++void InstructionSelector::VisitPoisonedLoad(Node* node) { VisitLoad(node); } ++ ++void InstructionSelector::VisitProtectedLoad(Node* node) { ++ // TODO(eholk) ++ UNIMPLEMENTED(); ++} ++ ++void InstructionSelector::VisitStore(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* value = node->InputAt(2); ++ ++ StoreRepresentation store_rep = StoreRepresentationOf(node->op()); ++ WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind(); ++ MachineRepresentation rep = store_rep.representation(); ++ ++ // TODO(riscv): I guess this could be done in a better way. ++ if (write_barrier_kind != kNoWriteBarrier && ++ V8_LIKELY(!FLAG_disable_write_barriers)) { ++ DCHECK(CanBeTaggedPointer(rep)); ++ InstructionOperand inputs[3]; ++ size_t input_count = 0; ++ inputs[input_count++] = g.UseUniqueRegister(base); ++ inputs[input_count++] = g.UseUniqueRegister(index); ++ inputs[input_count++] = g.UseUniqueRegister(value); ++ RecordWriteMode record_write_mode = ++ WriteBarrierKindToRecordWriteMode(write_barrier_kind); ++ InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()}; ++ size_t const temp_count = arraysize(temps); ++ InstructionCode code = kArchStoreWithWriteBarrier; ++ code |= MiscField::encode(static_cast(record_write_mode)); ++ Emit(code, 0, nullptr, input_count, inputs, temp_count, temps); ++ } else { ++ ArchOpcode opcode = kArchNop; ++ switch (rep) { ++ case MachineRepresentation::kFloat32: ++ opcode = kRiscvStoreFloat; ++ break; ++ case MachineRepresentation::kFloat64: ++ opcode = kRiscvStoreDouble; ++ break; ++ case MachineRepresentation::kBit: // Fall through. ++ case MachineRepresentation::kWord8: ++ opcode = kRiscvSb; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = kRiscvSh; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kRiscvSw; ++ break; ++ case MachineRepresentation::kTaggedSigned: // Fall through. ++ case MachineRepresentation::kTaggedPointer: // Fall through. ++ case MachineRepresentation::kTagged: // Fall through. ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvSd; ++ break; ++ case MachineRepresentation::kSimd128: ++ opcode = kRiscvMsaSt; ++ break; ++ case MachineRepresentation::kCompressedPointer: // Fall through. ++ case MachineRepresentation::kCompressed: // Fall through. ++ case MachineRepresentation::kNone: ++ UNREACHABLE(); ++ return; ++ } ++ ++ if (g.CanBeImmediate(index, opcode)) { ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), ++ g.UseRegister(base), g.UseImmediate(index), ++ g.UseRegisterOrImmediateZero(value)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), addr_reg, ++ g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired store opcode, using temp addr_reg. ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), ++ addr_reg, g.TempImmediate(0), g.UseRegisterOrImmediateZero(value)); ++ } ++ } ++} ++ ++void InstructionSelector::VisitProtectedStore(Node* node) { ++ // TODO(eholk) ++ UNIMPLEMENTED(); ++} ++ ++void InstructionSelector::VisitWord32And(Node* node) { ++ VisitBinop(this, node, kRiscvAnd32, true, kRiscvAnd32); ++} ++ ++void InstructionSelector::VisitWord64And(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ if (m.left().IsWord64Shr() && CanCover(node, m.left().node()) && ++ m.right().HasValue()) { ++ uint64_t mask = m.right().Value(); ++ uint32_t mask_width = base::bits::CountPopulation(mask); ++ uint32_t mask_msb = base::bits::CountLeadingZeros64(mask); ++ if ((mask_width != 0) && (mask_msb + mask_width == 64)) { ++ // The mask must be contiguous, and occupy the least-significant bits. ++ DCHECK_EQ(0u, base::bits::CountTrailingZeros64(mask)); ++ ++ // Select Dext for And(Shr(x, imm), mask) where the mask is in the least ++ // significant bits. ++ Int64BinopMatcher mleft(m.left().node()); ++ if (mleft.right().HasValue()) { ++ // Any shift value can match; int64 shifts use `value % 64`. ++ uint32_t lsb = static_cast(mleft.right().Value() & 0x3F); ++ ++ // Dext cannot extract bits past the register size, however since ++ // shifting the original value would have introduced some zeros we can ++ // still use Dext with a smaller mask and the remaining bits will be ++ // zeros. ++ if (lsb + mask_width > 64) mask_width = 64 - lsb; ++ ++ if (lsb == 0 && mask_width == 64) { ++ Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(mleft.left().node())); ++ return; ++ } ++ } ++ // Other cases fall through to the normal And operation. ++ } ++ } ++ VisitBinop(this, node, kRiscvAnd, true, kRiscvAnd); ++} ++ ++void InstructionSelector::VisitWord32Or(Node* node) { ++ VisitBinop(this, node, kRiscvOr32, true, kRiscvOr32); ++} ++ ++void InstructionSelector::VisitWord64Or(Node* node) { ++ VisitBinop(this, node, kRiscvOr, true, kRiscvOr); ++} ++ ++void InstructionSelector::VisitWord32Xor(Node* node) { ++ Int32BinopMatcher m(node); ++ if (m.left().IsWord32Or() && CanCover(node, m.left().node()) && ++ m.right().Is(-1)) { ++ Int32BinopMatcher mleft(m.left().node()); ++ if (!mleft.right().HasValue()) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvNor32, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node()), ++ g.UseRegister(mleft.right().node())); ++ return; ++ } ++ } ++ if (m.right().Is(-1)) { ++ // Use Nor for bit negation and eliminate constant loading for xori. ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvNor32, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.TempImmediate(0)); ++ return; ++ } ++ VisitBinop(this, node, kRiscvXor32, true, kRiscvXor32); ++} ++ ++void InstructionSelector::VisitWord64Xor(Node* node) { ++ Int64BinopMatcher m(node); ++ if (m.left().IsWord64Or() && CanCover(node, m.left().node()) && ++ m.right().Is(-1)) { ++ Int64BinopMatcher mleft(m.left().node()); ++ if (!mleft.right().HasValue()) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvNor, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node()), ++ g.UseRegister(mleft.right().node())); ++ return; ++ } ++ } ++ if (m.right().Is(-1)) { ++ // Use Nor for bit negation and eliminate constant loading for xori. ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvNor, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.TempImmediate(0)); ++ return; ++ } ++ VisitBinop(this, node, kRiscvXor, true, kRiscvXor); ++} ++ ++void InstructionSelector::VisitWord32Shl(Node* node) { ++ Int32BinopMatcher m(node); ++ if (m.left().IsWord32And() && CanCover(node, m.left().node()) && ++ m.right().IsInRange(1, 31)) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher mleft(m.left().node()); ++ // Match Word32Shl(Word32And(x, mask), imm) to Shl where the mask is ++ // contiguous, and the shift immediate non-zero. ++ if (mleft.right().HasValue()) { ++ uint32_t mask = mleft.right().Value(); ++ uint32_t mask_width = base::bits::CountPopulation(mask); ++ uint32_t mask_msb = base::bits::CountLeadingZeros32(mask); ++ if ((mask_width != 0) && (mask_msb + mask_width == 32)) { ++ uint32_t shift = m.right().Value(); ++ DCHECK_EQ(0u, base::bits::CountTrailingZeros32(mask)); ++ DCHECK_NE(0u, shift); ++ if ((shift + mask_width) >= 32) { ++ // If the mask is contiguous and reaches or extends beyond the top ++ // bit, only the shift is needed. ++ Emit(kRiscvShl32, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node()), ++ g.UseImmediate(m.right().node())); ++ return; ++ } ++ } ++ } ++ } ++ VisitRRO(this, kRiscvShl32, node); ++} ++ ++void InstructionSelector::VisitWord32Shr(Node* node) { ++ VisitRRO(this, kRiscvShr32, node); ++} ++ ++void InstructionSelector::VisitWord32Sar(Node* node) { ++ Int32BinopMatcher m(node); ++ if (m.left().IsWord32Shl() && CanCover(node, m.left().node())) { ++ Int32BinopMatcher mleft(m.left().node()); ++ if (m.right().HasValue() && mleft.right().HasValue()) { ++ RiscvOperandGenerator g(this); ++ uint32_t sar = m.right().Value(); ++ uint32_t shl = mleft.right().Value(); ++ if ((sar == shl) && (sar == 16)) { ++ Emit(kRiscvSignExtendShort, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node())); ++ return; ++ } else if ((sar == shl) && (sar == 24)) { ++ Emit(kRiscvSignExtendByte, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node())); ++ return; ++ } else if ((sar == shl) && (sar == 32)) { ++ Emit(kRiscvShl32, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node()), g.TempImmediate(0)); ++ return; ++ } ++ } ++ } ++ VisitRRO(this, kRiscvSar32, node); ++} ++ ++void InstructionSelector::VisitWord64Shl(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ if ((m.left().IsChangeInt32ToInt64() || m.left().IsChangeUint32ToUint64()) && ++ m.right().IsInRange(32, 63) && CanCover(node, m.left().node())) { ++ // There's no need to sign/zero-extend to 64-bit if we shift out the upper ++ // 32 bits anyway. ++ Emit(kRiscvShl64, g.DefineSameAsFirst(node), ++ g.UseRegister(m.left().node()->InputAt(0)), ++ g.UseImmediate(m.right().node())); ++ return; ++ } ++ if (m.left().IsWord64And() && CanCover(node, m.left().node()) && ++ m.right().IsInRange(1, 63)) { ++ // Match Word64Shl(Word64And(x, mask), imm) to Dshl where the mask is ++ // contiguous, and the shift immediate non-zero. ++ Int64BinopMatcher mleft(m.left().node()); ++ if (mleft.right().HasValue()) { ++ uint64_t mask = mleft.right().Value(); ++ uint32_t mask_width = base::bits::CountPopulation(mask); ++ uint32_t mask_msb = base::bits::CountLeadingZeros64(mask); ++ if ((mask_width != 0) && (mask_msb + mask_width == 64)) { ++ uint64_t shift = m.right().Value(); ++ DCHECK_EQ(0u, base::bits::CountTrailingZeros64(mask)); ++ DCHECK_NE(0u, shift); ++ ++ if ((shift + mask_width) >= 64) { ++ // If the mask is contiguous and reaches or extends beyond the top ++ // bit, only the shift is needed. ++ Emit(kRiscvShl64, g.DefineAsRegister(node), ++ g.UseRegister(mleft.left().node()), ++ g.UseImmediate(m.right().node())); ++ return; ++ } ++ } ++ } ++ } ++ VisitRRO(this, kRiscvShl64, node); ++} ++ ++void InstructionSelector::VisitWord64Shr(Node* node) { ++ VisitRRO(this, kRiscvShr64, node); ++} ++ ++void InstructionSelector::VisitWord64Sar(Node* node) { ++ if (TryEmitExtendingLoad(this, node, node)) return; ++ VisitRRO(this, kRiscvSar64, node); ++} ++ ++void InstructionSelector::VisitWord32Rol(Node* node) { UNREACHABLE(); } ++ ++void InstructionSelector::VisitWord64Rol(Node* node) { UNREACHABLE(); } ++ ++void InstructionSelector::VisitWord32Ror(Node* node) { ++ VisitRRO(this, kRiscvRor32, node); ++} ++ ++void InstructionSelector::VisitWord32Clz(Node* node) { ++ VisitRR(this, kRiscvClz32, node); ++} ++ ++void InstructionSelector::VisitWord32ReverseBits(Node* node) { UNREACHABLE(); } ++ ++void InstructionSelector::VisitWord64ReverseBits(Node* node) { UNREACHABLE(); } ++ ++void InstructionSelector::VisitWord64ReverseBytes(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvByteSwap64, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitWord32ReverseBytes(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvByteSwap32, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitSimd128ReverseBytes(Node* node) { ++ UNREACHABLE(); ++} ++ ++void InstructionSelector::VisitWord32Ctz(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvCtz32, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitWord64Ctz(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvCtz64, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitWord32Popcnt(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvPopcnt32, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitWord64Popcnt(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvPopcnt64, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitWord64Ror(Node* node) { ++ VisitRRO(this, kRiscvRor64, node); ++} ++ ++void InstructionSelector::VisitWord64Clz(Node* node) { ++ VisitRR(this, kRiscvClz64, node); ++} ++ ++void InstructionSelector::VisitInt32Add(Node* node) { ++ VisitBinop(this, node, kRiscvAdd32, true, kRiscvAdd32); ++} ++ ++void InstructionSelector::VisitInt64Add(Node* node) { ++ VisitBinop(this, node, kRiscvAdd64, true, kRiscvAdd64); ++} ++ ++void InstructionSelector::VisitInt32Sub(Node* node) { ++ VisitBinop(this, node, kRiscvSub32); ++} ++ ++void InstructionSelector::VisitInt64Sub(Node* node) { ++ VisitBinop(this, node, kRiscvSub64); ++} ++ ++void InstructionSelector::VisitInt32Mul(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher m(node); ++ if (m.right().HasValue() && m.right().Value() > 0) { ++ uint32_t value = static_cast(m.right().Value()); ++ if (base::bits::IsPowerOfTwo(value)) { ++ Emit(kRiscvShl32 | AddressingModeField::encode(kMode_None), ++ g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.TempImmediate(base::bits::WhichPowerOfTwo(value))); ++ return; ++ } ++ if (base::bits::IsPowerOfTwo(value + 1)) { ++ InstructionOperand temp = g.TempRegister(); ++ Emit(kRiscvShl32 | AddressingModeField::encode(kMode_None), temp, ++ g.UseRegister(m.left().node()), ++ g.TempImmediate(base::bits::WhichPowerOfTwo(value + 1))); ++ Emit(kRiscvSub32 | AddressingModeField::encode(kMode_None), ++ g.DefineAsRegister(node), temp, g.UseRegister(m.left().node())); ++ return; ++ } ++ } ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ if (CanCover(node, left) && CanCover(node, right)) { ++ if (left->opcode() == IrOpcode::kWord64Sar && ++ right->opcode() == IrOpcode::kWord64Sar) { ++ Int64BinopMatcher leftInput(left), rightInput(right); ++ if (leftInput.right().Is(32) && rightInput.right().Is(32)) { ++ // Combine untagging shifts with Dmul high. ++ Emit(kRiscvMulHigh64, g.DefineSameAsFirst(node), ++ g.UseRegister(leftInput.left().node()), ++ g.UseRegister(rightInput.left().node())); ++ return; ++ } ++ } ++ } ++ VisitRRR(this, kRiscvMul32, node); ++} ++ ++void InstructionSelector::VisitInt32MulHigh(Node* node) { ++ VisitRRR(this, kRiscvMulHigh32, node); ++} ++ ++void InstructionSelector::VisitUint32MulHigh(Node* node) { ++ VisitRRR(this, kRiscvMulHighU32, node); ++} ++ ++void InstructionSelector::VisitInt64Mul(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ // TODO(dusmil): Add optimization for shifts larger than 32. ++ if (m.right().HasValue() && m.right().Value() > 0) { ++ uint32_t value = static_cast(m.right().Value()); ++ if (base::bits::IsPowerOfTwo(value)) { ++ Emit(kRiscvShl64 | AddressingModeField::encode(kMode_None), ++ g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.TempImmediate(base::bits::WhichPowerOfTwo(value))); ++ return; ++ } ++ if (base::bits::IsPowerOfTwo(value + 1)) { ++ InstructionOperand temp = g.TempRegister(); ++ Emit(kRiscvShl64 | AddressingModeField::encode(kMode_None), temp, ++ g.UseRegister(m.left().node()), ++ g.TempImmediate(base::bits::WhichPowerOfTwo(value + 1))); ++ Emit(kRiscvSub64 | AddressingModeField::encode(kMode_None), ++ g.DefineAsRegister(node), temp, g.UseRegister(m.left().node())); ++ return; ++ } ++ } ++ Emit(kRiscvMul64, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitInt32Div(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher m(node); ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ if (CanCover(node, left) && CanCover(node, right)) { ++ if (left->opcode() == IrOpcode::kWord64Sar && ++ right->opcode() == IrOpcode::kWord64Sar) { ++ Int64BinopMatcher rightInput(right), leftInput(left); ++ if (rightInput.right().Is(32) && leftInput.right().Is(32)) { ++ // Combine both shifted operands with Ddiv. ++ Emit(kRiscvDiv64, g.DefineSameAsFirst(node), ++ g.UseRegister(leftInput.left().node()), ++ g.UseRegister(rightInput.left().node())); ++ return; ++ } ++ } ++ } ++ Emit(kRiscvDiv32, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitUint32Div(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher m(node); ++ Emit(kRiscvDivU32, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitInt32Mod(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher m(node); ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ if (CanCover(node, left) && CanCover(node, right)) { ++ if (left->opcode() == IrOpcode::kWord64Sar && ++ right->opcode() == IrOpcode::kWord64Sar) { ++ Int64BinopMatcher rightInput(right), leftInput(left); ++ if (rightInput.right().Is(32) && leftInput.right().Is(32)) { ++ // Combine both shifted operands with Dmod. ++ Emit(kRiscvMod64, g.DefineSameAsFirst(node), ++ g.UseRegister(leftInput.left().node()), ++ g.UseRegister(rightInput.left().node())); ++ return; ++ } ++ } ++ } ++ Emit(kRiscvMod32, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitUint32Mod(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int32BinopMatcher m(node); ++ Emit(kRiscvModU32, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitInt64Div(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ Emit(kRiscvDiv64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitUint64Div(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ Emit(kRiscvDivU64, g.DefineSameAsFirst(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitInt64Mod(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ Emit(kRiscvMod64, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitUint64Mod(Node* node) { ++ RiscvOperandGenerator g(this); ++ Int64BinopMatcher m(node); ++ Emit(kRiscvModU64, g.DefineAsRegister(node), g.UseRegister(m.left().node()), ++ g.UseRegister(m.right().node())); ++} ++ ++void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDS, node); ++} ++ ++void InstructionSelector::VisitRoundInt32ToFloat32(Node* node) { ++ VisitRR(this, kRiscvCvtSW, node); ++} ++ ++void InstructionSelector::VisitRoundUint32ToFloat32(Node* node) { ++ VisitRR(this, kRiscvCvtSUw, node); ++} ++ ++void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDW, node); ++} ++ ++void InstructionSelector::VisitChangeInt64ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDL, node); ++} ++ ++void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDUw, node); ++} ++ ++void InstructionSelector::VisitTruncateFloat32ToInt32(Node* node) { ++ VisitRR(this, kRiscvTruncWS, node); ++} ++ ++void InstructionSelector::VisitTruncateFloat32ToUint32(Node* node) { ++ VisitRR(this, kRiscvTruncUwS, node); ++} ++ ++void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* value = node->InputAt(0); ++ // Match ChangeFloat64ToInt32(Float64Round##OP) to corresponding instruction ++ // which does rounding and conversion to integer format. ++ if (CanCover(node, value)) { ++ switch (value->opcode()) { ++ case IrOpcode::kFloat64RoundDown: ++ Emit(kRiscvFloorWD, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ case IrOpcode::kFloat64RoundUp: ++ Emit(kRiscvCeilWD, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ case IrOpcode::kFloat64RoundTiesEven: ++ Emit(kRiscvRoundWD, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ case IrOpcode::kFloat64RoundTruncate: ++ Emit(kRiscvTruncWD, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ default: ++ break; ++ } ++ if (value->opcode() == IrOpcode::kChangeFloat32ToFloat64) { ++ Node* next = value->InputAt(0); ++ if (CanCover(value, next)) { ++ // Match ChangeFloat64ToInt32(ChangeFloat32ToFloat64(Float64Round##OP)) ++ switch (next->opcode()) { ++ case IrOpcode::kFloat32RoundDown: ++ Emit(kRiscvFloorWS, g.DefineAsRegister(node), ++ g.UseRegister(next->InputAt(0))); ++ return; ++ case IrOpcode::kFloat32RoundUp: ++ Emit(kRiscvCeilWS, g.DefineAsRegister(node), ++ g.UseRegister(next->InputAt(0))); ++ return; ++ case IrOpcode::kFloat32RoundTiesEven: ++ Emit(kRiscvRoundWS, g.DefineAsRegister(node), ++ g.UseRegister(next->InputAt(0))); ++ return; ++ case IrOpcode::kFloat32RoundTruncate: ++ Emit(kRiscvTruncWS, g.DefineAsRegister(node), ++ g.UseRegister(next->InputAt(0))); ++ return; ++ default: ++ Emit(kRiscvTruncWS, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ } ++ } else { ++ // Match float32 -> float64 -> int32 representation change path. ++ Emit(kRiscvTruncWS, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ } ++ } ++ } ++ VisitRR(this, kRiscvTruncWD, node); ++} ++ ++void InstructionSelector::VisitChangeFloat64ToInt64(Node* node) { ++ VisitRR(this, kRiscvTruncLD, node); ++} ++ ++void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) { ++ VisitRR(this, kRiscvTruncUwD, node); ++} ++ ++void InstructionSelector::VisitChangeFloat64ToUint64(Node* node) { ++ VisitRR(this, kRiscvTruncUlD, node); ++} ++ ++void InstructionSelector::VisitTruncateFloat64ToUint32(Node* node) { ++ VisitRR(this, kRiscvTruncUwD, node); ++} ++ ++void InstructionSelector::VisitTruncateFloat64ToInt64(Node* node) { ++ VisitRR(this, kRiscvTruncLD, node); ++} ++ ++void InstructionSelector::VisitTryTruncateFloat32ToInt64(Node* node) { ++ RiscvOperandGenerator g(this); ++ InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; ++ InstructionOperand outputs[2]; ++ size_t output_count = 0; ++ outputs[output_count++] = g.DefineAsRegister(node); ++ ++ Node* success_output = NodeProperties::FindProjection(node, 1); ++ if (success_output) { ++ outputs[output_count++] = g.DefineAsRegister(success_output); ++ } ++ ++ this->Emit(kRiscvTruncLS, output_count, outputs, 1, inputs); ++} ++ ++void InstructionSelector::VisitTryTruncateFloat64ToInt64(Node* node) { ++ RiscvOperandGenerator g(this); ++ InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; ++ InstructionOperand outputs[2]; ++ size_t output_count = 0; ++ outputs[output_count++] = g.DefineAsRegister(node); ++ ++ Node* success_output = NodeProperties::FindProjection(node, 1); ++ if (success_output) { ++ outputs[output_count++] = g.DefineAsRegister(success_output); ++ } ++ ++ Emit(kRiscvTruncLD, output_count, outputs, 1, inputs); ++} ++ ++void InstructionSelector::VisitTryTruncateFloat32ToUint64(Node* node) { ++ RiscvOperandGenerator g(this); ++ InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; ++ InstructionOperand outputs[2]; ++ size_t output_count = 0; ++ outputs[output_count++] = g.DefineAsRegister(node); ++ ++ Node* success_output = NodeProperties::FindProjection(node, 1); ++ if (success_output) { ++ outputs[output_count++] = g.DefineAsRegister(success_output); ++ } ++ ++ Emit(kRiscvTruncUlS, output_count, outputs, 1, inputs); ++} ++ ++void InstructionSelector::VisitTryTruncateFloat64ToUint64(Node* node) { ++ RiscvOperandGenerator g(this); ++ ++ InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0))}; ++ InstructionOperand outputs[2]; ++ size_t output_count = 0; ++ outputs[output_count++] = g.DefineAsRegister(node); ++ ++ Node* success_output = NodeProperties::FindProjection(node, 1); ++ if (success_output) { ++ outputs[output_count++] = g.DefineAsRegister(success_output); ++ } ++ ++ Emit(kRiscvTruncUlD, output_count, outputs, 1, inputs); ++} ++ ++void InstructionSelector::VisitBitcastWord32ToWord64(Node* node) { ++ UNIMPLEMENTED(); ++} ++ ++void InstructionSelector::VisitChangeInt32ToInt64(Node* node) { ++ Node* value = node->InputAt(0); ++ if (value->opcode() == IrOpcode::kLoad && CanCover(node, value)) { ++ // Generate sign-extending load. ++ LoadRepresentation load_rep = LoadRepresentationOf(value->op()); ++ InstructionCode opcode = kArchNop; ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kBit: // Fall through. ++ case MachineRepresentation::kWord8: ++ opcode = load_rep.IsUnsigned() ? kRiscvLbu : kRiscvLb; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = load_rep.IsUnsigned() ? kRiscvLhu : kRiscvLh; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kRiscvLw; ++ break; ++ default: ++ UNREACHABLE(); ++ return; ++ } ++ EmitLoad(this, value, opcode, node); ++ } else { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvShl32, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), ++ g.TempImmediate(0)); ++ } ++} ++ ++void InstructionSelector::VisitChangeUint32ToUint64(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* value = node->InputAt(0); ++ switch (value->opcode()) { ++ case IrOpcode::kLoad: { ++ LoadRepresentation load_rep = LoadRepresentationOf(value->op()); ++ if (load_rep.IsUnsigned()) { ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kWord8: ++ case MachineRepresentation::kWord16: ++ case MachineRepresentation::kWord32: ++ Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value)); ++ return; ++ default: ++ break; ++ } ++ } ++ break; ++ } ++ default: ++ break; ++ } ++ Emit(kRiscvZeroExtendWord, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitTruncateInt64ToInt32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* value = node->InputAt(0); ++ if (CanCover(node, value)) { ++ switch (value->opcode()) { ++ case IrOpcode::kWord64Sar: { ++ if (CanCover(value, value->InputAt(0)) && ++ TryEmitExtendingLoad(this, value, node)) { ++ return; ++ } else { ++ Int64BinopMatcher m(value); ++ if (m.right().IsInRange(32, 63)) { ++ // After smi untagging no need for truncate. Combine sequence. ++ Emit(kRiscvSar64, g.DefineSameAsFirst(node), ++ g.UseRegister(m.left().node()), ++ g.UseImmediate(m.right().node())); ++ return; ++ } ++ } ++ break; ++ } ++ default: ++ break; ++ } ++ } ++ ++ // Semantics of this machine IR is not clear. For example, x86 zero-extend the ++ // truncated value; arm treats it as nop thus the upper 32-bit as undefined; ++ // mips emits ext instruction which zero-extend the 32-bit value; for riscv, ++ // we do sign-extension of the truncated value ++ Emit(kRiscvSignExtendWord, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* value = node->InputAt(0); ++ // Match TruncateFloat64ToFloat32(ChangeInt32ToFloat64) to corresponding ++ // instruction. ++ if (CanCover(node, value) && ++ value->opcode() == IrOpcode::kChangeInt32ToFloat64) { ++ Emit(kRiscvCvtSW, g.DefineAsRegister(node), ++ g.UseRegister(value->InputAt(0))); ++ return; ++ } ++ VisitRR(this, kRiscvCvtSD, node); ++} ++ ++void InstructionSelector::VisitTruncateFloat64ToWord32(Node* node) { ++ VisitRR(this, kArchTruncateDoubleToI, node); ++} ++ ++void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) { ++ VisitRR(this, kRiscvTruncWD, node); ++} ++ ++void InstructionSelector::VisitRoundInt64ToFloat32(Node* node) { ++ VisitRR(this, kRiscvCvtSL, node); ++} ++ ++void InstructionSelector::VisitRoundInt64ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDL, node); ++} ++ ++void InstructionSelector::VisitRoundUint64ToFloat32(Node* node) { ++ VisitRR(this, kRiscvCvtSUl, node); ++} ++ ++void InstructionSelector::VisitRoundUint64ToFloat64(Node* node) { ++ VisitRR(this, kRiscvCvtDUl, node); ++} ++ ++void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) { ++ VisitRR(this, kRiscvBitcastFloat32ToInt32, node); ++} ++ ++void InstructionSelector::VisitBitcastFloat64ToInt64(Node* node) { ++ VisitRR(this, kRiscvBitcastDL, node); ++} ++ ++void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) { ++ VisitRR(this, kRiscvBitcastInt32ToFloat32, node); ++} ++ ++void InstructionSelector::VisitBitcastInt64ToFloat64(Node* node) { ++ VisitRR(this, kRiscvBitcastLD, node); ++} ++ ++void InstructionSelector::VisitFloat32Add(Node* node) { ++ VisitRRR(this, kRiscvAddS, node); ++} ++ ++void InstructionSelector::VisitFloat64Add(Node* node) { ++ VisitRRR(this, kRiscvAddD, node); ++} ++ ++void InstructionSelector::VisitFloat32Sub(Node* node) { ++ VisitRRR(this, kRiscvSubS, node); ++} ++ ++void InstructionSelector::VisitFloat64Sub(Node* node) { ++ VisitRRR(this, kRiscvSubD, node); ++} ++ ++void InstructionSelector::VisitFloat32Mul(Node* node) { ++ VisitRRR(this, kRiscvMulS, node); ++} ++ ++void InstructionSelector::VisitFloat64Mul(Node* node) { ++ VisitRRR(this, kRiscvMulD, node); ++} ++ ++void InstructionSelector::VisitFloat32Div(Node* node) { ++ VisitRRR(this, kRiscvDivS, node); ++} ++ ++void InstructionSelector::VisitFloat64Div(Node* node) { ++ VisitRRR(this, kRiscvDivD, node); ++} ++ ++void InstructionSelector::VisitFloat64Mod(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvModD, g.DefineAsFixed(node, fa0), ++ g.UseFixed(node->InputAt(0), fa0), g.UseFixed(node->InputAt(1), fa1)) ++ ->MarkAsCall(); ++} ++ ++void InstructionSelector::VisitFloat32Max(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvFloat32Max, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); ++} ++ ++void InstructionSelector::VisitFloat64Max(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvFloat64Max, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); ++} ++ ++void InstructionSelector::VisitFloat32Min(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvFloat32Min, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); ++} ++ ++void InstructionSelector::VisitFloat64Min(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvFloat64Min, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); ++} ++ ++void InstructionSelector::VisitFloat32Abs(Node* node) { ++ VisitRR(this, kRiscvAbsS, node); ++} ++ ++void InstructionSelector::VisitFloat64Abs(Node* node) { ++ VisitRR(this, kRiscvAbsD, node); ++} ++ ++void InstructionSelector::VisitFloat32Sqrt(Node* node) { ++ VisitRR(this, kRiscvSqrtS, node); ++} ++ ++void InstructionSelector::VisitFloat64Sqrt(Node* node) { ++ VisitRR(this, kRiscvSqrtD, node); ++} ++ ++void InstructionSelector::VisitFloat32RoundDown(Node* node) { ++ VisitRR(this, kRiscvFloat32RoundDown, node); ++} ++ ++void InstructionSelector::VisitFloat64RoundDown(Node* node) { ++ VisitRR(this, kRiscvFloat64RoundDown, node); ++} ++ ++void InstructionSelector::VisitFloat32RoundUp(Node* node) { ++ VisitRR(this, kRiscvFloat32RoundUp, node); ++} ++ ++void InstructionSelector::VisitFloat64RoundUp(Node* node) { ++ VisitRR(this, kRiscvFloat64RoundUp, node); ++} ++ ++void InstructionSelector::VisitFloat32RoundTruncate(Node* node) { ++ VisitRR(this, kRiscvFloat32RoundTruncate, node); ++} ++ ++void InstructionSelector::VisitFloat64RoundTruncate(Node* node) { ++ VisitRR(this, kRiscvFloat64RoundTruncate, node); ++} ++ ++void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) { ++ UNREACHABLE(); ++} ++ ++void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) { ++ VisitRR(this, kRiscvFloat32RoundTiesEven, node); ++} ++ ++void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) { ++ VisitRR(this, kRiscvFloat64RoundTiesEven, node); ++} ++ ++void InstructionSelector::VisitFloat32Neg(Node* node) { ++ VisitRR(this, kRiscvNegS, node); ++} ++ ++void InstructionSelector::VisitFloat64Neg(Node* node) { ++ VisitRR(this, kRiscvNegD, node); ++} ++ ++void InstructionSelector::VisitFloat64Ieee754Binop(Node* node, ++ InstructionCode opcode) { ++ RiscvOperandGenerator g(this); ++ Emit(opcode, g.DefineAsFixed(node, fa0), g.UseFixed(node->InputAt(0), fa0), ++ g.UseFixed(node->InputAt(1), fa1)) ++ ->MarkAsCall(); ++} ++ ++void InstructionSelector::VisitFloat64Ieee754Unop(Node* node, ++ InstructionCode opcode) { ++ RiscvOperandGenerator g(this); ++ Emit(opcode, g.DefineAsFixed(node, fa0), g.UseFixed(node->InputAt(0), fa1)) ++ ->MarkAsCall(); ++} ++ ++void InstructionSelector::EmitPrepareArguments( ++ ZoneVector* arguments, const CallDescriptor* call_descriptor, ++ Node* node) { ++ RiscvOperandGenerator g(this); ++ ++ // Prepare for C function call. ++ if (call_descriptor->IsCFunctionCall()) { ++ Emit(kArchPrepareCallCFunction | MiscField::encode(static_cast( ++ call_descriptor->ParameterCount())), ++ 0, nullptr, 0, nullptr); ++ ++ // Poke any stack arguments. ++ int slot = kCArgSlotCount; ++ for (PushParameter input : (*arguments)) { ++ Emit(kRiscvStoreToStackSlot, g.NoOutput(), g.UseRegister(input.node), ++ g.TempImmediate(slot << kSystemPointerSizeLog2)); ++ ++slot; ++ } ++ } else { ++ int push_count = static_cast(call_descriptor->StackParameterCount()); ++ if (push_count > 0) { ++ // Calculate needed space ++ int stack_size = 0; ++ for (PushParameter input : (*arguments)) { ++ if (input.node) { ++ stack_size += input.location.GetSizeInPointers(); ++ } ++ } ++ Emit(kRiscvStackClaim, g.NoOutput(), ++ g.TempImmediate(stack_size << kSystemPointerSizeLog2)); ++ } ++ for (size_t n = 0; n < arguments->size(); ++n) { ++ PushParameter input = (*arguments)[n]; ++ if (input.node) { ++ Emit(kRiscvStoreToStackSlot, g.NoOutput(), g.UseRegister(input.node), ++ g.TempImmediate(static_cast(n << kSystemPointerSizeLog2))); ++ } ++ } ++ } ++} ++ ++void InstructionSelector::EmitPrepareResults( ++ ZoneVector* results, const CallDescriptor* call_descriptor, ++ Node* node) { ++ RiscvOperandGenerator g(this); ++ ++ int reverse_slot = 0; ++ for (PushParameter output : *results) { ++ if (!output.location.IsCallerFrameSlot()) continue; ++ // Skip any alignment holes in nodes. ++ if (output.node != nullptr) { ++ DCHECK(!call_descriptor->IsCFunctionCall()); ++ if (output.location.GetType() == MachineType::Float32()) { ++ MarkAsFloat32(output.node); ++ } else if (output.location.GetType() == MachineType::Float64()) { ++ MarkAsFloat64(output.node); ++ } ++ Emit(kRiscvPeek, g.DefineAsRegister(output.node), ++ g.UseImmediate(reverse_slot)); ++ } ++ reverse_slot += output.location.GetSizeInPointers(); ++ } ++} ++ ++bool InstructionSelector::IsTailCallAddressImmediate() { return false; } ++ ++int InstructionSelector::GetTempsCountForTailCallFromJSFunction() { return 3; } ++ ++void InstructionSelector::VisitUnalignedLoad(Node* node) { ++ LoadRepresentation load_rep = LoadRepresentationOf(node->op()); ++ RiscvOperandGenerator g(this); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ ++ ArchOpcode opcode = kArchNop; ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kFloat32: ++ opcode = kRiscvULoadFloat; ++ break; ++ case MachineRepresentation::kFloat64: ++ opcode = kRiscvULoadDouble; ++ break; ++ case MachineRepresentation::kBit: // Fall through. ++ case MachineRepresentation::kWord8: ++ UNREACHABLE(); ++ case MachineRepresentation::kWord16: ++ opcode = load_rep.IsUnsigned() ? kRiscvUlhu : kRiscvUlh; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = load_rep.IsUnsigned() ? kRiscvUlwu : kRiscvUlw; ++ break; ++ case MachineRepresentation::kTaggedSigned: // Fall through. ++ case MachineRepresentation::kTaggedPointer: // Fall through. ++ case MachineRepresentation::kTagged: // Fall through. ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvUld; ++ break; ++ case MachineRepresentation::kSimd128: ++ opcode = kRiscvMsaLd; ++ break; ++ case MachineRepresentation::kCompressedPointer: // Fall through. ++ case MachineRepresentation::kCompressed: // Fall through. ++ case MachineRepresentation::kNone: ++ UNREACHABLE(); ++ } ++ ++ if (g.CanBeImmediate(index, opcode)) { ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(node), g.UseRegister(base), g.UseImmediate(index)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), addr_reg, ++ g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired load opcode, using temp addr_reg. ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(node), addr_reg, g.TempImmediate(0)); ++ } ++} ++ ++void InstructionSelector::VisitUnalignedStore(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* value = node->InputAt(2); ++ ++ UnalignedStoreRepresentation rep = UnalignedStoreRepresentationOf(node->op()); ++ ArchOpcode opcode = kArchNop; ++ switch (rep) { ++ case MachineRepresentation::kFloat32: ++ opcode = kRiscvUStoreFloat; ++ break; ++ case MachineRepresentation::kFloat64: ++ opcode = kRiscvUStoreDouble; ++ break; ++ case MachineRepresentation::kBit: // Fall through. ++ case MachineRepresentation::kWord8: ++ UNREACHABLE(); ++ case MachineRepresentation::kWord16: ++ opcode = kRiscvUsh; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kRiscvUsw; ++ break; ++ case MachineRepresentation::kTaggedSigned: // Fall through. ++ case MachineRepresentation::kTaggedPointer: // Fall through. ++ case MachineRepresentation::kTagged: // Fall through. ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvUsd; ++ break; ++ case MachineRepresentation::kSimd128: ++ opcode = kRiscvMsaSt; ++ break; ++ case MachineRepresentation::kCompressedPointer: // Fall through. ++ case MachineRepresentation::kCompressed: // Fall through. ++ case MachineRepresentation::kNone: ++ UNREACHABLE(); ++ } ++ ++ if (g.CanBeImmediate(index, opcode)) { ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), ++ g.UseRegister(base), g.UseImmediate(index), ++ g.UseRegisterOrImmediateZero(value)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), addr_reg, ++ g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired store opcode, using temp addr_reg. ++ Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), ++ addr_reg, g.TempImmediate(0), g.UseRegisterOrImmediateZero(value)); ++ } ++} ++ ++namespace { ++ ++// Shared routine for multiple compare operations. ++static void VisitCompare(InstructionSelector* selector, InstructionCode opcode, ++ InstructionOperand left, InstructionOperand right, ++ FlagsContinuation* cont) { ++ selector->EmitWithContinuation(opcode, left, right, cont); ++} ++ ++// Shared routine for multiple float32 compare operations. ++void VisitFloat32Compare(InstructionSelector* selector, Node* node, ++ FlagsContinuation* cont) { ++ RiscvOperandGenerator g(selector); ++ Float32BinopMatcher m(node); ++ InstructionOperand lhs, rhs; ++ ++ lhs = m.left().IsZero() ? g.UseImmediate(m.left().node()) ++ : g.UseRegister(m.left().node()); ++ rhs = m.right().IsZero() ? g.UseImmediate(m.right().node()) ++ : g.UseRegister(m.right().node()); ++ VisitCompare(selector, kRiscvCmpS, lhs, rhs, cont); ++} ++ ++// Shared routine for multiple float64 compare operations. ++void VisitFloat64Compare(InstructionSelector* selector, Node* node, ++ FlagsContinuation* cont) { ++ RiscvOperandGenerator g(selector); ++ Float64BinopMatcher m(node); ++ InstructionOperand lhs, rhs; ++ ++ lhs = m.left().IsZero() ? g.UseImmediate(m.left().node()) ++ : g.UseRegister(m.left().node()); ++ rhs = m.right().IsZero() ? g.UseImmediate(m.right().node()) ++ : g.UseRegister(m.right().node()); ++ VisitCompare(selector, kRiscvCmpD, lhs, rhs, cont); ++} ++ ++// Shared routine for multiple word compare operations. ++void VisitWordCompare(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, FlagsContinuation* cont, ++ bool commutative) { ++ RiscvOperandGenerator g(selector); ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ ++ // Match immediates on left or right side of comparison. ++ if (g.CanBeImmediate(right, opcode)) { ++ if (opcode == kRiscvTst) { ++ VisitCompare(selector, opcode, g.UseRegister(left), g.UseImmediate(right), ++ cont); ++ } else { ++ switch (cont->condition()) { ++ case kEqual: ++ case kNotEqual: ++ if (cont->IsSet()) { ++ VisitCompare(selector, opcode, g.UseRegister(left), ++ g.UseImmediate(right), cont); ++ } else { ++ VisitCompare(selector, opcode, g.UseRegister(left), ++ g.UseRegister(right), cont); ++ } ++ break; ++ case kSignedLessThan: ++ case kSignedGreaterThanOrEqual: ++ case kUnsignedLessThan: ++ case kUnsignedGreaterThanOrEqual: ++ VisitCompare(selector, opcode, g.UseRegister(left), ++ g.UseImmediate(right), cont); ++ break; ++ default: ++ VisitCompare(selector, opcode, g.UseRegister(left), ++ g.UseRegister(right), cont); ++ } ++ } ++ } else if (g.CanBeImmediate(left, opcode)) { ++ if (!commutative) cont->Commute(); ++ if (opcode == kRiscvTst) { ++ VisitCompare(selector, opcode, g.UseRegister(right), g.UseImmediate(left), ++ cont); ++ } else { ++ switch (cont->condition()) { ++ case kEqual: ++ case kNotEqual: ++ if (cont->IsSet()) { ++ VisitCompare(selector, opcode, g.UseRegister(right), ++ g.UseImmediate(left), cont); ++ } else { ++ VisitCompare(selector, opcode, g.UseRegister(right), ++ g.UseRegister(left), cont); ++ } ++ break; ++ case kSignedLessThan: ++ case kSignedGreaterThanOrEqual: ++ case kUnsignedLessThan: ++ case kUnsignedGreaterThanOrEqual: ++ VisitCompare(selector, opcode, g.UseRegister(right), ++ g.UseImmediate(left), cont); ++ break; ++ default: ++ VisitCompare(selector, opcode, g.UseRegister(right), ++ g.UseRegister(left), cont); ++ } ++ } ++ } else { ++ VisitCompare(selector, opcode, g.UseRegister(left), g.UseRegister(right), ++ cont); ++ } ++} ++ ++bool IsNodeUnsigned(Node* n) { ++ NodeMatcher m(n); ++ ++ if (m.IsLoad() || m.IsUnalignedLoad() || m.IsPoisonedLoad() || ++ m.IsProtectedLoad() || m.IsWord32AtomicLoad() || m.IsWord64AtomicLoad()) { ++ LoadRepresentation load_rep = LoadRepresentationOf(n->op()); ++ return load_rep.IsUnsigned(); ++ } else { ++ return m.IsUint32Div() || m.IsUint32LessThan() || ++ m.IsUint32LessThanOrEqual() || m.IsUint32Mod() || ++ m.IsUint32MulHigh() || m.IsChangeFloat64ToUint32() || ++ m.IsTruncateFloat64ToUint32() || m.IsTruncateFloat32ToUint32(); ++ } ++} ++ ++// Shared routine for multiple word compare operations. ++void VisitFullWord32Compare(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, FlagsContinuation* cont) { ++ RiscvOperandGenerator g(selector); ++ InstructionOperand leftOp = g.TempRegister(); ++ InstructionOperand rightOp = g.TempRegister(); ++ ++ selector->Emit(kRiscvShl64, leftOp, g.UseRegister(node->InputAt(0)), ++ g.TempImmediate(32)); ++ selector->Emit(kRiscvShl64, rightOp, g.UseRegister(node->InputAt(1)), ++ g.TempImmediate(32)); ++ ++ VisitCompare(selector, opcode, leftOp, rightOp, cont); ++} ++ ++void VisitOptimizedWord32Compare(InstructionSelector* selector, Node* node, ++ InstructionCode opcode, ++ FlagsContinuation* cont) { ++ if (FLAG_debug_code) { ++ RiscvOperandGenerator g(selector); ++ InstructionOperand leftOp = g.TempRegister(); ++ InstructionOperand rightOp = g.TempRegister(); ++ InstructionOperand optimizedResult = g.TempRegister(); ++ InstructionOperand fullResult = g.TempRegister(); ++ FlagsCondition condition = cont->condition(); ++ InstructionCode testOpcode = opcode | ++ FlagsConditionField::encode(condition) | ++ FlagsModeField::encode(kFlags_set); ++ ++ selector->Emit(testOpcode, optimizedResult, g.UseRegister(node->InputAt(0)), ++ g.UseRegister(node->InputAt(1))); ++ ++ selector->Emit(kRiscvShl64, leftOp, g.UseRegister(node->InputAt(0)), ++ g.TempImmediate(32)); ++ selector->Emit(kRiscvShl64, rightOp, g.UseRegister(node->InputAt(1)), ++ g.TempImmediate(32)); ++ selector->Emit(testOpcode, fullResult, leftOp, rightOp); ++ ++ selector->Emit(kRiscvAssertEqual, g.NoOutput(), optimizedResult, fullResult, ++ g.TempImmediate(static_cast( ++ AbortReason::kUnsupportedNonPrimitiveCompare))); ++ } ++ ++ VisitWordCompare(selector, node, opcode, cont, false); ++} ++ ++void VisitWord32Compare(InstructionSelector* selector, Node* node, ++ FlagsContinuation* cont) { ++ // RISC-V doesn't support Word32 compare instructions. Instead it relies ++ // that the values in registers are correctly sign-extended and uses ++ // Word64 comparison instead. This behavior is correct in most cases, ++ // but doesn't work when comparing signed with unsigned operands. ++ // We could simulate full Word32 compare in all cases but this would ++ // create an unnecessary overhead since unsigned integers are rarely ++ // used in JavaScript. ++ // The solution proposed here tries to match a comparison of signed ++ // with unsigned operand, and perform full Word32Compare only ++ // in those cases. Unfortunately, the solution is not complete because ++ // it might skip cases where Word32 full compare is needed, so ++ // basically it is a hack. ++ // When call to a host function in simulator, if the function return a ++ // int32 value, the simulator do not sign-extended to int64 because in ++ // simulator we do not know the function whether return a int32 or int64. ++ // so we need do a full word32 compare in this case. ++#ifndef USE_SIMULATOR ++ if (IsNodeUnsigned(node->InputAt(0)) != IsNodeUnsigned(node->InputAt(1))) { ++#else ++ if (IsNodeUnsigned(node->InputAt(0)) != IsNodeUnsigned(node->InputAt(1)) || ++ node->InputAt(0)->opcode() == IrOpcode::kCall || ++ node->InputAt(1)->opcode() == IrOpcode::kCall) { ++#endif ++ VisitFullWord32Compare(selector, node, kRiscvCmp, cont); ++ } else { ++ VisitOptimizedWord32Compare(selector, node, kRiscvCmp, cont); ++ } ++} ++ ++void VisitWord64Compare(InstructionSelector* selector, Node* node, ++ FlagsContinuation* cont) { ++ VisitWordCompare(selector, node, kRiscvCmp, cont, false); ++} ++ ++void EmitWordCompareZero(InstructionSelector* selector, Node* value, ++ FlagsContinuation* cont) { ++ RiscvOperandGenerator g(selector); ++ selector->EmitWithContinuation(kRiscvCmp, g.UseRegister(value), ++ g.TempImmediate(0), cont); ++} ++ ++void VisitAtomicLoad(InstructionSelector* selector, Node* node, ++ ArchOpcode opcode) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ if (g.CanBeImmediate(index, opcode)) { ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(node), g.UseRegister(base), ++ g.UseImmediate(index)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ selector->Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), ++ addr_reg, g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired load opcode, using temp addr_reg. ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.DefineAsRegister(node), addr_reg, g.TempImmediate(0)); ++ } ++} ++ ++void VisitAtomicStore(InstructionSelector* selector, Node* node, ++ ArchOpcode opcode) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* value = node->InputAt(2); ++ ++ if (g.CanBeImmediate(index, opcode)) { ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.NoOutput(), g.UseRegister(base), g.UseImmediate(index), ++ g.UseRegisterOrImmediateZero(value)); ++ } else { ++ InstructionOperand addr_reg = g.TempRegister(); ++ selector->Emit(kRiscvAdd64 | AddressingModeField::encode(kMode_None), ++ addr_reg, g.UseRegister(index), g.UseRegister(base)); ++ // Emit desired store opcode, using temp addr_reg. ++ selector->Emit(opcode | AddressingModeField::encode(kMode_MRI), ++ g.NoOutput(), addr_reg, g.TempImmediate(0), ++ g.UseRegisterOrImmediateZero(value)); ++ } ++} ++ ++void VisitAtomicExchange(InstructionSelector* selector, Node* node, ++ ArchOpcode opcode) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* value = node->InputAt(2); ++ ++ AddressingMode addressing_mode = kMode_MRI; ++ InstructionOperand inputs[3]; ++ size_t input_count = 0; ++ inputs[input_count++] = g.UseUniqueRegister(base); ++ inputs[input_count++] = g.UseUniqueRegister(index); ++ inputs[input_count++] = g.UseUniqueRegister(value); ++ InstructionOperand outputs[1]; ++ outputs[0] = g.UseUniqueRegister(node); ++ InstructionOperand temp[3]; ++ temp[0] = g.TempRegister(); ++ temp[1] = g.TempRegister(); ++ temp[2] = g.TempRegister(); ++ InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); ++ selector->Emit(code, 1, outputs, input_count, inputs, 3, temp); ++} ++ ++void VisitAtomicCompareExchange(InstructionSelector* selector, Node* node, ++ ArchOpcode opcode) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* old_value = node->InputAt(2); ++ Node* new_value = node->InputAt(3); ++ ++ AddressingMode addressing_mode = kMode_MRI; ++ InstructionOperand inputs[4]; ++ size_t input_count = 0; ++ inputs[input_count++] = g.UseUniqueRegister(base); ++ inputs[input_count++] = g.UseUniqueRegister(index); ++ inputs[input_count++] = g.UseUniqueRegister(old_value); ++ inputs[input_count++] = g.UseUniqueRegister(new_value); ++ InstructionOperand outputs[1]; ++ outputs[0] = g.UseUniqueRegister(node); ++ InstructionOperand temp[3]; ++ temp[0] = g.TempRegister(); ++ temp[1] = g.TempRegister(); ++ temp[2] = g.TempRegister(); ++ InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); ++ selector->Emit(code, 1, outputs, input_count, inputs, 3, temp); ++} ++ ++void VisitAtomicBinop(InstructionSelector* selector, Node* node, ++ ArchOpcode opcode) { ++ RiscvOperandGenerator g(selector); ++ Node* base = node->InputAt(0); ++ Node* index = node->InputAt(1); ++ Node* value = node->InputAt(2); ++ ++ AddressingMode addressing_mode = kMode_MRI; ++ InstructionOperand inputs[3]; ++ size_t input_count = 0; ++ inputs[input_count++] = g.UseUniqueRegister(base); ++ inputs[input_count++] = g.UseUniqueRegister(index); ++ inputs[input_count++] = g.UseUniqueRegister(value); ++ InstructionOperand outputs[1]; ++ outputs[0] = g.UseUniqueRegister(node); ++ InstructionOperand temps[4]; ++ temps[0] = g.TempRegister(); ++ temps[1] = g.TempRegister(); ++ temps[2] = g.TempRegister(); ++ temps[3] = g.TempRegister(); ++ InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); ++ selector->Emit(code, 1, outputs, input_count, inputs, 4, temps); ++} ++ ++} // namespace ++ ++void InstructionSelector::VisitStackPointerGreaterThan( ++ Node* node, FlagsContinuation* cont) { ++ StackCheckKind kind = StackCheckKindOf(node->op()); ++ InstructionCode opcode = ++ kArchStackPointerGreaterThan | MiscField::encode(static_cast(kind)); ++ ++ RiscvOperandGenerator g(this); ++ ++ // No outputs. ++ InstructionOperand* const outputs = nullptr; ++ const int output_count = 0; ++ ++ // Applying an offset to this stack check requires a temp register. Offsets ++ // are only applied to the first stack check. If applying an offset, we must ++ // ensure the input and temp registers do not alias, thus kUniqueRegister. ++ InstructionOperand temps[] = {g.TempRegister()}; ++ const int temp_count = (kind == StackCheckKind::kJSFunctionEntry ? 1 : 0); ++ const auto register_mode = (kind == StackCheckKind::kJSFunctionEntry) ++ ? OperandGenerator::kUniqueRegister ++ : OperandGenerator::kRegister; ++ ++ Node* const value = node->InputAt(0); ++ InstructionOperand inputs[] = {g.UseRegisterWithMode(value, register_mode)}; ++ static constexpr int input_count = arraysize(inputs); ++ ++ EmitWithContinuation(opcode, output_count, outputs, input_count, inputs, ++ temp_count, temps, cont); ++} ++ ++// Shared routine for word comparisons against zero. ++void InstructionSelector::VisitWordCompareZero(Node* user, Node* value, ++ FlagsContinuation* cont) { ++ // Try to combine with comparisons against 0 by simply inverting the branch. ++ while (CanCover(user, value)) { ++ if (value->opcode() == IrOpcode::kWord32Equal) { ++ Int32BinopMatcher m(value); ++ if (!m.right().Is(0)) break; ++ user = value; ++ value = m.left().node(); ++ } else if (value->opcode() == IrOpcode::kWord64Equal) { ++ Int64BinopMatcher m(value); ++ if (!m.right().Is(0)) break; ++ user = value; ++ value = m.left().node(); ++ } else { ++ break; ++ } ++ ++ cont->Negate(); ++ } ++ ++ if (CanCover(user, value)) { ++ switch (value->opcode()) { ++ case IrOpcode::kWord32Equal: ++ cont->OverwriteAndNegateIfEqual(kEqual); ++ return VisitWord32Compare(this, value, cont); ++ case IrOpcode::kInt32LessThan: ++ cont->OverwriteAndNegateIfEqual(kSignedLessThan); ++ return VisitWord32Compare(this, value, cont); ++ case IrOpcode::kInt32LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual); ++ return VisitWord32Compare(this, value, cont); ++ case IrOpcode::kUint32LessThan: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThan); ++ return VisitWord32Compare(this, value, cont); ++ case IrOpcode::kUint32LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual); ++ return VisitWord32Compare(this, value, cont); ++ case IrOpcode::kWord64Equal: ++ cont->OverwriteAndNegateIfEqual(kEqual); ++ return VisitWord64Compare(this, value, cont); ++ case IrOpcode::kInt64LessThan: ++ cont->OverwriteAndNegateIfEqual(kSignedLessThan); ++ return VisitWord64Compare(this, value, cont); ++ case IrOpcode::kInt64LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual); ++ return VisitWord64Compare(this, value, cont); ++ case IrOpcode::kUint64LessThan: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThan); ++ return VisitWord64Compare(this, value, cont); ++ case IrOpcode::kUint64LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual); ++ return VisitWord64Compare(this, value, cont); ++ case IrOpcode::kFloat32Equal: ++ cont->OverwriteAndNegateIfEqual(kEqual); ++ return VisitFloat32Compare(this, value, cont); ++ case IrOpcode::kFloat32LessThan: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThan); ++ return VisitFloat32Compare(this, value, cont); ++ case IrOpcode::kFloat32LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual); ++ return VisitFloat32Compare(this, value, cont); ++ case IrOpcode::kFloat64Equal: ++ cont->OverwriteAndNegateIfEqual(kEqual); ++ return VisitFloat64Compare(this, value, cont); ++ case IrOpcode::kFloat64LessThan: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThan); ++ return VisitFloat64Compare(this, value, cont); ++ case IrOpcode::kFloat64LessThanOrEqual: ++ cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual); ++ return VisitFloat64Compare(this, value, cont); ++ case IrOpcode::kProjection: ++ // Check if this is the overflow output projection of an ++ // WithOverflow node. ++ if (ProjectionIndexOf(value->op()) == 1u) { ++ // We cannot combine the WithOverflow with this branch ++ // unless the 0th projection (the use of the actual value of the ++ // is either nullptr, which means there's no use of the ++ // actual value, or was already defined, which means it is scheduled ++ // *AFTER* this branch). ++ Node* const node = value->InputAt(0); ++ Node* const result = NodeProperties::FindProjection(node, 0); ++ if (result == nullptr || IsDefined(result)) { ++ switch (node->opcode()) { ++ case IrOpcode::kInt32AddWithOverflow: ++ cont->OverwriteAndNegateIfEqual(kOverflow); ++ return VisitBinop(this, node, kRiscvAdd64, cont); ++ case IrOpcode::kInt32SubWithOverflow: ++ cont->OverwriteAndNegateIfEqual(kOverflow); ++ return VisitBinop(this, node, kRiscvSub64, cont); ++ case IrOpcode::kInt32MulWithOverflow: ++ cont->OverwriteAndNegateIfEqual(kOverflow); ++ return VisitBinop(this, node, kRiscvMulOvf32, cont); ++ case IrOpcode::kInt64AddWithOverflow: ++ cont->OverwriteAndNegateIfEqual(kOverflow); ++ return VisitBinop(this, node, kRiscvAddOvf64, cont); ++ case IrOpcode::kInt64SubWithOverflow: ++ cont->OverwriteAndNegateIfEqual(kOverflow); ++ return VisitBinop(this, node, kRiscvSubOvf64, cont); ++ default: ++ break; ++ } ++ } ++ } ++ break; ++ case IrOpcode::kWord32And: ++ case IrOpcode::kWord64And: ++ return VisitWordCompare(this, value, kRiscvTst, cont, true); ++ case IrOpcode::kStackPointerGreaterThan: ++ cont->OverwriteAndNegateIfEqual(kStackPointerGreaterThanCondition); ++ return VisitStackPointerGreaterThan(value, cont); ++ default: ++ break; ++ } ++ } ++ ++ // Continuation could not be combined with a compare, emit compare against 0. ++ EmitWordCompareZero(this, value, cont); ++} ++ ++void InstructionSelector::VisitSwitch(Node* node, const SwitchInfo& sw) { ++ RiscvOperandGenerator g(this); ++ InstructionOperand value_operand = g.UseRegister(node->InputAt(0)); ++ ++ // Emit either ArchTableSwitch or ArchBinarySearchSwitch. ++ if (enable_switch_jump_table_ == kEnableSwitchJumpTable) { ++ static const size_t kMaxTableSwitchValueRange = 2 << 16; ++ size_t table_space_cost = 10 + 2 * sw.value_range(); ++ size_t table_time_cost = 3; ++ size_t lookup_space_cost = 2 + 2 * sw.case_count(); ++ size_t lookup_time_cost = sw.case_count(); ++ if (sw.case_count() > 0 && ++ table_space_cost + 3 * table_time_cost <= ++ lookup_space_cost + 3 * lookup_time_cost && ++ sw.min_value() > std::numeric_limits::min() && ++ sw.value_range() <= kMaxTableSwitchValueRange) { ++ InstructionOperand index_operand = value_operand; ++ if (sw.min_value()) { ++ index_operand = g.TempRegister(); ++ Emit(kRiscvSub32, index_operand, value_operand, ++ g.TempImmediate(sw.min_value())); ++ } ++ // Generate a table lookup. ++ return EmitTableSwitch(sw, index_operand); ++ } ++ } ++ ++ // Generate a tree of conditional jumps. ++ return EmitBinarySearchSwitch(sw, value_operand); ++} ++ ++void InstructionSelector::VisitWord32Equal(Node* const node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node); ++ Int32BinopMatcher m(node); ++ if (m.right().Is(0)) { ++ return VisitWordCompareZero(m.node(), m.left().node(), &cont); ++ } ++ ++ VisitWord32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitInt32LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node); ++ VisitWord32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitInt32LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kSignedLessThanOrEqual, node); ++ VisitWord32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitUint32LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node); ++ VisitWord32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitUint32LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node); ++ VisitWord32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitInt32AddWithOverflow(Node* node) { ++ if (Node* ovf = NodeProperties::FindProjection(node, 1)) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); ++ return VisitBinop(this, node, kRiscvAdd64, &cont); ++ } ++ FlagsContinuation cont; ++ VisitBinop(this, node, kRiscvAdd64, &cont); ++} ++ ++void InstructionSelector::VisitInt32SubWithOverflow(Node* node) { ++ if (Node* ovf = NodeProperties::FindProjection(node, 1)) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); ++ return VisitBinop(this, node, kRiscvSub64, &cont); ++ } ++ FlagsContinuation cont; ++ VisitBinop(this, node, kRiscvSub64, &cont); ++} ++ ++void InstructionSelector::VisitInt32MulWithOverflow(Node* node) { ++ if (Node* ovf = NodeProperties::FindProjection(node, 1)) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); ++ return VisitBinop(this, node, kRiscvMulOvf32, &cont); ++ } ++ FlagsContinuation cont; ++ VisitBinop(this, node, kRiscvMulOvf32, &cont); ++} ++ ++void InstructionSelector::VisitInt64AddWithOverflow(Node* node) { ++ if (Node* ovf = NodeProperties::FindProjection(node, 1)) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); ++ return VisitBinop(this, node, kRiscvAddOvf64, &cont); ++ } ++ FlagsContinuation cont; ++ VisitBinop(this, node, kRiscvAddOvf64, &cont); ++} ++ ++void InstructionSelector::VisitInt64SubWithOverflow(Node* node) { ++ if (Node* ovf = NodeProperties::FindProjection(node, 1)) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); ++ return VisitBinop(this, node, kRiscvSubOvf64, &cont); ++ } ++ FlagsContinuation cont; ++ VisitBinop(this, node, kRiscvSubOvf64, &cont); ++} ++ ++void InstructionSelector::VisitWord64Equal(Node* const node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node); ++ Int64BinopMatcher m(node); ++ if (m.right().Is(0)) { ++ return VisitWordCompareZero(m.node(), m.left().node(), &cont); ++ } ++ ++ VisitWord64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitInt64LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node); ++ VisitWord64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitInt64LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kSignedLessThanOrEqual, node); ++ VisitWord64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitUint64LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node); ++ VisitWord64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitUint64LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node); ++ VisitWord64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat32Equal(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node); ++ VisitFloat32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat32LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node); ++ VisitFloat32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat32LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node); ++ VisitFloat32Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat64Equal(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node); ++ VisitFloat64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat64LessThan(Node* node) { ++ FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node); ++ VisitFloat64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) { ++ FlagsContinuation cont = ++ FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node); ++ VisitFloat64Compare(this, node, &cont); ++} ++ ++void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) { ++ VisitRR(this, kRiscvFloat64ExtractLowWord32, node); ++} ++ ++void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) { ++ VisitRR(this, kRiscvFloat64ExtractHighWord32, node); ++} ++ ++void InstructionSelector::VisitFloat64SilenceNaN(Node* node) { ++ VisitRR(this, kRiscvFloat64SilenceNaN, node); ++} ++ ++void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ Emit(kRiscvFloat64InsertLowWord32, g.DefineSameAsFirst(node), ++ g.UseRegister(left), g.UseRegister(right)); ++} ++ ++void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Node* left = node->InputAt(0); ++ Node* right = node->InputAt(1); ++ Emit(kRiscvFloat64InsertHighWord32, g.DefineSameAsFirst(node), ++ g.UseRegister(left), g.UseRegister(right)); ++} ++ ++void InstructionSelector::VisitMemoryBarrier(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvSync, g.NoOutput()); ++} ++ ++void InstructionSelector::VisitWord32AtomicLoad(Node* node) { ++ LoadRepresentation load_rep = LoadRepresentationOf(node->op()); ++ ArchOpcode opcode = kArchNop; ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kWord8: ++ opcode = ++ load_rep.IsSigned() ? kWord32AtomicLoadInt8 : kWord32AtomicLoadUint8; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = load_rep.IsSigned() ? kWord32AtomicLoadInt16 ++ : kWord32AtomicLoadUint16; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kWord32AtomicLoadWord32; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ VisitAtomicLoad(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord32AtomicStore(Node* node) { ++ MachineRepresentation rep = AtomicStoreRepresentationOf(node->op()); ++ ArchOpcode opcode = kArchNop; ++ switch (rep) { ++ case MachineRepresentation::kWord8: ++ opcode = kWord32AtomicStoreWord8; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = kWord32AtomicStoreWord16; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kWord32AtomicStoreWord32; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ VisitAtomicStore(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord64AtomicLoad(Node* node) { ++ LoadRepresentation load_rep = LoadRepresentationOf(node->op()); ++ ArchOpcode opcode = kArchNop; ++ switch (load_rep.representation()) { ++ case MachineRepresentation::kWord8: ++ opcode = kRiscvWord64AtomicLoadUint8; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = kRiscvWord64AtomicLoadUint16; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kRiscvWord64AtomicLoadUint32; ++ break; ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvWord64AtomicLoadUint64; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ VisitAtomicLoad(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord64AtomicStore(Node* node) { ++ MachineRepresentation rep = AtomicStoreRepresentationOf(node->op()); ++ ArchOpcode opcode = kArchNop; ++ switch (rep) { ++ case MachineRepresentation::kWord8: ++ opcode = kRiscvWord64AtomicStoreWord8; ++ break; ++ case MachineRepresentation::kWord16: ++ opcode = kRiscvWord64AtomicStoreWord16; ++ break; ++ case MachineRepresentation::kWord32: ++ opcode = kRiscvWord64AtomicStoreWord32; ++ break; ++ case MachineRepresentation::kWord64: ++ opcode = kRiscvWord64AtomicStoreWord64; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ VisitAtomicStore(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord32AtomicExchange(Node* node) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Int8()) { ++ opcode = kWord32AtomicExchangeInt8; ++ } else if (type == MachineType::Uint8()) { ++ opcode = kWord32AtomicExchangeUint8; ++ } else if (type == MachineType::Int16()) { ++ opcode = kWord32AtomicExchangeInt16; ++ } else if (type == MachineType::Uint16()) { ++ opcode = kWord32AtomicExchangeUint16; ++ } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { ++ opcode = kWord32AtomicExchangeWord32; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ ++ VisitAtomicExchange(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord64AtomicExchange(Node* node) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Uint8()) { ++ opcode = kRiscvWord64AtomicExchangeUint8; ++ } else if (type == MachineType::Uint16()) { ++ opcode = kRiscvWord64AtomicExchangeUint16; ++ } else if (type == MachineType::Uint32()) { ++ opcode = kRiscvWord64AtomicExchangeUint32; ++ } else if (type == MachineType::Uint64()) { ++ opcode = kRiscvWord64AtomicExchangeUint64; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ VisitAtomicExchange(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord32AtomicCompareExchange(Node* node) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Int8()) { ++ opcode = kWord32AtomicCompareExchangeInt8; ++ } else if (type == MachineType::Uint8()) { ++ opcode = kWord32AtomicCompareExchangeUint8; ++ } else if (type == MachineType::Int16()) { ++ opcode = kWord32AtomicCompareExchangeInt16; ++ } else if (type == MachineType::Uint16()) { ++ opcode = kWord32AtomicCompareExchangeUint16; ++ } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { ++ opcode = kWord32AtomicCompareExchangeWord32; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ ++ VisitAtomicCompareExchange(this, node, opcode); ++} ++ ++void InstructionSelector::VisitWord64AtomicCompareExchange(Node* node) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Uint8()) { ++ opcode = kRiscvWord64AtomicCompareExchangeUint8; ++ } else if (type == MachineType::Uint16()) { ++ opcode = kRiscvWord64AtomicCompareExchangeUint16; ++ } else if (type == MachineType::Uint32()) { ++ opcode = kRiscvWord64AtomicCompareExchangeUint32; ++ } else if (type == MachineType::Uint64()) { ++ opcode = kRiscvWord64AtomicCompareExchangeUint64; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ VisitAtomicCompareExchange(this, node, opcode); ++} ++void InstructionSelector::VisitWord32AtomicBinaryOperation( ++ Node* node, ArchOpcode int8_op, ArchOpcode uint8_op, ArchOpcode int16_op, ++ ArchOpcode uint16_op, ArchOpcode word32_op) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Int8()) { ++ opcode = int8_op; ++ } else if (type == MachineType::Uint8()) { ++ opcode = uint8_op; ++ } else if (type == MachineType::Int16()) { ++ opcode = int16_op; ++ } else if (type == MachineType::Uint16()) { ++ opcode = uint16_op; ++ } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { ++ opcode = word32_op; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ ++ VisitAtomicBinop(this, node, opcode); ++} ++ ++#define VISIT_ATOMIC_BINOP(op) \ ++ void InstructionSelector::VisitWord32Atomic##op(Node* node) { \ ++ VisitWord32AtomicBinaryOperation( \ ++ node, kWord32Atomic##op##Int8, kWord32Atomic##op##Uint8, \ ++ kWord32Atomic##op##Int16, kWord32Atomic##op##Uint16, \ ++ kWord32Atomic##op##Word32); \ ++ } ++VISIT_ATOMIC_BINOP(Add) ++VISIT_ATOMIC_BINOP(Sub) ++VISIT_ATOMIC_BINOP(And) ++VISIT_ATOMIC_BINOP(Or) ++VISIT_ATOMIC_BINOP(Xor) ++#undef VISIT_ATOMIC_BINOP ++ ++void InstructionSelector::VisitWord64AtomicBinaryOperation( ++ Node* node, ArchOpcode uint8_op, ArchOpcode uint16_op, ArchOpcode uint32_op, ++ ArchOpcode uint64_op) { ++ ArchOpcode opcode = kArchNop; ++ MachineType type = AtomicOpType(node->op()); ++ if (type == MachineType::Uint8()) { ++ opcode = uint8_op; ++ } else if (type == MachineType::Uint16()) { ++ opcode = uint16_op; ++ } else if (type == MachineType::Uint32()) { ++ opcode = uint32_op; ++ } else if (type == MachineType::Uint64()) { ++ opcode = uint64_op; ++ } else { ++ UNREACHABLE(); ++ return; ++ } ++ VisitAtomicBinop(this, node, opcode); ++} ++ ++#define VISIT_ATOMIC_BINOP(op) \ ++ void InstructionSelector::VisitWord64Atomic##op(Node* node) { \ ++ VisitWord64AtomicBinaryOperation( \ ++ node, kRiscvWord64Atomic##op##Uint8, kRiscvWord64Atomic##op##Uint16, \ ++ kRiscvWord64Atomic##op##Uint32, kRiscvWord64Atomic##op##Uint64); \ ++ } ++VISIT_ATOMIC_BINOP(Add) ++VISIT_ATOMIC_BINOP(Sub) ++VISIT_ATOMIC_BINOP(And) ++VISIT_ATOMIC_BINOP(Or) ++VISIT_ATOMIC_BINOP(Xor) ++#undef VISIT_ATOMIC_BINOP ++ ++void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) { ++ UNREACHABLE(); ++} ++ ++void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ++ UNREACHABLE(); ++} ++ ++#define SIMD_TYPE_LIST(V) \ ++ V(F32x4) \ ++ V(I32x4) \ ++ V(I16x8) \ ++ V(I8x16) ++ ++#define SIMD_UNOP_LIST(V) \ ++ V(F64x2Abs, kRiscvF64x2Abs) \ ++ V(F64x2Neg, kRiscvF64x2Neg) \ ++ V(F64x2Sqrt, kRiscvF64x2Sqrt) \ ++ V(F64x2Ceil, kRiscvF64x2Ceil) \ ++ V(F64x2Floor, kRiscvF64x2Floor) \ ++ V(F64x2Trunc, kRiscvF64x2Trunc) \ ++ V(F64x2NearestInt, kRiscvF64x2NearestInt) \ ++ V(I64x2Neg, kRiscvI64x2Neg) \ ++ V(F32x4SConvertI32x4, kRiscvF32x4SConvertI32x4) \ ++ V(F32x4UConvertI32x4, kRiscvF32x4UConvertI32x4) \ ++ V(F32x4Abs, kRiscvF32x4Abs) \ ++ V(F32x4Neg, kRiscvF32x4Neg) \ ++ V(F32x4Sqrt, kRiscvF32x4Sqrt) \ ++ V(F32x4RecipApprox, kRiscvF32x4RecipApprox) \ ++ V(F32x4RecipSqrtApprox, kRiscvF32x4RecipSqrtApprox) \ ++ V(F32x4Ceil, kRiscvF32x4Ceil) \ ++ V(F32x4Floor, kRiscvF32x4Floor) \ ++ V(F32x4Trunc, kRiscvF32x4Trunc) \ ++ V(F32x4NearestInt, kRiscvF32x4NearestInt) \ ++ V(I32x4SConvertF32x4, kRiscvI32x4SConvertF32x4) \ ++ V(I32x4UConvertF32x4, kRiscvI32x4UConvertF32x4) \ ++ V(I32x4Neg, kRiscvI32x4Neg) \ ++ V(I32x4SConvertI16x8Low, kRiscvI32x4SConvertI16x8Low) \ ++ V(I32x4SConvertI16x8High, kRiscvI32x4SConvertI16x8High) \ ++ V(I32x4UConvertI16x8Low, kRiscvI32x4UConvertI16x8Low) \ ++ V(I32x4UConvertI16x8High, kRiscvI32x4UConvertI16x8High) \ ++ V(I32x4Abs, kRiscvI32x4Abs) \ ++ V(I32x4BitMask, kRiscvI32x4BitMask) \ ++ V(I16x8Neg, kRiscvI16x8Neg) \ ++ V(I16x8SConvertI8x16Low, kRiscvI16x8SConvertI8x16Low) \ ++ V(I16x8SConvertI8x16High, kRiscvI16x8SConvertI8x16High) \ ++ V(I16x8UConvertI8x16Low, kRiscvI16x8UConvertI8x16Low) \ ++ V(I16x8UConvertI8x16High, kRiscvI16x8UConvertI8x16High) \ ++ V(I16x8Abs, kRiscvI16x8Abs) \ ++ V(I16x8BitMask, kRiscvI16x8BitMask) \ ++ V(I8x16Neg, kRiscvI8x16Neg) \ ++ V(I8x16Abs, kRiscvI8x16Abs) \ ++ V(I8x16BitMask, kRiscvI8x16BitMask) \ ++ V(S128Not, kRiscvS128Not) \ ++ V(V32x4AnyTrue, kRiscvV32x4AnyTrue) \ ++ V(V32x4AllTrue, kRiscvV32x4AllTrue) \ ++ V(V16x8AnyTrue, kRiscvV16x8AnyTrue) \ ++ V(V16x8AllTrue, kRiscvV16x8AllTrue) \ ++ V(V8x16AnyTrue, kRiscvV8x16AnyTrue) \ ++ V(V8x16AllTrue, kRiscvV8x16AllTrue) ++ ++#define SIMD_SHIFT_OP_LIST(V) \ ++ V(I64x2Shl) \ ++ V(I64x2ShrS) \ ++ V(I64x2ShrU) \ ++ V(I32x4Shl) \ ++ V(I32x4ShrS) \ ++ V(I32x4ShrU) \ ++ V(I16x8Shl) \ ++ V(I16x8ShrS) \ ++ V(I16x8ShrU) \ ++ V(I8x16Shl) \ ++ V(I8x16ShrS) \ ++ V(I8x16ShrU) ++ ++#define SIMD_BINOP_LIST(V) \ ++ V(F64x2Add, kRiscvF64x2Add) \ ++ V(F64x2Sub, kRiscvF64x2Sub) \ ++ V(F64x2Mul, kRiscvF64x2Mul) \ ++ V(F64x2Div, kRiscvF64x2Div) \ ++ V(F64x2Min, kRiscvF64x2Min) \ ++ V(F64x2Max, kRiscvF64x2Max) \ ++ V(F64x2Eq, kRiscvF64x2Eq) \ ++ V(F64x2Ne, kRiscvF64x2Ne) \ ++ V(F64x2Lt, kRiscvF64x2Lt) \ ++ V(F64x2Le, kRiscvF64x2Le) \ ++ V(I64x2Add, kRiscvI64x2Add) \ ++ V(I64x2Sub, kRiscvI64x2Sub) \ ++ V(I64x2Mul, kRiscvI64x2Mul) \ ++ V(F32x4Add, kRiscvF32x4Add) \ ++ V(F32x4AddHoriz, kRiscvF32x4AddHoriz) \ ++ V(F32x4Sub, kRiscvF32x4Sub) \ ++ V(F32x4Mul, kRiscvF32x4Mul) \ ++ V(F32x4Div, kRiscvF32x4Div) \ ++ V(F32x4Max, kRiscvF32x4Max) \ ++ V(F32x4Min, kRiscvF32x4Min) \ ++ V(F32x4Eq, kRiscvF32x4Eq) \ ++ V(F32x4Ne, kRiscvF32x4Ne) \ ++ V(F32x4Lt, kRiscvF32x4Lt) \ ++ V(F32x4Le, kRiscvF32x4Le) \ ++ V(I32x4Add, kRiscvI32x4Add) \ ++ V(I32x4AddHoriz, kRiscvI32x4AddHoriz) \ ++ V(I32x4Sub, kRiscvI32x4Sub) \ ++ V(I32x4Mul, kRiscvI32x4Mul) \ ++ V(I32x4MaxS, kRiscvI32x4MaxS) \ ++ V(I32x4MinS, kRiscvI32x4MinS) \ ++ V(I32x4MaxU, kRiscvI32x4MaxU) \ ++ V(I32x4MinU, kRiscvI32x4MinU) \ ++ V(I32x4Eq, kRiscvI32x4Eq) \ ++ V(I32x4Ne, kRiscvI32x4Ne) \ ++ V(I32x4GtS, kRiscvI32x4GtS) \ ++ V(I32x4GeS, kRiscvI32x4GeS) \ ++ V(I32x4GtU, kRiscvI32x4GtU) \ ++ V(I32x4GeU, kRiscvI32x4GeU) \ ++ V(I16x8Add, kRiscvI16x8Add) \ ++ V(I16x8AddSaturateS, kRiscvI16x8AddSaturateS) \ ++ V(I16x8AddSaturateU, kRiscvI16x8AddSaturateU) \ ++ V(I16x8AddHoriz, kRiscvI16x8AddHoriz) \ ++ V(I16x8Sub, kRiscvI16x8Sub) \ ++ V(I16x8SubSaturateS, kRiscvI16x8SubSaturateS) \ ++ V(I16x8SubSaturateU, kRiscvI16x8SubSaturateU) \ ++ V(I16x8Mul, kRiscvI16x8Mul) \ ++ V(I16x8MaxS, kRiscvI16x8MaxS) \ ++ V(I16x8MinS, kRiscvI16x8MinS) \ ++ V(I16x8MaxU, kRiscvI16x8MaxU) \ ++ V(I16x8MinU, kRiscvI16x8MinU) \ ++ V(I16x8Eq, kRiscvI16x8Eq) \ ++ V(I16x8Ne, kRiscvI16x8Ne) \ ++ V(I16x8GtS, kRiscvI16x8GtS) \ ++ V(I16x8GeS, kRiscvI16x8GeS) \ ++ V(I16x8GtU, kRiscvI16x8GtU) \ ++ V(I16x8GeU, kRiscvI16x8GeU) \ ++ V(I16x8RoundingAverageU, kRiscvI16x8RoundingAverageU) \ ++ V(I16x8SConvertI32x4, kRiscvI16x8SConvertI32x4) \ ++ V(I16x8UConvertI32x4, kRiscvI16x8UConvertI32x4) \ ++ V(I8x16Add, kRiscvI8x16Add) \ ++ V(I8x16AddSaturateS, kRiscvI8x16AddSaturateS) \ ++ V(I8x16AddSaturateU, kRiscvI8x16AddSaturateU) \ ++ V(I8x16Sub, kRiscvI8x16Sub) \ ++ V(I8x16SubSaturateS, kRiscvI8x16SubSaturateS) \ ++ V(I8x16SubSaturateU, kRiscvI8x16SubSaturateU) \ ++ V(I8x16Mul, kRiscvI8x16Mul) \ ++ V(I8x16MaxS, kRiscvI8x16MaxS) \ ++ V(I8x16MinS, kRiscvI8x16MinS) \ ++ V(I8x16MaxU, kRiscvI8x16MaxU) \ ++ V(I8x16MinU, kRiscvI8x16MinU) \ ++ V(I8x16Eq, kRiscvI8x16Eq) \ ++ V(I8x16Ne, kRiscvI8x16Ne) \ ++ V(I8x16GtS, kRiscvI8x16GtS) \ ++ V(I8x16GeS, kRiscvI8x16GeS) \ ++ V(I8x16GtU, kRiscvI8x16GtU) \ ++ V(I8x16GeU, kRiscvI8x16GeU) \ ++ V(I8x16RoundingAverageU, kRiscvI8x16RoundingAverageU) \ ++ V(I8x16SConvertI16x8, kRiscvI8x16SConvertI16x8) \ ++ V(I8x16UConvertI16x8, kRiscvI8x16UConvertI16x8) \ ++ V(S128And, kRiscvS128And) \ ++ V(S128Or, kRiscvS128Or) \ ++ V(S128Xor, kRiscvS128Xor) \ ++ V(S128AndNot, kRiscvS128AndNot) ++ ++void InstructionSelector::VisitS128Const(Node* node) { ++ RiscvOperandGenerator g(this); ++ static const int kUint32Immediates = kSimd128Size / sizeof(uint32_t); ++ uint32_t val[kUint32Immediates]; ++ memcpy(val, S128ImmediateParameterOf(node->op()).data(), kSimd128Size); ++ // If all bytes are zeros or ones, avoid emitting code for generic constants ++ bool all_zeros = !(val[0] || val[1] || val[2] || val[3]); ++ bool all_ones = val[0] == UINT32_MAX && val[1] == UINT32_MAX && ++ val[2] == UINT32_MAX && val[3] == UINT32_MAX; ++ InstructionOperand dst = g.DefineAsRegister(node); ++ if (all_zeros) { ++ Emit(kRiscvS128Zero, dst); ++ } else if (all_ones) { ++ Emit(kRiscvS128AllOnes, dst); ++ } else { ++ Emit(kRiscvS128Const, dst, g.UseImmediate(val[0]), g.UseImmediate(val[1]), ++ g.UseImmediate(val[2]), g.UseImmediate(val[3])); ++ } ++} ++ ++void InstructionSelector::VisitS128Zero(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvS128Zero, g.DefineAsRegister(node)); ++} ++ ++#define SIMD_VISIT_SPLAT(Type) \ ++ void InstructionSelector::Visit##Type##Splat(Node* node) { \ ++ VisitRR(this, kRiscv##Type##Splat, node); \ ++ } ++SIMD_TYPE_LIST(SIMD_VISIT_SPLAT) ++SIMD_VISIT_SPLAT(F64x2) ++#undef SIMD_VISIT_SPLAT ++ ++#define SIMD_VISIT_EXTRACT_LANE(Type, Sign) \ ++ void InstructionSelector::Visit##Type##ExtractLane##Sign(Node* node) { \ ++ VisitRRI(this, kRiscv##Type##ExtractLane##Sign, node); \ ++ } ++SIMD_VISIT_EXTRACT_LANE(F64x2, ) ++SIMD_VISIT_EXTRACT_LANE(F32x4, ) ++SIMD_VISIT_EXTRACT_LANE(I32x4, ) ++SIMD_VISIT_EXTRACT_LANE(I16x8, U) ++SIMD_VISIT_EXTRACT_LANE(I16x8, S) ++SIMD_VISIT_EXTRACT_LANE(I8x16, U) ++SIMD_VISIT_EXTRACT_LANE(I8x16, S) ++#undef SIMD_VISIT_EXTRACT_LANE ++ ++#define SIMD_VISIT_REPLACE_LANE(Type) \ ++ void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \ ++ VisitRRIR(this, kRiscv##Type##ReplaceLane, node); \ ++ } ++SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE) ++SIMD_VISIT_REPLACE_LANE(F64x2) ++#undef SIMD_VISIT_REPLACE_LANE ++ ++#define SIMD_VISIT_UNOP(Name, instruction) \ ++ void InstructionSelector::Visit##Name(Node* node) { \ ++ VisitRR(this, instruction, node); \ ++ } ++SIMD_UNOP_LIST(SIMD_VISIT_UNOP) ++#undef SIMD_VISIT_UNOP ++ ++#define SIMD_VISIT_SHIFT_OP(Name) \ ++ void InstructionSelector::Visit##Name(Node* node) { \ ++ VisitSimdShift(this, kRiscv##Name, node); \ ++ } ++SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP) ++#undef SIMD_VISIT_SHIFT_OP ++ ++#define SIMD_VISIT_BINOP(Name, instruction) \ ++ void InstructionSelector::Visit##Name(Node* node) { \ ++ VisitRRR(this, instruction, node); \ ++ } ++SIMD_BINOP_LIST(SIMD_VISIT_BINOP) ++#undef SIMD_VISIT_BINOP ++ ++void InstructionSelector::VisitS128Select(Node* node) { ++ VisitRRRR(this, kRiscvS128Select, node); ++} ++ ++namespace { ++ ++struct ShuffleEntry { ++ uint8_t shuffle[kSimd128Size]; ++ ArchOpcode opcode; ++}; ++ ++static const ShuffleEntry arch_shuffles[] = { ++ {{0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23}, ++ kRiscvS32x4InterleaveRight}, ++ {{8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31}, ++ kRiscvS32x4InterleaveLeft}, ++ {{0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27}, ++ kRiscvS32x4PackEven}, ++ {{4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31}, ++ kRiscvS32x4PackOdd}, ++ {{0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27}, ++ kRiscvS32x4InterleaveEven}, ++ {{4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31}, ++ kRiscvS32x4InterleaveOdd}, ++ ++ {{0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23}, ++ kRiscvS16x8InterleaveRight}, ++ {{8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31}, ++ kRiscvS16x8InterleaveLeft}, ++ {{0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29}, ++ kRiscvS16x8PackEven}, ++ {{2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31}, ++ kRiscvS16x8PackOdd}, ++ {{0, 1, 16, 17, 4, 5, 20, 21, 8, 9, 24, 25, 12, 13, 28, 29}, ++ kRiscvS16x8InterleaveEven}, ++ {{2, 3, 18, 19, 6, 7, 22, 23, 10, 11, 26, 27, 14, 15, 30, 31}, ++ kRiscvS16x8InterleaveOdd}, ++ {{6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9}, ++ kRiscvS16x4Reverse}, ++ {{2, 3, 0, 1, 6, 7, 4, 5, 10, 11, 8, 9, 14, 15, 12, 13}, ++ kRiscvS16x2Reverse}, ++ ++ {{0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23}, ++ kRiscvS8x16InterleaveRight}, ++ {{8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31}, ++ kRiscvS8x16InterleaveLeft}, ++ {{0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30}, ++ kRiscvS8x16PackEven}, ++ {{1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31}, ++ kRiscvS8x16PackOdd}, ++ {{0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30}, ++ kRiscvS8x16InterleaveEven}, ++ {{1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31}, ++ kRiscvS8x16InterleaveOdd}, ++ {{7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8}, kRiscvS8x8Reverse}, ++ {{3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12}, kRiscvS8x4Reverse}, ++ {{1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14}, ++ kRiscvS8x2Reverse}}; ++ ++bool TryMatchArchShuffle(const uint8_t* shuffle, const ShuffleEntry* table, ++ size_t num_entries, bool is_swizzle, ++ ArchOpcode* opcode) { ++ uint8_t mask = is_swizzle ? kSimd128Size - 1 : 2 * kSimd128Size - 1; ++ for (size_t i = 0; i < num_entries; ++i) { ++ const ShuffleEntry& entry = table[i]; ++ int j = 0; ++ for (; j < kSimd128Size; ++j) { ++ if ((entry.shuffle[j] & mask) != (shuffle[j] & mask)) { ++ break; ++ } ++ } ++ if (j == kSimd128Size) { ++ *opcode = entry.opcode; ++ return true; ++ } ++ } ++ return false; ++} ++ ++} // namespace ++ ++void InstructionSelector::VisitI8x16Shuffle(Node* node) { ++ uint8_t shuffle[kSimd128Size]; ++ bool is_swizzle; ++ CanonicalizeShuffle(node, shuffle, &is_swizzle); ++ uint8_t shuffle32x4[4]; ++ ArchOpcode opcode; ++ if (TryMatchArchShuffle(shuffle, arch_shuffles, arraysize(arch_shuffles), ++ is_swizzle, &opcode)) { ++ VisitRRR(this, opcode, node); ++ return; ++ } ++ Node* input0 = node->InputAt(0); ++ Node* input1 = node->InputAt(1); ++ uint8_t offset; ++ RiscvOperandGenerator g(this); ++ if (wasm::SimdShuffle::TryMatchConcat(shuffle, &offset)) { ++ Emit(kRiscvS8x16Concat, g.DefineSameAsFirst(node), g.UseRegister(input1), ++ g.UseRegister(input0), g.UseImmediate(offset)); ++ return; ++ } ++ if (wasm::SimdShuffle::TryMatch32x4Shuffle(shuffle, shuffle32x4)) { ++ Emit(kRiscvS32x4Shuffle, g.DefineAsRegister(node), g.UseRegister(input0), ++ g.UseRegister(input1), ++ g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle32x4))); ++ return; ++ } ++ Emit(kRiscvI8x16Shuffle, g.DefineAsRegister(node), g.UseRegister(input0), ++ g.UseRegister(input1), ++ g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle)), ++ g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle + 4)), ++ g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle + 8)), ++ g.UseImmediate(wasm::SimdShuffle::Pack4Lanes(shuffle + 12))); ++} ++ ++void InstructionSelector::VisitI8x16Swizzle(Node* node) { ++ RiscvOperandGenerator g(this); ++ InstructionOperand temps[] = {g.TempSimd128Register()}; ++ // We don't want input 0 or input 1 to be the same as output, since we will ++ // modify output before do the calculation. ++ Emit(kRiscvI8x16Swizzle, g.DefineAsRegister(node), ++ g.UseUniqueRegister(node->InputAt(0)), ++ g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); ++} ++ ++void InstructionSelector::VisitSignExtendWord8ToInt32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvSignExtendByte, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitSignExtendWord16ToInt32(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvSignExtendShort, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitSignExtendWord8ToInt64(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvSignExtendByte, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitSignExtendWord16ToInt64(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvSignExtendShort, g.DefineAsRegister(node), ++ g.UseRegister(node->InputAt(0))); ++} ++ ++void InstructionSelector::VisitSignExtendWord32ToInt64(Node* node) { ++ RiscvOperandGenerator g(this); ++ Emit(kRiscvShl32, g.DefineAsRegister(node), g.UseRegister(node->InputAt(0)), ++ g.TempImmediate(0)); ++} ++ ++void InstructionSelector::VisitF32x4Pmin(Node* node) { ++ VisitUniqueRRR(this, kRiscvF32x4Pmin, node); ++} ++ ++void InstructionSelector::VisitF32x4Pmax(Node* node) { ++ VisitUniqueRRR(this, kRiscvF32x4Pmax, node); ++} ++ ++void InstructionSelector::VisitF64x2Pmin(Node* node) { ++ VisitUniqueRRR(this, kRiscvF64x2Pmin, node); ++} ++ ++void InstructionSelector::VisitF64x2Pmax(Node* node) { ++ VisitUniqueRRR(this, kRiscvF64x2Pmax, node); ++} ++ ++// static ++MachineOperatorBuilder::Flags ++InstructionSelector::SupportedMachineOperatorFlags() { ++ MachineOperatorBuilder::Flags flags = MachineOperatorBuilder::kNoFlags; ++ return flags | MachineOperatorBuilder::kWord32ShiftIsSafe | ++ MachineOperatorBuilder::kInt32DivIsSafe | ++ MachineOperatorBuilder::kUint32DivIsSafe | ++ MachineOperatorBuilder::kFloat64RoundDown | ++ MachineOperatorBuilder::kFloat32RoundDown | ++ MachineOperatorBuilder::kFloat64RoundUp | ++ MachineOperatorBuilder::kFloat32RoundUp | ++ MachineOperatorBuilder::kFloat64RoundTruncate | ++ MachineOperatorBuilder::kFloat32RoundTruncate | ++ MachineOperatorBuilder::kFloat64RoundTiesEven | ++ MachineOperatorBuilder::kFloat32RoundTiesEven; ++} ++ ++// static ++MachineOperatorBuilder::AlignmentRequirements ++InstructionSelector::AlignmentRequirements() { ++ return MachineOperatorBuilder::AlignmentRequirements:: ++ NoUnalignedAccessSupport(); ++} ++ ++#undef SIMD_BINOP_LIST ++#undef SIMD_SHIFT_OP_LIST ++#undef SIMD_UNOP_LIST ++#undef SIMD_TYPE_LIST ++#undef TRACE_UNIMPL ++#undef TRACE ++ ++} // namespace compiler ++} // namespace internal ++} // namespace v8 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/c-linkage.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/compiler/c-linkage.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/compiler/c-linkage.cc +@@ -131,6 +131,19 @@ namespace { + d8.bit() | d9.bit() | d10.bit() | d11.bit() | d12.bit() | d13.bit() | \ + d14.bit() | d15.bit() + ++#elif V8_TARGET_ARCH_RISCV64 ++// =========================================================================== ++// == riscv64 ================================================================= ++// =========================================================================== ++#define PARAM_REGISTERS a0, a1, a2, a3, a4, a5, a6, a7 ++// fp is not part of CALLEE_SAVE_REGISTERS (similar to how MIPS64 or PPC defines ++// it) ++#define CALLEE_SAVE_REGISTERS \ ++ s1.bit() | s2.bit() | s3.bit() | s4.bit() | s5.bit() | s6.bit() | s7.bit() | \ ++ s8.bit() | s9.bit() | s10.bit() | s11.bit() ++#define CALLEE_SAVE_FP_REGISTERS \ ++ fs0.bit() | fs1.bit() | fs2.bit() | fs3.bit() | fs4.bit() | fs5.bit() | \ ++ fs6.bit() | fs7.bit() | fs8.bit() | fs9.bit() | fs10.bit() | fs11.bit() + #else + // =========================================================================== + // == unknown ================================================================ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/debug/debug-evaluate.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/debug/debug-evaluate.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/debug/debug-evaluate.cc +@@ -1060,8 +1060,10 @@ void DebugEvaluate::VerifyTransitiveBuil + } + } + CHECK(!failed); +-#if defined(V8_TARGET_ARCH_PPC) || defined(V8_TARGET_ARCH_PPC64) || \ +- defined(V8_TARGET_ARCH_MIPS64) ++ // FIXME (RISCV): does RISCV need this? ++#if defined(V8_TARGET_ARCH_PPC) || defined(V8_TARGET_ARCH_PPC64) || \ ++ defined(V8_TARGET_ARCH_MIPS64) || defined(V8_TARGET_ARCH_RISCV64) || \ ++ defined(V8_TARGET_ARCH_RISCV) + // Isolate-independent builtin calls and jumps do not emit reloc infos + // on PPC. We try to avoid using PC relative code due to performance + // issue with especially older hardwares. +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/debug/riscv64/debug-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/debug/riscv64/debug-riscv64.cc +@@ -0,0 +1,55 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/macro-assembler.h" ++#include "src/debug/debug.h" ++#include "src/debug/liveedit.h" ++#include "src/execution/frames-inl.h" ++ ++namespace v8 { ++namespace internal { ++ ++#define __ ACCESS_MASM(masm) ++ ++void DebugCodegen::GenerateHandleDebuggerStatement(MacroAssembler* masm) { ++ { ++ FrameScope scope(masm, StackFrame::INTERNAL); ++ __ CallRuntime(Runtime::kHandleDebuggerStatement, 0); ++ } ++ __ MaybeDropFrames(); ++ ++ // Return to caller. ++ __ Ret(); ++} ++ ++void DebugCodegen::GenerateFrameDropperTrampoline(MacroAssembler* masm) { ++ // Frame is being dropped: ++ // - Drop to the target frame specified by a1. ++ // - Look up current function on the frame. ++ // - Leave the frame. ++ // - Restart the frame by calling the function. ++ __ mv(fp, a1); ++ __ Ld(a1, MemOperand(fp, StandardFrameConstants::kFunctionOffset)); ++ ++ // Pop return address and frame. ++ __ LeaveFrame(StackFrame::INTERNAL); ++ ++ __ Ld(a0, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset)); ++ __ Lhu(a0, ++ FieldMemOperand(a0, SharedFunctionInfo::kFormalParameterCountOffset)); ++ __ mv(a2, a0); ++ ++ __ InvokeFunction(a1, a2, a0, JUMP_FUNCTION); ++} ++ ++const bool LiveEdit::kFrameDropperSupported = true; ++ ++#undef __ ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/deoptimizer/riscv64/deoptimizer-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/deoptimizer/riscv64/deoptimizer-riscv64.cc +@@ -0,0 +1,240 @@ ++// Copyright 2011 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/register-configuration.h" ++#include "src/codegen/safepoint-table.h" ++#include "src/deoptimizer/deoptimizer.h" ++ ++namespace v8 { ++namespace internal { ++ ++const bool Deoptimizer::kSupportsFixedDeoptExitSizes = false; ++const int Deoptimizer::kNonLazyDeoptExitSize = 0; ++const int Deoptimizer::kLazyDeoptExitSize = 0; ++ ++#define __ masm-> ++ ++// This code tries to be close to ia32 code so that any changes can be ++// easily ported. ++void Deoptimizer::GenerateDeoptimizationEntries(MacroAssembler* masm, ++ Isolate* isolate, ++ DeoptimizeKind deopt_kind) { ++ NoRootArrayScope no_root_array(masm); ++ ++ // Unlike on ARM we don't save all the registers, just the useful ones. ++ // For the rest, there are gaps on the stack, so the offsets remain the same. ++ const int kNumberOfRegisters = Register::kNumRegisters; ++ ++ RegList restored_regs = kJSCallerSaved | kCalleeSaved; ++ RegList saved_regs = restored_regs | sp.bit() | ra.bit(); ++ ++ const int kDoubleRegsSize = kDoubleSize * DoubleRegister::kNumRegisters; ++ ++ // Save all double FPU registers before messing with them. ++ __ Sub64(sp, sp, Operand(kDoubleRegsSize)); ++ const RegisterConfiguration* config = RegisterConfiguration::Default(); ++ for (int i = 0; i < config->num_allocatable_double_registers(); ++i) { ++ int code = config->GetAllocatableDoubleCode(i); ++ const DoubleRegister fpu_reg = DoubleRegister::from_code(code); ++ int offset = code * kDoubleSize; ++ __ StoreDouble(fpu_reg, MemOperand(sp, offset)); ++ } ++ ++ // Push saved_regs (needed to populate FrameDescription::registers_). ++ // Leave gaps for other registers. ++ __ Sub64(sp, sp, kNumberOfRegisters * kPointerSize); ++ for (int16_t i = kNumberOfRegisters - 1; i >= 0; i--) { ++ if ((saved_regs & (1 << i)) != 0) { ++ __ Sd(ToRegister(i), MemOperand(sp, kPointerSize * i)); ++ } ++ } ++ ++ __ li(a2, Operand(ExternalReference::Create( ++ IsolateAddressId::kCEntryFPAddress, isolate))); ++ __ Sd(fp, MemOperand(a2)); ++ ++ const int kSavedRegistersAreaSize = ++ (kNumberOfRegisters * kPointerSize) + kDoubleRegsSize; ++ ++ // Get the bailout is passed as kRootRegister by the caller. ++ __ mv(a2, kRootRegister); ++ ++ // Get the address of the location in the code object (a3) (return ++ // address for lazy deoptimization) and compute the fp-to-sp delta in ++ // register a4. ++ __ mv(a3, ra); ++ __ Add64(a4, sp, Operand(kSavedRegistersAreaSize)); ++ ++ __ Sub64(a4, fp, a4); ++ ++ // Allocate a new deoptimizer object. ++ __ PrepareCallCFunction(6, a5); ++ // Pass six arguments, according to n64 ABI. ++ __ mv(a0, zero_reg); ++ Label context_check; ++ __ Ld(a1, MemOperand(fp, CommonFrameConstants::kContextOrFrameTypeOffset)); ++ __ JumpIfSmi(a1, &context_check); ++ __ Ld(a0, MemOperand(fp, StandardFrameConstants::kFunctionOffset)); ++ __ bind(&context_check); ++ __ li(a1, Operand(static_cast(deopt_kind))); ++ // a2: bailout id already loaded. ++ // a3: code address or 0 already loaded. ++ // a4: already has fp-to-sp delta. ++ __ li(a5, Operand(ExternalReference::isolate_address(isolate))); ++ ++ // Call Deoptimizer::New(). ++ { ++ AllowExternalCallThatCantCauseGC scope(masm); ++ __ CallCFunction(ExternalReference::new_deoptimizer_function(), 6); ++ } ++ ++ // Preserve "deoptimizer" object in register a0 and get the input ++ // frame descriptor pointer to a1 (deoptimizer->input_); ++ // Move deopt-obj to a0 for call to Deoptimizer::ComputeOutputFrames() below. ++ __ Ld(a1, MemOperand(a0, Deoptimizer::input_offset())); ++ ++ // Copy core registers into FrameDescription::registers_[kNumRegisters]. ++ DCHECK_EQ(Register::kNumRegisters, kNumberOfRegisters); ++ for (int i = 0; i < kNumberOfRegisters; i++) { ++ int offset = (i * kPointerSize) + FrameDescription::registers_offset(); ++ if ((saved_regs & (1 << i)) != 0) { ++ __ Ld(a2, MemOperand(sp, i * kPointerSize)); ++ __ Sd(a2, MemOperand(a1, offset)); ++ } else if (FLAG_debug_code) { ++ __ li(a2, kDebugZapValue); ++ __ Sd(a2, MemOperand(a1, offset)); ++ } ++ } ++ ++ int double_regs_offset = FrameDescription::double_registers_offset(); ++ // Copy FPU registers to ++ // double_registers_[DoubleRegister::kNumAllocatableRegisters] ++ for (int i = 0; i < config->num_allocatable_double_registers(); ++i) { ++ int code = config->GetAllocatableDoubleCode(i); ++ int dst_offset = code * kDoubleSize + double_regs_offset; ++ int src_offset = code * kDoubleSize + kNumberOfRegisters * kPointerSize; ++ __ LoadDouble(ft0, MemOperand(sp, src_offset)); ++ __ StoreDouble(ft0, MemOperand(a1, dst_offset)); ++ } ++ ++ // Remove the saved registers from the stack. ++ __ Add64(sp, sp, Operand(kSavedRegistersAreaSize)); ++ ++ // Compute a pointer to the unwinding limit in register a2; that is ++ // the first stack slot not part of the input frame. ++ __ Ld(a2, MemOperand(a1, FrameDescription::frame_size_offset())); ++ __ Add64(a2, a2, sp); ++ ++ // Unwind the stack down to - but not including - the unwinding ++ // limit and copy the contents of the activation frame to the input ++ // frame description. ++ __ Add64(a3, a1, Operand(FrameDescription::frame_content_offset())); ++ Label pop_loop; ++ Label pop_loop_header; ++ __ BranchShort(&pop_loop_header); ++ __ bind(&pop_loop); ++ __ pop(a4); ++ __ Sd(a4, MemOperand(a3, 0)); ++ __ addi(a3, a3, sizeof(uint64_t)); ++ __ bind(&pop_loop_header); ++ __ BranchShort(&pop_loop, ne, a2, Operand(sp)); ++ // Compute the output frame in the deoptimizer. ++ __ push(a0); // Preserve deoptimizer object across call. ++ // a0: deoptimizer object; a1: scratch. ++ __ PrepareCallCFunction(1, a1); ++ // Call Deoptimizer::ComputeOutputFrames(). ++ { ++ AllowExternalCallThatCantCauseGC scope(masm); ++ __ CallCFunction(ExternalReference::compute_output_frames_function(), 1); ++ } ++ __ pop(a0); // Restore deoptimizer object (class Deoptimizer). ++ ++ __ Ld(sp, MemOperand(a0, Deoptimizer::caller_frame_top_offset())); ++ ++ // Replace the current (input) frame with the output frames. ++ Label outer_push_loop, inner_push_loop, outer_loop_header, inner_loop_header; ++ // Outer loop state: a4 = current "FrameDescription** output_", ++ // a1 = one past the last FrameDescription**. ++ __ Lw(a1, MemOperand(a0, Deoptimizer::output_count_offset())); ++ __ Ld(a4, MemOperand(a0, Deoptimizer::output_offset())); // a4 is output_. ++ __ CalcScaledAddress(a1, a4, a1, kPointerSizeLog2); ++ __ BranchShort(&outer_loop_header); ++ __ bind(&outer_push_loop); ++ // Inner loop state: a2 = current FrameDescription*, a3 = loop index. ++ __ Ld(a2, MemOperand(a4, 0)); // output_[ix] ++ __ Ld(a3, MemOperand(a2, FrameDescription::frame_size_offset())); ++ __ BranchShort(&inner_loop_header); ++ __ bind(&inner_push_loop); ++ __ Sub64(a3, a3, Operand(sizeof(uint64_t))); ++ __ Add64(a6, a2, Operand(a3)); ++ __ Ld(a7, MemOperand(a6, FrameDescription::frame_content_offset())); ++ __ push(a7); ++ __ bind(&inner_loop_header); ++ __ BranchShort(&inner_push_loop, ne, a3, Operand(zero_reg)); ++ ++ __ Add64(a4, a4, Operand(kPointerSize)); ++ __ bind(&outer_loop_header); ++ __ BranchShort(&outer_push_loop, lt, a4, Operand(a1)); ++ ++ __ Ld(a1, MemOperand(a0, Deoptimizer::input_offset())); ++ for (int i = 0; i < config->num_allocatable_double_registers(); ++i) { ++ int code = config->GetAllocatableDoubleCode(i); ++ const DoubleRegister fpu_reg = DoubleRegister::from_code(code); ++ int src_offset = code * kDoubleSize + double_regs_offset; ++ __ LoadDouble(fpu_reg, MemOperand(a1, src_offset)); ++ } ++ ++ // Push pc and continuation from the last output frame. ++ __ Ld(a6, MemOperand(a2, FrameDescription::pc_offset())); ++ __ push(a6); ++ __ Ld(a6, MemOperand(a2, FrameDescription::continuation_offset())); ++ __ push(a6); ++ ++ // Technically restoring 't3' should work unless zero_reg is also restored ++ // but it's safer to check for this. ++ DCHECK(!(t3.bit() & restored_regs)); ++ // Restore the registers from the last output frame. ++ __ mv(t3, a2); ++ for (int i = kNumberOfRegisters - 1; i >= 0; i--) { ++ int offset = (i * kPointerSize) + FrameDescription::registers_offset(); ++ if ((restored_regs & (1 << i)) != 0) { ++ __ Ld(ToRegister(i), MemOperand(t3, offset)); ++ } ++ } ++ ++ __ pop(t3); // Get continuation, leave pc on stack. ++ __ pop(ra); ++ __ Jump(t3); ++ __ stop(); ++} ++ ++// Maximum size of a table entry generated below. ++// FIXME(RISCV): Is this value correct? ++const int Deoptimizer::table_entry_size_ = 2 * kInstrSize; ++ ++Float32 RegisterValues::GetFloatRegister(unsigned n) const { ++ return Float32::FromBits( ++ static_cast(double_registers_[n].get_bits())); ++} ++ ++void FrameDescription::SetCallerPc(unsigned offset, intptr_t value) { ++ SetFrameSlot(offset, value); ++} ++ ++void FrameDescription::SetCallerFp(unsigned offset, intptr_t value) { ++ SetFrameSlot(offset, value); ++} ++ ++void FrameDescription::SetCallerConstantPool(unsigned offset, intptr_t value) { ++ // No embedded constant pool support. ++ UNREACHABLE(); ++} ++ ++void FrameDescription::SetPc(intptr_t pc) { pc_ = pc; } ++ ++#undef __ ++ ++} // namespace internal ++} // namespace v8 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/diagnostics/perf-jit.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/diagnostics/perf-jit.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/diagnostics/perf-jit.h +@@ -86,6 +86,7 @@ class PerfJitLogger : public CodeEventLo + static const uint32_t kElfMachARM64 = 183; + static const uint32_t kElfMachS390x = 22; + static const uint32_t kElfMachPPC64 = 21; ++ static const uint32_t kElfMachRISCV = 243; + + uint32_t GetElfMach() { + #if V8_TARGET_ARCH_IA32 +@@ -104,6 +105,8 @@ class PerfJitLogger : public CodeEventLo + return kElfMachS390x; + #elif V8_TARGET_ARCH_PPC64 + return kElfMachPPC64; ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ return kElfMachRISCV; + #else + UNIMPLEMENTED(); + return 0; +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/diagnostics/riscv64/disasm-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/diagnostics/riscv64/disasm-riscv64.cc +@@ -0,0 +1,1448 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++// A Disassembler object is used to disassemble a block of code instruction by ++// instruction. The default implementation of the NameConverter object can be ++// overriden to modify register names or to do symbol lookup on addresses. ++// ++// The example below will disassemble a block of code and print it to stdout. ++// ++// NameConverter converter; ++// Disassembler d(converter); ++// for (byte* pc = begin; pc < end;) { ++// v8::internal::EmbeddedVector buffer; ++// byte* prev_pc = pc; ++// pc += d.InstructionDecode(buffer, pc); ++// printf("%p %08x %s\n", ++// prev_pc, *reinterpret_cast(prev_pc), buffer); ++// } ++// ++// The Disassembler class also has a convenience method to disassemble a block ++// of code into a FILE*, meaning that the above functionality could also be ++// achieved by just calling Disassembler::Disassemble(stdout, begin, end); ++ ++#include ++#include ++#include ++#include ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/base/platform/platform.h" ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/diagnostics/disasm.h" ++ ++namespace v8 { ++namespace internal { ++ ++//------------------------------------------------------------------------------ ++ ++// Decoder decodes and disassembles instructions into an output buffer. ++// It uses the converter to convert register names and call destinations into ++// more informative description. ++class Decoder { ++ public: ++ Decoder(const disasm::NameConverter& converter, ++ v8::internal::Vector out_buffer) ++ : converter_(converter), out_buffer_(out_buffer), out_buffer_pos_(0) { ++ out_buffer_[out_buffer_pos_] = '\0'; ++ } ++ ++ ~Decoder() {} ++ ++ // Writes one disassembled instruction into 'buffer' (0-terminated). ++ // Returns the length of the disassembled machine instruction in bytes. ++ int InstructionDecode(byte* instruction); ++ ++ private: ++ // Bottleneck functions to print into the out_buffer. ++ void PrintChar(const char ch); ++ void Print(const char* str); ++ ++ // Printing of common values. ++ void PrintRegister(int reg); ++ void PrintFPURegister(int freg); ++ void PrintFPUStatusRegister(int freg); ++ void PrintRs1(Instruction* instr); ++ void PrintRs2(Instruction* instr); ++ void PrintRd(Instruction* instr); ++ void PrintVs1(Instruction* instr); ++ void PrintFRs1(Instruction* instr); ++ void PrintFRs2(Instruction* instr); ++ void PrintFRs3(Instruction* instr); ++ void PrintFRd(Instruction* instr); ++ void PrintImm12(Instruction* instr); ++ void PrintImm12X(Instruction* instr); ++ void PrintImm20U(Instruction* instr); ++ void PrintImm20J(Instruction* instr); ++ void PrintShamt(Instruction* instr); ++ void PrintShamt32(Instruction* instr); ++ void PrintAcquireRelease(Instruction* instr); ++ void PrintBranchOffset(Instruction* instr); ++ void PrintStoreOffset(Instruction* instr); ++ void PrintCSRReg(Instruction* instr); ++ void PrintRoundingMode(Instruction* instr); ++ void PrintMemoryOrder(Instruction* instr, bool is_pred); ++ ++ // Each of these functions decodes one particular instruction type. ++ void DecodeRType(Instruction* instr); ++ void DecodeR4Type(Instruction* instr); ++ void DecodeRAType(Instruction* instr); ++ void DecodeRFPType(Instruction* instr); ++ void DecodeIType(Instruction* instr); ++ void DecodeSType(Instruction* instr); ++ void DecodeBType(Instruction* instr); ++ void DecodeUType(Instruction* instr); ++ void DecodeJType(Instruction* instr); ++ ++ // Printing of instruction name. ++ void PrintInstructionName(Instruction* instr); ++ ++ // Handle formatting of instructions and their options. ++ int FormatRegister(Instruction* instr, const char* option); ++ int FormatFPURegisterOrRoundMode(Instruction* instr, const char* option); ++ int FormatOption(Instruction* instr, const char* option); ++ void Format(Instruction* instr, const char* format); ++ void Unknown(Instruction* instr); ++ ++ const disasm::NameConverter& converter_; ++ v8::internal::Vector out_buffer_; ++ int out_buffer_pos_; ++ ++ DISALLOW_COPY_AND_ASSIGN(Decoder); ++}; ++ ++// Support for assertions in the Decoder formatting functions. ++#define STRING_STARTS_WITH(string, compare_string) \ ++ (strncmp(string, compare_string, strlen(compare_string)) == 0) ++ ++// Append the ch to the output buffer. ++void Decoder::PrintChar(const char ch) { out_buffer_[out_buffer_pos_++] = ch; } ++ ++// Append the str to the output buffer. ++void Decoder::Print(const char* str) { ++ char cur = *str++; ++ while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) { ++ PrintChar(cur); ++ cur = *str++; ++ } ++ out_buffer_[out_buffer_pos_] = 0; ++} ++ ++// Print the register name according to the active name converter. ++void Decoder::PrintRegister(int reg) { ++ Print(converter_.NameOfCPURegister(reg)); ++} ++ ++void Decoder::PrintRs1(Instruction* instr) { ++ int reg = instr->Rs1Value(); ++ PrintRegister(reg); ++} ++ ++void Decoder::PrintRs2(Instruction* instr) { ++ int reg = instr->Rs2Value(); ++ PrintRegister(reg); ++} ++ ++void Decoder::PrintRd(Instruction* instr) { ++ int reg = instr->RdValue(); ++ PrintRegister(reg); ++} ++ ++void Decoder::PrintVs1(Instruction* instr) { ++ int val = instr->Rs1Value(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", val); ++} ++ ++// Print the FPUregister name according to the active name converter. ++void Decoder::PrintFPURegister(int freg) { ++ Print(converter_.NameOfXMMRegister(freg)); ++} ++ ++void Decoder::PrintFRs1(Instruction* instr) { ++ int reg = instr->Rs1Value(); ++ PrintFPURegister(reg); ++} ++ ++void Decoder::PrintFRs2(Instruction* instr) { ++ int reg = instr->Rs2Value(); ++ PrintFPURegister(reg); ++} ++ ++void Decoder::PrintFRs3(Instruction* instr) { ++ int reg = instr->Rs3Value(); ++ PrintFPURegister(reg); ++} ++ ++void Decoder::PrintFRd(Instruction* instr) { ++ int reg = instr->RdValue(); ++ PrintFPURegister(reg); ++} ++ ++void Decoder::PrintImm12X(Instruction* instr) { ++ int32_t imm = instr->Imm12Value(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); ++} ++ ++void Decoder::PrintImm12(Instruction* instr) { ++ int32_t imm = instr->Imm12Value(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); ++} ++ ++void Decoder::PrintBranchOffset(Instruction* instr) { ++ int32_t imm = instr->BranchOffset(); ++ const char* target = converter_.NameOfAddress(reinterpret_cast(instr) + imm); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d -> %s", imm, target); ++} ++ ++void Decoder::PrintStoreOffset(Instruction* instr) { ++ int32_t imm = instr->StoreOffset(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); ++} ++ ++void Decoder::PrintImm20U(Instruction* instr) { ++ int32_t imm = instr->Imm20UValue(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); ++} ++ ++void Decoder::PrintImm20J(Instruction* instr) { ++ int32_t imm = instr->Imm20JValue(); ++ const char* target = converter_.NameOfAddress(reinterpret_cast(instr) + imm); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d -> %s", imm, target); ++} ++ ++void Decoder::PrintShamt(Instruction* instr) { ++ int32_t imm = instr->Shamt(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); ++} ++ ++void Decoder::PrintShamt32(Instruction* instr) { ++ int32_t imm = instr->Shamt32(); ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); ++} ++ ++void Decoder::PrintAcquireRelease(Instruction* instr) { ++ bool aq = instr->AqValue(); ++ bool rl = instr->RlValue(); ++ if (aq || rl) { ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "."); ++ } ++ if (aq) { ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "aq"); ++ } ++ if (rl) { ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "rl"); ++ } ++} ++ ++void Decoder::PrintCSRReg(Instruction* instr) { ++ int32_t csr_reg = instr->CsrValue(); ++ std::string s; ++ switch (csr_reg) { ++ case csr_fflags: // Floating-Point Accrued Exceptions (RW) ++ s = "csr_fflags"; ++ break; ++ case csr_frm: // Floating-Point Dynamic Rounding Mode (RW) ++ s = "csr_frm"; ++ break; ++ case csr_fcsr: // Floating-Point Control and Status Register (RW) ++ s = "csr_fcsr"; ++ break; ++ case csr_cycle: ++ s = "csr_cycle"; ++ break; ++ case csr_time: ++ s = "csr_time"; ++ break; ++ case csr_instret: ++ s = "csr_instret"; ++ break; ++ case csr_cycleh: ++ s = "csr_cycleh"; ++ break; ++ case csr_timeh: ++ s = "csr_timeh"; ++ break; ++ case csr_instreth: ++ s = "csr_instreth"; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str()); ++} ++ ++void Decoder::PrintRoundingMode(Instruction* instr) { ++ int frm = instr->RoundMode(); ++ std::string s; ++ switch (frm) { ++ case RNE: ++ s = "RNE"; ++ break; ++ case RTZ: ++ s = "RTZ"; ++ break; ++ case RDN: ++ s = "RDN"; ++ break; ++ case RUP: ++ s = "RUP"; ++ break; ++ case RMM: ++ s = "RMM"; ++ break; ++ case DYN: ++ s = "DYN"; ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str()); ++} ++ ++void Decoder::PrintMemoryOrder(Instruction* instr, bool is_pred) { ++ int memOrder = instr->MemoryOrder(is_pred); ++ std::string s; ++ if ((memOrder & PSI) == PSI) { ++ s += "i"; ++ } ++ if ((memOrder & PSO) == PSO) { ++ s += "o"; ++ } ++ if ((memOrder & PSR) == PSR) { ++ s += "r"; ++ } ++ if ((memOrder & PSW) == PSW) { ++ s += "w"; ++ } ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str()); ++} ++ ++// Printing of instruction name. ++void Decoder::PrintInstructionName(Instruction* instr) {} ++ ++// Handle all register based formatting in this function to reduce the ++// complexity of FormatOption. ++int Decoder::FormatRegister(Instruction* instr, const char* format) { ++ DCHECK_EQ(format[0], 'r'); ++ if (format[1] == 's') { // 'rs[12]: Rs register. ++ if (format[2] == '1') { ++ int reg = instr->Rs1Value(); ++ PrintRegister(reg); ++ return 3; ++ } else if (format[2] == '2') { ++ int reg = instr->Rs2Value(); ++ PrintRegister(reg); ++ return 3; ++ } ++ UNREACHABLE(); ++ } else if (format[1] == 'd') { // 'rd: rd register. ++ int reg = instr->RdValue(); ++ PrintRegister(reg); ++ return 2; ++ } ++ UNREACHABLE(); ++} ++ ++// Handle all FPUregister based formatting in this function to reduce the ++// complexity of FormatOption. ++int Decoder::FormatFPURegisterOrRoundMode(Instruction* instr, ++ const char* format) { ++ DCHECK_EQ(format[0], 'f'); ++ if (format[1] == 's') { // 'fs[1-3]: Rs register. ++ if (format[2] == '1') { ++ int reg = instr->Rs1Value(); ++ PrintFPURegister(reg); ++ return 3; ++ } else if (format[2] == '2') { ++ int reg = instr->Rs2Value(); ++ PrintFPURegister(reg); ++ return 3; ++ } else if (format[2] == '3') { ++ int reg = instr->Rs3Value(); ++ PrintFPURegister(reg); ++ return 3; ++ } ++ UNREACHABLE(); ++ } else if (format[1] == 'd') { // 'fd: fd register. ++ int reg = instr->RdValue(); ++ PrintFPURegister(reg); ++ return 2; ++ } else if (format[1] == 'r') { // 'frm ++ DCHECK(STRING_STARTS_WITH(format, "frm")); ++ PrintRoundingMode(instr); ++ return 3; ++ } ++ UNREACHABLE(); ++} ++ ++// FormatOption takes a formatting string and interprets it based on ++// the current instructions. The format string points to the first ++// character of the option string (the option escape has already been ++// consumed by the caller.) FormatOption returns the number of ++// characters that were consumed from the formatting string. ++int Decoder::FormatOption(Instruction* instr, const char* format) { ++ switch (format[0]) { ++ case 'c': { // `csr: CSR registers ++ if (format[1] == 's') { ++ if (format[2] == 'r') { ++ PrintCSRReg(instr); ++ return 3; ++ } ++ } ++ UNREACHABLE(); ++ } ++ case 'i': { // 'imm12, 'imm12x, 'imm20U, or 'imm20J: Immediates. ++ if (format[3] == '1') { ++ if (format[4] == '2') { ++ DCHECK(STRING_STARTS_WITH(format, "imm12")); ++ if (format[5] == 'x') { ++ PrintImm12X(instr); ++ return 6; ++ } ++ PrintImm12(instr); ++ return 5; ++ } ++ } else if (format[3] == '2' && format[4] == '0') { ++ DCHECK(STRING_STARTS_WITH(format, "imm20")); ++ switch (format[5]) { ++ case 'U': ++ DCHECK(STRING_STARTS_WITH(format, "imm20U")); ++ PrintImm20U(instr); ++ break; ++ case 'J': ++ DCHECK(STRING_STARTS_WITH(format, "imm20J")); ++ PrintImm20J(instr); ++ break; ++ } ++ return 6; ++ } ++ UNREACHABLE(); ++ } ++ case 'o': { // 'offB or 'offS: Offsets. ++ if (format[3] == 'B') { ++ DCHECK(STRING_STARTS_WITH(format, "offB")); ++ PrintBranchOffset(instr); ++ return 4; ++ } else if (format[3] == 'S') { ++ DCHECK(STRING_STARTS_WITH(format, "offS")); ++ PrintStoreOffset(instr); ++ return 4; ++ } ++ UNREACHABLE(); ++ } ++ case 'r': { // 'r: registers. ++ return FormatRegister(instr, format); ++ } ++ case 'f': { // 'f: FPUregisters or `frm ++ return FormatFPURegisterOrRoundMode(instr, format); ++ } ++ case 'a': { // 'a: Atomic acquire and release. ++ PrintAcquireRelease(instr); ++ return 1; ++ } ++ case 'p': { // `pre ++ DCHECK(STRING_STARTS_WITH(format, "pre")); ++ PrintMemoryOrder(instr, true); ++ return 3; ++ } ++ case 's': { // 's32 or 's64: Shift amount. ++ if (format[1] == '3') { ++ DCHECK(STRING_STARTS_WITH(format, "s32")); ++ PrintShamt32(instr); ++ return 3; ++ } else if (format[1] == '6') { ++ DCHECK(STRING_STARTS_WITH(format, "s64")); ++ PrintShamt(instr); ++ return 3; ++ } else if (format[1] == 'u') { ++ DCHECK(STRING_STARTS_WITH(format, "suc")); ++ PrintMemoryOrder(instr, false); ++ return 3; ++ } ++ UNREACHABLE(); ++ } ++ case 'v': { // 'vs1: Raw values from register fields ++ DCHECK(STRING_STARTS_WITH(format, "vs1")); ++ PrintVs1(instr); ++ return 3; ++ } ++ } ++ UNREACHABLE(); ++} ++ ++// Format takes a formatting string for a whole instruction and prints it into ++// the output buffer. All escaped options are handed to FormatOption to be ++// parsed further. ++void Decoder::Format(Instruction* instr, const char* format) { ++ char cur = *format++; ++ while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) { ++ if (cur == '\'') { // Single quote is used as the formatting escape. ++ format += FormatOption(instr, format); ++ } else { ++ out_buffer_[out_buffer_pos_++] = cur; ++ } ++ cur = *format++; ++ } ++ out_buffer_[out_buffer_pos_] = '\0'; ++} ++ ++// For currently unimplemented decodings the disassembler calls Unknown(instr) ++// which will just print "unknown" of the instruction bits. ++void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); } ++ ++// RISCV Instruction Decode Routine ++void Decoder::DecodeRType(Instruction* instr) { ++ switch (instr->InstructionBits() & kRTypeMask) { ++ case RO_ADD: ++ Format(instr, "add 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SUB: ++ if (instr->Rs1Value() == zero_reg.code()) ++ Format(instr, "neg 'rd, rs2"); ++ else ++ Format(instr, "sub 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SLL: ++ Format(instr, "sll 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SLT: ++ if (instr->Rs2Value() == zero_reg.code()) ++ Format(instr, "sltz 'rd, 'rs1"); ++ else if (instr->Rs1Value() == zero_reg.code()) ++ Format(instr, "sgtz 'rd, 'rs2"); ++ else ++ Format(instr, "slt 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SLTU: ++ if (instr->Rs1Value() == zero_reg.code()) ++ Format(instr, "snez 'rd, 'rs2"); ++ else ++ Format(instr, "sltu 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_XOR: ++ Format(instr, "xor 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SRL: ++ Format(instr, "srl 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SRA: ++ Format(instr, "sra 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_OR: ++ Format(instr, "or 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_AND: ++ Format(instr, "and 'rd, 'rs1, 'rs2"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_ADDW: ++ Format(instr, "addw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SUBW: ++ if (instr->Rs1Value() == zero_reg.code()) ++ Format(instr, "negw 'rd, 'rs2"); ++ else ++ Format(instr, "subw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SLLW: ++ Format(instr, "sllw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SRLW: ++ Format(instr, "srlw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_SRAW: ++ Format(instr, "sraw 'rd, 'rs1, 'rs2"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ // TODO: Add RISCV M extension macro ++ case RO_MUL: ++ Format(instr, "mul 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_MULH: ++ Format(instr, "mulh 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_MULHSU: ++ Format(instr, "mulhsu 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_MULHU: ++ Format(instr, "mulhu 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_DIV: ++ Format(instr, "div 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_DIVU: ++ Format(instr, "divu 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_REM: ++ Format(instr, "rem 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_REMU: ++ Format(instr, "remu 'rd, 'rs1, 'rs2"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_MULW: ++ Format(instr, "mulw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_DIVW: ++ Format(instr, "divw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_DIVUW: ++ Format(instr, "divuw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_REMW: ++ Format(instr, "remw 'rd, 'rs1, 'rs2"); ++ break; ++ case RO_REMUW: ++ Format(instr, "remuw 'rd, 'rs1, 'rs2"); ++ break; ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: End Add RISCV M extension macro ++ default: { ++ switch (instr->BaseOpcode()) { ++ case AMO: ++ DecodeRAType(instr); ++ break; ++ case OP_FP: ++ DecodeRFPType(instr); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ } ++ } ++} ++ ++void Decoder::DecodeRAType(Instruction* instr) { ++ // TODO: Add macro for RISCV A extension ++ // Special handling for A extension instructions because it uses func5 ++ // For all A extension instruction, V8 simulator is pure sequential. No ++ // Memory address lock or other synchronizaiton behaviors. ++ switch (instr->InstructionBits() & kRATypeMask) { ++ case RO_LR_W: ++ Format(instr, "lr.w'a 'rd, ('rs1)"); ++ break; ++ case RO_SC_W: ++ Format(instr, "sc.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOSWAP_W: ++ Format(instr, "amoswap.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOADD_W: ++ Format(instr, "amoadd.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOXOR_W: ++ Format(instr, "amoxor.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOAND_W: ++ Format(instr, "amoand.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOOR_W: ++ Format(instr, "amoor.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMIN_W: ++ Format(instr, "amomin.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMAX_W: ++ Format(instr, "amomax.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMINU_W: ++ Format(instr, "amominu.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMAXU_W: ++ Format(instr, "amomaxu.w'a 'rd, 'rs2, ('rs1)"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_LR_D: ++ Format(instr, "lr.d'a 'rd, ('rs1)"); ++ break; ++ case RO_SC_D: ++ Format(instr, "sc.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOSWAP_D: ++ Format(instr, "amoswap.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOADD_D: ++ Format(instr, "amoadd.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOXOR_D: ++ Format(instr, "amoxor.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOAND_D: ++ Format(instr, "amoand.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOOR_D: ++ Format(instr, "amoor.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMIN_D: ++ Format(instr, "amomin.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMAX_D: ++ Format(instr, "amoswap.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMINU_D: ++ Format(instr, "amominu.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++ case RO_AMOMAXU_D: ++ Format(instr, "amomaxu.d'a 'rd, 'rs2, ('rs1)"); ++ break; ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: End Add macro for RISCV A extension ++ default: { ++ UNSUPPORTED_RISCV(); ++ } ++ } ++} ++ ++void Decoder::DecodeRFPType(Instruction* instr) { ++ // OP_FP instructions (F/D) uses func7 first. Some further uses fun3 and rs2() ++ ++ // kRATypeMask is only for func7 ++ switch (instr->InstructionBits() & kRFPTypeMask) { ++ // TODO: Add macro for RISCV F extension ++ case RO_FADD_S: ++ Format(instr, "fadd.s 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FSUB_S: ++ Format(instr, "fsub.s 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FMUL_S: ++ Format(instr, "fmul.s 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FDIV_S: ++ Format(instr, "fdiv.s 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FSQRT_S: ++ Format(instr, "fsqrt.s 'fd, 'fs1"); ++ break; ++ case RO_FSGNJ_S: { // RO_FSGNJN_S RO_FSGNJX_S ++ switch (instr->Funct3Value()) { ++ case 0b000: // RO_FSGNJ_S ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fmv.s 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnj.s 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FSGNJN_S ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fneg.s 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnjn.s 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b010: // RO_FSGNJX_S ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fabs.s 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnjx.s 'fd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FMIN_S: { // RO_FMAX_S ++ switch (instr->Funct3Value()) { ++ case 0b000: // RO_FMIN_S ++ Format(instr, "fmin.s 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FMAX_S ++ Format(instr, "fmax.s 'fd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FCVT_W_S: { // RO_FCVT_WU_S , 64F RO_FCVT_L_S RO_FCVT_LU_S ++ switch (instr->Rs2Value()) { ++ case 0b00000: // RO_FCVT_W_S ++ Format(instr, "fcvt.w.s ['frm] 'rd, 'fs1"); ++ break; ++ case 0b00001: // RO_FCVT_WU_S ++ Format(instr, "fcvt.wu.s ['frm] 'rd, 'fs1"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: // RO_FCVT_L_S ++ Format(instr, "fcvt.l.s ['frm] 'rd, 'fs1"); ++ break; ++ case 0b00011: // RO_FCVT_LU_S ++ Format(instr, "fcvt.lu.s ['frm] 'rd, 'fs1"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FMV: { // RO_FCLASS_S ++ if (instr->Rs2Value() != 0b00000) { ++ UNSUPPORTED_RISCV(); ++ } ++ switch (instr->Funct3Value()) { ++ case 0b000: // RO_FMV_X_W ++ Format(instr, "fmv.x.w 'rd, 'fs1"); ++ break; ++ case 0b001: // RO_FCLASS_S ++ Format(instr, "fclass.s 'rd, 'fs1"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FLE_S: { // RO_FEQ_S RO_FLT_S RO_FLE_S ++ switch (instr->Funct3Value()) { ++ case 0b010: // RO_FEQ_S ++ Format(instr, "feq.s 'rd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FLT_S ++ Format(instr, "flt.s 'rd, 'fs1, 'fs2"); ++ break; ++ case 0b000: // RO_FLE_S ++ Format(instr, "fle.s 'rd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FCVT_S_W: { // RO_FCVT_S_WU , 64F RO_FCVT_S_L RO_FCVT_S_LU ++ switch (instr->Rs2Value()) { ++ case 0b00000: // RO_FCVT_S_W ++ Format(instr, "fcvt.s.w 'fd, 'rs1"); ++ break; ++ case 0b00001: // RO_FCVT_S_WU ++ Format(instr, "fcvt.s.wu 'fd, 'rs1"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: // RO_FCVT_S_L ++ Format(instr, "fcvt.s.l 'fd, 'rs1"); ++ break; ++ case 0b00011: // RO_FCVT_S_LU ++ Format(instr, "fcvt.s.lu 'fd, 'rs1"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED_RISCV(); ++ } ++ } ++ break; ++ } ++ case RO_FMV_W_X: { ++ if (instr->Funct3Value() == 0b000) { ++ Format(instr, "fmv.w.x 'fd, 'rs1"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ // TODO: Add macro for RISCV D extension ++ case RO_FADD_D: ++ Format(instr, "fadd.d 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FSUB_D: ++ Format(instr, "fsub.d 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FMUL_D: ++ Format(instr, "fmul.d 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FDIV_D: ++ Format(instr, "fdiv.d 'fd, 'fs1, 'fs2"); ++ break; ++ case RO_FSQRT_D: { ++ if (instr->Rs2Value() == 0b00000) { ++ Format(instr, "fsqrt.d 'fd, 'fs1"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FSGNJ_D: { // RO_FSGNJN_D RO_FSGNJX_D ++ switch (instr->Funct3Value()) { ++ case 0b000: // RO_FSGNJ_D ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fmv.d 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnj.d 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FSGNJN_D ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fneg.d 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnjn.d 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b010: // RO_FSGNJX_D ++ if (instr->Rs1Value() == instr->Rs2Value()) ++ Format(instr, "fabs.d 'fd, 'fs1"); ++ else ++ Format(instr, "fsgnjx.d 'fd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FMIN_D: { // RO_FMAX_D ++ switch (instr->Funct3Value()) { ++ case 0b000: // RO_FMIN_D ++ Format(instr, "fmin.d 'fd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FMAX_D ++ Format(instr, "fmax.d 'fd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case (RO_FCVT_S_D & kRFPTypeMask): { ++ if (instr->Rs2Value() == 0b00001) { ++ Format(instr, "fcvt.s.d ['frm] 'fd, 'rs1"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FCVT_D_S: { ++ if (instr->Rs2Value() == 0b00000) { ++ Format(instr, "fcvt.d.s 'fd, 'fs1"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FLE_D: { // RO_FEQ_D RO_FLT_D RO_FLE_D ++ switch (instr->Funct3Value()) { ++ case 0b010: // RO_FEQ_S ++ Format(instr, "feq.d 'rd, 'fs1, 'fs2"); ++ break; ++ case 0b001: // RO_FLT_D ++ Format(instr, "flt.d 'rd, 'fs1, 'fs2"); ++ break; ++ case 0b000: // RO_FLE_D ++ Format(instr, "fle.d 'rd, 'fs1, 'fs2"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case (RO_FCLASS_D & kRFPTypeMask): { // RO_FCLASS_D , 64D RO_FMV_X_D ++ if (instr->Rs2Value() != 0b00000) { ++ UNSUPPORTED_RISCV(); ++ break; ++ } ++ switch (instr->Funct3Value()) { ++ case 0b001: // RO_FCLASS_D ++ Format(instr, "fclass.d 'rd, 'fs1"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b000: // RO_FMV_X_D ++ Format(instr, "fmv.x.d 'rd, 'fs1"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FCVT_W_D: { // RO_FCVT_WU_D , 64F RO_FCVT_L_D RO_FCVT_LU_D ++ switch (instr->Rs2Value()) { ++ case 0b00000: // RO_FCVT_W_D ++ Format(instr, "fcvt.w.d ['frm] 'rd, 'fs1"); ++ break; ++ case 0b00001: // RO_FCVT_WU_D ++ Format(instr, "fcvt.wu.d ['frm] 'rd, 'fs1"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: // RO_FCVT_L_D ++ Format(instr, "fcvt.l.d ['frm] 'rd, 'fs1"); ++ break; ++ case 0b00011: // RO_FCVT_LU_D ++ Format(instr, "fcvt.lu.d ['frm] 'rd, 'fs1"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ case RO_FCVT_D_W: { // RO_FCVT_D_WU , 64F RO_FCVT_D_L RO_FCVT_D_LU ++ switch (instr->Rs2Value()) { ++ case 0b00000: // RO_FCVT_D_W ++ Format(instr, "fcvt.d.w 'fd, 'rs1"); ++ break; ++ case 0b00001: // RO_FCVT_D_WU ++ Format(instr, "fcvt.d.wu 'fd, 'rs1"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: // RO_FCVT_D_L ++ Format(instr, "fcvt.d.l 'fd, 'rs1"); ++ break; ++ case 0b00011: // RO_FCVT_D_LU ++ Format(instr, "fcvt.d.lu 'fd, 'rs1"); ++ break; ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_FMV_D_X: { ++ if (instr->Funct3Value() == 0b000 && instr->Rs2Value() == 0b00000) { ++ Format(instr, "fmv.d.x 'fd, 'rs1"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED_RISCV(); ++ } ++ } ++} ++ ++void Decoder::DecodeR4Type(Instruction* instr) { ++ switch (instr->InstructionBits() & kR4TypeMask) { ++ // TODO: use F Extension macro block ++ case RO_FMADD_S: ++ Format(instr, "fmadd.s 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FMSUB_S: ++ Format(instr, "fmsub.s 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FNMSUB_S: ++ Format(instr, "fnmsub.s 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FNMADD_S: ++ Format(instr, "fnmadd.s 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ // TODO: use F Extension macro block ++ case RO_FMADD_D: ++ Format(instr, "fmadd.d 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FMSUB_D: ++ Format(instr, "fmsub.d 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FNMSUB_D: ++ Format(instr, "fnmsub.d 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ case RO_FNMADD_D: ++ Format(instr, "fnmadd.d 'fd, 'fs1, 'fs2, 'fs3"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++ ++void Decoder::DecodeIType(Instruction* instr) { ++ switch (instr->InstructionBits() & kITypeMask) { ++ case RO_JALR: ++ if (instr->RdValue() == zero_reg.code() && ++ instr->Rs1Value() == ra.code() && instr->Imm12Value() == 0) ++ Format(instr, "ret"); ++ else if (instr->RdValue() == zero_reg.code() && instr->Imm12Value() == 0) ++ Format(instr, "jr 'rs1"); ++ else if (instr->RdValue() == ra.code() && instr->Imm12Value() == 0) ++ Format(instr, "jalr 'rs1"); ++ else ++ Format(instr, "jalr 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LB: ++ Format(instr, "lb 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LH: ++ Format(instr, "lh 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LW: ++ Format(instr, "lw 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LBU: ++ Format(instr, "lbu 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LHU: ++ Format(instr, "lhu 'rd, 'imm12('rs1)"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_LWU: ++ Format(instr, "lwu 'rd, 'imm12('rs1)"); ++ break; ++ case RO_LD: ++ Format(instr, "ld 'rd, 'imm12('rs1)"); ++ break; ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ case RO_ADDI: ++ if (instr->Imm12Value() == 0) { ++ if (instr->RdValue() == zero_reg.code() && ++ instr->Rs1Value() == zero_reg.code()) ++ Format(instr, "nop"); ++ else ++ Format(instr, "mv 'rd, 'rs1"); ++ } else if (instr->Rs1Value() == zero_reg.code()) { ++ Format(instr, "li 'rd, 'imm12"); ++ } else { ++ Format(instr, "addi 'rd, 'rs1, 'imm12"); ++ } ++ break; ++ case RO_SLTI: ++ Format(instr, "slti 'rd, 'rs1, 'imm12"); ++ break; ++ case RO_SLTIU: ++ if (instr->Imm12Value() == 1) ++ Format(instr, "seqz 'rd, 'rs1"); ++ else ++ Format(instr, "sltiu 'rd, 'rs1, 'imm12"); ++ break; ++ case RO_XORI: ++ if (instr->Imm12Value() == -1) ++ Format(instr, "not 'rd, 'rs1"); ++ else ++ Format(instr, "xori 'rd, 'rs1, 'imm12x"); ++ break; ++ case RO_ORI: ++ Format(instr, "ori 'rd, 'rs1, 'imm12x"); ++ break; ++ case RO_ANDI: ++ Format(instr, "andi 'rd, 'rs1, 'imm12x"); ++ break; ++ case RO_SLLI: ++ Format(instr, "slli 'rd, 'rs1, 's64"); ++ break; ++ case RO_SRLI: { // RO_SRAI ++ if (!instr->IsArithShift()) { ++ Format(instr, "srli 'rd, 'rs1, 's64"); ++ } else { ++ Format(instr, "srai 'rd, 'rs1, 's64"); ++ } ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_ADDIW: ++ if (instr->Imm12Value() == 0) ++ Format(instr, "sext.w 'rd, 'rs1"); ++ else ++ Format(instr, "addiw 'rd, 'rs1, 'imm12"); ++ break; ++ case RO_SLLIW: ++ Format(instr, "slliw 'rd, 'rs1, 's32"); ++ break; ++ case RO_SRLIW: { // RO_SRAIW ++ if (!instr->IsArithShift()) { ++ Format(instr, "srliw 'rd, 'rs1, 's32"); ++ } else { ++ Format(instr, "sraiw 'rd, 'rs1, 's32"); ++ } ++ break; ++ } ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ case RO_FENCE: ++ if (instr->MemoryOrder(true) == PSIORW && ++ instr->MemoryOrder(false) == PSIORW) ++ Format(instr, "fence"); ++ else ++ Format(instr, "fence 'pre, 'suc"); ++ break; ++ case RO_ECALL: { // RO_EBREAK ++ if (instr->Imm12Value() == 0) { // ECALL ++ Format(instr, "ecall"); ++ } else if (instr->Imm12Value() == 1) { // EBREAK ++ Format(instr, "ebreak"); ++ } else { ++ UNSUPPORTED_RISCV(); ++ } ++ break; ++ } ++ // TODO: use Zifencei Standard Extension macro block ++ case RO_FENCE_I: ++ Format(instr, "fence.i"); ++ break; ++ // TODO: use Zicsr Standard Extension macro block ++ // FIXME(RISC-V): Add special formatting for CSR registers ++ case RO_CSRRW: ++ if (instr->CsrValue() == csr_fcsr) { ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "fscsr 'rs1"); ++ else ++ Format(instr, "fscsr 'rd, 'rs1"); ++ } else if (instr->CsrValue() == csr_frm) { ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "fsrm 'rs1"); ++ else ++ Format(instr, "fsrm 'rd, 'rs1"); ++ } else if (instr->CsrValue() == csr_fflags) { ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "fsflags 'rs1"); ++ else ++ Format(instr, "fsflags 'rd, 'rs1"); ++ } else if (instr->RdValue() == zero_reg.code()) { ++ Format(instr, "csrw 'csr, 'rs1"); ++ } else { ++ Format(instr, "csrrw 'rd, 'csr, 'rs1"); ++ } ++ break; ++ case RO_CSRRS: ++ if (instr->Rs1Value() == zero_reg.code()) { ++ switch (instr->CsrValue()) { ++ case csr_instret: ++ Format(instr, "rdinstret 'rd"); ++ break; ++ case csr_instreth: ++ Format(instr, "rdinstreth 'rd"); ++ break; ++ case csr_time: ++ Format(instr, "rdtime 'rd"); ++ break; ++ case csr_timeh: ++ Format(instr, "rdtimeh 'rd"); ++ break; ++ case csr_cycle: ++ Format(instr, "rdcycle 'rd"); ++ break; ++ case csr_cycleh: ++ Format(instr, "rdcycleh 'rd"); ++ break; ++ case csr_fflags: ++ Format(instr, "frflags 'rd"); ++ break; ++ case csr_frm: ++ Format(instr, "frrm 'rd"); ++ break; ++ case csr_fcsr: ++ Format(instr, "frcsr 'rd"); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } else if (instr->Rs1Value() == zero_reg.code()) { ++ Format(instr, "csrr 'rd, 'csr"); ++ } else if (instr->RdValue() == zero_reg.code()) { ++ Format(instr, "csrs 'csr, 'rs1"); ++ } else ++ Format(instr, "csrrs 'rd, 'csr, 'rs1"); ++ break; ++ case RO_CSRRC: ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "csrc 'csr, 'rs1"); ++ else ++ Format(instr, "csrrc 'rd, 'csr, 'rs1"); ++ break; ++ case RO_CSRRWI: ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "csrwi 'csr, 'vs1"); ++ else ++ Format(instr, "csrrwi 'rd, 'csr, 'vs1"); ++ break; ++ case RO_CSRRSI: ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "csrsi 'csr, 'vs1"); ++ else ++ Format(instr, "csrrsi 'rd, 'csr, 'vs1"); ++ break; ++ case RO_CSRRCI: ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "csrci 'csr, 'vs1"); ++ else ++ Format(instr, "csrrci 'rd, 'csr, 'vs1"); ++ break; ++ // TODO: use F Extension macro block ++ case RO_FLW: ++ Format(instr, "flw 'fd, 'imm12('rs1)"); ++ break; ++ // TODO: use D Extension macro block ++ case RO_FLD: ++ Format(instr, "fld 'fd, 'imm12('rs1)"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++ ++void Decoder::DecodeSType(Instruction* instr) { ++ switch (instr->InstructionBits() & kSTypeMask) { ++ case RO_SB: ++ Format(instr, "sb 'rs2, 'offS('rs1)"); ++ break; ++ case RO_SH: ++ Format(instr, "sh 'rs2, 'offS('rs1)"); ++ break; ++ case RO_SW: ++ Format(instr, "sw 'rs2, 'offS('rs1)"); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_SD: ++ Format(instr, "sd 'rs2, 'offS('rs1)"); ++ break; ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: use F Extension macro block ++ case RO_FSW: ++ Format(instr, "fsw 'fs2, 'offS('rs1)"); ++ break; ++ // TODO: use D Extension macro block ++ case RO_FSD: ++ Format(instr, "fsd 'fs2, 'offS('rs1)"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++ ++void Decoder::DecodeBType(Instruction* instr) { ++ switch (instr->InstructionBits() & kBTypeMask) { ++ case RO_BEQ: ++ Format(instr, "beq 'rs1, 'rs2, 'offB"); ++ break; ++ case RO_BNE: ++ Format(instr, "bne 'rs1, 'rs2, 'offB"); ++ break; ++ case RO_BLT: ++ Format(instr, "blt 'rs1, 'rs2, 'offB"); ++ break; ++ case RO_BGE: ++ Format(instr, "bge 'rs1, 'rs2, 'offB"); ++ break; ++ case RO_BLTU: ++ Format(instr, "bltu 'rs1, 'rs2, 'offB"); ++ break; ++ case RO_BGEU: ++ Format(instr, "bgeu 'rs1, 'rs2, 'offB"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++void Decoder::DecodeUType(Instruction* instr) { ++ // U Type doesn't have additional mask ++ switch (instr->BaseOpcodeFieldRaw()) { ++ case RO_LUI: ++ Format(instr, "lui 'rd, 'imm20U"); ++ break; ++ case RO_AUIPC: ++ Format(instr, "auipc 'rd, 'imm20U"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++void Decoder::DecodeJType(Instruction* instr) { ++ // J Type doesn't have additional mask ++ switch (instr->BaseOpcodeValue()) { ++ case RO_JAL: ++ if (instr->RdValue() == zero_reg.code()) ++ Format(instr, "j 'imm20J"); ++ else if (instr->RdValue() == ra.code()) ++ Format(instr, "jal 'imm20J"); ++ else ++ Format(instr, "jal 'rd, 'imm20J"); ++ break; ++ default: ++ UNSUPPORTED_RISCV(); ++ } ++} ++ ++// Disassemble the instruction at *instr_ptr into the output buffer. ++// All instructions are one word long, except for the simulator ++// pseudo-instruction stop(msg). For that one special case, we return ++// size larger than one kInstrSize. ++int Decoder::InstructionDecode(byte* instr_ptr) { ++ Instruction* instr = Instruction::At(instr_ptr); ++ // Print raw instruction bytes. ++ out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%08x ", ++ instr->InstructionBits()); ++ switch (instr->InstructionType()) { ++ case Instruction::kRType: ++ DecodeRType(instr); ++ break; ++ case Instruction::kR4Type: ++ DecodeR4Type(instr); ++ break; ++ case Instruction::kIType: ++ DecodeIType(instr); ++ break; ++ case Instruction::kSType: ++ DecodeSType(instr); ++ break; ++ case Instruction::kBType: ++ DecodeBType(instr); ++ break; ++ case Instruction::kUType: ++ DecodeUType(instr); ++ break; ++ case Instruction::kJType: ++ DecodeJType(instr); ++ break; ++ default: ++ Format(instr, "UNSUPPORTED"); ++ UNSUPPORTED_RISCV(); ++ } ++ return kInstrSize; ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++//------------------------------------------------------------------------------ ++ ++namespace disasm { ++ ++const char* NameConverter::NameOfAddress(byte* addr) const { ++ v8::internal::SNPrintF(tmp_buffer_, "%p", static_cast(addr)); ++ return tmp_buffer_.begin(); ++} ++ ++const char* NameConverter::NameOfConstant(byte* addr) const { ++ return NameOfAddress(addr); ++} ++ ++const char* NameConverter::NameOfCPURegister(int reg) const { ++ return v8::internal::Registers::Name(reg); ++} ++ ++const char* NameConverter::NameOfXMMRegister(int reg) const { ++ return v8::internal::FPURegisters::Name(reg); ++} ++ ++const char* NameConverter::NameOfByteCPURegister(int reg) const { ++ UNREACHABLE(); // RISC-V does not have the concept of a byte register. ++ return "nobytereg"; ++} ++ ++const char* NameConverter::NameInCode(byte* addr) const { ++ // The default name converter is called for unknown code. So we will not try ++ // to access any memory. ++ return ""; ++} ++ ++//------------------------------------------------------------------------------ ++ ++int Disassembler::InstructionDecode(v8::internal::Vector buffer, ++ byte* instruction) { ++ v8::internal::Decoder d(converter_, buffer); ++ return d.InstructionDecode(instruction); ++} ++ ++// The RISC-V assembler does not currently use constant pools. ++int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; } ++ ++void Disassembler::Disassemble(FILE* f, byte* begin, byte* end, ++ UnimplementedOpcodeAction unimplemented_action) { ++ NameConverter converter; ++ Disassembler d(converter, unimplemented_action); ++ for (byte* pc = begin; pc < end;) { ++ v8::internal::EmbeddedVector buffer; ++ buffer[0] = '\0'; ++ byte* prev_pc = pc; ++ pc += d.InstructionDecode(buffer, pc); ++ v8::internal::PrintF(f, "%p %08x %s\n", static_cast(prev_pc), ++ *reinterpret_cast(prev_pc), buffer.begin()); ++ } ++} ++ ++#undef STRING_STARTS_WITH ++ ++} // namespace disasm ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/frame-constants.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/execution/frame-constants.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/frame-constants.h +@@ -356,6 +356,10 @@ inline static int FrameSlotToFPOffset(in + #include "src/execution/mips64/frame-constants-mips64.h" // NOLINT + #elif V8_TARGET_ARCH_S390 + #include "src/execution/s390/frame-constants-s390.h" // NOLINT ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/execution/riscv64/frame-constants-riscv64.h" // NOLINT ++#elif V8_TARGET_ARCH_RISCV ++#include "src/execution/riscv/frame-constants-riscv.h" // NOLINT + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/frame-constants-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/frame-constants-riscv64.cc +@@ -0,0 +1,32 @@ ++// Copyright 2011 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/codegen/riscv64/assembler-riscv64-inl.h" ++#include "src/execution/frame-constants.h" ++#include "src/execution/frames.h" ++ ++#include "src/execution/riscv64/frame-constants-riscv64.h" ++ ++namespace v8 { ++namespace internal { ++ ++Register JavaScriptFrame::fp_register() { return v8::internal::fp; } ++Register JavaScriptFrame::context_register() { return cp; } ++Register JavaScriptFrame::constant_pool_pointer_register() { UNREACHABLE(); } ++ ++int InterpreterFrameConstants::RegisterStackSlotCount(int register_count) { ++ return register_count; ++} ++ ++int BuiltinContinuationFrameConstants::PaddingSlotCount(int register_count) { ++ USE(register_count); ++ return 0; ++} ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/frame-constants-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/frame-constants-riscv64.h +@@ -0,0 +1,87 @@ ++// Copyright 2011 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_EXECUTION_RISCV_FRAME_CONSTANTS_RISCV_H_ ++#define V8_EXECUTION_RISCV_FRAME_CONSTANTS_RISCV_H_ ++ ++#include "src/base/bits.h" ++#include "src/base/macros.h" ++#include "src/execution/frame-constants.h" ++#include "src/wasm/baseline/liftoff-assembler-defs.h" ++#include "src/wasm/wasm-linkage.h" ++ ++namespace v8 { ++namespace internal { ++ ++class EntryFrameConstants : public AllStatic { ++ public: ++ // This is the offset to where JSEntry pushes the current value of ++ // Isolate::c_entry_fp onto the stack. ++ static constexpr int kCallerFPOffset = ++ -(StandardFrameConstants::kFixedFrameSizeFromFp + kPointerSize); ++}; ++ ++class WasmCompileLazyFrameConstants : public TypedFrameConstants { ++ public: ++ static constexpr int kNumberOfSavedGpParamRegs = ++ arraysize(wasm::kGpParamRegisters); ++ static constexpr int kNumberOfSavedFpParamRegs = ++ arraysize(wasm::kFpParamRegisters); ++ ++ // FP-relative. ++ // Builtins::Generate_WasmCompileLazy pushes WasmInstance to the stack after ++ // pushing SavedGPParamRegs and SavedFpParamRegs onto the stack, therefore ++ // kWasmInstanceOffset is setup as such ++ static constexpr int kWasmInstanceOffset = TYPED_FRAME_PUSHED_VALUE_OFFSET( ++ kNumberOfSavedGpParamRegs + kNumberOfSavedGpParamRegs); ++ static constexpr int kFixedFrameSizeFromFp = ++ TypedFrameConstants::kFixedFrameSizeFromFp + ++ kNumberOfSavedGpParamRegs * kPointerSize + ++ kNumberOfSavedFpParamRegs * kDoubleSize; ++}; ++ ++// Frame constructed by the {WasmDebugBreak} builtin. ++// After pushing the frame type marker, the builtin pushes all Liftoff cache ++// registers (see liftoff-assembler-defs.h). ++class WasmDebugBreakFrameConstants : public TypedFrameConstants { ++ public: ++ // constexpr RegList kLiftoffAssemblerGpCacheRegs = ++ // Register::ListOf(a0, a1, a2, a3, a4, a5, a6, a7, t0, t1, t2, s7); ++ static constexpr uint32_t kPushedGpRegs = wasm::kLiftoffAssemblerGpCacheRegs; ++ ++ // constexpr RegList kLiftoffAssemblerFpCacheRegs = DoubleRegister::ListOf( ++ // ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7, fa0, fa1, fa2, fa3, fa4, fa5, ++ // fa6, fa7, ft8, ft9, ft10, ft11); ++ static constexpr uint32_t kPushedFpRegs = wasm::kLiftoffAssemblerFpCacheRegs; ++ ++ static constexpr int kNumPushedGpRegisters = ++ base::bits::CountPopulation(kPushedGpRegs); ++ static constexpr int kNumPushedFpRegisters = ++ base::bits::CountPopulation(kPushedFpRegs); ++ ++ static constexpr int kLastPushedGpRegisterOffset = ++ -kFixedFrameSizeFromFp - kNumPushedGpRegisters * kSystemPointerSize; ++ static constexpr int kLastPushedFpRegisterOffset = ++ kLastPushedGpRegisterOffset - kNumPushedFpRegisters * kDoubleSize; ++ ++ // Offsets are fp-relative. ++ static int GetPushedGpRegisterOffset(int reg_code) { ++ DCHECK_NE(0, kPushedGpRegs & (1 << reg_code)); ++ uint32_t lower_regs = kPushedGpRegs & ((uint32_t{1} << reg_code) - 1); ++ return kLastPushedGpRegisterOffset + ++ base::bits::CountPopulation(lower_regs) * kSystemPointerSize; ++ } ++ ++ static int GetPushedFpRegisterOffset(int reg_code) { ++ DCHECK_NE(0, kPushedFpRegs & (1 << reg_code)); ++ uint32_t lower_regs = kPushedFpRegs & ((uint32_t{1} << reg_code) - 1); ++ return kLastPushedFpRegisterOffset + ++ base::bits::CountPopulation(lower_regs) * kDoubleSize; ++ } ++}; ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_EXECUTION_RISCV_FRAME_CONSTANTS_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/simulator-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/simulator-riscv64.cc +@@ -0,0 +1,3509 @@ ++// Copyright 2020 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++// Copyright(c) 2010 - 2017, ++// The Regents of the University of California(Regents).All Rights Reserved. ++// ++// Redistribution and use in source and binary forms, ++// with or without modification, ++// are permitted provided that the following ++// conditions are met : 1. Redistributions of source code must retain the ++// above copyright notice, this list of conditions and the following ++// disclaimer.2. Redistributions in binary form must reproduce the above ++// copyright notice, this list of conditions and the following disclaimer in ++// the ++// documentation and / ++// or ++// other materials provided with the distribution.3. Neither the name of ++// the Regents nor the names of its contributors may be used to endorse ++// or ++// promote products derived from ++// this software without specific prior written permission. ++// ++// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, ++// INDIRECT, SPECIAL, ++// INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ++// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, ++// EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++// ++// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, ++// INCLUDING, BUT NOT LIMITED TO, ++// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++// PARTICULAR PURPOSE.THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, ++// IF ANY, ++// PROVIDED HEREUNDER IS PROVIDED ++// "AS IS".REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, ++// SUPPORT, UPDATES, ENHANCEMENTS, ++// OR MODIFICATIONS. ++ ++// The original source code covered by the above license above has been ++// modified significantly by the v8 project authors. ++ ++#include "src/execution/riscv64/simulator-riscv64.h" ++ ++// Only build the simulator if not compiling for real RISCV hardware. ++#if defined(USE_SIMULATOR) ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "src/base/bits.h" ++#include "src/codegen/assembler-inl.h" ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/diagnostics/disasm.h" ++#include "src/heap/combined-heap.h" ++#include "src/runtime/runtime-utils.h" ++#include "src/utils/ostreams.h" ++#include "src/utils/vector.h" ++ ++namespace v8 { ++namespace internal { ++ ++DEFINE_LAZY_LEAKY_OBJECT_GETTER(Simulator::GlobalMonitor, ++ Simulator::GlobalMonitor::Get) ++ ++// Util functions. ++inline bool HaveSameSign(int64_t a, int64_t b) { return ((a ^ b) >= 0); } ++ ++uint32_t get_fcsr_condition_bit(uint32_t cc) { ++ if (cc == 0) { ++ return 23; ++ } else { ++ return 24 + cc; ++ } ++} ++ ++// Generated by Assembler::break_()/stop(), ebreak code is passed as immediate ++// field of a subsequent LUI instruction; otherwise returns -1 ++static inline int32_t get_ebreak_code(Instruction* instr) { ++ DCHECK(instr->InstructionBits() == kBreakInstr); ++ byte* cur = reinterpret_cast(instr); ++ Instruction* next_instr = reinterpret_cast(cur + kInstrSize); ++ if (next_instr->BaseOpcodeFieldRaw() == RO_LUI) ++ return (next_instr->Imm20UValue()); ++ else ++ return -1; ++} ++ ++// This macro provides a platform independent use of sscanf. The reason for ++// SScanF not being implemented in a platform independent was through ++// ::v8::internal::OS in the same way as SNPrintF is that the Windows C Run-Time ++// Library does not provide vsscanf. ++#define SScanF sscanf // NOLINT ++ ++// The RiscvDebugger class is used by the simulator while debugging simulated ++// code. ++class RiscvDebugger { ++ public: ++ explicit RiscvDebugger(Simulator* sim) : sim_(sim) {} ++ ++ void Debug(); ++ // Print all registers with a nice formatting. ++ void PrintRegs(char name_prefix, int start_index, int end_index); ++ void PrintAllRegs(); ++ void PrintAllRegsIncludingFPU(); ++ ++ static const Instr kNopInstr = 0x0; ++ ++ private: ++ Simulator* sim_; ++ ++ int64_t GetRegisterValue(int regnum); ++ int64_t GetFPURegisterValue(int regnum); ++ float GetFPURegisterValueFloat(int regnum); ++ double GetFPURegisterValueDouble(int regnum); ++ bool GetValue(const char* desc, int64_t* value); ++}; ++ ++inline void UNSUPPORTED() { ++ printf("Sim: Unsupported instruction.\n"); ++ base::OS::Abort(); ++} ++ ++int64_t RiscvDebugger::GetRegisterValue(int regnum) { ++ if (regnum == kNumSimuRegisters) { ++ return sim_->get_pc(); ++ } else { ++ return sim_->get_register(regnum); ++ } ++} ++ ++int64_t RiscvDebugger::GetFPURegisterValue(int regnum) { ++ if (regnum == kNumFPURegisters) { ++ return sim_->get_pc(); ++ } else { ++ return sim_->get_fpu_register(regnum); ++ } ++} ++ ++float RiscvDebugger::GetFPURegisterValueFloat(int regnum) { ++ if (regnum == kNumFPURegisters) { ++ return sim_->get_pc(); ++ } else { ++ return sim_->get_fpu_register_float(regnum); ++ } ++} ++ ++double RiscvDebugger::GetFPURegisterValueDouble(int regnum) { ++ if (regnum == kNumFPURegisters) { ++ return sim_->get_pc(); ++ } else { ++ return sim_->get_fpu_register_double(regnum); ++ } ++} ++ ++bool RiscvDebugger::GetValue(const char* desc, int64_t* value) { ++ int regnum = Registers::Number(desc); ++ int fpuregnum = FPURegisters::Number(desc); ++ ++ if (regnum != kInvalidRegister) { ++ *value = GetRegisterValue(regnum); ++ return true; ++ } else if (fpuregnum != kInvalidFPURegister) { ++ *value = GetFPURegisterValue(fpuregnum); ++ return true; ++ } else if (strncmp(desc, "0x", 2) == 0) { ++ return SScanF(desc + 2, "%" SCNx64, reinterpret_cast(value)) == ++ 1; ++ } else { ++ return SScanF(desc, "%" SCNu64, reinterpret_cast(value)) == 1; ++ } ++ return false; ++} ++ ++#define REG_INFO(name) \ ++ name, GetRegisterValue(Registers::Number(name)), \ ++ GetRegisterValue(Registers::Number(name)) ++ ++void RiscvDebugger::PrintRegs(char name_prefix, int start_index, ++ int end_index) { ++ EmbeddedVector name1, name2; ++ DCHECK(name_prefix == 'a' || name_prefix == 't' || name_prefix == 's'); ++ DCHECK(start_index >= 0 && end_index <= 99); ++ int num_registers = (end_index - start_index) + 1; ++ for (int i = 0; i < num_registers / 2; i++) { ++ SNPrintF(name1, "%c%d", name_prefix, start_index + 2 * i); ++ SNPrintF(name2, "%c%d", name_prefix, start_index + 2 * i + 1); ++ PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \t%3s: 0x%016" PRIx64 ++ " %14" PRId64 " \n", ++ REG_INFO(name1.begin()), REG_INFO(name2.begin())); ++ } ++ if (num_registers % 2 == 1) { ++ SNPrintF(name1, "%c%d", name_prefix, end_index); ++ PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 " \n", REG_INFO(name1.begin())); ++ } ++} ++ ++void RiscvDebugger::PrintAllRegs() { ++ PrintF("\n"); ++ // ra, sp, gp ++ PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64 ++ "\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n", ++ REG_INFO("ra"), REG_INFO("sp"), REG_INFO("gp")); ++ ++ // tp, fp, pc ++ PrintF("%3s: 0x%016" PRIx64 " %14" PRId64 "\t%3s: 0x%016" PRIx64 " %14" PRId64 ++ "\t%3s: 0x%016" PRIx64 " %14" PRId64 "\n", ++ REG_INFO("tp"), REG_INFO("fp"), REG_INFO("pc")); ++ ++ // print register a0, .., a7 ++ PrintRegs('a', 0, 7); ++ // print registers s1, ..., s11 ++ PrintRegs('s', 1, 11); ++ // print registers t0, ..., t6 ++ PrintRegs('t', 0, 6); ++} ++ ++#undef REG_INFO ++ ++void RiscvDebugger::PrintAllRegsIncludingFPU() { ++#define FPU_REG_INFO(n) \ ++ FPURegisters::Name(n), GetFPURegisterValue(n), GetFPURegisterValueDouble(n) ++ ++ PrintAllRegs(); ++ ++ PrintF("\n\n"); ++ // f0, f1, f2, ... f31. ++ DCHECK(kNumFPURegisters % 2 == 0); ++ for (int i = 0; i < kNumFPURegisters; i += 2) ++ PrintF("%3s: 0x%016" PRIx64 " %16.4e \t%3s: 0x%016" PRIx64 " %16.4e\n", ++ FPU_REG_INFO(i), FPU_REG_INFO(i + 1)); ++#undef FPU_REG_INFO ++} ++ ++void RiscvDebugger::Debug() { ++ intptr_t last_pc = -1; ++ bool done = false; ++ ++#define COMMAND_SIZE 63 ++#define ARG_SIZE 255 ++ ++#define STR(a) #a ++#define XSTR(a) STR(a) ++ ++ char cmd[COMMAND_SIZE + 1]; ++ char arg1[ARG_SIZE + 1]; ++ char arg2[ARG_SIZE + 1]; ++ char* argv[3] = {cmd, arg1, arg2}; ++ ++ // Make sure to have a proper terminating character if reaching the limit. ++ cmd[COMMAND_SIZE] = 0; ++ arg1[ARG_SIZE] = 0; ++ arg2[ARG_SIZE] = 0; ++ ++ while (!done && (sim_->get_pc() != Simulator::end_sim_pc)) { ++ if (last_pc != sim_->get_pc()) { ++ disasm::NameConverter converter; ++ disasm::Disassembler dasm(converter); ++ // Use a reasonably large buffer. ++ v8::internal::EmbeddedVector buffer; ++ dasm.InstructionDecode(buffer, reinterpret_cast(sim_->get_pc())); ++ PrintF(" 0x%016" PRIx64 " %s\n", sim_->get_pc(), buffer.begin()); ++ last_pc = sim_->get_pc(); ++ } ++ char* line = ReadLine("sim> "); ++ if (line == nullptr) { ++ break; ++ } else { ++ char* last_input = sim_->last_debugger_input(); ++ if (strcmp(line, "\n") == 0 && last_input != nullptr) { ++ line = last_input; ++ } else { ++ // Ownership is transferred to sim_; ++ sim_->set_last_debugger_input(line); ++ } ++ // Use sscanf to parse the individual parts of the command line. At the ++ // moment no command expects more than two parameters. ++ int argc = SScanF( ++ line, ++ "%" XSTR(COMMAND_SIZE) "s " ++ "%" XSTR(ARG_SIZE) "s " ++ "%" XSTR(ARG_SIZE) "s", ++ cmd, arg1, arg2); ++ if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) { ++ Instruction* instr = reinterpret_cast(sim_->get_pc()); ++ if (!(instr->IsTrap()) || ++ instr->InstructionBits() == rtCallRedirInstr) { ++ sim_->InstructionDecode( ++ reinterpret_cast(sim_->get_pc())); ++ } else { ++ // Allow si to jump over generated breakpoints. ++ PrintF("/!\\ Jumping over generated breakpoint.\n"); ++ sim_->set_pc(sim_->get_pc() + kInstrSize); ++ } ++ } else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) { ++ // Execute the one instruction we broke at with breakpoints disabled. ++ sim_->InstructionDecode(reinterpret_cast(sim_->get_pc())); ++ // Leave the debugger shell. ++ done = true; ++ } else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) { ++ if (argc == 2) { ++ int64_t value; ++ double dvalue; ++ if (strcmp(arg1, "all") == 0) { ++ PrintAllRegs(); ++ } else if (strcmp(arg1, "allf") == 0) { ++ PrintAllRegsIncludingFPU(); ++ } else { ++ int regnum = Registers::Number(arg1); ++ int fpuregnum = FPURegisters::Number(arg1); ++ ++ if (regnum != kInvalidRegister) { ++ value = GetRegisterValue(regnum); ++ PrintF("%s: 0x%08" PRIx64 " %" PRId64 " \n", arg1, value, ++ value); ++ } else if (fpuregnum != kInvalidFPURegister) { ++ value = GetFPURegisterValue(fpuregnum); ++ dvalue = GetFPURegisterValueDouble(fpuregnum); ++ PrintF("%3s: 0x%016" PRIx64 " %16.4e\n", ++ FPURegisters::Name(fpuregnum), value, dvalue); ++ } else { ++ PrintF("%s unrecognized\n", arg1); ++ } ++ } ++ } else { ++ if (argc == 3) { ++ if (strcmp(arg2, "single") == 0) { ++ int64_t value; ++ float fvalue; ++ int fpuregnum = FPURegisters::Number(arg1); ++ ++ if (fpuregnum != kInvalidFPURegister) { ++ value = GetFPURegisterValue(fpuregnum); ++ value &= 0xFFFFFFFFUL; ++ fvalue = GetFPURegisterValueFloat(fpuregnum); ++ PrintF("%s: 0x%08" PRIx64 " %11.4e\n", arg1, value, fvalue); ++ } else { ++ PrintF("%s unrecognized\n", arg1); ++ } ++ } else { ++ PrintF("print single\n"); ++ } ++ } else { ++ PrintF("print or print single\n"); ++ } ++ } ++ } else if ((strcmp(cmd, "po") == 0) || ++ (strcmp(cmd, "printobject") == 0)) { ++ if (argc == 2) { ++ int64_t value; ++ StdoutStream os; ++ if (GetValue(arg1, &value)) { ++ Object obj(value); ++ os << arg1 << ": \n"; ++#ifdef DEBUG ++ obj.Print(os); ++ os << "\n"; ++#else ++ os << Brief(obj) << "\n"; ++#endif ++ } else { ++ os << arg1 << " unrecognized\n"; ++ } ++ } else { ++ PrintF("printobject \n"); ++ } ++ } else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) { ++ int64_t* cur = nullptr; ++ int64_t* end = nullptr; ++ int next_arg = 1; ++ ++ if (strcmp(cmd, "stack") == 0) { ++ cur = reinterpret_cast(sim_->get_register(Simulator::sp)); ++ } else { // Command "mem". ++ if (argc < 2) { ++ PrintF("Need to specify
to mem command\n"); ++ continue; ++ } ++ int64_t value; ++ if (!GetValue(arg1, &value)) { ++ PrintF("%s unrecognized\n", arg1); ++ continue; ++ } ++ cur = reinterpret_cast(value); ++ next_arg++; ++ } ++ ++ int64_t words; ++ if (argc == next_arg) { ++ words = 10; ++ } else { ++ if (!GetValue(argv[next_arg], &words)) { ++ words = 10; ++ } ++ } ++ end = cur + words; ++ ++ while (cur < end) { ++ PrintF(" 0x%012" PRIxPTR " : 0x%016" PRIx64 " %14" PRId64 " ", ++ reinterpret_cast(cur), *cur, *cur); ++ Object obj(*cur); ++ Heap* current_heap = sim_->isolate_->heap(); ++ if (obj.IsSmi() || ++ IsValidHeapObject(current_heap, HeapObject::cast(obj))) { ++ PrintF(" ("); ++ if (obj.IsSmi()) { ++ PrintF("smi %d", Smi::ToInt(obj)); ++ } else { ++ obj.ShortPrint(); ++ } ++ PrintF(")"); ++ } ++ PrintF("\n"); ++ cur++; ++ } ++ ++ } else if ((strcmp(cmd, "disasm") == 0) || (strcmp(cmd, "dpc") == 0) || ++ (strcmp(cmd, "di") == 0)) { ++ disasm::NameConverter converter; ++ disasm::Disassembler dasm(converter); ++ // Use a reasonably large buffer. ++ v8::internal::EmbeddedVector buffer; ++ ++ byte* cur = nullptr; ++ byte* end = nullptr; ++ ++ if (argc == 1) { ++ cur = reinterpret_cast(sim_->get_pc()); ++ end = cur + (10 * kInstrSize); ++ } else if (argc == 2) { ++ int regnum = Registers::Number(arg1); ++ if (regnum != kInvalidRegister || strncmp(arg1, "0x", 2) == 0) { ++ // The argument is an address or a register name. ++ int64_t value; ++ if (GetValue(arg1, &value)) { ++ cur = reinterpret_cast(value); ++ // Disassemble 10 instructions at . ++ end = cur + (10 * kInstrSize); ++ } ++ } else { ++ // The argument is the number of instructions. ++ int64_t value; ++ if (GetValue(arg1, &value)) { ++ cur = reinterpret_cast(sim_->get_pc()); ++ // Disassemble instructions. ++ end = cur + (value * kInstrSize); ++ } ++ } ++ } else { ++ int64_t value1; ++ int64_t value2; ++ if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { ++ cur = reinterpret_cast(value1); ++ end = cur + (value2 * kInstrSize); ++ } ++ } ++ ++ while (cur < end) { ++ dasm.InstructionDecode(buffer, cur); ++ PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast(cur), ++ buffer.begin()); ++ cur += kInstrSize; ++ } ++ } else if (strcmp(cmd, "gdb") == 0) { ++ PrintF("relinquishing control to gdb\n"); ++ v8::base::OS::DebugBreak(); ++ PrintF("regaining control from gdb\n"); ++ } else if (strcmp(cmd, "break") == 0 ++ || strcmp(cmd, "b") == 0 ++ || strcmp(cmd, "tbreak") == 0) { ++ bool is_tbreak = strcmp(cmd, "tbreak") == 0; ++ if (argc == 2) { ++ int64_t value; ++ if (GetValue(arg1, &value)) { ++ sim_->SetBreakpoint(reinterpret_cast(value), is_tbreak); ++ } else { ++ PrintF("%s unrecognized\n", arg1); ++ } ++ } else { ++ sim_->ListBreakpoints(); ++ PrintF("Use `break
` to set or disable a breakpoint\n"); ++ PrintF("Use `tbreak
` to set or disable a temporary breakpoint\n"); ++ } ++ } else if (strcmp(cmd, "flags") == 0) { ++ PrintF("No flags on RISC-V !\n"); ++ } else if (strcmp(cmd, "stop") == 0) { ++ int64_t value; ++ if (argc == 3) { ++ // Print information about all/the specified breakpoint(s). ++ if (strcmp(arg1, "info") == 0) { ++ if (strcmp(arg2, "all") == 0) { ++ PrintF("Stop information:\n"); ++ for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode; ++ i++) { ++ sim_->PrintStopInfo(i); ++ } ++ } else if (GetValue(arg2, &value)) { ++ sim_->PrintStopInfo(value); ++ } else { ++ PrintF("Unrecognized argument.\n"); ++ } ++ } else if (strcmp(arg1, "enable") == 0) { ++ // Enable all/the specified breakpoint(s). ++ if (strcmp(arg2, "all") == 0) { ++ for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode; ++ i++) { ++ sim_->EnableStop(i); ++ } ++ } else if (GetValue(arg2, &value)) { ++ sim_->EnableStop(value); ++ } else { ++ PrintF("Unrecognized argument.\n"); ++ } ++ } else if (strcmp(arg1, "disable") == 0) { ++ // Disable all/the specified breakpoint(s). ++ if (strcmp(arg2, "all") == 0) { ++ for (uint32_t i = kMaxWatchpointCode + 1; i <= kMaxStopCode; ++ i++) { ++ sim_->DisableStop(i); ++ } ++ } else if (GetValue(arg2, &value)) { ++ sim_->DisableStop(value); ++ } else { ++ PrintF("Unrecognized argument.\n"); ++ } ++ } ++ } else { ++ PrintF("Wrong usage. Use help command for more information.\n"); ++ } ++ } else if ((strcmp(cmd, "stat") == 0) || (strcmp(cmd, "st") == 0)) { ++ // Print registers and disassemble. ++ PrintAllRegs(); ++ PrintF("\n"); ++ ++ disasm::NameConverter converter; ++ disasm::Disassembler dasm(converter); ++ // Use a reasonably large buffer. ++ v8::internal::EmbeddedVector buffer; ++ ++ byte* cur = nullptr; ++ byte* end = nullptr; ++ ++ if (argc == 1) { ++ cur = reinterpret_cast(sim_->get_pc()); ++ end = cur + (10 * kInstrSize); ++ } else if (argc == 2) { ++ int64_t value; ++ if (GetValue(arg1, &value)) { ++ cur = reinterpret_cast(value); ++ // no length parameter passed, assume 10 instructions ++ end = cur + (10 * kInstrSize); ++ } ++ } else { ++ int64_t value1; ++ int64_t value2; ++ if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) { ++ cur = reinterpret_cast(value1); ++ end = cur + (value2 * kInstrSize); ++ } ++ } ++ ++ while (cur < end) { ++ dasm.InstructionDecode(buffer, cur); ++ PrintF(" 0x%08" PRIxPTR " %s\n", reinterpret_cast(cur), ++ buffer.begin()); ++ cur += kInstrSize; ++ } ++ } else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) { ++ PrintF("cont (alias 'c')\n"); ++ PrintF(" Continue execution\n"); ++ PrintF("stepi (alias 'si')\n"); ++ PrintF(" Step one instruction\n"); ++ PrintF("print (alias 'p')\n"); ++ PrintF(" print \n"); ++ PrintF(" Print register content\n"); ++ PrintF(" Use register name 'all' to print all GPRs\n"); ++ PrintF(" Use register name 'allf' to print all GPRs and FPRs\n"); ++ PrintF("printobject (alias 'po')\n"); ++ PrintF(" printobject \n"); ++ PrintF(" Print an object from a register\n"); ++ PrintF("stack\n"); ++ PrintF(" stack []\n"); ++ PrintF(" Dump stack content, default dump 10 words)\n"); ++ PrintF("mem\n"); ++ PrintF(" mem
[]\n"); ++ PrintF(" Dump memory content, default dump 10 words)\n"); ++ PrintF("flags\n"); ++ PrintF(" print flags\n"); ++ PrintF("disasm (alias 'di')\n"); ++ PrintF(" disasm []\n"); ++ PrintF(" disasm [
] (e.g., disasm pc) \n"); ++ PrintF(" disasm [[
] ]\n"); ++ PrintF(" Disassemble code, default is 10 instructions\n"); ++ PrintF(" from pc\n"); ++ PrintF("gdb \n"); ++ PrintF(" Return to gdb if the simulator was started with gdb\n"); ++ PrintF("break (alias 'b')\n"); ++ PrintF(" break : list all breakpoints\n"); ++ PrintF(" break
: set / enable / disable a breakpoint.\n"); ++ PrintF("tbreak\n"); ++ PrintF(" tbreak : list all breakpoints\n"); ++ PrintF(" tbreak
: set / enable / disable a temporary breakpoint.\n"); ++ PrintF(" Set a breakpoint enabled only for one stop. \n"); ++ PrintF("stop feature:\n"); ++ PrintF(" Description:\n"); ++ PrintF(" Stops are debug instructions inserted by\n"); ++ PrintF(" the Assembler::stop() function.\n"); ++ PrintF(" When hitting a stop, the Simulator will\n"); ++ PrintF(" stop and give control to the Debugger.\n"); ++ PrintF(" All stop codes are watched:\n"); ++ PrintF(" - They can be enabled / disabled: the Simulator\n"); ++ PrintF(" will / won't stop when hitting them.\n"); ++ PrintF(" - The Simulator keeps track of how many times they \n"); ++ PrintF(" are met. (See the info command.) Going over a\n"); ++ PrintF(" disabled stop still increases its counter. \n"); ++ PrintF(" Commands:\n"); ++ PrintF(" stop info all/ : print infos about number \n"); ++ PrintF(" or all stop(s).\n"); ++ PrintF(" stop enable/disable all/ : enables / disables\n"); ++ PrintF(" all or number stop(s)\n"); ++ } else { ++ PrintF("Unknown command: %s\n", cmd); ++ } ++ } ++ } ++ ++#undef COMMAND_SIZE ++#undef ARG_SIZE ++ ++#undef STR ++#undef XSTR ++} ++ ++void Simulator::SetBreakpoint(Instruction* location, bool is_tbreak) { ++ for (unsigned i = 0; i < breakpoints_.size(); i++) { ++ if (breakpoints_.at(i).location == location) { ++ if (breakpoints_.at(i).is_tbreak != is_tbreak) { ++ PrintF("Change breakpoint at %p to %s breakpoint\n", ++ reinterpret_cast(location), ++ is_tbreak ? "temporary" : "regular"); ++ breakpoints_.at(i).is_tbreak = is_tbreak; ++ return; ++ } ++ PrintF("Existing breakpoint at %p was %s\n", ++ reinterpret_cast(location), ++ breakpoints_.at(i).enabled ? "disabled" : "enabled"); ++ breakpoints_.at(i).enabled = !breakpoints_.at(i).enabled; ++ return; ++ } ++ } ++ Breakpoint new_breakpoint = {location, true, is_tbreak}; ++ breakpoints_.push_back(new_breakpoint); ++ PrintF("Set a %sbreakpoint at %p\n", ++ is_tbreak ? "temporary " : "", ++ reinterpret_cast(location)); ++} ++ ++void Simulator::ListBreakpoints() { ++ PrintF("Breakpoints:\n"); ++ for (unsigned i = 0; i < breakpoints_.size(); i++) { ++ PrintF("%p : %s %s\n", ++ reinterpret_cast(breakpoints_.at(i).location), ++ breakpoints_.at(i).enabled ? "enabled" : "disabled", ++ breakpoints_.at(i).is_tbreak ? ": temporary" : ""); ++ } ++} ++ ++void Simulator::CheckBreakpoints() { ++ bool hit_a_breakpoint = false; ++ bool is_tbreak = false; ++ Instruction* pc_ = reinterpret_cast(get_pc()); ++ for (unsigned i = 0; i < breakpoints_.size(); i++) { ++ if ((breakpoints_.at(i).location == pc_) && breakpoints_.at(i).enabled) { ++ hit_a_breakpoint = true; ++ if (breakpoints_.at(i).is_tbreak) { ++ // Disable a temporary breakpoint. ++ is_tbreak = true; ++ breakpoints_.at(i).enabled = false; ++ } ++ break; ++ } ++ } ++ if (hit_a_breakpoint) { ++ PrintF("Hit %sa breakpoint at %p.\n", ++ is_tbreak ? "and disabled " : "", ++ reinterpret_cast(pc_)); ++ RiscvDebugger dbg(this); ++ dbg.Debug(); ++ } ++} ++ ++bool Simulator::ICacheMatch(void* one, void* two) { ++ DCHECK_EQ(reinterpret_cast(one) & CachePage::kPageMask, 0); ++ DCHECK_EQ(reinterpret_cast(two) & CachePage::kPageMask, 0); ++ return one == two; ++} ++ ++static uint32_t ICacheHash(void* key) { ++ return static_cast(reinterpret_cast(key)) >> 2; ++} ++ ++static bool AllOnOnePage(uintptr_t start, size_t size) { ++ intptr_t start_page = (start & ~CachePage::kPageMask); ++ intptr_t end_page = ((start + size) & ~CachePage::kPageMask); ++ return start_page == end_page; ++} ++ ++void Simulator::set_last_debugger_input(char* input) { ++ DeleteArray(last_debugger_input_); ++ last_debugger_input_ = input; ++} ++ ++void Simulator::SetRedirectInstruction(Instruction* instruction) { ++ instruction->SetInstructionBits(rtCallRedirInstr); ++} ++ ++void Simulator::FlushICache(base::CustomMatcherHashMap* i_cache, ++ void* start_addr, size_t size) { ++ int64_t start = reinterpret_cast(start_addr); ++ int64_t intra_line = (start & CachePage::kLineMask); ++ start -= intra_line; ++ size += intra_line; ++ size = ((size - 1) | CachePage::kLineMask) + 1; ++ int offset = (start & CachePage::kPageMask); ++ while (!AllOnOnePage(start, size - 1)) { ++ int bytes_to_flush = CachePage::kPageSize - offset; ++ FlushOnePage(i_cache, start, bytes_to_flush); ++ start += bytes_to_flush; ++ size -= bytes_to_flush; ++ DCHECK_EQ((int64_t)0, start & CachePage::kPageMask); ++ offset = 0; ++ } ++ if (size != 0) { ++ FlushOnePage(i_cache, start, size); ++ } ++} ++ ++CachePage* Simulator::GetCachePage(base::CustomMatcherHashMap* i_cache, ++ void* page) { ++ base::HashMap::Entry* entry = i_cache->LookupOrInsert(page, ICacheHash(page)); ++ if (entry->value == nullptr) { ++ CachePage* new_page = new CachePage(); ++ entry->value = new_page; ++ } ++ return reinterpret_cast(entry->value); ++} ++ ++// Flush from start up to and not including start + size. ++void Simulator::FlushOnePage(base::CustomMatcherHashMap* i_cache, ++ intptr_t start, size_t size) { ++ DCHECK_LE(size, CachePage::kPageSize); ++ DCHECK(AllOnOnePage(start, size - 1)); ++ DCHECK_EQ(start & CachePage::kLineMask, 0); ++ DCHECK_EQ(size & CachePage::kLineMask, 0); ++ void* page = reinterpret_cast(start & (~CachePage::kPageMask)); ++ int offset = (start & CachePage::kPageMask); ++ CachePage* cache_page = GetCachePage(i_cache, page); ++ char* valid_bytemap = cache_page->ValidityByte(offset); ++ memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift); ++} ++ ++void Simulator::CheckICache(base::CustomMatcherHashMap* i_cache, ++ Instruction* instr) { ++ int64_t address = reinterpret_cast(instr); ++ void* page = reinterpret_cast(address & (~CachePage::kPageMask)); ++ void* line = reinterpret_cast(address & (~CachePage::kLineMask)); ++ int offset = (address & CachePage::kPageMask); ++ CachePage* cache_page = GetCachePage(i_cache, page); ++ char* cache_valid_byte = cache_page->ValidityByte(offset); ++ bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID); ++ char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask); ++ if (cache_hit) { ++ // Check that the data in memory matches the contents of the I-cache. ++ CHECK_EQ(0, memcmp(reinterpret_cast(instr), ++ cache_page->CachedData(offset), kInstrSize)); ++ } else { ++ // Cache miss. Load memory into the cache. ++ memcpy(cached_line, line, CachePage::kLineLength); ++ *cache_valid_byte = CachePage::LINE_VALID; ++ } ++} ++ ++Simulator::Simulator(Isolate* isolate) : isolate_(isolate) { ++ // Set up simulator support first. Some of this information is needed to ++ // setup the architecture state. ++ stack_size_ = FLAG_sim_stack_size * KB; ++ stack_ = reinterpret_cast(malloc(stack_size_)); ++ pc_modified_ = false; ++ icount_ = 0; ++ break_count_ = 0; ++ // Reset debug helpers. ++ breakpoints_.clear(); ++ // TODO: 'next' command ++ //break_on_next_ = false; ++ ++ // Set up architecture state. ++ // All registers are initialized to zero to start with. ++ for (int i = 0; i < kNumSimuRegisters; i++) { ++ registers_[i] = 0; ++ } ++ ++ for (int i = 0; i < kNumFPURegisters; i++) { ++ FPUregisters_[i] = 0; ++ } ++ ++ FCSR_ = 0; ++ ++ // The sp is initialized to point to the bottom (high address) of the ++ // allocated stack area. To be safe in potential stack underflows we leave ++ // some buffer below. ++ registers_[sp] = reinterpret_cast(stack_) + stack_size_ - 64; ++ // The ra and pc are initialized to a known bad value that will cause an ++ // access violation if the simulator ever tries to execute it. ++ registers_[pc] = bad_ra; ++ registers_[ra] = bad_ra; ++ ++ last_debugger_input_ = nullptr; ++} ++ ++Simulator::~Simulator() { ++ GlobalMonitor::Get()->RemoveLinkedAddress(&global_monitor_thread_); ++ free(stack_); ++} ++ ++// Get the active Simulator for the current thread. ++Simulator* Simulator::current(Isolate* isolate) { ++ v8::internal::Isolate::PerIsolateThreadData* isolate_data = ++ isolate->FindOrAllocatePerThreadDataForThisThread(); ++ DCHECK_NOT_NULL(isolate_data); ++ ++ Simulator* sim = isolate_data->simulator(); ++ if (sim == nullptr) { ++ // TODO(146): delete the simulator object when a thread/isolate goes away. ++ sim = new Simulator(isolate); ++ isolate_data->set_simulator(sim); ++ } ++ return sim; ++} ++ ++// Sets the register in the architecture state. It will also deal with ++// updating Simulator internal state for special registers such as PC. ++void Simulator::set_register(int reg, int64_t value) { ++ DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); ++ if (reg == pc) { ++ pc_modified_ = true; ++ } ++ ++ // Zero register always holds 0. ++ registers_[reg] = (reg == 0) ? 0 : value; ++} ++ ++void Simulator::set_dw_register(int reg, const int* dbl) { ++ DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); ++ registers_[reg] = dbl[1]; ++ registers_[reg] = registers_[reg] << 32; ++ registers_[reg] += dbl[0]; ++} ++ ++void Simulator::set_fpu_register(int fpureg, int64_t value) { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ FPUregisters_[fpureg] = value; ++} ++ ++void Simulator::set_fpu_register_word(int fpureg, int32_t value) { ++ // Set ONLY lower 32-bits, leaving upper bits untouched. ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ int32_t* pword; ++ if (kArchEndian == kLittle) { ++ pword = reinterpret_cast(&FPUregisters_[fpureg]); ++ } else { ++ pword = reinterpret_cast(&FPUregisters_[fpureg]) + 1; ++ } ++ *pword = value; ++} ++ ++void Simulator::set_fpu_register_hi_word(int fpureg, int32_t value) { ++ // Set ONLY upper 32-bits, leaving lower bits untouched. ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ int32_t* phiword; ++ if (kArchEndian == kLittle) { ++ phiword = (reinterpret_cast(&FPUregisters_[fpureg])) + 1; ++ } else { ++ phiword = reinterpret_cast(&FPUregisters_[fpureg]); ++ } ++ *phiword = value; ++} ++ ++void Simulator::set_fpu_register_float(int fpureg, float value) { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ FPUregisters_[fpureg] = box_float(value); ++} ++ ++void Simulator::set_fpu_register_double(int fpureg, double value) { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ *bit_cast(&FPUregisters_[fpureg]) = value; ++} ++ ++// Get the register from the architecture state. This function does handle ++// the special case of accessing the PC register. ++int64_t Simulator::get_register(int reg) const { ++ DCHECK((reg >= 0) && (reg < kNumSimuRegisters)); ++ if (reg == 0) ++ return 0; ++ else ++ return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0); ++} ++ ++double Simulator::get_double_from_register_pair(int reg) { ++ // TODO(plind): bad ABI stuff, refactor or remove. ++ DCHECK((reg >= 0) && (reg < kNumSimuRegisters) && ((reg % 2) == 0)); ++ ++ double dm_val = 0.0; ++ // Read the bits from the unsigned integer register_[] array ++ // into the double precision floating point value and return it. ++ char buffer[sizeof(registers_[0])]; ++ memcpy(buffer, ®isters_[reg], sizeof(registers_[0])); ++ memcpy(&dm_val, buffer, sizeof(registers_[0])); ++ return (dm_val); ++} ++ ++int64_t Simulator::get_fpu_register(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ return FPUregisters_[fpureg]; ++} ++ ++int32_t Simulator::get_fpu_register_word(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ return static_cast(FPUregisters_[fpureg] & 0xFFFFFFFF); ++} ++ ++int32_t Simulator::get_fpu_register_signed_word(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ return static_cast(FPUregisters_[fpureg] & 0xFFFFFFFF); ++} ++ ++int32_t Simulator::get_fpu_register_hi_word(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ return static_cast((FPUregisters_[fpureg] >> 32) & 0xFFFFFFFF); ++} ++ ++float Simulator::get_fpu_register_float(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ if (!is_boxed_float(FPUregisters_[fpureg])) { ++ return std::numeric_limits::quiet_NaN(); ++ } ++ return *bit_cast(const_cast(&FPUregisters_[fpureg])); ++} ++ ++double Simulator::get_fpu_register_double(int fpureg) const { ++ DCHECK((fpureg >= 0) && (fpureg < kNumFPURegisters)); ++ return *bit_cast(&FPUregisters_[fpureg]); ++} ++ ++// Runtime FP routines take up to two double arguments and zero ++// or one integer arguments. All are constructed here, ++// from fa0, fa1, and a0. ++void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { ++ *x = get_fpu_register_double(fa0); ++ *y = get_fpu_register_double(fa1); ++ *z = static_cast(get_register(a0)); ++} ++ ++// The return value is in fa0. ++void Simulator::SetFpResult(const double& result) { ++ set_fpu_register_double(fa0, result); ++} ++ ++// helper functions to read/write/set/clear CRC values/bits ++uint32_t Simulator::read_csr_value(uint32_t csr) { ++ switch (csr) { ++ case csr_fflags: // Floating-Point Accrued Exceptions (RW) ++ return (FCSR_ & kFcsrFlagsMask); ++ case csr_frm: // Floating-Point Dynamic Rounding Mode (RW) ++ return (FCSR_ & kFcsrFrmMask) >> kFcsrFrmShift; ++ case csr_fcsr: // Floating-Point Control and Status Register (RW) ++ return (FCSR_ & kFcsrMask); ++ default: ++ UNIMPLEMENTED(); ++ } ++} ++ ++uint32_t Simulator::get_dynamic_rounding_mode() { ++ return read_csr_value(csr_frm); ++} ++ ++void Simulator::write_csr_value(uint32_t csr, uint64_t val) { ++ uint32_t value = (uint32_t)val; ++ switch (csr) { ++ case csr_fflags: // Floating-Point Accrued Exceptions (RW) ++ DCHECK(value <= ((1 << kFcsrFlagsBits) - 1)); ++ FCSR_ = (FCSR_ & (~kFcsrFlagsMask)) | value; ++ break; ++ case csr_frm: // Floating-Point Dynamic Rounding Mode (RW) ++ DCHECK(value <= ((1 << kFcsrFrmBits) - 1)); ++ FCSR_ = (FCSR_ & (~kFcsrFrmMask)) | (value << kFcsrFrmShift); ++ break; ++ case csr_fcsr: // Floating-Point Control and Status Register (RW) ++ DCHECK(value <= ((1 << kFcsrBits) - 1)); ++ FCSR_ = (FCSR_ & (~kFcsrMask)) | value; ++ break; ++ default: ++ UNIMPLEMENTED(); ++ } ++} ++ ++void Simulator::set_csr_bits(uint32_t csr, uint64_t val) { ++ uint32_t value = (uint32_t)val; ++ switch (csr) { ++ case csr_fflags: // Floating-Point Accrued Exceptions (RW) ++ DCHECK(value <= ((1 << kFcsrFlagsBits) - 1)); ++ FCSR_ = FCSR_ | value; ++ break; ++ case csr_frm: // Floating-Point Dynamic Rounding Mode (RW) ++ DCHECK(value <= ((1 << kFcsrFrmBits) - 1)); ++ FCSR_ = FCSR_ | (value << kFcsrFrmShift); ++ break; ++ case csr_fcsr: // Floating-Point Control and Status Register (RW) ++ DCHECK(value <= ((1 << kFcsrBits) - 1)); ++ FCSR_ = FCSR_ | value; ++ break; ++ default: ++ UNIMPLEMENTED(); ++ } ++} ++ ++void Simulator::clear_csr_bits(uint32_t csr, uint64_t val) { ++ uint32_t value = (uint32_t)val; ++ switch (csr) { ++ case csr_fflags: // Floating-Point Accrued Exceptions (RW) ++ DCHECK(value <= ((1 << kFcsrFlagsBits) - 1)); ++ FCSR_ = FCSR_ & (~value); ++ break; ++ case csr_frm: // Floating-Point Dynamic Rounding Mode (RW) ++ DCHECK(value <= ((1 << kFcsrFrmBits) - 1)); ++ FCSR_ = FCSR_ & (~(value << kFcsrFrmShift)); ++ break; ++ case csr_fcsr: // Floating-Point Control and Status Register (RW) ++ DCHECK(value <= ((1 << kFcsrBits) - 1)); ++ FCSR_ = FCSR_ & (~value); ++ break; ++ default: ++ UNIMPLEMENTED(); ++ } ++} ++ ++bool Simulator::test_fflags_bits(uint32_t mask) { ++ return (FCSR_ & kFcsrFlagsMask & mask) != 0; ++} ++ ++template ++T Simulator::FMaxMinHelper(T a, T b, MaxMinKind kind) { ++ // set invalid bit for signaling nan ++ if ((a == std::numeric_limits::signaling_NaN()) || ++ (b == std::numeric_limits::signaling_NaN())) { ++ // FIXME: NV -> kInvalidOperation ++ set_csr_bits(csr_fflags, kInvalidOperation); ++ } ++ ++ T result = 0; ++ if (std::isnan(a) && std::isnan(b)) { ++ result = a; ++ } else if (std::isnan(a)) { ++ result = b; ++ } else if (std::isnan(b)) { ++ result = a; ++ } else if (b == a) { // Handle -0.0 == 0.0 case. ++ if (kind == MaxMinKind::kMax) { ++ result = std::signbit(b) ? a : b; ++ } else { ++ result = std::signbit(b) ? b : a; ++ } ++ } else { ++ result = (kind == MaxMinKind::kMax) ? fmax(a, b) : fmin(a, b); ++ } ++ ++ return result; ++} ++ ++// Raw access to the PC register. ++void Simulator::set_pc(int64_t value) { ++ pc_modified_ = true; ++ registers_[pc] = value; ++ DCHECK(has_bad_pc() || ((value % kInstrSize) == 0)); ++} ++ ++bool Simulator::has_bad_pc() const { ++ return ((registers_[pc] == bad_ra) || (registers_[pc] == end_sim_pc)); ++} ++ ++// Raw access to the PC register without the special adjustment when reading. ++int64_t Simulator::get_pc() const { return registers_[pc]; } ++ ++// The RISC-V spec leaves it open to the implementation on how to handle ++// unaligned reads and writes. For now, we simply disallow unaligned reads but ++// at some point, we may want to implement some other behavior. ++ ++// TODO(plind): refactor this messy debug code when we do unaligned access. ++void Simulator::DieOrDebug() { ++ if ((1)) { // Flag for this was removed. ++ RiscvDebugger dbg(this); ++ dbg.Debug(); ++ } else { ++ base::OS::Abort(); ++ } ++} ++ ++void Simulator::TraceRegWr(int64_t value, TraceType t) { ++ if (::v8::internal::FLAG_trace_sim) { ++ union { ++ int64_t fmt_int64; ++ int32_t fmt_int32[2]; ++ float fmt_float[2]; ++ double fmt_double; ++ } v; ++ v.fmt_int64 = value; ++ ++ switch (t) { ++ case WORD: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32 ++ " uint32:%" PRIu32, ++ v.fmt_int64, icount_, v.fmt_int32[0], v.fmt_int32[0]); ++ break; ++ case DWORD: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int64:%" PRId64 ++ " uint64:%" PRIu64, ++ value, icount_, value, value); ++ break; ++ case FLOAT: ++ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") flt:%e", ++ v.fmt_int64, icount_, v.fmt_float[0]); ++ break; ++ case DOUBLE: ++ SNPrintF(trace_buf_, "%016" PRIx64 " (%" PRId64 ") dbl:%e", ++ v.fmt_int64, icount_, v.fmt_double); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++} ++ ++// TODO(plind): consider making icount_ printing a flag option. ++template ++void Simulator::TraceMemRd(int64_t addr, T value, int64_t reg_value) { ++ if (::v8::internal::FLAG_trace_sim) { ++ if (std::is_integral::value) { ++ switch (sizeof(T)) { ++ case 1: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int8:%" PRId8 ++ " uint8:%" PRIu8 " <-- [addr: %" PRIx64 "]", ++ reg_value, icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ case 2: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int16:%" PRId16 ++ " uint16:%" PRIu16 " <-- [addr: %" PRIx64 "]", ++ reg_value, icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ case 4: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int32:%" PRId32 ++ " uint32:%" PRIu32 " <-- [addr: %" PRIx64 "]", ++ reg_value, icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ case 8: ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") int64:%" PRId64 ++ " uint64:%" PRIu64 " <-- [addr: %" PRIx64 "]", ++ reg_value, icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } else if (std::is_same::value) { ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") flt:%e <-- [addr: %" PRIx64 ++ "]", ++ reg_value, icount_, static_cast(value), addr); ++ } else if (std::is_same::value) { ++ SNPrintF(trace_buf_, ++ "%016" PRIx64 " (%" PRId64 ") dbl:%e <-- [addr: %" PRIx64 ++ "]", ++ reg_value, icount_, static_cast(value), addr); ++ } else { ++ UNREACHABLE(); ++ } ++ } ++} ++ ++template ++void Simulator::TraceMemWr(int64_t addr, T value) { ++ if (::v8::internal::FLAG_trace_sim) { ++ switch (sizeof(T)) { ++ case 1: ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ") int8:%" PRId8 ++ " uint8:%" PRIu8 " --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ case 2: ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ") int16:%" PRId16 ++ " uint16:%" PRIu16 " --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), ++ static_cast(value), addr); ++ break; ++ case 4: ++ if (std::is_integral::value) { ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ") int32:%" PRId32 ++ " uint32:%" PRIu32 " --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), ++ static_cast(value), addr); ++ } else { ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ++ ") flt:%e --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), addr); ++ } ++ break; ++ case 8: ++ if (std::is_integral::value) { ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ") int64:%" PRId64 ++ " uint64:%" PRIu64 " --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), ++ static_cast(value), addr); ++ } else { ++ SNPrintF(trace_buf_, ++ " (%" PRIu64 ++ ") dbl:%e --> [addr: %" PRIx64 "]", ++ icount_, static_cast(value), addr); ++ } ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++} ++ ++// RISCV Memory Read/Write functions ++ ++// FIXME (RISCV): check whether the specific board supports unaligned load/store ++// (determined by EEI). For now, we assume the board does not support unaligned ++// load/store (e.g., trapping) ++template ++T Simulator::ReadMem(int64_t addr, Instruction* instr) { ++ if (addr >= 0 && addr < 0x400) { ++ // This has to be a nullptr-dereference, drop into debugger. ++ PrintF("Memory read from bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR ++ " \n", ++ addr, reinterpret_cast(instr)); ++ DieOrDebug(); ++ } ++ ++ // check for natural alignment ++ if ((addr & (sizeof(T) - 1)) != 0) { ++ PrintF("Unaligned read at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr, ++ reinterpret_cast(instr)); ++ DieOrDebug(); ++ } ++ ++ T* ptr = reinterpret_cast(addr); ++ T value = *ptr; ++ return value; ++} ++ ++template ++void Simulator::WriteMem(int64_t addr, T value, Instruction* instr) { ++ if (addr >= 0 && addr < 0x400) { ++ // This has to be a nullptr-dereference, drop into debugger. ++ PrintF("Memory write to bad address: 0x%08" PRIx64 " , pc=0x%08" PRIxPTR ++ " \n", ++ addr, reinterpret_cast(instr)); ++ DieOrDebug(); ++ } ++ ++ // check for natural alignment ++ if ((addr & (sizeof(T) - 1)) != 0) { ++ PrintF("Unaligned write at 0x%08" PRIx64 " , pc=0x%08" V8PRIxPTR "\n", addr, ++ reinterpret_cast(instr)); ++ DieOrDebug(); ++ } ++ ++ T* ptr = reinterpret_cast(addr); ++ TraceMemWr(addr, value); ++ *ptr = value; ++} ++ ++// Returns the limit of the stack area to enable checking for stack overflows. ++uintptr_t Simulator::StackLimit(uintptr_t c_limit) const { ++ // The simulator uses a separate JS stack. If we have exhausted the C stack, ++ // we also drop down the JS limit to reflect the exhaustion on the JS stack. ++ if (GetCurrentStackPosition() < c_limit) { ++ return reinterpret_cast(get_sp()); ++ } ++ ++ // Otherwise the limit is the JS stack. Leave a safety margin of 1024 bytes ++ // to prevent overrunning the stack when pushing values. ++ return reinterpret_cast(stack_) + 1024; ++} ++ ++// Unsupported instructions use Format to print an error and stop execution. ++void Simulator::Format(Instruction* instr, const char* format) { ++ PrintF("Simulator found unsupported instruction:\n 0x%08" PRIxPTR " : %s\n", ++ reinterpret_cast(instr), format); ++ UNIMPLEMENTED_RISCV(); ++} ++ ++// Calls into the V8 runtime are based on this very simple interface. ++// Note: To be able to return two values from some calls the code in ++// runtime.cc uses the ObjectPair which is essentially two 32-bit values ++// stuffed into a 64-bit value. With the code below we assume that all runtime ++// calls return 64 bits of result. If they don't, the a1 result register ++// contains a bogus value, which is fine because it is caller-saved. ++ ++using SimulatorRuntimeCall = ObjectPair (*)(int64_t arg0, int64_t arg1, ++ int64_t arg2, int64_t arg3, ++ int64_t arg4, int64_t arg5, ++ int64_t arg6, int64_t arg7, ++ int64_t arg8, int64_t arg9); ++ ++// These prototypes handle the four types of FP calls. ++using SimulatorRuntimeCompareCall = int64_t (*)(double darg0, double darg1); ++using SimulatorRuntimeFPFPCall = double (*)(double darg0, double darg1); ++using SimulatorRuntimeFPCall = double (*)(double darg0); ++using SimulatorRuntimeFPIntCall = double (*)(double darg0, int32_t arg0); ++ ++// This signature supports direct call in to API function native callback ++// (refer to InvocationCallback in v8.h). ++using SimulatorRuntimeDirectApiCall = void (*)(int64_t arg0); ++using SimulatorRuntimeProfilingApiCall = void (*)(int64_t arg0, void* arg1); ++ ++// This signature supports direct call to accessor getter callback. ++using SimulatorRuntimeDirectGetterCall = void (*)(int64_t arg0, int64_t arg1); ++using SimulatorRuntimeProfilingGetterCall = void (*)(int64_t arg0, int64_t arg1, ++ void* arg2); ++ ++// Software interrupt instructions are used by the simulator to call into the ++// C-based V8 runtime. They are also used for debugging with simulator. ++void Simulator::SoftwareInterrupt() { ++ // There are two instructions that could get us here, the ebreak or ecall ++ // instructions are "SYSTEM" class opcode distinuished by Imm12Value field w/ ++ // the rest of instruction fields being zero ++ int32_t func = instr_.Imm12Value(); ++ // We first check if we met a call_rt_redirected. ++ if (instr_.InstructionBits() == rtCallRedirInstr) { // ECALL ++ Redirection* redirection = Redirection::FromInstruction(instr_.instr()); ++ ++ int64_t* stack_pointer = reinterpret_cast(get_register(sp)); ++ ++ int64_t arg0 = get_register(a0); ++ int64_t arg1 = get_register(a1); ++ int64_t arg2 = get_register(a2); ++ int64_t arg3 = get_register(a3); ++ int64_t arg4 = get_register(a4); ++ int64_t arg5 = get_register(a5); ++ int64_t arg6 = get_register(a6); ++ int64_t arg7 = get_register(a7); ++ int64_t arg8 = stack_pointer[0]; ++ int64_t arg9 = stack_pointer[1]; ++ STATIC_ASSERT(kMaxCParameters == 10); ++ ++ bool fp_call = ++ (redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) || ++ (redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) || ++ (redirection->type() == ExternalReference::BUILTIN_FP_CALL) || ++ (redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL); ++ ++ // This is dodgy but it works because the C entry stubs are never moved. ++ // See comment in codegen-arm.cc and bug 1242173. ++ int64_t saved_ra = get_register(ra); ++ ++ intptr_t external = ++ reinterpret_cast(redirection->external_function()); ++ ++ if (fp_call) { ++ double dval0, dval1; // one or two double parameters ++ int32_t ival; // zero or one integer parameters ++ int64_t iresult = 0; // integer return value ++ double dresult = 0; // double return value ++ GetFpArgs(&dval0, &dval1, &ival); ++ SimulatorRuntimeCall generic_target = ++ reinterpret_cast(external); ++ if (::v8::internal::FLAG_trace_sim) { ++ switch (redirection->type()) { ++ case ExternalReference::BUILTIN_FP_FP_CALL: ++ case ExternalReference::BUILTIN_COMPARE_CALL: ++ PrintF("Call to host function at %p with args %f, %f", ++ reinterpret_cast(FUNCTION_ADDR(generic_target)), ++ dval0, dval1); ++ break; ++ case ExternalReference::BUILTIN_FP_CALL: ++ PrintF("Call to host function at %p with arg %f", ++ reinterpret_cast(FUNCTION_ADDR(generic_target)), ++ dval0); ++ break; ++ case ExternalReference::BUILTIN_FP_INT_CALL: ++ PrintF("Call to host function at %p with args %f, %d", ++ reinterpret_cast(FUNCTION_ADDR(generic_target)), ++ dval0, ival); ++ break; ++ default: ++ UNREACHABLE(); ++ break; ++ } ++ } ++ switch (redirection->type()) { ++ case ExternalReference::BUILTIN_COMPARE_CALL: { ++ SimulatorRuntimeCompareCall target = ++ reinterpret_cast(external); ++ iresult = target(dval0, dval1); ++ set_register(a0, static_cast(iresult)); ++ // set_register(a1, static_cast(iresult >> 32)); ++ break; ++ } ++ case ExternalReference::BUILTIN_FP_FP_CALL: { ++ SimulatorRuntimeFPFPCall target = ++ reinterpret_cast(external); ++ dresult = target(dval0, dval1); ++ SetFpResult(dresult); ++ break; ++ } ++ case ExternalReference::BUILTIN_FP_CALL: { ++ SimulatorRuntimeFPCall target = ++ reinterpret_cast(external); ++ dresult = target(dval0); ++ SetFpResult(dresult); ++ break; ++ } ++ case ExternalReference::BUILTIN_FP_INT_CALL: { ++ SimulatorRuntimeFPIntCall target = ++ reinterpret_cast(external); ++ dresult = target(dval0, ival); ++ SetFpResult(dresult); ++ break; ++ } ++ default: ++ UNREACHABLE(); ++ break; ++ } ++ if (::v8::internal::FLAG_trace_sim) { ++ switch (redirection->type()) { ++ case ExternalReference::BUILTIN_COMPARE_CALL: ++ PrintF("Returned %08x\n", static_cast(iresult)); ++ break; ++ case ExternalReference::BUILTIN_FP_FP_CALL: ++ case ExternalReference::BUILTIN_FP_CALL: ++ case ExternalReference::BUILTIN_FP_INT_CALL: ++ PrintF("Returned %f\n", dresult); ++ break; ++ default: ++ UNREACHABLE(); ++ break; ++ } ++ } ++ } else if (redirection->type() == ExternalReference::DIRECT_API_CALL) { ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF("Call to host function at %p args %08" PRIx64 " \n", ++ reinterpret_cast(external), arg0); ++ } ++ SimulatorRuntimeDirectApiCall target = ++ reinterpret_cast(external); ++ target(arg0); ++ } else if (redirection->type() == ExternalReference::PROFILING_API_CALL) { ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF("Call to host function at %p args %08" PRIx64 " %08" PRIx64 ++ " \n", ++ reinterpret_cast(external), arg0, arg1); ++ } ++ SimulatorRuntimeProfilingApiCall target = ++ reinterpret_cast(external); ++ target(arg0, Redirection::ReverseRedirection(arg1)); ++ } else if (redirection->type() == ExternalReference::DIRECT_GETTER_CALL) { ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF("Call to host function at %p args %08" PRIx64 " %08" PRIx64 ++ " \n", ++ reinterpret_cast(external), arg0, arg1); ++ } ++ SimulatorRuntimeDirectGetterCall target = ++ reinterpret_cast(external); ++ target(arg0, arg1); ++ } else if (redirection->type() == ++ ExternalReference::PROFILING_GETTER_CALL) { ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF("Call to host function at %p args %08" PRIx64 " %08" PRIx64 ++ " %08" PRIx64 " \n", ++ reinterpret_cast(external), arg0, arg1, arg2); ++ } ++ SimulatorRuntimeProfilingGetterCall target = ++ reinterpret_cast(external); ++ target(arg0, arg1, Redirection::ReverseRedirection(arg2)); ++ } else { ++ DCHECK(redirection->type() == ExternalReference::BUILTIN_CALL || ++ redirection->type() == ExternalReference::BUILTIN_CALL_PAIR); ++ SimulatorRuntimeCall target = ++ reinterpret_cast(external); ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF( ++ "Call to host function at %p " ++ "args %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 ++ " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 " , %08" PRIx64 ++ " , %08" PRIx64 " , %08" PRIx64 " \n", ++ reinterpret_cast(FUNCTION_ADDR(target)), arg0, arg1, arg2, ++ arg3, arg4, arg5, arg6, arg7, arg8, arg9); ++ } ++ ObjectPair result = ++ target(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9); ++ set_register(a0, (int64_t)(result.x)); ++ set_register(a1, (int64_t)(result.y)); ++ } ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF("Returned %08" PRIx64 " : %08" PRIx64 " \n", get_register(a1), ++ get_register(a0)); ++ } ++ set_register(ra, saved_ra); ++ set_pc(get_register(ra)); ++ ++ } else if (func == 1) { // EBREAK ++ int32_t code = get_ebreak_code(instr_.instr()); ++ set_pc(get_pc() + kInstrSize * 2); ++ if (code != -1 && static_cast(code) <= kMaxStopCode) { ++ if (IsWatchpoint(code)) { ++ PrintWatchpoint(code); ++ } else { ++ IncreaseStopCounter(code); ++ HandleStop(code); ++ } ++ } else { ++ // All remaining break_ codes, and all traps are handled here. ++ RiscvDebugger dbg(this); ++ dbg.Debug(); ++ } ++ } else { ++ UNREACHABLE(); ++ } ++} ++ ++// Stop helper functions. ++bool Simulator::IsWatchpoint(uint64_t code) { ++ return (code <= kMaxWatchpointCode); ++} ++ ++void Simulator::PrintWatchpoint(uint64_t code) { ++ RiscvDebugger dbg(this); ++ ++break_count_; ++ PrintF("\n---- watchpoint %" PRId64 " marker: %3d (instr count: %8" PRId64 ++ " ) ----------" ++ "----------------------------------", ++ code, break_count_, icount_); ++ dbg.PrintAllRegs(); // Print registers and continue running. ++} ++ ++void Simulator::HandleStop(uint64_t code) { ++ // Stop if it is enabled, otherwise go on jumping over the stop ++ // and the message address. ++ if (IsEnabledStop(code)) { ++ RiscvDebugger dbg(this); ++ PrintF("Simulator hit stop (%" PRId64 ")\n", code); ++ dbg.Debug(); ++ } ++} ++ ++bool Simulator::IsStopInstruction(Instruction* instr) { ++ if (instr->InstructionBits() != kBreakInstr) return false; ++ int32_t code = get_ebreak_code(instr); ++ return code != -1 && static_cast(code) > kMaxWatchpointCode && ++ static_cast(code) <= kMaxStopCode; ++} ++ ++bool Simulator::IsEnabledStop(uint64_t code) { ++ DCHECK_LE(code, kMaxStopCode); ++ DCHECK_GT(code, kMaxWatchpointCode); ++ return !(watched_stops_[code].count & kStopDisabledBit); ++} ++ ++void Simulator::EnableStop(uint64_t code) { ++ if (!IsEnabledStop(code)) { ++ watched_stops_[code].count &= ~kStopDisabledBit; ++ } ++} ++ ++void Simulator::DisableStop(uint64_t code) { ++ if (IsEnabledStop(code)) { ++ watched_stops_[code].count |= kStopDisabledBit; ++ } ++} ++ ++void Simulator::IncreaseStopCounter(uint64_t code) { ++ DCHECK_LE(code, kMaxStopCode); ++ if ((watched_stops_[code].count & ~(1 << 31)) == 0x7FFFFFFF) { ++ PrintF("Stop counter for code %" PRId64 ++ " has overflowed.\n" ++ "Enabling this code and reseting the counter to 0.\n", ++ code); ++ watched_stops_[code].count = 0; ++ EnableStop(code); ++ } else { ++ watched_stops_[code].count++; ++ } ++} ++ ++// Print a stop status. ++void Simulator::PrintStopInfo(uint64_t code) { ++ if (code <= kMaxWatchpointCode) { ++ PrintF("That is a watchpoint, not a stop.\n"); ++ return; ++ } else if (code > kMaxStopCode) { ++ PrintF("Code too large, only %u stops can be used\n", kMaxStopCode + 1); ++ return; ++ } ++ const char* state = IsEnabledStop(code) ? "Enabled" : "Disabled"; ++ int32_t count = watched_stops_[code].count & ~kStopDisabledBit; ++ // Don't print the state of unused breakpoints. ++ if (count != 0) { ++ if (watched_stops_[code].desc) { ++ PrintF("stop %" PRId64 " - 0x%" PRIx64 " : \t%s, \tcounter = %i, \t%s\n", ++ code, code, state, count, watched_stops_[code].desc); ++ } else { ++ PrintF("stop %" PRId64 " - 0x%" PRIx64 " : \t%s, \tcounter = %i\n", code, ++ code, state, count); ++ } ++ } ++} ++ ++void Simulator::SignalException(Exception e) { ++ FATAL("Error: Exception %i raised.", static_cast(e)); ++} ++ ++// RISCV Instruction Decode Routine ++void Simulator::DecodeRVRType() { ++ switch (instr_.InstructionBits() & kRTypeMask) { ++ case RO_ADD: { ++ set_rd(sext_xlen(rs1() + rs2())); ++ break; ++ } ++ case RO_SUB: { ++ set_rd(sext_xlen(rs1() - rs2())); ++ break; ++ } ++ case RO_SLL: { ++ set_rd(sext_xlen(rs1() << (rs2() & (xlen - 1)))); ++ break; ++ } ++ case RO_SLT: { ++ set_rd(sreg_t(rs1()) < sreg_t(rs2())); ++ break; ++ } ++ case RO_SLTU: { ++ set_rd(reg_t(rs1()) < reg_t(rs2())); ++ break; ++ } ++ case RO_XOR: { ++ set_rd(rs1() ^ rs2()); ++ break; ++ } ++ case RO_SRL: { ++ set_rd(sext_xlen(zext_xlen(rs1()) >> (rs2() & (xlen - 1)))); ++ break; ++ } ++ case RO_SRA: { ++ set_rd(sext_xlen(sext_xlen(rs1()) >> (rs2() & (xlen - 1)))); ++ break; ++ } ++ case RO_OR: { ++ set_rd(rs1() | rs2()); ++ break; ++ } ++ case RO_AND: { ++ set_rd(rs1() & rs2()); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_ADDW: { ++ set_rd(sext32(rs1() + rs2())); ++ break; ++ } ++ case RO_SUBW: { ++ set_rd(sext32(rs1() - rs2())); ++ break; ++ } ++ case RO_SLLW: { ++ set_rd(sext32(rs1() << (rs2() & 0x1F))); ++ break; ++ } ++ case RO_SRLW: { ++ set_rd(sext32(uint32_t(rs1()) >> (rs2() & 0x1F))); ++ break; ++ } ++ case RO_SRAW: { ++ set_rd(sext32(int32_t(rs1()) >> (rs2() & 0x1F))); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ // TODO: Add RISCV M extension macro ++ case RO_MUL: { ++ set_rd(rs1() * rs2()); ++ break; ++ } ++ case RO_MULH: { ++ set_rd(mulh(rs1(), rs2())); ++ break; ++ } ++ case RO_MULHSU: { ++ set_rd(mulhsu(rs1(), rs2())); ++ break; ++ } ++ case RO_MULHU: { ++ set_rd(mulhu(rs1(), rs2())); ++ break; ++ } ++ case RO_DIV: { ++ sreg_t lhs = sext_xlen(rs1()); ++ sreg_t rhs = sext_xlen(rs2()); ++ if (rhs == 0) { ++ set_rd(-1); ++ } else if (lhs == INT64_MIN && rhs == -1) { ++ set_rd(lhs); ++ } else { ++ set_rd(sext_xlen(lhs / rhs)); ++ } ++ break; ++ } ++ case RO_DIVU: { ++ reg_t lhs = zext_xlen(rs1()); ++ reg_t rhs = zext_xlen(rs2()); ++ if (rhs == 0) { ++ set_rd(UINT64_MAX); ++ } else { ++ set_rd(zext_xlen(lhs / rhs)); ++ } ++ break; ++ } ++ case RO_REM: { ++ sreg_t lhs = sext_xlen(rs1()); ++ sreg_t rhs = sext_xlen(rs2()); ++ if (rhs == 0) { ++ set_rd(lhs); ++ } else if (lhs == INT64_MIN && rhs == -1) { ++ set_rd(0); ++ } else { ++ set_rd(sext_xlen(lhs % rhs)); ++ } ++ break; ++ } ++ case RO_REMU: { ++ reg_t lhs = zext_xlen(rs1()); ++ reg_t rhs = zext_xlen(rs2()); ++ if (rhs == 0) { ++ set_rd(lhs); ++ } else { ++ set_rd(zext_xlen(lhs % rhs)); ++ } ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_MULW: { ++ set_rd(sext32(sext32(rs1()) * sext32(rs2()))); ++ break; ++ } ++ case RO_DIVW: { ++ sreg_t lhs = sext32(rs1()); ++ sreg_t rhs = sext32(rs2()); ++ if (rhs == 0) { ++ set_rd(-1); ++ } else if (lhs == INT32_MIN && rhs == -1) { ++ set_rd(lhs); ++ } else { ++ set_rd(sext32(lhs / rhs)); ++ } ++ break; ++ } ++ case RO_DIVUW: { ++ reg_t lhs = zext32(rs1()); ++ reg_t rhs = zext32(rs2()); ++ if (rhs == 0) { ++ set_rd(UINT32_MAX); ++ } else { ++ set_rd(zext32(lhs / rhs)); ++ } ++ break; ++ } ++ case RO_REMW: { ++ sreg_t lhs = sext32(rs1()); ++ sreg_t rhs = sext32(rs2()); ++ if (rhs == 0) { ++ set_rd(lhs); ++ } else if (lhs == INT32_MIN && rhs == -1) { ++ set_rd(0); ++ } else { ++ set_rd(sext32(lhs % rhs)); ++ } ++ break; ++ } ++ case RO_REMUW: { ++ reg_t lhs = zext32(rs1()); ++ reg_t rhs = zext32(rs2()); ++ if (rhs == 0) { ++ set_rd(zext32(lhs)); ++ } else { ++ set_rd(zext32(lhs % rhs)); ++ } ++ break; ++ } ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: End Add RISCV M extension macro ++ default: { ++ switch (instr_.BaseOpcode()) { ++ case AMO: ++ DecodeRVRAType(); ++ break; ++ case OP_FP: ++ DecodeRVRFPType(); ++ break; ++ default: ++ UNSUPPORTED(); ++ } ++ } ++ } ++} ++ ++float Simulator::RoundF2FHelper(float input_val, int rmode) { ++ if (rmode == DYN) rmode = get_dynamic_rounding_mode(); ++ ++ float rounded = 0; ++ switch (rmode) { ++ case RNE: { // Round to Nearest, tiest to Even ++ int curr_mode = fegetround(); ++ fesetround(FE_TONEAREST); ++ rounded = std::nearbyintf(input_val); ++ fesetround(curr_mode); ++ break; ++ } ++ case RTZ: // Round towards Zero ++ rounded = std::truncf(input_val); ++ break; ++ case RDN: // Round Down (towards -infinity) ++ rounded = floorf(input_val); ++ break; ++ case RUP: // Round Up (towards +infinity) ++ rounded = ceilf(input_val); ++ break; ++ case RMM: // Round to Nearest, tiest to Max Magnitude ++ rounded = std::roundf(input_val); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ return rounded; ++} ++ ++double Simulator::RoundF2FHelper(double input_val, int rmode) { ++ if (rmode == DYN) rmode = get_dynamic_rounding_mode(); ++ ++ double rounded = 0; ++ switch (rmode) { ++ case RNE: { // Round to Nearest, tiest to Even ++ int curr_mode = fegetround(); ++ fesetround(FE_TONEAREST); ++ rounded = std::nearbyint(input_val); ++ fesetround(curr_mode); ++ break; ++ } ++ case RTZ: // Round towards Zero ++ rounded = std::trunc(input_val); ++ break; ++ case RDN: // Round Down (towards -infinity) ++ rounded = std::floor(input_val); ++ break; ++ case RUP: // Round Up (towards +infinity) ++ rounded = std::ceil(input_val); ++ break; ++ case RMM: // Round to Nearest, tiest to Max Magnitude ++ rounded = std::round(input_val); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ return rounded; ++} ++ ++// convert rounded floating-point to integer types, handle input values that ++// are out-of-range, underflow, or NaN, and set appropriate fflags ++template ++I_TYPE Simulator::RoundF2IHelper(F_TYPE original, int rmode) { ++ DCHECK(std::is_integral::value); ++ ++ DCHECK((std::is_same::value || ++ std::is_same::value)); ++ ++ I_TYPE max_i = std::numeric_limits::max(); ++ I_TYPE min_i = std::numeric_limits::min(); ++ ++ if (!std::isfinite(original)) { ++ set_fflags(kInvalidOperation); ++ if (std::isnan(original) || ++ original == std::numeric_limits::infinity()) { ++ return max_i; ++ } else { ++ DCHECK(original == -std::numeric_limits::infinity()); ++ return min_i; ++ } ++ } ++ ++ F_TYPE rounded = RoundF2FHelper(original, rmode); ++ if (original != rounded) set_fflags(kInexact); ++ ++ if (!std::isfinite(rounded)) { ++ set_fflags(kInvalidOperation); ++ if (std::isnan(rounded) || ++ rounded == std::numeric_limits::infinity()) { ++ return max_i; ++ } else { ++ DCHECK(rounded == -std::numeric_limits::infinity()); ++ return min_i; ++ } ++ } ++ ++ // FIXME (RISCV): comparison of rounded (float) and max_i (integer) may not ++ // be precise because max_i is promoted to floating point during comparison. ++ // Rounding up may happen when converting max_i to floating-point, e.g., ++ // max is 9223372036854775807 vs. (double)max is ++ // 9223372036854775808.00000000000000 ++ ++ // Since integer max values are either all 1s (for unsigned) or all 1s ++ // except for sign-bit (for signed), they cannot be represented precisely in ++ // floating point, in order to precisely tell whether the rounded floating ++ // point is within the max range, we compare against (max_i+1) which would ++ // have a single 1 w/ many trailing zeros ++ float max_i_plus_1 = ++ std::is_same::value ++ ? 0x1p64f // uint64_t::max + 1 cannot be represented in integers, ++ // so use its float representation directly ++ : static_cast(static_cast(max_i) + 1); ++ if (rounded >= max_i_plus_1) { ++ set_fflags(kOverflow | kInvalidOperation); ++ return max_i; ++ } ++ ++ // Since min_i (either 0 for unsigned, or for signed) is represented ++ // precisely in floating-point, comparing rounded directly against min_i ++ if (rounded <= min_i) { ++ if (rounded < min_i) set_fflags(kOverflow | kInvalidOperation); ++ return min_i; ++ } ++ ++ F_TYPE underflow_fval = ++ std::is_same::value ? FLT_MIN : DBL_MIN; ++ if (rounded < underflow_fval && rounded > -underflow_fval && rounded != 0) { ++ set_fflags(kUnderflow); ++ } ++ ++ return static_cast(rounded); ++} ++ ++template ++static int64_t FclassHelper(T value) { ++ switch (std::fpclassify(value)) { ++ case FP_INFINITE: ++ return (std::signbit(value) ? kNegativeInfinity : kPositiveInfinity); ++ case FP_NAN: ++ return (isSnan(value) ? kSignalingNaN : kQuietNaN); ++ case FP_NORMAL: ++ return (std::signbit(value) ? kNegativeNormalNumber ++ : kPositiveNormalNumber); ++ case FP_SUBNORMAL: ++ return (std::signbit(value) ? kNegativeSubnormalNumber ++ : kPositiveSubnormalNumber); ++ case FP_ZERO: ++ return (std::signbit(value) ? kNegativeZero : kPositiveZero); ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++template ++bool Simulator::CompareFHelper(T input1, T input2, FPUCondition cc) { ++ DCHECK(std::is_floating_point::value); ++ bool result = false; ++ switch (cc) { ++ case LT: ++ case LE: ++ // FLT, FLE are signaling compares ++ if (std::isnan(input1) || std::isnan(input2)) { ++ set_fflags(kInvalidOperation); ++ result = false; ++ } else { ++ result = (cc == LT) ? (input1 < input2) : (input1 <= input2); ++ } ++ break; ++ ++ case EQ: ++ if (std::numeric_limits::signaling_NaN() == input1 || ++ std::numeric_limits::signaling_NaN() == input2) { ++ set_fflags(kInvalidOperation); ++ } ++ if (std::isnan(input1) || std::isnan(input2)) { ++ result = false; ++ } else { ++ result = (input1 == input2); ++ } ++ break; ++ ++ default: ++ UNREACHABLE(); ++ } ++ return result; ++} ++ ++template ++static inline bool is_invalid_fmul(T src1, T src2) { ++ return (isinf(src1) && src2 == static_cast(0.0)) || ++ (src1 == static_cast(0.0) && isinf(src2)); ++} ++ ++template ++static inline bool is_invalid_fadd(T src1, T src2) { ++ return (isinf(src1) && isinf(src2) && ++ std::signbit(src1) != std::signbit(src2)); ++} ++ ++template ++static inline bool is_invalid_fsub(T src1, T src2) { ++ return (isinf(src1) && isinf(src2) && ++ std::signbit(src1) == std::signbit(src2)); ++} ++ ++template ++static inline bool is_invalid_fdiv(T src1, T src2) { ++ return ((src1 == 0 && src2 == 0) || (isinf(src1) && isinf(src2))); ++} ++ ++template ++static inline bool is_invalid_fsqrt(T src1) { ++ return (src1 < 0); ++} ++ ++void Simulator::DecodeRVRAType() { ++ // TODO: Add macro for RISCV A extension ++ // Special handling for A extension instructions because it uses func5 ++ // For all A extension instruction, V8 simulator is pure sequential. No ++ // Memory address lock or other synchronizaiton behaviors. ++ switch (instr_.InstructionBits() & kRATypeMask) { ++ case RO_LR_W: { ++ base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex); ++ int64_t addr = rs1(); ++ auto val = ReadMem(addr, instr_.instr()); ++ set_rd(sext32(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ local_monitor_.NotifyLoadLinked(addr, TransactionSize::Word); ++ GlobalMonitor::Get()->NotifyLoadLinked_Locked(addr, ++ &global_monitor_thread_); ++ break; ++ } ++ case RO_SC_W: { ++ int64_t addr = rs1(); ++ base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex); ++ if (local_monitor_.NotifyStoreConditional(addr, TransactionSize::Word) && ++ GlobalMonitor::Get()->NotifyStoreConditional_Locked( ++ addr, &global_monitor_thread_)) { ++ local_monitor_.NotifyStore(); ++ GlobalMonitor::Get()->NotifyStore_Locked(&global_monitor_thread_); ++ WriteMem(rs1(), (int32_t)rs2(), instr_.instr()); ++ set_rd(0, false); ++ } else { ++ set_rd(1, false); ++ } ++ break; ++ } ++ case RO_AMOSWAP_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return (uint32_t)rs2(); }, instr_.instr(), ++ WORD))); ++ break; ++ } ++ case RO_AMOADD_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return lhs + (uint32_t)rs2(); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOXOR_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return lhs ^ (uint32_t)rs2(); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOAND_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return lhs & (uint32_t)rs2(); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOOR_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return lhs | (uint32_t)rs2(); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOMIN_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](int32_t lhs) { return std::min(lhs, (int32_t)rs2()); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOMAX_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](int32_t lhs) { return std::max(lhs, (int32_t)rs2()); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOMINU_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return std::min(lhs, (uint32_t)rs2()); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++ case RO_AMOMAXU_W: { ++ set_rd(sext32(amo( ++ rs1(), [&](uint32_t lhs) { return std::max(lhs, (uint32_t)rs2()); }, ++ instr_.instr(), WORD))); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_LR_D: { ++ base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex); ++ int64_t addr = rs1(); ++ auto val = ReadMem(addr, instr_.instr()); ++ set_rd(val, false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ local_monitor_.NotifyLoadLinked(addr, TransactionSize::DoubleWord); ++ GlobalMonitor::Get()->NotifyLoadLinked_Locked(addr, ++ &global_monitor_thread_); ++ break; ++ } ++ case RO_SC_D: { ++ int64_t addr = rs1(); ++ base::MutexGuard lock_guard(&GlobalMonitor::Get()->mutex); ++ if (local_monitor_.NotifyStoreConditional(addr, ++ TransactionSize::DoubleWord) && ++ (GlobalMonitor::Get()->NotifyStoreConditional_Locked( ++ addr, &global_monitor_thread_))) { ++ GlobalMonitor::Get()->NotifyStore_Locked(&global_monitor_thread_); ++ WriteMem(rs1(), rs2(), instr_.instr()); ++ set_rd(0, false); ++ } else { ++ set_rd(1, false); ++ } ++ break; ++ } ++ case RO_AMOSWAP_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return rs2(); }, instr_.instr(), DWORD)); ++ break; ++ } ++ case RO_AMOADD_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return lhs + rs2(); }, instr_.instr(), ++ DWORD)); ++ break; ++ } ++ case RO_AMOXOR_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return lhs ^ rs2(); }, instr_.instr(), ++ DWORD)); ++ break; ++ } ++ case RO_AMOAND_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return lhs & rs2(); }, instr_.instr(), ++ DWORD)); ++ break; ++ } ++ case RO_AMOOR_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return lhs | rs2(); }, instr_.instr(), ++ DWORD)); ++ break; ++ } ++ case RO_AMOMIN_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return std::min(lhs, rs2()); }, ++ instr_.instr(), DWORD)); ++ break; ++ } ++ case RO_AMOMAX_D: { ++ set_rd(amo( ++ rs1(), [&](int64_t lhs) { return std::max(lhs, rs2()); }, ++ instr_.instr(), DWORD)); ++ break; ++ } ++ case RO_AMOMINU_D: { ++ set_rd(amo( ++ rs1(), [&](uint64_t lhs) { return std::min(lhs, (uint64_t)rs2()); }, ++ instr_.instr(), DWORD)); ++ break; ++ } ++ case RO_AMOMAXU_D: { ++ set_rd(amo( ++ rs1(), [&](uint64_t lhs) { return std::max(lhs, (uint64_t)rs2()); }, ++ instr_.instr(), DWORD)); ++ break; ++ } ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: End Add macro for RISCV A extension ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++} ++ ++void Simulator::DecodeRVRFPType() { ++ // OP_FP instructions (F/D) uses func7 first. Some further uses fun3 and ++ // rs2() ++ ++ // kRATypeMask is only for func7 ++ switch (instr_.InstructionBits() & kRFPTypeMask) { ++ // TODO: Add macro for RISCV F extension ++ case RO_FADD_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2) { ++ if (is_invalid_fadd(frs1, frs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return frs1 + frs2; ++ } ++ }; ++ set_frd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FSUB_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2) { ++ if (is_invalid_fsub(frs1, frs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return frs1 - frs2; ++ } ++ }; ++ set_frd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FMUL_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2) { ++ if (is_invalid_fmul(frs1, frs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return frs1 * frs2; ++ } ++ }; ++ set_frd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FDIV_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2) { ++ if (is_invalid_fdiv(frs1, frs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else if (frs2 == 0.0f) { ++ this->set_fflags(kDivideByZero); ++ return (std::signbit(frs1) == std::signbit(frs2) ++ ? std::numeric_limits::infinity() ++ : -std::numeric_limits::infinity()); ++ } else { ++ return frs1 / frs2; ++ } ++ }; ++ set_frd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FSQRT_S: { ++ if (instr_.Rs2Value() == 0b00000) { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs) { ++ if (is_invalid_fsqrt(frs)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::sqrt(frs); ++ } ++ }; ++ set_frd(CanonicalizeFPUOp1(fn)); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ case RO_FSGNJ_S: { // RO_FSGNJN_S RO_FSQNJX_S ++ switch (instr_.Funct3Value()) { ++ case 0b000: { // RO_FSGNJ_S ++ set_frd(fsgnj32(frs1(), frs2(), false, false)); ++ break; ++ } ++ case 0b001: { // RO_FSGNJN_S ++ set_frd(fsgnj32(frs1(), frs2(), true, false)); ++ break; ++ } ++ case 0b010: { // RO_FSQNJX_S ++ set_frd(fsgnj32(frs1(), frs2(), false, true)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FMIN_S: { // RO_FMAX_S ++ switch (instr_.Funct3Value()) { ++ case 0b000: { // RO_FMIN_S ++ set_frd(FMaxMinHelper(frs1(), frs2(), MaxMinKind::kMin)); ++ break; ++ } ++ case 0b001: { // RO_FMAX_S ++ set_frd(FMaxMinHelper(frs1(), frs2(), MaxMinKind::kMax)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FCVT_W_S: { // RO_FCVT_WU_S , 64F RO_FCVT_L_S RO_FCVT_LU_S ++ float original_val = frs1(); ++ switch (instr_.Rs2Value()) { ++ case 0b00000: { // RO_FCVT_W_S ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++ case 0b00001: { // RO_FCVT_WU_S ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: { // RO_FCVT_L_S ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++ case 0b00011: { // RO_FCVT_LU_S ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FMV: { // RO_FCLASS_S ++ switch (instr_.Funct3Value()) { ++ case 0b000: { ++ if (instr_.Rs2Value() == 0b00000) { ++ // RO_FMV_X_W ++ set_rd(sext_xlen(get_fpu_register_word(rs1_reg()))); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ case 0b001: { // RO_FCLASS_S ++ set_rd(FclassHelper(frs1())); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ // FIXME (RISCV): implement handling of NaN (quiet and signalling) ++ case RO_FLE_S: { // RO_FEQ_S RO_FLT_S RO_FLE_S ++ switch (instr_.Funct3Value()) { ++ case 0b010: { // RO_FEQ_S ++ set_rd(CompareFHelper(frs1(), frs2(), EQ)); ++ break; ++ } ++ case 0b001: { // RO_FLT_S ++ set_rd(CompareFHelper(frs1(), frs2(), LT)); ++ break; ++ } ++ case 0b000: { // RO_FLE_S ++ set_rd(CompareFHelper(frs1(), frs2(), LE)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FCVT_S_W: { // RO_FCVT_S_WU , 64F RO_FCVT_S_L RO_FCVT_S_LU ++ switch (instr_.Rs2Value()) { ++ case 0b00000: { // RO_FCVT_S_W ++ set_frd((float)(int32_t)rs1()); ++ break; ++ } ++ case 0b00001: { // RO_FCVT_S_WU ++ set_frd((float)(uint32_t)rs1()); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: { // RO_FCVT_S_L ++ set_frd((float)(int64_t)rs1()); ++ break; ++ } ++ case 0b00011: { // RO_FCVT_S_LU ++ set_frd((float)(uint64_t)rs1()); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FMV_W_X: { ++ if (instr_.Funct3Value() == 0b000) { ++ // since FMV preserves source bit-pattern, no need to canonize ++ set_frd(bit_cast((uint32_t)rs1())); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ // TODO: Add macro for RISCV D extension ++ case RO_FADD_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2) { ++ if (is_invalid_fadd(drs1, drs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return drs1 + drs2; ++ } ++ }; ++ set_drd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FSUB_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2) { ++ if (is_invalid_fsub(drs1, drs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return drs1 - drs2; ++ } ++ }; ++ set_drd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FMUL_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2) { ++ if (is_invalid_fmul(drs1, drs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return drs1 * drs2; ++ } ++ }; ++ set_drd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FDIV_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2) { ++ if (is_invalid_fdiv(drs1, drs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else if (drs2 == 0.0) { ++ this->set_fflags(kDivideByZero); ++ return (std::signbit(drs1) == std::signbit(drs2) ++ ? std::numeric_limits::infinity() ++ : -std::numeric_limits::infinity()); ++ } else { ++ return drs1 / drs2; ++ } ++ }; ++ set_drd(CanonicalizeFPUOp2(fn)); ++ break; ++ } ++ case RO_FSQRT_D: { ++ if (instr_.Rs2Value() == 0b00000) { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs) { ++ if (is_invalid_fsqrt(drs)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::sqrt(drs); ++ } ++ }; ++ set_drd(CanonicalizeFPUOp1(fn)); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ case RO_FSGNJ_D: { // RO_FSGNJN_D RO_FSQNJX_D ++ switch (instr_.Funct3Value()) { ++ case 0b000: { // RO_FSGNJ_D ++ set_drd(fsgnj64(drs1(), drs2(), false, false)); ++ break; ++ } ++ case 0b001: { // RO_FSGNJN_D ++ set_drd(fsgnj64(drs1(), drs2(), true, false)); ++ break; ++ } ++ case 0b010: { // RO_FSQNJX_D ++ set_drd(fsgnj64(drs1(), drs2(), false, true)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FMIN_D: { // RO_FMAX_D ++ switch (instr_.Funct3Value()) { ++ case 0b000: { // RO_FMIN_D ++ set_drd(FMaxMinHelper(drs1(), drs2(), MaxMinKind::kMin)); ++ break; ++ } ++ case 0b001: { // RO_FMAX_D ++ set_drd(FMaxMinHelper(drs1(), drs2(), MaxMinKind::kMax)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case (RO_FCVT_S_D & kRFPTypeMask): { ++ if (instr_.Rs2Value() == 0b00001) { ++ auto fn = [](double drs) { return (float)drs; }; ++ set_frd(CanonicalizeDoubleToFloatOperation(fn)); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ case RO_FCVT_D_S: { ++ if (instr_.Rs2Value() == 0b00000) { ++ auto fn = [](float frs) { return (double)frs; }; ++ set_drd(CanonicalizeFloatToDoubleOperation(fn)); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ case RO_FLE_D: { // RO_FEQ_D RO_FLT_D RO_FLE_D ++ switch (instr_.Funct3Value()) { ++ case 0b010: { // RO_FEQ_S ++ set_rd(CompareFHelper(drs1(), drs2(), EQ)); ++ break; ++ } ++ case 0b001: { // RO_FLT_D ++ set_rd(CompareFHelper(drs1(), drs2(), LT)); ++ break; ++ } ++ case 0b000: { // RO_FLE_D ++ set_rd(CompareFHelper(drs1(), drs2(), LE)); ++ break; ++ } ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case (RO_FCLASS_D & kRFPTypeMask): { // RO_FCLASS_D , 64D RO_FMV_X_D ++ if (instr_.Rs2Value() != 0b00000) { ++ UNSUPPORTED(); ++ break; ++ } ++ switch (instr_.Funct3Value()) { ++ case 0b001: { // RO_FCLASS_D ++ set_rd(FclassHelper(drs1())); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b000: { // RO_FMV_X_D ++ set_rd(bit_cast(drs1())); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FCVT_W_D: { // RO_FCVT_WU_D , 64F RO_FCVT_L_D RO_FCVT_LU_D ++ double original_val = drs1(); ++ switch (instr_.Rs2Value()) { ++ case 0b00000: { // RO_FCVT_W_D ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++ case 0b00001: { // RO_FCVT_WU_D ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: { // RO_FCVT_L_D ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++ case 0b00011: { // RO_FCVT_LU_D ++ set_rd(RoundF2IHelper(original_val, instr_.RoundMode())); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++ case RO_FCVT_D_W: { // RO_FCVT_D_WU , 64F RO_FCVT_D_L RO_FCVT_D_LU ++ switch (instr_.Rs2Value()) { ++ case 0b00000: { // RO_FCVT_D_W ++ set_drd((int32_t)rs1()); ++ break; ++ } ++ case 0b00001: { // RO_FCVT_D_WU ++ set_drd((uint32_t)rs1()); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case 0b00010: { // RO_FCVT_D_L ++ set_drd((int64_t)rs1()); ++ break; ++ } ++ case 0b00011: { // RO_FCVT_D_LU ++ set_drd((uint64_t)rs1()); ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_FMV_D_X: { ++ if (instr_.Funct3Value() == 0b000 && instr_.Rs2Value() == 0b00000) { ++ // Since FMV preserves source bit-pattern, no need to canonize ++ set_drd(bit_cast(rs1())); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++#endif /* V8_TARGET_ARCH_64_BIT */ ++ default: { ++ UNSUPPORTED(); ++ } ++ } ++} ++ ++void Simulator::DecodeRVR4Type() { ++ switch (instr_.InstructionBits() & kR4TypeMask) { ++ // TODO: use F Extension macro block ++ case RO_FMADD_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2, float frs3) { ++ if (is_invalid_fmul(frs1, frs2) || is_invalid_fadd(frs1 * frs2, frs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::fma(frs1, frs2, frs3); ++ } ++ }; ++ set_frd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FMSUB_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2, float frs3) { ++ if (is_invalid_fmul(frs1, frs2) || is_invalid_fsub(frs1 * frs2, frs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::fma(frs1, frs2, -frs3); ++ } ++ }; ++ set_frd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FNMSUB_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2, float frs3) { ++ if (is_invalid_fmul(frs1, frs2) || is_invalid_fsub(frs3, frs1 * frs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return -std::fma(frs1, frs2, -frs3); ++ } ++ }; ++ set_frd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FNMADD_S: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](float frs1, float frs2, float frs3) { ++ if (is_invalid_fmul(frs1, frs2) || is_invalid_fadd(frs1 * frs2, frs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return -std::fma(frs1, frs2, frs3); ++ } ++ }; ++ set_frd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ // TODO: use F Extension macro block ++ case RO_FMADD_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2, double drs3) { ++ if (is_invalid_fmul(drs1, drs2) || is_invalid_fadd(drs1 * drs2, drs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::fma(drs1, drs2, drs3); ++ } ++ }; ++ set_drd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FMSUB_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2, double drs3) { ++ if (is_invalid_fmul(drs1, drs2) || is_invalid_fsub(drs1 * drs2, drs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return std::fma(drs1, drs2, -drs3); ++ } ++ }; ++ set_drd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FNMSUB_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2, double drs3) { ++ if (is_invalid_fmul(drs1, drs2) || is_invalid_fsub(drs3, drs1 * drs2)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return -std::fma(drs1, drs2, -drs3); ++ } ++ }; ++ set_drd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ case RO_FNMADD_D: { ++ // TODO: use rm value (round mode) ++ auto fn = [this](double drs1, double drs2, double drs3) { ++ if (is_invalid_fmul(drs1, drs2) || is_invalid_fadd(drs1 * drs2, drs3)) { ++ this->set_fflags(kInvalidOperation); ++ return std::numeric_limits::quiet_NaN(); ++ } else { ++ return -std::fma(drs1, drs2, drs3); ++ } ++ }; ++ set_drd(CanonicalizeFPUOp3(fn)); ++ break; ++ } ++ default: ++ UNSUPPORTED(); ++ } ++} ++ ++void Simulator::DecodeRVIType() { ++ switch (instr_.InstructionBits() & kITypeMask) { ++ case RO_JALR: { ++ set_rd(get_pc() + kInstrSize); ++ // Note: No need to shift 2 for JALR's imm12, but set lowest bit to 0. ++ int64_t next_pc = (rs1() + imm12()) & ~reg_t(1); ++ set_pc(next_pc); ++ break; ++ } ++ case RO_LB: { ++ int64_t addr = rs1() + imm12(); ++ int8_t val = ReadMem(addr, instr_.instr()); ++ set_rd(sext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++ case RO_LH: { ++ int64_t addr = rs1() + imm12(); ++ int16_t val = ReadMem(addr, instr_.instr()); ++ set_rd(sext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++ case RO_LW: { ++ int64_t addr = rs1() + imm12(); ++ int32_t val = ReadMem(addr, instr_.instr()); ++ set_rd(sext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++ case RO_LBU: { ++ int64_t addr = rs1() + imm12(); ++ uint8_t val = ReadMem(addr, instr_.instr()); ++ set_rd(zext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++ case RO_LHU: { ++ int64_t addr = rs1() + imm12(); ++ uint16_t val = ReadMem(addr, instr_.instr()); ++ set_rd(zext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_LWU: { ++ int64_t addr = rs1() + imm12(); ++ uint32_t val = ReadMem(addr, instr_.instr()); ++ set_rd(zext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++ case RO_LD: { ++ int64_t addr = rs1() + imm12(); ++ int64_t val = ReadMem(addr, instr_.instr()); ++ set_rd(sext_xlen(val), false); ++ TraceMemRd(addr, val, get_register(rd_reg())); ++ break; ++ } ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ case RO_ADDI: { ++ set_rd(sext_xlen(rs1() + imm12())); ++ break; ++ } ++ case RO_SLTI: { ++ set_rd(sreg_t(rs1()) < sreg_t(imm12())); ++ break; ++ } ++ case RO_SLTIU: { ++ set_rd(reg_t(rs1()) < reg_t(imm12())); ++ break; ++ } ++ case RO_XORI: { ++ set_rd(imm12() ^ rs1()); ++ break; ++ } ++ case RO_ORI: { ++ set_rd(imm12() | rs1()); ++ break; ++ } ++ case RO_ANDI: { ++ set_rd(imm12() & rs1()); ++ break; ++ } ++ case RO_SLLI: { ++ require(shamt() < xlen); ++ set_rd(sext_xlen(rs1() << shamt())); ++ break; ++ } ++ case RO_SRLI: { // RO_SRAI ++ if (!instr_.IsArithShift()) { ++ require(shamt() < xlen); ++ set_rd(sext_xlen(zext_xlen(rs1()) >> shamt())); ++ } else { ++ require(shamt() < xlen); ++ set_rd(sext_xlen(sext_xlen(rs1()) >> shamt())); ++ } ++ break; ++ } ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_ADDIW: { ++ set_rd(sext32(rs1() + imm12())); ++ break; ++ } ++ case RO_SLLIW: { ++ set_rd(sext32(rs1() << shamt32())); ++ break; ++ } ++ case RO_SRLIW: { // RO_SRAIW ++ if (!instr_.IsArithShift()) { ++ set_rd(sext32(uint32_t(rs1()) >> shamt32())); ++ } else { ++ set_rd(sext32(int32_t(rs1()) >> shamt32())); ++ } ++ break; ++ } ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ case RO_FENCE: { ++ // DO nothing in sumulator ++ break; ++ } ++ case RO_ECALL: { // RO_EBREAK ++ if (instr_.Imm12Value() == 0) { // ECALL ++ SoftwareInterrupt(); ++ } else if (instr_.Imm12Value() == 1) { // EBREAK ++ SoftwareInterrupt(); ++ } else { ++ UNSUPPORTED(); ++ } ++ break; ++ } ++ // TODO: use Zifencei Standard Extension macro block ++ case RO_FENCE_I: { ++ // spike: flush icache. ++ break; ++ } ++ // TODO: use Zicsr Standard Extension macro block ++ case RO_CSRRW: { ++ if (rd_reg() != zero_reg) { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ } ++ write_csr_value(csr_reg(), rs1()); ++ break; ++ } ++ case RO_CSRRS: { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ if (rs1_reg() != zero_reg) { ++ set_csr_bits(csr_reg(), rs1()); ++ } ++ break; ++ } ++ case RO_CSRRC: { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ if (rs1_reg() != zero_reg) { ++ clear_csr_bits(csr_reg(), rs1()); ++ } ++ break; ++ } ++ case RO_CSRRWI: { ++ if (rd_reg() != zero_reg) { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ } ++ write_csr_value(csr_reg(), imm5CSR()); ++ break; ++ } ++ case RO_CSRRSI: { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ if (imm5CSR() != 0) { ++ set_csr_bits(csr_reg(), imm5CSR()); ++ } ++ break; ++ } ++ case RO_CSRRCI: { ++ set_rd(zext_xlen(read_csr_value(csr_reg()))); ++ if (imm5CSR() != 0) { ++ clear_csr_bits(csr_reg(), imm5CSR()); ++ } ++ break; ++ } ++ // TODO: use F Extension macro block ++ case RO_FLW: { ++ int64_t addr = rs1() + imm12(); ++ float val = ReadMem(addr, instr_.instr()); ++ set_frd(val, false); ++ TraceMemRd(addr, val, get_fpu_register(frd_reg())); ++ break; ++ } ++ // TODO: use D Extension macro block ++ case RO_FLD: { ++ int64_t addr = rs1() + imm12(); ++ double val = ReadMem(addr, instr_.instr()); ++ set_drd(val, false); ++ TraceMemRd(addr, val, get_fpu_register(frd_reg())); ++ break; ++ } ++ default: ++ UNSUPPORTED(); ++ } ++} ++ ++void Simulator::DecodeRVSType() { ++ switch (instr_.InstructionBits() & kSTypeMask) { ++ case RO_SB: ++ WriteMem(rs1() + s_imm12(), (uint8_t)rs2(), instr_.instr()); ++ break; ++ case RO_SH: ++ WriteMem(rs1() + s_imm12(), (uint16_t)rs2(), instr_.instr()); ++ break; ++ case RO_SW: ++ WriteMem(rs1() + s_imm12(), (uint32_t)rs2(), instr_.instr()); ++ break; ++#ifdef V8_TARGET_ARCH_64_BIT ++ case RO_SD: ++ WriteMem(rs1() + s_imm12(), (uint64_t)rs2(), instr_.instr()); ++ break; ++#endif /*V8_TARGET_ARCH_64_BIT*/ ++ // TODO: use F Extension macro block ++ case RO_FSW: { ++ WriteMem(rs1() + s_imm12(), ++ (uint32_t)get_fpu_register_word(rs2_reg()), ++ instr_.instr()); ++ break; ++ } ++ // TODO: use D Extension macro block ++ case RO_FSD: { ++ WriteMem(rs1() + s_imm12(), drs2(), instr_.instr()); ++ break; ++ } ++ default: ++ UNSUPPORTED(); ++ } ++} ++ ++void Simulator::DecodeRVBType() { ++ switch (instr_.InstructionBits() & kBTypeMask) { ++ case RO_BEQ: ++ if (rs1() == rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ case RO_BNE: ++ if (rs1() != rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ case RO_BLT: ++ if (rs1() < rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ case RO_BGE: ++ if (rs1() >= rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ case RO_BLTU: ++ if ((reg_t)rs1() < (reg_t)rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ case RO_BGEU: ++ if ((reg_t)rs1() >= (reg_t)rs2()) { ++ int64_t next_pc = get_pc() + boffset(); ++ set_pc(next_pc); ++ } ++ break; ++ default: ++ UNSUPPORTED(); ++ } ++} ++void Simulator::DecodeRVUType() { ++ // U Type doesn't have additoinal mask ++ switch (instr_.BaseOpcodeFieldRaw()) { ++ case RO_LUI: ++ set_rd(u_imm()); ++ break; ++ case RO_AUIPC: ++ set_rd(sext_xlen(u_imm() + get_pc())); ++ break; ++ default: ++ UNSUPPORTED(); ++ } ++} ++void Simulator::DecodeRVJType() { ++ // J Type doesn't have additional mask ++ switch (instr_.BaseOpcodeValue()) { ++ case RO_JAL: { ++ set_rd(get_pc() + kInstrSize); ++ int64_t next_pc = get_pc() + imm20J(); ++ set_pc(next_pc); ++ break; ++ } ++ default: ++ UNSUPPORTED(); ++ } ++} ++ ++// Executes the current instruction. ++void Simulator::InstructionDecode(Instruction* instr) { ++ if (v8::internal::FLAG_check_icache) { ++ CheckICache(i_cache(), instr); ++ } ++ pc_modified_ = false; ++ ++ v8::internal::EmbeddedVector buffer; ++ ++ if (::v8::internal::FLAG_trace_sim) { ++ SNPrintF(trace_buf_, " "); ++ disasm::NameConverter converter; ++ disasm::Disassembler dasm(converter); ++ // Use a reasonably large buffer. ++ dasm.InstructionDecode(buffer, reinterpret_cast(instr)); ++ ++ // PrintF("EXECUTING 0x%08" PRIxPTR " %-44s\n", ++ // reinterpret_cast(instr), buffer.begin()); ++ } ++ ++ instr_ = instr; ++ switch (instr_.InstructionType()) { ++ case Instruction::kRType: ++ DecodeRVRType(); ++ break; ++ case Instruction::kR4Type: ++ DecodeRVR4Type(); ++ break; ++ case Instruction::kIType: ++ DecodeRVIType(); ++ break; ++ case Instruction::kSType: ++ DecodeRVSType(); ++ break; ++ case Instruction::kBType: ++ DecodeRVBType(); ++ break; ++ case Instruction::kUType: ++ DecodeRVUType(); ++ break; ++ case Instruction::kJType: ++ DecodeRVJType(); ++ break; ++ default: ++ if (::v8::internal::FLAG_trace_sim) { ++ std::cout << "Unrecognized instruction [@pc=0x" << std::hex ++ << registers_[pc] << "]: 0x" << instr->InstructionBits() ++ << std::endl; ++ } ++ UNSUPPORTED(); ++ } ++ ++ if (::v8::internal::FLAG_trace_sim) { ++ PrintF(" 0x%012" PRIxPTR " %-44s %s\n", ++ reinterpret_cast(instr), buffer.begin(), ++ trace_buf_.begin()); ++ } ++ ++ if (!pc_modified_) { ++ set_register(pc, reinterpret_cast(instr) + kInstrSize); ++ } ++} ++ ++void Simulator::Execute() { ++ // Get the PC to simulate. Cannot use the accessor here as we need the ++ // raw PC value and not the one used as input to arithmetic instructions. ++ int64_t program_counter = get_pc(); ++ while (program_counter != end_sim_pc) { ++ Instruction* instr = reinterpret_cast(program_counter); ++ icount_++; ++ if (icount_ == static_cast(::v8::internal::FLAG_stop_sim_at)) { ++ RiscvDebugger dbg(this); ++ dbg.Debug(); ++ } else { ++ InstructionDecode(instr); ++ } ++ CheckBreakpoints(); ++ program_counter = get_pc(); ++ } ++} ++ ++void Simulator::CallInternal(Address entry) { ++ // Adjust JS-based stack limit to C-based stack limit. ++ isolate_->stack_guard()->AdjustStackLimitForSimulator(); ++ ++ // Prepare to execute the code at entry. ++ set_register(pc, static_cast(entry)); ++ // Put down marker for end of simulation. The simulator will stop simulation ++ // when the PC reaches this value. By saving the "end simulation" value into ++ // the LR the simulation stops when returning to this call point. ++ set_register(ra, end_sim_pc); ++ ++ // Remember the values of callee-saved registers. ++ // The code below assumes that r9 is not used as sb (static base) in ++ // simulator code and therefore is regarded as a callee-saved register. ++ int64_t s0_val = get_register(s0); ++ int64_t s1_val = get_register(s1); ++ int64_t s2_val = get_register(s2); ++ int64_t s3_val = get_register(s3); ++ int64_t s4_val = get_register(s4); ++ int64_t s5_val = get_register(s5); ++ int64_t s6_val = get_register(s6); ++ int64_t s7_val = get_register(s7); ++ int64_t gp_val = get_register(gp); ++ int64_t sp_val = get_register(sp); ++ int64_t fp_val = get_register(fp); ++ ++ // Set up the callee-saved registers with a known value. To be able to check ++ // that they are preserved properly across JS execution. ++ int64_t callee_saved_value = icount_; ++ set_register(s0, callee_saved_value); ++ set_register(s1, callee_saved_value); ++ set_register(s2, callee_saved_value); ++ set_register(s3, callee_saved_value); ++ set_register(s4, callee_saved_value); ++ set_register(s5, callee_saved_value); ++ set_register(s6, callee_saved_value); ++ set_register(s7, callee_saved_value); ++ set_register(gp, callee_saved_value); ++ set_register(fp, callee_saved_value); ++ ++ // Start the simulation. ++ Execute(); ++ ++ // Check that the callee-saved registers have been preserved. ++ CHECK_EQ(callee_saved_value, get_register(s0)); ++ CHECK_EQ(callee_saved_value, get_register(s1)); ++ CHECK_EQ(callee_saved_value, get_register(s2)); ++ CHECK_EQ(callee_saved_value, get_register(s3)); ++ CHECK_EQ(callee_saved_value, get_register(s4)); ++ CHECK_EQ(callee_saved_value, get_register(s5)); ++ CHECK_EQ(callee_saved_value, get_register(s6)); ++ CHECK_EQ(callee_saved_value, get_register(s7)); ++ CHECK_EQ(callee_saved_value, get_register(gp)); ++ CHECK_EQ(callee_saved_value, get_register(fp)); ++ ++ // Restore callee-saved registers with the original value. ++ set_register(s0, s0_val); ++ set_register(s1, s1_val); ++ set_register(s2, s2_val); ++ set_register(s3, s3_val); ++ set_register(s4, s4_val); ++ set_register(s5, s5_val); ++ set_register(s6, s6_val); ++ set_register(s7, s7_val); ++ set_register(gp, gp_val); ++ set_register(sp, sp_val); ++ set_register(fp, fp_val); ++} ++ ++intptr_t Simulator::CallImpl(Address entry, int argument_count, ++ const intptr_t* arguments) { ++ constexpr int kRegisterPassedArguments = 8; ++ // Set up arguments. ++ ++ // First four arguments passed in registers in both ABI's. ++ int reg_arg_count = std::min(kRegisterPassedArguments, argument_count); ++ if (reg_arg_count > 0) set_register(a0, arguments[0]); ++ if (reg_arg_count > 1) set_register(a1, arguments[1]); ++ if (reg_arg_count > 2) set_register(a2, arguments[2]); ++ if (reg_arg_count > 3) set_register(a3, arguments[3]); ++ ++ // Up to eight arguments passed in registers in N64 ABI. ++ // TODO(plind): N64 ABI calls these regs a4 - a7. Clarify this. ++ if (reg_arg_count > 4) set_register(a4, arguments[4]); ++ if (reg_arg_count > 5) set_register(a5, arguments[5]); ++ if (reg_arg_count > 6) set_register(a6, arguments[6]); ++ if (reg_arg_count > 7) set_register(a7, arguments[7]); ++ ++ if (::v8::internal::FLAG_trace_sim) { ++ std::cout << "CallImpl: reg_arg_count = " << reg_arg_count << std::hex ++ << " entry-pc (JSEntry) = 0x" << entry << " a0 (Isolate) = 0x" ++ << get_register(a0) << " a1 (orig_func/new_target) = 0x" ++ << get_register(a1) << " a2 (func/target) = 0x" ++ << get_register(a2) << " a3 (receiver) = 0x" << get_register(a3) ++ << " a4 (argc) = 0x" << get_register(a4) << " a5 (argv) = 0x" ++ << get_register(a5) << std::endl; ++ } ++ ++ // Remaining arguments passed on stack. ++ int64_t original_stack = get_register(sp); ++ // Compute position of stack on entry to generated code. ++ int stack_args_count = argument_count - reg_arg_count; ++ int stack_args_size = stack_args_count * sizeof(*arguments) + kCArgsSlotsSize; ++ int64_t entry_stack = original_stack - stack_args_size; ++ ++ if (base::OS::ActivationFrameAlignment() != 0) { ++ entry_stack &= -base::OS::ActivationFrameAlignment(); ++ } ++ // Store remaining arguments on stack, from low to high memory. ++ intptr_t* stack_argument = reinterpret_cast(entry_stack); ++ memcpy(stack_argument + kCArgSlotCount, arguments + reg_arg_count, ++ stack_args_count * sizeof(*arguments)); ++ set_register(sp, entry_stack); ++ ++ CallInternal(entry); ++ ++ // Pop stack passed arguments. ++ CHECK_EQ(entry_stack, get_register(sp)); ++ set_register(sp, original_stack); ++ ++ // return get_register(a0); ++ // RISCV uses a0 to return result ++ return get_register(a0); ++} ++ ++double Simulator::CallFP(Address entry, double d0, double d1) { ++ set_fpu_register_double(fa0, d0); ++ set_fpu_register_double(fa1, d1); ++ CallInternal(entry); ++ return get_fpu_register_double(fa0); ++} ++ ++uintptr_t Simulator::PushAddress(uintptr_t address) { ++ int64_t new_sp = get_register(sp) - sizeof(uintptr_t); ++ uintptr_t* stack_slot = reinterpret_cast(new_sp); ++ *stack_slot = address; ++ set_register(sp, new_sp); ++ return new_sp; ++} ++ ++uintptr_t Simulator::PopAddress() { ++ int64_t current_sp = get_register(sp); ++ uintptr_t* stack_slot = reinterpret_cast(current_sp); ++ uintptr_t address = *stack_slot; ++ set_register(sp, current_sp + sizeof(uintptr_t)); ++ return address; ++} ++ ++Simulator::LocalMonitor::LocalMonitor() ++ : access_state_(MonitorAccess::Open), ++ tagged_addr_(0), ++ size_(TransactionSize::None) {} ++ ++void Simulator::LocalMonitor::Clear() { ++ access_state_ = MonitorAccess::Open; ++ tagged_addr_ = 0; ++ size_ = TransactionSize::None; ++} ++ ++void Simulator::LocalMonitor::NotifyLoad() { ++ if (access_state_ == MonitorAccess::RMW) { ++ // A non linked load could clear the local monitor. As a result, it's ++ // most strict to unconditionally clear the local monitor on load. ++ Clear(); ++ } ++} ++ ++void Simulator::LocalMonitor::NotifyLoadLinked(uintptr_t addr, ++ TransactionSize size) { ++ access_state_ = MonitorAccess::RMW; ++ tagged_addr_ = addr; ++ size_ = size; ++} ++ ++void Simulator::LocalMonitor::NotifyStore() { ++ if (access_state_ == MonitorAccess::RMW) { ++ // A non exclusive store could clear the local monitor. As a result, it's ++ // most strict to unconditionally clear the local monitor on store. ++ Clear(); ++ } ++} ++ ++bool Simulator::LocalMonitor::NotifyStoreConditional(uintptr_t addr, ++ TransactionSize size) { ++ if (access_state_ == MonitorAccess::RMW) { ++ if (addr == tagged_addr_ && size_ == size) { ++ Clear(); ++ return true; ++ } else { ++ return false; ++ } ++ } else { ++ DCHECK(access_state_ == MonitorAccess::Open); ++ return false; ++ } ++} ++ ++Simulator::GlobalMonitor::LinkedAddress::LinkedAddress() ++ : access_state_(MonitorAccess::Open), ++ tagged_addr_(0), ++ next_(nullptr), ++ prev_(nullptr), ++ failure_counter_(0) {} ++ ++void Simulator::GlobalMonitor::LinkedAddress::Clear_Locked() { ++ access_state_ = MonitorAccess::Open; ++ tagged_addr_ = 0; ++} ++ ++void Simulator::GlobalMonitor::LinkedAddress::NotifyLoadLinked_Locked( ++ uintptr_t addr) { ++ access_state_ = MonitorAccess::RMW; ++ tagged_addr_ = addr; ++} ++ ++void Simulator::GlobalMonitor::LinkedAddress::NotifyStore_Locked() { ++ if (access_state_ == MonitorAccess::RMW) { ++ // A non exclusive store could clear the global monitor. As a result, it's ++ // most strict to unconditionally clear global monitors on store. ++ Clear_Locked(); ++ } ++} ++ ++bool Simulator::GlobalMonitor::LinkedAddress::NotifyStoreConditional_Locked( ++ uintptr_t addr, bool is_requesting_thread) { ++ if (access_state_ == MonitorAccess::RMW) { ++ if (is_requesting_thread) { ++ if (addr == tagged_addr_) { ++ Clear_Locked(); ++ // Introduce occasional sc/scd failures. This is to simulate the ++ // behavior of hardware, which can randomly fail due to background ++ // cache evictions. ++ if (failure_counter_++ >= kMaxFailureCounter) { ++ failure_counter_ = 0; ++ return false; ++ } else { ++ return true; ++ } ++ } ++ } else if ((addr & kExclusiveTaggedAddrMask) == ++ (tagged_addr_ & kExclusiveTaggedAddrMask)) { ++ // Check the masked addresses when responding to a successful lock by ++ // another thread so the implementation is more conservative (i.e. the ++ // granularity of locking is as large as possible.) ++ Clear_Locked(); ++ return false; ++ } ++ } ++ return false; ++} ++ ++void Simulator::GlobalMonitor::NotifyLoadLinked_Locked( ++ uintptr_t addr, LinkedAddress* linked_address) { ++ linked_address->NotifyLoadLinked_Locked(addr); ++ PrependProcessor_Locked(linked_address); ++} ++ ++void Simulator::GlobalMonitor::NotifyStore_Locked( ++ LinkedAddress* linked_address) { ++ // Notify each thread of the store operation. ++ for (LinkedAddress* iter = head_; iter; iter = iter->next_) { ++ iter->NotifyStore_Locked(); ++ } ++} ++ ++bool Simulator::GlobalMonitor::NotifyStoreConditional_Locked( ++ uintptr_t addr, LinkedAddress* linked_address) { ++ DCHECK(IsProcessorInLinkedList_Locked(linked_address)); ++ if (linked_address->NotifyStoreConditional_Locked(addr, true)) { ++ // Notify the other processors that this StoreConditional succeeded. ++ for (LinkedAddress* iter = head_; iter; iter = iter->next_) { ++ if (iter != linked_address) { ++ iter->NotifyStoreConditional_Locked(addr, false); ++ } ++ } ++ return true; ++ } else { ++ return false; ++ } ++} ++ ++bool Simulator::GlobalMonitor::IsProcessorInLinkedList_Locked( ++ LinkedAddress* linked_address) const { ++ return head_ == linked_address || linked_address->next_ || ++ linked_address->prev_; ++} ++ ++void Simulator::GlobalMonitor::PrependProcessor_Locked( ++ LinkedAddress* linked_address) { ++ if (IsProcessorInLinkedList_Locked(linked_address)) { ++ return; ++ } ++ ++ if (head_) { ++ head_->prev_ = linked_address; ++ } ++ linked_address->prev_ = nullptr; ++ linked_address->next_ = head_; ++ head_ = linked_address; ++} ++ ++void Simulator::GlobalMonitor::RemoveLinkedAddress( ++ LinkedAddress* linked_address) { ++ base::MutexGuard lock_guard(&mutex); ++ if (!IsProcessorInLinkedList_Locked(linked_address)) { ++ return; ++ } ++ ++ if (linked_address->prev_) { ++ linked_address->prev_->next_ = linked_address->next_; ++ } else { ++ head_ = linked_address->next_; ++ } ++ if (linked_address->next_) { ++ linked_address->next_->prev_ = linked_address->prev_; ++ } ++ linked_address->prev_ = nullptr; ++ linked_address->next_ = nullptr; ++} ++ ++#undef SScanF ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // USE_SIMULATOR +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/simulator-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/riscv64/simulator-riscv64.h +@@ -0,0 +1,764 @@ ++// Copyright 2020 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++// Copyright(c) 2010 - 2017, ++// The Regents of the University of California(Regents).All Rights Reserved. ++// ++// Redistribution and use in source and binary forms, ++// with or without modification, ++// are permitted provided that the following ++// conditions are met : 1. Redistributions of source code must retain the ++// above copyright notice, this list of conditions and the following ++// disclaimer.2. Redistributions in binary form must reproduce the above ++// copyright notice, this list of conditions and the following disclaimer in ++// the ++// documentation and / ++// or ++// other materials provided with the distribution.3. Neither the name of ++// the Regents nor the names of its contributors may be used to endorse ++// or ++// promote products derived from ++// this software without specific prior written permission. ++// ++// IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, ++// INDIRECT, SPECIAL, ++// INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ++// ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, ++// EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++// ++// REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, ++// INCLUDING, BUT NOT LIMITED TO, ++// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A ++// PARTICULAR PURPOSE.THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, ++// IF ANY, ++// PROVIDED HEREUNDER IS PROVIDED ++// "AS IS".REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, ++// SUPPORT, UPDATES, ENHANCEMENTS, ++// OR MODIFICATIONS. ++ ++// The original source code covered by the above license above has been ++// modified significantly by the v8 project authors. ++ ++// Declares a Simulator for RISC-V instructions if we are not generating a ++// native RISC-V binary. This Simulator allows us to run and debug RISC-V code ++// generation on regular desktop machines. V8 calls into generated code via the ++// GeneratedCode wrapper, which will start execution in the Simulator or ++// forwards to the real entry on a RISC-V HW platform. ++ ++#ifndef V8_EXECUTION_RISCV_SIMULATOR_RISCV_H_ ++#define V8_EXECUTION_RISCV_SIMULATOR_RISCV_H_ ++ ++// globals.h defines USE_SIMULATOR. ++#include "src/common/globals.h" ++ ++template ++int Compare(const T& a, const T& b) { ++ if (a == b) ++ return 0; ++ else if (a < b) ++ return -1; ++ else ++ return 1; ++} ++ ++// Returns the negative absolute value of its argument. ++template ::value>::type> ++T Nabs(T a) { ++ return a < 0 ? a : -a; ++} ++ ++#if defined(USE_SIMULATOR) ++// Running with a simulator. ++ ++#include "src/base/hashmap.h" ++#include "src/codegen/assembler.h" ++#include "src/codegen/riscv64/constants-riscv64.h" ++#include "src/execution/simulator-base.h" ++#include "src/utils/allocation.h" ++ ++namespace v8 { ++namespace internal { ++ ++// ----------------------------------------------------------------------------- ++// Utility types and functions for RISCV ++// TODO: Add Spike License here ++#ifdef V8_TARGET_ARCH_32_BIT ++using sreg_t = int32_t; ++using reg_t = uint32_t; ++#define xlen 32 ++#elif V8_TARGET_ARCH_64_BIT ++using sreg_t = int64_t; ++using reg_t = uint64_t; ++#define xlen 64 ++#else ++#error "Cannot detect Riscv's bitwidth" ++#endif ++ ++#define sext32(x) ((sreg_t)(int32_t)(x)) ++#define zext32(x) ((reg_t)(uint32_t)(x)) ++#define sext_xlen(x) (((sreg_t)(x) << (64 - xlen)) >> (64 - xlen)) ++#define zext_xlen(x) (((reg_t)(x) << (64 - xlen)) >> (64 - xlen)) ++ ++#define BIT(n) (0x1LL << n) ++#define QUIET_BIT_S(nan) (bit_cast(nan) & BIT(22)) ++#define QUIET_BIT_D(nan) (bit_cast(nan) & BIT(51)) ++static inline bool isSnan(float fp) { return !QUIET_BIT_S(fp); } ++static inline bool isSnan(double fp) { return !QUIET_BIT_D(fp); } ++#undef QUIET_BIT_S ++#undef QUIET_BIT_D ++ ++inline uint64_t mulhu(uint64_t a, uint64_t b) { ++ __uint128_t full_result = ((__uint128_t)a) * ((__uint128_t)b); ++ return full_result >> 64; ++} ++ ++inline int64_t mulh(int64_t a, int64_t b) { ++ __int128_t full_result = ((__int128_t)a) * ((__int128_t)b); ++ return full_result >> 64; ++} ++ ++inline int64_t mulhsu(int64_t a, uint64_t b) { ++ __int128_t full_result = ((__int128_t)a) * ((__uint128_t)b); ++ return full_result >> 64; ++} ++ ++// Floating point helpers ++#define F32_SIGN ((uint32_t)1 << 31) ++union u32_f32 { ++ uint32_t u; ++ float f; ++}; ++inline float fsgnj32(float rs1, float rs2, bool n, bool x) { ++ u32_f32 a = {.f = rs1}, b = {.f = rs2}; ++ u32_f32 res; ++ res.u = ++ (a.u & ~F32_SIGN) | ((((x) ? a.u : (n) ? F32_SIGN : 0) ^ b.u) & F32_SIGN); ++ return res.f; ++} ++#define F64_SIGN ((uint64_t)1 << 63) ++union u64_f64 { ++ uint64_t u; ++ double d; ++}; ++inline double fsgnj64(double rs1, double rs2, bool n, bool x) { ++ u64_f64 a = {.d = rs1}, b = {.d = rs2}; ++ u64_f64 res; ++ res.u = ++ (a.u & ~F64_SIGN) | ((((x) ? a.u : (n) ? F64_SIGN : 0) ^ b.u) & F64_SIGN); ++ return res.d; ++} ++ ++inline bool is_boxed_float(int64_t v) { ++ return (uint32_t)((v >> 32) + 1) == 0; ++} ++inline int64_t box_float(float v) { ++ return (0xFFFFFFFF00000000 | bit_cast(v)); ++} ++ ++// ----------------------------------------------------------------------------- ++// Utility functions ++ ++class CachePage { ++ public: ++ static const int LINE_VALID = 0; ++ static const int LINE_INVALID = 1; ++ ++ static const int kPageShift = 12; ++ static const int kPageSize = 1 << kPageShift; ++ static const int kPageMask = kPageSize - 1; ++ static const int kLineShift = 2; // The cache line is only 4 bytes right now. ++ static const int kLineLength = 1 << kLineShift; ++ static const int kLineMask = kLineLength - 1; ++ ++ CachePage() { memset(&validity_map_, LINE_INVALID, sizeof(validity_map_)); } ++ ++ char* ValidityByte(int offset) { ++ return &validity_map_[offset >> kLineShift]; ++ } ++ ++ char* CachedData(int offset) { return &data_[offset]; } ++ ++ private: ++ char data_[kPageSize]; // The cached data. ++ static const int kValidityMapSize = kPageSize >> kLineShift; ++ char validity_map_[kValidityMapSize]; // One byte per line. ++}; ++ ++class SimInstructionBase : public InstructionBase { ++ public: ++ Type InstructionType() const { return type_; } ++ inline Instruction* instr() const { return instr_; } ++ inline int32_t operand() const { return operand_; } ++ ++ protected: ++ SimInstructionBase() : operand_(-1), instr_(nullptr), type_(kUnsupported) {} ++ explicit SimInstructionBase(Instruction* instr) {} ++ ++ int32_t operand_; ++ Instruction* instr_; ++ Type type_; ++ ++ private: ++ DISALLOW_ASSIGN(SimInstructionBase); ++}; ++ ++class SimInstruction : public InstructionGetters { ++ public: ++ SimInstruction() {} ++ ++ explicit SimInstruction(Instruction* instr) { *this = instr; } ++ ++ SimInstruction& operator=(Instruction* instr) { ++ operand_ = *reinterpret_cast(instr); ++ instr_ = instr; ++ type_ = InstructionBase::InstructionType(); ++ DCHECK(reinterpret_cast(&operand_) == this); ++ return *this; ++ } ++}; ++ ++class Simulator : public SimulatorBase { ++ public: ++ friend class RiscvDebugger; ++ ++ // Registers are declared in order. See SMRL chapter 2. ++ enum Register { ++ no_reg = -1, ++ zero_reg = 0, ++ ra, ++ sp, ++ gp, ++ tp, ++ t0, ++ t1, ++ t2, ++ s0, ++ s1, ++ a0, ++ a1, ++ a2, ++ a3, ++ a4, ++ a5, ++ a6, ++ a7, ++ s2, ++ s3, ++ s4, ++ s5, ++ s6, ++ s7, ++ s8, ++ s9, ++ s10, ++ s11, ++ t3, ++ t4, ++ t5, ++ t6, ++ pc, // pc must be the last register. ++ kNumSimuRegisters, ++ // aliases ++ fp = s0 ++ }; ++ ++ // Coprocessor registers. ++ // Generated code will always use doubles. So we will only use even registers. ++ enum FPURegister { ++ ft0, ++ ft1, ++ ft2, ++ ft3, ++ ft4, ++ ft5, ++ ft6, ++ ft7, ++ fs0, ++ fs1, ++ fa0, ++ fa1, ++ fa2, ++ fa3, ++ fa4, ++ fa5, ++ fa6, ++ fa7, ++ fs2, ++ fs3, ++ fs4, ++ fs5, ++ fs6, ++ fs7, ++ fs8, ++ fs9, ++ fs10, ++ fs11, ++ ft8, ++ ft9, ++ ft10, ++ ft11, ++ kNumFPURegisters ++ }; ++ ++ explicit Simulator(Isolate* isolate); ++ ~Simulator(); ++ ++ // The currently executing Simulator instance. Potentially there can be one ++ // for each native thread. ++ V8_EXPORT_PRIVATE static Simulator* current(v8::internal::Isolate* isolate); ++ ++ // Accessors for register state. Reading the pc value adheres to the RISC-V ++ // architecture specification and is off by a 8 from the currently executing ++ // instruction. ++ void set_register(int reg, int64_t value); ++ void set_register_word(int reg, int32_t value); ++ void set_dw_register(int dreg, const int* dbl); ++ int64_t get_register(int reg) const; ++ double get_double_from_register_pair(int reg); ++ ++ // Same for FPURegisters. ++ void set_fpu_register(int fpureg, int64_t value); ++ void set_fpu_register_word(int fpureg, int32_t value); ++ void set_fpu_register_hi_word(int fpureg, int32_t value); ++ void set_fpu_register_float(int fpureg, float value); ++ void set_fpu_register_double(int fpureg, double value); ++ ++ int64_t get_fpu_register(int fpureg) const; ++ int32_t get_fpu_register_word(int fpureg) const; ++ int32_t get_fpu_register_signed_word(int fpureg) const; ++ int32_t get_fpu_register_hi_word(int fpureg) const; ++ float get_fpu_register_float(int fpureg) const; ++ double get_fpu_register_double(int fpureg) const; ++ ++ // RV CSR manipulation ++ uint32_t read_csr_value(uint32_t csr); ++ void write_csr_value(uint32_t csr, uint64_t value); ++ void set_csr_bits(uint32_t csr, uint64_t flags); ++ void clear_csr_bits(uint32_t csr, uint64_t flags); ++ ++ void set_fflags(uint32_t flags) { set_csr_bits(csr_fflags, flags); } ++ void clear_fflags(int32_t flags) { clear_csr_bits(csr_fflags, flags); } ++ ++ inline uint32_t get_dynamic_rounding_mode(); ++ inline bool test_fflags_bits(uint32_t mask); ++ ++ float RoundF2FHelper(float input_val, int rmode); ++ double RoundF2FHelper(double input_val, int rmode); ++ template ++ I_TYPE RoundF2IHelper(F_TYPE original, int rmode); ++ ++ template ++ T FMaxMinHelper(T a, T b, MaxMinKind kind); ++ ++ template ++ bool CompareFHelper(T input1, T input2, FPUCondition cc); ++ ++ // Special case of set_register and get_register to access the raw PC value. ++ void set_pc(int64_t value); ++ int64_t get_pc() const; ++ ++ Address get_sp() const { return static_cast
(get_register(sp)); } ++ ++ // Accessor to the internal simulator stack area. ++ uintptr_t StackLimit(uintptr_t c_limit) const; ++ ++ // Executes RISC-V instructions until the PC reaches end_sim_pc. ++ void Execute(); ++ ++ template ++ Return Call(Address entry, Args... args) { ++ return VariadicCall(this, &Simulator::CallImpl, entry, args...); ++ } ++ ++ // Alternative: call a 2-argument double function. ++ double CallFP(Address entry, double d0, double d1); ++ ++ // Push an address onto the JS stack. ++ uintptr_t PushAddress(uintptr_t address); ++ ++ // Pop an address from the JS stack. ++ uintptr_t PopAddress(); ++ ++ // Debugger input. ++ void set_last_debugger_input(char* input); ++ char* last_debugger_input() { return last_debugger_input_; } ++ ++ // Redirection support. ++ static void SetRedirectInstruction(Instruction* instruction); ++ ++ // ICache checking. ++ static bool ICacheMatch(void* one, void* two); ++ static void FlushICache(base::CustomMatcherHashMap* i_cache, void* start, ++ size_t size); ++ ++ // Returns true if pc register contains one of the 'special_values' defined ++ // below (bad_ra, end_sim_pc). ++ bool has_bad_pc() const; ++ ++ private: ++ enum special_values { ++ // Known bad pc value to ensure that the simulator does not execute ++ // without being properly setup. ++ bad_ra = -1, ++ // A pc value used to signal the simulator to stop execution. Generally ++ // the ra is set to this value on transition from native C code to ++ // simulated execution, so that the simulator can "return" to the native ++ // C code. ++ end_sim_pc = -2, ++ // Unpredictable value. ++ Unpredictable = 0xbadbeaf ++ }; ++ ++ V8_EXPORT_PRIVATE intptr_t CallImpl(Address entry, int argument_count, ++ const intptr_t* arguments); ++ ++ // Unsupported instructions use Format to print an error and stop execution. ++ void Format(Instruction* instr, const char* format); ++ ++ // Helpers for data value tracing. ++ enum TraceType { ++ BYTE, ++ HALF, ++ WORD, ++ DWORD, ++ FLOAT, ++ DOUBLE, ++ // FLOAT_DOUBLE, ++ // WORD_DWORD ++ }; ++ ++ // RISCV Memory read/write methods ++ template ++ T ReadMem(int64_t addr, Instruction* instr); ++ template ++ void WriteMem(int64_t addr, T value, Instruction* instr); ++ template ++ T amo(int64_t addr, OP f, Instruction* instr, TraceType t) { ++ auto lhs = ReadMem(addr, instr); ++ // FIXME: trace memory read for AMO ++ WriteMem(addr, (T)f(lhs), instr); ++ return lhs; ++ } ++ ++ // Helper for debugging memory access. ++ inline void DieOrDebug(); ++ ++ void TraceRegWr(int64_t value, TraceType t = DWORD); ++ void TraceMemWr(int64_t addr, int64_t value, TraceType t); ++ template ++ void TraceMemRd(int64_t addr, T value, int64_t reg_value); ++ template ++ void TraceMemWr(int64_t addr, T value); ++ ++ SimInstruction instr_; ++ ++ // RISCV utlity API to access register value ++ inline int32_t rs1_reg() const { return instr_.Rs1Value(); } ++ inline int64_t rs1() const { return get_register(rs1_reg()); } ++ inline float frs1() const { return get_fpu_register_float(rs1_reg()); } ++ inline double drs1() const { return get_fpu_register_double(rs1_reg()); } ++ inline int32_t rs2_reg() const { return instr_.Rs2Value(); } ++ inline int64_t rs2() const { return get_register(rs2_reg()); } ++ inline float frs2() const { return get_fpu_register_float(rs2_reg()); } ++ inline double drs2() const { return get_fpu_register_double(rs2_reg()); } ++ inline int32_t rs3_reg() const { return instr_.Rs3Value(); } ++ inline int64_t rs3() const { return get_register(rs3_reg()); } ++ inline float frs3() const { return get_fpu_register_float(rs3_reg()); } ++ inline double drs3() const { return get_fpu_register_double(rs3_reg()); } ++ inline int32_t rd_reg() const { return instr_.RdValue(); } ++ inline int32_t frd_reg() const { return instr_.RdValue(); } ++ inline int16_t boffset() const { return instr_.BranchOffset(); } ++ inline int16_t imm12() const { return instr_.Imm12Value(); } ++ inline int32_t imm20J() const { return instr_.Imm20JValue(); } ++ inline int32_t imm5CSR() const { return instr_.Rs1Value(); } ++ inline int16_t csr_reg() const { return instr_.CsrValue(); } ++ ++ inline void set_rd(int64_t value, bool trace = true) { ++ set_register(rd_reg(), value); ++ if (trace) TraceRegWr(get_register(rd_reg()), DWORD); ++ } ++ inline void set_frd(float value, bool trace = true) { ++ set_fpu_register_float(rd_reg(), value); ++ if (trace) TraceRegWr(get_fpu_register_word(rd_reg()), FLOAT); ++ } ++ inline void set_drd(double value, bool trace = true) { ++ set_fpu_register_double(rd_reg(), value); ++ if (trace) TraceRegWr(get_fpu_register(rd_reg()), DOUBLE); ++ } ++ inline int16_t shamt() const { return (imm12() & 0x3F); } ++ inline int16_t shamt32() const { return (imm12() & 0x1F); } ++ inline int32_t s_imm12() const { return instr_.StoreOffset(); } ++ inline int32_t u_imm() const { return instr_.Imm20UValue() << 12; } ++ inline void require(bool check) { ++ if (!check) { ++ SignalException(kIllegalInstruction); ++ } ++ } ++ ++ template ++ inline T CanonicalizeFPUOp3(Func fn) { ++ DCHECK(std::is_floating_point::value); ++ T src1 = std::is_same::value ? frs1() : drs1(); ++ T src2 = std::is_same::value ? frs2() : drs2(); ++ T src3 = std::is_same::value ? frs3() : drs3(); ++ auto alu_out = fn(src1, src2, src3); ++ // if any input or result is NaN, the result is quiet_NaN ++ if (std::isnan(alu_out) || std::isnan(src1) || std::isnan(src2) || ++ std::isnan(src3)) { ++ // signaling_nan sets kInvalidOperation bit ++ if (isSnan(alu_out) || isSnan(src1) || isSnan(src2) || isSnan(src3)) ++ set_fflags(kInvalidOperation); ++ alu_out = std::numeric_limits::quiet_NaN(); ++ } ++ return alu_out; ++ } ++ ++ template ++ inline T CanonicalizeFPUOp2(Func fn) { ++ DCHECK(std::is_floating_point::value); ++ T src1 = std::is_same::value ? frs1() : drs1(); ++ T src2 = std::is_same::value ? frs2() : drs2(); ++ auto alu_out = fn(src1, src2); ++ // if any input or result is NaN, the result is quiet_NaN ++ if (std::isnan(alu_out) || std::isnan(src1) || std::isnan(src2)) { ++ // signaling_nan sets kInvalidOperation bit ++ if (isSnan(alu_out) || isSnan(src1) || isSnan(src2)) ++ set_fflags(kInvalidOperation); ++ alu_out = std::numeric_limits::quiet_NaN(); ++ } ++ return alu_out; ++ } ++ ++ template ++ inline T CanonicalizeFPUOp1(Func fn) { ++ DCHECK(std::is_floating_point::value); ++ T src1 = std::is_same::value ? frs1() : drs1(); ++ auto alu_out = fn(src1); ++ // if any input or result is NaN, the result is quiet_NaN ++ if (std::isnan(alu_out) || std::isnan(src1)) { ++ // signaling_nan sets kInvalidOperation bit ++ if (isSnan(alu_out) || isSnan(src1)) set_fflags(kInvalidOperation); ++ alu_out = std::numeric_limits::quiet_NaN(); ++ } ++ return alu_out; ++ } ++ ++ template ++ inline float CanonicalizeDoubleToFloatOperation(Func fn) { ++ float alu_out = fn(drs1()); ++ if (std::isnan(alu_out) || std::isnan(drs1())) ++ alu_out = std::numeric_limits::quiet_NaN(); ++ return alu_out; ++ } ++ ++ template ++ inline float CanonicalizeFloatToDoubleOperation(Func fn) { ++ double alu_out = fn(frs1()); ++ if (std::isnan(alu_out) || std::isnan(frs1())) ++ alu_out = std::numeric_limits::quiet_NaN(); ++ return alu_out; ++ } ++ ++ // RISCV decoding routine ++ void DecodeRVRType(); ++ void DecodeRVR4Type(); ++ void DecodeRVRFPType(); // Special routine for R/OP_FP type ++ void DecodeRVRAType(); // Special routine for R/AMO type ++ void DecodeRVIType(); ++ void DecodeRVSType(); ++ void DecodeRVBType(); ++ void DecodeRVUType(); ++ void DecodeRVJType(); ++ ++ // Used for breakpoints and traps. ++ void SoftwareInterrupt(); ++ ++ // Debug helpers ++ ++ // Simulator breakpoints. ++ struct Breakpoint { ++ Instruction* location; ++ bool enabled; ++ bool is_tbreak; ++ }; ++ std::vector breakpoints_; ++ void SetBreakpoint(Instruction* breakpoint, bool is_tbreak); ++ void ListBreakpoints(); ++ void CheckBreakpoints(); ++ ++ // Stop helper functions. ++ bool IsWatchpoint(uint64_t code); ++ void PrintWatchpoint(uint64_t code); ++ void HandleStop(uint64_t code); ++ bool IsStopInstruction(Instruction* instr); ++ bool IsEnabledStop(uint64_t code); ++ void EnableStop(uint64_t code); ++ void DisableStop(uint64_t code); ++ void IncreaseStopCounter(uint64_t code); ++ void PrintStopInfo(uint64_t code); ++ ++ // Executes one instruction. ++ void InstructionDecode(Instruction* instr); ++ ++ // ICache. ++ static void CheckICache(base::CustomMatcherHashMap* i_cache, ++ Instruction* instr); ++ static void FlushOnePage(base::CustomMatcherHashMap* i_cache, intptr_t start, ++ size_t size); ++ static CachePage* GetCachePage(base::CustomMatcherHashMap* i_cache, ++ void* page); ++ ++ enum Exception { ++ none, ++ kIntegerOverflow, ++ kIntegerUnderflow, ++ kDivideByZero, ++ kNumExceptions, ++ // RISCV illegual instruction exception ++ kIllegalInstruction, ++ }; ++ ++ // Exceptions. ++ void SignalException(Exception e); ++ ++ // Handle arguments and return value for runtime FP functions. ++ void GetFpArgs(double* x, double* y, int32_t* z); ++ void SetFpResult(const double& result); ++ ++ void CallInternal(Address entry); ++ ++ // Architecture state. ++ // Registers. ++ int64_t registers_[kNumSimuRegisters]; ++ // Coprocessor Registers. ++ int64_t FPUregisters_[kNumFPURegisters]; ++ // Floating-point control and status register. ++ uint32_t FCSR_; ++ ++ // Simulator support. ++ // Allocate 1MB for stack. ++ size_t stack_size_; ++ char* stack_; ++ bool pc_modified_; ++ int64_t icount_; ++ int break_count_; ++ EmbeddedVector trace_buf_; ++ ++ // Debugger input. ++ char* last_debugger_input_; ++ ++ v8::internal::Isolate* isolate_; ++ ++ // Stop is disabled if bit 31 is set. ++ static const uint32_t kStopDisabledBit = 1 << 31; ++ ++ // A stop is enabled, meaning the simulator will stop when meeting the ++ // instruction, if bit 31 of watched_stops_[code].count is unset. ++ // The value watched_stops_[code].count & ~(1 << 31) indicates how many times ++ // the breakpoint was hit or gone through. ++ struct StopCountAndDesc { ++ uint32_t count; ++ char* desc; ++ }; ++ StopCountAndDesc watched_stops_[kMaxStopCode + 1]; ++ ++ // Synchronization primitives. ++ enum class MonitorAccess { ++ Open, ++ RMW, ++ }; ++ ++ enum class TransactionSize { ++ None = 0, ++ Word = 4, ++ DoubleWord = 8, ++ }; ++ ++ // The least-significant bits of the address are ignored. The number of bits ++ // is implementation-defined, between 3 and minimum page size. ++ static const uintptr_t kExclusiveTaggedAddrMask = ~((1 << 3) - 1); ++ ++ class LocalMonitor { ++ public: ++ LocalMonitor(); ++ ++ // These functions manage the state machine for the local monitor, but do ++ // not actually perform loads and stores. NotifyStoreConditional only ++ // returns true if the store conditional is allowed; the global monitor will ++ // still have to be checked to see whether the memory should be updated. ++ void NotifyLoad(); ++ void NotifyLoadLinked(uintptr_t addr, TransactionSize size); ++ void NotifyStore(); ++ bool NotifyStoreConditional(uintptr_t addr, TransactionSize size); ++ ++ private: ++ void Clear(); ++ ++ MonitorAccess access_state_; ++ uintptr_t tagged_addr_; ++ TransactionSize size_; ++ }; ++ ++ class GlobalMonitor { ++ public: ++ class LinkedAddress { ++ public: ++ LinkedAddress(); ++ ++ private: ++ friend class GlobalMonitor; ++ // These functions manage the state machine for the global monitor, but do ++ // not actually perform loads and stores. ++ void Clear_Locked(); ++ void NotifyLoadLinked_Locked(uintptr_t addr); ++ void NotifyStore_Locked(); ++ bool NotifyStoreConditional_Locked(uintptr_t addr, ++ bool is_requesting_thread); ++ ++ MonitorAccess access_state_; ++ uintptr_t tagged_addr_; ++ LinkedAddress* next_; ++ LinkedAddress* prev_; ++ // A scd can fail due to background cache evictions. Rather than ++ // simulating this, we'll just occasionally introduce cases where an ++ // store conditional fails. This will happen once after every ++ // kMaxFailureCounter exclusive stores. ++ static const int kMaxFailureCounter = 5; ++ int failure_counter_; ++ }; ++ ++ // Exposed so it can be accessed by Simulator::{Read,Write}Ex*. ++ base::Mutex mutex; ++ ++ void NotifyLoadLinked_Locked(uintptr_t addr, LinkedAddress* linked_address); ++ void NotifyStore_Locked(LinkedAddress* linked_address); ++ bool NotifyStoreConditional_Locked(uintptr_t addr, ++ LinkedAddress* linked_address); ++ ++ // Called when the simulator is destroyed. ++ void RemoveLinkedAddress(LinkedAddress* linked_address); ++ ++ static GlobalMonitor* Get(); ++ ++ private: ++ // Private constructor. Call {GlobalMonitor::Get()} to get the singleton. ++ GlobalMonitor() = default; ++ friend class base::LeakyObject; ++ ++ bool IsProcessorInLinkedList_Locked(LinkedAddress* linked_address) const; ++ void PrependProcessor_Locked(LinkedAddress* linked_address); ++ ++ LinkedAddress* head_ = nullptr; ++ }; ++ ++ LocalMonitor local_monitor_; ++ GlobalMonitor::LinkedAddress global_monitor_thread_; ++}; ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // defined(USE_SIMULATOR) ++#endif // V8_EXECUTION_RISCV_SIMULATOR_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/simulator-base.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/execution/simulator-base.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/simulator-base.h +@@ -89,9 +89,10 @@ class SimulatorBase { + static typename std::enable_if::value, intptr_t>::type + ConvertArg(T arg) { + static_assert(sizeof(T) <= sizeof(intptr_t), "type bigger than ptrsize"); +-#if V8_TARGET_ARCH_MIPS64 +- // The MIPS64 calling convention is to sign extend all values, even unsigned +- // ones. ++#if V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_RISCV64 ++ // The MIPS64 and RISCV64 calling convention is to sign extend all values, ++ // even unsigned ones. ++ // FIXME (RISCV): what about RISCV calling contention? + using signed_t = typename std::make_signed::type; + return static_cast(static_cast(arg)); + #else +@@ -125,6 +126,7 @@ class SimulatorBase { + // - V8_TARGET_ARCH_PPC: svc (Supervisor Call) + // - V8_TARGET_ARCH_PPC64: svc (Supervisor Call) + // - V8_TARGET_ARCH_S390: svc (Supervisor Call) ++// - V8_TARGET_ARCH_RISCV64: ecall (Supervisor Call) + class Redirection { + public: + Redirection(Address external_function, ExternalReference::Type type); +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/simulator.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/execution/simulator.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/execution/simulator.h +@@ -26,6 +26,10 @@ + #include "src/execution/mips64/simulator-mips64.h" + #elif V8_TARGET_ARCH_S390 + #include "src/execution/s390/simulator-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/execution/riscv64/simulator-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/execution/riscv/simulator-riscv.h" + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/flags/flag-definitions.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/flags/flag-definitions.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/flags/flag-definitions.h +@@ -1182,6 +1182,7 @@ DEFINE_BOOL(partial_constant_pool, true, + DEFINE_STRING(sim_arm64_optional_features, "none", + "enable optional features on the simulator for testing: none or " + "all") ++DEFINE_BOOL(debug_riscv, false, "enable debug prints") + + // Controlling source positions for Torque/CSA code. + DEFINE_BOOL(enable_source_at_csa_bind, false, +@@ -1372,7 +1373,7 @@ DEFINE_BOOL(check_icache, false, + "Check icache flushes in ARM and MIPS simulator") + DEFINE_INT(stop_sim_at, 0, "Simulator stop after x number of instructions") + #if defined(V8_TARGET_ARCH_ARM64) || defined(V8_TARGET_ARCH_MIPS64) || \ +- defined(V8_TARGET_ARCH_PPC64) ++ defined(V8_TARGET_ARCH_PPC64) || defined(V8_TARGET_ARCH_RISCV64) + DEFINE_INT(sim_stack_alignment, 16, + "Stack alignment in bytes in simulator. This must be a power of two " + "and it must be at least 16. 16 is default.") +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/heap/base/asm/riscv64/push_registers_asm.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/heap/base/asm/riscv64/push_registers_asm.cc +@@ -0,0 +1,47 @@ ++// Copyright 2020 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++// Push all callee-saved registers to get them on the stack for conservative ++// stack scanning. ++// ++// See asm/x64/push_registers_clang.cc for why the function is not generated ++// using clang. ++// ++// Do not depend on V8_TARGET_OS_* defines as some embedders may override the ++// GN toolchain (e.g. ChromeOS) and not provide them. ++asm( ++ ".global PushAllRegistersAndIterateStack \n" ++ ".type PushAllRegistersAndIterateStack, %function \n" ++ ".hidden PushAllRegistersAndIterateStack \n" ++ "PushAllRegistersAndIterateStack: \n" ++ // Push all callee-saved registers and save return address. ++ " addi sp, sp, -96 \n" ++ " sd ra, 88(sp) \n" ++ " sd s8, 80(sp) \n" ++ " sd sp, 72(sp) \n" ++ " sd gp, 64(sp) \n" ++ " sd s7, 56(sp) \n" ++ " sd s6, 48(sp) \n" ++ " sd s5, 40(sp) \n" ++ " sd s4, 32(sp) \n" ++ " sd s3, 24(sp) \n" ++ " sd s2, 16(sp) \n" ++ " sd s1, 8(sp) \n" ++ " sd s0, 0(sp) \n" ++ // Maintain frame pointer. ++ " mv s8, sp \n" ++ // Pass 1st parameter (a0) unchanged (Stack*). ++ // Pass 2nd parameter (a1) unchanged (StackVisitor*). ++ // Save 3rd parameter (a2; IterateStackCallback). ++ " mv a3, a2 \n" ++ " mv a2, sp \n" ++ // Call the callback. ++ " jalr a3 \n" ++ // Load return address. ++ " ld ra, 88(sp) \n" ++ // Restore frame pointer. ++ " ld s8, 80(sp) \n" ++ " addi sp, sp, 96 \n" ++ " jr ra \n"); ++ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/interpreter/interpreter-assembler.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/interpreter/interpreter-assembler.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/interpreter/interpreter-assembler.cc +@@ -1348,7 +1348,8 @@ void InterpreterAssembler::TraceBytecode + + // static + bool InterpreterAssembler::TargetSupportsUnalignedAccess() { +-#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 ++#if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_RISCV64 || \ ++ V8_TARGET_ARCH_RISCV + return false; + #elif V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_S390 || \ + V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_PPC || \ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/libsampler/sampler.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/libsampler/sampler.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/libsampler/sampler.cc +@@ -442,6 +442,12 @@ void SignalHandler::FillRegisterState(vo + state->sp = reinterpret_cast(ucontext->uc_mcontext.gregs[15]); + state->fp = reinterpret_cast(ucontext->uc_mcontext.gregs[11]); + state->lr = reinterpret_cast(ucontext->uc_mcontext.gregs[14]); ++#elif V8_HOST_ARCH_RISCV64 || V8_HOST_ARCH_RISCV ++ // Spec CH.25 RISC-V Assembly Programmer’s Handbook ++ state->pc = reinterpret_cast(mcontext.__gregs[REG_PC]); ++ state->sp = reinterpret_cast(mcontext.__gregs[REG_SP]); ++ state->fp = reinterpret_cast(mcontext.__gregs[REG_S0]); ++ state->lr = reinterpret_cast(mcontext.__gregs[REG_RA]); + #endif // V8_HOST_ARCH_* + #elif V8_OS_IOS + +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/logging/log.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/logging/log.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/logging/log.cc +@@ -594,6 +594,14 @@ void LowLevelLogger::LogCodeInfo() { + const char arch[] = "arm64"; + #elif V8_TARGET_ARCH_S390 + const char arch[] = "s390"; ++#elif V8_TARGET_ARCH_RISCV64 ++ // FIXME (RISCV) porting: need more specific arch strings based on cpu ++ // features ++ const char arch[] = "riscv64"; ++#elif V8_TARGET_ARCH_RISCV ++ // FIXME (RISCV) porting: need more specific arch strings based on cpu ++ // features ++ const char arch[] = "riscv"; + #else + const char arch[] = "unknown"; + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/backing-store.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/objects/backing-store.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/backing-store.cc +@@ -29,7 +29,8 @@ constexpr bool kUseGuardRegions = true; + constexpr bool kUseGuardRegions = false; + #endif + +-#if V8_TARGET_ARCH_MIPS64 ++#if V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_RISCV64 ++// FIXME(RISCV): Check this value + // MIPS64 has a user space of 2^40 bytes on most processors, + // address space limits needs to be smaller. + constexpr size_t kAddressSpaceLimit = 0x8000000000L; // 512 GiB +@@ -39,6 +40,10 @@ constexpr size_t kAddressSpaceLimit = 0x + constexpr size_t kAddressSpaceLimit = 0xC0000000; // 3 GiB + #endif + ++#if V8_TARGET_ARCH_RISCV ++#erro RISCV(32) architecture not supported ++#endif ++ + constexpr uint64_t kOneGiB = 1024 * 1024 * 1024; + constexpr uint64_t kNegativeGuardSize = 2 * kOneGiB; + +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/code.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/objects/code.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/code.cc +@@ -234,7 +234,7 @@ bool Code::IsIsolateIndependent(Isolate* + RelocInfo::ModeMask(RelocInfo::WASM_STUB_CALL))); + + #if defined(V8_TARGET_ARCH_PPC) || defined(V8_TARGET_ARCH_PPC64) || \ +- defined(V8_TARGET_ARCH_MIPS64) ++ defined(V8_TARGET_ARCH_MIPS64) || defined(V8_TARGET_ARCH_RISCV64) + return RelocIterator(*this, kModeMask).done(); + #elif defined(V8_TARGET_ARCH_X64) || defined(V8_TARGET_ARCH_ARM64) || \ + defined(V8_TARGET_ARCH_ARM) || defined(V8_TARGET_ARCH_MIPS) || \ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/code.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/objects/code.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/objects/code.h +@@ -461,6 +461,10 @@ class Code : public HeapObject { + : (COMPRESS_POINTERS_BOOL ? 16 : 28); + #elif V8_TARGET_ARCH_S390X + static constexpr int kHeaderPaddingSize = COMPRESS_POINTERS_BOOL ? 16 : 28; ++#elif V8_TARGET_ARCH_RISCV64 ++ static constexpr int kHeaderPaddingSize = 28; ++#elif V8_TARGET_ARCH_RISCV ++#error riscv32 unsupported yet + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/profiler/tick-sample.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/profiler/tick-sample.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/profiler/tick-sample.cc +@@ -125,6 +125,13 @@ bool SimulatorHelper::FillRegisters(Isol + state->sp = reinterpret_cast(simulator->get_register(Simulator::sp)); + state->fp = reinterpret_cast(simulator->get_register(Simulator::fp)); + state->lr = reinterpret_cast(simulator->get_register(Simulator::ra)); ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ if (!simulator->has_bad_pc()) { ++ state->pc = reinterpret_cast(simulator->get_pc()); ++ } ++ state->sp = reinterpret_cast(simulator->get_register(Simulator::sp)); ++ state->fp = reinterpret_cast(simulator->get_register(Simulator::fp)); ++ state->lr = reinterpret_cast(simulator->get_register(Simulator::ra)); + #endif + if (state->sp == 0 || state->fp == 0) { + // It possible that the simulator is interrupted while it is updating +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler-arch.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler-arch.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler-arch.h +@@ -23,6 +23,10 @@ + #include "src/regexp/mips64/regexp-macro-assembler-mips64.h" + #elif V8_TARGET_ARCH_S390 + #include "src/regexp/s390/regexp-macro-assembler-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/regexp/riscv64/regexp-macro-assembler-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/regexp/riscv/regexp-macro-assembler-riscv.h" + #else + #error Unsupported target architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp-macro-assembler.h +@@ -44,6 +44,7 @@ class RegExpMacroAssembler { + kARMImplementation, + kARM64Implementation, + kMIPSImplementation, ++ kRISCVImplementation, + kS390Implementation, + kPPCImplementation, + kX64Implementation, +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/regexp/regexp.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/regexp.cc +@@ -815,6 +815,9 @@ bool RegExpImpl::Compile(Isolate* isolat + #elif V8_TARGET_ARCH_MIPS64 + macro_assembler.reset(new RegExpMacroAssemblerMIPS(isolate, zone, mode, + output_register_count)); ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++ macro_assembler.reset(new RegExpMacroAssemblerRISCV(isolate, zone, mode, ++ output_register_count)); + #else + #error "Unsupported architecture" + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.cc +@@ -0,0 +1,1260 @@ ++// Copyright 2012 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#if V8_TARGET_ARCH_RISCV64 ++ ++#include "src/regexp/riscv64/regexp-macro-assembler-riscv64.h" ++ ++#include "src/codegen/assembler-inl.h" ++#include "src/codegen/macro-assembler.h" ++#include "src/logging/log.h" ++#include "src/objects/objects-inl.h" ++#include "src/regexp/regexp-macro-assembler.h" ++#include "src/regexp/regexp-stack.h" ++#include "src/snapshot/embedded/embedded-data.h" ++#include "src/strings/unicode.h" ++ ++namespace v8 { ++namespace internal { ++ ++/* clang-format off ++ * ++ * This assembler uses the following register assignment convention ++ * - t4 : Temporarily stores the index of capture start after a matching pass ++ * for a global regexp. ++ * - a5 : Pointer to current Code object including heap object tag. ++ * - a6 : Current position in input, as negative offset from end of string. ++ * Please notice that this is the byte offset, not the character offset! ++ * - a7 : Currently loaded character. Must be loaded using ++ * LoadCurrentCharacter before using any of the dispatch methods. ++ * - t0 : Points to tip of backtrack stack ++ * - t1 : Unused. ++ * - t2 : End of input (points to byte after last character in input). ++ * - fp : Frame pointer. Used to access arguments, local variables and ++ * RegExp registers. ++ * - sp : Points to tip of C stack. ++ * ++ * The remaining registers are free for computations. ++ * Each call to a public method should retain this convention. ++ * ++ * The stack will have the following structure: ++ * FIXME(RISCV): Verify that this stack description is correct ++ * ++ * - fp[80] Isolate* isolate (address of the current isolate) kIsolate ++ * kStackFrameHeader ++ * --- sp when called --- ++ * - fp[72] ra Return from RegExp code (ra). kReturnAddress ++ * - fp[64] s9, old-fp Old fp, callee saved(s9). ++ * - fp[0..63] fp..s7 Callee-saved registers fp..s7. ++ * --- frame pointer ---- ++ * - fp[-8] direct_call (1 = direct call from JS, 0 = from runtime) kDirectCall ++ * - fp[-16] stack_base (Top of backtracking stack). kStackHighEnd ++ * - fp[-24] capture array size (may fit multiple sets of matches) kNumOutputRegisters ++ * - fp[-32] int* capture_array (int[num_saved_registers_], for output). kRegisterOutput ++ * - fp[-40] end of input (address of end of string). kInputEnd ++ * - fp[-48] start of input (address of first character in string). kInputStart ++ * - fp[-56] start index (character index of start). kStartIndex ++ * - fp[-64] void* input_string (location of a handle containing the string). kInputString ++ * - fp[-72] success counter (only for global regexps to count matches). kSuccessfulCaptures ++ * - fp[-80] Offset of location before start of input (effectively character kStringStartMinusOne ++ * position -1). Used to initialize capture registers to a ++ * non-position. ++ * --------- The following output registers are 32-bit values. --------- ++ * - fp[-88] register 0 (Only positions must be stored in the first kRegisterZero ++ * - register 1 num_saved_registers_ registers) ++ * - ... ++ * - register num_registers-1 ++ * --- sp --- ++ * ++ * The first num_saved_registers_ registers are initialized to point to ++ * "character -1" in the string (i.e., char_size() bytes before the first ++ * character of the string). The remaining registers start out as garbage. ++ * ++ * The data up to the return address must be placed there by the calling ++ * code and the remaining arguments are passed in registers, e.g. by calling the ++ * code entry as cast to a function with the signature: ++ * int (*match)(String input_string, ++ * int start_index, ++ * Address start, ++ * Address end, ++ * int* capture_output_array, ++ * int num_capture_registers, ++ * byte* stack_area_base, ++ * bool direct_call = false, ++ * Isolate* isolate); ++ * The call is performed by NativeRegExpMacroAssembler::Execute() ++ * (in regexp-macro-assembler.cc) via the GeneratedCode wrapper. ++ * ++ * clang-format on ++ */ ++ ++#define __ ACCESS_MASM(masm_) ++ ++const int RegExpMacroAssemblerRISCV::kRegExpCodeSize; ++ ++RegExpMacroAssemblerRISCV::RegExpMacroAssemblerRISCV(Isolate* isolate, ++ Zone* zone, Mode mode, ++ int registers_to_save) ++ : NativeRegExpMacroAssembler(isolate, zone), ++ masm_(new MacroAssembler(isolate, CodeObjectRequired::kYes, ++ NewAssemblerBuffer(kRegExpCodeSize))), ++ mode_(mode), ++ num_registers_(registers_to_save), ++ num_saved_registers_(registers_to_save), ++ entry_label_(), ++ start_label_(), ++ success_label_(), ++ backtrack_label_(), ++ exit_label_(), ++ internal_failure_label_() { ++ masm_->set_root_array_available(false); ++ ++ DCHECK_EQ(0, registers_to_save % 2); ++ __ jmp(&entry_label_); // We'll write the entry code later. ++ // If the code gets too big or corrupted, an internal exception will be ++ // raised, and we will exit right away. ++ __ bind(&internal_failure_label_); ++ __ li(a0, Operand(FAILURE)); ++ __ Ret(); ++ __ bind(&start_label_); // And then continue from here. ++} ++ ++RegExpMacroAssemblerRISCV::~RegExpMacroAssemblerRISCV() { ++ delete masm_; ++ // Unuse labels in case we throw away the assembler without calling GetCode. ++ entry_label_.Unuse(); ++ start_label_.Unuse(); ++ success_label_.Unuse(); ++ backtrack_label_.Unuse(); ++ exit_label_.Unuse(); ++ check_preempt_label_.Unuse(); ++ stack_overflow_label_.Unuse(); ++ internal_failure_label_.Unuse(); ++} ++ ++int RegExpMacroAssemblerRISCV::stack_limit_slack() { ++ return RegExpStack::kStackLimitSlack; ++} ++ ++void RegExpMacroAssemblerRISCV::AdvanceCurrentPosition(int by) { ++ if (by != 0) { ++ __ Add64(current_input_offset(), current_input_offset(), ++ Operand(by * char_size())); ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::AdvanceRegister(int reg, int by) { ++ DCHECK_LE(0, reg); ++ DCHECK_GT(num_registers_, reg); ++ if (by != 0) { ++ __ Ld(a0, register_location(reg)); ++ __ Add64(a0, a0, Operand(by)); ++ __ Sd(a0, register_location(reg)); ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::Backtrack() { ++ CheckPreemption(); ++ if (has_backtrack_limit()) { ++ Label next; ++ __ Ld(a0, MemOperand(frame_pointer(), kBacktrackCount)); ++ __ Add64(a0, a0, Operand(1)); ++ __ Sd(a0, MemOperand(frame_pointer(), kBacktrackCount)); ++ __ Branch(&next, ne, a0, Operand(backtrack_limit())); ++ ++ // Exceeded limits are treated as a failed match. ++ Fail(); ++ ++ __ bind(&next); ++ } ++ // Pop Code offset from backtrack stack, add Code and jump to location. ++ Pop(a0); ++ __ Add64(a0, a0, code_pointer()); ++ __ Jump(a0); ++} ++ ++void RegExpMacroAssemblerRISCV::Bind(Label* label) { __ bind(label); } ++ ++void RegExpMacroAssemblerRISCV::CheckCharacter(uint32_t c, Label* on_equal) { ++ BranchOrBacktrack(on_equal, eq, current_character(), Operand(c)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckCharacterGT(uc16 limit, ++ Label* on_greater) { ++ BranchOrBacktrack(on_greater, gt, current_character(), Operand(limit)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckAtStart(int cp_offset, ++ Label* on_at_start) { ++ __ Ld(a1, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ __ Add64(a0, current_input_offset(), ++ Operand(-char_size() + cp_offset * char_size())); ++ BranchOrBacktrack(on_at_start, eq, a0, Operand(a1)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotAtStart(int cp_offset, ++ Label* on_not_at_start) { ++ __ Ld(a1, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ __ Add64(a0, current_input_offset(), ++ Operand(-char_size() + cp_offset * char_size())); ++ BranchOrBacktrack(on_not_at_start, ne, a0, Operand(a1)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckCharacterLT(uc16 limit, Label* on_less) { ++ BranchOrBacktrack(on_less, lt, current_character(), Operand(limit)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckGreedyLoop(Label* on_equal) { ++ Label backtrack_non_equal; ++ __ Lw(a0, MemOperand(backtrack_stackpointer(), 0)); ++ __ Branch(&backtrack_non_equal, ne, current_input_offset(), Operand(a0)); ++ __ Add64(backtrack_stackpointer(), backtrack_stackpointer(), ++ Operand(kIntSize)); ++ __ bind(&backtrack_non_equal); ++ BranchOrBacktrack(on_equal, eq, current_input_offset(), Operand(a0)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotBackReferenceIgnoreCase( ++ int start_reg, bool read_backward, bool unicode, Label* on_no_match) { ++ Label fallthrough; ++ __ Ld(a0, register_location(start_reg)); // Index of start of capture. ++ __ Ld(a1, register_location(start_reg + 1)); // Index of end of capture. ++ __ Sub64(a1, a1, a0); // Length of capture. ++ ++ // At this point, the capture registers are either both set or both cleared. ++ // If the capture length is zero, then the capture is either empty or cleared. ++ // Fall through in both cases. ++ __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); ++ ++ if (read_backward) { ++ __ Ld(t1, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ __ Add64(t1, t1, a1); ++ BranchOrBacktrack(on_no_match, le, current_input_offset(), Operand(t1)); ++ } else { ++ __ Add64(t1, a1, current_input_offset()); ++ // Check that there are enough characters left in the input. ++ BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); ++ } ++ ++ if (mode_ == LATIN1) { ++ Label success; ++ Label fail; ++ Label loop_check; ++ ++ // a0 - offset of start of capture. ++ // a1 - length of capture. ++ __ Add64(a0, a0, Operand(end_of_input_address())); ++ __ Add64(a2, end_of_input_address(), Operand(current_input_offset())); ++ if (read_backward) { ++ __ Sub64(a2, a2, Operand(a1)); ++ } ++ __ Add64(a1, a0, Operand(a1)); ++ ++ // a0 - Address of start of capture. ++ // a1 - Address of end of capture. ++ // a2 - Address of current input position. ++ ++ Label loop; ++ __ bind(&loop); ++ __ Lbu(a3, MemOperand(a0, 0)); ++ __ addi(a0, a0, char_size()); ++ __ Lbu(a4, MemOperand(a2, 0)); ++ __ addi(a2, a2, char_size()); ++ ++ __ Branch(&loop_check, eq, a4, Operand(a3)); ++ ++ // Mismatch, try case-insensitive match (converting letters to lower-case). ++ __ Or(a3, a3, Operand(0x20)); // Convert capture character to lower-case. ++ __ Or(a4, a4, Operand(0x20)); // Also convert input character. ++ __ Branch(&fail, ne, a4, Operand(a3)); ++ __ Sub64(a3, a3, Operand('a')); ++ __ Branch(&loop_check, Uless_equal, a3, Operand('z' - 'a')); ++ // Latin-1: Check for values in range [224,254] but not 247. ++ __ Sub64(a3, a3, Operand(224 - 'a')); ++ // Weren't Latin-1 letters. ++ __ Branch(&fail, Ugreater, a3, Operand(254 - 224)); ++ // Check for 247. ++ __ Branch(&fail, eq, a3, Operand(247 - 224)); ++ ++ __ bind(&loop_check); ++ __ Branch(&loop, lt, a0, Operand(a1)); ++ __ jmp(&success); ++ ++ __ bind(&fail); ++ GoTo(on_no_match); ++ ++ __ bind(&success); ++ // Compute new value of character position after the matched part. ++ __ Sub64(current_input_offset(), a2, end_of_input_address()); ++ if (read_backward) { ++ __ Ld(t1, register_location(start_reg)); // Index of start of capture. ++ __ Ld(a2, register_location(start_reg + 1)); // Index of end of capture. ++ __ Add64(current_input_offset(), current_input_offset(), Operand(t1)); ++ __ Sub64(current_input_offset(), current_input_offset(), Operand(a2)); ++ } ++ } else { ++ DCHECK(mode_ == UC16); ++ // Put regexp engine registers on stack. ++ RegList regexp_registers_to_retain = current_input_offset().bit() | ++ current_character().bit() | ++ backtrack_stackpointer().bit(); ++ __ MultiPush(regexp_registers_to_retain); ++ ++ int argument_count = 4; ++ __ PrepareCallCFunction(argument_count, a2); ++ ++ // a0 - offset of start of capture. ++ // a1 - length of capture. ++ ++ // Put arguments into arguments registers. ++ // Parameters are ++ // a0: Address byte_offset1 - Address captured substring's start. ++ // a1: Address byte_offset2 - Address of current character position. ++ // a2: size_t byte_length - length of capture in bytes(!). ++ // a3: Isolate* isolate. ++ ++ // Address of start of capture. ++ __ Add64(a0, a0, Operand(end_of_input_address())); ++ // Length of capture. ++ __ mv(a2, a1); ++ // Save length in callee-save register for use on return. ++ __ mv(s3, a1); ++ // Address of current input position. ++ __ Add64(a1, current_input_offset(), Operand(end_of_input_address())); ++ if (read_backward) { ++ __ Sub64(a1, a1, Operand(s3)); ++ } ++ // Isolate. ++ __ li(a3, Operand(ExternalReference::isolate_address(masm_->isolate()))); ++ ++ { ++ AllowExternalCallThatCantCauseGC scope(masm_); ++ ExternalReference function = ++ unicode ? ExternalReference::re_case_insensitive_compare_unicode( ++ isolate()) ++ : ExternalReference::re_case_insensitive_compare_non_unicode( ++ isolate()); ++ __ CallCFunction(function, argument_count); ++ } ++ ++ // Restore regexp engine registers. ++ __ MultiPop(regexp_registers_to_retain); ++ __ li(code_pointer(), Operand(masm_->CodeObject()), CONSTANT_SIZE); ++ __ Ld(end_of_input_address(), MemOperand(frame_pointer(), kInputEnd)); ++ ++ // Check if function returned non-zero for success or zero for failure. ++ BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); ++ // On success, increment position by length of capture. ++ if (read_backward) { ++ __ Sub64(current_input_offset(), current_input_offset(), Operand(s3)); ++ } else { ++ __ Add64(current_input_offset(), current_input_offset(), Operand(s3)); ++ } ++ } ++ ++ __ bind(&fallthrough); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotBackReference(int start_reg, ++ bool read_backward, ++ Label* on_no_match) { ++ Label fallthrough; ++ ++ // Find length of back-referenced capture. ++ __ Ld(a0, register_location(start_reg)); ++ __ Ld(a1, register_location(start_reg + 1)); ++ __ Sub64(a1, a1, a0); // Length to check. ++ ++ // At this point, the capture registers are either both set or both cleared. ++ // If the capture length is zero, then the capture is either empty or cleared. ++ // Fall through in both cases. ++ __ Branch(&fallthrough, eq, a1, Operand(zero_reg)); ++ ++ if (read_backward) { ++ __ Ld(t1, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ __ Add64(t1, t1, a1); ++ BranchOrBacktrack(on_no_match, le, current_input_offset(), Operand(t1)); ++ } else { ++ __ Add64(t1, a1, current_input_offset()); ++ // Check that there are enough characters left in the input. ++ BranchOrBacktrack(on_no_match, gt, t1, Operand(zero_reg)); ++ } ++ ++ // Compute pointers to match string and capture string. ++ __ Add64(a0, a0, Operand(end_of_input_address())); ++ __ Add64(a2, end_of_input_address(), Operand(current_input_offset())); ++ if (read_backward) { ++ __ Sub64(a2, a2, Operand(a1)); ++ } ++ __ Add64(a1, a1, Operand(a0)); ++ ++ Label loop; ++ __ bind(&loop); ++ if (mode_ == LATIN1) { ++ __ Lbu(a3, MemOperand(a0, 0)); ++ __ addi(a0, a0, char_size()); ++ __ Lbu(a4, MemOperand(a2, 0)); ++ __ addi(a2, a2, char_size()); ++ } else { ++ DCHECK(mode_ == UC16); ++ __ Lhu(a3, MemOperand(a0, 0)); ++ __ addi(a0, a0, char_size()); ++ __ Lhu(a4, MemOperand(a2, 0)); ++ __ addi(a2, a2, char_size()); ++ } ++ BranchOrBacktrack(on_no_match, ne, a3, Operand(a4)); ++ __ Branch(&loop, lt, a0, Operand(a1)); ++ ++ // Move current character position to position after match. ++ __ Sub64(current_input_offset(), a2, end_of_input_address()); ++ if (read_backward) { ++ __ Ld(t1, register_location(start_reg)); // Index of start of capture. ++ __ Ld(a2, register_location(start_reg + 1)); // Index of end of capture. ++ __ Add64(current_input_offset(), current_input_offset(), Operand(t1)); ++ __ Sub64(current_input_offset(), current_input_offset(), Operand(a2)); ++ } ++ __ bind(&fallthrough); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotCharacter(uint32_t c, ++ Label* on_not_equal) { ++ BranchOrBacktrack(on_not_equal, ne, current_character(), Operand(c)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckCharacterAfterAnd(uint32_t c, ++ uint32_t mask, ++ Label* on_equal) { ++ __ And(a0, current_character(), Operand(mask)); ++ Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); ++ BranchOrBacktrack(on_equal, eq, a0, rhs); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotCharacterAfterAnd(uint32_t c, ++ uint32_t mask, ++ Label* on_not_equal) { ++ __ And(a0, current_character(), Operand(mask)); ++ Operand rhs = (c == 0) ? Operand(zero_reg) : Operand(c); ++ BranchOrBacktrack(on_not_equal, ne, a0, rhs); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckNotCharacterAfterMinusAnd( ++ uc16 c, uc16 minus, uc16 mask, Label* on_not_equal) { ++ DCHECK_GT(String::kMaxUtf16CodeUnit, minus); ++ __ Sub64(a0, current_character(), Operand(minus)); ++ __ And(a0, a0, Operand(mask)); ++ BranchOrBacktrack(on_not_equal, ne, a0, Operand(c)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckCharacterInRange(uc16 from, uc16 to, ++ Label* on_in_range) { ++ __ Sub64(a0, current_character(), Operand(from)); ++ // Unsigned lower-or-same condition. ++ BranchOrBacktrack(on_in_range, Uless_equal, a0, Operand(to - from)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckCharacterNotInRange( ++ uc16 from, uc16 to, Label* on_not_in_range) { ++ __ Sub64(a0, current_character(), Operand(from)); ++ // Unsigned higher condition. ++ BranchOrBacktrack(on_not_in_range, Ugreater, a0, Operand(to - from)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckBitInTable(Handle table, ++ Label* on_bit_set) { ++ __ li(a0, Operand(table)); ++ if (mode_ != LATIN1 || kTableMask != String::kMaxOneByteCharCode) { ++ __ And(a1, current_character(), Operand(kTableSize - 1)); ++ __ Add64(a0, a0, a1); ++ } else { ++ __ Add64(a0, a0, current_character()); ++ } ++ ++ __ Lbu(a0, FieldMemOperand(a0, ByteArray::kHeaderSize)); ++ BranchOrBacktrack(on_bit_set, ne, a0, Operand(zero_reg)); ++} ++ ++bool RegExpMacroAssemblerRISCV::CheckSpecialCharacterClass(uc16 type, ++ Label* on_no_match) { ++ // Range checks (c in min..max) are generally implemented by an unsigned ++ // (c - min) <= (max - min) check. ++ switch (type) { ++ case 's': ++ // Match space-characters. ++ if (mode_ == LATIN1) { ++ // One byte space characters are '\t'..'\r', ' ' and \u00a0. ++ Label success; ++ __ Branch(&success, eq, current_character(), Operand(' ')); ++ // Check range 0x09..0x0D. ++ __ Sub64(a0, current_character(), Operand('\t')); ++ __ Branch(&success, Uless_equal, a0, Operand('\r' - '\t')); ++ // \u00a0 (NBSP). ++ BranchOrBacktrack(on_no_match, ne, a0, Operand(0x00A0 - '\t')); ++ __ bind(&success); ++ return true; ++ } ++ return false; ++ case 'S': ++ // The emitted code for generic character classes is good enough. ++ return false; ++ case 'd': ++ // Match Latin1 digits ('0'..'9'). ++ __ Sub64(a0, current_character(), Operand('0')); ++ BranchOrBacktrack(on_no_match, Ugreater, a0, Operand('9' - '0')); ++ return true; ++ case 'D': ++ // Match non Latin1-digits. ++ __ Sub64(a0, current_character(), Operand('0')); ++ BranchOrBacktrack(on_no_match, Uless_equal, a0, Operand('9' - '0')); ++ return true; ++ case '.': { ++ // Match non-newlines (not 0x0A('\n'), 0x0D('\r'), 0x2028 and 0x2029). ++ __ Xor(a0, current_character(), Operand(0x01)); ++ // See if current character is '\n'^1 or '\r'^1, i.e., 0x0B or 0x0C. ++ __ Sub64(a0, a0, Operand(0x0B)); ++ BranchOrBacktrack(on_no_match, Uless_equal, a0, Operand(0x0C - 0x0B)); ++ if (mode_ == UC16) { ++ // Compare original value to 0x2028 and 0x2029, using the already ++ // computed (current_char ^ 0x01 - 0x0B). I.e., check for ++ // 0x201D (0x2028 - 0x0B) or 0x201E. ++ __ Sub64(a0, a0, Operand(0x2028 - 0x0B)); ++ BranchOrBacktrack(on_no_match, Uless_equal, a0, Operand(1)); ++ } ++ return true; ++ } ++ case 'n': { ++ // Match newlines (0x0A('\n'), 0x0D('\r'), 0x2028 and 0x2029). ++ __ Xor(a0, current_character(), Operand(0x01)); ++ // See if current character is '\n'^1 or '\r'^1, i.e., 0x0B or 0x0C. ++ __ Sub64(a0, a0, Operand(0x0B)); ++ if (mode_ == LATIN1) { ++ BranchOrBacktrack(on_no_match, Ugreater, a0, Operand(0x0C - 0x0B)); ++ } else { ++ Label done; ++ BranchOrBacktrack(&done, Uless_equal, a0, Operand(0x0C - 0x0B)); ++ // Compare original value to 0x2028 and 0x2029, using the already ++ // computed (current_char ^ 0x01 - 0x0B). I.e., check for ++ // 0x201D (0x2028 - 0x0B) or 0x201E. ++ __ Sub64(a0, a0, Operand(0x2028 - 0x0B)); ++ BranchOrBacktrack(on_no_match, Ugreater, a0, Operand(1)); ++ __ bind(&done); ++ } ++ return true; ++ } ++ case 'w': { ++ if (mode_ != LATIN1) { ++ // Table is 256 entries, so all Latin1 characters can be tested. ++ BranchOrBacktrack(on_no_match, Ugreater, current_character(), ++ Operand('z')); ++ } ++ ExternalReference map = ++ ExternalReference::re_word_character_map(isolate()); ++ __ li(a0, Operand(map)); ++ __ Add64(a0, a0, current_character()); ++ __ Lbu(a0, MemOperand(a0, 0)); ++ BranchOrBacktrack(on_no_match, eq, a0, Operand(zero_reg)); ++ return true; ++ } ++ case 'W': { ++ Label done; ++ if (mode_ != LATIN1) { ++ // Table is 256 entries, so all Latin1 characters can be tested. ++ __ Branch(&done, Ugreater, current_character(), Operand('z')); ++ } ++ ExternalReference map = ++ ExternalReference::re_word_character_map(isolate()); ++ __ li(a0, Operand(map)); ++ __ Add64(a0, a0, current_character()); ++ __ Lbu(a0, MemOperand(a0, 0)); ++ BranchOrBacktrack(on_no_match, ne, a0, Operand(zero_reg)); ++ if (mode_ != LATIN1) { ++ __ bind(&done); ++ } ++ return true; ++ } ++ case '*': ++ // Match any character. ++ return true; ++ // No custom implementation (yet): s(UC16), S(UC16). ++ default: ++ return false; ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::Fail() { ++ __ li(a0, Operand(FAILURE)); ++ __ jmp(&exit_label_); ++} ++ ++Handle RegExpMacroAssemblerRISCV::GetCode(Handle source) { ++ Label return_a0; ++ if (masm_->has_exception()) { ++ // If the code gets corrupted due to long regular expressions and lack of ++ // space on trampolines, an internal exception flag is set. If this case ++ // is detected, we will jump into exit sequence right away. ++ __ bind_to(&entry_label_, internal_failure_label_.pos()); ++ } else { ++ // Finalize code - write the entry point code now we know how many ++ // registers we need. ++ ++ // Entry code: ++ __ bind(&entry_label_); ++ ++ // Tell the system that we have a stack frame. Because the type is MANUAL, ++ // no is generated. ++ FrameScope scope(masm_, StackFrame::MANUAL); ++ ++ // Actually emit code to start a new stack frame. ++ // Push arguments ++ // Save callee-save registers. ++ // Start new stack frame. ++ // Store link register in existing stack-cell. ++ // Order here should correspond to order of offset constants in header file. ++ // TODO(plind): we save fp..s11, but ONLY use s3 here - use the regs ++ // or dont save. ++ // ++ // FIXME (RISCV): how about saving only s*registers that are actually used? ++ RegList registers_to_retain = ++ fp.bit() | s1.bit() | s2.bit() | s3.bit() | s4.bit() | s5.bit() | ++ s6.bit() | s7.bit() | s8.bit() /*| s9.bit() | s10.bit() | s11.bit()*/; ++ DCHECK(NumRegs(registers_to_retain) == kNumCalleeRegsToRetain); ++ ++ // The remaining arguments are passed in registers, e.g.by calling the code ++ // entry as cast to a function with the signature: ++ // ++ // *int(*match)(String input_string, // a0 ++ // int start_index, // a1 ++ // Address start, // a2 ++ // Address end, // a3 ++ // int*capture_output_array, // a4 ++ // int num_capture_registers, // a5 ++ // byte* stack_area_base, // a6 ++ // bool direct_call = false, // a7 ++ // Isolate * isolate); // on the stack ++ RegList argument_registers = a0.bit() | a1.bit() | a2.bit() | a3.bit() | ++ a4.bit() | a5.bit() | a6.bit() | a7.bit(); ++ ++ // According to MultiPush implementation, registers will be pushed in the ++ // order of ra, fp, then s8, ..., s1, and finally a7,...a0 ++ __ MultiPush(ra.bit() | registers_to_retain | argument_registers); ++ ++ // Set frame pointer in space for it if this is not a direct call ++ // from generated code. ++ __ Add64(frame_pointer(), sp, ++ Operand(NumRegs(argument_registers) * kPointerSize)); ++ ++ STATIC_ASSERT(kSuccessfulCaptures == kInputString - kSystemPointerSize); ++ __ mv(a0, zero_reg); ++ __ push(a0); // Make room for success counter and initialize it to 0. ++ STATIC_ASSERT(kStringStartMinusOne == ++ kSuccessfulCaptures - kSystemPointerSize); ++ __ push(a0); // Make room for "string start - 1" constant. ++ STATIC_ASSERT(kBacktrackCount == kStringStartMinusOne - kSystemPointerSize); ++ __ push(a0); // The backtrack counter ++ ++ // Check if we have space on the stack for registers. ++ Label stack_limit_hit; ++ Label stack_ok; ++ ++ ExternalReference stack_limit = ++ ExternalReference::address_of_jslimit(masm_->isolate()); ++ __ li(a0, Operand(stack_limit)); ++ __ Ld(a0, MemOperand(a0)); ++ __ Sub64(a0, sp, a0); ++ // Handle it if the stack pointer is already below the stack limit. ++ __ Branch(&stack_limit_hit, le, a0, Operand(zero_reg)); ++ // Check if there is room for the variable number of registers above ++ // the stack limit. ++ __ Branch(&stack_ok, Ugreater_equal, a0, ++ Operand(num_registers_ * kPointerSize)); ++ // Exit with OutOfMemory exception. There is not enough space on the stack ++ // for our working registers. ++ __ li(a0, Operand(EXCEPTION)); ++ __ jmp(&return_a0); ++ ++ __ bind(&stack_limit_hit); ++ CallCheckStackGuardState(a0); ++ // If returned value is non-zero, we exit with the returned value as result. ++ __ Branch(&return_a0, ne, a0, Operand(zero_reg)); ++ ++ __ bind(&stack_ok); ++ // Allocate space on stack for registers. ++ __ Sub64(sp, sp, Operand(num_registers_ * kPointerSize)); ++ // Load string end. ++ __ Ld(end_of_input_address(), MemOperand(frame_pointer(), kInputEnd)); ++ // Load input start. ++ __ Ld(a0, MemOperand(frame_pointer(), kInputStart)); ++ // Find negative length (offset of start relative to end). ++ __ Sub64(current_input_offset(), a0, end_of_input_address()); ++ // Set a0 to address of char before start of the input string ++ // (effectively string position -1). ++ __ Ld(a1, MemOperand(frame_pointer(), kStartIndex)); ++ __ Sub64(a0, current_input_offset(), Operand(char_size())); ++ __ slli(t1, a1, (mode_ == UC16) ? 1 : 0); ++ __ Sub64(a0, a0, t1); ++ // Store this value in a local variable, for use when clearing ++ // position registers. ++ __ Sd(a0, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ ++ // Initialize code pointer register ++ __ li(code_pointer(), Operand(masm_->CodeObject()), CONSTANT_SIZE); ++ ++ Label load_char_start_regexp, start_regexp; ++ // Load newline if index is at start, previous character otherwise. ++ __ Branch(&load_char_start_regexp, ne, a1, Operand(zero_reg)); ++ __ li(current_character(), Operand('\n')); ++ __ jmp(&start_regexp); ++ ++ // Global regexp restarts matching here. ++ __ bind(&load_char_start_regexp); ++ // Load previous char as initial value of current character register. ++ LoadCurrentCharacterUnchecked(-1, 1); ++ __ bind(&start_regexp); ++ ++ // Initialize on-stack registers. ++ if (num_saved_registers_ > 0) { // Always is, if generated from a regexp. ++ // Fill saved registers with initial value = start offset - 1. ++ if (num_saved_registers_ > 8) { ++ // Address of register 0. ++ __ Add64(a1, frame_pointer(), Operand(kRegisterZero)); ++ __ li(a2, Operand(num_saved_registers_)); ++ Label init_loop; ++ __ bind(&init_loop); ++ __ Sd(a0, MemOperand(a1)); ++ __ Add64(a1, a1, Operand(-kPointerSize)); ++ __ Sub64(a2, a2, Operand(1)); ++ __ Branch(&init_loop, ne, a2, Operand(zero_reg)); ++ } else { ++ for (int i = 0; i < num_saved_registers_; i++) { ++ __ Sd(a0, register_location(i)); ++ } ++ } ++ } ++ ++ // Initialize backtrack stack pointer. ++ __ Ld(backtrack_stackpointer(), MemOperand(frame_pointer(), kStackHighEnd)); ++ ++ __ jmp(&start_label_); ++ ++ // Exit code: ++ if (success_label_.is_linked()) { ++ // Save captures when successful. ++ __ bind(&success_label_); ++ if (num_saved_registers_ > 0) { ++ // Copy captures to output. ++ __ Ld(a1, MemOperand(frame_pointer(), kInputStart)); ++ __ Ld(a0, MemOperand(frame_pointer(), kRegisterOutput)); ++ __ Ld(a2, MemOperand(frame_pointer(), kStartIndex)); ++ __ Sub64(a1, end_of_input_address(), a1); ++ // a1 is length of input in bytes. ++ if (mode_ == UC16) { ++ __ srli(a1, a1, 1); ++ } ++ // a1 is length of input in characters. ++ __ Add64(a1, a1, Operand(a2)); ++ // a1 is length of string in characters. ++ ++ DCHECK_EQ(0, num_saved_registers_ % 2); ++ // Always an even number of capture registers. This allows us to ++ // unroll the loop once to add an operation between a load of a register ++ // and the following use of that register. ++ for (int i = 0; i < num_saved_registers_; i += 2) { ++ __ Ld(a2, register_location(i)); ++ __ Ld(a3, register_location(i + 1)); ++ if (i == 0 && global_with_zero_length_check()) { ++ // Keep capture start in a4 for the zero-length check later. ++ __ mv(t4, a2); ++ } ++ if (mode_ == UC16) { ++ __ srai(a2, a2, 1); ++ __ Add64(a2, a2, a1); ++ __ srai(a3, a3, 1); ++ __ Add64(a3, a3, a1); ++ } else { ++ __ Add64(a2, a1, Operand(a2)); ++ __ Add64(a3, a1, Operand(a3)); ++ } ++ // V8 expects the output to be an int32_t array. ++ __ Sw(a2, MemOperand(a0)); ++ __ Add64(a0, a0, kIntSize); ++ __ Sw(a3, MemOperand(a0)); ++ __ Add64(a0, a0, kIntSize); ++ } ++ } ++ ++ if (global()) { ++ // Restart matching if the regular expression is flagged as global. ++ __ Ld(a0, MemOperand(frame_pointer(), kSuccessfulCaptures)); ++ __ Ld(a1, MemOperand(frame_pointer(), kNumOutputRegisters)); ++ __ Ld(a2, MemOperand(frame_pointer(), kRegisterOutput)); ++ // Increment success counter. ++ __ Add64(a0, a0, 1); ++ __ Sd(a0, MemOperand(frame_pointer(), kSuccessfulCaptures)); ++ // Capture results have been stored, so the number of remaining global ++ // output registers is reduced by the number of stored captures. ++ __ Sub64(a1, a1, num_saved_registers_); ++ // Check whether we have enough room for another set of capture results. ++ __ Branch(&return_a0, lt, a1, Operand(num_saved_registers_)); ++ ++ __ Sd(a1, MemOperand(frame_pointer(), kNumOutputRegisters)); ++ // Advance the location for output. ++ __ Add64(a2, a2, num_saved_registers_ * kIntSize); ++ __ Sd(a2, MemOperand(frame_pointer(), kRegisterOutput)); ++ ++ // Prepare a0 to initialize registers with its value in the next run. ++ __ Ld(a0, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ ++ if (global_with_zero_length_check()) { ++ // Special case for zero-length matches. ++ // t4: capture start index ++ // Not a zero-length match, restart. ++ __ Branch(&load_char_start_regexp, ne, current_input_offset(), ++ Operand(t4)); ++ // Offset from the end is zero if we already reached the end. ++ __ Branch(&exit_label_, eq, current_input_offset(), ++ Operand(zero_reg)); ++ // Advance current position after a zero-length match. ++ Label advance; ++ __ bind(&advance); ++ __ Add64(current_input_offset(), current_input_offset(), ++ Operand((mode_ == UC16) ? 2 : 1)); ++ if (global_unicode()) CheckNotInSurrogatePair(0, &advance); ++ } ++ ++ __ Branch(&load_char_start_regexp); ++ } else { ++ __ li(a0, Operand(SUCCESS)); ++ } ++ } ++ // Exit and return a0. ++ __ bind(&exit_label_); ++ if (global()) { ++ __ Ld(a0, MemOperand(frame_pointer(), kSuccessfulCaptures)); ++ } ++ ++ __ bind(&return_a0); ++ // Skip sp past regexp registers and local variables.. ++ __ mv(sp, frame_pointer()); ++ ++ // Restore registers fp..s11 and return (restoring ra to pc). ++ __ MultiPop(registers_to_retain | ra.bit()); ++ ++ __ Ret(); ++ ++ // Backtrack code (branch target for conditional backtracks). ++ if (backtrack_label_.is_linked()) { ++ __ bind(&backtrack_label_); ++ Backtrack(); ++ } ++ ++ Label exit_with_exception; ++ ++ // Preempt-code. ++ if (check_preempt_label_.is_linked()) { ++ SafeCallTarget(&check_preempt_label_); ++ // Put regexp engine registers on stack. ++ RegList regexp_registers_to_retain = current_input_offset().bit() | ++ current_character().bit() | ++ backtrack_stackpointer().bit(); ++ __ MultiPush(regexp_registers_to_retain); ++ CallCheckStackGuardState(a0); ++ __ MultiPop(regexp_registers_to_retain); ++ // If returning non-zero, we should end execution with the given ++ // result as return value. ++ __ Branch(&return_a0, ne, a0, Operand(zero_reg)); ++ ++ // String might have moved: Reload end of string from frame. ++ __ Ld(end_of_input_address(), MemOperand(frame_pointer(), kInputEnd)); ++ __ li(code_pointer(), Operand(masm_->CodeObject()), CONSTANT_SIZE); ++ SafeReturn(); ++ } ++ ++ // Backtrack stack overflow code. ++ if (stack_overflow_label_.is_linked()) { ++ SafeCallTarget(&stack_overflow_label_); ++ // Reached if the backtrack-stack limit has been hit. ++ // Put regexp engine registers on stack first. ++ RegList regexp_registers = ++ current_input_offset().bit() | current_character().bit(); ++ __ MultiPush(regexp_registers); ++ ++ // Call GrowStack(backtrack_stackpointer(), &stack_base) ++ static const int num_arguments = 3; ++ __ PrepareCallCFunction(num_arguments, a0); ++ __ mv(a0, backtrack_stackpointer()); ++ __ Add64(a1, frame_pointer(), Operand(kStackHighEnd)); ++ __ li(a2, Operand(ExternalReference::isolate_address(masm_->isolate()))); ++ ExternalReference grow_stack = ++ ExternalReference::re_grow_stack(masm_->isolate()); ++ __ CallCFunction(grow_stack, num_arguments); ++ // Restore regexp registers. ++ __ MultiPop(regexp_registers); ++ // If return nullptr, we have failed to grow the stack, and ++ // must exit with a stack-overflow exception. ++ __ Branch(&exit_with_exception, eq, a0, Operand(zero_reg)); ++ // Otherwise use return value as new stack pointer. ++ __ mv(backtrack_stackpointer(), a0); ++ // Restore saved registers and continue. ++ __ li(code_pointer(), Operand(masm_->CodeObject()), CONSTANT_SIZE); ++ __ Ld(end_of_input_address(), MemOperand(frame_pointer(), kInputEnd)); ++ SafeReturn(); ++ } ++ ++ if (exit_with_exception.is_linked()) { ++ // If any of the code above needed to exit with an exception. ++ __ bind(&exit_with_exception); ++ // Exit with Result EXCEPTION(-1) to signal thrown exception. ++ __ li(a0, Operand(EXCEPTION)); ++ __ jmp(&return_a0); ++ } ++ } ++ ++ CodeDesc code_desc; ++ masm_->GetCode(isolate(), &code_desc); ++ Handle code = ++ Factory::CodeBuilder(isolate(), code_desc, CodeKind::REGEXP) ++ .set_self_reference(masm_->CodeObject()) ++ .Build(); ++ LOG(masm_->isolate(), ++ RegExpCodeCreateEvent(Handle::cast(code), source)); ++ return Handle::cast(code); ++} ++ ++void RegExpMacroAssemblerRISCV::GoTo(Label* to) { ++ if (to == nullptr) { ++ Backtrack(); ++ return; ++ } ++ __ jmp(to); ++ return; ++} ++ ++void RegExpMacroAssemblerRISCV::IfRegisterGE(int reg, int comparand, ++ Label* if_ge) { ++ __ Ld(a0, register_location(reg)); ++ BranchOrBacktrack(if_ge, ge, a0, Operand(comparand)); ++} ++ ++void RegExpMacroAssemblerRISCV::IfRegisterLT(int reg, int comparand, ++ Label* if_lt) { ++ __ Ld(a0, register_location(reg)); ++ BranchOrBacktrack(if_lt, lt, a0, Operand(comparand)); ++} ++ ++void RegExpMacroAssemblerRISCV::IfRegisterEqPos(int reg, Label* if_eq) { ++ __ Ld(a0, register_location(reg)); ++ BranchOrBacktrack(if_eq, eq, a0, Operand(current_input_offset())); ++} ++ ++RegExpMacroAssembler::IrregexpImplementation ++RegExpMacroAssemblerRISCV::Implementation() { ++ return kRISCVImplementation; ++} ++ ++void RegExpMacroAssemblerRISCV::PopCurrentPosition() { ++ Pop(current_input_offset()); ++} ++ ++void RegExpMacroAssemblerRISCV::PopRegister(int register_index) { ++ Pop(a0); ++ __ Sd(a0, register_location(register_index)); ++} ++ ++void RegExpMacroAssemblerRISCV::PushBacktrack(Label* label) { ++ if (label->is_bound()) { ++ int target = label->pos(); ++ __ li(a0, Operand(target + Code::kHeaderSize - kHeapObjectTag)); ++ } else { ++ Assembler::BlockTrampolinePoolScope block_trampoline_pool(masm_); ++ Label after_constant; ++ __ Branch(&after_constant); ++ int offset = masm_->pc_offset(); ++ int cp_offset = offset + Code::kHeaderSize - kHeapObjectTag; ++ __ emit(0); ++ masm_->label_at_put(label, offset); ++ __ bind(&after_constant); ++ if (is_int16(cp_offset)) { ++ __ Lwu(a0, MemOperand(code_pointer(), cp_offset)); ++ } else { ++ __ Add64(a0, code_pointer(), cp_offset); ++ __ Lwu(a0, MemOperand(a0, 0)); ++ } ++ } ++ Push(a0); ++ CheckStackLimit(); ++} ++ ++void RegExpMacroAssemblerRISCV::PushCurrentPosition() { ++ Push(current_input_offset()); ++} ++ ++void RegExpMacroAssemblerRISCV::PushRegister(int register_index, ++ StackCheckFlag check_stack_limit) { ++ __ Ld(a0, register_location(register_index)); ++ Push(a0); ++ if (check_stack_limit) CheckStackLimit(); ++} ++ ++void RegExpMacroAssemblerRISCV::ReadCurrentPositionFromRegister(int reg) { ++ __ Ld(current_input_offset(), register_location(reg)); ++} ++ ++void RegExpMacroAssemblerRISCV::ReadStackPointerFromRegister(int reg) { ++ __ Ld(backtrack_stackpointer(), register_location(reg)); ++ __ Ld(a0, MemOperand(frame_pointer(), kStackHighEnd)); ++ __ Add64(backtrack_stackpointer(), backtrack_stackpointer(), Operand(a0)); ++} ++ ++void RegExpMacroAssemblerRISCV::SetCurrentPositionFromEnd(int by) { ++ Label after_position; ++ __ Branch(&after_position, ge, current_input_offset(), ++ Operand(-by * char_size())); ++ __ li(current_input_offset(), -by * char_size()); ++ // On RegExp code entry (where this operation is used), the character before ++ // the current position is expected to be already loaded. ++ // We have advanced the position, so it's safe to read backwards. ++ LoadCurrentCharacterUnchecked(-1, 1); ++ __ bind(&after_position); ++} ++ ++void RegExpMacroAssemblerRISCV::SetRegister(int register_index, int to) { ++ DCHECK(register_index >= num_saved_registers_); // Reserved for positions! ++ __ li(a0, Operand(to)); ++ __ Sd(a0, register_location(register_index)); ++} ++ ++bool RegExpMacroAssemblerRISCV::Succeed() { ++ __ jmp(&success_label_); ++ return global(); ++} ++ ++void RegExpMacroAssemblerRISCV::WriteCurrentPositionToRegister(int reg, ++ int cp_offset) { ++ if (cp_offset == 0) { ++ __ Sd(current_input_offset(), register_location(reg)); ++ } else { ++ __ Add64(a0, current_input_offset(), Operand(cp_offset * char_size())); ++ __ Sd(a0, register_location(reg)); ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::ClearRegisters(int reg_from, int reg_to) { ++ DCHECK(reg_from <= reg_to); ++ __ Ld(a0, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ for (int reg = reg_from; reg <= reg_to; reg++) { ++ __ Sd(a0, register_location(reg)); ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::WriteStackPointerToRegister(int reg) { ++ __ Ld(a1, MemOperand(frame_pointer(), kStackHighEnd)); ++ __ Sub64(a0, backtrack_stackpointer(), a1); ++ __ Sd(a0, register_location(reg)); ++} ++ ++bool RegExpMacroAssemblerRISCV::CanReadUnaligned() { return false; } ++ ++// Private methods: ++ ++void RegExpMacroAssemblerRISCV::CallCheckStackGuardState(Register scratch) { ++ DCHECK(!isolate()->IsGeneratingEmbeddedBuiltins()); ++ DCHECK(!masm_->options().isolate_independent_code); ++ ++ int stack_alignment = base::OS::ActivationFrameAlignment(); ++ ++ // Align the stack pointer and save the original sp value on the stack. ++ __ mv(scratch, sp); ++ __ Sub64(sp, sp, Operand(kPointerSize)); ++ DCHECK(base::bits::IsPowerOfTwo(stack_alignment)); ++ __ And(sp, sp, Operand(-stack_alignment)); ++ __ Sd(scratch, MemOperand(sp)); ++ ++ __ mv(a2, frame_pointer()); ++ // Code of self. ++ __ li(a1, Operand(masm_->CodeObject()), CONSTANT_SIZE); ++ ++ // We need to make room for the return address on the stack. ++ DCHECK(IsAligned(stack_alignment, kPointerSize)); ++ __ Sub64(sp, sp, Operand(stack_alignment)); ++ ++ // The stack pointer now points to cell where the return address will be ++ // written. Arguments are in registers, meaning we treat the return address as ++ // argument 5. Since DirectCEntry will handle allocating space for the C ++ // argument slots, we don't need to care about that here. This is how the ++ // stack will look (sp meaning the value of sp at this moment): ++ // [sp + 3] - empty slot if needed for alignment. ++ // [sp + 2] - saved sp. ++ // [sp + 1] - second word reserved for return value. ++ // [sp + 0] - first word reserved for return value. ++ ++ // a0 will point to the return address, placed by DirectCEntry. ++ __ mv(a0, sp); ++ ++ ExternalReference stack_guard_check = ++ ExternalReference::re_check_stack_guard_state(masm_->isolate()); ++ __ li(t6, Operand(stack_guard_check)); ++ ++ EmbeddedData d = EmbeddedData::FromBlob(); ++ CHECK(Builtins::IsIsolateIndependent(Builtins::kDirectCEntry)); ++ Address entry = d.InstructionStartOfBuiltin(Builtins::kDirectCEntry); ++ __ li(kScratchReg, Operand(entry, RelocInfo::OFF_HEAP_TARGET)); ++ __ Call(kScratchReg); ++ ++ // DirectCEntry allocated space for the C argument slots so we have to ++ // drop them with the return address from the stack with loading saved sp. ++ // At this point stack must look: ++ // [sp + 7] - empty slot if needed for alignment. ++ // [sp + 6] - saved sp. ++ // [sp + 5] - second word reserved for return value. ++ // [sp + 4] - first word reserved for return value. ++ // [sp + 3] - C argument slot. ++ // [sp + 2] - C argument slot. ++ // [sp + 1] - C argument slot. ++ // [sp + 0] - C argument slot. ++ __ Ld(sp, MemOperand(sp, stack_alignment + kCArgsSlotsSize)); ++ ++ __ li(code_pointer(), Operand(masm_->CodeObject())); ++} ++ ++// Helper function for reading a value out of a stack frame. ++template ++static T& frame_entry(Address re_frame, int frame_offset) { ++ return reinterpret_cast(Memory(re_frame + frame_offset)); ++} ++ ++template ++static T* frame_entry_address(Address re_frame, int frame_offset) { ++ return reinterpret_cast(re_frame + frame_offset); ++} ++ ++int64_t RegExpMacroAssemblerRISCV::CheckStackGuardState(Address* return_address, ++ Address raw_code, ++ Address re_frame) { ++ Code re_code = Code::cast(Object(raw_code)); ++ return NativeRegExpMacroAssembler::CheckStackGuardState( ++ frame_entry(re_frame, kIsolate), ++ static_cast(frame_entry(re_frame, kStartIndex)), ++ static_cast( ++ frame_entry(re_frame, kDirectCall)), ++ return_address, re_code, ++ frame_entry_address
(re_frame, kInputString), ++ frame_entry_address(re_frame, kInputStart), ++ frame_entry_address(re_frame, kInputEnd)); ++} ++ ++MemOperand RegExpMacroAssemblerRISCV::register_location(int register_index) { ++ DCHECK(register_index < (1 << 30)); ++ if (num_registers_ <= register_index) { ++ num_registers_ = register_index + 1; ++ } ++ return MemOperand(frame_pointer(), ++ kRegisterZero - register_index * kPointerSize); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckPosition(int cp_offset, ++ Label* on_outside_input) { ++ if (cp_offset >= 0) { ++ BranchOrBacktrack(on_outside_input, ge, current_input_offset(), ++ Operand(-cp_offset * char_size())); ++ } else { ++ __ Ld(a1, MemOperand(frame_pointer(), kStringStartMinusOne)); ++ __ Add64(a0, current_input_offset(), Operand(cp_offset * char_size())); ++ BranchOrBacktrack(on_outside_input, le, a0, Operand(a1)); ++ } ++} ++ ++void RegExpMacroAssemblerRISCV::BranchOrBacktrack(Label* to, ++ Condition condition, ++ Register rs, ++ const Operand& rt) { ++ if (condition == al) { // Unconditional. ++ if (to == nullptr) { ++ Backtrack(); ++ return; ++ } ++ __ jmp(to); ++ return; ++ } ++ if (to == nullptr) { ++ __ Branch(&backtrack_label_, condition, rs, rt); ++ return; ++ } ++ __ Branch(to, condition, rs, rt); ++} ++ ++void RegExpMacroAssemblerRISCV::SafeCall(Label* to, Condition cond, Register rs, ++ const Operand& rt) { ++ __ BranchAndLink(to, cond, rs, rt); ++} ++ ++void RegExpMacroAssemblerRISCV::SafeReturn() { ++ __ pop(ra); ++ __ Add64(t1, ra, Operand(masm_->CodeObject())); ++ __ Jump(t1); ++} ++ ++void RegExpMacroAssemblerRISCV::SafeCallTarget(Label* name) { ++ __ bind(name); ++ __ Sub64(ra, ra, Operand(masm_->CodeObject())); ++ __ push(ra); ++} ++ ++void RegExpMacroAssemblerRISCV::Push(Register source) { ++ DCHECK(source != backtrack_stackpointer()); ++ __ Add64(backtrack_stackpointer(), backtrack_stackpointer(), ++ Operand(-kIntSize)); ++ __ Sw(source, MemOperand(backtrack_stackpointer())); ++} ++ ++void RegExpMacroAssemblerRISCV::Pop(Register target) { ++ DCHECK(target != backtrack_stackpointer()); ++ __ Lw(target, MemOperand(backtrack_stackpointer())); ++ __ Add64(backtrack_stackpointer(), backtrack_stackpointer(), kIntSize); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckPreemption() { ++ // Check for preemption. ++ ExternalReference stack_limit = ++ ExternalReference::address_of_jslimit(masm_->isolate()); ++ __ li(a0, Operand(stack_limit)); ++ __ Ld(a0, MemOperand(a0)); ++ SafeCall(&check_preempt_label_, Uless_equal, sp, Operand(a0)); ++} ++ ++void RegExpMacroAssemblerRISCV::CheckStackLimit() { ++ ExternalReference stack_limit = ++ ExternalReference::address_of_regexp_stack_limit_address( ++ masm_->isolate()); ++ ++ __ li(a0, Operand(stack_limit)); ++ __ Ld(a0, MemOperand(a0)); ++ SafeCall(&stack_overflow_label_, Uless_equal, backtrack_stackpointer(), ++ Operand(a0)); ++} ++ ++void RegExpMacroAssemblerRISCV::LoadCurrentCharacterUnchecked(int cp_offset, ++ int characters) { ++ Register offset = current_input_offset(); ++ if (cp_offset != 0) { ++ // t4 is not being used to store the capture start index at this point. ++ __ Add64(t4, current_input_offset(), Operand(cp_offset * char_size())); ++ offset = t4; ++ } ++ // We assume that we cannot do unaligned loads on RISC-V, so this function ++ // must only be used to load a single character at a time. ++ DCHECK_EQ(1, characters); ++ __ Add64(t1, end_of_input_address(), Operand(offset)); ++ if (mode_ == LATIN1) { ++ __ Lbu(current_character(), MemOperand(t1, 0)); ++ } else { ++ DCHECK(mode_ == UC16); ++ __ Lhu(current_character(), MemOperand(t1, 0)); ++ } ++} ++ ++#undef __ ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_TARGET_ARCH_RISCV64 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/regexp/riscv64/regexp-macro-assembler-riscv64.h +@@ -0,0 +1,213 @@ ++// Copyright 2011 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_REGEXP_RISCV_REGEXP_MACRO_ASSEMBLER_RISCV_H_ ++#define V8_REGEXP_RISCV_REGEXP_MACRO_ASSEMBLER_RISCV_H_ ++ ++#include "src/codegen/macro-assembler.h" ++#include "src/codegen/riscv64/assembler-riscv64.h" ++#include "src/regexp/regexp-macro-assembler.h" ++ ++namespace v8 { ++namespace internal { ++ ++class V8_EXPORT_PRIVATE RegExpMacroAssemblerRISCV ++ : public NativeRegExpMacroAssembler { ++ public: ++ RegExpMacroAssemblerRISCV(Isolate* isolate, Zone* zone, Mode mode, ++ int registers_to_save); ++ virtual ~RegExpMacroAssemblerRISCV(); ++ virtual int stack_limit_slack(); ++ virtual void AdvanceCurrentPosition(int by); ++ virtual void AdvanceRegister(int reg, int by); ++ virtual void Backtrack(); ++ virtual void Bind(Label* label); ++ virtual void CheckAtStart(int cp_offset, Label* on_at_start); ++ virtual void CheckCharacter(uint32_t c, Label* on_equal); ++ virtual void CheckCharacterAfterAnd(uint32_t c, uint32_t mask, ++ Label* on_equal); ++ virtual void CheckCharacterGT(uc16 limit, Label* on_greater); ++ virtual void CheckCharacterLT(uc16 limit, Label* on_less); ++ // A "greedy loop" is a loop that is both greedy and with a simple ++ // body. It has a particularly simple implementation. ++ virtual void CheckGreedyLoop(Label* on_tos_equals_current_position); ++ virtual void CheckNotAtStart(int cp_offset, Label* on_not_at_start); ++ virtual void CheckNotBackReference(int start_reg, bool read_backward, ++ Label* on_no_match); ++ virtual void CheckNotBackReferenceIgnoreCase(int start_reg, ++ bool read_backward, bool unicode, ++ Label* on_no_match); ++ virtual void CheckNotCharacter(uint32_t c, Label* on_not_equal); ++ virtual void CheckNotCharacterAfterAnd(uint32_t c, uint32_t mask, ++ Label* on_not_equal); ++ virtual void CheckNotCharacterAfterMinusAnd(uc16 c, uc16 minus, uc16 mask, ++ Label* on_not_equal); ++ virtual void CheckCharacterInRange(uc16 from, uc16 to, Label* on_in_range); ++ virtual void CheckCharacterNotInRange(uc16 from, uc16 to, ++ Label* on_not_in_range); ++ virtual void CheckBitInTable(Handle table, Label* on_bit_set); ++ ++ // Checks whether the given offset from the current position is before ++ // the end of the string. ++ virtual void CheckPosition(int cp_offset, Label* on_outside_input); ++ virtual bool CheckSpecialCharacterClass(uc16 type, Label* on_no_match); ++ virtual void Fail(); ++ virtual Handle GetCode(Handle source); ++ virtual void GoTo(Label* label); ++ virtual void IfRegisterGE(int reg, int comparand, Label* if_ge); ++ virtual void IfRegisterLT(int reg, int comparand, Label* if_lt); ++ virtual void IfRegisterEqPos(int reg, Label* if_eq); ++ virtual IrregexpImplementation Implementation(); ++ virtual void LoadCurrentCharacterUnchecked(int cp_offset, ++ int character_count); ++ virtual void PopCurrentPosition(); ++ virtual void PopRegister(int register_index); ++ virtual void PushBacktrack(Label* label); ++ virtual void PushCurrentPosition(); ++ virtual void PushRegister(int register_index, ++ StackCheckFlag check_stack_limit); ++ virtual void ReadCurrentPositionFromRegister(int reg); ++ virtual void ReadStackPointerFromRegister(int reg); ++ virtual void SetCurrentPositionFromEnd(int by); ++ virtual void SetRegister(int register_index, int to); ++ virtual bool Succeed(); ++ virtual void WriteCurrentPositionToRegister(int reg, int cp_offset); ++ virtual void ClearRegisters(int reg_from, int reg_to); ++ virtual void WriteStackPointerToRegister(int reg); ++ virtual bool CanReadUnaligned(); ++ ++ // Called from RegExp if the stack-guard is triggered. ++ // If the code object is relocated, the return address is fixed before ++ // returning. ++ // {raw_code} is an Address because this is called via ExternalReference. ++ static int64_t CheckStackGuardState(Address* return_address, Address raw_code, ++ Address re_frame); ++ ++ void print_regexp_frame_constants(); ++ ++ private: ++ // Offsets from frame_pointer() of function parameters and stored registers. ++ static const int kFramePointer = 0; ++ ++ // Above the frame pointer - Stored registers and stack passed parameters. ++ // Registers s1 to s8, fp, and ra. ++ static const int kStoredRegisters = kFramePointer; ++ // Return address (stored from link register, read into pc on return). ++ ++ // This 9 is 8 s-regs (s1..s8) plus fp. ++ static const int kNumCalleeRegsToRetain = 9; ++ static const int kReturnAddress = ++ kStoredRegisters + kNumCalleeRegsToRetain * kPointerSize; ++ ++ // Stack frame header. ++ static const int kStackFrameHeader = kReturnAddress; ++ // Stack parameters placed by caller. ++ static const int kIsolate = kStackFrameHeader + kPointerSize; ++ ++ // Below the frame pointer. ++ // Register parameters stored by setup code. ++ static const int kDirectCall = kFramePointer - kPointerSize; ++ static const int kStackHighEnd = kDirectCall - kPointerSize; ++ static const int kNumOutputRegisters = kStackHighEnd - kPointerSize; ++ static const int kRegisterOutput = kNumOutputRegisters - kPointerSize; ++ static const int kInputEnd = kRegisterOutput - kPointerSize; ++ static const int kInputStart = kInputEnd - kPointerSize; ++ static const int kStartIndex = kInputStart - kPointerSize; ++ static const int kInputString = kStartIndex - kPointerSize; ++ // When adding local variables remember to push space for them in ++ // the frame in GetCode. ++ static const int kSuccessfulCaptures = kInputString - kPointerSize; ++ static const int kStringStartMinusOne = kSuccessfulCaptures - kPointerSize; ++ static const int kBacktrackCount = kStringStartMinusOne - kSystemPointerSize; ++ // First register address. Following registers are below it on the stack. ++ static const int kRegisterZero = kBacktrackCount - kSystemPointerSize; ++ ++ // Initial size of code buffer. ++ static const int kRegExpCodeSize = 1024; ++ ++ // Check whether preemption has been requested. ++ void CheckPreemption(); ++ ++ // Check whether we are exceeding the stack limit on the backtrack stack. ++ void CheckStackLimit(); ++ ++ // Generate a call to CheckStackGuardState. ++ void CallCheckStackGuardState(Register scratch); ++ ++ // The ebp-relative location of a regexp register. ++ MemOperand register_location(int register_index); ++ ++ // Register holding the current input position as negative offset from ++ // the end of the string. ++ inline Register current_input_offset() { return a6; } ++ ++ // The register containing the current character after LoadCurrentCharacter. ++ inline Register current_character() { return a7; } ++ ++ // Register holding address of the end of the input string. ++ inline Register end_of_input_address() { return t2; } ++ ++ // Register holding the frame address. Local variables, parameters and ++ // regexp registers are addressed relative to this. ++ inline Register frame_pointer() { return fp; } ++ ++ // The register containing the backtrack stack top. Provides a meaningful ++ // name to the register. ++ inline Register backtrack_stackpointer() { return t0; } ++ ++ // Register holding pointer to the current code object. ++ inline Register code_pointer() { return a5; } ++ ++ // Byte size of chars in the string to match (decided by the Mode argument). ++ inline int char_size() { return static_cast(mode_); } ++ ++ // Equivalent to a conditional branch to the label, unless the label ++ // is nullptr, in which case it is a conditional Backtrack. ++ void BranchOrBacktrack(Label* to, Condition condition, Register rs, ++ const Operand& rt); ++ ++ // Call and return internally in the generated code in a way that ++ // is GC-safe (i.e., doesn't leave absolute code addresses on the stack) ++ inline void SafeCall(Label* to, Condition cond, Register rs, ++ const Operand& rt); ++ inline void SafeReturn(); ++ inline void SafeCallTarget(Label* name); ++ ++ // Pushes the value of a register on the backtrack stack. Decrements the ++ // stack pointer by a word size and stores the register's value there. ++ inline void Push(Register source); ++ ++ // Pops a value from the backtrack stack. Reads the word at the stack pointer ++ // and increments it by a word size. ++ inline void Pop(Register target); ++ ++ Isolate* isolate() const { return masm_->isolate(); } ++ ++ MacroAssembler* masm_; ++ ++ // Which mode to generate code for (Latin1 or UC16). ++ Mode mode_; ++ ++ // One greater than maximal register index actually used. ++ int num_registers_; ++ ++ // Number of registers to output at the end (the saved registers ++ // are always 0..num_saved_registers_-1). ++ int num_saved_registers_; ++ ++ // Labels used internally. ++ Label entry_label_; ++ Label start_label_; ++ Label success_label_; ++ Label backtrack_label_; ++ Label exit_label_; ++ Label check_preempt_label_; ++ Label stack_overflow_label_; ++ Label internal_failure_label_; ++}; ++ ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_REGEXP_RISCV_REGEXP_MACRO_ASSEMBLER_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/runtime/runtime-atomics.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/runtime/runtime-atomics.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/runtime/runtime-atomics.cc +@@ -19,7 +19,8 @@ namespace internal { + + // Other platforms have CSA support, see builtins-sharedarraybuffer-gen.h. + #if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 || \ +- V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X ++ V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X || \ ++ V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + + namespace { + +@@ -568,6 +569,6 @@ RUNTIME_FUNCTION(Runtime_AtomicsXor) { U + + #endif // V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_PPC64 + // || V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_S390 || V8_TARGET_ARCH_S390X +- ++ // || V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV + } // namespace internal + } // namespace v8 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/snapshot/deserializer.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/snapshot/deserializer.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/snapshot/deserializer.h +@@ -29,9 +29,10 @@ class Object; + + // Used for platforms with embedded constant pools to trigger deserialization + // of objects found in code. +-#if defined(V8_TARGET_ARCH_MIPS) || defined(V8_TARGET_ARCH_MIPS64) || \ +- defined(V8_TARGET_ARCH_PPC) || defined(V8_TARGET_ARCH_S390) || \ +- defined(V8_TARGET_ARCH_PPC64) || V8_EMBEDDED_CONSTANT_POOL ++#if defined(V8_TARGET_ARCH_MIPS) || defined(V8_TARGET_ARCH_MIPS64) || \ ++ defined(V8_TARGET_ARCH_PPC) || defined(V8_TARGET_ARCH_S390) || \ ++ defined(V8_TARGET_ARCH_PPC64) || defined(V8_TARGET_ARCH_RISCV64) || \ ++ defined(V8_TARGET_ARCH_RISCV) || V8_EMBEDDED_CONSTANT_POOL + #define V8_CODE_EMBEDS_OBJECT_POINTER 1 + #else + #define V8_CODE_EMBEDS_OBJECT_POINTER 0 +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler-defs.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler-defs.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler-defs.h +@@ -69,6 +69,23 @@ constexpr RegList kLiftoffAssemblerFpCac + d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d16, d17, + d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29); + ++#elif V8_TARGET_ARCH_RISCV64 ++ ++// Any change of kLiftoffAssemblerGpCacheRegs also need to update ++// kPushedGpRegs in frame-constants-riscv64.h ++constexpr RegList kLiftoffAssemblerGpCacheRegs = ++ Register::ListOf(a0, a1, a2, a3, a4, a5, a6, a7, t0, t1, t2, s7); ++ ++// Any change of kLiftoffAssemblerGpCacheRegs also need to update ++// kPushedFpRegs in frame-constants-riscv64.h ++constexpr RegList kLiftoffAssemblerFpCacheRegs = ++ DoubleRegister::ListOf(ft0, ft1, ft2, ft3, ft4, ft5, ft6, ft7, fa0, fa1, ++ fa2, fa3, fa4, fa5, fa6, fa7, ft8, ft9, ft10, ft11); ++ ++#elif V8_TARGET_ARCH_RISCV ++ ++#error RISCV (32) architecture not supported yet ++ + #else + + constexpr RegList kLiftoffAssemblerGpCacheRegs = 0xff; +@@ -116,6 +133,18 @@ constexpr Condition kUnsignedLessEqual = + constexpr Condition kUnsignedGreaterThan = hi; + constexpr Condition kUnsignedGreaterEqual = hs; + ++#elif V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV ++constexpr Condition kEqual = eq; ++constexpr Condition kUnequal = ne; ++constexpr Condition kSignedLessThan = lt; ++constexpr Condition kSignedLessEqual = le; ++constexpr Condition kSignedGreaterThan = gt; ++constexpr Condition kSignedGreaterEqual = ge; ++constexpr Condition kUnsignedLessThan = ult; ++constexpr Condition kUnsignedLessEqual = ule; ++constexpr Condition kUnsignedGreaterThan = ugt; ++constexpr Condition kUnsignedGreaterEqual = uge; ++ + #else + + // On unimplemented platforms, just make this compile. +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/liftoff-assembler.h +@@ -1353,6 +1353,10 @@ class LiftoffStackSlots { + #include "src/wasm/baseline/mips64/liftoff-assembler-mips64.h" + #elif V8_TARGET_ARCH_S390 + #include "src/wasm/baseline/s390/liftoff-assembler-s390.h" ++#elif V8_TARGET_ARCH_RISCV64 ++#include "src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h" ++#elif V8_TARGET_ARCH_RISCV ++#include "src/wasm/baseline/riscv/liftoff-assembler-riscv.h" + #else + #error Unsupported architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h +=================================================================== +--- /dev/null ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h +@@ -0,0 +1,2335 @@ ++// Copyright 2017 the V8 project authors. All rights reserved. ++// Use of this source code is governed by a BSD-style license that can be ++// found in the LICENSE file. ++ ++#ifndef V8_WASM_BASELINE_RISCV_LIFTOFF_ASSEMBLER_RISCV_H_ ++#define V8_WASM_BASELINE_RISCV_LIFTOFF_ASSEMBLER_RISCV_H_ ++ ++#include "src/wasm/baseline/liftoff-assembler.h" ++ ++namespace v8 { ++namespace internal { ++namespace wasm { ++ ++namespace liftoff { ++ ++// Liftoff Frames. ++// ++// slot Frame ++// +--------------------+--------------------------- ++// n+4 | optional padding slot to keep the stack 16 byte aligned. ++// n+3 | parameter n | ++// ... | ... | ++// 4 | parameter 1 | or parameter 2 ++// 3 | parameter 0 | or parameter 1 ++// 2 | (result address) | or parameter 0 ++// -----+--------------------+--------------------------- ++// 1 | return addr (ra) | ++// 0 | previous frame (fp)| ++// -----+--------------------+ <-- frame ptr (fp) ++// -1 | 0xa: WASM | ++// -2 | instance | ++// -----+--------------------+--------------------------- ++// -3 | slot 0 | ^ ++// -4 | slot 1 | | ++// | | Frame slots ++// | | | ++// | | v ++// | optional padding slot to keep the stack 16 byte aligned. ++// -----+--------------------+ <-- stack ptr (sp) ++// ++ ++// fp-8 holds the stack marker, fp-16 is the instance parameter. ++constexpr int kInstanceOffset = 16; ++ ++inline MemOperand GetStackSlot(int offset) { return MemOperand(fp, -offset); } ++ ++inline MemOperand GetInstanceOperand() { return GetStackSlot(kInstanceOffset); } ++ ++inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, MemOperand src, ++ ValueType type) { ++ switch (type.kind()) { ++ case ValueType::kI32: ++ assm->Lw(dst.gp(), src); ++ break; ++ case ValueType::kI64: ++ assm->Ld(dst.gp(), src); ++ break; ++ case ValueType::kF32: ++ assm->LoadFloat(dst.fp(), src); ++ break; ++ case ValueType::kF64: ++ assm->LoadDouble(dst.fp(), src); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, ++ LiftoffRegister src, ValueType type) { ++ MemOperand dst(base, offset); ++ switch (type.kind()) { ++ case ValueType::kI32: ++ assm->Usw(src.gp(), dst); ++ break; ++ case ValueType::kI64: ++ assm->Usd(src.gp(), dst); ++ break; ++ case ValueType::kF32: ++ assm->UStoreFloat(src.fp(), dst, t5); ++ break; ++ case ValueType::kF64: ++ assm->UStoreDouble(src.fp(), dst, t5); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++inline void push(LiftoffAssembler* assm, LiftoffRegister reg, ValueType type) { ++ switch (type.kind()) { ++ case ValueType::kI32: ++ assm->addi(sp, sp, -kSystemPointerSize); ++ assm->Sw(reg.gp(), MemOperand(sp, 0)); ++ break; ++ case ValueType::kI64: ++ assm->push(reg.gp()); ++ break; ++ case ValueType::kF32: ++ assm->addi(sp, sp, -kSystemPointerSize); ++ assm->StoreFloat(reg.fp(), MemOperand(sp, 0)); ++ break; ++ case ValueType::kF64: ++ assm->addi(sp, sp, -kSystemPointerSize); ++ assm->StoreDouble(reg.fp(), MemOperand(sp, 0)); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++#if defined(V8_TARGET_BIG_ENDIAN) ++inline void ChangeEndiannessLoad(LiftoffAssembler* assm, LiftoffRegister dst, ++ LoadType type, LiftoffRegList pinned) { ++ bool is_float = false; ++ LiftoffRegister tmp = dst; ++ switch (type.value()) { ++ case LoadType::kI64Load8U: ++ case LoadType::kI64Load8S: ++ case LoadType::kI32Load8U: ++ case LoadType::kI32Load8S: ++ // No need to change endianness for byte size. ++ return; ++ case LoadType::kF32Load: ++ is_float = true; ++ tmp = assm->GetUnusedRegister(kGpReg, pinned); ++ assm->emit_type_conversion(kExprI32ReinterpretF32, tmp, dst); ++ V8_FALLTHROUGH; ++ case LoadType::kI64Load32U: ++ assm->TurboAssembler::ByteSwapUnsigned(tmp.gp(), tmp.gp(), 4); ++ break; ++ case LoadType::kI32Load: ++ case LoadType::kI64Load32S: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 4); ++ break; ++ case LoadType::kI32Load16S: ++ case LoadType::kI64Load16S: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 2); ++ break; ++ case LoadType::kI32Load16U: ++ case LoadType::kI64Load16U: ++ assm->TurboAssembler::ByteSwapUnsigned(tmp.gp(), tmp.gp(), 2); ++ break; ++ case LoadType::kF64Load: ++ is_float = true; ++ tmp = assm->GetUnusedRegister(kGpReg, pinned); ++ assm->emit_type_conversion(kExprI64ReinterpretF64, tmp, dst); ++ V8_FALLTHROUGH; ++ case LoadType::kI64Load: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 8); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ if (is_float) { ++ switch (type.value()) { ++ case LoadType::kF32Load: ++ assm->emit_type_conversion(kExprF32ReinterpretI32, dst, tmp); ++ break; ++ case LoadType::kF64Load: ++ assm->emit_type_conversion(kExprF64ReinterpretI64, dst, tmp); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++} ++ ++inline void ChangeEndiannessStore(LiftoffAssembler* assm, LiftoffRegister src, ++ StoreType type, LiftoffRegList pinned) { ++ bool is_float = false; ++ LiftoffRegister tmp = src; ++ switch (type.value()) { ++ case StoreType::kI64Store8: ++ case StoreType::kI32Store8: ++ // No need to change endianness for byte size. ++ return; ++ case StoreType::kF32Store: ++ is_float = true; ++ tmp = assm->GetUnusedRegister(kGpReg, pinned); ++ assm->emit_type_conversion(kExprI32ReinterpretF32, tmp, src); ++ V8_FALLTHROUGH; ++ case StoreType::kI32Store: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 4); ++ break; ++ case StoreType::kI32Store16: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 2); ++ break; ++ case StoreType::kF64Store: ++ is_float = true; ++ tmp = assm->GetUnusedRegister(kGpReg, pinned); ++ assm->emit_type_conversion(kExprI64ReinterpretF64, tmp, src); ++ V8_FALLTHROUGH; ++ case StoreType::kI64Store: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 8); ++ break; ++ case StoreType::kI64Store32: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 4); ++ break; ++ case StoreType::kI64Store16: ++ assm->TurboAssembler::ByteSwapSigned(tmp.gp(), tmp.gp(), 2); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ if (is_float) { ++ switch (type.value()) { ++ case StoreType::kF32Store: ++ assm->emit_type_conversion(kExprF32ReinterpretI32, src, tmp); ++ break; ++ case StoreType::kF64Store: ++ assm->emit_type_conversion(kExprF64ReinterpretI64, src, tmp); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ } ++} ++#endif // V8_TARGET_BIG_ENDIAN ++ ++} // namespace liftoff ++ ++int LiftoffAssembler::PrepareStackFrame() { ++ int offset = pc_offset(); ++ // When constant that represents size of stack frame can't be represented ++ // as 16bit we need three instructions to add it to sp, so we reserve space ++ // for this case. ++ Add64(sp, sp, Operand(0L)); ++ nop(); ++ nop(); ++ return offset; ++} ++ ++void LiftoffAssembler::PrepareTailCall(int num_callee_stack_params, ++ int stack_param_delta) { ++ UseScratchRegisterScope temps(this); ++ Register scratch = temps.Acquire(); ++ ++ // Push the return address and frame pointer to complete the stack frame. ++ Ld(scratch, MemOperand(fp, 8)); ++ Push(scratch); ++ Ld(scratch, MemOperand(fp, 0)); ++ Push(scratch); ++ ++ // Shift the whole frame upwards. ++ int slot_count = num_callee_stack_params + 2; ++ for (int i = slot_count - 1; i >= 0; --i) { ++ Ld(scratch, MemOperand(sp, i * 8)); ++ Sd(scratch, MemOperand(fp, (i - stack_param_delta) * 8)); ++ } ++ ++ // Set the new stack and frame pointer. ++ Add64(sp, fp, -stack_param_delta * 8); ++ Pop(ra, fp); ++} ++ ++void LiftoffAssembler::PatchPrepareStackFrame(int offset, int frame_size) { ++ // We can't run out of space, just pass anything big enough to not cause the ++ // assembler to try to grow the buffer. ++ constexpr int kAvailableSpace = 256; ++ TurboAssembler patching_assembler( ++ nullptr, AssemblerOptions{}, CodeObjectRequired::kNo, ++ ExternalAssemblerBuffer(buffer_start_ + offset, kAvailableSpace)); ++ // If bytes can be represented as 16bit, addi will be generated and two ++ // nops will stay untouched. Otherwise, lui-ori sequence will load it to ++ // register and, as third instruction, daddu will be generated. ++ patching_assembler.Add64(sp, sp, Operand(-frame_size)); ++} ++ ++void LiftoffAssembler::FinishCode() {} ++ ++void LiftoffAssembler::AbortCompilation() {} ++ ++// static ++constexpr int LiftoffAssembler::StaticStackFrameSize() { ++ return liftoff::kInstanceOffset; ++} ++ ++int LiftoffAssembler::SlotSizeForType(ValueType type) { ++ switch (type.kind()) { ++ case ValueType::kS128: ++ return type.element_size_bytes(); ++ default: ++ return kStackSlotSize; ++ } ++} ++ ++bool LiftoffAssembler::NeedsAlignment(ValueType type) { ++ switch (type.kind()) { ++ case ValueType::kS128: ++ return true; ++ default: ++ // No alignment because all other types are kStackSlotSize. ++ return false; ++ } ++} ++ ++void LiftoffAssembler::LoadConstant(LiftoffRegister reg, WasmValue value, ++ RelocInfo::Mode rmode) { ++ switch (value.type().kind()) { ++ case ValueType::kI32: ++ TurboAssembler::li(reg.gp(), Operand(value.to_i32(), rmode)); ++ break; ++ case ValueType::kI64: ++ TurboAssembler::li(reg.gp(), Operand(value.to_i64(), rmode)); ++ break; ++ case ValueType::kF32: ++ TurboAssembler::LoadFPRImmediate(reg.fp(), ++ value.to_f32_boxed().get_bits()); ++ break; ++ case ValueType::kF64: ++ TurboAssembler::LoadFPRImmediate(reg.fp(), ++ value.to_f64_boxed().get_bits()); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void LiftoffAssembler::LoadFromInstance(Register dst, uint32_t offset, ++ int size) { ++ DCHECK_LE(offset, kMaxInt); ++ Ld(dst, liftoff::GetInstanceOperand()); ++ DCHECK(size == 4 || size == 8); ++ if (size == 4) { ++ Lw(dst, MemOperand(dst, offset)); ++ } else { ++ Ld(dst, MemOperand(dst, offset)); ++ } ++} ++ ++void LiftoffAssembler::LoadTaggedPointerFromInstance(Register dst, ++ uint32_t offset) { ++ LoadFromInstance(dst, offset, kTaggedSize); ++} ++ ++void LiftoffAssembler::SpillInstance(Register instance) { ++ Sd(instance, liftoff::GetInstanceOperand()); ++} ++ ++void LiftoffAssembler::FillInstanceInto(Register dst) { ++ Ld(dst, liftoff::GetInstanceOperand()); ++} ++ ++void LiftoffAssembler::LoadTaggedPointer(Register dst, Register src_addr, ++ Register offset_reg, ++ int32_t offset_imm, ++ LiftoffRegList pinned) { ++ STATIC_ASSERT(kTaggedSize == kInt64Size); ++ Load(LiftoffRegister(dst), src_addr, offset_reg, ++ static_cast(offset_imm), LoadType::kI64Load, pinned); ++} ++ ++void LiftoffAssembler::StoreTaggedPointer(Register dst_addr, ++ int32_t offset_imm, ++ LiftoffRegister src, ++ LiftoffRegList pinned) { ++ bailout(kRefTypes, "GlobalSet"); ++} ++ ++void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr, ++ Register offset_reg, uint32_t offset_imm, ++ LoadType type, LiftoffRegList pinned, ++ uint32_t* protected_load_pc, bool is_load_mem) { ++ Register src = no_reg; ++ if (offset_reg != no_reg) { ++ src = GetUnusedRegister(kGpReg, pinned).gp(); ++ emit_ptrsize_add(src, src_addr, offset_reg); ++ } ++ MemOperand src_op = (offset_reg != no_reg) ? MemOperand(src, offset_imm) ++ : MemOperand(src_addr, offset_imm); ++ ++ if (protected_load_pc) *protected_load_pc = pc_offset(); ++ switch (type.value()) { ++ case LoadType::kI32Load8U: ++ case LoadType::kI64Load8U: ++ Lbu(dst.gp(), src_op); ++ break; ++ case LoadType::kI32Load8S: ++ case LoadType::kI64Load8S: ++ Lb(dst.gp(), src_op); ++ break; ++ case LoadType::kI32Load16U: ++ case LoadType::kI64Load16U: ++ TurboAssembler::Ulhu(dst.gp(), src_op); ++ break; ++ case LoadType::kI32Load16S: ++ case LoadType::kI64Load16S: ++ TurboAssembler::Ulh(dst.gp(), src_op); ++ break; ++ case LoadType::kI64Load32U: ++ TurboAssembler::Ulwu(dst.gp(), src_op); ++ break; ++ case LoadType::kI32Load: ++ case LoadType::kI64Load32S: ++ TurboAssembler::Ulw(dst.gp(), src_op); ++ break; ++ case LoadType::kI64Load: ++ TurboAssembler::Uld(dst.gp(), src_op); ++ break; ++ case LoadType::kF32Load: ++ TurboAssembler::ULoadFloat(dst.fp(), src_op, t5); ++ break; ++ case LoadType::kF64Load: ++ TurboAssembler::ULoadDouble(dst.fp(), src_op, t5); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++#if defined(V8_TARGET_BIG_ENDIAN) ++ if (is_load_mem) { ++ pinned.set(src_op.rm()); ++ liftoff::ChangeEndiannessLoad(this, dst, type, pinned); ++ } ++#endif ++} ++ ++void LiftoffAssembler::Store(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister src, ++ StoreType type, LiftoffRegList pinned, ++ uint32_t* protected_store_pc, bool is_store_mem) { ++ Register dst = no_reg; ++ MemOperand dst_op = MemOperand(dst_addr, offset_imm); ++ if (offset_reg != no_reg) { ++ if (is_store_mem) { ++ pinned.set(src); ++ } ++ dst = GetUnusedRegister(kGpReg, pinned).gp(); ++ emit_ptrsize_add(dst, dst_addr, offset_reg); ++ dst_op = MemOperand(dst, offset_imm); ++ } ++ ++#if defined(V8_TARGET_BIG_ENDIAN) ++ if (is_store_mem) { ++ pinned.set(dst_op.rm()); ++ LiftoffRegister tmp = GetUnusedRegister(src.reg_class(), pinned); ++ // Save original value. ++ Move(tmp, src, type.value_type()); ++ ++ src = tmp; ++ pinned.set(tmp); ++ liftoff::ChangeEndiannessStore(this, src, type, pinned); ++ } ++#endif ++ ++ if (protected_store_pc) *protected_store_pc = pc_offset(); ++ ++ // FIXME (RISCV): current implementation treats all stores as unaligned ++ switch (type.value()) { ++ case StoreType::kI32Store8: ++ case StoreType::kI64Store8: ++ Sb(src.gp(), dst_op); ++ break; ++ case StoreType::kI32Store16: ++ case StoreType::kI64Store16: ++ TurboAssembler::Ush(src.gp(), dst_op); ++ break; ++ case StoreType::kI32Store: ++ case StoreType::kI64Store32: ++ TurboAssembler::Usw(src.gp(), dst_op); ++ break; ++ case StoreType::kI64Store: ++ TurboAssembler::Usd(src.gp(), dst_op); ++ break; ++ case StoreType::kF32Store: ++ TurboAssembler::UStoreFloat(src.fp(), dst_op, t5); ++ break; ++ case StoreType::kF64Store: ++ TurboAssembler::UStoreDouble(src.fp(), dst_op, t5); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void LiftoffAssembler::AtomicLoad(LiftoffRegister dst, Register src_addr, ++ Register offset_reg, uint32_t offset_imm, ++ LoadType type, LiftoffRegList pinned) { ++ bailout(kAtomics, "AtomicLoad"); ++} ++ ++void LiftoffAssembler::AtomicStore(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister src, ++ StoreType type, LiftoffRegList pinned) { ++ bailout(kAtomics, "AtomicStore"); ++} ++ ++void LiftoffAssembler::AtomicAdd(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicAdd"); ++} ++ ++void LiftoffAssembler::AtomicSub(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicSub"); ++} ++ ++void LiftoffAssembler::AtomicAnd(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicAnd"); ++} ++ ++void LiftoffAssembler::AtomicOr(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicOr"); ++} ++ ++void LiftoffAssembler::AtomicXor(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicXor"); ++} ++ ++void LiftoffAssembler::AtomicExchange(Register dst_addr, Register offset_reg, ++ uint32_t offset_imm, ++ LiftoffRegister value, ++ LiftoffRegister result, StoreType type) { ++ bailout(kAtomics, "AtomicExchange"); ++} ++ ++void LiftoffAssembler::AtomicCompareExchange( ++ Register dst_addr, Register offset_reg, uint32_t offset_imm, ++ LiftoffRegister expected, LiftoffRegister new_value, LiftoffRegister result, ++ StoreType type) { ++ bailout(kAtomics, "AtomicCompareExchange"); ++} ++ ++void LiftoffAssembler::AtomicFence() { sync(); } ++ ++void LiftoffAssembler::LoadCallerFrameSlot(LiftoffRegister dst, ++ uint32_t caller_slot_idx, ++ ValueType type) { ++ MemOperand src(fp, kSystemPointerSize * (caller_slot_idx + 1)); ++ liftoff::Load(this, dst, src, type); ++} ++ ++void LiftoffAssembler::StoreCallerFrameSlot(LiftoffRegister src, ++ uint32_t caller_slot_idx, ++ ValueType type) { ++ int32_t offset = kSystemPointerSize * (caller_slot_idx + 1); ++ liftoff::Store(this, fp, offset, src, type); ++} ++ ++void LiftoffAssembler::LoadReturnStackSlot(LiftoffRegister dst, int offset, ++ ValueType type) { ++ liftoff::Load(this, dst, MemOperand(sp, offset), type); ++} ++ ++void LiftoffAssembler::MoveStackValue(uint32_t dst_offset, uint32_t src_offset, ++ ValueType type) { ++ DCHECK_NE(dst_offset, src_offset); ++ LiftoffRegister reg = GetUnusedRegister(reg_class_for(type), {}); ++ Fill(reg, src_offset, type); ++ Spill(dst_offset, reg, type); ++} ++ ++void LiftoffAssembler::Move(Register dst, Register src, ValueType type) { ++ DCHECK_NE(dst, src); ++ // TODO(ksreten): Handle different sizes here. ++ TurboAssembler::Move(dst, src); ++} ++ ++void LiftoffAssembler::Move(DoubleRegister dst, DoubleRegister src, ++ ValueType type) { ++ DCHECK_NE(dst, src); ++ TurboAssembler::Move(dst, src); ++} ++ ++void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueType type) { ++ RecordUsedSpillOffset(offset); ++ MemOperand dst = liftoff::GetStackSlot(offset); ++ switch (type.kind()) { ++ case ValueType::kI32: ++ Sw(reg.gp(), dst); ++ break; ++ case ValueType::kI64: ++ Sd(reg.gp(), dst); ++ break; ++ case ValueType::kF32: ++ StoreFloat(reg.fp(), dst); ++ break; ++ case ValueType::kF64: ++ TurboAssembler::StoreDouble(reg.fp(), dst); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void LiftoffAssembler::Spill(int offset, WasmValue value) { ++ RecordUsedSpillOffset(offset); ++ MemOperand dst = liftoff::GetStackSlot(offset); ++ switch (value.type().kind()) { ++ case ValueType::kI32: { ++ LiftoffRegister tmp = GetUnusedRegister(kGpReg, {}); ++ TurboAssembler::li(tmp.gp(), Operand(value.to_i32())); ++ Sw(tmp.gp(), dst); ++ break; ++ } ++ case ValueType::kI64: { ++ LiftoffRegister tmp = GetUnusedRegister(kGpReg, {}); ++ TurboAssembler::li(tmp.gp(), value.to_i64()); ++ Sd(tmp.gp(), dst); ++ break; ++ } ++ default: ++ // kWasmF32 and kWasmF64 are unreachable, since those ++ // constants are not tracked. ++ UNREACHABLE(); ++ } ++} ++ ++void LiftoffAssembler::Fill(LiftoffRegister reg, int offset, ValueType type) { ++ MemOperand src = liftoff::GetStackSlot(offset); ++ switch (type.kind()) { ++ case ValueType::kI32: ++ Lw(reg.gp(), src); ++ break; ++ case ValueType::kI64: ++ Ld(reg.gp(), src); ++ break; ++ case ValueType::kF32: ++ LoadFloat(reg.fp(), src); ++ break; ++ case ValueType::kF64: ++ TurboAssembler::LoadDouble(reg.fp(), src); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++} ++ ++void LiftoffAssembler::FillI64Half(Register, int offset, RegPairHalf) { ++ UNREACHABLE(); ++} ++ ++void LiftoffAssembler::FillStackSlotsWithZero(int start, int size) { ++ DCHECK_LT(0, size); ++ RecordUsedSpillOffset(start + size); ++ ++ if (size <= 12 * kStackSlotSize) { ++ // Special straight-line code for up to 12 slots. Generates one ++ // instruction per slot (<= 12 instructions total). ++ uint32_t remainder = size; ++ for (; remainder >= kStackSlotSize; remainder -= kStackSlotSize) { ++ Sd(zero_reg, liftoff::GetStackSlot(start + remainder)); ++ } ++ DCHECK(remainder == 4 || remainder == 0); ++ if (remainder) { ++ Sw(zero_reg, liftoff::GetStackSlot(start + remainder)); ++ } ++ } else { ++ // General case for bigger counts (12 instructions). ++ // Use a0 for start address (inclusive), a1 for end address (exclusive). ++ Push(a1, a0); ++ Add64(a0, fp, Operand(-start - size)); ++ Add64(a1, fp, Operand(-start)); ++ ++ Label loop; ++ bind(&loop); ++ Sd(zero_reg, MemOperand(a0)); ++ addi(a0, a0, kSystemPointerSize); ++ BranchShort(&loop, ne, a0, Operand(a1)); ++ ++ Pop(a1, a0); ++ } ++} ++ ++void LiftoffAssembler::emit_i64_clz(LiftoffRegister dst, LiftoffRegister src) { ++ TurboAssembler::Clz64(dst.gp(), src.gp()); ++} ++ ++void LiftoffAssembler::emit_i64_ctz(LiftoffRegister dst, LiftoffRegister src) { ++ TurboAssembler::Ctz64(dst.gp(), src.gp()); ++} ++ ++bool LiftoffAssembler::emit_i64_popcnt(LiftoffRegister dst, ++ LiftoffRegister src) { ++ TurboAssembler::Popcnt64(dst.gp(), src.gp()); ++ return true; ++} ++ ++void LiftoffAssembler::emit_i32_mul(Register dst, Register lhs, Register rhs) { ++ TurboAssembler::Mul32(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_i32_divs(Register dst, Register lhs, Register rhs, ++ Label* trap_div_by_zero, ++ Label* trap_div_unrepresentable) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); ++ ++ // Check if lhs == kMinInt and rhs == -1, since this case is unrepresentable. ++ TurboAssembler::CompareI(kScratchReg, lhs, Operand(kMinInt), ne); ++ TurboAssembler::CompareI(kScratchReg2, rhs, Operand(-1), ne); ++ add(kScratchReg, kScratchReg, kScratchReg2); ++ TurboAssembler::Branch(trap_div_unrepresentable, eq, kScratchReg, ++ Operand(zero_reg)); ++ ++ TurboAssembler::Div32(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_i32_divu(Register dst, Register lhs, Register rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); ++ TurboAssembler::Divu32(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_i32_rems(Register dst, Register lhs, Register rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); ++ TurboAssembler::Mod32(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_i32_remu(Register dst, Register lhs, Register rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs, Operand(zero_reg)); ++ TurboAssembler::Modu32(dst, lhs, rhs); ++} ++ ++#define I32_BINOP(name, instruction) \ ++ void LiftoffAssembler::emit_i32_##name(Register dst, Register lhs, \ ++ Register rhs) { \ ++ instruction(dst, lhs, rhs); \ ++ } ++ ++// clang-format off ++I32_BINOP(add, addw) ++I32_BINOP(sub, subw) ++I32_BINOP(and, and_) ++I32_BINOP(or, or_) ++I32_BINOP(xor, xor_) ++// clang-format on ++ ++#undef I32_BINOP ++ ++#define I32_BINOP_I(name, instruction) \ ++ void LiftoffAssembler::emit_i32_##name##i(Register dst, Register lhs, \ ++ int32_t imm) { \ ++ instruction(dst, lhs, Operand(imm)); \ ++ } ++ ++// clang-format off ++I32_BINOP_I(add, Add32) ++I32_BINOP_I(and, And) ++I32_BINOP_I(or, Or) ++I32_BINOP_I(xor, Xor) ++// clang-format on ++ ++#undef I32_BINOP_I ++ ++void LiftoffAssembler::emit_i32_clz(Register dst, Register src) { ++ TurboAssembler::Clz32(dst, src); ++} ++ ++void LiftoffAssembler::emit_i32_ctz(Register dst, Register src) { ++ TurboAssembler::Ctz32(dst, src); ++} ++ ++bool LiftoffAssembler::emit_i32_popcnt(Register dst, Register src) { ++ TurboAssembler::Popcnt32(dst, src); ++ return true; ++} ++ ++#define I32_SHIFTOP(name, instruction) \ ++ void LiftoffAssembler::emit_i32_##name(Register dst, Register src, \ ++ Register amount) { \ ++ instruction(dst, src, amount); \ ++ } ++#define I32_SHIFTOP_I(name, instruction) \ ++ void LiftoffAssembler::emit_i32_##name##i(Register dst, Register src, \ ++ int amount) { \ ++ instruction(dst, src, amount); \ ++ } ++ ++I32_SHIFTOP(shl, sllw) ++I32_SHIFTOP(sar, sraw) ++I32_SHIFTOP(shr, srlw) ++ ++I32_SHIFTOP_I(shl, slliw) ++I32_SHIFTOP_I(sar, sraiw) ++I32_SHIFTOP_I(shr, srliw) ++ ++#undef I32_SHIFTOP ++#undef I32_SHIFTOP_I ++ ++void LiftoffAssembler::emit_i64_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ TurboAssembler::Mul64(dst.gp(), lhs.gp(), rhs.gp()); ++} ++ ++bool LiftoffAssembler::emit_i64_divs(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs, ++ Label* trap_div_by_zero, ++ Label* trap_div_unrepresentable) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs.gp(), Operand(zero_reg)); ++ ++ // Check if lhs == MinInt64 and rhs == -1, since this case is unrepresentable. ++ TurboAssembler::CompareI(kScratchReg, lhs.gp(), ++ Operand(std::numeric_limits::min()), ne); ++ TurboAssembler::CompareI(kScratchReg2, rhs.gp(), Operand(-1), ne); ++ add(kScratchReg, kScratchReg, kScratchReg2); ++ TurboAssembler::Branch(trap_div_unrepresentable, eq, kScratchReg, ++ Operand(zero_reg)); ++ ++ TurboAssembler::Div64(dst.gp(), lhs.gp(), rhs.gp()); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_i64_divu(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs.gp(), Operand(zero_reg)); ++ TurboAssembler::Divu64(dst.gp(), lhs.gp(), rhs.gp()); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_i64_rems(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs.gp(), Operand(zero_reg)); ++ TurboAssembler::Mod64(dst.gp(), lhs.gp(), rhs.gp()); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_i64_remu(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs, ++ Label* trap_div_by_zero) { ++ TurboAssembler::Branch(trap_div_by_zero, eq, rhs.gp(), Operand(zero_reg)); ++ TurboAssembler::Modu64(dst.gp(), lhs.gp(), rhs.gp()); ++ return true; ++} ++ ++#define I64_BINOP(name, instruction) \ ++ void LiftoffAssembler::emit_i64_##name( \ ++ LiftoffRegister dst, LiftoffRegister lhs, LiftoffRegister rhs) { \ ++ instruction(dst.gp(), lhs.gp(), rhs.gp()); \ ++ } ++ ++// clang-format off ++I64_BINOP(add, add) ++I64_BINOP(sub, sub) ++I64_BINOP(and, and_) ++I64_BINOP(or, or_) ++I64_BINOP(xor, xor_) ++// clang-format on ++ ++#undef I64_BINOP ++ ++#define I64_BINOP_I(name, instruction) \ ++ void LiftoffAssembler::emit_i64_##name##i( \ ++ LiftoffRegister dst, LiftoffRegister lhs, int32_t imm) { \ ++ instruction(dst.gp(), lhs.gp(), Operand(imm)); \ ++ } ++ ++// clang-format off ++I64_BINOP_I(add, Add64) ++I64_BINOP_I(and, And) ++I64_BINOP_I(or, Or) ++I64_BINOP_I(xor, Xor) ++// clang-format on ++ ++#undef I64_BINOP_I ++ ++#define I64_SHIFTOP(name, instruction) \ ++ void LiftoffAssembler::emit_i64_##name( \ ++ LiftoffRegister dst, LiftoffRegister src, Register amount) { \ ++ instruction(dst.gp(), src.gp(), amount); \ ++ } ++#define I64_SHIFTOP_I(name, instruction) \ ++ void LiftoffAssembler::emit_i64_##name##i(LiftoffRegister dst, \ ++ LiftoffRegister src, int amount) { \ ++ DCHECK(is_uint6(amount)); \ ++ instruction(dst.gp(), src.gp(), amount); \ ++ } ++ ++I64_SHIFTOP(shl, sll) ++I64_SHIFTOP(sar, sra) ++I64_SHIFTOP(shr, srl) ++ ++I64_SHIFTOP_I(shl, slli) ++I64_SHIFTOP_I(sar, srai) ++I64_SHIFTOP_I(shr, srli) ++ ++#undef I64_SHIFTOP ++#undef I64_SHIFTOP_I ++ ++void LiftoffAssembler::emit_u32_to_intptr(Register dst, Register src) { ++ addw(dst, src, zero_reg); ++} ++ ++void LiftoffAssembler::emit_f32_neg(DoubleRegister dst, DoubleRegister src) { ++ TurboAssembler::Neg_s(dst, src); ++} ++ ++void LiftoffAssembler::emit_f64_neg(DoubleRegister dst, DoubleRegister src) { ++ TurboAssembler::Neg_d(dst, src); ++} ++ ++void LiftoffAssembler::emit_f32_min(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ TurboAssembler::Float32Min(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_f32_max(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ TurboAssembler::Float32Max(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_f32_copysign(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ bailout(kComplexOperation, "f32_copysign"); ++} ++ ++void LiftoffAssembler::emit_f64_min(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ TurboAssembler::Float64Min(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_f64_max(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ TurboAssembler::Float64Max(dst, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_f64_copysign(DoubleRegister dst, DoubleRegister lhs, ++ DoubleRegister rhs) { ++ bailout(kComplexOperation, "f64_copysign"); ++} ++ ++#define FP_BINOP(name, instruction) \ ++ void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister lhs, \ ++ DoubleRegister rhs) { \ ++ instruction(dst, lhs, rhs); \ ++ } ++#define FP_UNOP(name, instruction) \ ++ void LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \ ++ instruction(dst, src); \ ++ } ++#define FP_UNOP_RETURN_TRUE(name, instruction) \ ++ bool LiftoffAssembler::emit_##name(DoubleRegister dst, DoubleRegister src) { \ ++ instruction(dst, src, kScratchDoubleReg); \ ++ return true; \ ++ } ++ ++FP_BINOP(f32_add, fadd_s) ++FP_BINOP(f32_sub, fsub_s) ++FP_BINOP(f32_mul, fmul_s) ++FP_BINOP(f32_div, fdiv_s) ++FP_UNOP(f32_abs, fabs_s) ++FP_UNOP_RETURN_TRUE(f32_ceil, Ceil_s_s) ++FP_UNOP_RETURN_TRUE(f32_floor, Floor_s_s) ++FP_UNOP_RETURN_TRUE(f32_trunc, Trunc_s_s) ++FP_UNOP_RETURN_TRUE(f32_nearest_int, Round_s_s) ++FP_UNOP(f32_sqrt, fsqrt_s) ++FP_BINOP(f64_add, fadd_d) ++FP_BINOP(f64_sub, fsub_d) ++FP_BINOP(f64_mul, fmul_d) ++FP_BINOP(f64_div, fdiv_d) ++FP_UNOP(f64_abs, fabs_d) ++FP_UNOP_RETURN_TRUE(f64_ceil, Ceil_d_d) ++FP_UNOP_RETURN_TRUE(f64_floor, Floor_d_d) ++FP_UNOP_RETURN_TRUE(f64_trunc, Trunc_d_d) ++FP_UNOP_RETURN_TRUE(f64_nearest_int, Round_d_d) ++FP_UNOP(f64_sqrt, fsqrt_d) ++ ++#undef FP_BINOP ++#undef FP_UNOP ++#undef FP_UNOP_RETURN_TRUE ++ ++bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, ++ LiftoffRegister dst, ++ LiftoffRegister src, Label* trap) { ++ switch (opcode) { ++ case kExprI32ConvertI64: ++ // According to WebAssembly spec, if I64 value does not fit the range of ++ // I32, the value is undefined. Therefore, We use sign extension to ++ // implement I64 to I32 truncation ++ TurboAssembler::SignExtendWord(dst.gp(), src.gp()); ++ return true; ++ case kExprI32SConvertF32: ++ case kExprI32UConvertF32: ++ case kExprI32SConvertF64: ++ case kExprI32UConvertF64: ++ case kExprI64SConvertF32: ++ case kExprI64UConvertF32: ++ case kExprI64SConvertF64: ++ case kExprI64UConvertF64: ++ case kExprF32ConvertF64: { ++ // real conversion, if src is out-of-bound of target integer types, ++ // kScratchReg is set to 0 ++ switch (opcode) { ++ case kExprI32SConvertF32: ++ Trunc_w_s(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI32UConvertF32: ++ Trunc_uw_s(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI32SConvertF64: ++ Trunc_w_d(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI32UConvertF64: ++ Trunc_uw_d(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI64SConvertF32: ++ Trunc_l_s(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI64UConvertF32: ++ Trunc_ul_s(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI64SConvertF64: ++ Trunc_l_d(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprI64UConvertF64: ++ Trunc_ul_d(dst.gp(), src.fp(), kScratchReg); ++ break; ++ case kExprF32ConvertF64: ++ fcvt_s_d(dst.fp(), src.fp()); ++ // FIXME (?): what if double cannot be represented by float? ++ // Trunc_s_d(dst.gp(), src.fp(), kScratchReg); ++ break; ++ default: ++ UNREACHABLE(); ++ } ++ ++ // Checking if trap. ++ TurboAssembler::Branch(trap, eq, kScratchReg, Operand(zero_reg)); ++ ++ return true; ++ } ++ case kExprI32ReinterpretF32: ++ TurboAssembler::ExtractLowWordFromF64(dst.gp(), src.fp()); ++ return true; ++ case kExprI64SConvertI32: ++ TurboAssembler::SignExtendWord(dst.gp(), src.gp()); ++ return true; ++ case kExprI64UConvertI32: ++ TurboAssembler::ZeroExtendWord(dst.gp(), src.gp()); ++ return true; ++ case kExprI64ReinterpretF64: ++ fmv_x_d(dst.gp(), src.fp()); ++ return true; ++ case kExprF32SConvertI32: { ++ TurboAssembler::Cvt_s_w(dst.fp(), src.gp()); ++ return true; ++ } ++ case kExprF32UConvertI32: ++ TurboAssembler::Cvt_s_uw(dst.fp(), src.gp()); ++ return true; ++ case kExprF32ReinterpretI32: ++ fmv_w_x(dst.fp(), src.gp()); ++ return true; ++ case kExprF64SConvertI32: { ++ TurboAssembler::Cvt_d_w(dst.fp(), src.gp()); ++ return true; ++ } ++ case kExprF64UConvertI32: ++ TurboAssembler::Cvt_d_uw(dst.fp(), src.gp()); ++ return true; ++ case kExprF64ConvertF32: ++ fcvt_d_s(dst.fp(), src.fp()); ++ return true; ++ case kExprF64ReinterpretI64: ++ fmv_d_x(dst.fp(), src.gp()); ++ return true; ++ case kExprI32SConvertSatF32: ++ bailout(kNonTrappingFloatToInt, "kExprI32SConvertSatF32"); ++ return true; ++ case kExprI32UConvertSatF32: ++ bailout(kNonTrappingFloatToInt, "kExprI32UConvertSatF32"); ++ return true; ++ case kExprI32SConvertSatF64: ++ bailout(kNonTrappingFloatToInt, "kExprI32SConvertSatF64"); ++ return true; ++ case kExprI32UConvertSatF64: ++ bailout(kNonTrappingFloatToInt, "kExprI32UConvertSatF64"); ++ return true; ++ case kExprI64SConvertSatF32: ++ bailout(kNonTrappingFloatToInt, "kExprI64SConvertSatF32"); ++ return true; ++ case kExprI64UConvertSatF32: ++ bailout(kNonTrappingFloatToInt, "kExprI64UConvertSatF32"); ++ return true; ++ case kExprI64SConvertSatF64: ++ bailout(kNonTrappingFloatToInt, "kExprI64SConvertSatF64"); ++ return true; ++ case kExprI64UConvertSatF64: ++ bailout(kNonTrappingFloatToInt, "kExprI64UConvertSatF64"); ++ return true; ++ default: ++ return false; ++ } ++} ++ ++void LiftoffAssembler::emit_i32_signextend_i8(Register dst, Register src) { ++ slliw(dst, src, 32 - 8); ++ sraiw(dst, dst, 32 - 8); ++} ++ ++void LiftoffAssembler::emit_i32_signextend_i16(Register dst, Register src) { ++ slliw(dst, src, 32 - 16); ++ sraiw(dst, dst, 32 - 16); ++} ++ ++void LiftoffAssembler::emit_i64_signextend_i8(LiftoffRegister dst, ++ LiftoffRegister src) { ++ slli(dst.gp(), src.gp(), 64 - 8); ++ srai(dst.gp(), dst.gp(), 64 - 8); ++} ++ ++void LiftoffAssembler::emit_i64_signextend_i16(LiftoffRegister dst, ++ LiftoffRegister src) { ++ slli(dst.gp(), src.gp(), 64 - 16); ++ srai(dst.gp(), dst.gp(), 64 - 16); ++} ++ ++void LiftoffAssembler::emit_i64_signextend_i32(LiftoffRegister dst, ++ LiftoffRegister src) { ++ slli(dst.gp(), src.gp(), 64 - 32); ++ srai(dst.gp(), dst.gp(), 64 - 32); ++} ++ ++void LiftoffAssembler::emit_jump(Label* label) { ++ TurboAssembler::Branch(label); ++} ++ ++void LiftoffAssembler::emit_jump(Register target) { ++ TurboAssembler::Jump(target); ++} ++ ++void LiftoffAssembler::emit_cond_jump(Condition cond, Label* label, ++ ValueType type, Register lhs, ++ Register rhs) { ++ if (rhs != no_reg) { ++ TurboAssembler::Branch(label, cond, lhs, Operand(rhs)); ++ } else { ++ TurboAssembler::Branch(label, cond, lhs, Operand(zero_reg)); ++ } ++} ++ ++void LiftoffAssembler::emit_i32_eqz(Register dst, Register src) { ++ TurboAssembler::Sltu(dst, src, 1); ++} ++ ++void LiftoffAssembler::emit_i32_set_cond(Condition cond, Register dst, ++ Register lhs, Register rhs) { ++ TurboAssembler::CompareI(dst, lhs, Operand(rhs), cond); ++} ++ ++void LiftoffAssembler::emit_i64_eqz(Register dst, LiftoffRegister src) { ++ TurboAssembler::Sltu(dst, src.gp(), 1); ++} ++ ++void LiftoffAssembler::emit_i64_set_cond(Condition cond, Register dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ TurboAssembler::CompareI(dst, lhs.gp(), Operand(rhs.gp()), cond); ++} ++ ++static FPUCondition ConditionToConditionCmpFPU(Condition condition) { ++ switch (condition) { ++ case kEqual: ++ return EQ; ++ case kUnequal: ++ return NE; ++ case kUnsignedLessThan: ++ return LT; ++ case kUnsignedGreaterEqual: ++ return GE; ++ case kUnsignedLessEqual: ++ return LE; ++ case kUnsignedGreaterThan: ++ return GT; ++ default: ++ break; ++ } ++ UNREACHABLE(); ++} ++ ++void LiftoffAssembler::emit_f32_set_cond(Condition cond, Register dst, ++ DoubleRegister lhs, ++ DoubleRegister rhs) { ++ FPUCondition fcond = ConditionToConditionCmpFPU(cond); ++ TurboAssembler::CompareF32(dst, fcond, lhs, rhs); ++} ++ ++void LiftoffAssembler::emit_f64_set_cond(Condition cond, Register dst, ++ DoubleRegister lhs, ++ DoubleRegister rhs) { ++ FPUCondition fcond = ConditionToConditionCmpFPU(cond); ++ TurboAssembler::CompareF64(dst, fcond, lhs, rhs); ++} ++ ++bool LiftoffAssembler::emit_select(LiftoffRegister dst, Register condition, ++ LiftoffRegister true_value, ++ LiftoffRegister false_value, ++ ValueType type) { ++ return false; ++} ++ ++void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr, ++ Register offset_reg, uint32_t offset_imm, ++ LoadType type, ++ LoadTransformationKind transform, ++ uint32_t* protected_load_pc) { ++ bailout(kSimd, "load extend and load splat unimplemented"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shuffle(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs, ++ const uint8_t shuffle[16], ++ bool is_swizzle) { ++ bailout(kSimd, "emit_i8x16_shuffle"); ++} ++ ++void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_swizzle"); ++} ++ ++void LiftoffAssembler::emit_i8x16_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_splat"); ++} ++ ++void LiftoffAssembler::emit_i16x8_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_splat"); ++} ++ ++void LiftoffAssembler::emit_i32x4_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_splat"); ++} ++ ++void LiftoffAssembler::emit_i64x2_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i64x2_splat"); ++} ++ ++void LiftoffAssembler::emit_f32x4_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_splat"); ++} ++ ++void LiftoffAssembler::emit_f64x2_splat(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_splat"); ++} ++ ++void LiftoffAssembler::emit_i8x16_eq(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_eq"); ++} ++ ++void LiftoffAssembler::emit_i8x16_ne(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_ne"); ++} ++ ++void LiftoffAssembler::emit_i8x16_gt_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_gt_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_gt_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_gt_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_ge_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_ge_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_ge_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_ge_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_eq(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_eq"); ++} ++ ++void LiftoffAssembler::emit_i16x8_ne(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_ne"); ++} ++ ++void LiftoffAssembler::emit_i16x8_gt_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_gt_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_gt_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_gt_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_ge_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_ge_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_ge_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_ge_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_eq(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_eq"); ++} ++ ++void LiftoffAssembler::emit_i32x4_ne(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_ne"); ++} ++ ++void LiftoffAssembler::emit_i32x4_gt_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_gt_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_gt_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_gt_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_ge_s(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_ge_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_ge_u(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_ge_u"); ++} ++ ++void LiftoffAssembler::emit_f32x4_eq(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_eq"); ++} ++ ++void LiftoffAssembler::emit_f32x4_ne(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_ne"); ++} ++ ++void LiftoffAssembler::emit_f32x4_lt(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_lt"); ++} ++ ++void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_le"); ++} ++ ++void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_eq"); ++} ++ ++void LiftoffAssembler::emit_f64x2_ne(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_ne"); ++} ++ ++void LiftoffAssembler::emit_f64x2_lt(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_lt"); ++} ++ ++void LiftoffAssembler::emit_f64x2_le(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_le"); ++} ++ ++void LiftoffAssembler::emit_s128_const(LiftoffRegister dst, ++ const uint8_t imms[16]) { ++ bailout(kSimd, "emit_s128_const"); ++} ++ ++void LiftoffAssembler::emit_s128_not(LiftoffRegister dst, LiftoffRegister src) { ++ bailout(kSimd, "emit_s128_not"); ++} ++ ++void LiftoffAssembler::emit_s128_and(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_s128_and"); ++} ++ ++void LiftoffAssembler::emit_s128_or(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_s128_or"); ++} ++ ++void LiftoffAssembler::emit_s128_xor(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_s128_xor"); ++} ++ ++void LiftoffAssembler::emit_s128_and_not(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_s128_and_not"); ++} ++ ++void LiftoffAssembler::emit_s128_select(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ LiftoffRegister mask) { ++ bailout(kSimd, "emit_s128_select"); ++} ++ ++void LiftoffAssembler::emit_i8x16_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_neg"); ++} ++ ++void LiftoffAssembler::emit_v8x16_anytrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_anytrue"); ++} ++ ++void LiftoffAssembler::emit_v8x16_alltrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_alltrue"); ++} ++ ++void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_bitmask"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shl(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_shl"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shli(LiftoffRegister dst, LiftoffRegister lhs, ++ int32_t rhs) { ++ bailout(kSimd, "emit_i8x16_shli"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shr_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_shr_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shri_s(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i8x16_shri_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shr_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_shr_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_shri_u(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i8x16_shri_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_add"); ++} ++ ++void LiftoffAssembler::emit_i8x16_add_saturate_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_add_saturate_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_add_saturate_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_add_saturate_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_sub"); ++} ++ ++void LiftoffAssembler::emit_i8x16_sub_saturate_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_sub_saturate_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_sub_saturate_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_sub_saturate_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_mul"); ++} ++ ++void LiftoffAssembler::emit_i8x16_min_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_min_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_min_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_min_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_max_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_max_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_max_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_max_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_neg"); ++} ++ ++void LiftoffAssembler::emit_v16x8_anytrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_anytrue"); ++} ++ ++void LiftoffAssembler::emit_v16x8_alltrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_alltrue"); ++} ++ ++void LiftoffAssembler::emit_i16x8_bitmask(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_bitmask"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shl(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_shl"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shli(LiftoffRegister dst, LiftoffRegister lhs, ++ int32_t rhs) { ++ bailout(kSimd, "emit_i16x8_shli"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shr_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_shr_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shri_s(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i16x8_shri_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shr_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_shr_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_shri_u(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i16x8_shri_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_add"); ++} ++ ++void LiftoffAssembler::emit_i16x8_add_saturate_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_add_saturate_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_add_saturate_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_add_saturate_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_sub"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sub_saturate_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_sub_saturate_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sub_saturate_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_sub_saturate_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_mul"); ++} ++ ++void LiftoffAssembler::emit_i16x8_min_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_min_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_min_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_min_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_max_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_max_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_max_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_max_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_neg"); ++} ++ ++void LiftoffAssembler::emit_v32x4_anytrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_v32x4_anytrue"); ++} ++ ++void LiftoffAssembler::emit_v32x4_alltrue(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_v32x4_alltrue"); ++} ++ ++void LiftoffAssembler::emit_i32x4_bitmask(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_bitmask"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shl(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_shl"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shli(LiftoffRegister dst, LiftoffRegister lhs, ++ int32_t rhs) { ++ bailout(kSimd, "emit_i32x4_shli"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shr_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_shr_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shri_s(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i32x4_shri_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shr_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_shr_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_shri_u(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i32x4_shri_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_add"); ++} ++ ++void LiftoffAssembler::emit_i32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_sub"); ++} ++ ++void LiftoffAssembler::emit_i32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_mul"); ++} ++ ++void LiftoffAssembler::emit_i32x4_min_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_min_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_min_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_min_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_max_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_max_s"); ++} ++ ++void LiftoffAssembler::emit_i32x4_max_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i32x4_max_u"); ++} ++ ++void LiftoffAssembler::emit_i64x2_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i64x2_neg"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shl(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_shl"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shli(LiftoffRegister dst, LiftoffRegister lhs, ++ int32_t rhs) { ++ bailout(kSimd, "emit_i64x2_shli"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shr_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_shr_s"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shri_s(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i64x2_shri_s"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shr_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_shr_u"); ++} ++ ++void LiftoffAssembler::emit_i64x2_shri_u(LiftoffRegister dst, ++ LiftoffRegister lhs, int32_t rhs) { ++ bailout(kSimd, "emit_i64x2_shri_u"); ++} ++ ++void LiftoffAssembler::emit_i64x2_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_add"); ++} ++ ++void LiftoffAssembler::emit_i64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_sub"); ++} ++ ++void LiftoffAssembler::emit_i64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i64x2_mul"); ++} ++ ++void LiftoffAssembler::emit_f32x4_abs(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_abs"); ++} ++ ++void LiftoffAssembler::emit_f32x4_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_neg"); ++} ++ ++void LiftoffAssembler::emit_f32x4_sqrt(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_sqrt"); ++} ++ ++bool LiftoffAssembler::emit_f32x4_ceil(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_ceil"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f32x4_floor(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_floor"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f32x4_trunc(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_trunc"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f32x4_nearest_int(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_nearest_int"); ++ return true; ++} ++ ++void LiftoffAssembler::emit_f32x4_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_add"); ++} ++ ++void LiftoffAssembler::emit_f32x4_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_sub"); ++} ++ ++void LiftoffAssembler::emit_f32x4_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_mul"); ++} ++ ++void LiftoffAssembler::emit_f32x4_div(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_div"); ++} ++ ++void LiftoffAssembler::emit_f32x4_min(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_min"); ++} ++ ++void LiftoffAssembler::emit_f32x4_max(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_max"); ++} ++ ++void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_pmin"); ++} ++ ++void LiftoffAssembler::emit_f32x4_pmax(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f32x4_pmax"); ++} ++ ++void LiftoffAssembler::emit_f64x2_abs(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_abs"); ++} ++ ++void LiftoffAssembler::emit_f64x2_neg(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_neg"); ++} ++ ++void LiftoffAssembler::emit_f64x2_sqrt(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_sqrt"); ++} ++ ++bool LiftoffAssembler::emit_f64x2_ceil(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_ceil"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f64x2_floor(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_floor"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f64x2_trunc(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_trunc"); ++ return true; ++} ++ ++bool LiftoffAssembler::emit_f64x2_nearest_int(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f64x2_nearest_int"); ++ return true; ++} ++ ++void LiftoffAssembler::emit_f64x2_add(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_add"); ++} ++ ++void LiftoffAssembler::emit_f64x2_sub(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_sub"); ++} ++ ++void LiftoffAssembler::emit_f64x2_mul(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_mul"); ++} ++ ++void LiftoffAssembler::emit_f64x2_div(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_div"); ++} ++ ++void LiftoffAssembler::emit_f64x2_min(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_min"); ++} ++ ++void LiftoffAssembler::emit_f64x2_max(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_max"); ++} ++ ++void LiftoffAssembler::emit_f64x2_pmin(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_pmin"); ++} ++ ++void LiftoffAssembler::emit_f64x2_pmax(LiftoffRegister dst, LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_f64x2_pmax"); ++} ++ ++void LiftoffAssembler::emit_i32x4_sconvert_f32x4(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_sconvert_f32x4"); ++} ++ ++void LiftoffAssembler::emit_i32x4_uconvert_f32x4(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_uconvert_f32x4"); ++} ++ ++void LiftoffAssembler::emit_f32x4_sconvert_i32x4(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_sconvert_i32x4"); ++} ++ ++void LiftoffAssembler::emit_f32x4_uconvert_i32x4(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_f32x4_uconvert_i32x4"); ++} ++ ++void LiftoffAssembler::emit_i8x16_sconvert_i16x8(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_sconvert_i16x8"); ++} ++ ++void LiftoffAssembler::emit_i8x16_uconvert_i16x8(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_uconvert_i16x8"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sconvert_i32x4(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_sconvert_i32x4"); ++} ++ ++void LiftoffAssembler::emit_i16x8_uconvert_i32x4(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_uconvert_i32x4"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sconvert_i8x16_low(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_sconvert_i8x16_low"); ++} ++ ++void LiftoffAssembler::emit_i16x8_sconvert_i8x16_high(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_sconvert_i8x16_high"); ++} ++ ++void LiftoffAssembler::emit_i16x8_uconvert_i8x16_low(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_uconvert_i8x16_low"); ++} ++ ++void LiftoffAssembler::emit_i16x8_uconvert_i8x16_high(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_uconvert_i8x16_high"); ++} ++ ++void LiftoffAssembler::emit_i32x4_sconvert_i16x8_low(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_sconvert_i16x8_low"); ++} ++ ++void LiftoffAssembler::emit_i32x4_sconvert_i16x8_high(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_sconvert_i16x8_high"); ++} ++ ++void LiftoffAssembler::emit_i32x4_uconvert_i16x8_low(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_uconvert_i16x8_low"); ++} ++ ++void LiftoffAssembler::emit_i32x4_uconvert_i16x8_high(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_uconvert_i16x8_high"); ++} ++ ++void LiftoffAssembler::emit_i8x16_rounding_average_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i8x16_rounding_average_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_rounding_average_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ LiftoffRegister rhs) { ++ bailout(kSimd, "emit_i16x8_rounding_average_u"); ++} ++ ++void LiftoffAssembler::emit_i8x16_abs(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i8x16_abs"); ++} ++ ++void LiftoffAssembler::emit_i16x8_abs(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i16x8_abs"); ++} ++ ++void LiftoffAssembler::emit_i32x4_abs(LiftoffRegister dst, ++ LiftoffRegister src) { ++ bailout(kSimd, "emit_i32x4_abs"); ++} ++ ++void LiftoffAssembler::emit_i8x16_extract_lane_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i8x16_extract_lane_s"); ++} ++ ++void LiftoffAssembler::emit_i8x16_extract_lane_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i8x16_extract_lane_u"); ++} ++ ++void LiftoffAssembler::emit_i16x8_extract_lane_s(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i16x8_extract_lane_s"); ++} ++ ++void LiftoffAssembler::emit_i16x8_extract_lane_u(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i16x8_extract_lane_u"); ++} ++ ++void LiftoffAssembler::emit_i32x4_extract_lane(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i32x4_extract_lane"); ++} ++ ++void LiftoffAssembler::emit_i64x2_extract_lane(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i64x2_extract_lane"); ++} ++ ++void LiftoffAssembler::emit_f32x4_extract_lane(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_f32x4_extract_lane"); ++} ++ ++void LiftoffAssembler::emit_f64x2_extract_lane(LiftoffRegister dst, ++ LiftoffRegister lhs, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_f64x2_extract_lane"); ++} ++ ++void LiftoffAssembler::emit_i8x16_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i8x16_replace_lane"); ++} ++ ++void LiftoffAssembler::emit_i16x8_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i16x8_replace_lane"); ++} ++ ++void LiftoffAssembler::emit_i32x4_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i32x4_replace_lane"); ++} ++ ++void LiftoffAssembler::emit_i64x2_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_i64x2_replace_lane"); ++} ++ ++void LiftoffAssembler::emit_f32x4_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_f32x4_replace_lane"); ++} ++ ++void LiftoffAssembler::emit_f64x2_replace_lane(LiftoffRegister dst, ++ LiftoffRegister src1, ++ LiftoffRegister src2, ++ uint8_t imm_lane_idx) { ++ bailout(kSimd, "emit_f64x2_replace_lane"); ++} ++ ++void LiftoffAssembler::StackCheck(Label* ool_code, Register limit_address) { ++ TurboAssembler::Uld(limit_address, MemOperand(limit_address)); ++ TurboAssembler::Branch(ool_code, ule, sp, Operand(limit_address)); ++} ++ ++void LiftoffAssembler::CallTrapCallbackForTesting() { ++ PrepareCallCFunction(0, GetUnusedRegister(kGpReg, {}).gp()); ++ CallCFunction(ExternalReference::wasm_call_trap_callback_for_testing(), 0); ++} ++ ++void LiftoffAssembler::AssertUnreachable(AbortReason reason) { ++ if (emit_debug_code()) Abort(reason); ++} ++ ++void LiftoffAssembler::PushRegisters(LiftoffRegList regs) { ++ LiftoffRegList gp_regs = regs & kGpCacheRegList; ++ unsigned num_gp_regs = gp_regs.GetNumRegsSet(); ++ if (num_gp_regs) { ++ unsigned offset = num_gp_regs * kSystemPointerSize; ++ Add64(sp, sp, Operand(-offset)); ++ while (!gp_regs.is_empty()) { ++ LiftoffRegister reg = gp_regs.GetFirstRegSet(); ++ offset -= kSystemPointerSize; ++ Sd(reg.gp(), MemOperand(sp, offset)); ++ gp_regs.clear(reg); ++ } ++ DCHECK_EQ(offset, 0); ++ } ++ LiftoffRegList fp_regs = regs & kFpCacheRegList; ++ unsigned num_fp_regs = fp_regs.GetNumRegsSet(); ++ if (num_fp_regs) { ++ Add64(sp, sp, Operand(-(num_fp_regs * kStackSlotSize))); ++ unsigned offset = 0; ++ while (!fp_regs.is_empty()) { ++ LiftoffRegister reg = fp_regs.GetFirstRegSet(); ++ TurboAssembler::StoreDouble(reg.fp(), MemOperand(sp, offset)); ++ fp_regs.clear(reg); ++ offset += sizeof(double); ++ } ++ DCHECK_EQ(offset, num_fp_regs * sizeof(double)); ++ } ++} ++ ++void LiftoffAssembler::PopRegisters(LiftoffRegList regs) { ++ LiftoffRegList fp_regs = regs & kFpCacheRegList; ++ unsigned fp_offset = 0; ++ while (!fp_regs.is_empty()) { ++ LiftoffRegister reg = fp_regs.GetFirstRegSet(); ++ TurboAssembler::LoadDouble(reg.fp(), MemOperand(sp, fp_offset)); ++ fp_regs.clear(reg); ++ fp_offset += sizeof(double); ++ } ++ if (fp_offset) Add64(sp, sp, Operand(fp_offset)); ++ LiftoffRegList gp_regs = regs & kGpCacheRegList; ++ unsigned gp_offset = 0; ++ while (!gp_regs.is_empty()) { ++ LiftoffRegister reg = gp_regs.GetLastRegSet(); ++ Ld(reg.gp(), MemOperand(sp, gp_offset)); ++ gp_regs.clear(reg); ++ gp_offset += kSystemPointerSize; ++ } ++ Add64(sp, sp, Operand(gp_offset)); ++} ++ ++void LiftoffAssembler::DropStackSlotsAndRet(uint32_t num_stack_slots) { ++ TurboAssembler::DropAndRet(static_cast(num_stack_slots)); ++} ++ ++void LiftoffAssembler::CallC(const wasm::FunctionSig* sig, ++ const LiftoffRegister* args, ++ const LiftoffRegister* rets, ++ ValueType out_argument_type, int stack_bytes, ++ ExternalReference ext_ref) { ++ Add64(sp, sp, Operand(-stack_bytes)); ++ ++ int arg_bytes = 0; ++ for (ValueType param_type : sig->parameters()) { ++ liftoff::Store(this, sp, arg_bytes, *args++, param_type); ++ arg_bytes += param_type.element_size_bytes(); ++ } ++ DCHECK_LE(arg_bytes, stack_bytes); ++ ++ // Pass a pointer to the buffer with the arguments to the C function. ++ // On RISC-V, the first argument is passed in {a0}. ++ constexpr Register kFirstArgReg = a0; ++ mv(kFirstArgReg, sp); ++ ++ // Now call the C function. ++ constexpr int kNumCCallArgs = 1; ++ PrepareCallCFunction(kNumCCallArgs, kScratchReg); ++ CallCFunction(ext_ref, kNumCCallArgs); ++ ++ // Move return value to the right register. ++ const LiftoffRegister* next_result_reg = rets; ++ if (sig->return_count() > 0) { ++ DCHECK_EQ(1, sig->return_count()); ++ constexpr Register kReturnReg = a0; ++ if (kReturnReg != next_result_reg->gp()) { ++ Move(*next_result_reg, LiftoffRegister(kReturnReg), sig->GetReturn(0)); ++ } ++ ++next_result_reg; ++ } ++ ++ // Load potential output value from the buffer on the stack. ++ if (out_argument_type != kWasmStmt) { ++ liftoff::Load(this, *next_result_reg, MemOperand(sp, 0), out_argument_type); ++ } ++ ++ Add64(sp, sp, Operand(stack_bytes)); ++} ++ ++void LiftoffAssembler::CallNativeWasmCode(Address addr) { ++ Call(addr, RelocInfo::WASM_CALL); ++} ++ ++void LiftoffAssembler::TailCallNativeWasmCode(Address addr) { ++ Jump(addr, RelocInfo::WASM_CALL); ++} ++ ++void LiftoffAssembler::CallIndirect(const wasm::FunctionSig* sig, ++ compiler::CallDescriptor* call_descriptor, ++ Register target) { ++ if (target == no_reg) { ++ pop(kScratchReg); ++ Call(kScratchReg); ++ } else { ++ Call(target); ++ } ++} ++ ++void LiftoffAssembler::TailCallIndirect(Register target) { ++ if (target == no_reg) { ++ Pop(kScratchReg); ++ Jump(kScratchReg); ++ } else { ++ Jump(target); ++ } ++} ++ ++void LiftoffAssembler::CallRuntimeStub(WasmCode::RuntimeStubId sid) { ++ // A direct call to a wasm runtime stub defined in this module. ++ // Just encode the stub index. This will be patched at relocation. ++ Call(static_cast
(sid), RelocInfo::WASM_STUB_CALL); ++} ++ ++void LiftoffAssembler::AllocateStackSlot(Register addr, uint32_t size) { ++ Add64(sp, sp, Operand(-size)); ++ TurboAssembler::Move(addr, sp); ++} ++ ++void LiftoffAssembler::DeallocateStackSlot(uint32_t size) { ++ Add64(sp, sp, Operand(size)); ++} ++ ++void LiftoffStackSlots::Construct() { ++ for (auto& slot : slots_) { ++ const LiftoffAssembler::VarState& src = slot.src_; ++ switch (src.loc()) { ++ case LiftoffAssembler::VarState::kStack: ++ asm_->Ld(kScratchReg, liftoff::GetStackSlot(slot.src_offset_)); ++ asm_->push(kScratchReg); ++ break; ++ case LiftoffAssembler::VarState::kRegister: ++ liftoff::push(asm_, src.reg(), src.type()); ++ break; ++ case LiftoffAssembler::VarState::kIntConst: { ++ asm_->li(kScratchReg, Operand(src.i32_const())); ++ asm_->push(kScratchReg); ++ break; ++ } ++ } ++ } ++} ++ ++} // namespace wasm ++} // namespace internal ++} // namespace v8 ++ ++#endif // V8_WASM_BASELINE_RISCV_LIFTOFF_ASSEMBLER_RISCV_H_ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.cc +@@ -307,6 +307,40 @@ void JumpTableAssembler::NopBytes(int by + } + } + ++#elif V8_TARGET_ARCH_RISCV64 ++void JumpTableAssembler::EmitLazyCompileJumpSlot(uint32_t func_index, ++ Address lazy_compile_target) { ++ int start = pc_offset(); ++ li(kWasmCompileLazyFuncIndexRegister, func_index); // max. 2 instr ++ // Jump produces max. 9 instructions (8 for li + 1 for jr) ++ Jump(lazy_compile_target, RelocInfo::NONE); ++ int nop_bytes = start + kLazyCompileTableSlotSize - pc_offset(); ++ DCHECK_EQ(nop_bytes % kInstrSize, 0); ++ for (int i = 0; i < nop_bytes; i += kInstrSize) nop(); ++} ++ ++bool JumpTableAssembler::EmitJumpSlot(Address target) { ++ PatchAndJump(target); ++ return true; ++} ++ ++void JumpTableAssembler::EmitFarJumpSlot(Address target) { ++ JumpToInstructionStream(target); ++} ++ ++// static ++void JumpTableAssembler::PatchFarJumpSlot(Address slot, Address target) { ++ UNREACHABLE(); ++} ++ ++void JumpTableAssembler::NopBytes(int bytes) { ++ DCHECK_LE(0, bytes); ++ DCHECK_EQ(0, bytes % kInstrSize); ++ for (; bytes > 0; bytes -= kInstrSize) { ++ nop(); ++ } ++} ++ + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/jump-table-assembler.h +@@ -215,6 +215,11 @@ class V8_EXPORT_PRIVATE JumpTableAssembl + static constexpr int kJumpTableSlotSize = 8 * kInstrSize; + static constexpr int kFarJumpTableSlotSize = 6 * kInstrSize; + static constexpr int kLazyCompileTableSlotSize = 8 * kInstrSize; ++#elif V8_TARGET_ARCH_RISCV64 ++ static constexpr int kJumpTableLineSize = 6 * kInstrSize; ++ static constexpr int kJumpTableSlotSize = 6 * kInstrSize; ++ static constexpr int kFarJumpTableSlotSize = 9 * kInstrSize; ++ static constexpr int kLazyCompileTableSlotSize = 9 * kInstrSize; + #else + #error Unknown architecture. + #endif +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/wasm-linkage.h +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/wasm-linkage.h ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/wasm-linkage.h +@@ -102,6 +102,22 @@ constexpr Register kGpReturnRegisters[] + constexpr DoubleRegister kFpParamRegisters[] = {d0, d2}; + constexpr DoubleRegister kFpReturnRegisters[] = {d0, d2}; + ++#elif V8_TARGET_ARCH_RISCV64 ++// =========================================================================== ++// == riscv64 ================================================================= ++// =========================================================================== ++// Note that kGpParamRegisters and kFpParamRegisters are used in ++// Builtins::Generate_WasmCompileLazy (builtins-riscv64.cc) ++constexpr Register kGpParamRegisters[] = {a0, a2, a3, a4, a5, a6, a7}; ++constexpr Register kGpReturnRegisters[] = {a0, a1}; ++constexpr DoubleRegister kFpParamRegisters[] = {fa0, fa1, fa2, fa3, ++ fa4, fa5, fa6}; ++constexpr DoubleRegister kFpReturnRegisters[] = {fa0, fa1}; ++ ++#elif V8_TARGET_ARCH_RISCV ++ ++#error RISCV(32) architecture not supported ++ + #else + // =========================================================================== + // == unknown ================================================================ +Index: qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/wasm-serialization.cc +=================================================================== +--- qtwebengine-everywhere-src-5.15.3.orig/src/3rdparty/chromium/v8/src/wasm/wasm-serialization.cc ++++ qtwebengine-everywhere-src-5.15.3/src/3rdparty/chromium/v8/src/wasm/wasm-serialization.cc +@@ -368,7 +368,8 @@ bool NativeModuleSerializer::WriteCode(c + writer->WriteVector(code->source_positions()); + writer->WriteVector(code->protected_instructions_data()); + #if V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64 || V8_TARGET_ARCH_ARM || \ +- V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64 || V8_TARGET_ARCH_S390X ++ V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64 || V8_TARGET_ARCH_S390X || \ ++ V8_TARGET_ARCH_RISCV64 || V8_TARGET_ARCH_RISCV32 + // On platforms that don't support misaligned word stores, copy to an aligned + // buffer if necessary so we can relocate the serialized code. + std::unique_ptr aligned_buffer; From 3653318480b60a8a8d716f1de49c8ead96db7e5d Mon Sep 17 00:00:00 2001 From: John Date: Fri, 31 Mar 2023 15:41:11 +0200 Subject: [PATCH 149/189] DirectXShaderCompiler: update to 1.7.2212.1. --- srcpkgs/DirectXShaderCompiler/template | 44 +++++++++++++++----------- 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/srcpkgs/DirectXShaderCompiler/template b/srcpkgs/DirectXShaderCompiler/template index 8409124ff559b..2f82073f0e55b 100644 --- a/srcpkgs/DirectXShaderCompiler/template +++ b/srcpkgs/DirectXShaderCompiler/template @@ -1,6 +1,6 @@ # Template file for 'DirectXShaderCompiler' pkgname=DirectXShaderCompiler -version=1.7.2207 +version=1.7.2212.1 revision=1 archs="x86_64* i686*" build_style=cmake @@ -10,20 +10,23 @@ short_desc="DirectX Shader Compiler based on LLVM/Clang. " maintainer="Joshua Woodie " license="LLVM" homepage="https://github.com/microsoft/DirectXShaderCompiler" -_SPIRV_Headers_commit=b2a156e1c0434bc8c99aaebba1c7be98be7ac580 -_SPIRV_Tools_commit=b930e734ea198b7aabbbf04ee1562cf6f57962f0 -_re2_commit=3e9622e0cd94ebba6e04d5c50b7af32029e330d8 -_effcee_commit=ddf5e2bb92957dc8a12c5392f8495333d6844133 +_SPIRV_Headers_commit=1d31a100405cf8783ca7a31e31cdd727c9fc54c3 +_SPIRV_Tools_commit=40f5bf59c6acb4754a0bffd3c53a715732883a12 +_re2_commit=4be240789d5b322df9f02b7e19c8651f3ccbf205 +_effcee_commit=35912e1b7778ec2ddcff7e7188177761539e59e0 +_DirectX_Headers_commit=980971e835876dc0cde415e8f9bc646e64667bf7 distfiles="https://github.com/microsoft/DirectXShaderCompiler/archive/refs/tags/v${version}.tar.gz https://github.com/KhronosGroup/SPIRV-Headers/archive/${_SPIRV_Headers_commit}.tar.gz https://github.com/KhronosGroup/SPIRV-Tools/archive/${_SPIRV_Tools_commit}.tar.gz https://github.com/google/re2/archive/${_re2_commit}.tar.gz - https://github.com/google/effcee/archive/${_effcee_commit}.tar.gz" -checksum="a52aad3830b4d3e39734455ad7f288ad24e32c006e256d987a0ed44fc54fbd26 - b200990e1c07894906e298368e7e56d5ab9d728d851f9292587ec740c2b4d409 - 9cddc845f99d7daa65940ff9deb6754cd71b67987ec9860bb0ef2af8a8732c84 - 218e0f8d100ba09a089582de7a54ae0ebfa08fd8e43b4c8035ef2faa5e0d284a - 5809b2f80b67dc231c52da743be37bb46c5ce4a59dde344761f7c4295119750c" + https://github.com/google/effcee/archive/${_effcee_commit}.tar.gz + https://github.com/microsoft/DirectX-Headers/archive/${_DirectX_Headers_commit}.tar.gz" +checksum="f345a555aa02d16cf2ac6e6e72bf340f20626849ece6ba3700ae17a1ca6fc6b7 + ec09b682c93bffc6e3d58459840a0306b6b9360e56e797c4243d2d7b785dea74 + b99c91307a4b466754ffeaaaa6086bda55780ccf1557592004a1736fb9aa7ce7 + da5c23ecdb9a55c82d6802ee55812dfb99a035a4838287c0b7c0051bd0fdb9fc + 3e9d106b8cb018db6dffb3f38748f6b162266b5307433fe36d0af26bb236befb + b5a4b6d8806ff7f29f19879f83d015dbe8740676d4ca0b48647a789cc7773c4e" if [ "$XBPS_TARGET_LIBC" = "musl" ]; then # Tests on musl would require some patching to be done @@ -33,14 +36,17 @@ fi nocross="fun with cmake and bunlded llvm" post_extract() { - rmdir -v ${wrksrc}/external/SPIRV-Headers - mv ${wrksrc}/../SPIRV-Headers-${_SPIRV_Headers_commit} ${wrksrc}/external/SPIRV-Headers - rmdir -v ${wrksrc}/external/SPIRV-Tools - mv ${wrksrc}/../SPIRV-Tools-${_SPIRV_Tools_commit} ${wrksrc}/external/SPIRV-Tools - rmdir -v ${wrksrc}/external/re2 - mv ${wrksrc}/../re2-${_re2_commit} ${wrksrc}/external/re2 - rmdir -v ${wrksrc}/external/effcee - mv ${wrksrc}/../effcee-${_effcee_commit} ${wrksrc}/external/effcee + mv "$pkgname-$version"/* . + rmdir -v external/SPIRV-Headers + mv SPIRV-Headers-${_SPIRV_Headers_commit} external/SPIRV-Headers + rmdir -v external/SPIRV-Tools + mv SPIRV-Tools-${_SPIRV_Tools_commit} external/SPIRV-Tools + rmdir -v external/re2 + mv re2-${_re2_commit} external/re2 + rmdir -v external/effcee + mv effcee-${_effcee_commit} external/effcee + rmdir -v external/DirectX-Headers + mv DirectX-Headers-${_DirectX_Headers_commit} external/DirectX-Headers } do_install() { From 9e1d3e5476872d9af2099267b66bdce4635c2963 Mon Sep 17 00:00:00 2001 From: John Date: Wed, 5 Apr 2023 01:50:00 +0200 Subject: [PATCH 150/189] linux6.2: add patch for logitech lightpseed reciever --- ...he-new-lightspeed-receiver-iteration.patch | 276 ++++++++++++++++++ 1 file changed, 276 insertions(+) create mode 100644 srcpkgs/linux6.2/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch diff --git a/srcpkgs/linux6.2/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch b/srcpkgs/linux6.2/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch new file mode 100644 index 0000000000000..30054f697d40c --- /dev/null +++ b/srcpkgs/linux6.2/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch @@ -0,0 +1,276 @@ +From patchwork Sat Jan 23 18:03:33 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?q?Filipe_La=C3=ADns?= +X-Patchwork-Id: 12041761 +X-Patchwork-Delegate: jikos@jikos.cz +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-23.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, + INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, + SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham + autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id CAA6BC433E0 + for ; Sat, 23 Jan 2021 18:04:54 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 9274B22DFA + for ; Sat, 23 Jan 2021 18:04:54 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726151AbhAWSEg (ORCPT ); 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+ auth=pass smtp.auth=ffy00 smtp.mailfrom=lains@archlinux.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-input@vger.kernel.org + +From: Filipe Laíns + +Tested with the G Pro X Superlight. libratbag sees the device, as +expected, and input events are passing trough. + +https://github.com/libratbag/libratbag/pull/1122 + +The receiver has a quirk where the moused interface doesn't have a +report ID, I am not sure why, perhaps they forgot. All other interfaces +have report IDs so I am left scratching my head. +Since this driver doesn't have a quirk system, I simply implemented it +as a different receiver type, which is true, it just wouldn't be the +prefered approach :P + +Signed-off-by: Filipe Laíns +--- + drivers/hid/hid-ids.h | 1 + + drivers/hid/hid-logitech-dj.c | 49 +++++++++++++++++++++++++---------- + 2 files changed, 37 insertions(+), 13 deletions(-) + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index 4c5f23640f9c..8eac3c93fa38 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -803,6 +803,7 @@ + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1 0xc539 + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1 0xc53f + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY 0xc53a ++#define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2 0xc547 + #define USB_DEVICE_ID_SPACETRAVELLER 0xc623 + #define USB_DEVICE_ID_SPACENAVIGATOR 0xc626 + #define USB_DEVICE_ID_DINOVO_DESKTOP 0xc704 +diff --git a/drivers/hid/hid-logitech-dj.c b/drivers/hid/hid-logitech-dj.c +index 1401ee2067ca..6596c81947a8 100644 +--- a/drivers/hid/hid-logitech-dj.c ++++ b/drivers/hid/hid-logitech-dj.c +@@ -114,6 +114,7 @@ enum recvr_type { + recvr_type_dj, + recvr_type_hidpp, + recvr_type_gaming_hidpp, ++ recvr_type_gaming_hidpp_missing_mse_report_id, /* lightspeed receiver missing the mouse report ID */ + recvr_type_mouse_only, + recvr_type_27mhz, + recvr_type_bluetooth, +@@ -1360,6 +1361,7 @@ static int logi_dj_ll_parse(struct hid_device *hid) + dbg_hid("%s: sending a mouse descriptor, reports_supported: %llx\n", + __func__, djdev->reports_supported); + if (djdev->dj_receiver_dev->type == recvr_type_gaming_hidpp || ++ djdev->dj_receiver_dev->type == recvr_type_gaming_hidpp_missing_mse_report_id || + djdev->dj_receiver_dev->type == recvr_type_mouse_only) + rdcat(rdesc, &rsize, mse_high_res_descriptor, + sizeof(mse_high_res_descriptor)); +@@ -1692,11 +1692,12 @@ + } + /* + * Mouse-only receivers send unnumbered mouse data. The 27 MHz +- * receiver uses 6 byte packets, the nano receiver 8 bytes. ++ * receiver uses 6 byte packets, the nano receiver 8 bytes. and ++ * some gaming ones are using 16 bytes. + */ + if (djrcv_dev->unnumbered_application == HID_GD_MOUSE && +- size <= 8) { +- u8 mouse_report[9]; ++ size <= 16) { ++ u8 mouse_report[17]; + + /* Prepend report id */ + mouse_report[0] = REPORT_TYPE_MOUSE; +@@ -1688,6 +1706,7 @@ static int logi_dj_probe(struct hid_device *hdev, + case recvr_type_dj: no_dj_interfaces = 3; break; + case recvr_type_hidpp: no_dj_interfaces = 2; break; + case recvr_type_gaming_hidpp: no_dj_interfaces = 3; break; ++ case recvr_type_gaming_hidpp_missing_mse_report_id: no_dj_interfaces = 3; break; + case recvr_type_mouse_only: no_dj_interfaces = 2; break; + case recvr_type_27mhz: no_dj_interfaces = 2; break; + case recvr_type_bluetooth: no_dj_interfaces = 2; break; +@@ -1984,6 +1984,10 @@ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, + USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1), + .driver_data = recvr_type_gaming_hidpp}, ++ { /* Logitech lightspeed receiver (0xc547) */ ++ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, ++ USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2), ++ .driver_data = recvr_type_gaming_hidpp_missing_mse_report_id}, + + { /* Logitech 27 MHz HID++ 1.0 receiver (0xc513) */ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER), +From patchwork Sat Jan 23 18:03:34 2021 +Content-Type: text/plain; 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+ bh=pUy5GRn6iAd0774+zrvt/xxLsLy5Gfph7I887BlZzNk=; + b=noC/7x4rdVIF6TIIpPH6gRDnKKvdwV8Dh1v1QhdRRC+my3IExMwH+AujrLW22mX6LXKjM0 + hIi/YnKi2uRn2SAw== +From: =?utf-8?q?Filipe_La=C3=ADns?= +To: Jiri Kosina , + Benjamin Tissoires , + linux-input@vger.kernel.org, linux-kernel@vger.kernel.org +Cc: =?utf-8?q?Filipe_La=C3=ADns?= +Subject: [PATCH 2/2] HID: logitech-hidpp: add support for the G Pro X + Superlight over USB +Date: Sat, 23 Jan 2021 18:03:34 +0000 +Message-Id: <20210123180334.3062995-2-lains@archlinux.org> +X-Mailer: git-send-email 2.30.0 +In-Reply-To: <20210123180334.3062995-1-lains@archlinux.org> +References: <20210123180334.3062995-1-lains@archlinux.org> +MIME-Version: 1.0 +Authentication-Results: mail.archlinux.org; + auth=pass smtp.auth=ffy00 smtp.mailfrom=lains@archlinux.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-input@vger.kernel.org + +From: Filipe Laíns + +Tested and is working :) + +Signed-off-by: Filipe Laíns +--- + drivers/hid/hid-logitech-hidpp.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 291c6b4d26b7..54a289510a7d 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -4268,6 +4268,8 @@ static const struct hid_device_id hidpp_devices[] = { + .driver_data = HIDPP_QUIRK_CLASS_G920 | HIDPP_QUIRK_FORCE_OUTPUT_REPORTS}, + { /* Logitech G Pro Gaming Mouse over USB */ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC088) }, ++ { /* Logitech G Pro X Superlight Gaming Mouse over USB */ ++ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC094) }, + + { /* MX5000 keyboard over Bluetooth */ + HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb305), From cae99e1d99f436cf053fdc9ed56a3bd97d60c408 Mon Sep 17 00:00:00 2001 From: John Date: Wed, 5 Apr 2023 13:37:05 +0200 Subject: [PATCH 151/189] webkit2gtk: enable jit on riscv64 --- .../patches/fix-riscv64-build.patch | 28 +++++++++++++++++++ srcpkgs/webkit2gtk/template | 2 +- 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 srcpkgs/webkit2gtk/patches/fix-riscv64-build.patch diff --git a/srcpkgs/webkit2gtk/patches/fix-riscv64-build.patch b/srcpkgs/webkit2gtk/patches/fix-riscv64-build.patch new file mode 100644 index 0000000000000..3f599ea3c5698 --- /dev/null +++ b/srcpkgs/webkit2gtk/patches/fix-riscv64-build.patch @@ -0,0 +1,28 @@ +diff --git a/Source/JavaScriptCore/offlineasm/riscv64.rb b/Source/JavaScriptCore/offlineasm/riscv64.rb +index 81f356d04ae1..4abb1761509d 100644 +--- a/Source/JavaScriptCore/offlineasm/riscv64.rb ++++ b/Source/JavaScriptCore/offlineasm/riscv64.rb +@@ -1523,7 +1523,8 @@ def riscv64GenerateWASMPlaceholders(list) + if node.is_a? Instruction + case node.opcode + when "loadlinkacqb", "loadlinkacqh", "loadlinkacqi", "loadlinkacqq", +- "storecondrelb", "storecondrelh", "storecondreli", "storecondrelq" ++ "storecondrelb", "storecondrelh", "storecondreli", "storecondrelq", ++ "loadv", "storev" + newList << Instruction.new(node.codeOrigin, "rv_ebreak", [], "WebAssembly placeholder for opcode #{node.opcode}") + else + newList << node +diff --git a/Source/WTF/wtf/PlatformEnable.h b/Source/WTF/wtf/PlatformEnable.h +index e30a3d8ce077..937fdd447f92 100644 +--- a/Source/WTF/wtf/PlatformEnable.h ++++ b/Source/WTF/wtf/PlatformEnable.h +@@ -616,7 +616,7 @@ + #undef ENABLE_WEBASSEMBLY + #define ENABLE_WEBASSEMBLY 1 + #undef ENABLE_WEBASSEMBLY_B3JIT +-#define ENABLE_WEBASSEMBLY_B3JIT 0 ++#define ENABLE_WEBASSEMBLY_B3JIT 1 + #undef ENABLE_WEBASSEMBLY_BBQJIT + #define ENABLE_WEBASSEMBLY_BBQJIT 0 + #endif + diff --git a/srcpkgs/webkit2gtk/template b/srcpkgs/webkit2gtk/template index 421fa8b2d0c83..9e895f32ca63c 100644 --- a/srcpkgs/webkit2gtk/template +++ b/srcpkgs/webkit2gtk/template @@ -87,7 +87,7 @@ fi # only a few platform support JIT case "$XBPS_TARGET_MACHINE" in - aarch64*|x86_64*) + aarch64*|x86_64*|riscv64*) build_options_default+=" jit" if [ "$XBPS_TARGET_LIBC" = "glibc" ]; then build_options_default+=" sampling_profiler" From 5e0f42673ebb3b390a4baf621b8ea20cd5a2199d Mon Sep 17 00:00:00 2001 From: John Date: Thu, 6 Apr 2023 21:29:27 +0200 Subject: [PATCH 152/189] build-style/zig-build: workaround bug in binutils --- common/environment/build-style/zig-build.sh | 9 +++++++++ .../0108-chromium-cursed^Uscoped_file.patch | 18 ++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch diff --git a/common/environment/build-style/zig-build.sh b/common/environment/build-style/zig-build.sh index 049b7cd437d53..4517d9722f897 100644 --- a/common/environment/build-style/zig-build.sh +++ b/common/environment/build-style/zig-build.sh @@ -1 +1,10 @@ hostmakedepends+=" zig" + +# GNU Binutils fails on programs compiled/linked (?) with llvm +# See: https://sourceware.org/bugzilla//show_bug.cgi?id=30237 +# +if [ "${XBPS_TARGET_MACHINE/-musl/}" = "riscv64" ]; then + hostmakedepends+=" llvm" + OBJCOPY="llvm-objcopy" + STRIP="llvm-strip" +fi diff --git a/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch b/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch new file mode 100644 index 0000000000000..dd31da9790adc --- /dev/null +++ b/srcpkgs/qt6-webengine/patches/0108-chromium-cursed^Uscoped_file.patch @@ -0,0 +1,18 @@ +--- qt6-webengine-6.4.2.orig/src/3rdparty/chromium/base/files/scoped_file_linux.cc ++++ qt6-webengine-6.4.2/src/3rdparty/chromium/base/files/scoped_file_linux.cc +@@ -77,15 +77,3 @@ bool IsFDOwned(int fd) { + } + + } // namespace base +- +-extern "C" { +- +-int __close(int); +- +-__attribute__((visibility("default"), noinline)) int close(int fd) { +- if (base::IsFDOwned(fd) && g_is_ownership_enforced) +- CrashOnFdOwnershipViolation(); +- return __close(fd); +-} +- +-} // extern "C" From 11331b3ed1d7cdb667288007a407951324d1bd1e Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 01:46:18 +0200 Subject: [PATCH 153/189] flashrom: update to 1.3.0. --- srcpkgs/flashrom/template | 42 ++++++++++++++++++--------------------- srcpkgs/libflashrom | 1 + srcpkgs/libflashrom-devel | 1 + 3 files changed, 21 insertions(+), 23 deletions(-) create mode 120000 srcpkgs/libflashrom create mode 120000 srcpkgs/libflashrom-devel diff --git a/srcpkgs/flashrom/template b/srcpkgs/flashrom/template index af1e0d4246030..47d7eb604410d 100644 --- a/srcpkgs/flashrom/template +++ b/srcpkgs/flashrom/template @@ -1,8 +1,8 @@ # Template file for 'flashrom' pkgname=flashrom -version=1.2 -revision=3 -build_style=gnu-makefile +version=1.3.0 +revision=1 +build_style=meson hostmakedepends="pkg-config" makedepends="pciutils-devel libusb-compat-devel libftdi1-devel" short_desc="Utility for reading, writing, erasing and verifying flash ROM chips" @@ -10,25 +10,21 @@ maintainer="teldra " license="GPL-2.0-only" homepage="https://www.flashrom.org" distfiles=https://github.com/flashrom/flashrom/archive/v$version.tar.gz -checksum=a5bac412cefb87bb426912fed46ccc38799d088a9b92dbe7bac38c5df016d9b2 +checksum=91d3ae239e435682561966350d00890b8bf5ae1a947af1f647198aa391196890 -post_patch() { - # The Makefile detection is fragile!!! - # It doesn't defend against __attribute__("something") - case "$XBPS_TARGET_MACHINE" in - x86_64* | i686*) _arch=x86 ;; - aarch64* | arm*) _arch=arm ;; - ppc*) _arch=ppc ;; - mips*) _arch=mips ;; - *) msg_error "Unknown arch\n" ;; - esac - case "$XBPS_TARGET_ENDIAN" in - be) _endian=big ;; - le) _endian=little ;; - esac - vsed -i -e 's/^override TARGET_OS :=.*/TARGET_OS := Linux/' \ - -e "s/^override ARCH :=.*/ARCH := $_arch/" \ - -e "s/^override ENDIAN :=.*/ENDIAN := $_endian/" \ - -e 's/sbin/bin/' \ - Makefile +libflashrom_package() { + short_desc+=" - library files" + pkg_install() { + vmove "usr/lib/*.so.*" + } +} + +libflashrom-devel_package() { + short_desc+=" - development files" + depends="libflashrom>=${version}_${revision}" + pkg_install() { + vmove usr/include + vmove "usr/lib/*.a" + vmove "usr/lib/*.so" + } } diff --git a/srcpkgs/libflashrom b/srcpkgs/libflashrom new file mode 120000 index 0000000000000..183c7f43a41c8 --- /dev/null +++ b/srcpkgs/libflashrom @@ -0,0 +1 @@ +flashrom \ No newline at end of file diff --git a/srcpkgs/libflashrom-devel b/srcpkgs/libflashrom-devel new file mode 120000 index 0000000000000..183c7f43a41c8 --- /dev/null +++ b/srcpkgs/libflashrom-devel @@ -0,0 +1 @@ +flashrom \ No newline at end of file From 708704ee9574cca97fbe5f215e30ddf447bfe94b Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 13:30:18 +0200 Subject: [PATCH 154/189] dep: mark broken on riscv64 --- srcpkgs/dep/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/dep/template b/srcpkgs/dep/template index 53d2ca09c1873..cd5cc219dec61 100644 --- a/srcpkgs/dep/template +++ b/srcpkgs/dep/template @@ -14,6 +14,10 @@ homepage="https://github.com/golang/dep" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=929c8f759838f98323211ba408a831ea80d93b75beda8584b6d950f393a3298a +case $XBPS_TARGET_MACHINE in + riscv64*) broken="Uses boltdb";; +esac + post_install() { vlicense LICENSE } From b4d3fca889bc7f3a02d9f6afdce7bbff55f84ccb Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 13:35:38 +0200 Subject: [PATCH 155/189] go-jira: mark broken on riscv64 --- srcpkgs/go-jira/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/go-jira/template b/srcpkgs/go-jira/template index 5e80ab41445cd..07c0b48b6bf3d 100644 --- a/srcpkgs/go-jira/template +++ b/srcpkgs/go-jira/template @@ -12,3 +12,8 @@ license="Apache-2.0" homepage="https://github.com/go-jira/jira" distfiles="https://github.com/go-jira/jira/archive/v$version.tar.gz" checksum=179abe90458281175a482cbd2e1ad662bdf563ef5acfc2cadf215ae32e0bd1e6 + + +case $XBPS_TARGET_MACHINE in + riscv64*) broken="Outdated unix dep";; +esac From 5750353125de757c4c90fd04c928f8c7e2d8f90b Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 13:59:24 +0200 Subject: [PATCH 156/189] NoiseTorch: add riscv64 patch --- srcpkgs/NoiseTorch/patches/riscv.patch.old | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 srcpkgs/NoiseTorch/patches/riscv.patch.old diff --git a/srcpkgs/NoiseTorch/patches/riscv.patch.old b/srcpkgs/NoiseTorch/patches/riscv.patch.old new file mode 100644 index 0000000000000..739a0f67d0861 --- /dev/null +++ b/srcpkgs/NoiseTorch/patches/riscv.patch.old @@ -0,0 +1,11 @@ +--- a/vendor/golang.org/x/exp/shiny/driver/x11driver/shm_shmopen_syscall.go 2021-09-28 16:27:57.000000000 +0200 ++++ - 2023-04-08 13:42:39.358728873 +0200 +@@ -3,7 +3,7 @@ + // license that can be found in the LICENSE file. + + // +build linux dragonfly +-// +build amd64 arm arm64 mips64 mips64le ++// +build amd64 arm arm64 mips64 mips64le riscv64 + + package x11driver + From 65180035e54c501862a5c58421627622919c6fd9 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 14:06:18 +0200 Subject: [PATCH 157/189] kodi-addon-inputstream-adaptive: add riscv64 patch --- .../patches/riscv.patch | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 srcpkgs/kodi-addon-inputstream-adaptive/patches/riscv.patch diff --git a/srcpkgs/kodi-addon-inputstream-adaptive/patches/riscv.patch b/srcpkgs/kodi-addon-inputstream-adaptive/patches/riscv.patch new file mode 100644 index 0000000000000..6460182972950 --- /dev/null +++ b/srcpkgs/kodi-addon-inputstream-adaptive/patches/riscv.patch @@ -0,0 +1,20 @@ +--- kodi-addon-inputstream-adaptive-2.6.7/wvdecrypter/cdm/build/build_config.h 2021-02-10 21:23:12.000000000 +0100 ++++ - 2023-04-08 14:05:51.583643126 +0200 +@@ -138,6 +138,17 @@ + #define ARCH_CPU_32_BITS 1 + #define ARCH_CPU_LITTLE_ENDIAN 1 + #endif ++#elif defined(__riscv) || defined(__riscv__) ++#define ARCH_CPU_RISCV_FAMILY 1 ++#define ARCH_CPU_RISCV 1 ++#define ARCH_CPU_LITTLE_ENDIAN 1 ++#if defined(__riscv_xlen) ++# if (__riscv_xlen == 64) ++# define ARCH_CPU_64_BITS 1 ++# else ++# define ARCH_CPU_32_BITS 1 ++# endif ++#endif + #else + #error Please add support for your architecture in build/build_config.h + #endif From ae6a0bdcea78f60b6de6c0221fad9b2b86cdf048 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 14:09:05 +0200 Subject: [PATCH 158/189] ripgrep: mark broken on riscv64-musl --- srcpkgs/ripgrep/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/ripgrep/template b/srcpkgs/ripgrep/template index 883cd105872fc..00b7c07d393c9 100644 --- a/srcpkgs/ripgrep/template +++ b/srcpkgs/ripgrep/template @@ -13,6 +13,10 @@ homepage="https://github.com/BurntSushi/ripgrep/" distfiles="https://github.com/BurntSushi/${pkgname}/archive/${version}.tar.gz" checksum=0fb17aaf285b3eee8ddab17b833af1e190d73de317ff9648751ab0660d763ed2 +case $XBPS_TARGET_MACHINE in + riscv64-musl) broken="jemalloc";; +esac + pre_build() { # Newer libc needed for riscv64 cargo update --package libc --precise 0.2.139 From a10167f59bbf78736c1712ff1060a8fa9c3284da Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 14:14:11 +0200 Subject: [PATCH 159/189] python3-pyside2: update to 5.15.9. --- .../python3-pyside2/patches/python-importlib.patch | 12 ++++++++++++ srcpkgs/python3-pyside2/patches/python3.11.patch | 11 +++++++++++ srcpkgs/python3-pyside2/template | 6 +++--- 3 files changed, 26 insertions(+), 3 deletions(-) create mode 100644 srcpkgs/python3-pyside2/patches/python-importlib.patch diff --git a/srcpkgs/python3-pyside2/patches/python-importlib.patch b/srcpkgs/python3-pyside2/patches/python-importlib.patch new file mode 100644 index 0000000000000..f22027994e698 --- /dev/null +++ b/srcpkgs/python3-pyside2/patches/python-importlib.patch @@ -0,0 +1,12 @@ +diff -ru pyside-setup-opensource-src-5.15.6.orig/sources/shiboken2/libshiboken/embed/signature_bootstrap.py pyside-setup-opensource-src-5.15.6/sources/shiboken2/libshiboken/embed/signature_bootstrap.py +--- pyside-setup-opensource-src-5.15.6.orig/sources/shiboken2/libshiboken/embed/signature_bootstrap.py 2022-09-08 23:54:19.419724864 +0200 ++++ pyside-setup-opensource-src-5.15.6/sources/shiboken2/libshiboken/embed/signature_bootstrap.py 2022-09-08 23:55:04.494277606 +0200 +@@ -211,7 +211,7 @@ + return self if self._mod2path.get(fullname) else None + + def load_module(self, fullname): +- import importlib ++ import importlib.machinery + import sys + + filename = self._mod2path.get(fullname) diff --git a/srcpkgs/python3-pyside2/patches/python3.11.patch b/srcpkgs/python3-pyside2/patches/python3.11.patch index 3522f4e817e04..ea77b6daa827a 100644 --- a/srcpkgs/python3-pyside2/patches/python3.11.patch +++ b/srcpkgs/python3-pyside2/patches/python3.11.patch @@ -209,3 +209,14 @@ diff -rU3 pyside-setup-opensource-src-5.15.2-orig/build_scripts/config.py pyside ] self.setup_script_dir = None +--- pyside-setup-opensource-src-5.15.7/sources/shiboken2/libshiboken/pep384impl.cpp 2022-09-23 08:47:20.000000000 +0200 ++++ pyside-setup-opensource-src-5.15.8/sources/shiboken2/libshiboken/pep384impl.cpp 2023-01-04 08:07:17.000000000 +0100 +@@ -751,7 +751,7 @@ + #endif // IS_PY2 + Shiboken::AutoDecRef privateobj(PyObject_GetAttr( + reinterpret_cast(Py_TYPE(self)), Shiboken::PyMagicName::name())); +-#ifndef Py_LIMITED_API ++#if !defined(Py_LIMITED_API) && PY_VERSION_HEX < 0x03010000 + return _Py_Mangle(privateobj, name); + #else + // PYSIDE-1436: _Py_Mangle is no longer exposed; implement it always. diff --git a/srcpkgs/python3-pyside2/template b/srcpkgs/python3-pyside2/template index 50e6ff260d3b5..5b16061d51577 100644 --- a/srcpkgs/python3-pyside2/template +++ b/srcpkgs/python3-pyside2/template @@ -1,7 +1,7 @@ # Template file for 'python3-pyside2' pkgname=python3-pyside2 -version=5.15.5 -revision=2 +version=5.15.9 +revision=1 _pkgname="pyside-setup-opensource-src-${version}" build_wrksrc="sources/pyside2" build_style=cmake @@ -23,7 +23,7 @@ maintainer="yopito " license="LGPL-3.0-or-later" homepage="https://wiki.qt.io/Qt_for_Python" distfiles="https://download.qt.io/official_releases/QtForPython/pyside2/PySide2-${version}-src/${_pkgname}.tar.xz" -checksum=3920a4fb353300260c9bc46ff70f1fb975c5e7efa22e9d51222588928ce19b33 +checksum=2ea5917652036a9007d66ba4dc0aa75f381a3a25ccf0fa70fa2d9e9c8c9dacae build_options="webengine" desc_option_webengine="Build Qt5 WebEngine bindings" From 3a80987034e687cdc2de34eb28144b059cc2a3e2 Mon Sep 17 00:00:00 2001 From: John Date: Sat, 8 Apr 2023 14:34:18 +0200 Subject: [PATCH 160/189] shiboken2: update to 5.15.9. --- srcpkgs/shiboken2/template | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/srcpkgs/shiboken2/template b/srcpkgs/shiboken2/template index 084ecc3ba1e1c..9b37674637540 100644 --- a/srcpkgs/shiboken2/template +++ b/srcpkgs/shiboken2/template @@ -1,6 +1,6 @@ # Template file for 'shiboken2' pkgname=shiboken2 -version=5.15.7 +version=5.15.9 revision=1 _pkgname="pyside-setup-opensource-src-${version}" build_wrksrc="sources/shiboken2" @@ -14,7 +14,7 @@ maintainer="yopito " license="GPL-3.0-or-later" homepage="https://wiki.qt.io/Qt_for_Python/Shiboken" distfiles="https://download.qt.io/official_releases/QtForPython/pyside2/PySide2-${version}-src/${_pkgname}.tar.xz" -checksum=f61210ae24e6882d5d0ca0059229e5dc4f35e2bca92dd6caf96c0f41943a8294 +checksum=2ea5917652036a9007d66ba4dc0aa75f381a3a25ccf0fa70fa2d9e9c8c9dacae python_version=3 export CLANG_INSTALL_DIR=${XBPS_CROSS_BASE}/usr From df6fdaa7f553787c98af9de826f9d32c93981f23 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:39:33 +0200 Subject: [PATCH 161/189] py-spy: add riscv64 patch --- srcpkgs/py-spy/patches/riscv.patch | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 srcpkgs/py-spy/patches/riscv.patch diff --git a/srcpkgs/py-spy/patches/riscv.patch b/srcpkgs/py-spy/patches/riscv.patch new file mode 100644 index 0000000000000..d853395535093 --- /dev/null +++ b/srcpkgs/py-spy/patches/riscv.patch @@ -0,0 +1,13 @@ +diff --git a/src/python_bindings/mod.rs b/src/python_bindings/mod.rs +index e69156a..2de0b3d 100644 +--- a/src/python_bindings/mod.rs ++++ b/src/python_bindings/mod.rs +@@ -121,7 +121,7 @@ pub mod pyruntime { + } + } + +- #[cfg(all(target_os="linux", target_arch="x86_64"))] ++ #[cfg(all(target_os="linux", any(target_arch="x86_64", target_arch="riscv64")))] + pub fn get_tstate_current_offset(version: &Version) -> Option { + match version { + Version{major: 3, minor: 7, patch: 0..=3, ..} => Some(1392), From 75ee6aa495b85187cc793e2c56ddca2fe4e99a47 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:42:15 +0200 Subject: [PATCH 162/189] kubernetes-helm: mark broken on riscv64 --- srcpkgs/kubernetes-helm/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/kubernetes-helm/template b/srcpkgs/kubernetes-helm/template index 7fbcdc2c9b63a..4fc761a5c1353 100644 --- a/srcpkgs/kubernetes-helm/template +++ b/srcpkgs/kubernetes-helm/template @@ -12,6 +12,10 @@ checksum=320076ba47bfdf31f753e92fe8464a1314600ff365acce3b361e067488364b33 conflicts="helm" nopie=true +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="gox just silently skips unkown archs?";; +esac + _convert_arch() { case "$1" in aarch64*) echo arm64;; @@ -20,6 +24,7 @@ _convert_arch() { i686*) echo 386;; x86_64*) echo amd64;; ppc64le*) echo ppc64le;; + riscv64*) echo riscv64;; esac } From 2769961dcff03432f59820c7bfecba039ed01599 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:50:25 +0200 Subject: [PATCH 163/189] NetAuth: mark broken on riscv64 --- srcpkgs/NetAuth/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/NetAuth/template b/srcpkgs/NetAuth/template index 08d5f78d0da88..56f1c7261f747 100644 --- a/srcpkgs/NetAuth/template +++ b/srcpkgs/NetAuth/template @@ -15,6 +15,10 @@ homepage="https://netauth.org" distfiles="https://github.com/NetAuth/NetAuth/archive/v$version.tar.gz" checksum=cf84b2e63b7a59ec6e415ead1a94994b040b30fee2b27e482073371cfb0fb444 +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="boltdb";; +esac + post_install() { for sh in bash zsh; do vtargetrun ${DESTDIR}/usr/bin/netauth system cli ${sh} netauth.${sh} From 45446353fb9258bc9ddfad49af28b14f58fce67f Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:56:28 +0200 Subject: [PATCH 164/189] gomatrix: mark broken on riscv64 --- srcpkgs/gomatrix/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/gomatrix/template b/srcpkgs/gomatrix/template index c78893ef1337a..f36db03caf9b7 100644 --- a/srcpkgs/gomatrix/template +++ b/srcpkgs/gomatrix/template @@ -11,6 +11,10 @@ homepage="https://github.com/GeertJohan/gomatrix" distfiles="https://github.com/GeertJohan/gomatrix/archive/v${version}.tar.gz" checksum=4d71d2509ac84f2340537d5e6f0eb9810b4173706f13cd6fe5e5e8ee5a69a50c +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Old sys dependency";; +esac + post_install() { vlicense LICENSE } From 70bf702a34b2fc6bec9a1caaadd7726cec16b98b Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:58:32 +0200 Subject: [PATCH 165/189] netns: mark broken on riscv64 --- srcpkgs/netns/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/netns/template b/srcpkgs/netns/template index 71287f72ce3da..b9f1a5e1d55ad 100644 --- a/srcpkgs/netns/template +++ b/srcpkgs/netns/template @@ -11,6 +11,10 @@ homepage="https://github.com/genuinetools/netns" distfiles="https://github.com/genuinetools/netns/archive/v${version}.tar.gz" checksum=3a55e96e71067989902b65a6de74f1ebbb63ea3f6fc85184523e8d289b0eb35d +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Some rather olt etcd.io/bbolt dep";; +esac + post_install() { vlicense LICENSE } From 4a4d99538d40b5e2ab70bc54840773ba569c5df4 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 13:59:32 +0200 Subject: [PATCH 166/189] gperftools: update to 2.10. --- .../patches/sigev_notify_thread_id.patch | 65 ------------------- srcpkgs/gperftools/template | 6 +- 2 files changed, 3 insertions(+), 68 deletions(-) delete mode 100644 srcpkgs/gperftools/patches/sigev_notify_thread_id.patch diff --git a/srcpkgs/gperftools/patches/sigev_notify_thread_id.patch b/srcpkgs/gperftools/patches/sigev_notify_thread_id.patch deleted file mode 100644 index a275eb59bbeb8..0000000000000 --- a/srcpkgs/gperftools/patches/sigev_notify_thread_id.patch +++ /dev/null @@ -1,65 +0,0 @@ -From d9c4c3b481e641b719d3d790987ed7d094157bf2 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?=C4=90o=C3=A0n=20Tr=E1=BA=A7n=20C=C3=B4ng=20Danh?= - -Date: Fri, 12 Feb 2021 19:21:18 +0700 -Subject: [PATCH] profile-handler: use documented sigev_notify_thread_id in - sigevent - -sigevent(7) is documented to have sigev_notify_thread_id as its member. -In glibc system, it's a macro expanded to the legacy _sigev_un._tid, -_sigev_un._tid is obviously an internal implementation detail as -signaled by its underscore prefix. And this macro was hidden inside -linux/signal.h in older version of glibc. - -On Linux that use musl libc, sigev_notify_thread_id is also a macro, but -it's expanded to __sev_fields.sigev_notify_thread_id - -[alkondratenko@gmail.com: amputated broken linux/signal.h dependency] -[alkondratenko@gmail.com: see https://github.com/gperftools/gperftools/pull/1250] -Signed-off-by: Aliaksey Kandratsenka ---- - src/profile-handler.cc | 17 ++++++++++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git src/profile-handler.cc src/profile-handler.cc -index 7fdcb693..fe3715b1 100644 ---- a/src/profile-handler.cc -+++ b/src/profile-handler.cc -@@ -49,6 +49,9 @@ - #if HAVE_LINUX_SIGEV_THREAD_ID - // for timer_{create,settime} and associated typedefs & constants - #include -+// for sigevent -+#include -+ - // for sys_gettid - #include "base/linux_syscall_support.h" - // for perftools_pthread_key_create -@@ -61,6 +64,18 @@ - #include "base/spinlock.h" - #include "maybe_threads.h" - -+// Some Linux systems don't have sigev_notify_thread_id defined in -+// signal.h (despite having SIGEV_THREAD_ID defined) and also lack -+// working linux/signal.h. So lets workaround. Note, we know that at -+// least on Linux sigev_notify_thread_id is macro. -+// -+// See https://sourceware.org/bugzilla/show_bug.cgi?id=27417 and -+// https://bugzilla.kernel.org/show_bug.cgi?id=200081 -+// -+#if __linux__ && HAVE_LINUX_SIGEV_THREAD_ID && !defined(sigev_notify_thread_id) -+#define sigev_notify_thread_id _sigev_un._tid -+#endif -+ - using std::list; - using std::string; - -@@ -272,7 +287,7 @@ static void StartLinuxThreadTimer(int timer_type, int signal_number, - struct itimerspec its; - memset(&sevp, 0, sizeof(sevp)); - sevp.sigev_notify = SIGEV_THREAD_ID; -- sevp._sigev_un._tid = sys_gettid(); -+ sevp.sigev_notify_thread_id = sys_gettid(); - sevp.sigev_signo = signal_number; - clockid_t clock = CLOCK_THREAD_CPUTIME_ID; - if (timer_type == ITIMER_REAL) { diff --git a/srcpkgs/gperftools/template b/srcpkgs/gperftools/template index de7e9423d343b..9627938c56836 100644 --- a/srcpkgs/gperftools/template +++ b/srcpkgs/gperftools/template @@ -1,7 +1,7 @@ # Template file for 'gperftools' pkgname=gperftools -version=2.8 -revision=2 +version=2.10 +revision=1 build_style=gnu-configure hostmakedepends="automake libtool" makedepends="libunwind-devel" @@ -11,7 +11,7 @@ maintainer="Enno Boland " license="BSD-3-Clause" homepage="https://github.com/gperftools/gperftools" distfiles="${homepage}/releases/download/${pkgname}-${version}/${pkgname}-${version}.tar.gz" -checksum=240deacdd628b6459671b83eb0c4db8e97baadf659f25b92e9a078d536bd513e +checksum=83e3bfdd28b8bcf53222c3798d4d395d52dadbbae59e8730c4a6d31a9c3732d8 if [ "$XBPS_TARGET_LIBC" = "musl" ]; then # needed by some newly enabled code From 8e1c760f48f5b91600a029c33106e45c61b9bfe4 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:08:27 +0200 Subject: [PATCH 167/189] grpc: mark broken on riscv64 --- srcpkgs/grpc/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/grpc/template b/srcpkgs/grpc/template index d7cbf441d44de..6c263c8ddeff5 100644 --- a/srcpkgs/grpc/template +++ b/srcpkgs/grpc/template @@ -30,6 +30,10 @@ skip_extraction=" opencensus-proto-v${_opencensus}.tar.gz xds-${_xds}.tar.gz" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Smth with abseil?";; +esac + if [ "$CROSS_BUILD" ]; then # need host grpc_cpp_plugin hostmakedepends+=" grpc" From c35b5196721881ba1dd836fbe7c5958f5e451187 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:12:14 +0200 Subject: [PATCH 168/189] cri-o: mark broken on riscv64 --- srcpkgs/cri-o/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/cri-o/template b/srcpkgs/cri-o/template index 47cb2865d09c6..4e2e678c4ca3e 100644 --- a/srcpkgs/cri-o/template +++ b/srcpkgs/cri-o/template @@ -22,6 +22,10 @@ if [ "$CROSS_BUILD" ]; then hostmakedepends+=" cri-o-devel" fi +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Some old vendored lib :shrug:";; +esac + post_build() { cd conmon if [ "$CROSS_BUILD" ]; then From 45626862c1f7af6bee9793fee18555101ed0ecfc Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:14:56 +0200 Subject: [PATCH 169/189] xi-editor: mark broken on riscv64 --- srcpkgs/xi-editor/template | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/srcpkgs/xi-editor/template b/srcpkgs/xi-editor/template index cc3f658ccdf2f..d12801f7ed84a 100644 --- a/srcpkgs/xi-editor/template +++ b/srcpkgs/xi-editor/template @@ -10,3 +10,8 @@ license="Apache-2.0" homepage="https://github.com/xi-editor/xi-editor" distfiles="https://github.com/xi-editor/xi-editor/archive/v${version}.tar.gz" checksum=e42998ad9b6d6df0f797afd005f9c1286aad24c30a77d0dd380730c248274b8d + +# Xi editor is discontinued +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Old libc create";; +esac From 99ef996893ef09f90195c27a917010e758f8b269 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:15:53 +0200 Subject: [PATCH 170/189] firefox-esr: mark broken on riscv64 for now --- srcpkgs/firefox-esr/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template index 2ddcc411b92eb..bb74560f749c9 100644 --- a/srcpkgs/firefox-esr/template +++ b/srcpkgs/firefox-esr/template @@ -40,6 +40,7 @@ case $XBPS_TARGET_MACHINE in armv[56]*) broken="required NEON extensions are not supported on armv6" ;; ppc64*) ;; ppc*) broken="xptcall bitrot" ;; + riscv64*) broken="Not supported yet";; esac # we need this because cargo verifies checksums of all files in vendor From 646da5c73a76534d59fb165c48ee66b47ca750b8 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:17:28 +0200 Subject: [PATCH 171/189] kcgi: mark broken on riscv64 --- srcpkgs/kcgi/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/kcgi/template b/srcpkgs/kcgi/template index 7d7525e43abe4..2b935a3cf7d27 100644 --- a/srcpkgs/kcgi/template +++ b/srcpkgs/kcgi/template @@ -19,6 +19,10 @@ checksum=d886e5700f5ec72b00cb668e9f06b7b3906b6ccdc5bab4c89e436d4cc4c0c7a1 export CFLAGS="-DENABLE_SECCOMP_FILTER=1" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken=" #error Unknown seccomp arch: please contact us with your uname -m";; +esac + seccomp_audit_get_suffix() { case "$1" in i686*) echo "X86" ;; From 80a2f59ab6daf7460e8e6f388787046ee4e3b927 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 14:20:05 +0200 Subject: [PATCH 172/189] nomad: mark broken on riscv64 --- srcpkgs/nomad/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/nomad/template b/srcpkgs/nomad/template index 121edb0dde2da..af68376f6b790 100644 --- a/srcpkgs/nomad/template +++ b/srcpkgs/nomad/template @@ -17,6 +17,10 @@ checksum=21bb378584a3f0e3bf3731f89b64658fedf20c829de8eedba9a6773cddfa0c3e make_dirs="/etc/nomad.d 0755 root root /var/lib/nomad 0755 root root" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="boltdb" +esac + post_install() { vlicense LICENSE vsv nomad From aa235beb1bd079241bd3de1cdf0b9d5a55292fd5 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 19:29:58 +0200 Subject: [PATCH 173/189] hobbits: set fsigned for riscv64 --- srcpkgs/hobbits/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/hobbits/template b/srcpkgs/hobbits/template index c4c008e021ff3..d5827c740b78f 100644 --- a/srcpkgs/hobbits/template +++ b/srcpkgs/hobbits/template @@ -30,7 +30,7 @@ case "$XBPS_TARGET_MACHINE" in esac case "$XBPS_TARGET_MACHINE" in - arm*|aarch64*|ppc*) CXXFLAGS+=" -fsigned-char" + arm*|aarch64*|ppc*|riscv64*) CXXFLAGS+=" -fsigned-char" esac post_extract() { From d1661ede85899516d2a50126087b3cebb9e78fe2 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 19:36:11 +0200 Subject: [PATCH 174/189] unicorn: mark broken on riscv64 for now --- srcpkgs/unicorn/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/unicorn/template b/srcpkgs/unicorn/template index 3afdc86b7ad6d..65e5a68fe3b7c 100644 --- a/srcpkgs/unicorn/template +++ b/srcpkgs/unicorn/template @@ -10,6 +10,10 @@ homepage="https://www.unicorn-engine.org/" distfiles="https://github.com/unicorn-engine/unicorn/archive/${version}.tar.gz" checksum=6400e16f9211486fa5353b1870e6a82f8aa342e429718d1cbca08d609aaadc52 +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Wait for update";; +esac + post_patch() { # don't build the samples echo "clean:" > samples/Makefile From d78b1941b08b9ffc100eecde4612d344dd5f4ee8 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 19:40:07 +0200 Subject: [PATCH 175/189] influxdb: mark broken on riscv64 --- srcpkgs/influxdb/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/influxdb/template b/srcpkgs/influxdb/template index 70544e746f864..ecbe3a24c41a0 100644 --- a/srcpkgs/influxdb/template +++ b/srcpkgs/influxdb/template @@ -24,6 +24,10 @@ _influxdb_homedir="/var/lib/influxdb" make_dirs="${_influxdb_homedir} 0755 _influxdb _influxdb" conf_files="/etc/${pkgname}/${pkgname}.conf" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="boltdb";; +esac + post_build() { make -C man build } From f77a40254b3a1452f50644a1230136e0451072b9 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 9 Apr 2023 19:43:28 +0200 Subject: [PATCH 176/189] mysql++: nocross --- srcpkgs/mysql++/template | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/srcpkgs/mysql++/template b/srcpkgs/mysql++/template index 2e26a322d3929..ad3665b8a7b35 100644 --- a/srcpkgs/mysql++/template +++ b/srcpkgs/mysql++/template @@ -26,8 +26,9 @@ mysql++-devel_package() { } } -case "${XBPS_TARGET_MACHINE}" in - arm*|aarch64*|mips*) - broken="${XBPS_TARGET_MACHINE} not supported yet" - ;; -esac +nocross=yes # It builds just fine +#case "${XBPS_TARGET_MACHINE}" in +# arm*|aarch64*|mips*) +# broken="${XBPS_TARGET_MACHINE} not supported yet" +# ;; +#esac From 465e96c014aaac05903ce718fcdab6fa310c086a Mon Sep 17 00:00:00 2001 From: John Date: Thu, 13 Apr 2023 18:56:48 +0200 Subject: [PATCH 177/189] xbps: set riscv64 repos --- srcpkgs/xbps/template | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/srcpkgs/xbps/template b/srcpkgs/xbps/template index 2d02a562b4954..bd0ee9c24f500 100644 --- a/srcpkgs/xbps/template +++ b/srcpkgs/xbps/template @@ -42,6 +42,12 @@ post_install() { aarch64*) suffix="/aarch64";; *-musl) suffix="/musl";; esac + case "$XBPS_TARGET_MACHINE" in + riscv64) repo="https://void.johnnynator.dev/current" + suffix="riscv64/";; + riscv64-musl) repo="https://void.johnnynator.dev/current" + suffix="riscv64-musl/";; + esac echo "repository=${repo}${suffix}" > \ ${DESTDIR}/usr/share/xbps.d/00-repository-main.conf From 197ced96de7c8f35f117d146a4c5746581df72d6 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 01:29:32 +0200 Subject: [PATCH 178/189] amber: mark broken for now --- srcpkgs/amber/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/amber/template b/srcpkgs/amber/template index 0d8f235148279..2fdadee34710a 100644 --- a/srcpkgs/amber/template +++ b/srcpkgs/amber/template @@ -10,6 +10,10 @@ homepage="https://github.com/dalance/amber" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=bf974e997fffa0d54463fc85e44f054563372ca4dade50099fb6ecec0ca8c483 +case $XBPS_TARGET_MACHINE in + riscv64*) broken=":shrug:";; +esac + post_install() { vlicense LICENSE } From f4381fc5388d1a17548e633d7067f6c89d2f2f5a Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 01:30:55 +0200 Subject: [PATCH 179/189] gnome-authenticator/: mark broken for now --- srcpkgs/gnome-authenticator/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/gnome-authenticator/template b/srcpkgs/gnome-authenticator/template index c2aa2c8c08660..c7c9a95ea423c 100644 --- a/srcpkgs/gnome-authenticator/template +++ b/srcpkgs/gnome-authenticator/template @@ -19,6 +19,10 @@ make_check=ci-skip # Test timeout while compiling tests export BINDGEN_EXTRA_CLANG_ARGS="${BINDGEN_EXTRA_CLANG_ARGS} -DPW_ENABLE_DEPRECATED" +case "$XBPS_TARGET_MACHINE" in + riscv64*) broken="Something pulls in an old unsupported nix crate";; +esac + post_patch() { [ -z "$CROSS_BUILD" ] && return 0 vsed -i src/meson.build \ From d31a0f0669b3876541f5aebff9f3bb473b3fe519 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 01:32:08 +0200 Subject: [PATCH 180/189] orz: mark broken for now --- srcpkgs/orz/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/orz/template b/srcpkgs/orz/template index 335e94f6b32d3..5727ff8509e06 100644 --- a/srcpkgs/orz/template +++ b/srcpkgs/orz/template @@ -10,6 +10,10 @@ homepage="https://github.com/richox/orz" distfiles="${homepage}/archive/v${version}.tar.gz" checksum=ff9f8d77084f0510cfb4966be7cf02a00c4a17715879dfdb85eaa1380023a7c7 +case $XBPS_TARGET_MACHINE in + riscv64*) broken=":shrug:";; +esac + post_install() { vlicense LICENSE } From 93577a82463245481984e9f2412eeef910c482bd Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 01:32:58 +0200 Subject: [PATCH 181/189] todoist: do not build on riscv64 yet --- srcpkgs/todoist/template | 1 + 1 file changed, 1 insertion(+) diff --git a/srcpkgs/todoist/template b/srcpkgs/todoist/template index 15a2fba8864d6..5f998669fe0c2 100644 --- a/srcpkgs/todoist/template +++ b/srcpkgs/todoist/template @@ -3,6 +3,7 @@ pkgname=todoist version=0.20.0 revision=2 build_style=go +archs="~riscv64*" go_import_path="github.com/sachaos/todoist" short_desc="Todoist CLI Client" maintainer="Gerardo Di Iorio " From 2b35c279d76585a5f230a48f3b52335884e7f284 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 01:43:33 +0200 Subject: [PATCH 182/189] alert-after: bump libc crate for riscv64 --- srcpkgs/alert-after/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/alert-after/template b/srcpkgs/alert-after/template index 8345dc5196241..9b1fd41352cb7 100644 --- a/srcpkgs/alert-after/template +++ b/srcpkgs/alert-after/template @@ -11,3 +11,7 @@ license="Apache-2.0" homepage="https://crates.io/crates/alert-after" distfiles="https://github.com/frewsxcv/alert-after/archive/${version}.tar.gz" checksum=f40dd43f667735741be95f753e52d3ec36731fcb3c3217084ad07e70dbac7a2a + +post_patch() { + cargo update --package libc@0.2.51 --precise 0.2.139 +} From 25e66073c88d78a834bbb29bf1e3724c64af2724 Mon Sep 17 00:00:00 2001 From: John Date: Fri, 14 Apr 2023 02:43:26 +0200 Subject: [PATCH 183/189] tmplgen: update libc crate for riscv64 --- srcpkgs/tmplgen/template | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/srcpkgs/tmplgen/template b/srcpkgs/tmplgen/template index f51cced3b077f..42887e53e81cf 100644 --- a/srcpkgs/tmplgen/template +++ b/srcpkgs/tmplgen/template @@ -14,6 +14,10 @@ checksum=8c8aa5b65045614529626978852416a965d57c77dd5953be58bc84f8d8b27f9b # cba for now, tests weren't shipped in the previous tarballs make_check=no +post_patch() { + cargo update --package libc@0.2.49 --precise 0.2.139 +} + post_install() { vman man/tmplgen.1 } From abed9c763e11b9a3ba255aaf486cacf7754bca40 Mon Sep 17 00:00:00 2001 From: John Date: Sun, 2 Jul 2023 01:38:13 +0200 Subject: [PATCH 184/189] fixup! flatpak: add missing -devel dependency --- srcpkgs/flatpak/template | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/srcpkgs/flatpak/template b/srcpkgs/flatpak/template index 2f7b6b0187921..fa8eaf8b7b919 100644 --- a/srcpkgs/flatpak/template +++ b/srcpkgs/flatpak/template @@ -48,7 +48,7 @@ flatpak-devel_package() { short_desc+=" - development files" depends="${sourcepkg}>=${version}_${revision} libglib-devel libostree-devel libcurl-devel libarchive-devel json-glib-devel dconf-devel libseccomp-devel - gpgme-devel" + gpgme-devel polkit-devel" pkg_install() { vmove usr/include vmove usr/lib/pkgconfig From 99d3e4b313e97b552056479cb64e016d6d5cc464 Mon Sep 17 00:00:00 2001 From: John Date: Tue, 11 Jul 2023 08:59:08 +0200 Subject: [PATCH 185/189] linux6.3: add riscv64 bits --- srcpkgs/linux6.3/files/riscv-dotconfig | 10595 ++++++++++++++++ ...k-Add-StarFive-JH7110-system-clock-a.patch | 532 + ...k-Add-StarFive-JH7110-always-on-cloc.patch | 184 + ...lace-SOC_STARFIVE-with-ARCH_STARFIVE.patch | 57 + ...tor-out-common-JH7100-and-JH7110-cod.patch | 760 ++ ...ame-clk-starfive-jh7100.h-to-clk-sta.patch | 67 + ...ame-jh7100-to-jh71x0-for-the-common-.patch | 1258 ++ ...eplace-SOC_STARFIVE-with-ARCH_STARFI.patch | 33 + ...te-subdirectory-for-StarFive-drivers.patch | 99 + ...-Factor-out-common-JH71X0-reset-code.patch | 403 + ...Extract-the-common-JH71X0-reset-code.patch | 222 + ...ename-jh7100-to-jh71x0-for-the-commo.patch | 174 + ...h71x0-Use-32bit-I-O-on-32bit-registe.patch | 153 + ...-StarFive-JH7110-system-clock-driver.patch | 567 + ...-StarFive-JH7110-always-on-clock-dri.patch | 214 + ...ive-Add-StarFive-JH7110-reset-driver.patch | 121 + ...ings-timer-Add-StarFive-JH7110-clint.patch | 30 + ...rrupt-controller-Add-StarFive-JH7110.patch | 31 + ...dings-riscv-Add-SiFive-S7-compatible.patch | 30 + ...ve-Add-initial-StarFive-JH7110-devic.patch | 539 + ...ve-Add-StarFive-JH7110-pin-function-.patch | 335 + ...ve-Add-StarFive-JH7110-VisionFive-2-.patch | 302 + ...ve-jh7110-Correct-the-properties-of-.patch | 43 + ...hdog-Add-watchdog-for-StarFive-JH710.patch | 97 + ...atchdog-Add-StarFive-Watchdog-driver.patch | 687 + ...ts-starfive-jh7100-Add-watchdog-node.patch | 36 + ...er-Add-timer-for-StarFive-JH7110-SoC.patch | 119 + ...locksource-Add-StarFive-timer-driver.patch | 572 + ...v-dts-jh7110-starfive-Add-timer-node.patch | 46 + ...dings-hwmon-Add-starfive-jh71x0-temp.patch | 95 + ...d-StarFive-JH71x0-temperature-sensor.patch | 467 + ...-cdns-qspi-nor-constrain-minItems-ma.patch | 83 + ...spi-Add-support-for-StarFive-JH7110-.patch | 86 + ...ive-Enable-axp15060-pmic-for-cpufreq.patch | 42 + ...tdev-Add-JH7110-SOC-to-the-allowlist.patch | 29 + ...rfive-Add-cpu-scaling-for-JH7110-SoC.patch | 113 + ...k-Add-StarFive-JH7110-System-Top-Gro.patch | 203 + ...-StarFive-JH7110-System-Top-Group-cl.patch | 228 + ...k-Add-StarFive-JH7110-Image-Signal-P.patch | 166 + ...-StarFive-JH7110-Image-Signal-Proces.patch | 305 + ...k-Add-StarFive-JH7110-Video-Output-c.patch | 173 + ...-StarFive-JH7110-Video-Output-clock-.patch | 294 + ...te-maintainer-of-JH71x0-clock-driver.patch | 28 + ...h7110-Add-StarFive-STG-ISP-VOUT-rese.patch | 66 + ...ve-jh7110-Add-DVP-and-HDMI-TX-pixel-.patch | 74 + ...ve-jh7110-Add-STGCRG-ISPCRG-VOUTCRG-.patch | 98 + ...gs-crypto-Add-StarFive-crypto-module.patch | 95 + ...o-starfive-Add-crypto-engine-support.patch | 355 + ...ve-Add-crypto-and-DMA-node-for-Visio.patch | 58 + ...o-starfive-Add-hash-and-HMAC-support.patch | 1149 ++ ...bindings-PWM-Add-StarFive-PWM-module.patch | 77 + ...-pwm-starfive-Add-PWM-driver-support.patch | 304 + ...et-snps-dwmac-Add-dwmac-5.20-version.patch | 53 + ...orm-Add-snps-dwmac-5.20-IP-compatibl.patch | 33 + ...-snps-dwmac-Add-ahb-reset-reset-name.patch | 50 + ...dings-net-Add-support-StarFive-dwmac.patch | 181 + ...d-glue-layer-for-StarFive-JH7110-SoC.patch | 185 + ...-starfive-Add-phy-interface-settings.patch | 96 + ...ings-phy-Add-StarFive-JH7110-USB-PHY.patch | 74 + ...ngs-phy-Add-StarFive-JH7110-PCIe-PHY.patch | 83 + ...arfive-Add-JH7110-USB-2.0-PHY-driver.patch | 185 + ...rfive-Add-JH7110-PCIE-2.0-PHY-driver.patch | 226 + ...b-Add-StarFive-JH7110-USB-controller.patch | 157 + ...cdns3-Add-StarFive-JH7110-USB-driver.patch | 467 + ...ve-Add-USB-dts-configuration-for-JH7.patch | 91 + ...k-Add-StarFive-JH7110-PLL-clock-gene.patch | 88 + ...Add-StarFive-JH7110-PLL-clock-driver.patch | 704 + ...k-jh7110-syscrg-Add-PLL-clock-inputs.patch | 79 + ...-jh7110-sys-Modify-PLL-clocks-source.patch | 78 + ...-starfive-Add-StarFive-syscon-module.patch | 92 + ...dts-starfive-jh7110-Add-syscon-nodes.patch | 60 + ...ve-jh7110-Add-PLL-clock-node-and-mod.patch | 53 + ...snps-dw-axi-dmac-constrain-the-items.patch | 67 + ...-dmac-Add-support-for-StarFive-JH711.patch | 128 + ...-dmac-Increase-polling-time-to-DMA-t.patch | 34 + ...dts-starfive-add-dma-controller-node.patch | 45 + ...-Add-TDM-controller-bindings-for-Sta.patch | 123 + ...-ASoC-starfive-Add-JH7110-TDM-driver.patch | 799 ++ ...ve-add-the-node-and-pins-configurati.patch | 105 + ...add-JH7110-PCIe-dt-binding-documents.patch | 186 + ...five-add-StarFive-JH7110-PCIe-driver.patch | 1014 ++ ...ve-add-PCIe-dts-configuration-for-JH.patch | 188 + ...dts-starfive-add-pmu-controller-node.patch | 34 + .../patches/0083-add-missing-include.patch | 24 + ...o-hash-Add-statesize-to-crypto_ahash.patch | 70 + ...he-new-lightspeed-receiver-iteration.patch | 276 + srcpkgs/linux6.3/template | 2 +- 87 files changed, 29023 insertions(+), 1 deletion(-) create mode 100644 srcpkgs/linux6.3/files/riscv-dotconfig create mode 100644 srcpkgs/linux6.3/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-system-clock-a.patch create mode 100644 srcpkgs/linux6.3/patches/0002-dt-bindings-clock-Add-StarFive-JH7110-always-on-cloc.patch create mode 100644 srcpkgs/linux6.3/patches/0003-clk-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch create mode 100644 srcpkgs/linux6.3/patches/0004-clk-starfive-Factor-out-common-JH7100-and-JH7110-cod.patch create mode 100644 srcpkgs/linux6.3/patches/0005-clk-starfive-Rename-clk-starfive-jh7100.h-to-clk-sta.patch create mode 100644 srcpkgs/linux6.3/patches/0006-clk-starfive-Rename-jh7100-to-jh71x0-for-the-common-.patch create mode 100644 srcpkgs/linux6.3/patches/0007-reset-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFI.patch create mode 100644 srcpkgs/linux6.3/patches/0008-reset-Create-subdirectory-for-StarFive-drivers.patch create mode 100644 srcpkgs/linux6.3/patches/0009-reset-starfive-Factor-out-common-JH71X0-reset-code.patch create mode 100644 srcpkgs/linux6.3/patches/0010-reset-starfive-Extract-the-common-JH71X0-reset-code.patch create mode 100644 srcpkgs/linux6.3/patches/0011-reset-starfive-Rename-jh7100-to-jh71x0-for-the-commo.patch create mode 100644 srcpkgs/linux6.3/patches/0012-reset-starfive-jh71x0-Use-32bit-I-O-on-32bit-registe.patch create mode 100644 srcpkgs/linux6.3/patches/0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0014-clk-starfive-Add-StarFive-JH7110-always-on-clock-dri.patch create mode 100644 srcpkgs/linux6.3/patches/0015-reset-starfive-Add-StarFive-JH7110-reset-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0016-dt-bindings-timer-Add-StarFive-JH7110-clint.patch create mode 100644 srcpkgs/linux6.3/patches/0017-dt-bindings-interrupt-controller-Add-StarFive-JH7110.patch create mode 100644 srcpkgs/linux6.3/patches/0018-dt-bindings-riscv-Add-SiFive-S7-compatible.patch create mode 100644 srcpkgs/linux6.3/patches/0019-riscv-dts-starfive-Add-initial-StarFive-JH7110-devic.patch create mode 100644 srcpkgs/linux6.3/patches/0020-riscv-dts-starfive-Add-StarFive-JH7110-pin-function-.patch create mode 100644 srcpkgs/linux6.3/patches/0021-riscv-dts-starfive-Add-StarFive-JH7110-VisionFive-2-.patch create mode 100644 srcpkgs/linux6.3/patches/0022-riscv-dts-starfive-jh7110-Correct-the-properties-of-.patch create mode 100644 srcpkgs/linux6.3/patches/0023-dt-bindings-watchdog-Add-watchdog-for-StarFive-JH710.patch create mode 100644 srcpkgs/linux6.3/patches/0024-drivers-watchdog-Add-StarFive-Watchdog-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0025-riscv-dts-starfive-jh7100-Add-watchdog-node.patch create mode 100644 srcpkgs/linux6.3/patches/0026-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.3/patches/0027-clocksource-Add-StarFive-timer-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0028-riscv-dts-jh7110-starfive-Add-timer-node.patch create mode 100644 srcpkgs/linux6.3/patches/0029-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch create mode 100644 srcpkgs/linux6.3/patches/0030-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch create mode 100644 srcpkgs/linux6.3/patches/0031-dt-bindings-qspi-cdns-qspi-nor-constrain-minItems-ma.patch create mode 100644 srcpkgs/linux6.3/patches/0032-spi-cadence-quadspi-Add-support-for-StarFive-JH7110-.patch create mode 100644 srcpkgs/linux6.3/patches/0033-riscv-dts-starfive-Enable-axp15060-pmic-for-cpufreq.patch create mode 100644 srcpkgs/linux6.3/patches/0034-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch create mode 100644 srcpkgs/linux6.3/patches/0035-riscv-dts-starfive-Add-cpu-scaling-for-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.3/patches/0036-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch create mode 100644 srcpkgs/linux6.3/patches/0037-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch create mode 100644 srcpkgs/linux6.3/patches/0038-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch create mode 100644 srcpkgs/linux6.3/patches/0039-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch create mode 100644 srcpkgs/linux6.3/patches/0040-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch create mode 100644 srcpkgs/linux6.3/patches/0041-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch create mode 100644 srcpkgs/linux6.3/patches/0042-MAINTAINERS-Update-maintainer-of-JH71x0-clock-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0043-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch create mode 100644 srcpkgs/linux6.3/patches/0044-riscv-dts-starfive-jh7110-Add-DVP-and-HDMI-TX-pixel-.patch create mode 100644 srcpkgs/linux6.3/patches/0045-riscv-dts-starfive-jh7110-Add-STGCRG-ISPCRG-VOUTCRG-.patch create mode 100644 srcpkgs/linux6.3/patches/0046-dt-bindings-crypto-Add-StarFive-crypto-module.patch create mode 100644 srcpkgs/linux6.3/patches/0047-crypto-starfive-Add-crypto-engine-support.patch create mode 100644 srcpkgs/linux6.3/patches/0048-riscv-dts-starfive-Add-crypto-and-DMA-node-for-Visio.patch create mode 100644 srcpkgs/linux6.3/patches/0049-crypto-starfive-Add-hash-and-HMAC-support.patch create mode 100644 srcpkgs/linux6.3/patches/0050-dt-bindings-PWM-Add-StarFive-PWM-module.patch create mode 100644 srcpkgs/linux6.3/patches/0051-pwm-starfive-Add-PWM-driver-support.patch create mode 100644 srcpkgs/linux6.3/patches/0052-dt-bindings-net-snps-dwmac-Add-dwmac-5.20-version.patch create mode 100644 srcpkgs/linux6.3/patches/0053-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch create mode 100644 srcpkgs/linux6.3/patches/0054-dt-bindings-net-snps-dwmac-Add-ahb-reset-reset-name.patch create mode 100644 srcpkgs/linux6.3/patches/0055-dt-bindings-net-Add-support-StarFive-dwmac.patch create mode 100644 srcpkgs/linux6.3/patches/0056-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.3/patches/0057-net-stmmac-dwmac-starfive-Add-phy-interface-settings.patch create mode 100644 srcpkgs/linux6.3/patches/0058-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch create mode 100644 srcpkgs/linux6.3/patches/0059-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch create mode 100644 srcpkgs/linux6.3/patches/0060-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0061-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0062-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch create mode 100644 srcpkgs/linux6.3/patches/0063-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0064-riscv-dts-starfive-Add-USB-dts-configuration-for-JH7.patch create mode 100644 srcpkgs/linux6.3/patches/0065-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch create mode 100644 srcpkgs/linux6.3/patches/0066-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0067-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch create mode 100644 srcpkgs/linux6.3/patches/0068-clk-starfive-jh7110-sys-Modify-PLL-clocks-source.patch create mode 100644 srcpkgs/linux6.3/patches/0069-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch create mode 100644 srcpkgs/linux6.3/patches/0070-riscv-dts-starfive-jh7110-Add-syscon-nodes.patch create mode 100644 srcpkgs/linux6.3/patches/0071-riscv-dts-starfive-jh7110-Add-PLL-clock-node-and-mod.patch create mode 100644 srcpkgs/linux6.3/patches/0072-dt-bindings-dma-snps-dw-axi-dmac-constrain-the-items.patch create mode 100644 srcpkgs/linux6.3/patches/0073-dmaengine-dw-axi-dmac-Add-support-for-StarFive-JH711.patch create mode 100644 srcpkgs/linux6.3/patches/0074-dmaengine-dw-axi-dmac-Increase-polling-time-to-DMA-t.patch create mode 100644 srcpkgs/linux6.3/patches/0075-riscv-dts-starfive-add-dma-controller-node.patch create mode 100644 srcpkgs/linux6.3/patches/0076-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch create mode 100644 srcpkgs/linux6.3/patches/0077-ASoC-starfive-Add-JH7110-TDM-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0078-riscv-dts-starfive-add-the-node-and-pins-configurati.patch create mode 100644 srcpkgs/linux6.3/patches/0079-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch create mode 100644 srcpkgs/linux6.3/patches/0080-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch create mode 100644 srcpkgs/linux6.3/patches/0081-riscv-dts-starfive-add-PCIe-dts-configuration-for-JH.patch create mode 100644 srcpkgs/linux6.3/patches/0082-riscv-dts-starfive-add-pmu-controller-node.patch create mode 100644 srcpkgs/linux6.3/patches/0083-add-missing-include.patch create mode 100644 srcpkgs/linux6.3/patches/0084-crypto-hash-Add-statesize-to-crypto_ahash.patch create mode 100644 srcpkgs/linux6.3/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch diff --git a/srcpkgs/linux6.3/files/riscv-dotconfig b/srcpkgs/linux6.3/files/riscv-dotconfig new file mode 100644 index 0000000000000..a8f7c28b86153 --- /dev/null +++ b/srcpkgs/linux6.3/files/riscv-dotconfig @@ -0,0 +1,10595 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 6.3.3 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-linux-musl-gcc (GCC) 12.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=120200 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23900 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23900 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=125 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="_1" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_WATCH_QUEUE=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_SIM=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ_FULL=y +CONFIG_CONTEXT_TRACKING_USER=y +CONFIG_CONTEXT_TRACKING_USER_FORCE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_LSM=y +# end of BPF subsystem + +CONFIG_PREEMPT_VOLUNTARY_BUILD=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +CONFIG_RCU_LAZY=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_MEMCG=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_MM_CID=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_FORCE is not set +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_AS_HAS_INSN=y + +# +# SoC selection +# +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_SIFIVE=y +CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_STARFIVE=y +CONFIG_SOC_STARFIVE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_VIRT=y +CONFIG_SOC_VIRT=y +# end of SoC selection + +# +# CPU errata selection +# +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PMU=y +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_NONPORTABLE is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_SMP=y +CONFIG_NR_CPUS=480 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_RISCV_SBI_V01 is not set +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_KEXEC=y +# CONFIG_KEXEC_FILE is not set +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Boot options + +CONFIG_PORTABLE=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_DPM_WATCHDOG=y +CONFIG_DPM_WATCHDOG_TIMEOUT=60 +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +CONFIG_ENERGY_MODEL=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +# end of CPU Frequency scaling +# end of CPU Power Management + +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_KVM_XFER_TO_GUEST_WORK=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_FUNCTION_ALIGNMENT=0 +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_MQ_RDMA=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB_DEPRECATED is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_DEFERRED_STRUCT_PAGE_INIT=y +CONFIG_PAGE_IDLE_FLAG=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +CONFIG_GET_FREE_REGION=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +# CONFIG_DAMON_LRU_SORT is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XFRM_ESPINTCP=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_BPF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_NETLABEL=y +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +# CONFIG_BPFILTER_UMH is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_NONE=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_DEBUG=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +# end of AX.25 network device drivers + +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_MTK=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_VIRTIO=m +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=y +# CONFIG_RXPERF is not set +CONFIG_AF_KCM=m +CONFIG_STREAM_PARSER=y +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_SPI is not set +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +# end of Near Field Communication (NFC) devices + +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_PCI_FTPCI100=y +CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCIE_RCAR_EP=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_STARFIVE=m + +# +# DesignWare PCI Core Support +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCI_MESON=y +CONFIG_PCIE_FU740=y +# end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +CONFIG_PCIE_CADENCE=y +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_EP=y +CONFIG_PCIE_CADENCE_PLAT=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +# end of Cadence PCIe controllers support +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m +CONFIG_PCI_EPF_VNTB=m +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +CONFIG_CXL_BUS=m +CONFIG_CXL_PCI=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PMEM=m +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m + +# +# RapidIO Switch drivers +# +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_UPLOAD=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_ARCH_NUMA=y +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MOXTET=m +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUNXI_RSB=m +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_FW_CS_DSP=m +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +# CONFIG_SM_FTL is not set +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PSTORE is not set +CONFIG_MTD_SWAP=m +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +CONFIG_MTD_MAP_BANK_WIDTH_16=y +CONFIG_MTD_MAP_BANK_WIDTH_32=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m + +# +# Raw/parallel NAND flash controllers +# +CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_SUNXI=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m +CONFIG_MTD_NAND_RENESAS=m + +# +# Misc +# +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y +CONFIG_MTD_SPI_NAND=m + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_MXIC=y +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_NUMA=y +CONFIG_OF_DMA_DEFAULT_COHERENT=y +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +# CONFIG_NVME_AUTH is not set +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_AUTH is not set +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_XILINX_SDFEC=m +CONFIG_MISC_RTSX=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_C2PORT=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_SPI=y +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_ECHO=m +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_GP_PCI1XXXX=m +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_AHCI_CEVA=m +CONFIG_AHCI_SUNXI=m +CONFIG_AHCI_QORIQ=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_RCAR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +# CONFIG_PATA_OF_PLATFORM is not set +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_DM_AUDIT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RIONET_RX_SIZE=128 +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_SUNGEM_PHY=m +# CONFIG_ARCNET is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI_TUNE_BURST=y +CONFIG_ATM_ENI_BURST_TX_16W=y +CONFIG_ATM_ENI_BURST_TX_8W=y +CONFIG_ATM_ENI_BURST_TX_4W=y +CONFIG_ATM_ENI_BURST_TX_2W=y +CONFIG_ATM_ENI_BURST_RX_16W=y +CONFIG_ATM_ENI_BURST_RX_8W=y +CONFIG_ATM_ENI_BURST_RX_4W=y +CONFIG_ATM_ENI_BURST_RX_2W=y +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_NICSTAR_USE_SUNI=y +CONFIG_ATM_NICSTAR_USE_IDT77105=y +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +# CONFIG_CAIF_DRIVERS is not set + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m +CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_SLICOSS=m +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_SUN4I_EMAC=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AX88796C_COMPRESSION is not set +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACB_PCI=m +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_CAVIUM_PTP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +CONFIG_NET_VENDOR_CORTINA=y +CONFIG_GEMINI_ETHERNET=m +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +CONFIG_TULIP_NAPI=y +CONFIG_TULIP_NAPI_HW_MITIGATION=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGB=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_LIBWX=m +CONFIG_NGBE=m +# CONFIG_TXGBE is not set +CONFIG_JME=m +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +# CONFIG_OCTEON_EP is not set +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_EN_MACSEC is not set +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXFW=m +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_VCAP=y +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NI=y +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_NET_IPSEC=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_IONIC=m +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_LL2=y +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +CONFIG_QED_RDMA=y +CONFIG_QED_ISCSI=y +CONFIG_QED_FCOE=y +CONFIG_QED_OOO=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_QCA7000=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_SH_ETH=m +CONFIG_RAVB=m +CONFIG_RENESAS_ETHER_SWITCH=m +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_SXGBE_ETH=m +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_LOONGSON=m +CONFIG_STMMAC_PCI=m +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_MSE102X=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIN1100_PHY is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_NCN26000_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TD510_PHY is not set +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_FLEXCAN=m +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_C_CAN=m +# CONFIG_CAN_C_CAN_PLATFORM is not set +CONFIG_CAN_C_CAN_PCI=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_USB is not set +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set + +# +# MCTP Device Drivers +# +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# end of MCTP Device Drivers + +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_SUN4I=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +CONFIG_PCS_LYNX=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ADM8211=m +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +# CONFIG_WIL6210_DEBUGFS is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K_DEBUGFS=y +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATH12K=m +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K_TRACING=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +CONFIG_LIBIPW_DEBUG=y +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# CONFIG_IWLEGACY_DEBUGFS is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615_COMMON=m +CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921_COMMON=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7996E=m +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_USB=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CU=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW89=m +CONFIG_RTW89_CORE=m +CONFIG_RTW89_PCI=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852CE=m +# CONFIG_RTW89_DEBUGMSG is not set +# CONFIG_RTW89_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WFX=m +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +# CONFIG_CW1200_WLAN_SPI is not set +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +# CONFIG_WL1251_SPI is not set +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=y +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +# CONFIG_IOSM is not set +CONFIG_MTK_T7XX=m +# end of Wireless WAN + +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +# CONFIG_KEYBOARD_SAMSUNG is not set +CONFIG_KEYBOARD_GOLDFISH_EVENTS=y +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_SUN4I_LRADC=m +CONFIG_KEYBOARD_IQS62X=m +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_KEYBOARD_BCM is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUN4I=m +CONFIG_TOUCHSCREEN_SUR40=m +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +# CONFIG_INPUT_AD714X_SPI is not set +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MMA8450=m +# CONFIG_INPUT_GPIO_BEEPER is not set +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +# CONFIG_INPUT_IQS7222 is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_AMBAKMI=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_SUN4I_PS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_EM=m +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=m +CONFIG_SERIAL_AMBA_PL011=m +CONFIG_SERIAL_EARLYCON_SEMIHOST=y +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_SH_SCI=m +CONFIG_SERIAL_SH_SCI_NR_UARTS=18 +CONFIG_SERIAL_SH_SCI_DMA=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SC16IS7XX_CORE=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=y +CONFIG_SERIAL_SC16IS7XX_SPI=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_SPRD=y +CONFIG_SERIAL_SPRD_CONSOLE=y +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=y +CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_HVC_DRIVER=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_PANIC_EVENT=y +# CONFIG_IPMI_PANIC_STRING is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_POLARFIRE_SOC=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM_JH7110=m +CONFIG_APPLICOM=m + +# +# PCMCIA character devices +# +CONFIG_SYNCLINK_CS=m +CONFIG_CARDMAN_4000=m +CONFIG_CARDMAN_4040=m +CONFIG_SCR24X=m +CONFIG_IPWIRELESS=m +# end of PCMCIA character devices + +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_I2C_MV64XXX=m +CONFIG_I2C_NOMADIK=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RIIC=m +CONFIG_I2C_RK3X=m +CONFIG_I2C_RZV2M=m +CONFIG_I2C_SH_MOBILE=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_XILINX=m +CONFIG_I2C_RCAR=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_VIRTIO=m +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_SLAVE_TESTUNIT=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_NXP_FLEXSPI=m +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PL022=m +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_ROCKCHIP=m +CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SH_MSIOF=m +CONFIG_SPI_SH_HSPI=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_SUN4I=m +CONFIG_SPI_SUN6I=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y + +# +# HSI controllers +# + +# +# HSI clients +# +CONFIG_HSI_CHAR=m +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CY8C95X0=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_CS47L15=y +CONFIG_PINCTRL_CS47L35=y +CONFIG_PINCTRL_CS47L85=y +CONFIG_PINCTRL_CS47L90=y +CONFIG_PINCTRL_CS47L92=y + +# +# Renesas pinctrl drivers +# +CONFIG_PINCTRL_RENESAS=y +CONFIG_PINCTRL_RZG2L=y +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=m +CONFIG_PINCTRL_SUNXI=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN5I=y +CONFIG_PINCTRL_SUN6I_A31=y +CONFIG_PINCTRL_SUN6I_A31_R=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN8I_V3S=y +# CONFIG_PINCTRL_SUN9I_A80 is not set +CONFIG_PINCTRL_SUN9I_A80_R=y +CONFIG_PINCTRL_SUN20I_D1=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_A100=y +CONFIG_PINCTRL_SUN50I_A100_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_IDIO_16=m + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_74XX_MMIO=m +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +# CONFIG_GPIO_EXAR is not set +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_PL061=m +CONFIG_GPIO_RCAR=m +# CONFIG_GPIO_SIFIVE is not set +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_XILINX=m +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_TQMX86=m +# CONFIG_GPIO_WM8994 is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +CONFIG_GPIO_MAX3191X=m +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_MOCKUP=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +# end of Virtual GPIO drivers + +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# end of 1-wire Slaves + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_IP5XXX_POWER=m +# CONFIG_TEST_POWER is not set +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_CPCAP=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_QCOM_BATTMGR=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_BQ27XXX_HDQ=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_GPIO=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_BQ2415X is not set +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_BATTERY_UG3105=m +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_SMPRO=m +# CONFIG_SENSORS_AD7314 is not set +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_ADT7310 is not set +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_MAX1111 is not set +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +# CONFIG_SENSORS_MAX197 is not set +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +# CONFIG_SENSORS_MENF21BMC_HWMON is not set +CONFIG_SENSORS_MR75203=m +# CONFIG_SENSORS_ADCXX is not set +CONFIG_SENSORS_LM63=m +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +# CONFIG_SENSORS_NTC_THERMISTOR is not set +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775_I2C is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_OCC_P8_I2C=m +CONFIG_SENSORS_OCC=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_SENSORS_PECI=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +# CONFIG_SENSORS_IR38064_REGULATOR is not set +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +# CONFIG_SENSORS_XDPE152 is not set +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SFCTEMP=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +# CONFIG_SENSORS_ADS7871 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_IDLE_THERMAL is not set +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=m +CONFIG_MAX77620_THERMAL=m +CONFIG_SUN8I_THERMAL=m +CONFIG_RCAR_THERMAL=m +CONFIG_RCAR_GEN3_THERMAL=m +CONFIG_RZG2L_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_MENF21BMC_WATCHDOG is not set +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +CONFIG_SUNXI_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m +CONFIG_RENESAS_WDT=m +CONFIG_RENESAS_RZAWDT=m +CONFIG_RENESAS_RZN1WDT=m +CONFIG_RENESAS_RZG2LWDT=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_STARFIVE_WATCHDOG=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +CONFIG_MFD_SUN4I_GPADC=m +# CONFIG_MFD_AS3711 is not set +CONFIG_MFD_SMPRO=m +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +CONFIG_MFD_ATMEL_HLCDC=m +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AC100=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_MFD_IQS62X=m +# CONFIG_MFD_JANZ_CMODIO is not set +CONFIG_MFD_KEMPLD=m +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m +# CONFIG_MFD_MT6397 is not set +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_OCELOT=m +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +CONFIG_MFD_SY7636A=m +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=m +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SM501 is not set +CONFIG_MFD_SKY81452=m +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SUN6I_PRCM is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +# CONFIG_MFD_LP8788 is not set +CONFIG_MFD_TI_LMU=m +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +# CONFIG_MFD_TPS65218 is not set +CONFIG_MFD_TPS65219=m +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_LM3533=m +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +# CONFIG_RAVE_SP_CORE is not set +CONFIG_MFD_INTEL_M10_BMC_CORE=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_88PG86X=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA9121=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +# CONFIG_REGULATOR_ISL6271A is not set +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +CONFIG_REGULATOR_LP873X=m +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set +CONFIG_REGULATOR_MAX20411=m +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_ROHM=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65219=m +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_SUNXI=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y + +# +# CEC support +# +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +# end of CEC support + +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=m +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_H264=m +CONFIG_V4L2_VP9=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +CONFIG_VIDEOBUF_VMALLOC=m +# end of Video4Linux options + +# +# Media controller options +# +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y + +# +# Analog TV USB devices +# +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_ZORAN is not set + +# +# Media capture/analog TV support +# +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +# CONFIG_I2C_SI470X is not set +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +CONFIG_VIDEO_CAFE_CCIC=m + +# +# Mediatek media platform drivers +# + +# +# Microchip Technology, Inc. media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# +CONFIG_VIDEO_RCAR_ISP=m +CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_RZG2L_CSI2=m +CONFIG_VIDEO_RZG2L_CRU=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_FDP1=m +CONFIG_VIDEO_RENESAS_JPU=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_RCAR_DRIF=m + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# + +# +# Sunxi media platform drivers +# +CONFIG_VIDEO_SUN4I_CSI=m +CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_SUN6I_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_DEINTERLACE=m +CONFIG_VIDEO_SUN8I_ROTATE=m + +# +# Texas Instruments drivers +# + +# +# Verisilicon media platform drivers +# +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_SUNXI=y + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_VIDEO_XILINX_VTC=m + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VISL=m +# CONFIG_VISL_DEBUGFS is not set +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m +CONFIG_UVC_COMMON=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=m + +# +# Camera sensor devices +# +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M032=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T001=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_NOON010PC30=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_S5K6AA=m +CONFIG_VIDEO_SR030PC30=m +CONFIG_VIDEO_ST_VGXY61=m +CONFIG_VIDEO_VS6624=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_M5MOLS=m +# end of Camera sensor devices + +# +# Lens drivers +# +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +# end of Flash devices + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +CONFIG_VIDEO_AD9389B=m +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +# end of Video encoders + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +CONFIG_SDR_MAX2175=m +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +# end of Miscellaneous helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_EC100=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_L64781=m +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_STV0297=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_VES1820=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_MN88443X=m +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_DRX39XYJ=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +CONFIG_VIDEO_NOMODESET=y +CONFIG_DRM=m +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_BUDDY=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m +# end of I2C encoder or helper chips + +# +# ARM devices +# +CONFIG_DRM_KOMEDA=m +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +# CONFIG_DRM_AMD_DC_HDCP is not set +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_DRM_NOUVEAU=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_RZG2L_MIPI_DSI=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_SUN6I_DSI=m +CONFIG_DRM_SUN8I_DW_HDMI=m +CONFIG_DRM_SUN8I_MIXER=m +CONFIG_DRM_SUN8I_TCON_TOP=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_EBBG_FT8719=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX8394=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CDNS_DSI_J721E=y +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_DW_HDMI=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +CONFIG_DRM_DW_HDMI_CEC=m +# end of Display Interface Bridges + +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV_THERMAL=y +CONFIG_DRM_LOGICVC=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_SIMPLEDRM=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_I740=m +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SMSCUFX=m +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_GOLDFISH is not set +CONFIG_FB_VIRTUAL=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_DRM_ACCEL=y +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTL_DEBUG is not set +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_PREALLOC_SIZE=1024 +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_IMX_AUDMUX=m +# end of SoC Audio for Freescale CPUs + +CONFIG_SND_I2S_HI6210_I2S=m +# CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_MTK_BTCVSD=m + +# +# SoC Audio support for Renesas SoCs +# +CONFIG_SND_SOC_SH4_FSI=m +CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_RZ=m +# end of SoC Audio support for Renesas SoCs + +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_STARFIVE=m +CONFIG_SND_SOC_JH7110_TDM=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# +# Allwinner SoC Audio support +# +CONFIG_SND_SUN4I_CODEC=m +CONFIG_SND_SUN4I_I2S=m +CONFIG_SND_SUN4I_SPDIF=m +CONFIG_SND_SUN50I_DMIC=m +# end of Allwinner SoC Audio support + +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m +# CONFIG_SND_SOC_AW88395 is not set +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +# CONFIG_SND_SOC_INNO_RK3036 is not set +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PEB2466=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8315=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_VIRTIO=m +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_STEAM_FF=y +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +# end of Special HID drivers + +# +# HID-BPF support +# +# end of HID-BPF support + +# +# USB HID support +# +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +CONFIG_I2C_HID=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_I2C_HID_CORE=m +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XHCI_RCAR=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_U132_HCD=m +CONFIG_USB_SL811_HCD=m +# CONFIG_USB_SL811_HCD_ISO is not set +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_RENESAS_USBHS_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_RENESAS_USBHS=m + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set + +# +# USB dual-mode controller drivers +# +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DUAL_ROLE is not set + +# +# Platform Glue Layer +# +CONFIG_USB_MUSB_SUNXI=m +CONFIG_USB_MUSB_POLARFIRE_SOC=m + +# +# MUSB DMA mode +# +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC2=m +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=m +# CONFIG_USB_CHIPIDEA_UDC is not set +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_IMX=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_TEGRA=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_DUAL_ROLE is not set + +# +# USB port drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +# CONFIG_USB_CHAOSKEY is not set +CONFIG_USB_ONBOARD_HUB=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_USB_ISP1301=m +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_U_SERIAL_CONSOLE=y + +# +# USB Peripheral Controller +# +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RENESAS_USB3=m +CONFIG_USB_RENESAS_USBF=m +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SNP_UDC_PLAT=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=m +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_TCM=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_PI3USB30532=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_CRYPTO=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_ARMMMCI=m +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +# CONFIG_MMC_SDHCI_MILBEAUT is not set +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_TMIO_CORE=m +CONFIG_MMC_SDHI=m +CONFIG_MMC_SDHI_SYS_DMAC=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_SH_MMCIF=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_SUNXI=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_AM654=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_RENESAS=m +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y + +# +# LED drivers +# +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_TCA6507=m +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m + +# +# RGB LED drivers +# +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m + +# +# Simple LED drivers +# +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_SIFIVE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_AC100=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_SD3078=m + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +CONFIG_RTC_DRV_MAX6916=m +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_PCF2127=m +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_RTC_DRV_NTXEC=m + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SH=m +CONFIG_RTC_DRV_PL030=m +CONFIG_RTC_DRV_PL031=m +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_POLARFIRE_SOC=m +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_AMBA_PL08X=y +CONFIG_DMA_SUN6I=m +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +CONFIG_PLX_DMA=m +CONFIG_XILINX_XDMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +# CONFIG_SF_PDMA is not set +CONFIG_RENESAS_DMA=y +CONFIG_RCAR_DMAC=m +CONFIG_RENESAS_USB_DMAC=m +CONFIG_RZ_DMAC=m + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_LINEDISP=m +CONFIG_HD44780_COMMON=m +CONFIG_HD44780=m +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PARPORT_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +CONFIG_PANEL=m +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_VIRQFD=y +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_VP_VDPA=m +CONFIG_SNET_VDPA=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_COMEDI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +# CONFIG_COMEDI_MISC_DRIVERS is not set +# CONFIG_COMEDI_ISA_DRIVERS is not set +# CONFIG_COMEDI_PCI_DRIVERS is not set +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_ROUTING=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Active energy metering IC +# +# CONFIG_ADE7854 is not set +# end of Active energy metering IC + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +CONFIG_FB_SM750=m +CONFIG_USB_EMXX=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_SP8870=m +CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=m +CONFIG_VIDEO_SUN6I_ISP=m +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STAGING_BOARD is not set +CONFIG_LTE_GDM724X=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +# CONFIG_VME_BUS is not set +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIPE=m +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SI5341=m +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_VC7=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_MCHP_CLK_MPFS=y +CONFIG_CLK_RENESAS=y +CONFIG_CLK_R9A07G043=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RZG2L=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_SUNXI_CCU=m +CONFIG_SUN20I_D1_CCU=m +CONFIG_SUN20I_D1_R_CCU=m +CONFIG_SUN6I_RTC_CCU=m +CONFIG_SUN8I_DE2_CCU=m +CONFIG_XILINX_VCU=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SUN6I=m + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_SUN4I_TIMER=y +CONFIG_RENESAS_OSTM=y +CONFIG_RISCV_TIMER=y +CONFIG_STARFIVE_TIMER=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=m +CONFIG_ARM_MHU_V2=m +CONFIG_PLATFORM_MHU=m +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_POLARFIRE_SOC_MAILBOX=m +CONFIG_SUN6I_MSGBOX=m +CONFIG_IOMMU_IOVA=m +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_OF_IOMMU=y +CONFIG_IOMMUFD=m +CONFIG_SUN50I_IOMMU=y +# CONFIG_IPMMU_VMSA is not set + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_RCAR_REMOTEPROC=m +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_QCOM=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +CONFIG_POLARFIRE_SOC_SYS_CTRL=m +CONFIG_WPCM450_SOC=m + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_PDR_HELPERS=m +CONFIG_QCOM_PMIC_GLINK=m +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +CONFIG_SOC_RENESAS=y +CONFIG_ARCH_RZG2L=y +CONFIG_ARCH_R9A07G043=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_JH71XX_PMU=y +CONFIG_SUNXI_SRAM=y +CONFIG_SUN20I_PPU=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_PTN5150=m +# CONFIG_EXTCON_RT8973A is not set +CONFIG_EXTCON_SM5502=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_ARM_PL172_MPMC=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_RENESAS_RPCIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_KX022A=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_KX022A_I2C=m +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +CONFIG_MC3230=m +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +CONFIG_MMA9551_CORE=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MSA311=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +# end of Accelerometers + +# +# Analog to digital converters +# +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AD4130=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +# CONFIG_CC10001_ADC is not set +CONFIG_CPCAP_ADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +# CONFIG_MAX1027 is not set +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +# CONFIG_MAX1363 is not set +CONFIG_MAX9611=m +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +CONFIG_MCP3911=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MP2629_ADC=m +# CONFIG_NAU7802 is not set +CONFIG_QCOM_VADC_COMMON=m +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RICHTEK_RTQ6056=m +CONFIG_RZG2L_ADC=m +CONFIG_SD_ADC_MODULATOR=m +CONFIG_SUN4I_GPADC=m +# CONFIG_TI_ADC081C is not set +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +# CONFIG_TI_ADC128S052 is not set +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +# CONFIG_TI_AM335X_ADC is not set +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_XILINX_XADC=m +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +CONFIG_AD74115=m +CONFIG_AD74413R=m +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +CONFIG_IIO_RESCALE=m +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +CONFIG_ADA4250=m +CONFIG_HMC425=m +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +CONFIG_IIO_MS_SENSORS_I2C=m + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +CONFIG_AD3552R=m +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +CONFIG_AD5592R_BASE=m +CONFIG_AD5592R=m +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +CONFIG_LTC2688=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +# CONFIG_AD5755 is not set +CONFIG_AD5758=m +CONFIG_AD5761=m +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +CONFIG_AD7293=m +# CONFIG_AD7303 is not set +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +# CONFIG_MAX517 is not set +CONFIG_MAX5522=m +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Filters +# +CONFIG_ADMV8818=m +# end of Filters + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +# CONFIG_ADRF6780 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +CONFIG_AM2315=m +# CONFIG_DHT11 is not set +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +# end of Inertial measurement units + +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=m +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9960=m +CONFIG_AS73211=m +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +CONFIG_IQS621_ALS=m +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_RPR0521=m +# CONFIG_SENSORS_LM3533 is not set +# CONFIG_LTR501 is not set +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +# CONFIG_STK3310 is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +CONFIG_TSL2591=m +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_US5182D=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +# CONFIG_VEML6070 is not set +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +# end of Light sensors + +# +# Magnetometer sensors +# +CONFIG_AK8974=m +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_RM3100=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_TI_TMAG5273=m +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +CONFIG_IIO_MUX=m +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +CONFIG_IIO_HRTIMER_TRIGGER=m +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +CONFIG_IQS624_POS=m +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +CONFIG_AD5110=m +CONFIG_AD5272=m +# CONFIG_DS1803 is not set +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +# CONFIG_MCP4131 is not set +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +# end of Digital potentiometers + +# +# Digital potentiostats +# +CONFIG_LMP91000=m +# end of Digital potentiostats + +# +# Pressure sensors +# +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +CONFIG_ICP10100=m +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX_COMMON=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +CONFIG_MLX90632=m +# CONFIG_TMP006 is not set +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX30208=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +# end of Temperature sensors + +CONFIG_NTB=y +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +# CONFIG_NTB_PINGPONG is not set +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +# CONFIG_NTB_MSI_TEST is not set +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_RCAR=m +CONFIG_PWM_RENESAS_TPU=m +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_STARFIVE_PTC=m +CONFIG_PWM_SUN4I=m +CONFIG_PWM_XILINX=m + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_AL_FIC=y +CONFIG_MADERA_IRQ=m +CONFIG_RENESAS_RZG2L_IRQC=y +# CONFIG_XILINX_INTC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_POLARFIRE_SOC=y +CONFIG_RESET_RZG2L_USBPHY_CTRL=m +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_SUN4I_USB=m +CONFIG_PHY_SUN6I_MIPI_DPHY=m +CONFIG_PHY_SUN9I_USB=m +CONFIG_PHY_SUN50I_USB3=m + +# +# PHY drivers for Broadcom platforms +# +CONFIG_BCM_KONA_USB2_PHY=m +# end of PHY drivers for Broadcom platforms + +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_LAN966X_SERDES=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_R8A779F0_ETHERNET_SERDES=m +CONFIG_PHY_RCAR_GEN2=m +CONFIG_PHY_RCAR_GEN3_PCIE=m +CONFIG_PHY_RCAR_GEN3_USB2=m +CONFIG_PHY_RCAR_GEN3_USB3=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +CONFIG_RAS=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set + +# +# Android +# +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +CONFIG_LIBNVDIMM=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +CONFIG_OF_PMEM=m +CONFIG_NVDIMM_KEYS=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_SUNXI_SID=m +CONFIG_NVMEM_U_BOOT_ENV=m + +# +# HW tracing support +# +CONFIG_STM=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +# CONFIG_STM_DUMMY is not set +CONFIG_STM_SOURCE_CONSOLE=y +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STM_SOURCE_FTRACE=m +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +CONFIG_PECI=m +CONFIG_PECI_CPU=m +CONFIG_HTE=y +# end of Device Drivers + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +CONFIG_QNX6FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_ROMFS_FS=m +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_ZSTD_COMPRESS=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_ZONE=m +CONFIG_PSTORE_BLK=m +CONFIG_PSTORE_BLK_BLKDEV="" +CONFIG_PSTORE_BLK_KMSG_SIZE=64 +CONFIG_PSTORE_BLK_MAX_REASON=2 +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EROFS_FS=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_PCPU_KTHREAD=y +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_CRYPTOSYSTEM=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS_COMMON=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +# CONFIG_DLM_DEPRECATED_API is not set +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=y +# end of Compression + +# +# Random number generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_CRYPTO_DEV_SUN4I_SS=m +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=m +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS=m +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +CONFIG_PACKING=y +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=y +CONFIG_CRC4=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=y +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=y +CONFIG_842_DECOMPRESS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_BCH=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_INTERVAL_TREE_SPAN_ITER=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CHECK_SIGNATURE=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +CONFIG_FONT_TER16x32=y +# CONFIG_FONT_6x8 is not set +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_MEMREGION=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +CONFIG_PARMAN=m +CONFIG_OBJAGG=m +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m +CONFIG_POLYNOMIAL=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_NONE is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_BTF=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_PAGE_OWNER=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_TORTURE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +# CONFIG_DEBUG_CGROUP_REF is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_RETHOOK=y +CONFIG_RETHOOK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FPROBE=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_OSNOISE_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y +CONFIG_SYNTH_EVENTS=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set +# CONFIG_SAMPLES is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# riscv Debugging +# +# end of riscv Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_TEST_DHRY is not set +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ASYNC_RAID6_TEST=m +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/srcpkgs/linux6.3/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-system-clock-a.patch b/srcpkgs/linux6.3/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-system-clock-a.patch new file mode 100644 index 0000000000000..a685f84bf0561 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-system-clock-a.patch @@ -0,0 +1,532 @@ +From d0e45d2b51a12cd14cbf401bab474162e2220f2b Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:13 +0800 +Subject: [PATCH 01/84] dt-bindings: clock: Add StarFive JH7110 system clock + and reset generator + +Add bindings for the system clock and reset generator (SYSCRG) on the +JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Conor Dooley +Reviewed-by: Rob Herring +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../clock/starfive,jh7110-syscrg.yaml | 104 +++++++++ + MAINTAINERS | 16 +- + .../dt-bindings/clock/starfive,jh7110-crg.h | 203 ++++++++++++++++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++ + 4 files changed, 458 insertions(+), 7 deletions(-) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml + create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h + create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +new file mode 100644 +index 000000000000..84373ae31644 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +@@ -0,0 +1,104 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 System Clock and Reset Generator ++ ++maintainers: ++ - Emil Renner Berthing ++ ++properties: ++ compatible: ++ const: starfive,jh7110-syscrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ oneOf: ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC1 RMII reference or GMAC1 RGMII RX ++ - description: External I2S TX bit clock ++ - description: External I2S TX left/right channel clock ++ - description: External I2S RX bit clock ++ - description: External I2S RX left/right channel clock ++ - description: External TDM clock ++ - description: External audio master clock ++ ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC1 RMII reference ++ - description: GMAC1 RGMII RX ++ - description: External I2S TX bit clock ++ - description: External I2S TX left/right channel clock ++ - description: External I2S RX bit clock ++ - description: External I2S RX left/right channel clock ++ - description: External TDM clock ++ - description: External audio master clock ++ ++ clock-names: ++ oneOf: ++ - items: ++ - const: osc ++ - enum: ++ - gmac1_rmii_refin ++ - gmac1_rgmii_rxin ++ - const: i2stx_bclk_ext ++ - const: i2stx_lrck_ext ++ - const: i2srx_bclk_ext ++ - const: i2srx_lrck_ext ++ - const: tdm_ext ++ - const: mclk_ext ++ ++ - items: ++ - const: osc ++ - const: gmac1_rmii_refin ++ - const: gmac1_rgmii_rxin ++ - const: i2stx_bclk_ext ++ - const: i2stx_lrck_ext ++ - const: i2srx_bclk_ext ++ - const: i2srx_lrck_ext ++ - const: tdm_ext ++ - const: mclk_ext ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - '#clock-cells' ++ - '#reset-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ clock-controller@13020000 { ++ compatible = "starfive,jh7110-syscrg"; ++ reg = <0x13020000 0x10000>; ++ clocks = <&osc>, <&gmac1_rmii_refin>, ++ <&gmac1_rgmii_rxin>, ++ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, ++ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, ++ <&tdm_ext>, <&mclk_ext>; ++ clock-names = "osc", "gmac1_rmii_refin", ++ "gmac1_rgmii_rxin", ++ "i2stx_bclk_ext", "i2stx_lrck_ext", ++ "i2srx_bclk_ext", "i2srx_lrck_ext", ++ "tdm_ext", "mclk_ext"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +diff --git a/MAINTAINERS b/MAINTAINERS +index c6545eb54104..ac1bd1c3b0d7 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19903,12 +19903,13 @@ M: Emil Renner Berthing + S: Maintained + F: arch/riscv/boot/dts/starfive/ + +-STARFIVE JH7100 CLOCK DRIVERS ++STARFIVE JH71X0 CLOCK DRIVERS + M: Emil Renner Berthing ++M: Hal Feng + S: Maintained +-F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml +-F: drivers/clk/starfive/clk-starfive-jh7100* +-F: include/dt-bindings/clock/starfive-jh7100*.h ++F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml ++F: drivers/clk/starfive/clk-starfive-jh71* ++F: include/dt-bindings/clock/starfive?jh71*.h + + STARFIVE JH7110 MMC/SD/SDIO DRIVER + M: William Qiu +@@ -19926,12 +19927,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* + F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h + F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h + +-STARFIVE JH7100 RESET CONTROLLER DRIVER ++STARFIVE JH71X0 RESET CONTROLLER DRIVER + M: Emil Renner Berthing ++M: Hal Feng + S: Maintained + F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml +-F: drivers/reset/reset-starfive-jh7100.c +-F: include/dt-bindings/reset/starfive-jh7100.h ++F: drivers/reset/starfive/reset-starfive-jh71* ++F: include/dt-bindings/reset/starfive?jh71*.h + + STARFIVE JH71XX PMU CONTROLLER DRIVER + M: Walker Chen +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +new file mode 100644 +index 000000000000..fdd1852e34cc +--- /dev/null ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -0,0 +1,203 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * Copyright 2022 Emil Renner Berthing ++ */ ++ ++#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ ++#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ ++ ++/* SYSCRG clocks */ ++#define JH7110_SYSCLK_CPU_ROOT 0 ++#define JH7110_SYSCLK_CPU_CORE 1 ++#define JH7110_SYSCLK_CPU_BUS 2 ++#define JH7110_SYSCLK_GPU_ROOT 3 ++#define JH7110_SYSCLK_PERH_ROOT 4 ++#define JH7110_SYSCLK_BUS_ROOT 5 ++#define JH7110_SYSCLK_NOCSTG_BUS 6 ++#define JH7110_SYSCLK_AXI_CFG0 7 ++#define JH7110_SYSCLK_STG_AXIAHB 8 ++#define JH7110_SYSCLK_AHB0 9 ++#define JH7110_SYSCLK_AHB1 10 ++#define JH7110_SYSCLK_APB_BUS 11 ++#define JH7110_SYSCLK_APB0 12 ++#define JH7110_SYSCLK_PLL0_DIV2 13 ++#define JH7110_SYSCLK_PLL1_DIV2 14 ++#define JH7110_SYSCLK_PLL2_DIV2 15 ++#define JH7110_SYSCLK_AUDIO_ROOT 16 ++#define JH7110_SYSCLK_MCLK_INNER 17 ++#define JH7110_SYSCLK_MCLK 18 ++#define JH7110_SYSCLK_MCLK_OUT 19 ++#define JH7110_SYSCLK_ISP_2X 20 ++#define JH7110_SYSCLK_ISP_AXI 21 ++#define JH7110_SYSCLK_GCLK0 22 ++#define JH7110_SYSCLK_GCLK1 23 ++#define JH7110_SYSCLK_GCLK2 24 ++#define JH7110_SYSCLK_CORE 25 ++#define JH7110_SYSCLK_CORE1 26 ++#define JH7110_SYSCLK_CORE2 27 ++#define JH7110_SYSCLK_CORE3 28 ++#define JH7110_SYSCLK_CORE4 29 ++#define JH7110_SYSCLK_DEBUG 30 ++#define JH7110_SYSCLK_RTC_TOGGLE 31 ++#define JH7110_SYSCLK_TRACE0 32 ++#define JH7110_SYSCLK_TRACE1 33 ++#define JH7110_SYSCLK_TRACE2 34 ++#define JH7110_SYSCLK_TRACE3 35 ++#define JH7110_SYSCLK_TRACE4 36 ++#define JH7110_SYSCLK_TRACE_COM 37 ++#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 ++#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 ++#define JH7110_SYSCLK_OSC_DIV2 40 ++#define JH7110_SYSCLK_PLL1_DIV4 41 ++#define JH7110_SYSCLK_PLL1_DIV8 42 ++#define JH7110_SYSCLK_DDR_BUS 43 ++#define JH7110_SYSCLK_DDR_AXI 44 ++#define JH7110_SYSCLK_GPU_CORE 45 ++#define JH7110_SYSCLK_GPU_CORE_CLK 46 ++#define JH7110_SYSCLK_GPU_SYS_CLK 47 ++#define JH7110_SYSCLK_GPU_APB 48 ++#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 ++#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 ++#define JH7110_SYSCLK_ISP_TOP_CORE 51 ++#define JH7110_SYSCLK_ISP_TOP_AXI 52 ++#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 ++#define JH7110_SYSCLK_HIFI4_CORE 54 ++#define JH7110_SYSCLK_HIFI4_AXI 55 ++#define JH7110_SYSCLK_AXI_CFG1_MAIN 56 ++#define JH7110_SYSCLK_AXI_CFG1_AHB 57 ++#define JH7110_SYSCLK_VOUT_SRC 58 ++#define JH7110_SYSCLK_VOUT_AXI 59 ++#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 ++#define JH7110_SYSCLK_VOUT_TOP_AHB 61 ++#define JH7110_SYSCLK_VOUT_TOP_AXI 62 ++#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 ++#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 ++#define JH7110_SYSCLK_JPEGC_AXI 65 ++#define JH7110_SYSCLK_CODAJ12_AXI 66 ++#define JH7110_SYSCLK_CODAJ12_CORE 67 ++#define JH7110_SYSCLK_CODAJ12_APB 68 ++#define JH7110_SYSCLK_VDEC_AXI 69 ++#define JH7110_SYSCLK_WAVE511_AXI 70 ++#define JH7110_SYSCLK_WAVE511_BPU 71 ++#define JH7110_SYSCLK_WAVE511_VCE 72 ++#define JH7110_SYSCLK_WAVE511_APB 73 ++#define JH7110_SYSCLK_VDEC_JPG 74 ++#define JH7110_SYSCLK_VDEC_MAIN 75 ++#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 ++#define JH7110_SYSCLK_VENC_AXI 77 ++#define JH7110_SYSCLK_WAVE420L_AXI 78 ++#define JH7110_SYSCLK_WAVE420L_BPU 79 ++#define JH7110_SYSCLK_WAVE420L_VCE 80 ++#define JH7110_SYSCLK_WAVE420L_APB 81 ++#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 ++#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 ++#define JH7110_SYSCLK_AXI_CFG0_MAIN 84 ++#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 ++#define JH7110_SYSCLK_AXIMEM2_AXI 86 ++#define JH7110_SYSCLK_QSPI_AHB 87 ++#define JH7110_SYSCLK_QSPI_APB 88 ++#define JH7110_SYSCLK_QSPI_REF_SRC 89 ++#define JH7110_SYSCLK_QSPI_REF 90 ++#define JH7110_SYSCLK_SDIO0_AHB 91 ++#define JH7110_SYSCLK_SDIO1_AHB 92 ++#define JH7110_SYSCLK_SDIO0_SDCARD 93 ++#define JH7110_SYSCLK_SDIO1_SDCARD 94 ++#define JH7110_SYSCLK_USB_125M 95 ++#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 ++#define JH7110_SYSCLK_GMAC1_AHB 97 ++#define JH7110_SYSCLK_GMAC1_AXI 98 ++#define JH7110_SYSCLK_GMAC_SRC 99 ++#define JH7110_SYSCLK_GMAC1_GTXCLK 100 ++#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 ++#define JH7110_SYSCLK_GMAC1_PTP 102 ++#define JH7110_SYSCLK_GMAC1_RX 103 ++#define JH7110_SYSCLK_GMAC1_RX_INV 104 ++#define JH7110_SYSCLK_GMAC1_TX 105 ++#define JH7110_SYSCLK_GMAC1_TX_INV 106 ++#define JH7110_SYSCLK_GMAC1_GTXC 107 ++#define JH7110_SYSCLK_GMAC0_GTXCLK 108 ++#define JH7110_SYSCLK_GMAC0_PTP 109 ++#define JH7110_SYSCLK_GMAC_PHY 110 ++#define JH7110_SYSCLK_GMAC0_GTXC 111 ++#define JH7110_SYSCLK_IOMUX_APB 112 ++#define JH7110_SYSCLK_MAILBOX_APB 113 ++#define JH7110_SYSCLK_INT_CTRL_APB 114 ++#define JH7110_SYSCLK_CAN0_APB 115 ++#define JH7110_SYSCLK_CAN0_TIMER 116 ++#define JH7110_SYSCLK_CAN0_CAN 117 ++#define JH7110_SYSCLK_CAN1_APB 118 ++#define JH7110_SYSCLK_CAN1_TIMER 119 ++#define JH7110_SYSCLK_CAN1_CAN 120 ++#define JH7110_SYSCLK_PWM_APB 121 ++#define JH7110_SYSCLK_WDT_APB 122 ++#define JH7110_SYSCLK_WDT_CORE 123 ++#define JH7110_SYSCLK_TIMER_APB 124 ++#define JH7110_SYSCLK_TIMER0 125 ++#define JH7110_SYSCLK_TIMER1 126 ++#define JH7110_SYSCLK_TIMER2 127 ++#define JH7110_SYSCLK_TIMER3 128 ++#define JH7110_SYSCLK_TEMP_APB 129 ++#define JH7110_SYSCLK_TEMP_CORE 130 ++#define JH7110_SYSCLK_SPI0_APB 131 ++#define JH7110_SYSCLK_SPI1_APB 132 ++#define JH7110_SYSCLK_SPI2_APB 133 ++#define JH7110_SYSCLK_SPI3_APB 134 ++#define JH7110_SYSCLK_SPI4_APB 135 ++#define JH7110_SYSCLK_SPI5_APB 136 ++#define JH7110_SYSCLK_SPI6_APB 137 ++#define JH7110_SYSCLK_I2C0_APB 138 ++#define JH7110_SYSCLK_I2C1_APB 139 ++#define JH7110_SYSCLK_I2C2_APB 140 ++#define JH7110_SYSCLK_I2C3_APB 141 ++#define JH7110_SYSCLK_I2C4_APB 142 ++#define JH7110_SYSCLK_I2C5_APB 143 ++#define JH7110_SYSCLK_I2C6_APB 144 ++#define JH7110_SYSCLK_UART0_APB 145 ++#define JH7110_SYSCLK_UART0_CORE 146 ++#define JH7110_SYSCLK_UART1_APB 147 ++#define JH7110_SYSCLK_UART1_CORE 148 ++#define JH7110_SYSCLK_UART2_APB 149 ++#define JH7110_SYSCLK_UART2_CORE 150 ++#define JH7110_SYSCLK_UART3_APB 151 ++#define JH7110_SYSCLK_UART3_CORE 152 ++#define JH7110_SYSCLK_UART4_APB 153 ++#define JH7110_SYSCLK_UART4_CORE 154 ++#define JH7110_SYSCLK_UART5_APB 155 ++#define JH7110_SYSCLK_UART5_CORE 156 ++#define JH7110_SYSCLK_PWMDAC_APB 157 ++#define JH7110_SYSCLK_PWMDAC_CORE 158 ++#define JH7110_SYSCLK_SPDIF_APB 159 ++#define JH7110_SYSCLK_SPDIF_CORE 160 ++#define JH7110_SYSCLK_I2STX0_APB 161 ++#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 ++#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 ++#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 ++#define JH7110_SYSCLK_I2STX0_BCLK 165 ++#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 ++#define JH7110_SYSCLK_I2STX0_LRCK 167 ++#define JH7110_SYSCLK_I2STX1_APB 168 ++#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 ++#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 ++#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 ++#define JH7110_SYSCLK_I2STX1_BCLK 172 ++#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 ++#define JH7110_SYSCLK_I2STX1_LRCK 174 ++#define JH7110_SYSCLK_I2SRX_APB 175 ++#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 ++#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 ++#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 ++#define JH7110_SYSCLK_I2SRX_BCLK 179 ++#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 ++#define JH7110_SYSCLK_I2SRX_LRCK 181 ++#define JH7110_SYSCLK_PDM_DMIC 182 ++#define JH7110_SYSCLK_PDM_APB 183 ++#define JH7110_SYSCLK_TDM_AHB 184 ++#define JH7110_SYSCLK_TDM_APB 185 ++#define JH7110_SYSCLK_TDM_INTERNAL 186 ++#define JH7110_SYSCLK_TDM_TDM 187 ++#define JH7110_SYSCLK_TDM_TDM_INV 188 ++#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 ++ ++#define JH7110_SYSCLK_END 190 ++ ++#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +new file mode 100644 +index 000000000000..b88216a4fe40 +--- /dev/null ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -0,0 +1,142 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * Copyright (C) 2022 Emil Renner Berthing ++ */ ++ ++#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ ++#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ ++ ++/* SYSCRG resets */ ++#define JH7110_SYSRST_JTAG_APB 0 ++#define JH7110_SYSRST_SYSCON_APB 1 ++#define JH7110_SYSRST_IOMUX_APB 2 ++#define JH7110_SYSRST_BUS 3 ++#define JH7110_SYSRST_DEBUG 4 ++#define JH7110_SYSRST_CORE0 5 ++#define JH7110_SYSRST_CORE1 6 ++#define JH7110_SYSRST_CORE2 7 ++#define JH7110_SYSRST_CORE3 8 ++#define JH7110_SYSRST_CORE4 9 ++#define JH7110_SYSRST_CORE0_ST 10 ++#define JH7110_SYSRST_CORE1_ST 11 ++#define JH7110_SYSRST_CORE2_ST 12 ++#define JH7110_SYSRST_CORE3_ST 13 ++#define JH7110_SYSRST_CORE4_ST 14 ++#define JH7110_SYSRST_TRACE0 15 ++#define JH7110_SYSRST_TRACE1 16 ++#define JH7110_SYSRST_TRACE2 17 ++#define JH7110_SYSRST_TRACE3 18 ++#define JH7110_SYSRST_TRACE4 19 ++#define JH7110_SYSRST_TRACE_COM 20 ++#define JH7110_SYSRST_GPU_APB 21 ++#define JH7110_SYSRST_GPU_DOMA 22 ++#define JH7110_SYSRST_NOC_BUS_APB 23 ++#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 ++#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 ++#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 ++#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 ++#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 ++#define JH7110_SYSRST_NOC_BUS_DDRC 29 ++#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 ++#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 ++ ++#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 ++#define JH7110_SYSRST_AXI_CFG1_AHB 33 ++#define JH7110_SYSRST_AXI_CFG1_MAIN 34 ++#define JH7110_SYSRST_AXI_CFG0_MAIN 35 ++#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 ++#define JH7110_SYSRST_AXI_CFG0_HIFI4 37 ++#define JH7110_SYSRST_DDR_AXI 38 ++#define JH7110_SYSRST_DDR_OSC 39 ++#define JH7110_SYSRST_DDR_APB 40 ++#define JH7110_SYSRST_ISP_TOP 41 ++#define JH7110_SYSRST_ISP_TOP_AXI 42 ++#define JH7110_SYSRST_VOUT_TOP_SRC 43 ++#define JH7110_SYSRST_CODAJ12_AXI 44 ++#define JH7110_SYSRST_CODAJ12_CORE 45 ++#define JH7110_SYSRST_CODAJ12_APB 46 ++#define JH7110_SYSRST_WAVE511_AXI 47 ++#define JH7110_SYSRST_WAVE511_BPU 48 ++#define JH7110_SYSRST_WAVE511_VCE 49 ++#define JH7110_SYSRST_WAVE511_APB 50 ++#define JH7110_SYSRST_VDEC_JPG 51 ++#define JH7110_SYSRST_VDEC_MAIN 52 ++#define JH7110_SYSRST_AXIMEM0_AXI 53 ++#define JH7110_SYSRST_WAVE420L_AXI 54 ++#define JH7110_SYSRST_WAVE420L_BPU 55 ++#define JH7110_SYSRST_WAVE420L_VCE 56 ++#define JH7110_SYSRST_WAVE420L_APB 57 ++#define JH7110_SYSRST_AXIMEM1_AXI 58 ++#define JH7110_SYSRST_AXIMEM2_AXI 59 ++#define JH7110_SYSRST_INTMEM 60 ++#define JH7110_SYSRST_QSPI_AHB 61 ++#define JH7110_SYSRST_QSPI_APB 62 ++#define JH7110_SYSRST_QSPI_REF 63 ++ ++#define JH7110_SYSRST_SDIO0_AHB 64 ++#define JH7110_SYSRST_SDIO1_AHB 65 ++#define JH7110_SYSRST_GMAC1_AXI 66 ++#define JH7110_SYSRST_GMAC1_AHB 67 ++#define JH7110_SYSRST_MAILBOX_APB 68 ++#define JH7110_SYSRST_SPI0_APB 69 ++#define JH7110_SYSRST_SPI1_APB 70 ++#define JH7110_SYSRST_SPI2_APB 71 ++#define JH7110_SYSRST_SPI3_APB 72 ++#define JH7110_SYSRST_SPI4_APB 73 ++#define JH7110_SYSRST_SPI5_APB 74 ++#define JH7110_SYSRST_SPI6_APB 75 ++#define JH7110_SYSRST_I2C0_APB 76 ++#define JH7110_SYSRST_I2C1_APB 77 ++#define JH7110_SYSRST_I2C2_APB 78 ++#define JH7110_SYSRST_I2C3_APB 79 ++#define JH7110_SYSRST_I2C4_APB 80 ++#define JH7110_SYSRST_I2C5_APB 81 ++#define JH7110_SYSRST_I2C6_APB 82 ++#define JH7110_SYSRST_UART0_APB 83 ++#define JH7110_SYSRST_UART0_CORE 84 ++#define JH7110_SYSRST_UART1_APB 85 ++#define JH7110_SYSRST_UART1_CORE 86 ++#define JH7110_SYSRST_UART2_APB 87 ++#define JH7110_SYSRST_UART2_CORE 88 ++#define JH7110_SYSRST_UART3_APB 89 ++#define JH7110_SYSRST_UART3_CORE 90 ++#define JH7110_SYSRST_UART4_APB 91 ++#define JH7110_SYSRST_UART4_CORE 92 ++#define JH7110_SYSRST_UART5_APB 93 ++#define JH7110_SYSRST_UART5_CORE 94 ++#define JH7110_SYSRST_SPDIF_APB 95 ++ ++#define JH7110_SYSRST_PWMDAC_APB 96 ++#define JH7110_SYSRST_PDM_DMIC 97 ++#define JH7110_SYSRST_PDM_APB 98 ++#define JH7110_SYSRST_I2SRX_APB 99 ++#define JH7110_SYSRST_I2SRX_BCLK 100 ++#define JH7110_SYSRST_I2STX0_APB 101 ++#define JH7110_SYSRST_I2STX0_BCLK 102 ++#define JH7110_SYSRST_I2STX1_APB 103 ++#define JH7110_SYSRST_I2STX1_BCLK 104 ++#define JH7110_SYSRST_TDM_AHB 105 ++#define JH7110_SYSRST_TDM_CORE 106 ++#define JH7110_SYSRST_TDM_APB 107 ++#define JH7110_SYSRST_PWM_APB 108 ++#define JH7110_SYSRST_WDT_APB 109 ++#define JH7110_SYSRST_WDT_CORE 110 ++#define JH7110_SYSRST_CAN0_APB 111 ++#define JH7110_SYSRST_CAN0_CORE 112 ++#define JH7110_SYSRST_CAN0_TIMER 113 ++#define JH7110_SYSRST_CAN1_APB 114 ++#define JH7110_SYSRST_CAN1_CORE 115 ++#define JH7110_SYSRST_CAN1_TIMER 116 ++#define JH7110_SYSRST_TIMER_APB 117 ++#define JH7110_SYSRST_TIMER0 118 ++#define JH7110_SYSRST_TIMER1 119 ++#define JH7110_SYSRST_TIMER2 120 ++#define JH7110_SYSRST_TIMER3 121 ++#define JH7110_SYSRST_INT_CTRL_APB 122 ++#define JH7110_SYSRST_TEMP_APB 123 ++#define JH7110_SYSRST_TEMP_CORE 124 ++#define JH7110_SYSRST_JTAG_CERTIFICATION 125 ++ ++#define JH7110_SYSRST_END 126 ++ ++#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0002-dt-bindings-clock-Add-StarFive-JH7110-always-on-cloc.patch b/srcpkgs/linux6.3/patches/0002-dt-bindings-clock-Add-StarFive-JH7110-always-on-cloc.patch new file mode 100644 index 0000000000000..30a12271d4a21 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0002-dt-bindings-clock-Add-StarFive-JH7110-always-on-cloc.patch @@ -0,0 +1,184 @@ +From a0910efccdbc837442ba254ed3e6ffae9a321217 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:14 +0800 +Subject: [PATCH 02/84] dt-bindings: clock: Add StarFive JH7110 always-on clock + and reset generator + +Add bindings for the always-on clock and reset generator (AONCRG) on the +JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Conor Dooley +Reviewed-by: Rob Herring +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++ + 3 files changed, 137 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml +new file mode 100644 +index 000000000000..923680a44aef +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml +@@ -0,0 +1,107 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Always-On Clock and Reset Generator ++ ++maintainers: ++ - Emil Renner Berthing ++ ++properties: ++ compatible: ++ const: starfive,jh7110-aoncrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ oneOf: ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC0 RMII reference or GMAC0 RGMII RX ++ - description: STG AXI/AHB ++ - description: APB Bus ++ - description: GMAC0 GTX ++ ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC0 RMII reference or GMAC0 RGMII RX ++ - description: STG AXI/AHB or GMAC0 RGMII RX ++ - description: APB Bus or STG AXI/AHB ++ - description: GMAC0 GTX or APB Bus ++ - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX ++ ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC0 RMII reference ++ - description: GMAC0 RGMII RX ++ - description: STG AXI/AHB ++ - description: APB Bus ++ - description: GMAC0 GTX ++ - description: RTC Oscillator (32.768 kHz) ++ ++ clock-names: ++ oneOf: ++ - minItems: 5 ++ items: ++ - const: osc ++ - enum: ++ - gmac0_rmii_refin ++ - gmac0_rgmii_rxin ++ - const: stg_axiahb ++ - const: apb_bus ++ - const: gmac0_gtxclk ++ - const: rtc_osc ++ ++ - minItems: 6 ++ items: ++ - const: osc ++ - const: gmac0_rmii_refin ++ - const: gmac0_rgmii_rxin ++ - const: stg_axiahb ++ - const: apb_bus ++ - const: gmac0_gtxclk ++ - const: rtc_osc ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - '#clock-cells' ++ - '#reset-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ clock-controller@17000000 { ++ compatible = "starfive,jh7110-aoncrg"; ++ reg = <0x17000000 0x10000>; ++ clocks = <&osc>, <&gmac0_rmii_refin>, ++ <&gmac0_rgmii_rxin>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>, ++ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, ++ <&rtc_osc>; ++ clock-names = "osc", "gmac0_rmii_refin", ++ "gmac0_rgmii_rxin", "stg_axiahb", ++ "apb_bus", "gmac0_gtxclk", ++ "rtc_osc"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index fdd1852e34cc..06257bfd9ac1 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -200,4 +200,22 @@ + + #define JH7110_SYSCLK_END 190 + ++/* AONCRG clocks */ ++#define JH7110_AONCLK_OSC_DIV4 0 ++#define JH7110_AONCLK_APB_FUNC 1 ++#define JH7110_AONCLK_GMAC0_AHB 2 ++#define JH7110_AONCLK_GMAC0_AXI 3 ++#define JH7110_AONCLK_GMAC0_RMII_RTX 4 ++#define JH7110_AONCLK_GMAC0_TX 5 ++#define JH7110_AONCLK_GMAC0_TX_INV 6 ++#define JH7110_AONCLK_GMAC0_RX 7 ++#define JH7110_AONCLK_GMAC0_RX_INV 8 ++#define JH7110_AONCLK_OTPC_APB 9 ++#define JH7110_AONCLK_RTC_APB 10 ++#define JH7110_AONCLK_RTC_INTERNAL 11 ++#define JH7110_AONCLK_RTC_32K 12 ++#define JH7110_AONCLK_RTC_CAL 13 ++ ++#define JH7110_AONCLK_END 14 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index b88216a4fe40..d78e38690ceb 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -139,4 +139,16 @@ + + #define JH7110_SYSRST_END 126 + ++/* AONCRG resets */ ++#define JH7110_AONRST_GMAC0_AXI 0 ++#define JH7110_AONRST_GMAC0_AHB 1 ++#define JH7110_AONRST_IOMUX 2 ++#define JH7110_AONRST_PMU_APB 3 ++#define JH7110_AONRST_PMU_WKUP 4 ++#define JH7110_AONRST_RTC_APB 5 ++#define JH7110_AONRST_RTC_CAL 6 ++#define JH7110_AONRST_RTC_32K 7 ++ ++#define JH7110_AONRST_END 8 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0003-clk-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch b/srcpkgs/linux6.3/patches/0003-clk-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch new file mode 100644 index 0000000000000..7cbdbbff24a34 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0003-clk-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch @@ -0,0 +1,57 @@ +From f3ce3214fc7d911aed9f9170cad99a91918b5727 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sat, 1 Apr 2023 19:19:15 +0800 +Subject: [PATCH 03/84] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE + +Using ARCH_FOO symbol is preferred than SOC_FOO. +Set obj-y for starfive/ in Makefile, so the StarFive drivers +can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n. + +Reviewed-by: Conor Dooley +Signed-off-by: Hal Feng +Reviewed-by: Heiko Stuebner +--- + drivers/clk/Makefile | 2 +- + drivers/clk/starfive/Kconfig | 6 +++--- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index e3ca0d058a25..3bed88d67a3a 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -117,7 +117,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/ + obj-y += sprd/ + obj-$(CONFIG_ARCH_STI) += st/ + obj-$(CONFIG_ARCH_STM32) += stm32/ +-obj-$(CONFIG_SOC_STARFIVE) += starfive/ ++obj-y += starfive/ + obj-$(CONFIG_ARCH_SUNXI) += sunxi/ + obj-y += sunxi-ng/ + obj-$(CONFIG_ARCH_TEGRA) += tegra/ +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 003bd2d56ce7..ef3517f4a276 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -2,8 +2,8 @@ + + config CLK_STARFIVE_JH7100 + bool "StarFive JH7100 clock support" +- depends on SOC_STARFIVE || COMPILE_TEST +- default SOC_STARFIVE ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE + help + Say yes here to support the clock controller on the StarFive JH7100 + SoC. +@@ -11,7 +11,7 @@ config CLK_STARFIVE_JH7100 + config CLK_STARFIVE_JH7100_AUDIO + tristate "StarFive JH7100 audio clock support" + depends on CLK_STARFIVE_JH7100 +- default m if SOC_STARFIVE ++ default m if ARCH_STARFIVE + help + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0004-clk-starfive-Factor-out-common-JH7100-and-JH7110-cod.patch b/srcpkgs/linux6.3/patches/0004-clk-starfive-Factor-out-common-JH7100-and-JH7110-cod.patch new file mode 100644 index 0000000000000..cce39a45dd1f2 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0004-clk-starfive-Factor-out-common-JH7100-and-JH7110-cod.patch @@ -0,0 +1,760 @@ +From 5c49a496824d8dfed3bfe25965ea8e552ecd3c89 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:16 +0800 +Subject: [PATCH 04/84] clk: starfive: Factor out common JH7100 and JH7110 code + +The clock control registers on the StarFive JH7100 and JH7110 work +identically, so factor out the code then drivers for the two SoCs +can share it without depending on each other. No functional change. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + drivers/clk/starfive/Kconfig | 5 + + drivers/clk/starfive/Makefile | 3 +- + drivers/clk/starfive/clk-starfive-jh7100.c | 325 -------------------- + drivers/clk/starfive/clk-starfive-jh7100.h | 2 + + drivers/clk/starfive/clk-starfive-jh71x0.c | 333 +++++++++++++++++++++ + 5 files changed, 342 insertions(+), 326 deletions(-) + create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index ef3517f4a276..3ceeb19b5eda 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -1,8 +1,12 @@ + # SPDX-License-Identifier: GPL-2.0 + ++config CLK_STARFIVE_JH71X0 ++ bool ++ + config CLK_STARFIVE_JH7100 + bool "StarFive JH7100 clock support" + depends on ARCH_STARFIVE || COMPILE_TEST ++ select CLK_STARFIVE_JH71X0 + default ARCH_STARFIVE + help + Say yes here to support the clock controller on the StarFive JH7100 +@@ -11,6 +15,7 @@ config CLK_STARFIVE_JH7100 + config CLK_STARFIVE_JH7100_AUDIO + tristate "StarFive JH7100 audio clock support" + depends on CLK_STARFIVE_JH7100 ++ select CLK_STARFIVE_JH71X0 + default m if ARCH_STARFIVE + help + Say Y or M here to support the audio clocks on the StarFive JH7100 +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 0fa8ecb9ec1c..82edfa9f9cb8 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 +-# StarFive Clock ++obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o ++ + obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o + obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c +index 691aeebc7092..eea52f16af0d 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100.c ++++ b/drivers/clk/starfive/clk-starfive-jh7100.c +@@ -7,15 +7,10 @@ + * Copyright (C) 2021 Emil Renner Berthing + */ + +-#include + #include +-#include + #include + #include +-#include +-#include + #include +-#include + #include + + #include +@@ -269,326 +264,6 @@ static const struct jh7100_clk_data jh7100_clk_data[] __initconst = { + JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), + }; + +-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) +-{ +- return container_of(hw, struct jh7100_clk, hw); +-} +- +-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk) +-{ +- return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]); +-} +- +-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk) +-{ +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); +- void __iomem *reg = priv->base + 4 * clk->idx; +- +- return readl_relaxed(reg); +-} +- +-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) +-{ +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); +- void __iomem *reg = priv->base + 4 * clk->idx; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->rmw_lock, flags); +- value |= readl_relaxed(reg) & ~mask; +- writel_relaxed(value, reg); +- spin_unlock_irqrestore(&priv->rmw_lock, flags); +-} +- +-static int jh7100_clk_enable(struct clk_hw *hw) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE); +- return 0; +-} +- +-static void jh7100_clk_disable(struct clk_hw *hw) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0); +-} +- +-static int jh7100_clk_is_enabled(struct clk_hw *hw) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- +- return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE); +-} +- +-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK; +- +- return div ? parent_rate / div : 0; +-} +- +-static int jh7100_clk_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- unsigned long parent = req->best_parent_rate; +- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); +- unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); +- unsigned long result = parent / div; +- +- /* +- * we want the result clamped by min_rate and max_rate if possible: +- * case 1: div hits the max divider value, which means it's less than +- * parent / rate, so the result is greater than rate and min_rate in +- * particular. we can't do anything about result > max_rate because the +- * divider doesn't go any further. +- * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is +- * always lower or equal to rate and max_rate. however the result may +- * turn out lower than min_rate, but then the next higher rate is fine: +- * div - 1 = ceil(parent / rate) - 1 < parent / rate +- * and thus +- * min_rate <= rate < parent / (div - 1) +- */ +- if (result < req->min_rate && div > 1) +- result = parent / (div - 1); +- +- req->rate = result; +- return 0; +-} +- +-static int jh7100_clk_set_rate(struct clk_hw *hw, +- unsigned long rate, +- unsigned long parent_rate) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), +- 1UL, (unsigned long)clk->max_div); +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); +- return 0; +-} +- +-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw, +- unsigned long parent_rate) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 reg = jh7100_clk_reg_get(clk); +- unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) + +- ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT); +- +- return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; +-} +- +-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- unsigned long parent100 = 100 * req->best_parent_rate; +- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); +- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), +- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); +- unsigned long result = parent100 / div100; +- +- /* clamp the result as in jh7100_clk_determine_rate() above */ +- if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX) +- result = parent100 / (div100 + 1); +- if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN) +- result = parent100 / (div100 - 1); +- +- req->rate = result; +- return 0; +-} +- +-static int jh7100_clk_frac_set_rate(struct clk_hw *hw, +- unsigned long rate, +- unsigned long parent_rate) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), +- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); +- u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100); +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value); +- return 0; +-} +- +-static u8 jh7100_clk_get_parent(struct clk_hw *hw) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = jh7100_clk_reg_get(clk); +- +- return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT; +-} +- +-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = (u32)index << JH7100_CLK_MUX_SHIFT; +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value); +- return 0; +-} +- +-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw, +- struct clk_rate_request *req) +-{ +- return clk_mux_determine_rate_flags(hw, req, 0); +-} +- +-static int jh7100_clk_get_phase(struct clk_hw *hw) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = jh7100_clk_reg_get(clk); +- +- return (value & JH7100_CLK_INVERT) ? 180 : 0; +-} +- +-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees) +-{ +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value; +- +- if (degrees == 0) +- value = 0; +- else if (degrees == 180) +- value = JH7100_CLK_INVERT; +- else +- return -EINVAL; +- +- jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value); +- return 0; +-} +- +-#ifdef CONFIG_DEBUG_FS +-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) +-{ +- static const struct debugfs_reg32 jh7100_clk_reg = { +- .name = "CTRL", +- .offset = 0, +- }; +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); +- struct debugfs_regset32 *regset; +- +- regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); +- if (!regset) +- return; +- +- regset->regs = &jh7100_clk_reg; +- regset->nregs = 1; +- regset->base = priv->base + 4 * clk->idx; +- +- debugfs_create_regset32("registers", 0400, dentry, regset); +-} +-#else +-#define jh7100_clk_debug_init NULL +-#endif +- +-static const struct clk_ops jh7100_clk_gate_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_div_ops = { +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_fdiv_ops = { +- .recalc_rate = jh7100_clk_frac_recalc_rate, +- .determine_rate = jh7100_clk_frac_determine_rate, +- .set_rate = jh7100_clk_frac_set_rate, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_gdiv_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_mux_ops = { +- .determine_rate = jh7100_clk_mux_determine_rate, +- .set_parent = jh7100_clk_set_parent, +- .get_parent = jh7100_clk_get_parent, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_gmux_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .determine_rate = jh7100_clk_mux_determine_rate, +- .set_parent = jh7100_clk_set_parent, +- .get_parent = jh7100_clk_get_parent, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_mdiv_ops = { +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .get_parent = jh7100_clk_get_parent, +- .set_parent = jh7100_clk_set_parent, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_gmd_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .get_parent = jh7100_clk_get_parent, +- .set_parent = jh7100_clk_set_parent, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-static const struct clk_ops jh7100_clk_inv_ops = { +- .get_phase = jh7100_clk_get_phase, +- .set_phase = jh7100_clk_set_phase, +- .debug_init = jh7100_clk_debug_init, +-}; +- +-const struct clk_ops *starfive_jh7100_clk_ops(u32 max) +-{ +- if (max & JH7100_CLK_DIV_MASK) { +- if (max & JH7100_CLK_MUX_MASK) { +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gmd_ops; +- return &jh7100_clk_mdiv_ops; +- } +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gdiv_ops; +- if (max == JH7100_CLK_FRAC_MAX) +- return &jh7100_clk_fdiv_ops; +- return &jh7100_clk_div_ops; +- } +- +- if (max & JH7100_CLK_MUX_MASK) { +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gmux_ops; +- return &jh7100_clk_mux_ops; +- } +- +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gate_ops; +- +- return &jh7100_clk_inv_ops; +-} +-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops); +- + static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) + { + struct jh7100_clk_priv *priv = data; +diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h +index f116be5740a5..a8ba6e25b5ce 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100.h ++++ b/drivers/clk/starfive/clk-starfive-jh7100.h +@@ -4,6 +4,8 @@ + + #include + #include ++#include ++#include + + /* register fields */ + #define JH7100_CLK_ENABLE BIT(31) +diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c +new file mode 100644 +index 000000000000..6c07b61b4a32 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh71x0.c +@@ -0,0 +1,333 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7100 Clock Generator Driver ++ * ++ * Copyright (C) 2021-2022 Emil Renner Berthing ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "clk-starfive-jh7100.h" ++ ++static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) ++{ ++ return container_of(hw, struct jh7100_clk, hw); ++} ++ ++static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk) ++{ ++ return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]); ++} ++ ++static u32 jh7100_clk_reg_get(struct jh7100_clk *clk) ++{ ++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ void __iomem *reg = priv->base + 4 * clk->idx; ++ ++ return readl_relaxed(reg); ++} ++ ++static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) ++{ ++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ void __iomem *reg = priv->base + 4 * clk->idx; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&priv->rmw_lock, flags); ++ value |= readl_relaxed(reg) & ~mask; ++ writel_relaxed(value, reg); ++ spin_unlock_irqrestore(&priv->rmw_lock, flags); ++} ++ ++static int jh7100_clk_enable(struct clk_hw *hw) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE); ++ return 0; ++} ++ ++static void jh7100_clk_disable(struct clk_hw *hw) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0); ++} ++ ++static int jh7100_clk_is_enabled(struct clk_hw *hw) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ ++ return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE); ++} ++ ++static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK; ++ ++ return div ? parent_rate / div : 0; ++} ++ ++static int jh7100_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ unsigned long parent = req->best_parent_rate; ++ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); ++ unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); ++ unsigned long result = parent / div; ++ ++ /* ++ * we want the result clamped by min_rate and max_rate if possible: ++ * case 1: div hits the max divider value, which means it's less than ++ * parent / rate, so the result is greater than rate and min_rate in ++ * particular. we can't do anything about result > max_rate because the ++ * divider doesn't go any further. ++ * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is ++ * always lower or equal to rate and max_rate. however the result may ++ * turn out lower than min_rate, but then the next higher rate is fine: ++ * div - 1 = ceil(parent / rate) - 1 < parent / rate ++ * and thus ++ * min_rate <= rate < parent / (div - 1) ++ */ ++ if (result < req->min_rate && div > 1) ++ result = parent / (div - 1); ++ ++ req->rate = result; ++ return 0; ++} ++ ++static int jh7100_clk_set_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), ++ 1UL, (unsigned long)clk->max_div); ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); ++ return 0; ++} ++ ++static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 reg = jh7100_clk_reg_get(clk); ++ unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) + ++ ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT); ++ ++ return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; ++} ++ ++static int jh7100_clk_frac_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ unsigned long parent100 = 100 * req->best_parent_rate; ++ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); ++ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), ++ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); ++ unsigned long result = parent100 / div100; ++ ++ /* clamp the result as in jh7100_clk_determine_rate() above */ ++ if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX) ++ result = parent100 / (div100 + 1); ++ if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN) ++ result = parent100 / (div100 - 1); ++ ++ req->rate = result; ++ return 0; ++} ++ ++static int jh7100_clk_frac_set_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), ++ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); ++ u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100); ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value); ++ return 0; ++} ++ ++static u8 jh7100_clk_get_parent(struct clk_hw *hw) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 value = jh7100_clk_reg_get(clk); ++ ++ return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT; ++} ++ ++static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 value = (u32)index << JH7100_CLK_MUX_SHIFT; ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value); ++ return 0; ++} ++ ++static int jh7100_clk_mux_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ return clk_mux_determine_rate_flags(hw, req, 0); ++} ++ ++static int jh7100_clk_get_phase(struct clk_hw *hw) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 value = jh7100_clk_reg_get(clk); ++ ++ return (value & JH7100_CLK_INVERT) ? 180 : 0; ++} ++ ++static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees) ++{ ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ u32 value; ++ ++ if (degrees == 0) ++ value = 0; ++ else if (degrees == 180) ++ value = JH7100_CLK_INVERT; ++ else ++ return -EINVAL; ++ ++ jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value); ++ return 0; ++} ++ ++#ifdef CONFIG_DEBUG_FS ++static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ static const struct debugfs_reg32 jh7100_clk_reg = { ++ .name = "CTRL", ++ .offset = 0, ++ }; ++ struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ struct debugfs_regset32 *regset; ++ ++ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); ++ if (!regset) ++ return; ++ ++ regset->regs = &jh7100_clk_reg; ++ regset->nregs = 1; ++ regset->base = priv->base + 4 * clk->idx; ++ ++ debugfs_create_regset32("registers", 0400, dentry, regset); ++} ++#else ++#define jh7100_clk_debug_init NULL ++#endif ++ ++static const struct clk_ops jh7100_clk_gate_ops = { ++ .enable = jh7100_clk_enable, ++ .disable = jh7100_clk_disable, ++ .is_enabled = jh7100_clk_is_enabled, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_div_ops = { ++ .recalc_rate = jh7100_clk_recalc_rate, ++ .determine_rate = jh7100_clk_determine_rate, ++ .set_rate = jh7100_clk_set_rate, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_fdiv_ops = { ++ .recalc_rate = jh7100_clk_frac_recalc_rate, ++ .determine_rate = jh7100_clk_frac_determine_rate, ++ .set_rate = jh7100_clk_frac_set_rate, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_gdiv_ops = { ++ .enable = jh7100_clk_enable, ++ .disable = jh7100_clk_disable, ++ .is_enabled = jh7100_clk_is_enabled, ++ .recalc_rate = jh7100_clk_recalc_rate, ++ .determine_rate = jh7100_clk_determine_rate, ++ .set_rate = jh7100_clk_set_rate, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_mux_ops = { ++ .determine_rate = jh7100_clk_mux_determine_rate, ++ .set_parent = jh7100_clk_set_parent, ++ .get_parent = jh7100_clk_get_parent, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_gmux_ops = { ++ .enable = jh7100_clk_enable, ++ .disable = jh7100_clk_disable, ++ .is_enabled = jh7100_clk_is_enabled, ++ .determine_rate = jh7100_clk_mux_determine_rate, ++ .set_parent = jh7100_clk_set_parent, ++ .get_parent = jh7100_clk_get_parent, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_mdiv_ops = { ++ .recalc_rate = jh7100_clk_recalc_rate, ++ .determine_rate = jh7100_clk_determine_rate, ++ .get_parent = jh7100_clk_get_parent, ++ .set_parent = jh7100_clk_set_parent, ++ .set_rate = jh7100_clk_set_rate, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_gmd_ops = { ++ .enable = jh7100_clk_enable, ++ .disable = jh7100_clk_disable, ++ .is_enabled = jh7100_clk_is_enabled, ++ .recalc_rate = jh7100_clk_recalc_rate, ++ .determine_rate = jh7100_clk_determine_rate, ++ .get_parent = jh7100_clk_get_parent, ++ .set_parent = jh7100_clk_set_parent, ++ .set_rate = jh7100_clk_set_rate, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++static const struct clk_ops jh7100_clk_inv_ops = { ++ .get_phase = jh7100_clk_get_phase, ++ .set_phase = jh7100_clk_set_phase, ++ .debug_init = jh7100_clk_debug_init, ++}; ++ ++const struct clk_ops *starfive_jh7100_clk_ops(u32 max) ++{ ++ if (max & JH7100_CLK_DIV_MASK) { ++ if (max & JH7100_CLK_MUX_MASK) { ++ if (max & JH7100_CLK_ENABLE) ++ return &jh7100_clk_gmd_ops; ++ return &jh7100_clk_mdiv_ops; ++ } ++ if (max & JH7100_CLK_ENABLE) ++ return &jh7100_clk_gdiv_ops; ++ if (max == JH7100_CLK_FRAC_MAX) ++ return &jh7100_clk_fdiv_ops; ++ return &jh7100_clk_div_ops; ++ } ++ ++ if (max & JH7100_CLK_MUX_MASK) { ++ if (max & JH7100_CLK_ENABLE) ++ return &jh7100_clk_gmux_ops; ++ return &jh7100_clk_mux_ops; ++ } ++ ++ if (max & JH7100_CLK_ENABLE) ++ return &jh7100_clk_gate_ops; ++ ++ return &jh7100_clk_inv_ops; ++} ++EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0005-clk-starfive-Rename-clk-starfive-jh7100.h-to-clk-sta.patch b/srcpkgs/linux6.3/patches/0005-clk-starfive-Rename-clk-starfive-jh7100.h-to-clk-sta.patch new file mode 100644 index 0000000000000..006172b8c078f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0005-clk-starfive-Rename-clk-starfive-jh7100.h-to-clk-sta.patch @@ -0,0 +1,67 @@ +From 9d8040a22a2b23f040cfee670133b957aa5da3e7 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:17 +0800 +Subject: [PATCH 05/84] clk: starfive: Rename clk-starfive-jh7100.h to + clk-starfive-jh71x0.h + +Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making +the code to be common. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +- + drivers/clk/starfive/clk-starfive-jh7100.c | 2 +- + drivers/clk/starfive/clk-starfive-jh71x0.c | 2 +- + .../starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} | 0 + 4 files changed, 3 insertions(+), 3 deletions(-) + rename drivers/clk/starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} (100%) + +diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c +index 8473a65e219b..db0d9533bd9c 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c ++++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c +@@ -16,7 +16,7 @@ + + #include + +-#include "clk-starfive-jh7100.h" ++#include "clk-starfive-jh71x0.h" + + /* external clocks */ + #define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0) +diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c +index eea52f16af0d..662eb8f74c12 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100.c ++++ b/drivers/clk/starfive/clk-starfive-jh7100.c +@@ -15,7 +15,7 @@ + + #include + +-#include "clk-starfive-jh7100.h" ++#include "clk-starfive-jh71x0.h" + + /* external clocks */ + #define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0) +diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c +index 6c07b61b4a32..0140bdf27a01 100644 +--- a/drivers/clk/starfive/clk-starfive-jh71x0.c ++++ b/drivers/clk/starfive/clk-starfive-jh71x0.c +@@ -10,7 +10,7 @@ + #include + #include + +-#include "clk-starfive-jh7100.h" ++#include "clk-starfive-jh71x0.h" + + static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) + { +diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh71x0.h +similarity index 100% +rename from drivers/clk/starfive/clk-starfive-jh7100.h +rename to drivers/clk/starfive/clk-starfive-jh71x0.h +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0006-clk-starfive-Rename-jh7100-to-jh71x0-for-the-common-.patch b/srcpkgs/linux6.3/patches/0006-clk-starfive-Rename-jh7100-to-jh71x0-for-the-common-.patch new file mode 100644 index 0000000000000..b6deb72ad8aff --- /dev/null +++ b/srcpkgs/linux6.3/patches/0006-clk-starfive-Rename-jh7100-to-jh71x0-for-the-common-.patch @@ -0,0 +1,1258 @@ +From 50999b34d9560aa959a7be386a172c3d8b8eb986 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:18 +0800 +Subject: [PATCH 06/84] clk: starfive: Rename "jh7100" to "jh71x0" for the + common code + +Rename some variables from "jh7100" or "JH7100" to "jh71x0" +or "JH71X0". + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../clk/starfive/clk-starfive-jh7100-audio.c | 72 ++-- + drivers/clk/starfive/clk-starfive-jh7100.c | 389 +++++++++--------- + drivers/clk/starfive/clk-starfive-jh71x0.c | 282 ++++++------- + drivers/clk/starfive/clk-starfive-jh71x0.h | 81 ++-- + 4 files changed, 418 insertions(+), 406 deletions(-) + +diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c +index db0d9533bd9c..02aefb7264f8 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c ++++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c +@@ -28,66 +28,66 @@ + #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6) + #define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7) + +-static const struct jh7100_clk_data jh7100_audclk_data[] = { +- JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, ++static const struct jh71x0_clk_data jh7100_audclk_data[] = { ++ JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), +- JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, ++ JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), +- JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, ++ JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, + JH7100_AUDCLK_ADC_MCLK, + JH7100_AUDCLK_I2SADC_BCLK_IOPAD), +- JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), +- JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, ++ JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), ++ JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, + JH7100_AUDCLK_I2SADC_BCLK_N, + JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, + JH7100_AUDCLK_I2SADC_BCLK), +- JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, ++ JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), +- JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, ++ JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), +- JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, ++ JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), +- JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, ++ JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, + JH7100_AUDCLK_DAC_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), +- JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), +- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, ++ JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), ++ JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), +- JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, ++ JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), +- JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), +- JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, ++ JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), ++ JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, + JH7100_AUDCLK_I2S1_BCLK_N, + JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), +- JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), +- JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), +- JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), +- JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), +- JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), +- JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), +- JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), +- JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, ++ JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), ++ JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), ++ JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), ++ JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), ++ JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), ++ JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), ++ JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), ++ JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, + JH7100_AUDCLK_VAD_INTMEM, + JH7100_AUDCLK_AUDIO_12288), + }; + + static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data) + { +- struct jh7100_clk_priv *priv = data; ++ struct jh71x0_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7100_AUDCLK_END) +@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d + + static int jh7100_audclk_probe(struct platform_device *pdev) + { +- struct jh7100_clk_priv *priv; ++ struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; + +@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev) + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7100_audclk_data[idx].name, +- .ops = starfive_jh7100_clk_ops(max), ++ .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, +- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, ++ .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = jh7100_audclk_data[idx].flags, + }; +- struct jh7100_clk *clk = &priv->reg[idx]; ++ struct jh71x0_clk *clk = &priv->reg[idx]; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { +@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev) + + clk->hw.init = &init; + clk->idx = idx; +- clk->max_div = max & JH7100_CLK_DIV_MASK; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) +diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c +index 662eb8f74c12..69cc11ea7e33 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7100.c ++++ b/drivers/clk/starfive/clk-starfive-jh7100.c +@@ -23,250 +23,253 @@ + #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) + #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) + +-static const struct jh7100_clk_data jh7100_clk_data[] __initconst = { +- JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, ++static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { ++ JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, ++ JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, ++ JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, ++ JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, ++ JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT), +- JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, ++ JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, ++ JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, ++ JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), +- JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, ++ JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), ++ JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, ++ JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT), +- JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, ++ JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), +- JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT), +- JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT), +- JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT), +- JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT), +- JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), +- JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), +- JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, ++ JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT), ++ JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT), ++ JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT), ++ JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT), ++ JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), ++ JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), ++ JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_OSC_AUD), +- JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE), +- JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS), +- JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), +- JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), +- JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), +- JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS), +- JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI), +- JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI), +- JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT), +- JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS), +- JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS), +- JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV), +- JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT), +- JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC), +- JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT), +- JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC), +- JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS), +- JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS), +- JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), +- JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), +- JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT), +- JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC), +- JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS), +- JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS), +- JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC), +- JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS), +- JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS), +- JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), +- JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), +- JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT), +- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2), +- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4), +- JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS), +- JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4, ++ JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE), ++ JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS), ++ JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), ++ JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), ++ JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), ++ JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS), ++ JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI), ++ JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI), ++ JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT), ++ JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS), ++ JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS), ++ JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV), ++ JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT), ++ JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC), ++ JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT), ++ JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC), ++ JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS), ++ JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS), ++ JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), ++ JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), ++ JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT), ++ JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC), ++ JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS), ++ JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS), ++ JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC), ++ JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS), ++ JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS), ++ JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), ++ JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), ++ JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT), ++ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, ++ JH7100_CLK_DDRPLL_DIV2), ++ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, ++ JH7100_CLK_DDRPLL_DIV4), ++ JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS), ++ JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), +- JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4, ++ JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), +- JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), +- JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), +- JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, ++ JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), ++ JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), ++ JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, + JH7100_CLK_CPU_AXI, + JH7100_CLK_NNEBUS_SRC1), +- JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), +- JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS), +- JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS), +- JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), +- JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT), +- JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC), +- JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE), +- JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE), +- JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS), +- JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS), +- JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), +- JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), +- JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), +- JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS), +- JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS), +- JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT), +- JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), +- JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV), +- JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, ++ JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), ++ JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS), ++ JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS), ++ JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), ++ JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT), ++ JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC), ++ JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE), ++ JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE), ++ JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS), ++ JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS), ++ JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), ++ JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), ++ JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), ++ JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS), ++ JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS), ++ JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT), ++ JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), ++ JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, ++ JH7100_CLK_USBPHY_ROOTDIV), ++ JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_USBPHY_PLLDIV25M), +- JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), +- JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), +- JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), +- JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), +- JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC), +- JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS), +- JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS), +- JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS), +- JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC), +- JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS), +- JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS), +- JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC), +- JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS), +- JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS), +- JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT), +- JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT), +- JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC), +- JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS), +- JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS), +- JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC), +- JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT), +- JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC), +- JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT), +- JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT), +- JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV), +- JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), +- JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), +- JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), +- JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, ++ JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), ++ JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), ++ JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), ++ JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), ++ JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC), ++ JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS), ++ JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS), ++ JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS), ++ JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC), ++ JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS), ++ JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS), ++ JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC), ++ JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS), ++ JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS), ++ JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT), ++ JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT), ++ JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC), ++ JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS), ++ JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS), ++ JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC), ++ JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT), ++ JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC), ++ JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT), ++ JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT), ++ JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV), ++ JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), ++ JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), ++ JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), ++ JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, + JH7100_CLK_GMAC_GTX, + JH7100_CLK_GMAC_TX_INV, + JH7100_CLK_GMAC_RMII_TX), +- JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), +- JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, ++ JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), ++ JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, + JH7100_CLK_GMAC_GR_MII_RX, + JH7100_CLK_GMAC_RMII_RX), +- JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), +- JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF), +- JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV), +- JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS), +- JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS), +- JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB), +- JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB), +- JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB), +- JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC), +- JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS), +- JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), +- JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS), +- JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS), +- JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), ++ JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF), ++ JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV), ++ JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS), ++ JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS), ++ JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB), ++ JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB), ++ JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB), ++ JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC), ++ JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS), ++ JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), ++ JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS), ++ JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS), ++ JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), + }; + + static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) + { +- struct jh7100_clk_priv *priv = data; ++ struct jh71x0_clk_priv *priv = data; + unsigned int idx = clkspec->args[0]; + + if (idx < JH7100_CLK_PLL0_OUT) +@@ -280,7 +283,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data + + static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) + { +- struct jh7100_clk_priv *priv; ++ struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; + +@@ -314,12 +317,12 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jh7100_clk_data[idx].name, +- .ops = starfive_jh7100_clk_ops(max), ++ .ops = starfive_jh71x0_clk_ops(max), + .parent_data = parents, +- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, ++ .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .flags = jh7100_clk_data[idx].flags, + }; +- struct jh7100_clk *clk = &priv->reg[idx]; ++ struct jh71x0_clk *clk = &priv->reg[idx]; + unsigned int i; + + for (i = 0; i < init.num_parents; i++) { +@@ -341,7 +344,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) + + clk->hw.init = &init; + clk->idx = idx; +- clk->max_div = max & JH7100_CLK_DIV_MASK; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; + + ret = devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) +diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c +index 0140bdf27a01..b372083d11c3 100644 +--- a/drivers/clk/starfive/clk-starfive-jh71x0.c ++++ b/drivers/clk/starfive/clk-starfive-jh71x0.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0 + /* +- * StarFive JH7100 Clock Generator Driver ++ * StarFive JH71X0 Clock Generator Driver + * + * Copyright (C) 2021-2022 Emil Renner Berthing + */ +@@ -12,27 +12,27 @@ + + #include "clk-starfive-jh71x0.h" + +-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw) ++static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw) + { +- return container_of(hw, struct jh7100_clk, hw); ++ return container_of(hw, struct jh71x0_clk, hw); + } + +-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk) ++static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) + { +- return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]); ++ return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); + } + +-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk) ++static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) + { +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + void __iomem *reg = priv->base + 4 * clk->idx; + + return readl_relaxed(reg); + } + +-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) ++static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) + { +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + void __iomem *reg = priv->base + 4 * clk->idx; + unsigned long flags; + +@@ -42,41 +42,41 @@ static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value) + spin_unlock_irqrestore(&priv->rmw_lock, flags); + } + +-static int jh7100_clk_enable(struct clk_hw *hw) ++static int jh71x0_clk_enable(struct clk_hw *hw) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE); + return 0; + } + +-static void jh7100_clk_disable(struct clk_hw *hw) ++static void jh71x0_clk_disable(struct clk_hw *hw) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0); + } + +-static int jh7100_clk_is_enabled(struct clk_hw *hw) ++static int jh71x0_clk_is_enabled(struct clk_hw *hw) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + +- return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE); ++ return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE); + } + +-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw, ++static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK; ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK; + + return div ? parent_rate / div : 0; + } + +-static int jh7100_clk_determine_rate(struct clk_hw *hw, ++static int jh71x0_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + unsigned long parent = req->best_parent_rate; + unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); + unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); +@@ -102,232 +102,232 @@ static int jh7100_clk_determine_rate(struct clk_hw *hw, + return 0; + } + +-static int jh7100_clk_set_rate(struct clk_hw *hw, ++static int jh71x0_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), + 1UL, (unsigned long)clk->max_div); + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div); + return 0; + } + +-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw, ++static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 reg = jh7100_clk_reg_get(clk); +- unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) + +- ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ u32 reg = jh71x0_clk_reg_get(clk); ++ unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) + ++ ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT); + +- return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; ++ return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; + } + +-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw, ++static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { + unsigned long parent100 = 100 * req->best_parent_rate; + unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), +- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); ++ JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX); + unsigned long result = parent100 / div100; + +- /* clamp the result as in jh7100_clk_determine_rate() above */ +- if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX) ++ /* clamp the result as in jh71x0_clk_determine_rate() above */ ++ if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX) + result = parent100 / (div100 + 1); +- if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN) ++ if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN) + result = parent100 / (div100 - 1); + + req->rate = result; + return 0; + } + +-static int jh7100_clk_frac_set_rate(struct clk_hw *hw, ++static int jh71x0_clk_frac_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), +- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX); +- u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100); ++ JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX); ++ u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100); + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value); + return 0; + } + +-static u8 jh7100_clk_get_parent(struct clk_hw *hw) ++static u8 jh71x0_clk_get_parent(struct clk_hw *hw) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = jh7100_clk_reg_get(clk); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ u32 value = jh71x0_clk_reg_get(clk); + +- return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT; ++ return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT; + } + +-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index) ++static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = (u32)index << JH7100_CLK_MUX_SHIFT; ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT; + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value); + return 0; + } + +-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw, ++static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { + return clk_mux_determine_rate_flags(hw, req, 0); + } + +-static int jh7100_clk_get_phase(struct clk_hw *hw) ++static int jh71x0_clk_get_phase(struct clk_hw *hw) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- u32 value = jh7100_clk_reg_get(clk); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ u32 value = jh71x0_clk_reg_get(clk); + +- return (value & JH7100_CLK_INVERT) ? 180 : 0; ++ return (value & JH71X0_CLK_INVERT) ? 180 : 0; + } + +-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees) ++static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees) + { +- struct jh7100_clk *clk = jh7100_clk_from(hw); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); + u32 value; + + if (degrees == 0) + value = 0; + else if (degrees == 180) +- value = JH7100_CLK_INVERT; ++ value = JH71X0_CLK_INVERT; + else + return -EINVAL; + +- jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value); ++ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value); + return 0; + } + + #ifdef CONFIG_DEBUG_FS +-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) ++static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) + { +- static const struct debugfs_reg32 jh7100_clk_reg = { ++ static const struct debugfs_reg32 jh71x0_clk_reg = { + .name = "CTRL", + .offset = 0, + }; +- struct jh7100_clk *clk = jh7100_clk_from(hw); +- struct jh7100_clk_priv *priv = jh7100_priv_from(clk); ++ struct jh71x0_clk *clk = jh71x0_clk_from(hw); ++ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + struct debugfs_regset32 *regset; + + regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); + if (!regset) + return; + +- regset->regs = &jh7100_clk_reg; ++ regset->regs = &jh71x0_clk_reg; + regset->nregs = 1; + regset->base = priv->base + 4 * clk->idx; + + debugfs_create_regset32("registers", 0400, dentry, regset); + } + #else +-#define jh7100_clk_debug_init NULL ++#define jh71x0_clk_debug_init NULL + #endif + +-static const struct clk_ops jh7100_clk_gate_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_gate_ops = { ++ .enable = jh71x0_clk_enable, ++ .disable = jh71x0_clk_disable, ++ .is_enabled = jh71x0_clk_is_enabled, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_div_ops = { +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_div_ops = { ++ .recalc_rate = jh71x0_clk_recalc_rate, ++ .determine_rate = jh71x0_clk_determine_rate, ++ .set_rate = jh71x0_clk_set_rate, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_fdiv_ops = { +- .recalc_rate = jh7100_clk_frac_recalc_rate, +- .determine_rate = jh7100_clk_frac_determine_rate, +- .set_rate = jh7100_clk_frac_set_rate, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_fdiv_ops = { ++ .recalc_rate = jh71x0_clk_frac_recalc_rate, ++ .determine_rate = jh71x0_clk_frac_determine_rate, ++ .set_rate = jh71x0_clk_frac_set_rate, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_gdiv_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_gdiv_ops = { ++ .enable = jh71x0_clk_enable, ++ .disable = jh71x0_clk_disable, ++ .is_enabled = jh71x0_clk_is_enabled, ++ .recalc_rate = jh71x0_clk_recalc_rate, ++ .determine_rate = jh71x0_clk_determine_rate, ++ .set_rate = jh71x0_clk_set_rate, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_mux_ops = { +- .determine_rate = jh7100_clk_mux_determine_rate, +- .set_parent = jh7100_clk_set_parent, +- .get_parent = jh7100_clk_get_parent, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_mux_ops = { ++ .determine_rate = jh71x0_clk_mux_determine_rate, ++ .set_parent = jh71x0_clk_set_parent, ++ .get_parent = jh71x0_clk_get_parent, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_gmux_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .determine_rate = jh7100_clk_mux_determine_rate, +- .set_parent = jh7100_clk_set_parent, +- .get_parent = jh7100_clk_get_parent, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_gmux_ops = { ++ .enable = jh71x0_clk_enable, ++ .disable = jh71x0_clk_disable, ++ .is_enabled = jh71x0_clk_is_enabled, ++ .determine_rate = jh71x0_clk_mux_determine_rate, ++ .set_parent = jh71x0_clk_set_parent, ++ .get_parent = jh71x0_clk_get_parent, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_mdiv_ops = { +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .get_parent = jh7100_clk_get_parent, +- .set_parent = jh7100_clk_set_parent, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_mdiv_ops = { ++ .recalc_rate = jh71x0_clk_recalc_rate, ++ .determine_rate = jh71x0_clk_determine_rate, ++ .get_parent = jh71x0_clk_get_parent, ++ .set_parent = jh71x0_clk_set_parent, ++ .set_rate = jh71x0_clk_set_rate, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_gmd_ops = { +- .enable = jh7100_clk_enable, +- .disable = jh7100_clk_disable, +- .is_enabled = jh7100_clk_is_enabled, +- .recalc_rate = jh7100_clk_recalc_rate, +- .determine_rate = jh7100_clk_determine_rate, +- .get_parent = jh7100_clk_get_parent, +- .set_parent = jh7100_clk_set_parent, +- .set_rate = jh7100_clk_set_rate, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_gmd_ops = { ++ .enable = jh71x0_clk_enable, ++ .disable = jh71x0_clk_disable, ++ .is_enabled = jh71x0_clk_is_enabled, ++ .recalc_rate = jh71x0_clk_recalc_rate, ++ .determine_rate = jh71x0_clk_determine_rate, ++ .get_parent = jh71x0_clk_get_parent, ++ .set_parent = jh71x0_clk_set_parent, ++ .set_rate = jh71x0_clk_set_rate, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-static const struct clk_ops jh7100_clk_inv_ops = { +- .get_phase = jh7100_clk_get_phase, +- .set_phase = jh7100_clk_set_phase, +- .debug_init = jh7100_clk_debug_init, ++static const struct clk_ops jh71x0_clk_inv_ops = { ++ .get_phase = jh71x0_clk_get_phase, ++ .set_phase = jh71x0_clk_set_phase, ++ .debug_init = jh71x0_clk_debug_init, + }; + +-const struct clk_ops *starfive_jh7100_clk_ops(u32 max) ++const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) + { +- if (max & JH7100_CLK_DIV_MASK) { +- if (max & JH7100_CLK_MUX_MASK) { +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gmd_ops; +- return &jh7100_clk_mdiv_ops; ++ if (max & JH71X0_CLK_DIV_MASK) { ++ if (max & JH71X0_CLK_MUX_MASK) { ++ if (max & JH71X0_CLK_ENABLE) ++ return &jh71x0_clk_gmd_ops; ++ return &jh71x0_clk_mdiv_ops; + } +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gdiv_ops; +- if (max == JH7100_CLK_FRAC_MAX) +- return &jh7100_clk_fdiv_ops; +- return &jh7100_clk_div_ops; ++ if (max & JH71X0_CLK_ENABLE) ++ return &jh71x0_clk_gdiv_ops; ++ if (max == JH71X0_CLK_FRAC_MAX) ++ return &jh71x0_clk_fdiv_ops; ++ return &jh71x0_clk_div_ops; + } + +- if (max & JH7100_CLK_MUX_MASK) { +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gmux_ops; +- return &jh7100_clk_mux_ops; ++ if (max & JH71X0_CLK_MUX_MASK) { ++ if (max & JH71X0_CLK_ENABLE) ++ return &jh71x0_clk_gmux_ops; ++ return &jh71x0_clk_mux_ops; + } + +- if (max & JH7100_CLK_ENABLE) +- return &jh7100_clk_gate_ops; ++ if (max & JH71X0_CLK_ENABLE) ++ return &jh71x0_clk_gate_ops; + +- return &jh7100_clk_inv_ops; ++ return &jh71x0_clk_inv_ops; + } +-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops); ++EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); +diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h +index a8ba6e25b5ce..34bb11c72eb7 100644 +--- a/drivers/clk/starfive/clk-starfive-jh71x0.h ++++ b/drivers/clk/starfive/clk-starfive-jh71x0.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: GPL-2.0 */ +-#ifndef __CLK_STARFIVE_JH7100_H +-#define __CLK_STARFIVE_JH7100_H ++#ifndef __CLK_STARFIVE_JH71X0_H ++#define __CLK_STARFIVE_JH71X0_H + + #include + #include +@@ -8,107 +8,116 @@ + #include + + /* register fields */ +-#define JH7100_CLK_ENABLE BIT(31) +-#define JH7100_CLK_INVERT BIT(30) +-#define JH7100_CLK_MUX_MASK GENMASK(27, 24) +-#define JH7100_CLK_MUX_SHIFT 24 +-#define JH7100_CLK_DIV_MASK GENMASK(23, 0) +-#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) +-#define JH7100_CLK_FRAC_SHIFT 8 +-#define JH7100_CLK_INT_MASK GENMASK(7, 0) ++#define JH71X0_CLK_ENABLE BIT(31) ++#define JH71X0_CLK_INVERT BIT(30) ++#define JH71X0_CLK_MUX_MASK GENMASK(27, 24) ++#define JH71X0_CLK_MUX_SHIFT 24 ++#define JH71X0_CLK_DIV_MASK GENMASK(23, 0) ++#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8) ++#define JH71X0_CLK_FRAC_SHIFT 8 ++#define JH71X0_CLK_INT_MASK GENMASK(7, 0) + + /* fractional divider min/max */ +-#define JH7100_CLK_FRAC_MIN 100UL +-#define JH7100_CLK_FRAC_MAX 25599UL ++#define JH71X0_CLK_FRAC_MIN 100UL ++#define JH71X0_CLK_FRAC_MAX 25599UL + + /* clock data */ +-struct jh7100_clk_data { ++struct jh71x0_clk_data { + const char *name; + unsigned long flags; + u32 max; + u8 parents[4]; + }; + +-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ ++#define JH71X0_GATE(_idx, _name, _flags, _parent) \ ++[_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT | (_flags), \ +- .max = JH7100_CLK_ENABLE, \ ++ .max = JH71X0_CLK_ENABLE, \ + .parents = { [0] = _parent }, \ + } + +-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ ++#define JH71X0__DIV(_idx, _name, _max, _parent) \ ++[_idx] = { \ + .name = _name, \ + .flags = 0, \ + .max = _max, \ + .parents = { [0] = _parent }, \ + } + +-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ ++#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ ++[_idx] = { \ + .name = _name, \ + .flags = _flags, \ +- .max = JH7100_CLK_ENABLE | (_max), \ ++ .max = JH71X0_CLK_ENABLE | (_max), \ + .parents = { [0] = _parent }, \ + } + +-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ ++#define JH71X0_FDIV(_idx, _name, _parent) \ ++[_idx] = { \ + .name = _name, \ + .flags = 0, \ +- .max = JH7100_CLK_FRAC_MAX, \ ++ .max = JH71X0_CLK_FRAC_MAX, \ + .parents = { [0] = _parent }, \ + } + +-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ ++#define JH71X0__MUX(_idx, _name, _nparents, ...) \ ++[_idx] = { \ + .name = _name, \ + .flags = 0, \ +- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ ++ .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \ + .parents = { __VA_ARGS__ }, \ + } + +-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ ++#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \ ++[_idx] = { \ + .name = _name, \ + .flags = _flags, \ +- .max = JH7100_CLK_ENABLE | \ +- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ ++ .max = JH71X0_CLK_ENABLE | \ ++ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \ + .parents = { __VA_ARGS__ }, \ + } + +-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \ ++#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \ ++[_idx] = { \ + .name = _name, \ + .flags = 0, \ +- .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ ++ .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ + } + +-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \ ++#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \ ++[_idx] = { \ + .name = _name, \ + .flags = _flags, \ +- .max = JH7100_CLK_ENABLE | \ +- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ ++ .max = JH71X0_CLK_ENABLE | \ ++ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \ + .parents = { __VA_ARGS__ }, \ + } + +-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ ++#define JH71X0__INV(_idx, _name, _parent) \ ++[_idx] = { \ + .name = _name, \ + .flags = CLK_SET_RATE_PARENT, \ +- .max = JH7100_CLK_INVERT, \ ++ .max = JH71X0_CLK_INVERT, \ + .parents = { [0] = _parent }, \ + } + +-struct jh7100_clk { ++struct jh71x0_clk { + struct clk_hw hw; + unsigned int idx; + unsigned int max_div; + }; + +-struct jh7100_clk_priv { ++struct jh71x0_clk_priv { + /* protect clk enable and set rate/parent from happening at the same time */ + spinlock_t rmw_lock; + struct device *dev; + void __iomem *base; + struct clk_hw *pll[3]; +- struct jh7100_clk reg[]; ++ struct jh71x0_clk reg[]; + }; + +-const struct clk_ops *starfive_jh7100_clk_ops(u32 max); ++const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); + + #endif +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0007-reset-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFI.patch b/srcpkgs/linux6.3/patches/0007-reset-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFI.patch new file mode 100644 index 0000000000000..4fed9e07e4b3c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0007-reset-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFI.patch @@ -0,0 +1,33 @@ +From e903bebe2e352577bf0bcb8fdfe10d1abb86afe5 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sat, 1 Apr 2023 19:19:19 +0800 +Subject: [PATCH 07/84] reset: starfive: Replace SOC_STARFIVE with + ARCH_STARFIVE + +Using ARCH_FOO symbol is preferred than SOC_FOO. + +Reviewed-by: Philipp Zabel +Reviewed-by: Conor Dooley +Signed-off-by: Hal Feng +--- + drivers/reset/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 2a52c990d4fe..6ae5aa46a6b2 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -234,8 +234,8 @@ config RESET_SOCFPGA + + config RESET_STARFIVE_JH7100 + bool "StarFive JH7100 Reset Driver" +- depends on SOC_STARFIVE || COMPILE_TEST +- default SOC_STARFIVE ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JH7100 SoC. + +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0008-reset-Create-subdirectory-for-StarFive-drivers.patch b/srcpkgs/linux6.3/patches/0008-reset-Create-subdirectory-for-StarFive-drivers.patch new file mode 100644 index 0000000000000..199c3b71a6506 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0008-reset-Create-subdirectory-for-StarFive-drivers.patch @@ -0,0 +1,99 @@ +From 341c6a4f66ab404a775e6a3a5a62fa8d10d7d905 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:20 +0800 +Subject: [PATCH 08/84] reset: Create subdirectory for StarFive drivers + +This moves the StarFive JH7100 reset driver to a new subdirectory in +preparation for adding more StarFive reset drivers. + +Reviewed-by: Philipp Zabel +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + drivers/reset/Kconfig | 8 +------- + drivers/reset/Makefile | 2 +- + drivers/reset/starfive/Kconfig | 8 ++++++++ + drivers/reset/starfive/Makefile | 2 ++ + drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0 + 5 files changed, 12 insertions(+), 8 deletions(-) + create mode 100644 drivers/reset/starfive/Kconfig + create mode 100644 drivers/reset/starfive/Makefile + rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%) + +diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig +index 6ae5aa46a6b2..6aa8f243b30c 100644 +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -232,13 +232,6 @@ config RESET_SOCFPGA + This enables the reset driver for the SoCFPGA ARMv7 platforms. This + driver gets initialized early during platform init calls. + +-config RESET_STARFIVE_JH7100 +- bool "StarFive JH7100 Reset Driver" +- depends on ARCH_STARFIVE || COMPILE_TEST +- default ARCH_STARFIVE +- help +- This enables the reset controller driver for the StarFive JH7100 SoC. +- + config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" if COMPILE_TEST + default ARCH_SUNPLUS +@@ -320,6 +313,7 @@ config RESET_ZYNQ + help + This enables the reset controller driver for Xilinx Zynq SoCs. + ++source "drivers/reset/starfive/Kconfig" + source "drivers/reset/sti/Kconfig" + source "drivers/reset/hisilicon/Kconfig" + source "drivers/reset/tegra/Kconfig" +diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile +index 3e7e5fd633a8..7fec5af6c964 100644 +--- a/drivers/reset/Makefile ++++ b/drivers/reset/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-y += core.o + obj-y += hisilicon/ ++obj-y += starfive/ + obj-$(CONFIG_ARCH_STI) += sti/ + obj-$(CONFIG_ARCH_TEGRA) += tegra/ + obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o +@@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o + obj-$(CONFIG_RESET_SCMI) += reset-scmi.o + obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o + obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o + obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o + obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o + obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o +diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig +new file mode 100644 +index 000000000000..abbf0c52d03e +--- /dev/null ++++ b/drivers/reset/starfive/Kconfig +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++config RESET_STARFIVE_JH7100 ++ bool "StarFive JH7100 Reset Driver" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE ++ help ++ This enables the reset controller driver for the StarFive JH7100 SoC. +diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile +new file mode 100644 +index 000000000000..670d049423f5 +--- /dev/null ++++ b/drivers/reset/starfive/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o +diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c +similarity index 100% +rename from drivers/reset/reset-starfive-jh7100.c +rename to drivers/reset/starfive/reset-starfive-jh7100.c +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0009-reset-starfive-Factor-out-common-JH71X0-reset-code.patch b/srcpkgs/linux6.3/patches/0009-reset-starfive-Factor-out-common-JH71X0-reset-code.patch new file mode 100644 index 0000000000000..aa73b3b80ae99 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0009-reset-starfive-Factor-out-common-JH71X0-reset-code.patch @@ -0,0 +1,403 @@ +From 3bc6939db614bc2d88001cfbe9851144fdc8a434 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:21 +0800 +Subject: [PATCH 09/84] reset: starfive: Factor out common JH71X0 reset code + +The StarFive JH7100 SoC has additional reset controllers for audio and +video, but the registers follow the same structure. On the JH7110 the +reset registers don't get their own memory range, but instead follow the +clock control registers. The registers still follow the same structure +though, so let's factor out the common code to handle all these cases. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + drivers/reset/starfive/Kconfig | 4 + + drivers/reset/starfive/Makefile | 2 + + .../reset/starfive/reset-starfive-jh7100.c | 150 +--------------- + .../reset/starfive/reset-starfive-jh71x0.c | 162 ++++++++++++++++++ + .../reset/starfive/reset-starfive-jh71x0.h | 11 ++ + 5 files changed, 180 insertions(+), 149 deletions(-) + create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c + create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h + +diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig +index abbf0c52d03e..1927a5a3b53a 100644 +--- a/drivers/reset/starfive/Kconfig ++++ b/drivers/reset/starfive/Kconfig +@@ -1,8 +1,12 @@ + # SPDX-License-Identifier: GPL-2.0-only + ++config RESET_STARFIVE_JH71X0 ++ bool ++ + config RESET_STARFIVE_JH7100 + bool "StarFive JH7100 Reset Driver" + depends on ARCH_STARFIVE || COMPILE_TEST ++ select RESET_STARFIVE_JH71X0 + default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JH7100 SoC. +diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile +index 670d049423f5..f6aa12466fad 100644 +--- a/drivers/reset/starfive/Makefile ++++ b/drivers/reset/starfive/Makefile +@@ -1,2 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o ++ + obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o +diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c +index fc44b2fb3e03..5a68327c1f6a 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7100.c ++++ b/drivers/reset/starfive/reset-starfive-jh7100.c +@@ -5,158 +5,10 @@ + * Copyright (C) 2021 Emil Renner Berthing + */ + +-#include +-#include +-#include +-#include + #include + #include +-#include +-#include + +-#include +- +-/* register offsets */ +-#define JH7100_RESET_ASSERT0 0x00 +-#define JH7100_RESET_ASSERT1 0x04 +-#define JH7100_RESET_ASSERT2 0x08 +-#define JH7100_RESET_ASSERT3 0x0c +-#define JH7100_RESET_STATUS0 0x10 +-#define JH7100_RESET_STATUS1 0x14 +-#define JH7100_RESET_STATUS2 0x18 +-#define JH7100_RESET_STATUS3 0x1c +- +-/* +- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts +- * line 32m + n, and writing a 0 deasserts the same line. +- * Most reset lines have their status inverted so a 0 bit in the STATUS +- * register means the line is asserted and a 1 means it's deasserted. A few +- * lines don't though, so store the expected value of the status registers when +- * all lines are asserted. +- */ +-static const u64 jh7100_reset_asserted[2] = { +- /* STATUS0 */ +- BIT_ULL_MASK(JH7100_RST_U74) | +- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | +- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | +- /* STATUS1 */ +- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | +- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), +- /* STATUS2 */ +- BIT_ULL_MASK(JH7100_RST_E24) | +- /* STATUS3 */ +- 0, +-}; +- +-struct jh7100_reset { +- struct reset_controller_dev rcdev; +- /* protect registers against concurrent read-modify-write */ +- spinlock_t lock; +- void __iomem *base; +-}; +- +-static inline struct jh7100_reset * +-jh7100_reset_from(struct reset_controller_dev *rcdev) +-{ +- return container_of(rcdev, struct jh7100_reset, rcdev); +-} +- +-static int jh7100_reset_update(struct reset_controller_dev *rcdev, +- unsigned long id, bool assert) +-{ +- struct jh7100_reset *data = jh7100_reset_from(rcdev); +- unsigned long offset = BIT_ULL_WORD(id); +- u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64); +- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); +- u64 done = jh7100_reset_asserted[offset] & mask; +- u64 value; +- unsigned long flags; +- int ret; +- +- if (!assert) +- done ^= mask; +- +- spin_lock_irqsave(&data->lock, flags); +- +- value = readq(reg_assert); +- if (assert) +- value |= mask; +- else +- value &= ~mask; +- writeq(value, reg_assert); +- +- /* if the associated clock is gated, deasserting might otherwise hang forever */ +- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); +- +- spin_unlock_irqrestore(&data->lock, flags); +- return ret; +-} +- +-static int jh7100_reset_assert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return jh7100_reset_update(rcdev, id, true); +-} +- +-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- return jh7100_reset_update(rcdev, id, false); +-} +- +-static int jh7100_reset_reset(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- int ret; +- +- ret = jh7100_reset_assert(rcdev, id); +- if (ret) +- return ret; +- +- return jh7100_reset_deassert(rcdev, id); +-} +- +-static int jh7100_reset_status(struct reset_controller_dev *rcdev, +- unsigned long id) +-{ +- struct jh7100_reset *data = jh7100_reset_from(rcdev); +- unsigned long offset = BIT_ULL_WORD(id); +- u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); +- u64 value = readq(reg_status); +- +- return !((value ^ jh7100_reset_asserted[offset]) & mask); +-} +- +-static const struct reset_control_ops jh7100_reset_ops = { +- .assert = jh7100_reset_assert, +- .deassert = jh7100_reset_deassert, +- .reset = jh7100_reset_reset, +- .status = jh7100_reset_status, +-}; +- +-static int __init jh7100_reset_probe(struct platform_device *pdev) +-{ +- struct jh7100_reset *data; +- +- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); +- if (!data) +- return -ENOMEM; +- +- data->base = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(data->base)) +- return PTR_ERR(data->base); +- +- data->rcdev.ops = &jh7100_reset_ops; +- data->rcdev.owner = THIS_MODULE; +- data->rcdev.nr_resets = JH7100_RSTN_END; +- data->rcdev.dev = &pdev->dev; +- data->rcdev.of_node = pdev->dev.of_node; +- spin_lock_init(&data->lock); +- +- return devm_reset_controller_register(&pdev->dev, &data->rcdev); +-} ++#include "reset-starfive-jh71x0.h" + + static const struct of_device_id jh7100_reset_dt_ids[] = { + { .compatible = "starfive,jh7100-reset" }, +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c +new file mode 100644 +index 000000000000..114a13c4b8a6 +--- /dev/null ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.c +@@ -0,0 +1,162 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Reset driver for the StarFive JH7100 SoC ++ * ++ * Copyright (C) 2021 Emil Renner Berthing ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "reset-starfive-jh71x0.h" ++ ++#include ++ ++/* register offsets */ ++#define JH7100_RESET_ASSERT0 0x00 ++#define JH7100_RESET_ASSERT1 0x04 ++#define JH7100_RESET_ASSERT2 0x08 ++#define JH7100_RESET_ASSERT3 0x0c ++#define JH7100_RESET_STATUS0 0x10 ++#define JH7100_RESET_STATUS1 0x14 ++#define JH7100_RESET_STATUS2 0x18 ++#define JH7100_RESET_STATUS3 0x1c ++ ++/* ++ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts ++ * line 32m + n, and writing a 0 deasserts the same line. ++ * Most reset lines have their status inverted so a 0 bit in the STATUS ++ * register means the line is asserted and a 1 means it's deasserted. A few ++ * lines don't though, so store the expected value of the status registers when ++ * all lines are asserted. ++ */ ++static const u64 jh7100_reset_asserted[2] = { ++ /* STATUS0 */ ++ BIT_ULL_MASK(JH7100_RST_U74) | ++ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | ++ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | ++ /* STATUS1 */ ++ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | ++ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), ++ /* STATUS2 */ ++ BIT_ULL_MASK(JH7100_RST_E24) | ++ /* STATUS3 */ ++ 0, ++}; ++ ++struct jh7100_reset { ++ struct reset_controller_dev rcdev; ++ /* protect registers against concurrent read-modify-write */ ++ spinlock_t lock; ++ void __iomem *base; ++}; ++ ++static inline struct jh7100_reset * ++jh7100_reset_from(struct reset_controller_dev *rcdev) ++{ ++ return container_of(rcdev, struct jh7100_reset, rcdev); ++} ++ ++static int jh7100_reset_update(struct reset_controller_dev *rcdev, ++ unsigned long id, bool assert) ++{ ++ struct jh7100_reset *data = jh7100_reset_from(rcdev); ++ unsigned long offset = BIT_ULL_WORD(id); ++ u64 mask = BIT_ULL_MASK(id); ++ void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64); ++ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); ++ u64 done = jh7100_reset_asserted[offset] & mask; ++ u64 value; ++ unsigned long flags; ++ int ret; ++ ++ if (!assert) ++ done ^= mask; ++ ++ spin_lock_irqsave(&data->lock, flags); ++ ++ value = readq(reg_assert); ++ if (assert) ++ value |= mask; ++ else ++ value &= ~mask; ++ writeq(value, reg_assert); ++ ++ /* if the associated clock is gated, deasserting might otherwise hang forever */ ++ ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); ++ ++ spin_unlock_irqrestore(&data->lock, flags); ++ return ret; ++} ++ ++static int jh7100_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return jh7100_reset_update(rcdev, id, true); ++} ++ ++static int jh7100_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ return jh7100_reset_update(rcdev, id, false); ++} ++ ++static int jh7100_reset_reset(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ int ret; ++ ++ ret = jh7100_reset_assert(rcdev, id); ++ if (ret) ++ return ret; ++ ++ return jh7100_reset_deassert(rcdev, id); ++} ++ ++static int jh7100_reset_status(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct jh7100_reset *data = jh7100_reset_from(rcdev); ++ unsigned long offset = BIT_ULL_WORD(id); ++ u64 mask = BIT_ULL_MASK(id); ++ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); ++ u64 value = readq(reg_status); ++ ++ return !((value ^ jh7100_reset_asserted[offset]) & mask); ++} ++ ++static const struct reset_control_ops jh7100_reset_ops = { ++ .assert = jh7100_reset_assert, ++ .deassert = jh7100_reset_deassert, ++ .reset = jh7100_reset_reset, ++ .status = jh7100_reset_status, ++}; ++ ++int jh7100_reset_probe(struct platform_device *pdev) ++{ ++ struct jh7100_reset *data; ++ ++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ data->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(data->base)) ++ return PTR_ERR(data->base); ++ ++ data->rcdev.ops = &jh7100_reset_ops; ++ data->rcdev.owner = THIS_MODULE; ++ data->rcdev.nr_resets = JH7100_RSTN_END; ++ data->rcdev.dev = &pdev->dev; ++ data->rcdev.of_node = pdev->dev.of_node; ++ spin_lock_init(&data->lock); ++ ++ return devm_reset_controller_register(&pdev->dev, &data->rcdev); ++} ++EXPORT_SYMBOL_GPL(jh7100_reset_probe); +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h +new file mode 100644 +index 000000000000..318d7a0e096a +--- /dev/null ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0-or-later */ ++/* ++ * Copyright (C) 2021 Emil Renner Berthing ++ */ ++ ++#ifndef __RESET_STARFIVE_JH71X0_H ++#define __RESET_STARFIVE_JH71X0_H ++ ++int jh7100_reset_probe(struct platform_device *pdev); ++ ++#endif /* __RESET_STARFIVE_JH71X0_H */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0010-reset-starfive-Extract-the-common-JH71X0-reset-code.patch b/srcpkgs/linux6.3/patches/0010-reset-starfive-Extract-the-common-JH71X0-reset-code.patch new file mode 100644 index 0000000000000..96d81be8aee59 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0010-reset-starfive-Extract-the-common-JH71X0-reset-code.patch @@ -0,0 +1,222 @@ +From 87464a537e8e8c15c217919acb7008cc5799cf30 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:22 +0800 +Subject: [PATCH 10/84] reset: starfive: Extract the common JH71X0 reset code + +Extract the common JH71X0 reset code for reusing them to +support JH7110 SoC. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../reset/starfive/reset-starfive-jh7100.c | 49 ++++++++++++ + .../reset/starfive/reset-starfive-jh71x0.c | 76 ++++++------------- + .../reset/starfive/reset-starfive-jh71x0.h | 5 +- + 3 files changed, 76 insertions(+), 54 deletions(-) + +diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c +index 5a68327c1f6a..9d7cb4ed8869 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7100.c ++++ b/drivers/reset/starfive/reset-starfive-jh7100.c +@@ -10,6 +10,55 @@ + + #include "reset-starfive-jh71x0.h" + ++#include ++ ++/* register offsets */ ++#define JH7100_RESET_ASSERT0 0x00 ++#define JH7100_RESET_ASSERT1 0x04 ++#define JH7100_RESET_ASSERT2 0x08 ++#define JH7100_RESET_ASSERT3 0x0c ++#define JH7100_RESET_STATUS0 0x10 ++#define JH7100_RESET_STATUS1 0x14 ++#define JH7100_RESET_STATUS2 0x18 ++#define JH7100_RESET_STATUS3 0x1c ++ ++/* ++ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts ++ * line 32m + n, and writing a 0 deasserts the same line. ++ * Most reset lines have their status inverted so a 0 bit in the STATUS ++ * register means the line is asserted and a 1 means it's deasserted. A few ++ * lines don't though, so store the expected value of the status registers when ++ * all lines are asserted. ++ */ ++static const u64 jh7100_reset_asserted[2] = { ++ /* STATUS0 */ ++ BIT_ULL_MASK(JH7100_RST_U74) | ++ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | ++ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | ++ /* STATUS1 */ ++ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | ++ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), ++ /* STATUS2 */ ++ BIT_ULL_MASK(JH7100_RST_E24) | ++ /* STATUS3 */ ++ 0, ++}; ++ ++static int __init jh7100_reset_probe(struct platform_device *pdev) ++{ ++ void __iomem *base = devm_platform_ioremap_resource(pdev, 0); ++ ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node, ++ base + JH7100_RESET_ASSERT0, ++ base + JH7100_RESET_STATUS0, ++ jh7100_reset_asserted, ++ JH7100_RSTN_END, ++ THIS_MODULE); ++} ++ + static const struct of_device_id jh7100_reset_dt_ids[] = { + { .compatible = "starfive,jh7100-reset" }, + { /* sentinel */ } +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c +index 114a13c4b8a6..3577444a89c6 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.c ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.c +@@ -10,51 +10,18 @@ + #include + #include + #include +-#include + #include + #include + + #include "reset-starfive-jh71x0.h" + +-#include +- +-/* register offsets */ +-#define JH7100_RESET_ASSERT0 0x00 +-#define JH7100_RESET_ASSERT1 0x04 +-#define JH7100_RESET_ASSERT2 0x08 +-#define JH7100_RESET_ASSERT3 0x0c +-#define JH7100_RESET_STATUS0 0x10 +-#define JH7100_RESET_STATUS1 0x14 +-#define JH7100_RESET_STATUS2 0x18 +-#define JH7100_RESET_STATUS3 0x1c +- +-/* +- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts +- * line 32m + n, and writing a 0 deasserts the same line. +- * Most reset lines have their status inverted so a 0 bit in the STATUS +- * register means the line is asserted and a 1 means it's deasserted. A few +- * lines don't though, so store the expected value of the status registers when +- * all lines are asserted. +- */ +-static const u64 jh7100_reset_asserted[2] = { +- /* STATUS0 */ +- BIT_ULL_MASK(JH7100_RST_U74) | +- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | +- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | +- /* STATUS1 */ +- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | +- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), +- /* STATUS2 */ +- BIT_ULL_MASK(JH7100_RST_E24) | +- /* STATUS3 */ +- 0, +-}; +- + struct jh7100_reset { + struct reset_controller_dev rcdev; + /* protect registers against concurrent read-modify-write */ + spinlock_t lock; +- void __iomem *base; ++ void __iomem *assert; ++ void __iomem *status; ++ const u64 *asserted; + }; + + static inline struct jh7100_reset * +@@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev, + struct jh7100_reset *data = jh7100_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64); +- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); +- u64 done = jh7100_reset_asserted[offset] & mask; ++ void __iomem *reg_assert = data->assert + offset * sizeof(u64); ++ void __iomem *reg_status = data->status + offset * sizeof(u64); ++ u64 done = data->asserted ? data->asserted[offset] & mask : 0; + u64 value; + unsigned long flags; + int ret; +@@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, + struct jh7100_reset *data = jh7100_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64); ++ void __iomem *reg_status = data->status + offset * sizeof(u64); + u64 value = readq(reg_status); + +- return !((value ^ jh7100_reset_asserted[offset]) & mask); ++ return !((value ^ data->asserted[offset]) & mask); + } + + static const struct reset_control_ops jh7100_reset_ops = { +@@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_ops = { + .status = jh7100_reset_status, + }; + +-int jh7100_reset_probe(struct platform_device *pdev) ++int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node, ++ void __iomem *assert, void __iomem *status, ++ const u64 *asserted, unsigned int nr_resets, ++ struct module *owner) + { + struct jh7100_reset *data; + +- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + +- data->base = devm_platform_ioremap_resource(pdev, 0); +- if (IS_ERR(data->base)) +- return PTR_ERR(data->base); +- + data->rcdev.ops = &jh7100_reset_ops; +- data->rcdev.owner = THIS_MODULE; +- data->rcdev.nr_resets = JH7100_RSTN_END; +- data->rcdev.dev = &pdev->dev; +- data->rcdev.of_node = pdev->dev.of_node; ++ data->rcdev.owner = owner; ++ data->rcdev.nr_resets = nr_resets; ++ data->rcdev.dev = dev; ++ data->rcdev.of_node = of_node; ++ + spin_lock_init(&data->lock); ++ data->assert = assert; ++ data->status = status; ++ data->asserted = asserted; + +- return devm_reset_controller_register(&pdev->dev, &data->rcdev); ++ return devm_reset_controller_register(dev, &data->rcdev); + } +-EXPORT_SYMBOL_GPL(jh7100_reset_probe); ++EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register); +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h +index 318d7a0e096a..1fc5a648c8d8 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.h ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.h +@@ -6,6 +6,9 @@ + #ifndef __RESET_STARFIVE_JH71X0_H + #define __RESET_STARFIVE_JH71X0_H + +-int jh7100_reset_probe(struct platform_device *pdev); ++int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node, ++ void __iomem *assert, void __iomem *status, ++ const u64 *asserted, unsigned int nr_resets, ++ struct module *owner); + + #endif /* __RESET_STARFIVE_JH71X0_H */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0011-reset-starfive-Rename-jh7100-to-jh71x0-for-the-commo.patch b/srcpkgs/linux6.3/patches/0011-reset-starfive-Rename-jh7100-to-jh71x0-for-the-commo.patch new file mode 100644 index 0000000000000..d4b0fe78c72fa --- /dev/null +++ b/srcpkgs/linux6.3/patches/0011-reset-starfive-Rename-jh7100-to-jh71x0-for-the-commo.patch @@ -0,0 +1,174 @@ +From 17185ea18248398b75c23379aac27f8e911f0685 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:23 +0800 +Subject: [PATCH 11/84] reset: starfive: Rename "jh7100" to "jh71x0" for the + common code + +For the common code will be shared with the StarFive JH7110 SoC. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../reset/starfive/reset-starfive-jh7100.c | 2 +- + .../reset/starfive/reset-starfive-jh71x0.c | 50 +++++++++---------- + .../reset/starfive/reset-starfive-jh71x0.h | 2 +- + 3 files changed, 27 insertions(+), 27 deletions(-) + +diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c +index 9d7cb4ed8869..5f06e5ae3346 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7100.c ++++ b/drivers/reset/starfive/reset-starfive-jh7100.c +@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) + if (IS_ERR(base)) + return PTR_ERR(base); + +- return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node, ++ return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node, + base + JH7100_RESET_ASSERT0, + base + JH7100_RESET_STATUS0, + jh7100_reset_asserted, +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c +index 3577444a89c6..a689f4730ed7 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.c ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.c +@@ -1,6 +1,6 @@ + // SPDX-License-Identifier: GPL-2.0-or-later + /* +- * Reset driver for the StarFive JH7100 SoC ++ * Reset driver for the StarFive JH71X0 SoCs + * + * Copyright (C) 2021 Emil Renner Berthing + */ +@@ -15,7 +15,7 @@ + + #include "reset-starfive-jh71x0.h" + +-struct jh7100_reset { ++struct jh71x0_reset { + struct reset_controller_dev rcdev; + /* protect registers against concurrent read-modify-write */ + spinlock_t lock; +@@ -24,16 +24,16 @@ struct jh7100_reset { + const u64 *asserted; + }; + +-static inline struct jh7100_reset * +-jh7100_reset_from(struct reset_controller_dev *rcdev) ++static inline struct jh71x0_reset * ++jh71x0_reset_from(struct reset_controller_dev *rcdev) + { +- return container_of(rcdev, struct jh7100_reset, rcdev); ++ return container_of(rcdev, struct jh71x0_reset, rcdev); + } + +-static int jh7100_reset_update(struct reset_controller_dev *rcdev, ++static int jh71x0_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) + { +- struct jh7100_reset *data = jh7100_reset_from(rcdev); ++ struct jh71x0_reset *data = jh71x0_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); + void __iomem *reg_assert = data->assert + offset * sizeof(u64); +@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev, + return ret; + } + +-static int jh7100_reset_assert(struct reset_controller_dev *rcdev, ++static int jh71x0_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) + { +- return jh7100_reset_update(rcdev, id, true); ++ return jh71x0_reset_update(rcdev, id, true); + } + +-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev, ++static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) + { +- return jh7100_reset_update(rcdev, id, false); ++ return jh71x0_reset_update(rcdev, id, false); + } + +-static int jh7100_reset_reset(struct reset_controller_dev *rcdev, ++static int jh71x0_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) + { + int ret; + +- ret = jh7100_reset_assert(rcdev, id); ++ ret = jh71x0_reset_assert(rcdev, id); + if (ret) + return ret; + +- return jh7100_reset_deassert(rcdev, id); ++ return jh71x0_reset_deassert(rcdev, id); + } + +-static int jh7100_reset_status(struct reset_controller_dev *rcdev, ++static int jh71x0_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) + { +- struct jh7100_reset *data = jh7100_reset_from(rcdev); ++ struct jh71x0_reset *data = jh71x0_reset_from(rcdev); + unsigned long offset = BIT_ULL_WORD(id); + u64 mask = BIT_ULL_MASK(id); + void __iomem *reg_status = data->status + offset * sizeof(u64); +@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev, + return !((value ^ data->asserted[offset]) & mask); + } + +-static const struct reset_control_ops jh7100_reset_ops = { +- .assert = jh7100_reset_assert, +- .deassert = jh7100_reset_deassert, +- .reset = jh7100_reset_reset, +- .status = jh7100_reset_status, ++static const struct reset_control_ops jh71x0_reset_ops = { ++ .assert = jh71x0_reset_assert, ++ .deassert = jh71x0_reset_deassert, ++ .reset = jh71x0_reset_reset, ++ .status = jh71x0_reset_status, + }; + +-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node, ++int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, + const u64 *asserted, unsigned int nr_resets, + struct module *owner) + { +- struct jh7100_reset *data; ++ struct jh71x0_reset *data; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + +- data->rcdev.ops = &jh7100_reset_ops; ++ data->rcdev.ops = &jh71x0_reset_ops; + data->rcdev.owner = owner; + data->rcdev.nr_resets = nr_resets; + data->rcdev.dev = dev; +@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_no + + return devm_reset_controller_register(dev, &data->rcdev); + } +-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register); ++EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register); +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h +index 1fc5a648c8d8..ac9e80dd3f59 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.h ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.h +@@ -6,7 +6,7 @@ + #ifndef __RESET_STARFIVE_JH71X0_H + #define __RESET_STARFIVE_JH71X0_H + +-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node, ++int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, + const u64 *asserted, unsigned int nr_resets, + struct module *owner); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0012-reset-starfive-jh71x0-Use-32bit-I-O-on-32bit-registe.patch b/srcpkgs/linux6.3/patches/0012-reset-starfive-jh71x0-Use-32bit-I-O-on-32bit-registe.patch new file mode 100644 index 0000000000000..aa6e1402f5fb2 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0012-reset-starfive-jh71x0-Use-32bit-I-O-on-32bit-registe.patch @@ -0,0 +1,153 @@ +From e6cfe6b13aebe134eeaabd29e2591313f9b2c49b Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:24 +0800 +Subject: [PATCH 12/84] reset: starfive: jh71x0: Use 32bit I/O on 32bit + registers + +We currently use 64bit I/O on the 32bit registers. This works because +there are an even number of assert and status registers, so they're only +ever accessed in pairs on 64bit boundaries. + +There are however other reset controllers for audio and video on the +JH7100 SoC with only one status register that isn't 64bit aligned so +64bit I/O results in an unaligned access exception. + +Switch to 32bit I/O in preparation for supporting these resets too. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../reset/starfive/reset-starfive-jh7100.c | 14 ++++----- + .../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++---------- + .../reset/starfive/reset-starfive-jh71x0.h | 2 +- + 3 files changed, 23 insertions(+), 24 deletions(-) + +diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c +index 5f06e5ae3346..2a56f7fd4ba7 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7100.c ++++ b/drivers/reset/starfive/reset-starfive-jh7100.c +@@ -30,16 +30,16 @@ + * lines don't though, so store the expected value of the status registers when + * all lines are asserted. + */ +-static const u64 jh7100_reset_asserted[2] = { ++static const u32 jh7100_reset_asserted[4] = { + /* STATUS0 */ +- BIT_ULL_MASK(JH7100_RST_U74) | +- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) | +- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) | ++ BIT(JH7100_RST_U74 % 32) | ++ BIT(JH7100_RST_VP6_DRESET % 32) | ++ BIT(JH7100_RST_VP6_BRESET % 32), + /* STATUS1 */ +- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) | +- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET), ++ BIT(JH7100_RST_HIFI4_DRESET % 32) | ++ BIT(JH7100_RST_HIFI4_BRESET % 32), + /* STATUS2 */ +- BIT_ULL_MASK(JH7100_RST_E24) | ++ BIT(JH7100_RST_E24 % 32), + /* STATUS3 */ + 0, + }; +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c +index a689f4730ed7..55bbbd2de52c 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.c ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.c +@@ -8,7 +8,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -21,7 +20,7 @@ struct jh71x0_reset { + spinlock_t lock; + void __iomem *assert; + void __iomem *status; +- const u64 *asserted; ++ const u32 *asserted; + }; + + static inline struct jh71x0_reset * +@@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) + { + struct jh71x0_reset *data = jh71x0_reset_from(rcdev); +- unsigned long offset = BIT_ULL_WORD(id); +- u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_assert = data->assert + offset * sizeof(u64); +- void __iomem *reg_status = data->status + offset * sizeof(u64); +- u64 done = data->asserted ? data->asserted[offset] & mask : 0; +- u64 value; ++ unsigned long offset = id / 32; ++ u32 mask = BIT(id % 32); ++ void __iomem *reg_assert = data->assert + offset * sizeof(u32); ++ void __iomem *reg_status = data->status + offset * sizeof(u32); ++ u32 done = data->asserted ? data->asserted[offset] & mask : 0; ++ u32 value; + unsigned long flags; + int ret; + +@@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, + + spin_lock_irqsave(&data->lock, flags); + +- value = readq(reg_assert); ++ value = readl(reg_assert); + if (assert) + value |= mask; + else + value &= ~mask; +- writeq(value, reg_assert); ++ writel(value, reg_assert); + + /* if the associated clock is gated, deasserting might otherwise hang forever */ +- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); ++ ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000); + + spin_unlock_irqrestore(&data->lock, flags); + return ret; +@@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) + { + struct jh71x0_reset *data = jh71x0_reset_from(rcdev); +- unsigned long offset = BIT_ULL_WORD(id); +- u64 mask = BIT_ULL_MASK(id); +- void __iomem *reg_status = data->status + offset * sizeof(u64); +- u64 value = readq(reg_status); ++ unsigned long offset = id / 32; ++ u32 mask = BIT(id % 32); ++ void __iomem *reg_status = data->status + offset * sizeof(u32); ++ u32 value = readl(reg_status); + + return !((value ^ data->asserted[offset]) & mask); + } +@@ -107,7 +106,7 @@ static const struct reset_control_ops jh71x0_reset_ops = { + + int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, +- const u64 *asserted, unsigned int nr_resets, ++ const u32 *asserted, unsigned int nr_resets, + struct module *owner) + { + struct jh71x0_reset *data; +diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h +index ac9e80dd3f59..db7d39a87f87 100644 +--- a/drivers/reset/starfive/reset-starfive-jh71x0.h ++++ b/drivers/reset/starfive/reset-starfive-jh71x0.h +@@ -8,7 +8,7 @@ + + int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, +- const u64 *asserted, unsigned int nr_resets, ++ const u32 *asserted, unsigned int nr_resets, + struct module *owner); + + #endif /* __RESET_STARFIVE_JH71X0_H */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch b/srcpkgs/linux6.3/patches/0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch new file mode 100644 index 0000000000000..03d505ce93fee --- /dev/null +++ b/srcpkgs/linux6.3/patches/0013-clk-starfive-Add-StarFive-JH7110-system-clock-driver.patch @@ -0,0 +1,567 @@ +From 7e32307e13766270ff6b492c8d59df4e2c14ad36 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:25 +0800 +Subject: [PATCH 13/84] clk: starfive: Add StarFive JH7110 system clock driver + +Add driver for the StarFive JH7110 system clock controller and +register an auxiliary device for system reset controller which +is named as "reset-sys". + +Tested-by: Tommaso Merciai +Signed-off-by: Emil Renner Berthing +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +--- + drivers/clk/starfive/Kconfig | 11 + + drivers/clk/starfive/Makefile | 2 + + .../clk/starfive/clk-starfive-jh7110-sys.c | 490 ++++++++++++++++++ + drivers/clk/starfive/clk-starfive-jh7110.h | 11 + + 4 files changed, 514 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110.h + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 3ceeb19b5eda..670c5084aeb8 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -20,3 +20,14 @@ config CLK_STARFIVE_JH7100_AUDIO + help + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. ++ ++config CLK_STARFIVE_JH7110_SYS ++ bool "StarFive JH7110 system clock support" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default ARCH_STARFIVE ++ help ++ Say yes here to support the system clock controller on the ++ StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 82edfa9f9cb8..5ca4e887fb9c 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o + + obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o + obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o ++ ++obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +new file mode 100644 +index 000000000000..5ec210644e1d +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +@@ -0,0 +1,490 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 System Clock Driver ++ * ++ * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0) ++#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1) ++#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2) ++#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3) ++#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4) ++#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5) ++#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6) ++#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7) ++#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8) ++#define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9) ++#define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10) ++#define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11) ++ ++static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { ++ /* root */ ++ JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2, ++ JH7110_SYSCLK_OSC, ++ JH7110_SYSCLK_PLL0_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT), ++ JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE), ++ JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2, ++ JH7110_SYSCLK_PLL2_OUT, ++ JH7110_SYSCLK_PLL1_OUT), ++ JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2, ++ JH7110_SYSCLK_PLL0_OUT, ++ JH7110_SYSCLK_PLL2_OUT), ++ JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2, ++ JH7110_SYSCLK_OSC, ++ JH7110_SYSCLK_PLL2_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT), ++ JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT), ++ JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0), ++ JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), ++ JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS), ++ JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT), ++ JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2, ++ JH7110_SYSCLK_MCLK_INNER, ++ JH7110_SYSCLK_MCLK_EXT), ++ JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER), ++ JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2, ++ JH7110_SYSCLK_PLL2_OUT, ++ JH7110_SYSCLK_PLL1_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X), ++ JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2), ++ JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2), ++ JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2), ++ /* cores */ ++ JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS), ++ JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS), ++ /* noc */ ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_CPU_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_AXI_CFG0), ++ /* ddr */ ++ JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC), ++ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2), ++ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4), ++ JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4, ++ JH7110_SYSCLK_OSC_DIV2, ++ JH7110_SYSCLK_PLL1_DIV2, ++ JH7110_SYSCLK_PLL1_DIV4, ++ JH7110_SYSCLK_PLL1_DIV8), ++ JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS), ++ /* gpu */ ++ JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT), ++ JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE), ++ JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE), ++ /* isp */ ++ JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X), ++ JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_ISP_AXI), ++ /* hifi4 */ ++ JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT), ++ JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE), ++ /* axi_cfg1 */ ++ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_ISP_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_AHB0), ++ /* vout */ ++ JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1), ++ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0, ++ JH7110_SYSCLK_MCLK), ++ JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, ++ JH7110_SYSCLK_OSC), ++ /* jpegc */ ++ JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI), ++ JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS), ++ /* vdec */ ++ JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT), ++ JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI), ++ JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT), ++ JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI), ++ /* venc */ ++ JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI), ++ JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI), ++ /* axi_cfg0 */ ++ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_AHB1), ++ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_AXI_CFG0), ++ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_HIFI4_AXI), ++ /* intmem */ ++ JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0), ++ /* qspi */ ++ JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1), ++ JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2, ++ JH7110_SYSCLK_OSC, ++ JH7110_SYSCLK_QSPI_REF_SRC), ++ /* sdio */ ++ JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0), ++ JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0), ++ JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), ++ JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), ++ /* stg */ ++ JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL, ++ JH7110_SYSCLK_NOCSTG_BUS), ++ /* gmac1 */ ++ JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0), ++ JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB), ++ JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, ++ JH7110_SYSCLK_GMAC1_RMII_REFIN), ++ JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), ++ JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2, ++ JH7110_SYSCLK_GMAC1_RGMII_RXIN, ++ JH7110_SYSCLK_GMAC1_RMII_RTX), ++ JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX), ++ JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, ++ JH7110_SYSCLK_GMAC1_GTXCLK, ++ JH7110_SYSCLK_GMAC1_RMII_RTX), ++ JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX), ++ JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK), ++ /* gmac0 */ ++ JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT), ++ JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), ++ JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC), ++ JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK), ++ /* apb misc */ ++ JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS), ++ /* can0 */ ++ JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC), ++ JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), ++ /* can1 */ ++ JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC), ++ JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), ++ /* pwm */ ++ JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS), ++ /* wdt */ ++ JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC), ++ /* timer */ ++ JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC), ++ /* temp sensor */ ++ JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC), ++ /* spi */ ++ JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS), ++ /* i2c */ ++ JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS), ++ JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS), ++ /* uart */ ++ JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC), ++ JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), ++ JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), ++ JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), ++ /* pwmdac */ ++ JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT), ++ /* spdif */ ++ JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK), ++ /* i2stx0 */ ++ JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), ++ JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", ++ JH7110_SYSCLK_I2STX0_BCLK_MST), ++ JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2, ++ JH7110_SYSCLK_I2STX0_BCLK_MST_INV, ++ JH7110_SYSCLK_I2STX0_BCLK_MST), ++ JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2, ++ JH7110_SYSCLK_I2STX0_BCLK_MST, ++ JH7110_SYSCLK_I2STX_BCLK_EXT), ++ JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK), ++ JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2, ++ JH7110_SYSCLK_I2STX0_LRCK_MST, ++ JH7110_SYSCLK_I2STX_LRCK_EXT), ++ /* i2stx1 */ ++ JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), ++ JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", ++ JH7110_SYSCLK_I2STX1_BCLK_MST), ++ JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2, ++ JH7110_SYSCLK_I2STX1_BCLK_MST_INV, ++ JH7110_SYSCLK_I2STX1_BCLK_MST), ++ JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2, ++ JH7110_SYSCLK_I2STX1_BCLK_MST, ++ JH7110_SYSCLK_I2STX_BCLK_EXT), ++ JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK), ++ JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2, ++ JH7110_SYSCLK_I2STX1_LRCK_MST, ++ JH7110_SYSCLK_I2STX_LRCK_EXT), ++ /* i2srx */ ++ JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), ++ JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", ++ JH7110_SYSCLK_I2SRX_BCLK_MST), ++ JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2, ++ JH7110_SYSCLK_I2SRX_BCLK_MST_INV, ++ JH7110_SYSCLK_I2SRX_BCLK_MST), ++ JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2, ++ JH7110_SYSCLK_I2SRX_BCLK_MST, ++ JH7110_SYSCLK_I2SRX_BCLK_EXT), ++ JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK), ++ JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2, ++ JH7110_SYSCLK_I2SRX_LRCK_MST, ++ JH7110_SYSCLK_I2SRX_LRCK_EXT), ++ /* pdm */ ++ JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK), ++ JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0), ++ /* tdm */ ++ JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0), ++ JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0), ++ JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK), ++ JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2, ++ JH7110_SYSCLK_TDM_INTERNAL, ++ JH7110_SYSCLK_TDM_EXT), ++ JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM), ++ /* jtag */ ++ JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, ++ JH7110_SYSCLK_OSC), ++}; ++ ++static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_SYSCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static void jh7110_reset_unregister_adev(void *_adev) ++{ ++ struct auxiliary_device *adev = _adev; ++ ++ auxiliary_device_delete(adev); ++} ++ ++static void jh7110_reset_adev_release(struct device *dev) ++{ ++ struct auxiliary_device *adev = to_auxiliary_dev(dev); ++ ++ auxiliary_device_uninit(adev); ++} ++ ++int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, ++ const char *adev_name, ++ u32 adev_id) ++{ ++ struct auxiliary_device *adev; ++ int ret; ++ ++ adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL); ++ if (!adev) ++ return -ENOMEM; ++ ++ adev->name = adev_name; ++ adev->dev.parent = priv->dev; ++ adev->dev.release = jh7110_reset_adev_release; ++ adev->id = adev_id; ++ ++ ret = auxiliary_device_init(adev); ++ if (ret) ++ return ret; ++ ++ ret = auxiliary_device_add(adev); ++ if (ret) { ++ auxiliary_device_uninit(adev); ++ return ret; ++ } ++ ++ return devm_add_action_or_reset(priv->dev, ++ jh7110_reset_unregister_adev, adev); ++} ++EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); ++ ++static int __init jh7110_syscrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_SYSCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ dev_set_drvdata(priv->dev, (void *)(&priv->base)); ++ ++ /* ++ * These PLL clocks are not actually fixed factor clocks and can be ++ * controlled by the syscon registers of JH7110. They will be dropped ++ * and registered in the PLL clock driver instead. ++ */ ++ /* 24MHz -> 1000.0MHz */ ++ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", ++ "osc", 0, 125, 3); ++ if (IS_ERR(priv->pll[0])) ++ return PTR_ERR(priv->pll[0]); ++ ++ /* 24MHz -> 1066.0MHz */ ++ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", ++ "osc", 0, 533, 12); ++ if (IS_ERR(priv->pll[1])) ++ return PTR_ERR(priv->pll[1]); ++ ++ /* 24MHz -> 1188.0MHz */ ++ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", ++ "osc", 0, 99, 2); ++ if (IS_ERR(priv->pll[2])) ++ return PTR_ERR(priv->pll[2]); ++ ++ for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { ++ u32 max = jh7110_sysclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_sysclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_sysclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_SYSCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx == JH7110_SYSCLK_OSC) ++ parents[i].fw_name = "osc"; ++ else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN) ++ parents[i].fw_name = "gmac1_rmii_refin"; ++ else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN) ++ parents[i].fw_name = "gmac1_rgmii_rxin"; ++ else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT) ++ parents[i].fw_name = "i2stx_bclk_ext"; ++ else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT) ++ parents[i].fw_name = "i2stx_lrck_ext"; ++ else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT) ++ parents[i].fw_name = "i2srx_bclk_ext"; ++ else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT) ++ parents[i].fw_name = "i2srx_lrck_ext"; ++ else if (pidx == JH7110_SYSCLK_TDM_EXT) ++ parents[i].fw_name = "tdm_ext"; ++ else if (pidx == JH7110_SYSCLK_MCLK_EXT) ++ parents[i].fw_name = "mclk_ext"; ++ else ++ parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ return ret; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv); ++ if (ret) ++ return ret; ++ ++ return jh7110_reset_controller_register(priv, "rst-sys", 0); ++} ++ ++static const struct of_device_id jh7110_syscrg_match[] = { ++ { .compatible = "starfive,jh7110-syscrg" }, ++ { /* sentinel */ } ++}; ++ ++static struct platform_driver jh7110_syscrg_driver = { ++ .driver = { ++ .name = "clk-starfive-jh7110-sys", ++ .of_match_table = jh7110_syscrg_match, ++ .suppress_bind_attrs = true, ++ }, ++}; ++builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe); +diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h +new file mode 100644 +index 000000000000..f29682b8d400 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110.h +@@ -0,0 +1,11 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __CLK_STARFIVE_JH7110_H ++#define __CLK_STARFIVE_JH7110_H ++ ++#include "clk-starfive-jh71x0.h" ++ ++int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, ++ const char *adev_name, ++ u32 adev_id); ++ ++#endif +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0014-clk-starfive-Add-StarFive-JH7110-always-on-clock-dri.patch b/srcpkgs/linux6.3/patches/0014-clk-starfive-Add-StarFive-JH7110-always-on-clock-dri.patch new file mode 100644 index 0000000000000..6598a3f1c5ecc --- /dev/null +++ b/srcpkgs/linux6.3/patches/0014-clk-starfive-Add-StarFive-JH7110-always-on-clock-dri.patch @@ -0,0 +1,214 @@ +From 616aee39ed0a5d706542f740dd32c52d6a1b39aa Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:26 +0800 +Subject: [PATCH 14/84] clk: starfive: Add StarFive JH7110 always-on clock + driver + +Add driver for the StarFive JH7110 always-on clock controller +and register an auxiliary device for always-on reset controller +which is named as "reset-aon". + +Tested-by: Tommaso Merciai +Signed-off-by: Emil Renner Berthing +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +--- + drivers/clk/starfive/Kconfig | 11 ++ + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++ + 3 files changed, 168 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 670c5084aeb8..71c1148ee5f6 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS + help + Say yes here to support the system clock controller on the + StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_AON ++ tristate "StarFive JH7110 always-on clock support" ++ depends on CLK_STARFIVE_JH7110_SYS ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the always-on clock controller on the ++ StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 5ca4e887fb9c..f3df7d957b1e 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o + obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c +new file mode 100644 +index 000000000000..a2799fe8a234 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c +@@ -0,0 +1,156 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 Always-On Clock Driver ++ * ++ * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0) ++#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 1) ++#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 2) ++#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 3) ++#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 4) ++#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5) ++#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6) ++ ++static const struct jh71x0_clk_data jh7110_aonclk_data[] = { ++ /* source */ ++ JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC), ++ JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2, ++ JH7110_AONCLK_OSC_DIV4, ++ JH7110_AONCLK_OSC), ++ /* gmac0 */ ++ JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB), ++ JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30, ++ JH7110_AONCLK_GMAC0_RMII_REFIN), ++ JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", ++ CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, ++ JH7110_AONCLK_GMAC0_GTXCLK, ++ JH7110_AONCLK_GMAC0_RMII_RTX), ++ JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX), ++ JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2, ++ JH7110_AONCLK_GMAC0_RGMII_RXIN, ++ JH7110_AONCLK_GMAC0_RMII_RTX), ++ JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX), ++ /* otpc */ ++ JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS), ++ /* rtc */ ++ JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS), ++ JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC), ++ JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2, ++ JH7110_AONCLK_RTC_OSC, ++ JH7110_AONCLK_RTC_INTERNAL), ++ JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC), ++}; ++ ++static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_AONCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int jh7110_aoncrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_AONCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ dev_set_drvdata(priv->dev, (void *)(&priv->base)); ++ ++ for (idx = 0; idx < JH7110_AONCLK_END; idx++) { ++ u32 max = jh7110_aonclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_aonclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_aonclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_aonclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_AONCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx == JH7110_AONCLK_OSC) ++ parents[i].fw_name = "osc"; ++ else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN) ++ parents[i].fw_name = "gmac0_rmii_refin"; ++ else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN) ++ parents[i].fw_name = "gmac0_rgmii_rxin"; ++ else if (pidx == JH7110_AONCLK_STG_AXIAHB) ++ parents[i].fw_name = "stg_axiahb"; ++ else if (pidx == JH7110_AONCLK_APB_BUS) ++ parents[i].fw_name = "apb_bus"; ++ else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK) ++ parents[i].fw_name = "gmac0_gtxclk"; ++ else if (pidx == JH7110_AONCLK_RTC_OSC) ++ parents[i].fw_name = "rtc_osc"; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ return ret; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv); ++ if (ret) ++ return ret; ++ ++ return jh7110_reset_controller_register(priv, "rst-aon", 1); ++} ++ ++static const struct of_device_id jh7110_aoncrg_match[] = { ++ { .compatible = "starfive,jh7110-aoncrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match); ++ ++static struct platform_driver jh7110_aoncrg_driver = { ++ .probe = jh7110_aoncrg_probe, ++ .driver = { ++ .name = "clk-starfive-jh7110-aon", ++ .of_match_table = jh7110_aoncrg_match, ++ }, ++}; ++module_platform_driver(jh7110_aoncrg_driver); ++ ++MODULE_AUTHOR("Emil Renner Berthing"); ++MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0015-reset-starfive-Add-StarFive-JH7110-reset-driver.patch b/srcpkgs/linux6.3/patches/0015-reset-starfive-Add-StarFive-JH7110-reset-driver.patch new file mode 100644 index 0000000000000..cad599502849d --- /dev/null +++ b/srcpkgs/linux6.3/patches/0015-reset-starfive-Add-StarFive-JH7110-reset-driver.patch @@ -0,0 +1,121 @@ +From 85cff48889e5eed59ca4353c123377294c38da20 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sat, 1 Apr 2023 19:19:27 +0800 +Subject: [PATCH 15/84] reset: starfive: Add StarFive JH7110 reset driver + +Add auxiliary driver to support StarFive JH7110 system +and always-on resets. + +Tested-by: Tommaso Merciai +Signed-off-by: Hal Feng +--- + drivers/reset/starfive/Kconfig | 8 +++ + drivers/reset/starfive/Makefile | 1 + + .../reset/starfive/reset-starfive-jh7110.c | 70 +++++++++++++++++++ + 3 files changed, 79 insertions(+) + create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c + +diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig +index 1927a5a3b53a..1fa706a2c3dc 100644 +--- a/drivers/reset/starfive/Kconfig ++++ b/drivers/reset/starfive/Kconfig +@@ -10,3 +10,11 @@ config RESET_STARFIVE_JH7100 + default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JH7100 SoC. ++ ++config RESET_STARFIVE_JH7110 ++ bool "StarFive JH7110 Reset Driver" ++ depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS ++ select RESET_STARFIVE_JH71X0 ++ default ARCH_STARFIVE ++ help ++ This enables the reset controller driver for the StarFive JH7110 SoC. +diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile +index f6aa12466fad..7a44b66fb9d5 100644 +--- a/drivers/reset/starfive/Makefile ++++ b/drivers/reset/starfive/Makefile +@@ -2,3 +2,4 @@ + obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o + + obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o ++obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o +diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c +new file mode 100644 +index 000000000000..c1b3a490d951 +--- /dev/null ++++ b/drivers/reset/starfive/reset-starfive-jh7110.c +@@ -0,0 +1,70 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Reset driver for the StarFive JH7110 SoC ++ * ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++ ++#include "reset-starfive-jh71x0.h" ++ ++#include ++ ++struct jh7110_reset_info { ++ unsigned int nr_resets; ++ unsigned int assert_offset; ++ unsigned int status_offset; ++}; ++ ++static const struct jh7110_reset_info jh7110_sys_info = { ++ .nr_resets = JH7110_SYSRST_END, ++ .assert_offset = 0x2F8, ++ .status_offset = 0x308, ++}; ++ ++static const struct jh7110_reset_info jh7110_aon_info = { ++ .nr_resets = JH7110_AONRST_END, ++ .assert_offset = 0x38, ++ .status_offset = 0x3C, ++}; ++ ++static int jh7110_reset_probe(struct auxiliary_device *adev, ++ const struct auxiliary_device_id *id) ++{ ++ struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data); ++ void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent); ++ ++ if (!info || !base) ++ return -ENODEV; ++ ++ return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node, ++ *base + info->assert_offset, ++ *base + info->status_offset, ++ NULL, ++ info->nr_resets, ++ NULL); ++} ++ ++static const struct auxiliary_device_id jh7110_reset_ids[] = { ++ { ++ .name = "clk_starfive_jh7110_sys.rst-sys", ++ .driver_data = (kernel_ulong_t)&jh7110_sys_info, ++ }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-aon", ++ .driver_data = (kernel_ulong_t)&jh7110_aon_info, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids); ++ ++static struct auxiliary_driver jh7110_reset_driver = { ++ .probe = jh7110_reset_probe, ++ .id_table = jh7110_reset_ids, ++}; ++module_auxiliary_driver(jh7110_reset_driver); ++ ++MODULE_AUTHOR("Hal Feng "); ++MODULE_DESCRIPTION("StarFive JH7110 reset driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0016-dt-bindings-timer-Add-StarFive-JH7110-clint.patch b/srcpkgs/linux6.3/patches/0016-dt-bindings-timer-Add-StarFive-JH7110-clint.patch new file mode 100644 index 0000000000000..8e6ab66afe910 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0016-dt-bindings-timer-Add-StarFive-JH7110-clint.patch @@ -0,0 +1,30 @@ +From ca665d396b71255e894692828fe9c39ae172b333 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:28 +0800 +Subject: [PATCH 16/84] dt-bindings: timer: Add StarFive JH7110 clint + +Add compatible string for the StarFive JH7110 clint. + +Reviewed-by: Conor Dooley +Acked-by: Krzysztof Kozlowski +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +index aada6957216c..94bef9424df1 100644 +--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml ++++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml +@@ -31,6 +31,7 @@ properties: + - enum: + - sifive,fu540-c000-clint + - starfive,jh7100-clint ++ - starfive,jh7110-clint + - canaan,k210-clint + - const: sifive,clint0 + - items: +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0017-dt-bindings-interrupt-controller-Add-StarFive-JH7110.patch b/srcpkgs/linux6.3/patches/0017-dt-bindings-interrupt-controller-Add-StarFive-JH7110.patch new file mode 100644 index 0000000000000..87d69cdb13dba --- /dev/null +++ b/srcpkgs/linux6.3/patches/0017-dt-bindings-interrupt-controller-Add-StarFive-JH7110.patch @@ -0,0 +1,31 @@ +From 20a0e2a9baa8eaa47b090e5764eb56dc3d6a11e8 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:29 +0800 +Subject: [PATCH 17/84] dt-bindings: interrupt-controller: Add StarFive JH7110 + plic + +Add compatible string for StarFive JH7110 plic. + +Reviewed-by: Conor Dooley +Acked-by: Krzysztof Kozlowski +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +--- + .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +index 63bc89e13480..4e98261f2948 100644 +--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml ++++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +@@ -59,6 +59,7 @@ properties: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic ++ - starfive,jh7110-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0018-dt-bindings-riscv-Add-SiFive-S7-compatible.patch b/srcpkgs/linux6.3/patches/0018-dt-bindings-riscv-Add-SiFive-S7-compatible.patch new file mode 100644 index 0000000000000..6cd968e1f6100 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0018-dt-bindings-riscv-Add-SiFive-S7-compatible.patch @@ -0,0 +1,30 @@ +From 06c6baba348cd9c96614070d16d95aa86a6d6593 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sat, 1 Apr 2023 19:19:30 +0800 +Subject: [PATCH 18/84] dt-bindings: riscv: Add SiFive S7 compatible + +Add a new compatible string in cpu.yaml for SiFive S7 CPU +core which is used on SiFive U74-MC core complex etc. + +Reviewed-by: Conor Dooley +Acked-by: Krzysztof Kozlowski +Signed-off-by: Hal Feng +--- + Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml +index 001931d526ec..14b5b7ea0ce0 100644 +--- a/Documentation/devicetree/bindings/riscv/cpus.yaml ++++ b/Documentation/devicetree/bindings/riscv/cpus.yaml +@@ -35,6 +35,7 @@ properties: + - sifive,e7 + - sifive,e71 + - sifive,rocket0 ++ - sifive,s7 + - sifive,u5 + - sifive,u54 + - sifive,u7 +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0019-riscv-dts-starfive-Add-initial-StarFive-JH7110-devic.patch b/srcpkgs/linux6.3/patches/0019-riscv-dts-starfive-Add-initial-StarFive-JH7110-devic.patch new file mode 100644 index 0000000000000..f0e98d5ab2cdf --- /dev/null +++ b/srcpkgs/linux6.3/patches/0019-riscv-dts-starfive-Add-initial-StarFive-JH7110-devic.patch @@ -0,0 +1,539 @@ +From 51f991e05eb874225417cb3b5a2b1ddddc70e170 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:31 +0800 +Subject: [PATCH 19/84] riscv: dts: starfive: Add initial StarFive JH7110 + device tree + +Add initial device tree for the JH7110 RISC-V SoC by StarFive +Technology Ltd. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Co-developed-by: Jianlong Huang +Signed-off-by: Jianlong Huang +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 509 +++++++++++++++++++++++ + 1 file changed, 509 insertions(+) + create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +new file mode 100644 +index 000000000000..d484ecdf93f7 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -0,0 +1,509 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022 Emil Renner Berthing ++ */ ++ ++/dts-v1/; ++#include ++#include ++ ++/ { ++ compatible = "starfive,jh7110"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ S7_0: cpu@0 { ++ compatible = "sifive,s7", "riscv"; ++ reg = <0>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <8192>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <16384>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ riscv,isa = "rv64imac_zba_zbb"; ++ tlb-split; ++ status = "disabled"; ++ ++ cpu0_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ U74_1: cpu@1 { ++ compatible = "sifive,u74-mc", "riscv"; ++ reg = <1>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ riscv,isa = "rv64imafdc_zba_zbb"; ++ tlb-split; ++ ++ cpu1_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ U74_2: cpu@2 { ++ compatible = "sifive,u74-mc", "riscv"; ++ reg = <2>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ riscv,isa = "rv64imafdc_zba_zbb"; ++ tlb-split; ++ ++ cpu2_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ U74_3: cpu@3 { ++ compatible = "sifive,u74-mc", "riscv"; ++ reg = <3>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ riscv,isa = "rv64imafdc_zba_zbb"; ++ tlb-split; ++ ++ cpu3_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ U74_4: cpu@4 { ++ compatible = "sifive,u74-mc", "riscv"; ++ reg = <4>; ++ d-cache-block-size = <64>; ++ d-cache-sets = <64>; ++ d-cache-size = <32768>; ++ d-tlb-sets = <1>; ++ d-tlb-size = <40>; ++ device_type = "cpu"; ++ i-cache-block-size = <64>; ++ i-cache-sets = <64>; ++ i-cache-size = <32768>; ++ i-tlb-sets = <1>; ++ i-tlb-size = <40>; ++ mmu-type = "riscv,sv39"; ++ next-level-cache = <&ccache>; ++ riscv,isa = "rv64imafdc_zba_zbb"; ++ tlb-split; ++ ++ cpu4_intc: interrupt-controller { ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ }; ++ ++ cpu-map { ++ cluster0 { ++ core0 { ++ cpu = <&S7_0>; ++ }; ++ ++ core1 { ++ cpu = <&U74_1>; ++ }; ++ ++ core2 { ++ cpu = <&U74_2>; ++ }; ++ ++ core3 { ++ cpu = <&U74_3>; ++ }; ++ ++ core4 { ++ cpu = <&U74_4>; ++ }; ++ }; ++ }; ++ }; ++ ++ gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "gmac0_rgmii_rxin"; ++ #clock-cells = <0>; ++ }; ++ ++ gmac0_rmii_refin: gmac0-rmii-refin-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "gmac0_rmii_refin"; ++ #clock-cells = <0>; ++ }; ++ ++ gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "gmac1_rgmii_rxin"; ++ #clock-cells = <0>; ++ }; ++ ++ gmac1_rmii_refin: gmac1-rmii-refin-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "gmac1_rmii_refin"; ++ #clock-cells = <0>; ++ }; ++ ++ i2srx_bclk_ext: i2srx-bclk-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "i2srx_bclk_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ i2srx_lrck_ext: i2srx-lrck-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "i2srx_lrck_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ i2stx_bclk_ext: i2stx-bclk-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "i2stx_bclk_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ i2stx_lrck_ext: i2stx-lrck-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "i2stx_lrck_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ mclk_ext: mclk-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "mclk_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ osc: oscillator { ++ compatible = "fixed-clock"; ++ clock-output-names = "osc"; ++ #clock-cells = <0>; ++ }; ++ ++ rtc_osc: rtc-oscillator { ++ compatible = "fixed-clock"; ++ clock-output-names = "rtc_osc"; ++ #clock-cells = <0>; ++ }; ++ ++ tdm_ext: tdm-ext-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "tdm_ext"; ++ #clock-cells = <0>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&plic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ clint: timer@2000000 { ++ compatible = "starfive,jh7110-clint", "sifive,clint0"; ++ reg = <0x0 0x2000000 0x0 0x10000>; ++ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, ++ <&cpu1_intc 3>, <&cpu1_intc 7>, ++ <&cpu2_intc 3>, <&cpu2_intc 7>, ++ <&cpu3_intc 3>, <&cpu3_intc 7>, ++ <&cpu4_intc 3>, <&cpu4_intc 7>; ++ }; ++ ++ ccache: cache-controller@2010000 { ++ compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; ++ reg = <0x0 0x2010000 0x0 0x4000>; ++ interrupts = <1>, <3>, <4>, <2>; ++ cache-block-size = <64>; ++ cache-level = <2>; ++ cache-sets = <2048>; ++ cache-size = <2097152>; ++ cache-unified; ++ }; ++ ++ plic: interrupt-controller@c000000 { ++ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; ++ reg = <0x0 0xc000000 0x0 0x4000000>; ++ interrupts-extended = <&cpu0_intc 11>, ++ <&cpu1_intc 11>, <&cpu1_intc 9>, ++ <&cpu2_intc 11>, <&cpu2_intc 9>, ++ <&cpu3_intc 11>, <&cpu3_intc 9>, ++ <&cpu4_intc 11>, <&cpu4_intc 9>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ #address-cells = <0>; ++ riscv,ndev = <136>; ++ }; ++ ++ uart0: serial@10000000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x10000000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, ++ <&syscrg JH7110_SYSCLK_UART0_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART0_APB>; ++ interrupts = <32>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart1: serial@10010000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x10010000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, ++ <&syscrg JH7110_SYSCLK_UART1_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART1_APB>; ++ interrupts = <33>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@10020000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x10020000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, ++ <&syscrg JH7110_SYSCLK_UART2_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART2_APB>; ++ interrupts = <34>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@10030000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x10030000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C0_APB>; ++ interrupts = <35>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@10040000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x10040000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C1_APB>; ++ interrupts = <36>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@10050000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x10050000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C2_APB>; ++ interrupts = <37>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ uart3: serial@12000000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x12000000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, ++ <&syscrg JH7110_SYSCLK_UART3_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART3_APB>; ++ interrupts = <45>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@12010000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x12010000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, ++ <&syscrg JH7110_SYSCLK_UART4_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART4_APB>; ++ interrupts = <46>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@12020000 { ++ compatible = "snps,dw-apb-uart"; ++ reg = <0x0 0x12020000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, ++ <&syscrg JH7110_SYSCLK_UART5_APB>; ++ clock-names = "baudclk", "apb_pclk"; ++ resets = <&syscrg JH7110_SYSRST_UART5_APB>; ++ interrupts = <47>; ++ reg-io-width = <4>; ++ reg-shift = <2>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@12030000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12030000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C3_APB>; ++ interrupts = <48>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@12040000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12040000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C4_APB>; ++ interrupts = <49>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@12050000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12050000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C5_APB>; ++ interrupts = <50>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c6: i2c@12060000 { ++ compatible = "snps,designware-i2c"; ++ reg = <0x0 0x12060000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; ++ clock-names = "ref"; ++ resets = <&syscrg JH7110_SYSRST_I2C6_APB>; ++ interrupts = <51>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ syscrg: clock-controller@13020000 { ++ compatible = "starfive,jh7110-syscrg"; ++ reg = <0x0 0x13020000 0x0 0x10000>; ++ clocks = <&osc>, <&gmac1_rmii_refin>, ++ <&gmac1_rgmii_rxin>, ++ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, ++ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, ++ <&tdm_ext>, <&mclk_ext>; ++ clock-names = "osc", "gmac1_rmii_refin", ++ "gmac1_rgmii_rxin", ++ "i2stx_bclk_ext", "i2stx_lrck_ext", ++ "i2srx_bclk_ext", "i2srx_lrck_ext", ++ "tdm_ext", "mclk_ext"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ sysgpio: pinctrl@13040000 { ++ compatible = "starfive,jh7110-sys-pinctrl"; ++ reg = <0x0 0x13040000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; ++ resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; ++ interrupts = <86>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ aoncrg: clock-controller@17000000 { ++ compatible = "starfive,jh7110-aoncrg"; ++ reg = <0x0 0x17000000 0x0 0x10000>; ++ clocks = <&osc>, <&gmac0_rmii_refin>, ++ <&gmac0_rgmii_rxin>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>, ++ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, ++ <&rtc_osc>; ++ clock-names = "osc", "gmac0_rmii_refin", ++ "gmac0_rgmii_rxin", "stg_axiahb", ++ "apb_bus", "gmac0_gtxclk", ++ "rtc_osc"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ aongpio: pinctrl@17020000 { ++ compatible = "starfive,jh7110-aon-pinctrl"; ++ reg = <0x0 0x17020000 0x0 0x10000>; ++ resets = <&aoncrg JH7110_AONRST_IOMUX>; ++ interrupts = <85>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ }; ++}; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0020-riscv-dts-starfive-Add-StarFive-JH7110-pin-function-.patch b/srcpkgs/linux6.3/patches/0020-riscv-dts-starfive-Add-StarFive-JH7110-pin-function-.patch new file mode 100644 index 0000000000000..24ab9235deb8c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0020-riscv-dts-starfive-Add-StarFive-JH7110-pin-function-.patch @@ -0,0 +1,335 @@ +From 32aa3ce02cd5ae74880ab57e1bfbad25daa07afd Mon Sep 17 00:00:00 2001 +From: Jianlong Huang +Date: Sat, 1 Apr 2023 19:19:32 +0800 +Subject: [PATCH 20/84] riscv: dts: starfive: Add StarFive JH7110 pin function + definitions + +Add pin function definitions for StarFive JH7110 SoC. + +Tested-by: Tommaso Merciai +Co-developed-by: Emil Renner Berthing +Signed-off-by: Emil Renner Berthing +Signed-off-by: Jianlong Huang +Signed-off-by: Hal Feng +--- + arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++++++++++++ + 1 file changed, 308 insertions(+) + create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h +new file mode 100644 +index 000000000000..fb0139b56723 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h +@@ -0,0 +1,308 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef __JH7110_PINFUNC_H__ ++#define __JH7110_PINFUNC_H__ ++ ++/* ++ * mux bits: ++ * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | ++ * | din | dout | doen | function | gpio nr | ++ * ++ * dout: output signal ++ * doen: output enable signal ++ * din: optional input signal, 0xff = none ++ * function: function selector ++ * gpio nr: gpio number, 0 - 63 ++ */ ++#define GPIOMUX(n, dout, doen, din) ( \ ++ (((din) & 0xff) << 24) | \ ++ (((dout) & 0xff) << 16) | \ ++ (((doen) & 0x3f) << 10) | \ ++ ((n) & 0x3f)) ++ ++#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) ++ ++/* sys_iomux dout */ ++#define GPOUT_LOW 0 ++#define GPOUT_HIGH 1 ++#define GPOUT_SYS_WAVE511_UART_TX 2 ++#define GPOUT_SYS_CAN0_STBY 3 ++#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 ++#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 ++#define GPOUT_SYS_CAN0_TXD 6 ++#define GPOUT_SYS_USB_DRIVE_VBUS 7 ++#define GPOUT_SYS_QSPI_CS1 8 ++#define GPOUT_SYS_SPDIF 9 ++#define GPOUT_SYS_HDMI_CEC_SDA 10 ++#define GPOUT_SYS_HDMI_DDC_SCL 11 ++#define GPOUT_SYS_HDMI_DDC_SDA 12 ++#define GPOUT_SYS_WATCHDOG 13 ++#define GPOUT_SYS_I2C0_CLK 14 ++#define GPOUT_SYS_I2C0_DATA 15 ++#define GPOUT_SYS_SDIO0_BACK_END_POWER 16 ++#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 ++#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 ++#define GPOUT_SYS_SDIO0_RST 19 ++#define GPOUT_SYS_UART0_TX 20 ++#define GPOUT_SYS_HIFI4_JTAG_TDO 21 ++#define GPOUT_SYS_JTAG_TDO 22 ++#define GPOUT_SYS_PDM_MCLK 23 ++#define GPOUT_SYS_PWM_CHANNEL0 24 ++#define GPOUT_SYS_PWM_CHANNEL1 25 ++#define GPOUT_SYS_PWM_CHANNEL2 26 ++#define GPOUT_SYS_PWM_CHANNEL3 27 ++#define GPOUT_SYS_PWMDAC_LEFT 28 ++#define GPOUT_SYS_PWMDAC_RIGHT 29 ++#define GPOUT_SYS_SPI0_CLK 30 ++#define GPOUT_SYS_SPI0_FSS 31 ++#define GPOUT_SYS_SPI0_TXD 32 ++#define GPOUT_SYS_GMAC_PHYCLK 33 ++#define GPOUT_SYS_I2SRX_BCLK 34 ++#define GPOUT_SYS_I2SRX_LRCK 35 ++#define GPOUT_SYS_I2STX0_BCLK 36 ++#define GPOUT_SYS_I2STX0_LRCK 37 ++#define GPOUT_SYS_MCLK 38 ++#define GPOUT_SYS_TDM_CLK 39 ++#define GPOUT_SYS_TDM_SYNC 40 ++#define GPOUT_SYS_TDM_TXD 41 ++#define GPOUT_SYS_TRACE_DATA0 42 ++#define GPOUT_SYS_TRACE_DATA1 43 ++#define GPOUT_SYS_TRACE_DATA2 44 ++#define GPOUT_SYS_TRACE_DATA3 45 ++#define GPOUT_SYS_TRACE_REF 46 ++#define GPOUT_SYS_CAN1_STBY 47 ++#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 ++#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 ++#define GPOUT_SYS_CAN1_TXD 50 ++#define GPOUT_SYS_I2C1_CLK 51 ++#define GPOUT_SYS_I2C1_DATA 52 ++#define GPOUT_SYS_SDIO1_BACK_END_POWER 53 ++#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 ++#define GPOUT_SYS_SDIO1_CLK 55 ++#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 ++#define GPOUT_SYS_SDIO1_CMD 57 ++#define GPOUT_SYS_SDIO1_DATA0 58 ++#define GPOUT_SYS_SDIO1_DATA1 59 ++#define GPOUT_SYS_SDIO1_DATA2 60 ++#define GPOUT_SYS_SDIO1_DATA3 61 ++#define GPOUT_SYS_SDIO1_DATA4 63 ++#define GPOUT_SYS_SDIO1_DATA5 63 ++#define GPOUT_SYS_SDIO1_DATA6 64 ++#define GPOUT_SYS_SDIO1_DATA7 65 ++#define GPOUT_SYS_SDIO1_RST 66 ++#define GPOUT_SYS_UART1_RTS 67 ++#define GPOUT_SYS_UART1_TX 68 ++#define GPOUT_SYS_I2STX1_SDO0 69 ++#define GPOUT_SYS_I2STX1_SDO1 70 ++#define GPOUT_SYS_I2STX1_SDO2 71 ++#define GPOUT_SYS_I2STX1_SDO3 72 ++#define GPOUT_SYS_SPI1_CLK 73 ++#define GPOUT_SYS_SPI1_FSS 74 ++#define GPOUT_SYS_SPI1_TXD 75 ++#define GPOUT_SYS_I2C2_CLK 76 ++#define GPOUT_SYS_I2C2_DATA 77 ++#define GPOUT_SYS_UART2_RTS 78 ++#define GPOUT_SYS_UART2_TX 79 ++#define GPOUT_SYS_SPI2_CLK 80 ++#define GPOUT_SYS_SPI2_FSS 81 ++#define GPOUT_SYS_SPI2_TXD 82 ++#define GPOUT_SYS_I2C3_CLK 83 ++#define GPOUT_SYS_I2C3_DATA 84 ++#define GPOUT_SYS_UART3_TX 85 ++#define GPOUT_SYS_SPI3_CLK 86 ++#define GPOUT_SYS_SPI3_FSS 87 ++#define GPOUT_SYS_SPI3_TXD 88 ++#define GPOUT_SYS_I2C4_CLK 89 ++#define GPOUT_SYS_I2C4_DATA 90 ++#define GPOUT_SYS_UART4_RTS 91 ++#define GPOUT_SYS_UART4_TX 92 ++#define GPOUT_SYS_SPI4_CLK 93 ++#define GPOUT_SYS_SPI4_FSS 94 ++#define GPOUT_SYS_SPI4_TXD 95 ++#define GPOUT_SYS_I2C5_CLK 96 ++#define GPOUT_SYS_I2C5_DATA 97 ++#define GPOUT_SYS_UART5_RTS 98 ++#define GPOUT_SYS_UART5_TX 99 ++#define GPOUT_SYS_SPI5_CLK 100 ++#define GPOUT_SYS_SPI5_FSS 101 ++#define GPOUT_SYS_SPI5_TXD 102 ++#define GPOUT_SYS_I2C6_CLK 103 ++#define GPOUT_SYS_I2C6_DATA 104 ++#define GPOUT_SYS_SPI6_CLK 105 ++#define GPOUT_SYS_SPI6_FSS 106 ++#define GPOUT_SYS_SPI6_TXD 107 ++ ++/* aon_iomux dout */ ++#define GPOUT_AON_CLK_32K_OUT 2 ++#define GPOUT_AON_PTC0_PWM4 3 ++#define GPOUT_AON_PTC0_PWM5 4 ++#define GPOUT_AON_PTC0_PWM6 5 ++#define GPOUT_AON_PTC0_PWM7 6 ++#define GPOUT_AON_CLK_GCLK0 7 ++#define GPOUT_AON_CLK_GCLK1 8 ++#define GPOUT_AON_CLK_GCLK2 9 ++ ++/* sys_iomux doen */ ++#define GPOEN_ENABLE 0 ++#define GPOEN_DISABLE 1 ++#define GPOEN_SYS_HDMI_CEC_SDA 2 ++#define GPOEN_SYS_HDMI_DDC_SCL 3 ++#define GPOEN_SYS_HDMI_DDC_SDA 4 ++#define GPOEN_SYS_I2C0_CLK 5 ++#define GPOEN_SYS_I2C0_DATA 6 ++#define GPOEN_SYS_HIFI4_JTAG_TDO 7 ++#define GPOEN_SYS_JTAG_TDO 8 ++#define GPOEN_SYS_PWM0_CHANNEL0 9 ++#define GPOEN_SYS_PWM0_CHANNEL1 10 ++#define GPOEN_SYS_PWM0_CHANNEL2 11 ++#define GPOEN_SYS_PWM0_CHANNEL3 12 ++#define GPOEN_SYS_SPI0_NSSPCTL 13 ++#define GPOEN_SYS_SPI0_NSSP 14 ++#define GPOEN_SYS_TDM_SYNC 15 ++#define GPOEN_SYS_TDM_TXD 16 ++#define GPOEN_SYS_I2C1_CLK 17 ++#define GPOEN_SYS_I2C1_DATA 18 ++#define GPOEN_SYS_SDIO1_CMD 19 ++#define GPOEN_SYS_SDIO1_DATA0 20 ++#define GPOEN_SYS_SDIO1_DATA1 21 ++#define GPOEN_SYS_SDIO1_DATA2 22 ++#define GPOEN_SYS_SDIO1_DATA3 23 ++#define GPOEN_SYS_SDIO1_DATA4 24 ++#define GPOEN_SYS_SDIO1_DATA5 25 ++#define GPOEN_SYS_SDIO1_DATA6 26 ++#define GPOEN_SYS_SDIO1_DATA7 27 ++#define GPOEN_SYS_SPI1_NSSPCTL 28 ++#define GPOEN_SYS_SPI1_NSSP 29 ++#define GPOEN_SYS_I2C2_CLK 30 ++#define GPOEN_SYS_I2C2_DATA 31 ++#define GPOEN_SYS_SPI2_NSSPCTL 32 ++#define GPOEN_SYS_SPI2_NSSP 33 ++#define GPOEN_SYS_I2C3_CLK 34 ++#define GPOEN_SYS_I2C3_DATA 35 ++#define GPOEN_SYS_SPI3_NSSPCTL 36 ++#define GPOEN_SYS_SPI3_NSSP 37 ++#define GPOEN_SYS_I2C4_CLK 38 ++#define GPOEN_SYS_I2C4_DATA 39 ++#define GPOEN_SYS_SPI4_NSSPCTL 40 ++#define GPOEN_SYS_SPI4_NSSP 41 ++#define GPOEN_SYS_I2C5_CLK 42 ++#define GPOEN_SYS_I2C5_DATA 43 ++#define GPOEN_SYS_SPI5_NSSPCTL 44 ++#define GPOEN_SYS_SPI5_NSSP 45 ++#define GPOEN_SYS_I2C6_CLK 46 ++#define GPOEN_SYS_I2C6_DATA 47 ++#define GPOEN_SYS_SPI6_NSSPCTL 48 ++#define GPOEN_SYS_SPI6_NSSP 49 ++ ++/* aon_iomux doen */ ++#define GPOEN_AON_PTC0_OE_N_4 2 ++#define GPOEN_AON_PTC0_OE_N_5 3 ++#define GPOEN_AON_PTC0_OE_N_6 4 ++#define GPOEN_AON_PTC0_OE_N_7 5 ++ ++/* sys_iomux gin */ ++#define GPI_NONE 255 ++ ++#define GPI_SYS_WAVE511_UART_RX 0 ++#define GPI_SYS_CAN0_RXD 1 ++#define GPI_SYS_USB_OVERCURRENT 2 ++#define GPI_SYS_SPDIF 3 ++#define GPI_SYS_JTAG_RST 4 ++#define GPI_SYS_HDMI_CEC_SDA 5 ++#define GPI_SYS_HDMI_DDC_SCL 6 ++#define GPI_SYS_HDMI_DDC_SDA 7 ++#define GPI_SYS_HDMI_HPD 8 ++#define GPI_SYS_I2C0_CLK 9 ++#define GPI_SYS_I2C0_DATA 10 ++#define GPI_SYS_SDIO0_CD 11 ++#define GPI_SYS_SDIO0_INT 12 ++#define GPI_SYS_SDIO0_WP 13 ++#define GPI_SYS_UART0_RX 14 ++#define GPI_SYS_HIFI4_JTAG_TCK 15 ++#define GPI_SYS_HIFI4_JTAG_TDI 16 ++#define GPI_SYS_HIFI4_JTAG_TMS 17 ++#define GPI_SYS_HIFI4_JTAG_RST 18 ++#define GPI_SYS_JTAG_TDI 19 ++#define GPI_SYS_JTAG_TMS 20 ++#define GPI_SYS_PDM_DMIC0 21 ++#define GPI_SYS_PDM_DMIC1 22 ++#define GPI_SYS_I2SRX_SDIN0 23 ++#define GPI_SYS_I2SRX_SDIN1 24 ++#define GPI_SYS_I2SRX_SDIN2 25 ++#define GPI_SYS_SPI0_CLK 26 ++#define GPI_SYS_SPI0_FSS 27 ++#define GPI_SYS_SPI0_RXD 28 ++#define GPI_SYS_JTAG_TCK 29 ++#define GPI_SYS_MCLK_EXT 30 ++#define GPI_SYS_I2SRX_BCLK 31 ++#define GPI_SYS_I2SRX_LRCK 32 ++#define GPI_SYS_I2STX0_BCLK 33 ++#define GPI_SYS_I2STX0_LRCK 34 ++#define GPI_SYS_TDM_CLK 35 ++#define GPI_SYS_TDM_RXD 36 ++#define GPI_SYS_TDM_SYNC 37 ++#define GPI_SYS_CAN1_RXD 38 ++#define GPI_SYS_I2C1_CLK 39 ++#define GPI_SYS_I2C1_DATA 40 ++#define GPI_SYS_SDIO1_CD 41 ++#define GPI_SYS_SDIO1_INT 42 ++#define GPI_SYS_SDIO1_WP 43 ++#define GPI_SYS_SDIO1_CMD 44 ++#define GPI_SYS_SDIO1_DATA0 45 ++#define GPI_SYS_SDIO1_DATA1 46 ++#define GPI_SYS_SDIO1_DATA2 47 ++#define GPI_SYS_SDIO1_DATA3 48 ++#define GPI_SYS_SDIO1_DATA4 49 ++#define GPI_SYS_SDIO1_DATA5 50 ++#define GPI_SYS_SDIO1_DATA6 51 ++#define GPI_SYS_SDIO1_DATA7 52 ++#define GPI_SYS_SDIO1_STRB 53 ++#define GPI_SYS_UART1_CTS 54 ++#define GPI_SYS_UART1_RX 55 ++#define GPI_SYS_SPI1_CLK 56 ++#define GPI_SYS_SPI1_FSS 57 ++#define GPI_SYS_SPI1_RXD 58 ++#define GPI_SYS_I2C2_CLK 59 ++#define GPI_SYS_I2C2_DATA 60 ++#define GPI_SYS_UART2_CTS 61 ++#define GPI_SYS_UART2_RX 62 ++#define GPI_SYS_SPI2_CLK 63 ++#define GPI_SYS_SPI2_FSS 64 ++#define GPI_SYS_SPI2_RXD 65 ++#define GPI_SYS_I2C3_CLK 66 ++#define GPI_SYS_I2C3_DATA 67 ++#define GPI_SYS_UART3_RX 68 ++#define GPI_SYS_SPI3_CLK 69 ++#define GPI_SYS_SPI3_FSS 70 ++#define GPI_SYS_SPI3_RXD 71 ++#define GPI_SYS_I2C4_CLK 72 ++#define GPI_SYS_I2C4_DATA 73 ++#define GPI_SYS_UART4_CTS 74 ++#define GPI_SYS_UART4_RX 75 ++#define GPI_SYS_SPI4_CLK 76 ++#define GPI_SYS_SPI4_FSS 77 ++#define GPI_SYS_SPI4_RXD 78 ++#define GPI_SYS_I2C5_CLK 79 ++#define GPI_SYS_I2C5_DATA 80 ++#define GPI_SYS_UART5_CTS 81 ++#define GPI_SYS_UART5_RX 82 ++#define GPI_SYS_SPI5_CLK 83 ++#define GPI_SYS_SPI5_FSS 84 ++#define GPI_SYS_SPI5_RXD 85 ++#define GPI_SYS_I2C6_CLK 86 ++#define GPI_SYS_I2C6_DATA 87 ++#define GPI_SYS_SPI6_CLK 88 ++#define GPI_SYS_SPI6_FSS 89 ++#define GPI_SYS_SPI6_RXD 90 ++ ++/* aon_iomux gin */ ++#define GPI_AON_PMU_GPIO_WAKEUP_0 0 ++#define GPI_AON_PMU_GPIO_WAKEUP_1 1 ++#define GPI_AON_PMU_GPIO_WAKEUP_2 2 ++#define GPI_AON_PMU_GPIO_WAKEUP_3 3 ++ ++#endif +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0021-riscv-dts-starfive-Add-StarFive-JH7110-VisionFive-2-.patch b/srcpkgs/linux6.3/patches/0021-riscv-dts-starfive-Add-StarFive-JH7110-VisionFive-2-.patch new file mode 100644 index 0000000000000..4009107d1b4c0 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0021-riscv-dts-starfive-Add-StarFive-JH7110-VisionFive-2-.patch @@ -0,0 +1,302 @@ +From d86f4ceb876a82d181a3c4a48b19899b610c6f4a Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Sat, 1 Apr 2023 19:19:33 +0800 +Subject: [PATCH 21/84] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 + board device tree + +Add a minimal device tree for StarFive JH7110 VisionFive 2 board +which has version A and version B. Support booting and basic +clock/reset/pinctrl/uart drivers. + +Tested-by: Tommaso Merciai +Reviewed-by: Conor Dooley +Acked-by: Conor Dooley +Signed-off-by: Emil Renner Berthing +Co-developed-by: Jianlong Huang +Signed-off-by: Jianlong Huang +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +--- + arch/riscv/boot/dts/starfive/Makefile | 6 +- + .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++ + .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++ + .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++ + 4 files changed, 246 insertions(+), 1 deletion(-) + create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts + create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts + create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi + +diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile +index 7b00a48580ca..170956846d49 100644 +--- a/arch/riscv/boot/dts/starfive/Makefile ++++ b/arch/riscv/boot/dts/starfive/Makefile +@@ -1,2 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 +-dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb ++dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb ++dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb ++ ++dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb ++dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +new file mode 100644 +index 000000000000..4af3300f3cf3 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022 Emil Renner Berthing ++ */ ++ ++/dts-v1/; ++#include "jh7110-starfive-visionfive-2.dtsi" ++ ++/ { ++ model = "StarFive VisionFive 2 v1.2A"; ++ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +new file mode 100644 +index 000000000000..9230cc3d8946 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022 Emil Renner Berthing ++ */ ++ ++/dts-v1/; ++#include "jh7110-starfive-visionfive-2.dtsi" ++ ++/ { ++ model = "StarFive VisionFive 2 v1.3B"; ++ compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +new file mode 100644 +index 000000000000..2a6d81609284 +--- /dev/null ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -0,0 +1,215 @@ ++// SPDX-License-Identifier: GPL-2.0 OR MIT ++/* ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022 Emil Renner Berthing ++ */ ++ ++/dts-v1/; ++#include "jh7110.dtsi" ++#include "jh7110-pinfunc.h" ++#include ++ ++/ { ++ aliases { ++ i2c0 = &i2c0; ++ i2c2 = &i2c2; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ serial0 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ cpus { ++ timebase-frequency = <4000000>; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x0 0x40000000 0x1 0x0>; ++ }; ++ ++ gpio-restart { ++ compatible = "gpio-restart"; ++ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; ++ priority = <224>; ++ }; ++}; ++ ++&gmac0_rgmii_rxin { ++ clock-frequency = <125000000>; ++}; ++ ++&gmac0_rmii_refin { ++ clock-frequency = <50000000>; ++}; ++ ++&gmac1_rgmii_rxin { ++ clock-frequency = <125000000>; ++}; ++ ++&gmac1_rmii_refin { ++ clock-frequency = <50000000>; ++}; ++ ++&i2srx_bclk_ext { ++ clock-frequency = <12288000>; ++}; ++ ++&i2srx_lrck_ext { ++ clock-frequency = <192000>; ++}; ++ ++&i2stx_bclk_ext { ++ clock-frequency = <12288000>; ++}; ++ ++&i2stx_lrck_ext { ++ clock-frequency = <192000>; ++}; ++ ++&mclk_ext { ++ clock-frequency = <12288000>; ++}; ++ ++&osc { ++ clock-frequency = <24000000>; ++}; ++ ++&rtc_osc { ++ clock-frequency = <32768>; ++}; ++ ++&tdm_ext { ++ clock-frequency = <49152000>; ++}; ++ ++&i2c0 { ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ status = "okay"; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++ status = "okay"; ++}; ++ ++&i2c5 { ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c5_pins>; ++ status = "okay"; ++}; ++ ++&i2c6 { ++ clock-frequency = <100000>; ++ i2c-sda-hold-time-ns = <300>; ++ i2c-sda-falling-time-ns = <510>; ++ i2c-scl-falling-time-ns = <510>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6_pins>; ++ status = "okay"; ++}; ++ ++&sysgpio { ++ i2c0_pins: i2c0-0 { ++ i2c-pins { ++ pinmux = , ++ ; ++ bias-disable; /* external pull-up */ ++ input-enable; ++ input-schmitt-enable; ++ }; ++ }; ++ ++ i2c2_pins: i2c2-0 { ++ i2c-pins { ++ pinmux = , ++ ; ++ bias-disable; /* external pull-up */ ++ input-enable; ++ input-schmitt-enable; ++ }; ++ }; ++ ++ i2c5_pins: i2c5-0 { ++ i2c-pins { ++ pinmux = , ++ ; ++ bias-disable; /* external pull-up */ ++ input-enable; ++ input-schmitt-enable; ++ }; ++ }; ++ ++ i2c6_pins: i2c6-0 { ++ i2c-pins { ++ pinmux = , ++ ; ++ bias-disable; /* external pull-up */ ++ input-enable; ++ input-schmitt-enable; ++ }; ++ }; ++ ++ uart0_pins: uart0-0 { ++ tx-pins { ++ pinmux = ; ++ bias-disable; ++ drive-strength = <12>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ rx-pins { ++ pinmux = ; ++ bias-disable; /* external pull-up */ ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-enable; ++ slew-rate = <0>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins>; ++ status = "okay"; ++}; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0022-riscv-dts-starfive-jh7110-Correct-the-properties-of-.patch b/srcpkgs/linux6.3/patches/0022-riscv-dts-starfive-jh7110-Correct-the-properties-of-.patch new file mode 100644 index 0000000000000..4a95f1baf4f81 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0022-riscv-dts-starfive-jh7110-Correct-the-properties-of-.patch @@ -0,0 +1,43 @@ +From 088994f8fd11fd50208850666c435abf5f2708f8 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Sat, 1 Apr 2023 19:19:34 +0800 +Subject: [PATCH 22/84] riscv: dts: starfive: jh7110: Correct the properties of + S7 core + +The S7 core has no L1 data cache and MMU, so delete some +related properties. + +Signed-off-by: Hal Feng +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 --------- + 1 file changed, 9 deletions(-) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index d484ecdf93f7..4c5fdb905da8 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -20,21 +20,12 @@ cpus { + S7_0: cpu@0 { + compatible = "sifive,s7", "riscv"; + reg = <0>; +- d-cache-block-size = <64>; +- d-cache-sets = <64>; +- d-cache-size = <8192>; +- d-tlb-sets = <1>; +- d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; +- i-tlb-sets = <1>; +- i-tlb-size = <40>; +- mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imac_zba_zbb"; +- tlb-split; + status = "disabled"; + + cpu0_intc: interrupt-controller { +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0023-dt-bindings-watchdog-Add-watchdog-for-StarFive-JH710.patch b/srcpkgs/linux6.3/patches/0023-dt-bindings-watchdog-Add-watchdog-for-StarFive-JH710.patch new file mode 100644 index 0000000000000..fbd326115f718 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0023-dt-bindings-watchdog-Add-watchdog-for-StarFive-JH710.patch @@ -0,0 +1,97 @@ +From 9849b12c48c250d450898ef28912941c1477d62d Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 14 Mar 2023 21:24:35 +0800 +Subject: [PATCH 23/84] dt-bindings: watchdog: Add watchdog for StarFive JH7100 + and JH7110 + +Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC. +And Use JH7100 as first StarFive SoC with watchdog. + +Signed-off-by: Xingyu Wu +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Guenter Roeck +--- + .../watchdog/starfive,jh7100-wdt.yaml | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml + +diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml +new file mode 100644 +index 000000000000..68f3f6fd08a6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive Watchdog for JH7100 and JH7110 SoC ++ ++maintainers: ++ - Xingyu Wu ++ - Samin Guo ++ ++description: ++ The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog ++ has only one timeout phase and reboots. And JH7110 watchdog has two ++ timeout phases. At the first phase, the signal of watchdog interrupt ++ output(WDOGINT) will rise when counter is 0. The counter will reload ++ the timeout value. And then, if counter decreases to 0 again and WDOGINT ++ isn't cleared, the watchdog will reset the system unless the watchdog ++ reset is disabled. ++ ++allOf: ++ - $ref: watchdog.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7100-wdt ++ - starfive,jh7110-wdt ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: APB clock ++ - description: Core clock ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: core ++ ++ resets: ++ items: ++ - description: APB reset ++ - description: Core reset ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ watchdog@12480000 { ++ compatible = "starfive,jh7100-wdt"; ++ reg = <0x12480000 0x10000>; ++ clocks = <&clk 171>, ++ <&clk 172>; ++ clock-names = "apb", "core"; ++ resets = <&rst 99>, ++ <&rst 100>; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0024-drivers-watchdog-Add-StarFive-Watchdog-driver.patch b/srcpkgs/linux6.3/patches/0024-drivers-watchdog-Add-StarFive-Watchdog-driver.patch new file mode 100644 index 0000000000000..3e06187fe3858 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0024-drivers-watchdog-Add-StarFive-Watchdog-driver.patch @@ -0,0 +1,687 @@ +From d211abfaf54922367a9285d7617d913f5bd66e99 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 14 Mar 2023 21:24:36 +0800 +Subject: [PATCH 24/84] drivers: watchdog: Add StarFive Watchdog driver + +Add watchdog driver for the StarFive JH7100 and JH7110 SoC. + +Signed-off-by: Xingyu Wu +Reviewed-by: Emil Renner Berthing +Reviewed-by: Guenter Roeck +--- + MAINTAINERS | 7 + + drivers/watchdog/Kconfig | 11 + + drivers/watchdog/Makefile | 3 + + drivers/watchdog/starfive-wdt.c | 606 ++++++++++++++++++++++++++++++++ + 4 files changed, 627 insertions(+) + create mode 100644 drivers/watchdog/starfive-wdt.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index ac1bd1c3b0d7..b3fdec579c39 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19954,6 +19954,13 @@ S: Supported + F: Documentation/devicetree/bindings/rng/starfive* + F: drivers/char/hw_random/jh7110-trng.c + ++STARFIVE WATCHDOG DRIVER ++M: Xingyu Wu ++M: Samin Guo ++S: Supported ++F: Documentation/devicetree/bindings/watchdog/starfive* ++F: drivers/watchdog/starfive-wdt.c ++ + STATIC BRANCH/CALL + M: Peter Zijlstra + M: Josh Poimboeuf +diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig +index f0872970daf9..f22138709bf5 100644 +--- a/drivers/watchdog/Kconfig ++++ b/drivers/watchdog/Kconfig +@@ -1999,6 +1999,17 @@ config WATCHDOG_RTAS + To compile this driver as a module, choose M here. The module + will be called wdrtas. + ++# RISC-V Architecture ++ ++config STARFIVE_WATCHDOG ++ tristate "StarFive Watchdog support" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ select WATCHDOG_CORE ++ default ARCH_STARFIVE ++ help ++ Say Y here to support the watchdog of StarFive JH7100 and JH7110 ++ SoC. This driver can also be built as a module if choose M. ++ + # S390 Architecture + + config DIAG288_WATCHDOG +diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile +index 9cbf6580f16c..b4c4ccf2d703 100644 +--- a/drivers/watchdog/Makefile ++++ b/drivers/watchdog/Makefile +@@ -192,6 +192,9 @@ obj-$(CONFIG_MEN_A21_WDT) += mena21_wdt.o + obj-$(CONFIG_PSERIES_WDT) += pseries-wdt.o + obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o + ++# RISC-V Architecture ++obj-$(CONFIG_STARFIVE_WATCHDOG) += starfive-wdt.o ++ + # S390 Architecture + obj-$(CONFIG_DIAG288_WATCHDOG) += diag288_wdt.o + +diff --git a/drivers/watchdog/starfive-wdt.c b/drivers/watchdog/starfive-wdt.c +new file mode 100644 +index 000000000000..1995cceca51e +--- /dev/null ++++ b/drivers/watchdog/starfive-wdt.c +@@ -0,0 +1,606 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Starfive Watchdog driver ++ * ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* JH7100 Watchdog register define */ ++#define STARFIVE_WDT_JH7100_INTSTAUS 0x000 ++#define STARFIVE_WDT_JH7100_CONTROL 0x104 ++#define STARFIVE_WDT_JH7100_LOAD 0x108 ++#define STARFIVE_WDT_JH7100_EN 0x110 ++#define STARFIVE_WDT_JH7100_RELOAD 0x114 /* Write 0 or 1 to reload preset value */ ++#define STARFIVE_WDT_JH7100_VALUE 0x118 ++#define STARFIVE_WDT_JH7100_INTCLR 0x120 /* ++ * [0]: Write 1 to clear interrupt ++ * [1]: 1 mean clearing and 0 mean complete ++ * [31:2]: reserved. ++ */ ++#define STARFIVE_WDT_JH7100_LOCK 0x13c /* write 0x378f0765 to unlock */ ++ ++/* JH7110 Watchdog register define */ ++#define STARFIVE_WDT_JH7110_LOAD 0x000 ++#define STARFIVE_WDT_JH7110_VALUE 0x004 ++#define STARFIVE_WDT_JH7110_CONTROL 0x008 /* ++ * [0]: reset enable; ++ * [1]: interrupt enable && watchdog enable ++ * [31:2]: reserved. ++ */ ++#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */ ++#define STARFIVE_WDT_JH7110_IMS 0x014 ++#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */ ++ ++/* WDOGCONTROL */ ++#define STARFIVE_WDT_ENABLE 0x1 ++#define STARFIVE_WDT_EN_SHIFT 0 ++#define STARFIVE_WDT_RESET_EN 0x1 ++#define STARFIVE_WDT_JH7100_RST_EN_SHIFT 0 ++#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1 ++ ++/* WDOGLOCK */ ++#define STARFIVE_WDT_JH7100_UNLOCK_KEY 0x378f0765 ++#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551 ++ ++/* WDOGINTCLR */ ++#define STARFIVE_WDT_INTCLR 0x1 ++#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */ ++ ++#define STARFIVE_WDT_MAXCNT 0xffffffff ++#define STARFIVE_WDT_DEFAULT_TIME (15) ++#define STARFIVE_WDT_DELAY_US 0 ++#define STARFIVE_WDT_TIMEOUT_US 10000 ++ ++/* module parameter */ ++#define STARFIVE_WDT_EARLY_ENA 0 ++ ++static bool nowayout = WATCHDOG_NOWAYOUT; ++static int heartbeat; ++static bool early_enable = STARFIVE_WDT_EARLY_ENA; ++ ++module_param(heartbeat, int, 0); ++module_param(early_enable, bool, 0); ++module_param(nowayout, bool, 0); ++ ++MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default=" ++ __MODULE_STRING(STARFIVE_WDT_DEFAULT_TIME) ")"); ++MODULE_PARM_DESC(early_enable, ++ "Watchdog is started at boot time if set to 1, default=" ++ __MODULE_STRING(STARFIVE_WDT_EARLY_ENA)); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++ ++struct starfive_wdt_variant { ++ unsigned int control; /* Watchdog Control Resgister for reset enable */ ++ unsigned int load; /* Watchdog Load register */ ++ unsigned int reload; /* Watchdog Reload Control register */ ++ unsigned int enable; /* Watchdog Enable Register */ ++ unsigned int value; /* Watchdog Counter Value Register */ ++ unsigned int int_clr; /* Watchdog Interrupt Clear Register */ ++ unsigned int unlock; /* Watchdog Lock Register */ ++ unsigned int int_status; /* Watchdog Interrupt Status Register */ ++ ++ u32 unlock_key; ++ char enrst_shift; ++ char en_shift; ++ bool intclr_check; /* whether need to check it before clearing interrupt */ ++ char intclr_ava_shift; ++ bool double_timeout; /* The watchdog need twice timeout to reboot */ ++}; ++ ++struct starfive_wdt { ++ struct watchdog_device wdd; ++ spinlock_t lock; /* spinlock for register handling */ ++ void __iomem *base; ++ struct clk *core_clk; ++ struct clk *apb_clk; ++ const struct starfive_wdt_variant *variant; ++ unsigned long freq; ++ u32 count; /* count of timeout */ ++ u32 reload; /* restore the count */ ++}; ++ ++/* Register layout and configuration for the JH7100 */ ++static const struct starfive_wdt_variant starfive_wdt_jh7100_variant = { ++ .control = STARFIVE_WDT_JH7100_CONTROL, ++ .load = STARFIVE_WDT_JH7100_LOAD, ++ .reload = STARFIVE_WDT_JH7100_RELOAD, ++ .enable = STARFIVE_WDT_JH7100_EN, ++ .value = STARFIVE_WDT_JH7100_VALUE, ++ .int_clr = STARFIVE_WDT_JH7100_INTCLR, ++ .unlock = STARFIVE_WDT_JH7100_LOCK, ++ .unlock_key = STARFIVE_WDT_JH7100_UNLOCK_KEY, ++ .int_status = STARFIVE_WDT_JH7100_INTSTAUS, ++ .enrst_shift = STARFIVE_WDT_JH7100_RST_EN_SHIFT, ++ .en_shift = STARFIVE_WDT_EN_SHIFT, ++ .intclr_check = true, ++ .intclr_ava_shift = STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT, ++ .double_timeout = false, ++}; ++ ++/* Register layout and configuration for the JH7110 */ ++static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = { ++ .control = STARFIVE_WDT_JH7110_CONTROL, ++ .load = STARFIVE_WDT_JH7110_LOAD, ++ .enable = STARFIVE_WDT_JH7110_CONTROL, ++ .value = STARFIVE_WDT_JH7110_VALUE, ++ .int_clr = STARFIVE_WDT_JH7110_INTCLR, ++ .unlock = STARFIVE_WDT_JH7110_LOCK, ++ .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY, ++ .int_status = STARFIVE_WDT_JH7110_IMS, ++ .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT, ++ .en_shift = STARFIVE_WDT_EN_SHIFT, ++ .intclr_check = false, ++ .double_timeout = true, ++}; ++ ++static int starfive_wdt_enable_clock(struct starfive_wdt *wdt) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(wdt->apb_clk); ++ if (ret) ++ return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n"); ++ ++ ret = clk_prepare_enable(wdt->core_clk); ++ if (ret) ++ return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n"); ++ ++ return 0; ++} ++ ++static void starfive_wdt_disable_clock(struct starfive_wdt *wdt) ++{ ++ clk_disable_unprepare(wdt->core_clk); ++ clk_disable_unprepare(wdt->apb_clk); ++} ++ ++static inline int starfive_wdt_get_clock(struct starfive_wdt *wdt) ++{ ++ struct device *dev = wdt->wdd.parent; ++ ++ wdt->apb_clk = devm_clk_get(dev, "apb"); ++ if (IS_ERR(wdt->apb_clk)) ++ return dev_err_probe(dev, PTR_ERR(wdt->apb_clk), "failed to get apb clock\n"); ++ ++ wdt->core_clk = devm_clk_get(dev, "core"); ++ if (IS_ERR(wdt->core_clk)) ++ return dev_err_probe(dev, PTR_ERR(wdt->core_clk), "failed to get core clock\n"); ++ ++ return 0; ++} ++ ++static inline int starfive_wdt_reset_init(struct device *dev) ++{ ++ struct reset_control *rsts; ++ int ret; ++ ++ rsts = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(rsts)) ++ return dev_err_probe(dev, PTR_ERR(rsts), "failed to get resets\n"); ++ ++ ret = reset_control_deassert(rsts); ++ if (ret) ++ return dev_err_probe(dev, ret, "failed to deassert resets\n"); ++ ++ return 0; ++} ++ ++static u32 starfive_wdt_ticks_to_sec(struct starfive_wdt *wdt, u32 ticks) ++{ ++ return DIV_ROUND_CLOSEST(ticks, wdt->freq); ++} ++ ++/* Write unlock-key to unlock. Write other value to lock. */ ++static void starfive_wdt_unlock(struct starfive_wdt *wdt) ++{ ++ spin_lock(&wdt->lock); ++ writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); ++} ++ ++static void starfive_wdt_lock(struct starfive_wdt *wdt) ++{ ++ writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock); ++ spin_unlock(&wdt->lock); ++} ++ ++/* enable watchdog interrupt to reset/reboot */ ++static void starfive_wdt_enable_reset(struct starfive_wdt *wdt) ++{ ++ u32 val; ++ ++ val = readl(wdt->base + wdt->variant->control); ++ val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift; ++ writel(val, wdt->base + wdt->variant->control); ++} ++ ++/* interrupt status whether has been raised from the counter */ ++static bool starfive_wdt_raise_irq_status(struct starfive_wdt *wdt) ++{ ++ return !!readl(wdt->base + wdt->variant->int_status); ++} ++ ++/* waiting interrupt can be free to clear */ ++static int starfive_wdt_wait_int_free(struct starfive_wdt *wdt) ++{ ++ u32 value; ++ ++ return readl_poll_timeout_atomic(wdt->base + wdt->variant->int_clr, value, ++ !(value & BIT(wdt->variant->intclr_ava_shift)), ++ STARFIVE_WDT_DELAY_US, STARFIVE_WDT_TIMEOUT_US); ++} ++ ++/* clear interrupt signal before initialization or reload */ ++static int starfive_wdt_int_clr(struct starfive_wdt *wdt) ++{ ++ int ret; ++ ++ if (wdt->variant->intclr_check) { ++ ret = starfive_wdt_wait_int_free(wdt); ++ if (ret) ++ return dev_err_probe(wdt->wdd.parent, ret, ++ "watchdog is not ready to clear interrupt.\n"); ++ } ++ writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); ++ ++ return 0; ++} ++ ++static inline void starfive_wdt_set_count(struct starfive_wdt *wdt, u32 val) ++{ ++ writel(val, wdt->base + wdt->variant->load); ++} ++ ++static inline u32 starfive_wdt_get_count(struct starfive_wdt *wdt) ++{ ++ return readl(wdt->base + wdt->variant->value); ++} ++ ++/* enable watchdog */ ++static inline void starfive_wdt_enable(struct starfive_wdt *wdt) ++{ ++ u32 val; ++ ++ val = readl(wdt->base + wdt->variant->enable); ++ val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift; ++ writel(val, wdt->base + wdt->variant->enable); ++} ++ ++/* disable watchdog */ ++static inline void starfive_wdt_disable(struct starfive_wdt *wdt) ++{ ++ u32 val; ++ ++ val = readl(wdt->base + wdt->variant->enable); ++ val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift); ++ writel(val, wdt->base + wdt->variant->enable); ++} ++ ++static inline void starfive_wdt_set_reload_count(struct starfive_wdt *wdt, u32 count) ++{ ++ starfive_wdt_set_count(wdt, count); ++ ++ /* 7100 need set any value to reload register and could reload value to counter */ ++ if (wdt->variant->reload) ++ writel(0x1, wdt->base + wdt->variant->reload); ++} ++ ++static unsigned int starfive_wdt_max_timeout(struct starfive_wdt *wdt) ++{ ++ if (wdt->variant->double_timeout) ++ return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, (wdt->freq / 2)) - 1; ++ ++ return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, wdt->freq) - 1; ++} ++ ++static unsigned int starfive_wdt_get_timeleft(struct watchdog_device *wdd) ++{ ++ struct starfive_wdt *wdt = watchdog_get_drvdata(wdd); ++ u32 count; ++ ++ /* ++ * If the watchdog takes twice timeout and set half count value, ++ * timeleft value should add the count value before first timeout. ++ */ ++ count = starfive_wdt_get_count(wdt); ++ if (wdt->variant->double_timeout && !starfive_wdt_raise_irq_status(wdt)) ++ count += wdt->count; ++ ++ return starfive_wdt_ticks_to_sec(wdt, count); ++} ++ ++static int starfive_wdt_keepalive(struct watchdog_device *wdd) ++{ ++ struct starfive_wdt *wdt = watchdog_get_drvdata(wdd); ++ int ret; ++ ++ starfive_wdt_unlock(wdt); ++ ret = starfive_wdt_int_clr(wdt); ++ if (ret) ++ goto exit; ++ ++ starfive_wdt_set_reload_count(wdt, wdt->count); ++ ++exit: ++ /* exit with releasing spinlock and locking registers */ ++ starfive_wdt_lock(wdt); ++ return ret; ++} ++ ++static int starfive_wdt_start(struct starfive_wdt *wdt) ++{ ++ int ret; ++ ++ starfive_wdt_unlock(wdt); ++ /* disable watchdog, to be safe */ ++ starfive_wdt_disable(wdt); ++ ++ starfive_wdt_enable_reset(wdt); ++ ret = starfive_wdt_int_clr(wdt); ++ if (ret) ++ goto exit; ++ ++ starfive_wdt_set_count(wdt, wdt->count); ++ starfive_wdt_enable(wdt); ++ ++exit: ++ starfive_wdt_lock(wdt); ++ return ret; ++} ++ ++static void starfive_wdt_stop(struct starfive_wdt *wdt) ++{ ++ starfive_wdt_unlock(wdt); ++ starfive_wdt_disable(wdt); ++ starfive_wdt_lock(wdt); ++} ++ ++static int starfive_wdt_pm_start(struct watchdog_device *wdd) ++{ ++ struct starfive_wdt *wdt = watchdog_get_drvdata(wdd); ++ int ret = pm_runtime_get_sync(wdd->parent); ++ ++ if (ret < 0) ++ return ret; ++ ++ return starfive_wdt_start(wdt); ++} ++ ++static int starfive_wdt_pm_stop(struct watchdog_device *wdd) ++{ ++ struct starfive_wdt *wdt = watchdog_get_drvdata(wdd); ++ ++ starfive_wdt_stop(wdt); ++ return pm_runtime_put_sync(wdd->parent); ++} ++ ++static int starfive_wdt_set_timeout(struct watchdog_device *wdd, ++ unsigned int timeout) ++{ ++ struct starfive_wdt *wdt = watchdog_get_drvdata(wdd); ++ unsigned long count = timeout * wdt->freq; ++ ++ /* some watchdogs take two timeouts to reset */ ++ if (wdt->variant->double_timeout) ++ count /= 2; ++ ++ wdt->count = count; ++ wdd->timeout = timeout; ++ ++ starfive_wdt_unlock(wdt); ++ starfive_wdt_disable(wdt); ++ starfive_wdt_set_reload_count(wdt, wdt->count); ++ starfive_wdt_enable(wdt); ++ starfive_wdt_lock(wdt); ++ ++ return 0; ++} ++ ++#define STARFIVE_WDT_OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE) ++ ++static const struct watchdog_info starfive_wdt_info = { ++ .options = STARFIVE_WDT_OPTIONS, ++ .identity = "StarFive Watchdog", ++}; ++ ++static const struct watchdog_ops starfive_wdt_ops = { ++ .owner = THIS_MODULE, ++ .start = starfive_wdt_pm_start, ++ .stop = starfive_wdt_pm_stop, ++ .ping = starfive_wdt_keepalive, ++ .set_timeout = starfive_wdt_set_timeout, ++ .get_timeleft = starfive_wdt_get_timeleft, ++}; ++ ++static int starfive_wdt_probe(struct platform_device *pdev) ++{ ++ struct starfive_wdt *wdt; ++ int ret; ++ ++ wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL); ++ if (!wdt) ++ return -ENOMEM; ++ ++ wdt->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(wdt->base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(wdt->base), "error mapping registers\n"); ++ ++ wdt->wdd.parent = &pdev->dev; ++ ret = starfive_wdt_get_clock(wdt); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, wdt); ++ pm_runtime_enable(&pdev->dev); ++ if (pm_runtime_enabled(&pdev->dev)) { ++ ret = pm_runtime_get_sync(&pdev->dev); ++ if (ret < 0) ++ return ret; ++ } else { ++ /* runtime PM is disabled but clocks need to be enabled */ ++ ret = starfive_wdt_enable_clock(wdt); ++ if (ret) ++ return ret; ++ } ++ ++ ret = starfive_wdt_reset_init(&pdev->dev); ++ if (ret) ++ goto err_exit; ++ ++ watchdog_set_drvdata(&wdt->wdd, wdt); ++ wdt->wdd.info = &starfive_wdt_info; ++ wdt->wdd.ops = &starfive_wdt_ops; ++ wdt->variant = of_device_get_match_data(&pdev->dev); ++ spin_lock_init(&wdt->lock); ++ ++ wdt->freq = clk_get_rate(wdt->core_clk); ++ if (!wdt->freq) { ++ dev_err(&pdev->dev, "get clock rate failed.\n"); ++ ret = -EINVAL; ++ goto err_exit; ++ } ++ ++ wdt->wdd.min_timeout = 1; ++ wdt->wdd.max_timeout = starfive_wdt_max_timeout(wdt); ++ wdt->wdd.timeout = STARFIVE_WDT_DEFAULT_TIME; ++ watchdog_init_timeout(&wdt->wdd, heartbeat, &pdev->dev); ++ starfive_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); ++ ++ watchdog_set_nowayout(&wdt->wdd, nowayout); ++ watchdog_stop_on_reboot(&wdt->wdd); ++ watchdog_stop_on_unregister(&wdt->wdd); ++ ++ if (early_enable) { ++ ret = starfive_wdt_start(wdt); ++ if (ret) ++ goto err_exit; ++ set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); ++ } else { ++ starfive_wdt_stop(wdt); ++ } ++ ++ ret = watchdog_register_device(&wdt->wdd); ++ if (ret) ++ goto err_exit; ++ ++ if (!early_enable) ++ return pm_runtime_put_sync(&pdev->dev); ++ ++ return 0; ++ ++err_exit: ++ starfive_wdt_disable_clock(wdt); ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int starfive_wdt_remove(struct platform_device *pdev) ++{ ++ struct starfive_wdt *wdt = platform_get_drvdata(pdev); ++ ++ starfive_wdt_stop(wdt); ++ watchdog_unregister_device(&wdt->wdd); ++ ++ if (pm_runtime_enabled(&pdev->dev)) ++ pm_runtime_disable(&pdev->dev); ++ else ++ /* disable clock without PM */ ++ starfive_wdt_disable_clock(wdt); ++ ++ return 0; ++} ++ ++static void starfive_wdt_shutdown(struct platform_device *pdev) ++{ ++ struct starfive_wdt *wdt = platform_get_drvdata(pdev); ++ ++ starfive_wdt_pm_stop(&wdt->wdd); ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int starfive_wdt_suspend(struct device *dev) ++{ ++ struct starfive_wdt *wdt = dev_get_drvdata(dev); ++ ++ /* Save watchdog state, and turn it off. */ ++ wdt->reload = starfive_wdt_get_count(wdt); ++ ++ /* Note that WTCNT doesn't need to be saved. */ ++ starfive_wdt_stop(wdt); ++ ++ return pm_runtime_force_suspend(dev); ++} ++ ++static int starfive_wdt_resume(struct device *dev) ++{ ++ struct starfive_wdt *wdt = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = pm_runtime_force_resume(dev); ++ if (ret) ++ return ret; ++ ++ starfive_wdt_unlock(wdt); ++ /* Restore watchdog state. */ ++ starfive_wdt_set_reload_count(wdt, wdt->reload); ++ starfive_wdt_lock(wdt); ++ ++ return starfive_wdt_start(wdt); ++} ++#endif /* CONFIG_PM_SLEEP */ ++ ++#ifdef CONFIG_PM ++static int starfive_wdt_runtime_suspend(struct device *dev) ++{ ++ struct starfive_wdt *wdt = dev_get_drvdata(dev); ++ ++ starfive_wdt_disable_clock(wdt); ++ ++ return 0; ++} ++ ++static int starfive_wdt_runtime_resume(struct device *dev) ++{ ++ struct starfive_wdt *wdt = dev_get_drvdata(dev); ++ ++ return starfive_wdt_enable_clock(wdt); ++} ++#endif /* CONFIG_PM */ ++ ++static const struct dev_pm_ops starfive_wdt_pm_ops = { ++ SET_RUNTIME_PM_OPS(starfive_wdt_runtime_suspend, starfive_wdt_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(starfive_wdt_suspend, starfive_wdt_resume) ++}; ++ ++static const struct of_device_id starfive_wdt_match[] = { ++ { .compatible = "starfive,jh7100-wdt", .data = &starfive_wdt_jh7100_variant }, ++ { .compatible = "starfive,jh7110-wdt", .data = &starfive_wdt_jh7110_variant }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_wdt_match); ++ ++static struct platform_driver starfive_wdt_driver = { ++ .probe = starfive_wdt_probe, ++ .remove = starfive_wdt_remove, ++ .shutdown = starfive_wdt_shutdown, ++ .driver = { ++ .name = "starfive-wdt", ++ .pm = &starfive_wdt_pm_ops, ++ .of_match_table = of_match_ptr(starfive_wdt_match), ++ }, ++}; ++module_platform_driver(starfive_wdt_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_AUTHOR("Samin Guo "); ++MODULE_DESCRIPTION("StarFive Watchdog Device Driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0025-riscv-dts-starfive-jh7100-Add-watchdog-node.patch b/srcpkgs/linux6.3/patches/0025-riscv-dts-starfive-jh7100-Add-watchdog-node.patch new file mode 100644 index 0000000000000..aa9013d3aaaba --- /dev/null +++ b/srcpkgs/linux6.3/patches/0025-riscv-dts-starfive-jh7100-Add-watchdog-node.patch @@ -0,0 +1,36 @@ +From 7841ed91ac3118db11826c502caf1e7ff2996041 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 14 Mar 2023 21:24:37 +0800 +Subject: [PATCH 25/84] riscv: dts: starfive: jh7100: Add watchdog node + +Add watchdog node for the StarFive JH7100 RISC-V SoC. + +Signed-off-by: Xingyu Wu +Reviewed-by: Emil Renner Berthing +--- + arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi +index 000447482aca..4218621ea3b9 100644 +--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi +@@ -238,5 +238,15 @@ i2c3: i2c@12460000 { + #size-cells = <0>; + status = "disabled"; + }; ++ ++ watchdog@12480000 { ++ compatible = "starfive,jh7100-wdt"; ++ reg = <0x0 0x12480000 0x0 0x10000>; ++ clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, ++ <&clkgen JH7100_CLK_WDT_CORE>; ++ clock-names = "apb", "core"; ++ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, ++ <&rstgen JH7100_RSTN_WDT>; ++ }; + }; + }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0026-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch b/srcpkgs/linux6.3/patches/0026-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch new file mode 100644 index 0000000000000..d93f00baedb56 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0026-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch @@ -0,0 +1,119 @@ +From 8e7f8e12b46d169ecdf44249de6f1e0c6a1b883a Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 20 Mar 2023 21:54:31 +0800 +Subject: [PATCH 26/84] dt-bindings: timer: Add timer for StarFive JH7110 SoC + +Add bindings for the timer on the JH7110 RISC-V SoC +by StarFive Technology Ltd. + +Signed-off-by: Xingyu Wu +Reviewed-by: Krzysztof Kozlowski +--- + .../bindings/timer/starfive,jh7110-timer.yaml | 95 +++++++++++++++++++ + 1 file changed, 95 insertions(+) + create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml + +diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +new file mode 100644 +index 000000000000..24b34618f2c8 +--- /dev/null ++++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +@@ -0,0 +1,95 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Timer ++maintainers: ++ - Xingyu Wu ++ - Samin Guo ++ ++description: ++ This timer has four free-running 32 bit counters in StarFive JH7110 SoC. ++ And each channel(counter) triggers an interrupt when timeout. They support ++ one-shot mode and continuous-run mode. ++ ++properties: ++ compatible: ++ const: starfive,jh7110-timer ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ items: ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ clocks: ++ items: ++ - description: timer APB ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: ch0 ++ - const: ch1 ++ - const: ch2 ++ - const: ch3 ++ ++ resets: ++ items: ++ - description: timer APB ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ reset-names: ++ items: ++ - const: apb ++ - const: ch0 ++ - const: ch1 ++ - const: ch2 ++ - const: ch3 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ timer@13050000 { ++ compatible = "starfive,jh7110-timer"; ++ reg = <0x13050000 0x10000>; ++ interrupts = <69>, <70>, <71> ,<72>; ++ clocks = <&clk 124>, ++ <&clk 125>, ++ <&clk 126>, ++ <&clk 127>, ++ <&clk 128>; ++ clock-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ resets = <&rst 117>, ++ <&rst 118>, ++ <&rst 119>, ++ <&rst 120>, ++ <&rst 121>; ++ reset-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ }; ++ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0027-clocksource-Add-StarFive-timer-driver.patch b/srcpkgs/linux6.3/patches/0027-clocksource-Add-StarFive-timer-driver.patch new file mode 100644 index 0000000000000..35339bf4f3de3 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0027-clocksource-Add-StarFive-timer-driver.patch @@ -0,0 +1,572 @@ +From ef26079b53c13dc8fc3a3a55e791c1ae0d1b1128 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 20 Mar 2023 21:54:32 +0800 +Subject: [PATCH 27/84] clocksource: Add StarFive timer driver + +Add timer driver for the StarFive JH7110 SoC. + +Signed-off-by: Xingyu Wu +--- + MAINTAINERS | 7 + + drivers/clocksource/Kconfig | 12 + + drivers/clocksource/Makefile | 1 + + drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++ + drivers/clocksource/timer-starfive.h | 96 +++++++ + 5 files changed, 506 insertions(+) + create mode 100644 drivers/clocksource/timer-starfive.c + create mode 100644 drivers/clocksource/timer-starfive.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index b3fdec579c39..d8fa71c6099e 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19948,6 +19948,13 @@ S: Maintained + T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ + F: drivers/soc/starfive/ + ++STARFIVE TIMER DRIVER ++M: Samin Guo ++M: Xingyu Wu ++S: Supported ++F: Documentation/devicetree/bindings/timer/starfive* ++F: drivers/clocksource/timer-starfive* ++ + STARFIVE TRNG DRIVER + M: Jia Jie Ho + S: Supported +diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig +index 5fc8f0e7fb38..35daf07d4db7 100644 +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -630,6 +630,18 @@ config RISCV_TIMER + is accessed via both the SBI and the rdcycle instruction. This is + required for all RISC-V systems. + ++config STARFIVE_TIMER ++ bool "Timer for the STARFIVE SoCs" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ select TIMER_OF ++ select CLKSRC_MMIO ++ default ARCH_STARFIVE ++ help ++ This enables the timer for StarFive SoCs. On RISC-V platform, ++ the system has started RISCV_TIMER. But you can also use this timer ++ to do a lot more on StarFive SoCs. This timer can provide high ++ precision and four channels to use in JH7110 SoC. ++ + config CLINT_TIMER + bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST + depends on GENERIC_SCHED_CLOCK && RISCV +diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile +index 64ab547de97b..276695d95cdc 100644 +--- a/drivers/clocksource/Makefile ++++ b/drivers/clocksource/Makefile +@@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o + obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o + obj-$(CONFIG_X86_NUMACHIP) += numachip.o + obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o ++obj-$(CONFIG_STARFIVE_TIMER) += timer-starfive.o + obj-$(CONFIG_CLINT_TIMER) += timer-clint.o + obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o + obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o +diff --git a/drivers/clocksource/timer-starfive.c b/drivers/clocksource/timer-starfive.c +new file mode 100644 +index 000000000000..53163948ed86 +--- /dev/null ++++ b/drivers/clocksource/timer-starfive.c +@@ -0,0 +1,390 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Starfive Timer driver ++ * ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * ++ * Author: ++ * Xingyu Wu ++ * Samin Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "timer-starfive.h" ++ ++static const struct starfive_timer_chan_base starfive_timer_jh7110_base = { ++ .ctrl = STARFIVE_TIMER_JH7110_CTL, ++ .load = STARFIVE_TIMER_JH7110_LOAD, ++ .enable = STARFIVE_TIMER_JH7110_ENABLE, ++ .reload = STARFIVE_TIMER_JH7110_RELOAD, ++ .value = STARFIVE_TIMER_JH7110_VALUE, ++ .intclr = STARFIVE_TIMER_JH7110_INT_CLR, ++ .intmask = STARFIVE_TIMER_JH7110_INT_MASK, ++ .channel_num = STARFIVE_TIMER_CH_4, ++ .channel_base = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1), ++ STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)}, ++}; ++ ++static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt) ++{ ++ return container_of(evt, struct starfive_clkevt, evt); ++} ++ ++/* 0:continuous-run mode, 1:single-run mode */ ++static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod) ++{ ++ writel(mod, clkevt->ctrl); ++} ++ ++/* Interrupt Mask Register, 0:Unmask, 1:Mask */ ++static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt) ++{ ++ writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask); ++} ++ ++static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt) ++{ ++ writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask); ++} ++ ++/* ++ * BIT(0): Read value represent channel intr status. ++ * Write 1 to this bit to clear interrupt. Write 0 has no effects. ++ * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written. ++ */ ++static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt) ++{ ++ u32 value; ++ int ret; ++ ++ /* waiting interrupt can be to clearing */ ++ ret = readl_poll_timeout_atomic(clkevt->intclr, value, ++ !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK), ++ STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US); ++ if (!ret) ++ writel(0x1, clkevt->intclr); ++ ++ return ret; ++} ++ ++/* ++ * The initial value to be loaded into the ++ * counter and is also used as the reload value. ++ * val = clock rate --> 1s ++ */ ++static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val) ++{ ++ writel(val, clkevt->load); ++} ++ ++static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt) ++{ ++ return readl(clkevt->value); ++} ++ ++/* ++ * Write RELOAD register to reload preset value to counter. ++ * (Write 0 and write 1 are both ok) ++ */ ++static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt) ++{ ++ writel(0, clkevt->reload); ++} ++ ++static inline void starfive_timer_enable(struct starfive_clkevt *clkevt) ++{ ++ writel(STARFIVE_TIMER_ENA, clkevt->enable); ++} ++ ++static inline void starfive_timer_disable(struct starfive_clkevt *clkevt) ++{ ++ writel(STARFIVE_TIMER_DIS, clkevt->enable); ++} ++ ++static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt) ++{ ++ int ret; ++ ++ starfive_timer_int_disable(clkevt); ++ ret = starfive_timer_int_clear(clkevt); ++ if (ret) ++ return ret; ++ ++ starfive_timer_int_enable(clkevt); ++ starfive_timer_enable(clkevt); ++ ++ return 0; ++} ++ ++static int starfive_timer_shutdown(struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ starfive_timer_disable(clkevt); ++ return starfive_timer_int_clear(clkevt); ++} ++ ++static void starfive_timer_suspend(struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ clkevt->reload_val = starfive_timer_get_val(clkevt); ++ starfive_timer_shutdown(evt); ++} ++ ++static void starfive_timer_resume(struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ starfive_timer_set_load(clkevt, clkevt->reload_val); ++ starfive_timer_set_reload(clkevt); ++ starfive_timer_int_enable(clkevt); ++ starfive_timer_enable(clkevt); ++} ++ ++static int starfive_timer_tick_resume(struct clock_event_device *evt) ++{ ++ starfive_timer_resume(evt); ++ ++ return 0; ++} ++ ++static int starfive_clocksource_init(struct starfive_clkevt *clkevt) ++{ ++ int ret; ++ ++ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN); ++ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS); ++ ret = starfive_timer_int_init_enable(clkevt); ++ if (ret) ++ return ret; ++ ++ return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate, ++ STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS, ++ clocksource_mmio_readl_down); ++} ++ ++/* IRQ handler for the timer */ ++static irqreturn_t starfive_timer_interrupt(int irq, void *priv) ++{ ++ struct clock_event_device *evt = (struct clock_event_device *)priv; ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ if (starfive_timer_int_clear(clkevt)) ++ return IRQ_NONE; ++ ++ if (evt->event_handler) ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static int starfive_timer_set_periodic(struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ starfive_timer_disable(clkevt); ++ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN); ++ starfive_timer_set_load(clkevt, clkevt->periodic); ++ ++ return starfive_timer_int_init_enable(clkevt); ++} ++ ++static int starfive_timer_set_oneshot(struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ starfive_timer_disable(clkevt); ++ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE); ++ starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS); ++ ++ return starfive_timer_int_init_enable(clkevt); ++} ++ ++static int starfive_timer_set_next_event(unsigned long next, ++ struct clock_event_device *evt) ++{ ++ struct starfive_clkevt *clkevt = to_starfive_clkevt(evt); ++ ++ starfive_timer_disable(clkevt); ++ starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE); ++ starfive_timer_set_load(clkevt, next); ++ starfive_timer_enable(clkevt); ++ ++ return 0; ++} ++ ++static void starfive_set_clockevent(struct clock_event_device *evt) ++{ ++ evt->features = CLOCK_EVT_FEAT_PERIODIC | ++ CLOCK_EVT_FEAT_ONESHOT | ++ CLOCK_EVT_FEAT_DYNIRQ; ++ evt->set_state_shutdown = starfive_timer_shutdown; ++ evt->set_state_periodic = starfive_timer_set_periodic; ++ evt->set_state_oneshot = starfive_timer_set_oneshot; ++ evt->set_state_oneshot_stopped = starfive_timer_shutdown; ++ evt->tick_resume = starfive_timer_tick_resume; ++ evt->set_next_event = starfive_timer_set_next_event; ++ evt->suspend = starfive_timer_suspend; ++ evt->resume = starfive_timer_resume; ++ evt->rating = STARFIVE_CLOCKEVENT_RATING; ++} ++ ++static void starfive_clockevents_register(struct starfive_clkevt *clkevt) ++{ ++ clkevt->rate = clk_get_rate(clkevt->clk); ++ clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ); ++ ++ starfive_set_clockevent(&clkevt->evt); ++ clkevt->evt.name = clkevt->name; ++ clkevt->evt.irq = clkevt->irq; ++ clkevt->evt.cpumask = cpu_possible_mask; ++ ++ clockevents_config_and_register(&clkevt->evt, clkevt->rate, ++ STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS); ++} ++ ++static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer, ++ struct starfive_clkevt *clkevt, ++ void __iomem *base, int ch) ++{ ++ void __iomem *channel_base; ++ ++ channel_base = base + timer->channel_base[ch]; ++ clkevt->base = channel_base; ++ clkevt->ctrl = channel_base + timer->ctrl; ++ clkevt->load = channel_base + timer->load; ++ clkevt->enable = channel_base + timer->enable; ++ clkevt->reload = channel_base + timer->reload; ++ clkevt->value = channel_base + timer->value; ++ clkevt->intclr = channel_base + timer->intclr; ++ clkevt->intmask = channel_base + timer->intmask; ++} ++ ++static int __init starfive_timer_probe(struct platform_device *pdev) ++{ ++ const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev); ++ char name[10]; ++ struct starfive_timer_priv *priv; ++ struct starfive_clkevt *clkevt; ++ struct clk *pclk; ++ struct reset_control *rst; ++ int ch; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(priv->base), ++ "failed to map registers\n"); ++ ++ rst = devm_reset_control_get_exclusive(&pdev->dev, "apb"); ++ if (IS_ERR(rst)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n"); ++ ++ pclk = devm_clk_get_enabled(&pdev->dev, "apb"); ++ if (IS_ERR(pclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pclk), ++ "failed to get & enable apb clock\n"); ++ ++ ret = reset_control_deassert(rst); ++ if (ret) ++ goto err; ++ ++ priv->dev = &pdev->dev; ++ platform_set_drvdata(pdev, priv); ++ ++ for (ch = 0; ch < timer_base->channel_num; ch++) { ++ clkevt = &priv->clkevt[ch]; ++ snprintf(name, sizeof(name), "ch%d", ch); ++ ++ starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch); ++ /* Ensure timers are disabled */ ++ starfive_timer_disable(clkevt); ++ ++ rst = devm_reset_control_get_exclusive(&pdev->dev, name); ++ if (IS_ERR(rst)) { ++ ret = PTR_ERR(rst); ++ goto err; ++ } ++ ++ clkevt->clk = devm_clk_get_enabled(&pdev->dev, name); ++ if (IS_ERR(clkevt->clk)) { ++ ret = PTR_ERR(clkevt->clk); ++ goto err; ++ } ++ ++ ret = reset_control_deassert(rst); ++ if (ret) ++ goto ch_err; ++ ++ clkevt->irq = platform_get_irq(pdev, ch); ++ if (clkevt->irq < 0) { ++ ret = clkevt->irq; ++ goto ch_err; ++ } ++ ++ snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch); ++ starfive_clockevents_register(clkevt); ++ ++ ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt, ++ IRQF_TIMER | IRQF_IRQPOLL, ++ clkevt->name, &clkevt->evt); ++ if (ret) ++ goto ch_err; ++ ++ ret = starfive_clocksource_init(clkevt); ++ if (ret) ++ goto ch_err; ++ } ++ ++ return 0; ++ ++ch_err: ++ /* Only unregister the failed channel and the rest timer channels continue to work. */ ++ clk_disable_unprepare(clkevt->clk); ++err: ++ /* If no other channel successfully registers, pclk should be disabled. */ ++ if (!ch) ++ clk_disable_unprepare(pclk); ++ ++ return ret; ++} ++ ++static const struct of_device_id starfive_timer_match[] = { ++ { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_timer_match); ++ ++static struct platform_driver starfive_timer_driver = { ++ .probe = starfive_timer_probe, ++ .driver = { ++ .name = "starfive-timer", ++ .of_match_table = starfive_timer_match, ++ }, ++}; ++module_platform_driver(starfive_timer_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive timer driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clocksource/timer-starfive.h b/drivers/clocksource/timer-starfive.h +new file mode 100644 +index 000000000000..62eb630cc98d +--- /dev/null ++++ b/drivers/clocksource/timer-starfive.h +@@ -0,0 +1,96 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef __STARFIVE_TIMER_H__ ++#define __STARFIVE_TIMER_H__ ++ ++/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */ ++#define STARFIVE_TIMER_CH_LEN 0x40 ++#define STARFIVE_TIMER_CH_BASE(x) ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN) ++ ++#define STARFIVE_CLOCK_SOURCE_RATING 200 ++#define STARFIVE_VALID_BITS 32 ++#define STARFIVE_DELAY_US 0 ++#define STARFIVE_TIMEOUT_US 10000 ++#define STARFIVE_CLOCKEVENT_RATING 300 ++#define STARFIVE_TIMER_MAX_TICKS 0xffffffff ++#define STARFIVE_TIMER_MIN_TICKS 0xf ++ ++#define STARFIVE_TIMER_JH7110_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */ ++#define STARFIVE_TIMER_JH7110_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */ ++#define STARFIVE_TIMER_JH7110_LOAD 0x08 /* RW: load value to counter */ ++#define STARFIVE_TIMER_JH7110_ENABLE 0x10 /* RW[0]: timer enable register */ ++#define STARFIVE_TIMER_JH7110_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */ ++#define STARFIVE_TIMER_JH7110_VALUE 0x18 /* RO: timer value register */ ++#define STARFIVE_TIMER_JH7110_INT_CLR 0x20 /* RW: timer interrupt clear register */ ++#define STARFIVE_TIMER_JH7110_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */ ++#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1) ++ ++enum STARFIVE_TIMER_CH { ++ STARFIVE_TIMER_CH_0 = 0, ++ STARFIVE_TIMER_CH_1, ++ STARFIVE_TIMER_CH_2, ++ STARFIVE_TIMER_CH_3, ++ STARFIVE_TIMER_CH_4, ++ STARFIVE_TIMER_CH_5, ++ STARFIVE_TIMER_CH_6, ++ STARFIVE_TIMER_CH_7, ++ STARFIVE_TIMER_CH_MAX ++}; ++ ++enum STARFIVE_TIMER_INTMASK { ++ STARFIVE_TIMER_INTMASK_DIS = 0, ++ STARFIVE_TIMER_INTMASK_ENA = 1 ++}; ++ ++enum STARFIVE_TIMER_MOD { ++ STARFIVE_TIMER_MOD_CONTIN = 0, ++ STARFIVE_TIMER_MOD_SINGLE = 1 ++}; ++ ++enum STARFIVE_TIMER_CTL_EN { ++ STARFIVE_TIMER_DIS = 0, ++ STARFIVE_TIMER_ENA = 1 ++}; ++ ++struct starfive_timer_chan_base { ++ /* Resgister */ ++ unsigned int ctrl; ++ unsigned int load; ++ unsigned int enable; ++ unsigned int reload; ++ unsigned int value; ++ unsigned int intclr; ++ unsigned int intmask; ++ ++ unsigned int channel_num; /* timer channel numbers */ ++ unsigned int channel_base[]; ++}; ++ ++struct starfive_clkevt { ++ struct clock_event_device evt; ++ struct clk *clk; ++ char name[20]; ++ int irq; ++ u32 periodic; ++ u32 rate; ++ u32 reload_val; ++ void __iomem *base; ++ void __iomem *ctrl; ++ void __iomem *load; ++ void __iomem *enable; ++ void __iomem *reload; ++ void __iomem *value; ++ void __iomem *intclr; ++ void __iomem *intmask; ++}; ++ ++struct starfive_timer_priv { ++ struct device *dev; ++ void __iomem *base; ++ struct starfive_clkevt clkevt[]; ++}; ++ ++#endif /* __STARFIVE_TIMER_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0028-riscv-dts-jh7110-starfive-Add-timer-node.patch b/srcpkgs/linux6.3/patches/0028-riscv-dts-jh7110-starfive-Add-timer-node.patch new file mode 100644 index 0000000000000..7342a7f97ae05 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0028-riscv-dts-jh7110-starfive-Add-timer-node.patch @@ -0,0 +1,46 @@ +From fda30fc61b8de414af613e0607680ecf27b34839 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 20 Mar 2023 21:54:33 +0800 +Subject: [PATCH 28/84] riscv: dts: jh7110: starfive: Add timer node + +Add the timer node for the Starfive JH7110 SoC. + +Signed-off-by: Xingyu Wu +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 4c5fdb905da8..587aa6830c4b 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -469,6 +469,26 @@ sysgpio: pinctrl@13040000 { + #gpio-cells = <2>; + }; + ++ timer@13050000 { ++ compatible = "starfive,jh7110-timer"; ++ reg = <0x0 0x13050000 0x0 0x10000>; ++ interrupts = <69>, <70>, <71> ,<72>; ++ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>, ++ <&syscrg JH7110_SYSCLK_TIMER0>, ++ <&syscrg JH7110_SYSCLK_TIMER1>, ++ <&syscrg JH7110_SYSCLK_TIMER2>, ++ <&syscrg JH7110_SYSCLK_TIMER3>; ++ clock-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ resets = <&syscrg JH7110_SYSRST_TIMER_APB>, ++ <&syscrg JH7110_SYSRST_TIMER0>, ++ <&syscrg JH7110_SYSRST_TIMER1>, ++ <&syscrg JH7110_SYSRST_TIMER2>, ++ <&syscrg JH7110_SYSRST_TIMER3>; ++ reset-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ }; ++ + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0029-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch b/srcpkgs/linux6.3/patches/0029-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch new file mode 100644 index 0000000000000..26bde36433bb0 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0029-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch @@ -0,0 +1,95 @@ +From 1c0a57d7ee23eb163e7c8d9dd58dade48ec98a26 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Tue, 21 Mar 2023 10:26:43 +0800 +Subject: [PATCH 29/84] dt-bindings: hwmon: Add starfive,jh71x0-temp + +Add bindings for the temperature sensor on the StarFive JH7100 and +JH7110 SoCs. + +Signed-off-by: Emil Renner Berthing +Signed-off-by: Hal Feng +Reviewed-by: Rob Herring +--- + .../bindings/hwmon/starfive,jh71x0-temp.yaml | 70 +++++++++++++++++++ + 1 file changed, 70 insertions(+) + create mode 100644 Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml + +diff --git a/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml +new file mode 100644 +index 000000000000..f5b34528928d +--- /dev/null ++++ b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml +@@ -0,0 +1,70 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH71x0 Temperature Sensor ++ ++maintainers: ++ - Emil Renner Berthing ++ ++description: | ++ StarFive Technology Co. JH71x0 embedded temperature sensor ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7100-temp ++ - starfive,jh7110-temp ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 2 ++ maxItems: 2 ++ ++ clock-names: ++ items: ++ - const: "sense" ++ - const: "bus" ++ ++ '#thermal-sensor-cells': ++ const: 0 ++ ++ resets: ++ minItems: 2 ++ maxItems: 2 ++ ++ reset-names: ++ items: ++ - const: "sense" ++ - const: "bus" ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ ++ temperature-sensor@124a0000 { ++ compatible = "starfive,jh7100-temp"; ++ reg = <0x124a0000 0x10000>; ++ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, ++ <&clkgen JH7100_CLK_TEMP_APB>; ++ clock-names = "sense", "bus"; ++ #thermal-sensor-cells = <0>; ++ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, ++ <&rstgen JH7100_RSTN_TEMP_APB>; ++ reset-names = "sense", "bus"; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0030-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch b/srcpkgs/linux6.3/patches/0030-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch new file mode 100644 index 0000000000000..a633e1d3d9de5 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0030-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch @@ -0,0 +1,467 @@ +From 9b6f7b5e3adc2eb2bf602ce58b6da65a0723ebb1 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Tue, 21 Mar 2023 10:26:44 +0800 +Subject: [PATCH 30/84] hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor + +Add driver for the StarFive JH71x0 temperature sensor. You +can enable/disable it and read temperature in milli Celcius +through sysfs. + +Signed-off-by: Emil Renner Berthing +Co-developed-by: Samin Guo +Signed-off-by: Samin Guo +Signed-off-by: Hal Feng +--- + Documentation/hwmon/index.rst | 1 + + Documentation/hwmon/sfctemp.rst | 33 ++++ + MAINTAINERS | 8 + + drivers/hwmon/Kconfig | 10 + + drivers/hwmon/Makefile | 1 + + drivers/hwmon/sfctemp.c | 331 ++++++++++++++++++++++++++++++++ + 6 files changed, 384 insertions(+) + create mode 100644 Documentation/hwmon/sfctemp.rst + create mode 100644 drivers/hwmon/sfctemp.c + +diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst +index f1fe75f596a5..d72bb1df6431 100644 +--- a/Documentation/hwmon/index.rst ++++ b/Documentation/hwmon/index.rst +@@ -184,6 +184,7 @@ Hardware Monitoring Kernel Drivers + sch5627 + sch5636 + scpi-hwmon ++ sfctemp + sht15 + sht21 + sht3x +diff --git a/Documentation/hwmon/sfctemp.rst b/Documentation/hwmon/sfctemp.rst +new file mode 100644 +index 000000000000..9fbd5bb1f356 +--- /dev/null ++++ b/Documentation/hwmon/sfctemp.rst +@@ -0,0 +1,33 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++Kernel driver sfctemp ++===================== ++ ++Supported chips: ++ - StarFive JH7100 ++ - StarFive JH7110 ++ ++Authors: ++ - Emil Renner Berthing ++ ++Description ++----------- ++ ++This driver adds support for reading the built-in temperature sensor on the ++JH7100 and JH7110 RISC-V SoCs by StarFive Technology Co. Ltd. ++ ++``sysfs`` interface ++------------------- ++ ++The temperature sensor can be enabled, disabled and queried via the standard ++hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of ++``X``: ++ ++================ ==== ============================================= ++Name Perm Description ++================ ==== ============================================= ++temp1_enable RW Enable or disable temperature sensor. ++ Automatically enabled by the driver, ++ but may be disabled to save power. ++temp1_input RO Temperature reading in milli-degrees Celsius. ++================ ==== ============================================= +diff --git a/MAINTAINERS b/MAINTAINERS +index d8fa71c6099e..83d88a6fc1d8 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -18909,6 +18909,14 @@ S: Supported + F: Documentation/networking/devlink/sfc.rst + F: drivers/net/ethernet/sfc/ + ++SFCTEMP HWMON DRIVER ++M: Emil Renner Berthing ++L: linux-hwmon@vger.kernel.org ++S: Maintained ++F: Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml ++F: Documentation/hwmon/sfctemp.rst ++F: drivers/hwmon/sfctemp.c ++ + SFF/SFP/SFP+ MODULE SUPPORT + M: Russell King + L: netdev@vger.kernel.org +diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig +index 5b3b76477b0e..abb82a73dbaf 100644 +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -1929,6 +1929,16 @@ config SENSORS_STTS751 + This driver can also be built as a module. If so, the module + will be called stts751. + ++config SENSORS_SFCTEMP ++ tristate "Starfive JH71x0 temperature sensor" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ help ++ If you say yes here you get support for temperature sensor ++ on the Starfive JH71x0 SoCs. ++ ++ This driver can also be built as a module. If so, the module ++ will be called sfctemp. ++ + config SENSORS_SMM665 + tristate "Summit Microelectronics SMM665" + depends on I2C +diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile +index 88712b5031c8..386f4debe68b 100644 +--- a/drivers/hwmon/Makefile ++++ b/drivers/hwmon/Makefile +@@ -181,6 +181,7 @@ obj-$(CONFIG_SENSORS_SBRMI) += sbrmi.o + obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o + obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o + obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o ++obj-$(CONFIG_SENSORS_SFCTEMP) += sfctemp.o + obj-$(CONFIG_SENSORS_SL28CPLD) += sl28cpld-hwmon.o + obj-$(CONFIG_SENSORS_SHT15) += sht15.o + obj-$(CONFIG_SENSORS_SHT21) += sht21.o +diff --git a/drivers/hwmon/sfctemp.c b/drivers/hwmon/sfctemp.c +new file mode 100644 +index 000000000000..d7484e2b8100 +--- /dev/null ++++ b/drivers/hwmon/sfctemp.c +@@ -0,0 +1,331 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2021 Emil Renner Berthing ++ * Copyright (C) 2021 Samin Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * TempSensor reset. The RSTN can be de-asserted once the analog core has ++ * powered up. Trst(min 100ns) ++ * 0:reset 1:de-assert ++ */ ++#define SFCTEMP_RSTN BIT(0) ++ ++/* ++ * TempSensor analog core power down. The analog core will be powered up ++ * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the ++ * analog core is powered up. ++ * 0:power up 1:power down ++ */ ++#define SFCTEMP_PD BIT(1) ++ ++/* ++ * TempSensor start conversion enable. ++ * 0:disable 1:enable ++ */ ++#define SFCTEMP_RUN BIT(2) ++ ++/* ++ * TempSensor conversion value output. ++ * Temp(C)=DOUT*Y/4094 - K ++ */ ++#define SFCTEMP_DOUT_POS 16 ++#define SFCTEMP_DOUT_MSK GENMASK(27, 16) ++ ++/* DOUT to Celcius conversion constants */ ++#define SFCTEMP_Y1000 237500L ++#define SFCTEMP_Z 4094L ++#define SFCTEMP_K1000 81100L ++ ++struct sfctemp { ++ /* serialize access to hardware register and enabled below */ ++ struct mutex lock; ++ void __iomem *regs; ++ struct clk *clk_sense; ++ struct clk *clk_bus; ++ struct reset_control *rst_sense; ++ struct reset_control *rst_bus; ++ bool enabled; ++}; ++ ++static void sfctemp_power_up(struct sfctemp *sfctemp) ++{ ++ /* make sure we're powered down first */ ++ writel(SFCTEMP_PD, sfctemp->regs); ++ udelay(1); ++ ++ writel(0, sfctemp->regs); ++ /* wait t_pu(50us) + t_rst(100ns) */ ++ usleep_range(60, 200); ++ ++ /* de-assert reset */ ++ writel(SFCTEMP_RSTN, sfctemp->regs); ++ udelay(1); /* wait t_su(500ps) */ ++} ++ ++static void sfctemp_power_down(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_PD, sfctemp->regs); ++} ++ ++static void sfctemp_run(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs); ++ udelay(1); ++} ++ ++static void sfctemp_stop(struct sfctemp *sfctemp) ++{ ++ writel(SFCTEMP_RSTN, sfctemp->regs); ++} ++ ++static int sfctemp_enable(struct sfctemp *sfctemp) ++{ ++ int ret = 0; ++ ++ mutex_lock(&sfctemp->lock); ++ if (sfctemp->enabled) ++ goto done; ++ ++ ret = clk_prepare_enable(sfctemp->clk_bus); ++ if (ret) ++ goto err; ++ ret = reset_control_deassert(sfctemp->rst_bus); ++ if (ret) ++ goto err_disable_bus; ++ ++ ret = clk_prepare_enable(sfctemp->clk_sense); ++ if (ret) ++ goto err_assert_bus; ++ ret = reset_control_deassert(sfctemp->rst_sense); ++ if (ret) ++ goto err_disable_sense; ++ ++ sfctemp_power_up(sfctemp); ++ sfctemp_run(sfctemp); ++ sfctemp->enabled = true; ++done: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++ ++err_disable_sense: ++ clk_disable_unprepare(sfctemp->clk_sense); ++err_assert_bus: ++ reset_control_assert(sfctemp->rst_bus); ++err_disable_bus: ++ clk_disable_unprepare(sfctemp->clk_bus); ++err: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++} ++ ++static int sfctemp_disable(struct sfctemp *sfctemp) ++{ ++ mutex_lock(&sfctemp->lock); ++ if (!sfctemp->enabled) ++ goto done; ++ ++ sfctemp_stop(sfctemp); ++ sfctemp_power_down(sfctemp); ++ reset_control_assert(sfctemp->rst_sense); ++ clk_disable_unprepare(sfctemp->clk_sense); ++ reset_control_assert(sfctemp->rst_bus); ++ clk_disable_unprepare(sfctemp->clk_bus); ++ sfctemp->enabled = false; ++done: ++ mutex_unlock(&sfctemp->lock); ++ return 0; ++} ++ ++static void sfctemp_disable_action(void *data) ++{ ++ sfctemp_disable(data); ++} ++ ++static int sfctemp_convert(struct sfctemp *sfctemp, long *val) ++{ ++ int ret; ++ ++ mutex_lock(&sfctemp->lock); ++ if (!sfctemp->enabled) { ++ ret = -ENODATA; ++ goto out; ++ } ++ ++ /* calculate temperature in milli Celcius */ ++ *val = (long)((readl(sfctemp->regs) & SFCTEMP_DOUT_MSK) >> SFCTEMP_DOUT_POS) ++ * SFCTEMP_Y1000 / SFCTEMP_Z - SFCTEMP_K1000; ++ ++ ret = 0; ++out: ++ mutex_unlock(&sfctemp->lock); ++ return ret; ++} ++ ++static umode_t sfctemp_is_visible(const void *data, enum hwmon_sensor_types type, ++ u32 attr, int channel) ++{ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ return 0644; ++ case hwmon_temp_input: ++ return 0444; ++ default: ++ return 0; ++ } ++ default: ++ return 0; ++ } ++} ++ ++static int sfctemp_read(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long *val) ++{ ++ struct sfctemp *sfctemp = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ *val = sfctemp->enabled; ++ return 0; ++ case hwmon_temp_input: ++ return sfctemp_convert(sfctemp, val); ++ default: ++ return -EINVAL; ++ } ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int sfctemp_write(struct device *dev, enum hwmon_sensor_types type, ++ u32 attr, int channel, long val) ++{ ++ struct sfctemp *sfctemp = dev_get_drvdata(dev); ++ ++ switch (type) { ++ case hwmon_temp: ++ switch (attr) { ++ case hwmon_temp_enable: ++ if (val == 0) ++ return sfctemp_disable(sfctemp); ++ if (val == 1) ++ return sfctemp_enable(sfctemp); ++ return -EINVAL; ++ default: ++ return -EINVAL; ++ } ++ default: ++ return -EINVAL; ++ } ++} ++ ++static const struct hwmon_channel_info *sfctemp_info[] = { ++ HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), ++ HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT), ++ NULL ++}; ++ ++static const struct hwmon_ops sfctemp_hwmon_ops = { ++ .is_visible = sfctemp_is_visible, ++ .read = sfctemp_read, ++ .write = sfctemp_write, ++}; ++ ++static const struct hwmon_chip_info sfctemp_chip_info = { ++ .ops = &sfctemp_hwmon_ops, ++ .info = sfctemp_info, ++}; ++ ++static int sfctemp_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device *hwmon_dev; ++ struct sfctemp *sfctemp; ++ int ret; ++ ++ sfctemp = devm_kzalloc(dev, sizeof(*sfctemp), GFP_KERNEL); ++ if (!sfctemp) ++ return -ENOMEM; ++ ++ dev_set_drvdata(dev, sfctemp); ++ mutex_init(&sfctemp->lock); ++ ++ sfctemp->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(sfctemp->regs)) ++ return PTR_ERR(sfctemp->regs); ++ ++ sfctemp->clk_sense = devm_clk_get(dev, "sense"); ++ if (IS_ERR(sfctemp->clk_sense)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_sense), ++ "error getting sense clock\n"); ++ ++ sfctemp->clk_bus = devm_clk_get(dev, "bus"); ++ if (IS_ERR(sfctemp->clk_bus)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_bus), ++ "error getting bus clock\n"); ++ ++ sfctemp->rst_sense = devm_reset_control_get_exclusive(dev, "sense"); ++ if (IS_ERR(sfctemp->rst_sense)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_sense), ++ "error getting sense reset\n"); ++ ++ sfctemp->rst_bus = devm_reset_control_get_exclusive(dev, "bus"); ++ if (IS_ERR(sfctemp->rst_bus)) ++ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_bus), ++ "error getting busreset\n"); ++ ++ ret = reset_control_assert(sfctemp->rst_sense); ++ if (ret) ++ return dev_err_probe(dev, ret, "error asserting sense reset\n"); ++ ++ ret = reset_control_assert(sfctemp->rst_bus); ++ if (ret) ++ return dev_err_probe(dev, ret, "error asserting bus reset\n"); ++ ++ ret = devm_add_action(dev, sfctemp_disable_action, sfctemp); ++ if (ret) ++ return ret; ++ ++ ret = sfctemp_enable(sfctemp); ++ if (ret) ++ return dev_err_probe(dev, ret, "error enabling temperature sensor: %d\n", ret); ++ ++ hwmon_dev = devm_hwmon_device_register_with_info(dev, "sfctemp", sfctemp, ++ &sfctemp_chip_info, NULL); ++ return PTR_ERR_OR_ZERO(hwmon_dev); ++} ++ ++static const struct of_device_id sfctemp_of_match[] = { ++ { .compatible = "starfive,jh7100-temp" }, ++ { .compatible = "starfive,jh7110-temp" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, sfctemp_of_match); ++ ++static struct platform_driver sfctemp_driver = { ++ .probe = sfctemp_probe, ++ .driver = { ++ .name = "sfctemp", ++ .of_match_table = sfctemp_of_match, ++ }, ++}; ++module_platform_driver(sfctemp_driver); ++ ++MODULE_AUTHOR("Emil Renner Berthing"); ++MODULE_DESCRIPTION("StarFive JH71x0 temperature sensor driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0031-dt-bindings-qspi-cdns-qspi-nor-constrain-minItems-ma.patch b/srcpkgs/linux6.3/patches/0031-dt-bindings-qspi-cdns-qspi-nor-constrain-minItems-ma.patch new file mode 100644 index 0000000000000..fd58d7713c375 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0031-dt-bindings-qspi-cdns-qspi-nor-constrain-minItems-ma.patch @@ -0,0 +1,83 @@ +From 1f2839a2c476b8261eb59b1487128d52a9478ffa Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Thu, 2 Mar 2023 18:52:20 +0800 +Subject: [PATCH 31/84] dt-bindings: qspi: cdns,qspi-nor: constrain + minItems/maxItems of resets + +The QSPI controller needs three reset items to work properly on JH7110 SoC, +so there is need to change the maxItems's value to 3 and add minItems +whose value is equal to 2. Other platforms do not have this constraint. + +Signed-off-by: William Qiu +--- + .../bindings/spi/cdns,qspi-nor.yaml | 37 +++++++++++++++++-- + 1 file changed, 33 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +index 5c01db128be0..b310069762dd 100644 +--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml ++++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +@@ -19,6 +19,33 @@ allOf: + then: + required: + - power-domains ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: starfive,jh7110-qspi ++ then: ++ properties: ++ resets: ++ minItems: 2 ++ maxItems: 3 ++ ++ reset-names: ++ minItems: 2 ++ maxItems: 3 ++ items: ++ enum: [ qspi, qspi-ocp, rstc_ref ] ++ ++ else: ++ properties: ++ resets: ++ maxItems: 2 ++ ++ reset-names: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ enum: [ qspi, qspi-ocp ] + + properties: + compatible: +@@ -30,6 +57,7 @@ properties: + - intel,lgm-qspi + - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi ++ - starfive,jh7110-qspi + - const: cdns,qspi-nor + - const: cdns,qspi-nor + +@@ -79,13 +107,14 @@ properties: + maxItems: 1 + + resets: +- maxItems: 2 ++ minItems: 2 ++ maxItems: 3 + + reset-names: +- minItems: 1 +- maxItems: 2 ++ minItems: 2 ++ maxItems: 3 + items: +- enum: [ qspi, qspi-ocp ] ++ enum: [ qspi, qspi-ocp, rstc_ref ] + + required: + - compatible +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0032-spi-cadence-quadspi-Add-support-for-StarFive-JH7110-.patch b/srcpkgs/linux6.3/patches/0032-spi-cadence-quadspi-Add-support-for-StarFive-JH7110-.patch new file mode 100644 index 0000000000000..ed93d76cd9cd7 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0032-spi-cadence-quadspi-Add-support-for-StarFive-JH7110-.patch @@ -0,0 +1,86 @@ +From ab380f594fb3f99276b8d1389ac6ae98ed142c62 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Thu, 2 Mar 2023 18:52:21 +0800 +Subject: [PATCH 32/84] spi: cadence-quadspi: Add support for StarFive JH7110 + QSPI + +Add QSPI reset operation in device probe and add RISCV support to +QUAD SPI Kconfig. + +Co-developed-by: Ziv Xu +Signed-off-by: Ziv Xu +Signed-off-by: William Qiu +--- + drivers/spi/Kconfig | 2 +- + drivers/spi/spi-cadence-quadspi.c | 21 ++++++++++++++++++++- + 2 files changed, 21 insertions(+), 2 deletions(-) + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 47bbba04fe3a..839d426a741c 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -239,7 +239,7 @@ config SPI_CADENCE + + config SPI_CADENCE_QUADSPI + tristate "Cadence Quad SPI controller" +- depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST) ++ depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST) + help + Enable support for the Cadence Quad SPI Flash controller. + +diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c +index 64b6a460d739..c789fa9e2177 100644 +--- a/drivers/spi/spi-cadence-quadspi.c ++++ b/drivers/spi/spi-cadence-quadspi.c +@@ -1615,7 +1615,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi) + static int cqspi_probe(struct platform_device *pdev) + { + const struct cqspi_driver_platdata *ddata; +- struct reset_control *rstc, *rstc_ocp; ++ struct reset_control *rstc, *rstc_ocp, *rstc_ref; + struct device *dev = &pdev->dev; + struct spi_master *master; + struct resource *res_ahb; +@@ -1705,6 +1705,17 @@ static int cqspi_probe(struct platform_device *pdev) + goto probe_reset_failed; + } + ++ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { ++ rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); ++ if (IS_ERR(rstc_ref)) { ++ ret = PTR_ERR(rstc_ref); ++ dev_err(dev, "Cannot get QSPI REF reset.\n"); ++ goto probe_reset_failed; ++ } ++ reset_control_assert(rstc_ref); ++ reset_control_deassert(rstc_ref); ++ } ++ + reset_control_assert(rstc); + reset_control_deassert(rstc); + +@@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { + .get_dma_status = cqspi_get_versal_dma_status, + }; + ++static const struct cqspi_driver_platdata jh7110_qspi = { ++ .quirks = CQSPI_DISABLE_DAC_MODE, ++}; ++ + static const struct of_device_id cqspi_dt_ids[] = { + { + .compatible = "cdns,qspi-nor", +@@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { + .compatible = "intel,socfpga-qspi", + .data = &socfpga_qspi, + }, ++ { ++ .compatible = "starfive,jh7110-qspi", ++ .data = &jh7110_qspi, ++ }, + { /* end of table */ } + }; + +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0033-riscv-dts-starfive-Enable-axp15060-pmic-for-cpufreq.patch b/srcpkgs/linux6.3/patches/0033-riscv-dts-starfive-Enable-axp15060-pmic-for-cpufreq.patch new file mode 100644 index 0000000000000..016c10f54fee9 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0033-riscv-dts-starfive-Enable-axp15060-pmic-for-cpufreq.patch @@ -0,0 +1,42 @@ +From 3d5f892a47b9ce9c43200eef53f17f13ce7afd62 Mon Sep 17 00:00:00 2001 +From: Mason Huo +Date: Fri, 21 Apr 2023 11:14:29 +0800 +Subject: [PATCH 33/84] riscv: dts: starfive: Enable axp15060 pmic for cpufreq + +The VisionFive 2 board has an embedded pmic axp15060, +which supports the cpu DVFS through the dcdc2 regulator. +This patch enables axp15060 pmic and configs the dcdc2. + +Signed-off-by: Mason Huo +--- + .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 2a6d81609284..cca1c8040801 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -114,6 +114,20 @@ &i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; ++ ++ axp15060: pmic@36 { ++ compatible = "x-powers,axp15060"; ++ reg = <0x36>; ++ ++ regulators { ++ vdd_cpu: dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1540000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ }; ++ }; + }; + + &i2c6 { +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0034-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch b/srcpkgs/linux6.3/patches/0034-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch new file mode 100644 index 0000000000000..b2211706683ed --- /dev/null +++ b/srcpkgs/linux6.3/patches/0034-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch @@ -0,0 +1,29 @@ +From 2a693feb0950065624aa1be4a4f02cf649f76d65 Mon Sep 17 00:00:00 2001 +From: Mason Huo +Date: Fri, 21 Apr 2023 11:14:30 +0800 +Subject: [PATCH 34/84] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist + +Add the compatible strings for supporting the generic +cpufreq driver on the StarFive JH7110 SoC. + +Signed-off-by: Mason Huo +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index e85703651098..79537d0ed7cf 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -86,6 +86,8 @@ static const struct of_device_id allowlist[] __initconst = { + { .compatible = "st-ericsson,u9500", }, + { .compatible = "st-ericsson,u9540", }, + ++ { .compatible = "starfive,jh7110", }, ++ + { .compatible = "ti,omap2", }, + { .compatible = "ti,omap4", }, + { .compatible = "ti,omap5", }, +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0035-riscv-dts-starfive-Add-cpu-scaling-for-JH7110-SoC.patch b/srcpkgs/linux6.3/patches/0035-riscv-dts-starfive-Add-cpu-scaling-for-JH7110-SoC.patch new file mode 100644 index 0000000000000..53a7db5be2d2b --- /dev/null +++ b/srcpkgs/linux6.3/patches/0035-riscv-dts-starfive-Add-cpu-scaling-for-JH7110-SoC.patch @@ -0,0 +1,113 @@ +From c832f8d10317f1b3145ed5e138f801fdd94c8315 Mon Sep 17 00:00:00 2001 +From: Mason Huo +Date: Fri, 21 Apr 2023 11:14:31 +0800 +Subject: [PATCH 35/84] riscv: dts: starfive: Add cpu scaling for JH7110 SoC + +Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. +It supports up to 4 cpu frequency loads. + +Signed-off-by: Mason Huo +--- + .../jh7110-starfive-visionfive-2.dtsi | 16 +++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 33 +++++++++++++++++++ + 2 files changed, 49 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index cca1c8040801..43a9dbb839d2 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -227,3 +227,19 @@ &uart0 { + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&U74_1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_4 { ++ cpu-supply = <&vdd_cpu>; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 587aa6830c4b..90fd0eb52004 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -53,6 +53,9 @@ U74_1: cpu@1 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -79,6 +82,9 @@ U74_2: cpu@2 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -105,6 +111,9 @@ U74_3: cpu@3 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -131,6 +140,9 @@ U74_4: cpu@4 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -164,6 +176,27 @@ core4 { + }; + }; + ++ cpu_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-375000000 { ++ opp-hz = /bits/ 64 <375000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-750000000 { ++ opp-hz = /bits/ 64 <750000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1040000>; ++ }; ++ }; ++ + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0036-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch b/srcpkgs/linux6.3/patches/0036-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch new file mode 100644 index 0000000000000..942fbe2830423 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0036-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch @@ -0,0 +1,203 @@ +From b94b67196e07be3259041ebf8f59380e067c61b7 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:00 +0800 +Subject: [PATCH 36/84] dt-bindings: clock: Add StarFive JH7110 + System-Top-Group clock and reset generator + +Add bindings for the System-Top-Group clock and reset generator (STGCRG) +on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++ + 3 files changed, 144 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml +new file mode 100644 +index 000000000000..b64ccd84200a +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml +@@ -0,0 +1,82 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 System-Top-Group Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-stgcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Main Oscillator (24 MHz) ++ - description: HIFI4 core ++ - description: STG AXI/AHB ++ - description: USB (125 MHz) ++ - description: CPU Bus ++ - description: HIFI4 Axi ++ - description: NOC STG Bus ++ - description: APB Bus ++ ++ clock-names: ++ items: ++ - const: osc ++ - const: hifi4_core ++ - const: stg_axiahb ++ - const: usb_125m ++ - const: cpu_bus ++ - const: hifi4_axi ++ - const: nocstg_bus ++ - const: apb_bus ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - '#clock-cells' ++ - '#reset-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ stgcrg: clock-controller@10230000 { ++ compatible = "starfive,jh7110-stgcrg"; ++ reg = <0x10230000 0x10000>; ++ clocks = <&osc>, ++ <&syscrg JH7110_SYSCLK_HIFI4_CORE>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&syscrg JH7110_SYSCLK_CPU_BUS>, ++ <&syscrg JH7110_SYSCLK_HIFI4_AXI>, ++ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>; ++ clock-names = "osc", "hifi4_core", ++ "stg_axiahb", "usb_125m", ++ "cpu_bus", "hifi4_axi", ++ "nocstg_bus", "apb_bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 06257bfd9ac1..6c8e8b4cf1f6 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ + /* + * Copyright 2022 Emil Renner Berthing ++ * Copyright 2022 StarFive Technology Co., Ltd. + */ + + #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +@@ -218,4 +219,37 @@ + + #define JH7110_AONCLK_END 14 + ++/* STGCRG clocks */ ++#define JH7110_STGCLK_HIFI4_CLK_CORE 0 ++#define JH7110_STGCLK_USB0_APB 1 ++#define JH7110_STGCLK_USB0_UTMI_APB 2 ++#define JH7110_STGCLK_USB0_AXI 3 ++#define JH7110_STGCLK_USB0_LPM 4 ++#define JH7110_STGCLK_USB0_STB 5 ++#define JH7110_STGCLK_USB0_APP_125 6 ++#define JH7110_STGCLK_USB0_REFCLK 7 ++#define JH7110_STGCLK_PCIE0_AXI_MST0 8 ++#define JH7110_STGCLK_PCIE0_APB 9 ++#define JH7110_STGCLK_PCIE0_TL 10 ++#define JH7110_STGCLK_PCIE1_AXI_MST0 11 ++#define JH7110_STGCLK_PCIE1_APB 12 ++#define JH7110_STGCLK_PCIE1_TL 13 ++#define JH7110_STGCLK_PCIE_SLV_MAIN 14 ++#define JH7110_STGCLK_SEC_AHB 15 ++#define JH7110_STGCLK_SEC_MISC_AHB 16 ++#define JH7110_STGCLK_GRP0_MAIN 17 ++#define JH7110_STGCLK_GRP0_BUS 18 ++#define JH7110_STGCLK_GRP0_STG 19 ++#define JH7110_STGCLK_GRP1_MAIN 20 ++#define JH7110_STGCLK_GRP1_BUS 21 ++#define JH7110_STGCLK_GRP1_STG 22 ++#define JH7110_STGCLK_GRP1_HIFI 23 ++#define JH7110_STGCLK_E2_RTC 24 ++#define JH7110_STGCLK_E2_CORE 25 ++#define JH7110_STGCLK_E2_DBG 26 ++#define JH7110_STGCLK_DMA1P_AXI 27 ++#define JH7110_STGCLK_DMA1P_AHB 28 ++ ++#define JH7110_STGCLK_END 29 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index d78e38690ceb..4e96ab81dd8e 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ + /* + * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + + #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ +@@ -151,4 +152,31 @@ + + #define JH7110_AONRST_END 8 + ++/* STGCRG resets */ ++#define JH7110_STGRST_SYSCON 0 ++#define JH7110_STGRST_HIFI4_CORE 1 ++#define JH7110_STGRST_HIFI4_AXI 2 ++#define JH7110_STGRST_SEC_AHB 3 ++#define JH7110_STGRST_E24_CORE 4 ++#define JH7110_STGRST_DMA1P_AXI 5 ++#define JH7110_STGRST_DMA1P_AHB 6 ++#define JH7110_STGRST_USB0_AXI 7 ++#define JH7110_STGRST_USB0_APB 8 ++#define JH7110_STGRST_USB0_UTMI_APB 9 ++#define JH7110_STGRST_USB0_PWRUP 10 ++#define JH7110_STGRST_PCIE0_AXI_MST0 11 ++#define JH7110_STGRST_PCIE0_AXI_SLV0 12 ++#define JH7110_STGRST_PCIE0_AXI_SLV 13 ++#define JH7110_STGRST_PCIE0_BRG 14 ++#define JH7110_STGRST_PCIE0_CORE 15 ++#define JH7110_STGRST_PCIE0_APB 16 ++#define JH7110_STGRST_PCIE1_AXI_MST0 17 ++#define JH7110_STGRST_PCIE1_AXI_SLV0 18 ++#define JH7110_STGRST_PCIE1_AXI_SLV 19 ++#define JH7110_STGRST_PCIE1_BRG 20 ++#define JH7110_STGRST_PCIE1_CORE 21 ++#define JH7110_STGRST_PCIE1_APB 22 ++ ++#define JH7110_STGRST_END 23 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0037-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch b/srcpkgs/linux6.3/patches/0037-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch new file mode 100644 index 0000000000000..a5480135b202c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0037-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch @@ -0,0 +1,228 @@ +From f5c110f27d894ebaf8c102a31292a51feda7ed87 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 24 Apr 2023 21:54:01 +0800 +Subject: [PATCH 37/84] clk: starfive: Add StarFive JH7110 System-Top-Group + clock driver + +Add driver for the StarFive JH7110 System-Top-Group clock controller. + +Signed-off-by: Xingyu Wu +Co-developed-by: Xingyu Wu +Signed-off-by: Emil Renner Berthing +--- + drivers/clk/starfive/Kconfig | 11 ++ + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-stg.c | 173 ++++++++++++++++++ + 3 files changed, 185 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 71c1148ee5f6..a60abed21650 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -42,3 +42,14 @@ config CLK_STARFIVE_JH7110_AON + help + Say yes here to support the always-on clock controller on the + StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_STG ++ tristate "StarFive JH7110 System-Top-Group clock support" ++ depends on CLK_STARFIVE_JH7110_SYS ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the System-Top-Group clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index f3df7d957b1e..b81e97ee2659 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -6,3 +6,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c +new file mode 100644 +index 000000000000..dafcb7190592 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 System-Top-Group Clock Driver ++ * ++ * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0) ++#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1) ++#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2) ++#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3) ++#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4) ++#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5) ++#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6) ++#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7) ++#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8) ++ ++static const struct jh71x0_clk_data jh7110_stgclk_data[] = { ++ /* hifi4 */ ++ JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, ++ JH7110_STGCLK_HIFI4_CORE), ++ /* usb */ ++ JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), ++ JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), ++ JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), ++ JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), ++ /* pci-e */ ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ /* security */ ++ JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++ /* stg mtrx */ ++ JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_CPU_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, ++ JH7110_STGCLK_NOCSTG_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_CPU_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, ++ JH7110_STGCLK_NOCSTG_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, ++ JH7110_STGCLK_HIFI4_AXI), ++ /* e24_rvpi */ ++ JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), ++ JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), ++ /* dw_sgdma1p */ ++ JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++}; ++ ++static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_STGCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int jh7110_stgcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ for (idx = 0; idx < JH7110_STGCLK_END; idx++) { ++ u32 max = jh7110_stgclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_stgclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_stgclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = { ++ "osc", ++ "hifi4_core", ++ "stg_axiahb", ++ "usb_125m", ++ "cpu_bus", ++ "hifi4_axi", ++ "nocstg_bus", ++ "apb_bus" ++ }; ++ unsigned int i; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_stgclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_STGCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx < JH7110_STGCLK_EXT_END) ++ parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ return ret; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv); ++ if (ret) ++ return ret; ++ ++ return jh7110_reset_controller_register(priv, "rst-stg", 2); ++} ++ ++static const struct of_device_id jh7110_stgcrg_match[] = { ++ { .compatible = "starfive,jh7110-stgcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match); ++ ++static struct platform_driver jh7110_stgcrg_driver = { ++ .probe = jh7110_stgcrg_probe, ++ .driver = { ++ .name = "clk-starfive-jh7110-stg", ++ .of_match_table = jh7110_stgcrg_match, ++ }, ++}; ++module_platform_driver(jh7110_stgcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_AUTHOR("Emil Renner Berthing "); ++MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0038-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch b/srcpkgs/linux6.3/patches/0038-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch new file mode 100644 index 0000000000000..c78d35e41115a --- /dev/null +++ b/srcpkgs/linux6.3/patches/0038-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch @@ -0,0 +1,166 @@ +From c9a9077f3bb48304a9b8005746c14a5d4b374c56 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:02 +0800 +Subject: [PATCH 38/84] dt-bindings: clock: Add StarFive JH7110 + Image-Signal-Process clock and reset generator + +Add bindings for the Image-Signal-Process clock and reset +generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 18 ++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++ + 3 files changed, 121 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml +new file mode 100644 +index 000000000000..3b8b85be5cd0 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml +@@ -0,0 +1,87 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-ispcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: ISP Top core ++ - description: ISP Top Axi ++ - description: NOC ISP Bus ++ - description: external DVP ++ ++ clock-names: ++ items: ++ - const: isp_top_core ++ - const: isp_top_axi ++ - const: noc_bus_isp_axi ++ - const: dvp_clk ++ ++ resets: ++ items: ++ - description: ISP Top core ++ - description: ISP Top Axi ++ - description: NOC ISP Bus ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ power-domains: ++ maxItems: 1 ++ description: ++ ISP domain power ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - '#clock-cells' ++ - '#reset-cells' ++ - power-domains ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ ispcrg: clock-controller@19810000 { ++ compatible = "starfive,jh7110-ispcrg"; ++ reg = <0x19810000 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, ++ <&dvp_clk>; ++ clock-names = "isp_top_core", "isp_top_axi", ++ "noc_bus_isp_axi", "dvp_clk"; ++ resets = <&syscrg JH7110_SYSRST_ISP_TOP>, ++ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_ISP>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 6c8e8b4cf1f6..39acf30db491 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -252,4 +252,22 @@ + + #define JH7110_STGCLK_END 29 + ++/* ISPCRG clocks */ ++#define JH7110_ISPCLK_DOM4_APB_FUNC 0 ++#define JH7110_ISPCLK_MIPI_RX0_PXL 1 ++#define JH7110_ISPCLK_DVP_INV 2 ++#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 ++#define JH7110_ISPCLK_M31DPHY_REF_IN 4 ++#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 ++#define JH7110_ISPCLK_VIN_APB 6 ++#define JH7110_ISPCLK_VIN_SYS 7 ++#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 ++#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 ++#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 ++#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 ++#define JH7110_ISPCLK_VIN_P_AXI_WR 12 ++#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 ++ ++#define JH7110_ISPCLK_END 14 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index 4e96ab81dd8e..2c5d9dcefffa 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -179,4 +179,20 @@ + + #define JH7110_STGRST_END 23 + ++/* ISPCRG resets */ ++#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 ++#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 ++#define JH7110_ISPRST_M31DPHY_HW 2 ++#define JH7110_ISPRST_M31DPHY_B09_AON 3 ++#define JH7110_ISPRST_VIN_APB 4 ++#define JH7110_ISPRST_VIN_PIXEL_IF0 5 ++#define JH7110_ISPRST_VIN_PIXEL_IF1 6 ++#define JH7110_ISPRST_VIN_PIXEL_IF2 7 ++#define JH7110_ISPRST_VIN_PIXEL_IF3 8 ++#define JH7110_ISPRST_VIN_SYS 9 ++#define JH7110_ISPRST_VIN_P_AXI_RD 10 ++#define JH7110_ISPRST_VIN_P_AXI_WR 11 ++ ++#define JH7110_ISPRST_END 12 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0039-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch b/srcpkgs/linux6.3/patches/0039-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch new file mode 100644 index 0000000000000..6c50afa6d037f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0039-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch @@ -0,0 +1,305 @@ +From 999551e5b00dc4d9a723739e828cb28dadf692a0 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:03 +0800 +Subject: [PATCH 39/84] clk: starfive: Add StarFive JH7110 Image-Signal-Process + clock driver + +Add driver for the StarFive JH7110 Image-Signal-Process clock controller. +And these clock controllers should power on and enable the clocks from +SYSCRG first before registering. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 11 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-isp.c | 232 ++++++++++++++++++ + drivers/clk/starfive/clk-starfive-jh7110.h | 6 + + 4 files changed, 250 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index a60abed21650..be02eabebeff 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -53,3 +53,14 @@ config CLK_STARFIVE_JH7110_STG + help + Say yes here to support the System-Top-Group clock controller + on the StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_ISP ++ tristate "StarFive JH7110 Image-Signal-Process clock support" ++ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the Image-Signal-Process clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index b81e97ee2659..76fb9f8d628b 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c +new file mode 100644 +index 000000000000..7e51447060fe +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c +@@ -0,0 +1,232 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 Image-Signal-Process Clock Driver ++ * ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0) ++#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1) ++#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2) ++#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3) ++#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4) ++ ++static struct clk_bulk_data jh7110_isp_top_clks[] = { ++ { .id = "isp_top_core" }, ++ { .id = "isp_top_axi" } ++}; ++ ++static const struct jh71x0_clk_data jh7110_ispclk_data[] = { ++ /* syscon */ ++ JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, ++ JH7110_ISPCLK_ISP_TOP_AXI), ++ JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), ++ /* vin */ ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, ++ JH7110_ISPCLK_DOM4_APB_FUNC), ++ JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, ++ JH7110_ISPCLK_MIPI_RX0_PXL, ++ JH7110_ISPCLK_DVP_INV), ++ /* ispv2_top_wrapper */ ++ JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, ++ JH7110_ISPCLK_MIPI_RX0_PXL, ++ JH7110_ISPCLK_DVP_INV), ++}; ++ ++static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) ++{ ++ struct reset_control *top_rsts; ++ ++ /* The resets should be shared and other ISP modules will use its. */ ++ top_rsts = devm_reset_control_array_get_shared(priv->dev); ++ if (IS_ERR(top_rsts)) ++ return dev_err_probe(priv->dev, PTR_ERR(top_rsts), ++ "failed to get top resets\n"); ++ ++ return reset_control_deassert(top_rsts); ++} ++ ++static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_ISPCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++#ifdef CONFIG_PM ++static int jh7110_ispcrg_suspend(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); ++ ++ return 0; ++} ++ ++static int jh7110_ispcrg_resume(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); ++} ++#endif ++ ++static const struct dev_pm_ops jh7110_ispcrg_pm_ops = { ++ SET_RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL) ++}; ++ ++static int jh7110_ispcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ struct top_sysclk *top; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_ISPCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); ++ if (!top) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ top->top_clks = jh7110_isp_top_clks; ++ top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks); ++ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, "failed to get main clocks\n"); ++ dev_set_drvdata(priv->dev, top); ++ ++ /* enable power domain and clocks */ ++ pm_runtime_enable(priv->dev); ++ ret = pm_runtime_get_sync(priv->dev); ++ if (ret < 0) ++ return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); ++ ++ ret = jh7110_isp_top_rst_init(priv); ++ if (ret) ++ goto err_exit; ++ ++ for (idx = 0; idx < JH7110_ISPCLK_END; idx++) { ++ u32 max = jh7110_ispclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_ispclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_ispclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = { ++ "isp_top_core", ++ "isp_top_axi", ++ "noc_bus_isp_axi", ++ "dvp_clk" ++ }; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_ispclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_ISPCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else ++ parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ goto err_exit; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv); ++ if (ret) ++ goto err_exit; ++ ++ ret = jh7110_reset_controller_register(priv, "rst-isp", 3); ++ if (ret) ++ goto err_exit; ++ ++ return 0; ++ ++err_exit: ++ pm_runtime_put_sync(priv->dev); ++ pm_runtime_disable(priv->dev); ++ return ret; ++} ++ ++static int jh7110_ispcrg_remove(struct platform_device *pdev) ++{ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_ispcrg_match[] = { ++ { .compatible = "starfive,jh7110-ispcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match); ++ ++static struct platform_driver jh7110_ispcrg_driver = { ++ .probe = jh7110_ispcrg_probe, ++ .remove = jh7110_ispcrg_remove, ++ .driver = { ++ .name = "clk-starfive-jh7110-isp", ++ .of_match_table = jh7110_ispcrg_match, ++ .pm = &jh7110_ispcrg_pm_ops, ++ }, ++}; ++module_platform_driver(jh7110_ispcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h +index f29682b8d400..5425fd89394a 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110.h ++++ b/drivers/clk/starfive/clk-starfive-jh7110.h +@@ -4,6 +4,12 @@ + + #include "clk-starfive-jh71x0.h" + ++/* top clocks of ISP/VOUT domain from SYSCRG */ ++struct top_sysclk { ++ struct clk_bulk_data *top_clks; ++ int top_clks_num; ++}; ++ + int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, + const char *adev_name, + u32 adev_id); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0040-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch b/srcpkgs/linux6.3/patches/0040-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch new file mode 100644 index 0000000000000..b0be9d9caa22f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0040-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch @@ -0,0 +1,173 @@ +From 3f7b94ced90805710632d82e035561c96929aa5a Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:04 +0800 +Subject: [PATCH 40/84] dt-bindings: clock: Add StarFive JH7110 Video-Output + clock and reset generator + +Add bindings for the Video-Output clock and reset generator (VOUTCRG) +on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-voutcrg.yaml | 90 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++ + 3 files changed, 128 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml +new file mode 100644 +index 000000000000..af77bd8c86b1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml +@@ -0,0 +1,90 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Video-Output Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-voutcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Vout Top core ++ - description: Vout Top Ahb ++ - description: Vout Top Axi ++ - description: Vout Top HDMI MCLK ++ - description: I2STX0 BCLK ++ - description: external HDMI pixel ++ ++ clock-names: ++ items: ++ - const: vout_src ++ - const: vout_top_ahb ++ - const: vout_top_axi ++ - const: vout_top_hdmitx0_mclk ++ - const: i2stx0_bclk ++ - const: hdmitx0_pixelclk ++ ++ resets: ++ maxItems: 1 ++ description: Vout Top core ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ power-domains: ++ maxItems: 1 ++ description: ++ Vout domain power ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - '#clock-cells' ++ - '#reset-cells' ++ - power-domains ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ voutcrg: clock-controller@295C0000 { ++ compatible = "starfive,jh7110-voutcrg"; ++ reg = <0x295C0000 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, ++ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "vout_src", "vout_top_ahb", ++ "vout_top_axi", "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", "hdmitx0_pixelclk"; ++ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_VOUT>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 39acf30db491..016227c64a27 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -270,4 +270,26 @@ + + #define JH7110_ISPCLK_END 14 + ++/* VOUTCRG clocks */ ++#define JH7110_VOUTCLK_APB 0 ++#define JH7110_VOUTCLK_DC8200_PIX 1 ++#define JH7110_VOUTCLK_DSI_SYS 2 ++#define JH7110_VOUTCLK_TX_ESC 3 ++#define JH7110_VOUTCLK_DC8200_AXI 4 ++#define JH7110_VOUTCLK_DC8200_CORE 5 ++#define JH7110_VOUTCLK_DC8200_AHB 6 ++#define JH7110_VOUTCLK_DC8200_PIX0 7 ++#define JH7110_VOUTCLK_DC8200_PIX1 8 ++#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 ++#define JH7110_VOUTCLK_DSITX_APB 10 ++#define JH7110_VOUTCLK_DSITX_SYS 11 ++#define JH7110_VOUTCLK_DSITX_DPI 12 ++#define JH7110_VOUTCLK_DSITX_TXESC 13 ++#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 ++#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 ++#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 ++#define JH7110_VOUTCLK_HDMI_TX_SYS 17 ++ ++#define JH7110_VOUTCLK_END 18 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index 2c5d9dcefffa..eaf4a0d84f6a 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -195,4 +195,20 @@ + + #define JH7110_ISPRST_END 12 + ++/* VOUTCRG resets */ ++#define JH7110_VOUTRST_DC8200_AXI 0 ++#define JH7110_VOUTRST_DC8200_AHB 1 ++#define JH7110_VOUTRST_DC8200_CORE 2 ++#define JH7110_VOUTRST_DSITX_DPI 3 ++#define JH7110_VOUTRST_DSITX_APB 4 ++#define JH7110_VOUTRST_DSITX_RXESC 5 ++#define JH7110_VOUTRST_DSITX_SYS 6 ++#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 ++#define JH7110_VOUTRST_DSITX_TXESC 8 ++#define JH7110_VOUTRST_HDMI_TX_HDMI 9 ++#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 ++#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 ++ ++#define JH7110_VOUTRST_END 12 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0041-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch b/srcpkgs/linux6.3/patches/0041-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch new file mode 100644 index 0000000000000..9fa1b3c972ee3 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0041-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch @@ -0,0 +1,294 @@ +From 299c36725661e18784d6dc61fa1b26cd5a29a91c Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:05 +0800 +Subject: [PATCH 41/84] clk: starfive: Add StarFive JH7110 Video-Output clock + driver + +Add driver for the StarFive JH7110 Video-Output clock controller. +And these clock controllers should power on and enable the clocks from +SYSCRG first before registering. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 11 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-vout.c | 239 ++++++++++++++++++ + 3 files changed, 251 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index be02eabebeff..b0c7744965d7 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -64,3 +64,14 @@ config CLK_STARFIVE_JH7110_ISP + help + Say yes here to support the Image-Signal-Process clock controller + on the StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_VOUT ++ tristate "StarFive JH7110 Video-Output clock support" ++ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the Video-Output clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 76fb9f8d628b..841377e45bb6 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c +new file mode 100644 +index 000000000000..e5ef0c8c0494 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c +@@ -0,0 +1,239 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 Video-Output Clock Driver ++ * ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0) ++#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1) ++#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2) ++#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3) ++#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4) ++#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5) ++#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6) ++ ++static struct clk_bulk_data jh7110_vout_top_clks[] = { ++ { .id = "vout_src" }, ++ { .id = "vout_top_ahb" } ++}; ++ ++static const struct jh71x0_clk_data jh7110_voutclk_data[] = { ++ /* divider */ ++ JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), ++ JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), ++ JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ /* dc8200 */ ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ /* LCD */ ++ JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX0, ++ JH7110_VOUTCLK_DC8200_PIX1), ++ /* dsiTx */ ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), ++ JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), ++ /* mipitx DPHY */ ++ JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, ++ JH7110_VOUTCLK_TX_ESC), ++ /* hdmi */ ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, ++ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, ++ JH7110_VOUTCLK_I2STX0_BCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), ++}; ++ ++static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) ++{ ++ struct reset_control *top_rst; ++ ++ /* The reset should be shared and other Vout modules will use its. */ ++ top_rst = devm_reset_control_get_shared(priv->dev, NULL); ++ if (IS_ERR(top_rst)) ++ return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n"); ++ ++ return reset_control_deassert(top_rst); ++} ++ ++static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_VOUTCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++#ifdef CONFIG_PM ++static int jh7110_voutcrg_suspend(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); ++ ++ return 0; ++} ++ ++static int jh7110_voutcrg_resume(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); ++} ++#endif ++ ++static const struct dev_pm_ops jh7110_voutcrg_pm_ops = { ++ SET_RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL) ++}; ++ ++static int jh7110_voutcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ struct top_sysclk *top; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_VOUTCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); ++ if (!top) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ top->top_clks = jh7110_vout_top_clks; ++ top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks); ++ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n"); ++ dev_set_drvdata(priv->dev, top); ++ ++ /* enable power domain and clocks */ ++ pm_runtime_enable(priv->dev); ++ ret = pm_runtime_get_sync(priv->dev); ++ if (ret < 0) ++ return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); ++ ++ ret = jh7110_vout_top_rst_init(priv); ++ if (ret) ++ goto err_exit; ++ ++ for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) { ++ u32 max = jh7110_voutclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_voutclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_voutclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = { ++ "vout_src", ++ "vout_top_ahb", ++ "vout_top_axi", ++ "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", ++ "hdmitx0_pixelclk" ++ }; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_voutclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_VOUTCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx < JH7110_VOUTCLK_EXT_END) ++ parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ goto err_exit; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv); ++ if (ret) ++ goto err_exit; ++ ++ ret = jh7110_reset_controller_register(priv, "rst-vout", 4); ++ if (ret) ++ goto err_exit; ++ ++ return 0; ++ ++err_exit: ++ pm_runtime_put_sync(priv->dev); ++ pm_runtime_disable(priv->dev); ++ return ret; ++} ++ ++static int jh7110_voutcrg_remove(struct platform_device *pdev) ++{ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_voutcrg_match[] = { ++ { .compatible = "starfive,jh7110-voutcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match); ++ ++static struct platform_driver jh7110_voutcrg_driver = { ++ .probe = jh7110_voutcrg_probe, ++ .remove = jh7110_voutcrg_remove, ++ .driver = { ++ .name = "clk-starfive-jh7110-vout", ++ .of_match_table = jh7110_voutcrg_match, ++ .pm = &jh7110_voutcrg_pm_ops, ++ }, ++}; ++module_platform_driver(jh7110_voutcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0042-MAINTAINERS-Update-maintainer-of-JH71x0-clock-driver.patch b/srcpkgs/linux6.3/patches/0042-MAINTAINERS-Update-maintainer-of-JH71x0-clock-driver.patch new file mode 100644 index 0000000000000..9bbdcfdf3d848 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0042-MAINTAINERS-Update-maintainer-of-JH71x0-clock-driver.patch @@ -0,0 +1,28 @@ +From 6ab0fb6e3e545d043912691d711272f3eef5e18d Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:06 +0800 +Subject: [PATCH 42/84] MAINTAINERS: Update maintainer of JH71x0 clock drivers + +Add a new maintainer which is in charge of StarFive JH7110 +STG/ISP/VOUT clock drivers. + +Signed-off-by: Xingyu Wu +--- + MAINTAINERS | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 83d88a6fc1d8..625d259937e9 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19914,6 +19914,7 @@ F: arch/riscv/boot/dts/starfive/ + STARFIVE JH71X0 CLOCK DRIVERS + M: Emil Renner Berthing + M: Hal Feng ++M: Xingyu Wu + S: Maintained + F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml + F: drivers/clk/starfive/clk-starfive-jh71* +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0043-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch b/srcpkgs/linux6.3/patches/0043-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch new file mode 100644 index 0000000000000..bdd71cea5cabc --- /dev/null +++ b/srcpkgs/linux6.3/patches/0043-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch @@ -0,0 +1,66 @@ +From 5929ccc31a984132dbeadb6d055db3dc2d3b2747 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:07 +0800 +Subject: [PATCH 43/84] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT + resets support + +Add new struct members and auxiliary_device_id of resets to support +System-Top-Group, Image-Signal-Process and Video-Output on the StarFive +JH7110 SoC. + +Signed-off-by: Xingyu Wu +--- + .../reset/starfive/reset-starfive-jh7110.c | 30 +++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c +index c1b3a490d951..4eb2da4a22c4 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7110.c ++++ b/drivers/reset/starfive/reset-starfive-jh7110.c +@@ -29,6 +29,24 @@ static const struct jh7110_reset_info jh7110_aon_info = { + .status_offset = 0x3C, + }; + ++static const struct jh7110_reset_info jh7110_stg_info = { ++ .nr_resets = JH7110_STGRST_END, ++ .assert_offset = 0x74, ++ .status_offset = 0x78, ++}; ++ ++static const struct jh7110_reset_info jh7110_isp_info = { ++ .nr_resets = JH7110_ISPRST_END, ++ .assert_offset = 0x38, ++ .status_offset = 0x3C, ++}; ++ ++static const struct jh7110_reset_info jh7110_vout_info = { ++ .nr_resets = JH7110_VOUTRST_END, ++ .assert_offset = 0x48, ++ .status_offset = 0x4C, ++}; ++ + static int jh7110_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) + { +@@ -55,6 +73,18 @@ static const struct auxiliary_device_id jh7110_reset_ids[] = { + .name = "clk_starfive_jh7110_sys.rst-aon", + .driver_data = (kernel_ulong_t)&jh7110_aon_info, + }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-stg", ++ .driver_data = (kernel_ulong_t)&jh7110_stg_info, ++ }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-isp", ++ .driver_data = (kernel_ulong_t)&jh7110_isp_info, ++ }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-vout", ++ .driver_data = (kernel_ulong_t)&jh7110_vout_info, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0044-riscv-dts-starfive-jh7110-Add-DVP-and-HDMI-TX-pixel-.patch b/srcpkgs/linux6.3/patches/0044-riscv-dts-starfive-jh7110-Add-DVP-and-HDMI-TX-pixel-.patch new file mode 100644 index 0000000000000..f7e0bbebb8dcc --- /dev/null +++ b/srcpkgs/linux6.3/patches/0044-riscv-dts-starfive-jh7110-Add-DVP-and-HDMI-TX-pixel-.patch @@ -0,0 +1,74 @@ +From 48de6c50a7e768361fd604574acf8403a68e904d Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:08 +0800 +Subject: [PATCH 44/84] riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel + external clocks + +Add DVP and HDMI TX pixel external fixed clocks and the rates are +74.25MHz and 297MHz. + +Signed-off-by: Xingyu Wu +--- + .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 8 ++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ + 2 files changed, 20 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 43a9dbb839d2..4cd9b133d0dd 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -38,6 +38,10 @@ gpio-restart { + }; + }; + ++&dvp_clk { ++ clock-frequency = <74250000>; ++}; ++ + &gmac0_rgmii_rxin { + clock-frequency = <125000000>; + }; +@@ -54,6 +58,10 @@ &gmac1_rmii_refin { + clock-frequency = <50000000>; + }; + ++&hdmitx0_pixelclk { ++ clock-frequency = <297000000>; ++}; ++ + &i2srx_bclk_ext { + clock-frequency = <12288000>; + }; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 90fd0eb52004..c45222c6230a 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -197,6 +197,12 @@ opp-1500000000 { + }; + }; + ++ dvp_clk: dvp-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "dvp_clk"; ++ #clock-cells = <0>; ++ }; ++ + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; +@@ -221,6 +227,12 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { + #clock-cells = <0>; + }; + ++ hdmitx0_pixelclk: hdmitx0-pixel-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "hdmitx0_pixelclk"; ++ #clock-cells = <0>; ++ }; ++ + i2srx_bclk_ext: i2srx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_bclk_ext"; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0045-riscv-dts-starfive-jh7110-Add-STGCRG-ISPCRG-VOUTCRG-.patch b/srcpkgs/linux6.3/patches/0045-riscv-dts-starfive-jh7110-Add-STGCRG-ISPCRG-VOUTCRG-.patch new file mode 100644 index 0000000000000..0994089c0e868 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0045-riscv-dts-starfive-jh7110-Add-STGCRG-ISPCRG-VOUTCRG-.patch @@ -0,0 +1,98 @@ +From 65ff9404fa8f927bd99476457775ccea7a320e7a Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Mon, 24 Apr 2023 21:54:09 +0800 +Subject: [PATCH 45/84] riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG + nodes + +Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 +System-Top-Group, Image-Signal-Process and Video-Output +clock and reset drivers for the JH7110 RISC-V SoC. + +Reviewed-by: Conor Dooley +Signed-off-by: Xingyu Wu +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 55 ++++++++++++++++++++++++ + 1 file changed, 55 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index c45222c6230a..7df6094dd151 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -6,6 +6,7 @@ + + /dts-v1/; + #include ++#include + #include + + / { +@@ -398,6 +399,25 @@ i2c2: i2c@10050000 { + status = "disabled"; + }; + ++ stgcrg: clock-controller@10230000 { ++ compatible = "starfive,jh7110-stgcrg"; ++ reg = <0x0 0x10230000 0x0 0x10000>; ++ clocks = <&osc>, ++ <&syscrg JH7110_SYSCLK_HIFI4_CORE>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&syscrg JH7110_SYSCLK_CPU_BUS>, ++ <&syscrg JH7110_SYSCLK_HIFI4_AXI>, ++ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>; ++ clock-names = "osc", "hifi4_core", ++ "stg_axiahb", "usb_125m", ++ "cpu_bus", "hifi4_axi", ++ "nocstg_bus", "apb_bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; +@@ -561,5 +581,40 @@ aongpio: pinctrl@17020000 { + gpio-controller; + #gpio-cells = <2>; + }; ++ ++ ispcrg: clock-controller@19810000 { ++ compatible = "starfive,jh7110-ispcrg"; ++ reg = <0x0 0x19810000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, ++ <&dvp_clk>; ++ clock-names = "isp_top_core", "isp_top_axi", ++ "noc_bus_isp_axi", "dvp_clk"; ++ resets = <&syscrg JH7110_SYSRST_ISP_TOP>, ++ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_ISP>; ++ }; ++ ++ voutcrg: clock-controller@295c0000 { ++ compatible = "starfive,jh7110-voutcrg"; ++ reg = <0x0 0x295c0000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, ++ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "vout_src", "vout_top_ahb", ++ "vout_top_axi", "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", "hdmitx0_pixelclk"; ++ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_VOUT>; ++ }; + }; + }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0046-dt-bindings-crypto-Add-StarFive-crypto-module.patch b/srcpkgs/linux6.3/patches/0046-dt-bindings-crypto-Add-StarFive-crypto-module.patch new file mode 100644 index 0000000000000..033f18ec74ae8 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0046-dt-bindings-crypto-Add-StarFive-crypto-module.patch @@ -0,0 +1,95 @@ +From 4b20fc5fa829003777231944db4523ae07b641b4 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Thu, 4 May 2023 15:33:57 +0800 +Subject: [PATCH 46/84] dt-bindings: crypto: Add StarFive crypto module + +Add documentation to describe StarFive cryptographic engine. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +Reviewed-by: Rob Herring +--- + .../crypto/starfive,jh7110-crypto.yaml | 70 +++++++++++++++++++ + 1 file changed, 70 insertions(+) + create mode 100644 Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml + +diff --git a/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml +new file mode 100644 +index 000000000000..71a2876bd6e4 +--- /dev/null ++++ b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml +@@ -0,0 +1,70 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive Cryptographic Module ++ ++maintainers: ++ - Jia Jie Ho ++ - William Qiu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-crypto ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Hardware reference clock ++ - description: AHB reference clock ++ ++ clock-names: ++ items: ++ - const: hclk ++ - const: ahb ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++ dmas: ++ items: ++ - description: TX DMA channel ++ - description: RX DMA channel ++ ++ dma-names: ++ items: ++ - const: tx ++ - const: rx ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - dmas ++ - dma-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ crypto: crypto@16000000 { ++ compatible = "starfive,jh7110-crypto"; ++ reg = <0x16000000 0x4000>; ++ clocks = <&clk 15>, <&clk 16>; ++ clock-names = "hclk", "ahb"; ++ interrupts = <28>; ++ resets = <&reset 3>; ++ dmas = <&dma 1 2>, ++ <&dma 0 2>; ++ dma-names = "tx", "rx"; ++ }; ++... +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0047-crypto-starfive-Add-crypto-engine-support.patch b/srcpkgs/linux6.3/patches/0047-crypto-starfive-Add-crypto-engine-support.patch new file mode 100644 index 0000000000000..adf313e168350 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0047-crypto-starfive-Add-crypto-engine-support.patch @@ -0,0 +1,355 @@ +From 3aed66625f5e2d4be6c5b4704c8e5c5da08fbb72 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Thu, 4 May 2023 15:33:58 +0800 +Subject: [PATCH 47/84] crypto: starfive - Add crypto engine support + +Adding device probe and DMA init for StarFive cryptographic module. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +--- + drivers/crypto/Kconfig | 1 + + drivers/crypto/Makefile | 1 + + drivers/crypto/starfive/Kconfig | 17 +++ + drivers/crypto/starfive/Makefile | 4 + + drivers/crypto/starfive/jh7110-cryp.c | 201 ++++++++++++++++++++++++++ + drivers/crypto/starfive/jh7110-cryp.h | 63 ++++++++ + 6 files changed, 287 insertions(+) + create mode 100644 drivers/crypto/starfive/Kconfig + create mode 100644 drivers/crypto/starfive/Makefile + create mode 100644 drivers/crypto/starfive/jh7110-cryp.c + create mode 100644 drivers/crypto/starfive/jh7110-cryp.h + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index 3b2516d1433f..c9b6a8747fa1 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -822,5 +822,6 @@ config CRYPTO_DEV_SA2UL + + source "drivers/crypto/keembay/Kconfig" + source "drivers/crypto/aspeed/Kconfig" ++source "drivers/crypto/starfive/Kconfig" + + endif # CRYPTO_HW +diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile +index 476f1a25ca32..5ff5242a1824 100644 +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -52,3 +52,4 @@ obj-y += xilinx/ + obj-y += hisilicon/ + obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ + obj-y += keembay/ ++obj-y += starfive/ +diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig +new file mode 100644 +index 000000000000..2436e93d27ef +--- /dev/null ++++ b/drivers/crypto/starfive/Kconfig +@@ -0,0 +1,17 @@ ++# ++# StarFive crypto drivers configuration ++# ++ ++config CRYPTO_DEV_JH7110 ++ tristate "StarFive JH7110 cryptographic engine driver" ++ depends on SOC_STARFIVE ++ select CRYPTO_ENGINE ++ select ARM_AMBA ++ select DMADEVICES ++ select AMBA_PL08X ++ help ++ Support for StarFive JH7110 crypto hardware acceleration engine. ++ This module provides acceleration for public key algo, ++ skciphers, AEAD and hash functions. ++ ++ If you choose 'M' here, this module will be called jh7110-crypto. +diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Makefile +new file mode 100644 +index 000000000000..41221acaee39 +--- /dev/null ++++ b/drivers/crypto/starfive/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj-$(CONFIG_CRYPTO_DEV_JH7110) += jh7110-crypto.o ++jh7110-crypto-objs := jh7110-cryp.o +diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c +new file mode 100644 +index 000000000000..4b2505c23168 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-cryp.c +@@ -0,0 +1,201 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cryptographic API. ++ * ++ * Support for StarFive hardware cryptographic engine. ++ * Copyright (c) 2022 StarFive Technology ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "jh7110-cryp.h" ++ ++#define DRIVER_NAME "jh7110-crypto" ++ ++struct starfive_dev_list { ++ struct list_head dev_list; ++ spinlock_t lock; /* protect dev_list */ ++}; ++ ++static struct starfive_dev_list dev_list = { ++ .dev_list = LIST_HEAD_INIT(dev_list.dev_list), ++ .lock = __SPIN_LOCK_UNLOCKED(dev_list.lock), ++}; ++ ++struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = NULL, *tmp; ++ ++ spin_lock_bh(&dev_list.lock); ++ if (!ctx->cryp) { ++ list_for_each_entry(tmp, &dev_list.dev_list, list) { ++ cryp = tmp; ++ break; ++ } ++ ctx->cryp = cryp; ++ } else { ++ cryp = ctx->cryp; ++ } ++ ++ spin_unlock_bh(&dev_list.lock); ++ ++ return cryp; ++} ++ ++static int starfive_dma_init(struct starfive_cryp_dev *cryp) ++{ ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ dma_cap_set(DMA_SLAVE, mask); ++ ++ cryp->tx = dma_request_chan(cryp->dev, "tx"); ++ if (IS_ERR(cryp->tx)) ++ return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx), ++ "Error requesting tx dma channel.\n"); ++ ++ cryp->rx = dma_request_chan(cryp->dev, "rx"); ++ if (IS_ERR(cryp->rx)) { ++ dma_release_channel(cryp->tx); ++ return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx), ++ "Error requesting rx dma channel.\n"); ++ } ++ ++ return 0; ++} ++ ++static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) ++{ ++ dma_release_channel(cryp->tx); ++ dma_release_channel(cryp->rx); ++} ++ ++static int starfive_cryp_probe(struct platform_device *pdev) ++{ ++ struct starfive_cryp_dev *cryp; ++ struct resource *res; ++ int ret; ++ ++ cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); ++ if (!cryp) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, cryp); ++ cryp->dev = &pdev->dev; ++ ++ cryp->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(cryp->base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), ++ "Error remapping memory for platform device\n"); ++ ++ cryp->phys_base = res->start; ++ cryp->dma_maxburst = 32; ++ ++ cryp->hclk = devm_clk_get(&pdev->dev, "hclk"); ++ if (IS_ERR(cryp->hclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk), ++ "Error getting hardware reference clock\n"); ++ ++ cryp->ahb = devm_clk_get(&pdev->dev, "ahb"); ++ if (IS_ERR(cryp->ahb)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb), ++ "Error getting ahb reference clock\n"); ++ ++ cryp->rst = devm_reset_control_get_shared(cryp->dev, NULL); ++ if (IS_ERR(cryp->rst)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), ++ "Error getting hardware reset line\n"); ++ ++ clk_prepare_enable(cryp->hclk); ++ clk_prepare_enable(cryp->ahb); ++ reset_control_deassert(cryp->rst); ++ ++ spin_lock(&dev_list.lock); ++ list_add(&cryp->list, &dev_list.dev_list); ++ spin_unlock(&dev_list.lock); ++ ++ ret = starfive_dma_init(cryp); ++ if (ret) { ++ if (ret == -EPROBE_DEFER) ++ goto err_probe_defer; ++ else ++ goto err_dma_init; ++ } ++ ++ /* Initialize crypto engine */ ++ cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1); ++ if (!cryp->engine) { ++ ret = -ENOMEM; ++ goto err_engine; ++ } ++ ++ ret = crypto_engine_start(cryp->engine); ++ if (ret) ++ goto err_engine_start; ++ ++ return 0; ++ ++err_engine_start: ++ crypto_engine_exit(cryp->engine); ++err_engine: ++ starfive_dma_cleanup(cryp); ++err_dma_init: ++ spin_lock(&dev_list.lock); ++ list_del(&cryp->list); ++ spin_unlock(&dev_list.lock); ++ ++ clk_disable_unprepare(cryp->hclk); ++ clk_disable_unprepare(cryp->ahb); ++ reset_control_assert(cryp->rst); ++err_probe_defer: ++ return ret; ++} ++ ++static int starfive_cryp_remove(struct platform_device *pdev) ++{ ++ struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev); ++ ++ crypto_engine_stop(cryp->engine); ++ crypto_engine_exit(cryp->engine); ++ ++ starfive_dma_cleanup(cryp); ++ ++ spin_lock(&dev_list.lock); ++ list_del(&cryp->list); ++ spin_unlock(&dev_list.lock); ++ ++ clk_disable_unprepare(cryp->hclk); ++ clk_disable_unprepare(cryp->ahb); ++ reset_control_assert(cryp->rst); ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_dt_ids[] __maybe_unused = { ++ { .compatible = "starfive,jh7110-crypto", .data = NULL}, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, starfive_dt_ids); ++ ++static struct platform_driver starfive_cryp_driver = { ++ .probe = starfive_cryp_probe, ++ .remove = starfive_cryp_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .of_match_table = starfive_dt_ids, ++ }, ++}; ++ ++module_platform_driver(starfive_cryp_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("StarFive JH7110 Cryptographic Module"); +diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfive/jh7110-cryp.h +new file mode 100644 +index 000000000000..393efd38b098 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-cryp.h +@@ -0,0 +1,63 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __STARFIVE_STR_H__ ++#define __STARFIVE_STR_H__ ++ ++#include ++#include ++#include ++ ++#include ++ ++#define STARFIVE_ALG_CR_OFFSET 0x0 ++#define STARFIVE_ALG_FIFO_OFFSET 0x4 ++#define STARFIVE_IE_MASK_OFFSET 0x8 ++#define STARFIVE_IE_FLAG_OFFSET 0xc ++#define STARFIVE_DMA_IN_LEN_OFFSET 0x10 ++#define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 ++ ++#define STARFIVE_MSG_BUFFER_SIZE SZ_16K ++ ++union starfive_alg_cr { ++ u32 v; ++ struct { ++ u32 start :1; ++ u32 aes_dma_en :1; ++ u32 rsvd_0 :1; ++ u32 hash_dma_en :1; ++ u32 alg_done :1; ++ u32 rsvd_1 :3; ++ u32 clear :1; ++ u32 rsvd_2 :23; ++ }; ++}; ++ ++struct starfive_cryp_ctx { ++ struct crypto_engine_ctx enginectx; ++ struct starfive_cryp_dev *cryp; ++}; ++ ++struct starfive_cryp_dev { ++ struct list_head list; ++ struct device *dev; ++ ++ struct clk *hclk; ++ struct clk *ahb; ++ struct reset_control *rst; ++ ++ void __iomem *base; ++ phys_addr_t phys_base; ++ ++ u32 dma_maxburst; ++ struct dma_chan *tx; ++ struct dma_chan *rx; ++ struct dma_slave_config cfg_in; ++ struct dma_slave_config cfg_out; ++ ++ struct crypto_engine *engine; ++ ++ union starfive_alg_cr alg_cr; ++}; ++ ++struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx); ++ ++#endif +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0048-riscv-dts-starfive-Add-crypto-and-DMA-node-for-Visio.patch b/srcpkgs/linux6.3/patches/0048-riscv-dts-starfive-Add-crypto-and-DMA-node-for-Visio.patch new file mode 100644 index 0000000000000..48c38a9936b72 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0048-riscv-dts-starfive-Add-crypto-and-DMA-node-for-Visio.patch @@ -0,0 +1,58 @@ +From aa20d2ae9eeac633ff791c4617689e35dff190f3 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Thu, 4 May 2023 15:33:59 +0800 +Subject: [PATCH 48/84] riscv: dts: starfive: Add crypto and DMA node for + VisionFive 2 + +Add StarFive cryptographic module and dedicated DMA controller node to +VisionFive 2 SoCs. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +Acked-by: Palmer Dabbelt +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 28 ++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 7df6094dd151..df7a912b73b7 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -616,5 +616,33 @@ voutcrg: clock-controller@295c0000 { + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; ++ ++ sdma: dma@16008000 { ++ compatible = "arm,pl080", "arm,primecell"; ++ arm,primecell-periphid = <0x00041080>; ++ reg = <0x0 0x16008000 0x0 0x4000>; ++ interrupts = <29>; ++ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, ++ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; ++ clock-names = "hclk", "apb_pclk"; ++ resets = <&stgcrg JH7110_STGRST_SEC_AHB>; ++ lli-bus-interface-ahb1; ++ mem-bus-interface-ahb1; ++ memcpy-burst-size = <256>; ++ memcpy-bus-width = <32>; ++ #dma-cells = <2>; ++ }; ++ ++ crypto: crypto@16000000 { ++ compatible = "starfive,jh7110-crypto"; ++ reg = <0x0 0x16000000 0x0 0x4000>; ++ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, ++ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; ++ clock-names = "hclk", "ahb"; ++ interrupts = <28>; ++ resets = <&stgcrg JH7110_STGRST_SEC_AHB>; ++ dmas = <&sdma 1 2>, <&sdma 0 2>; ++ dma-names = "tx", "rx"; ++ }; + }; + }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0049-crypto-starfive-Add-hash-and-HMAC-support.patch b/srcpkgs/linux6.3/patches/0049-crypto-starfive-Add-hash-and-HMAC-support.patch new file mode 100644 index 0000000000000..c9125fb91237c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0049-crypto-starfive-Add-hash-and-HMAC-support.patch @@ -0,0 +1,1149 @@ +From d2af1a51db522bc4671f0c0dd31aac10deaceeaf Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Thu, 4 May 2023 15:34:00 +0800 +Subject: [PATCH 49/84] crypto: starfive - Add hash and HMAC support + +Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic +module. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +--- + drivers/crypto/starfive/Kconfig | 4 + + drivers/crypto/starfive/Makefile | 2 +- + drivers/crypto/starfive/jh7110-cryp.c | 39 ++ + drivers/crypto/starfive/jh7110-cryp.h | 70 +- + drivers/crypto/starfive/jh7110-hash.c | 892 ++++++++++++++++++++++++++ + 5 files changed, 1003 insertions(+), 4 deletions(-) + create mode 100644 drivers/crypto/starfive/jh7110-hash.c + +diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig +index 2436e93d27ef..8795b2fddb4e 100644 +--- a/drivers/crypto/starfive/Kconfig ++++ b/drivers/crypto/starfive/Kconfig +@@ -6,6 +6,10 @@ config CRYPTO_DEV_JH7110 + tristate "StarFive JH7110 cryptographic engine driver" + depends on SOC_STARFIVE + select CRYPTO_ENGINE ++ select CRYPTO_HMAC ++ select CRYPTO_SHA256 ++ select CRYPTO_SHA512 ++ select CRYPTO_SM3_GENERIC + select ARM_AMBA + select DMADEVICES + select AMBA_PL08X +diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Makefile +index 41221acaee39..2af49062e36d 100644 +--- a/drivers/crypto/starfive/Makefile ++++ b/drivers/crypto/starfive/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + + obj-$(CONFIG_CRYPTO_DEV_JH7110) += jh7110-crypto.o +-jh7110-crypto-objs := jh7110-cryp.o ++jh7110-crypto-objs := jh7110-cryp.o jh7110-hash.o +diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c +index 4b2505c23168..279b19f51cb4 100644 +--- a/drivers/crypto/starfive/jh7110-cryp.c ++++ b/drivers/crypto/starfive/jh7110-cryp.c +@@ -79,10 +79,25 @@ static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) + dma_release_channel(cryp->rx); + } + ++static irqreturn_t starfive_cryp_irq(int irq, void *priv) ++{ ++ u32 status; ++ struct starfive_cryp_dev *cryp = (struct starfive_cryp_dev *)priv; ++ ++ status = readl(cryp->base + STARFIVE_IE_FLAG_OFFSET); ++ if (status & STARFIVE_IE_FLAG_HASH_DONE) { ++ writel(STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); ++ tasklet_schedule(&cryp->hash_done); ++ } ++ ++ return IRQ_HANDLED; ++} ++ + static int starfive_cryp_probe(struct platform_device *pdev) + { + struct starfive_cryp_dev *cryp; + struct resource *res; ++ int irq; + int ret; + + cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); +@@ -97,6 +112,8 @@ static int starfive_cryp_probe(struct platform_device *pdev) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), + "Error remapping memory for platform device\n"); + ++ tasklet_init(&cryp->hash_done, starfive_hash_done_task, (unsigned long)cryp); ++ + cryp->phys_base = res->start; + cryp->dma_maxburst = 32; + +@@ -115,6 +132,16 @@ static int starfive_cryp_probe(struct platform_device *pdev) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), + "Error getting hardware reset line\n"); + ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_irq(&pdev->dev, irq, starfive_cryp_irq, 0, pdev->name, ++ (void *)cryp); ++ if (ret) ++ return dev_err_probe(&pdev->dev, irq, ++ "Failed to register interrupt handler\n"); ++ + clk_prepare_enable(cryp->hclk); + clk_prepare_enable(cryp->ahb); + reset_control_deassert(cryp->rst); +@@ -142,8 +169,14 @@ static int starfive_cryp_probe(struct platform_device *pdev) + if (ret) + goto err_engine_start; + ++ ret = starfive_hash_register_algs(); ++ if (ret) ++ goto err_algs_hash; ++ + return 0; + ++err_algs_hash: ++ crypto_engine_stop(cryp->engine); + err_engine_start: + crypto_engine_exit(cryp->engine); + err_engine: +@@ -156,6 +189,8 @@ static int starfive_cryp_probe(struct platform_device *pdev) + clk_disable_unprepare(cryp->hclk); + clk_disable_unprepare(cryp->ahb); + reset_control_assert(cryp->rst); ++ ++ tasklet_kill(&cryp->hash_done); + err_probe_defer: + return ret; + } +@@ -164,6 +199,10 @@ static int starfive_cryp_remove(struct platform_device *pdev) + { + struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev); + ++ starfive_hash_unregister_algs(); ++ ++ tasklet_kill(&cryp->hash_done); ++ + crypto_engine_stop(cryp->engine); + crypto_engine_exit(cryp->engine); + +diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfive/jh7110-cryp.h +index 393efd38b098..7a589f6eca14 100644 +--- a/drivers/crypto/starfive/jh7110-cryp.h ++++ b/drivers/crypto/starfive/jh7110-cryp.h +@@ -7,6 +7,8 @@ + #include + + #include ++#include ++#include + + #define STARFIVE_ALG_CR_OFFSET 0x0 + #define STARFIVE_ALG_FIFO_OFFSET 0x4 +@@ -15,7 +17,43 @@ + #define STARFIVE_DMA_IN_LEN_OFFSET 0x10 + #define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 + ++#define STARFIVE_IE_MASK_HASH_DONE BIT(2) ++#define STARFIVE_IE_FLAG_HASH_DONE BIT(2) ++ + #define STARFIVE_MSG_BUFFER_SIZE SZ_16K ++#define MAX_KEY_SIZE SHA512_BLOCK_SIZE ++ ++union starfive_hash_csr { ++ u32 v; ++ struct { ++ u32 start :1; ++ u32 reset :1; ++ u32 ie :1; ++ u32 firstb :1; ++#define STARFIVE_HASH_SM3 0x0 ++#define STARFIVE_HASH_SHA224 0x3 ++#define STARFIVE_HASH_SHA256 0x4 ++#define STARFIVE_HASH_SHA384 0x5 ++#define STARFIVE_HASH_SHA512 0x6 ++#define STARFIVE_HASH_MODE_MASK 0x7 ++ u32 mode :3; ++ u32 rsvd_1 :1; ++ u32 final :1; ++ u32 rsvd_2 :2; ++#define STARFIVE_HASH_HMAC_FLAGS 0x800 ++ u32 hmac :1; ++ u32 rsvd_3 :1; ++#define STARFIVE_HASH_KEY_DONE BIT(13) ++ u32 key_done :1; ++ u32 key_flag :1; ++ u32 hmac_done :1; ++#define STARFIVE_HASH_BUSY BIT(16) ++ u32 busy :1; ++ u32 hashdone :1; ++ u32 rsvd_4 :14; ++ }; ++}; ++ + + union starfive_alg_cr { + u32 v; +@@ -34,12 +72,18 @@ union starfive_alg_cr { + struct starfive_cryp_ctx { + struct crypto_engine_ctx enginectx; + struct starfive_cryp_dev *cryp; ++ struct starfive_cryp_request_ctx *rctx; ++ ++ unsigned int hash_mode; ++ u8 key[MAX_KEY_SIZE]; ++ int keylen; ++ bool is_hmac; ++ struct crypto_ahash *ahash_fbk; + }; + + struct starfive_cryp_dev { + struct list_head list; + struct device *dev; +- + struct clk *hclk; + struct clk *ahb; + struct reset_control *rst; +@@ -52,12 +96,32 @@ struct starfive_cryp_dev { + struct dma_chan *rx; + struct dma_slave_config cfg_in; + struct dma_slave_config cfg_out; +- + struct crypto_engine *engine; +- ++ struct tasklet_struct hash_done; ++ int err; + union starfive_alg_cr alg_cr; ++ union { ++ struct ahash_request *hreq; ++ } req; ++}; ++ ++struct starfive_cryp_request_ctx { ++ union { ++ union starfive_hash_csr hash; ++ } csr; ++ ++ struct scatterlist *in_sg; ++ struct ahash_request ahash_fbk_req; ++ size_t total; ++ unsigned int blksize; ++ unsigned int digsize; ++ unsigned long in_sg_len; + }; + + struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx); + ++int starfive_hash_register_algs(void); ++void starfive_hash_unregister_algs(void); ++ ++void starfive_hash_done_task(unsigned long param); + #endif +diff --git a/drivers/crypto/starfive/jh7110-hash.c b/drivers/crypto/starfive/jh7110-hash.c +new file mode 100644 +index 000000000000..3801e44f2f33 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-hash.c +@@ -0,0 +1,892 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Hash function and HMAC support for StarFive driver ++ * ++ * Copyright (c) 2022 StarFive Technology ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "jh7110-cryp.h" ++ ++#define STARFIVE_HASH_REGS_OFFSET 0x300 ++#define STARFIVE_HASH_SHACSR (STARFIVE_HASH_REGS_OFFSET + 0x0) ++#define STARFIVE_HASH_SHAWDR (STARFIVE_HASH_REGS_OFFSET + 0x4) ++#define STARFIVE_HASH_SHARDR (STARFIVE_HASH_REGS_OFFSET + 0x8) ++#define STARFIVE_HASH_SHAWSR (STARFIVE_HASH_REGS_OFFSET + 0xC) ++#define STARFIVE_HASH_SHAWLEN3 (STARFIVE_HASH_REGS_OFFSET + 0x10) ++#define STARFIVE_HASH_SHAWLEN2 (STARFIVE_HASH_REGS_OFFSET + 0x14) ++#define STARFIVE_HASH_SHAWLEN1 (STARFIVE_HASH_REGS_OFFSET + 0x18) ++#define STARFIVE_HASH_SHAWLEN0 (STARFIVE_HASH_REGS_OFFSET + 0x1C) ++#define STARFIVE_HASH_SHAWKR (STARFIVE_HASH_REGS_OFFSET + 0x20) ++#define STARFIVE_HASH_SHAWKLEN (STARFIVE_HASH_REGS_OFFSET + 0x24) ++ ++#define STARFIVE_HASH_BUFLEN SHA512_BLOCK_SIZE ++ ++static inline int starfive_hash_wait_busy(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ u32 status; ++ ++ return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, ++ !(status & STARFIVE_HASH_BUSY), 10, 100000); ++} ++ ++static inline int starfive_hash_wait_key_done(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ u32 status; ++ ++ return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, ++ (status & STARFIVE_HASH_KEY_DONE), 10, 100000); ++} ++ ++static int starfive_hash_hmac_key(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ int klen = ctx->keylen, loop; ++ unsigned int *key = (unsigned int *)ctx->key; ++ unsigned char *cl; ++ ++ writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN); ++ ++ rctx->csr.hash.hmac = 1; ++ rctx->csr.hash.key_flag = 1; ++ ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ ++ for (loop = 0; loop < klen / sizeof(unsigned int); loop++, key++) ++ writel(*key, cryp->base + STARFIVE_HASH_SHAWKR); ++ ++ if (klen & 0x3) { ++ cl = (unsigned char *)key; ++ for (loop = 0; loop < (klen & 0x3); loop++, cl++) ++ writeb(*cl, cryp->base + STARFIVE_HASH_SHAWKR); ++ } ++ ++ if (starfive_hash_wait_key_done(ctx)) ++ return dev_err_probe(cryp->dev, -ETIMEDOUT, "starfive_hash_wait_key_done error\n"); ++ ++ return 0; ++} ++ ++static void starfive_hash_start(void *param) ++{ ++ struct starfive_cryp_ctx *ctx = param; ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ union starfive_alg_cr alg_cr; ++ union starfive_hash_csr csr; ++ ++ dma_unmap_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE); ++ ++ alg_cr.v = 0; ++ alg_cr.clear = 1; ++ ++ writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); ++ ++ csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR); ++ csr.firstb = 0; ++ csr.final = 1; ++ ++ writel(~STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); ++ writel(csr.v, cryp->base + STARFIVE_HASH_SHACSR); ++} ++ ++static int starfive_hash_xmit_dma(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ struct dma_async_tx_descriptor *in_desc; ++ union starfive_alg_cr alg_cr; ++ int total_len; ++ int ret; ++ ++ if (!rctx->total) { ++ starfive_hash_start(ctx); ++ return 0; ++ } ++ ++ writel(rctx->total, cryp->base + STARFIVE_DMA_IN_LEN_OFFSET); ++ ++ total_len = rctx->total; ++ total_len = (total_len & 0x3) ? (((total_len >> 2) + 1) << 2) : total_len; ++ sg_dma_len(rctx->in_sg) = total_len; ++ ++ alg_cr.v = 0; ++ alg_cr.start = 1; ++ alg_cr.hash_dma_en = 1; ++ ++ writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); ++ ++ ret = dma_map_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE); ++ if (!ret) ++ return dev_err_probe(cryp->dev, -EINVAL, "dma_map_sg() error\n"); ++ ++ cryp->cfg_in.direction = DMA_MEM_TO_DEV; ++ cryp->cfg_in.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cryp->cfg_in.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cryp->cfg_in.src_maxburst = cryp->dma_maxburst; ++ cryp->cfg_in.dst_maxburst = cryp->dma_maxburst; ++ cryp->cfg_in.dst_addr = cryp->phys_base + STARFIVE_ALG_FIFO_OFFSET; ++ ++ dmaengine_slave_config(cryp->tx, &cryp->cfg_in); ++ ++ in_desc = dmaengine_prep_slave_sg(cryp->tx, rctx->in_sg, ++ ret, DMA_MEM_TO_DEV, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ ++ if (!in_desc) ++ return -EINVAL; ++ ++ in_desc->callback = starfive_hash_start; ++ in_desc->callback_param = ctx; ++ ++ dmaengine_submit(in_desc); ++ dma_async_issue_pending(cryp->tx); ++ ++ return 0; ++} ++ ++static int starfive_hash_xmit(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ int ret = 0; ++ ++ rctx->csr.hash.v = 0; ++ rctx->csr.hash.reset = 1; ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ ++ if (starfive_hash_wait_busy(ctx)) ++ return dev_err_probe(cryp->dev, -ETIMEDOUT, "Error resetting engine.\n"); ++ ++ rctx->csr.hash.v = 0; ++ rctx->csr.hash.mode = ctx->hash_mode; ++ rctx->csr.hash.ie = 1; ++ ++ if (ctx->is_hmac) { ++ ret = starfive_hash_hmac_key(ctx); ++ if (ret) ++ return ret; ++ } else { ++ rctx->csr.hash.start = 1; ++ rctx->csr.hash.firstb = 1; ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ } ++ ++ return starfive_hash_xmit_dma(ctx); ++} ++ ++static int starfive_hash_copy_hash(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); ++ int count, *data; ++ int mlen; ++ ++ if (!req->result) ++ return 0; ++ ++ mlen = rctx->digsize / sizeof(u32); ++ data = (u32 *)req->result; ++ ++ for (count = 0; count < mlen; count++) ++ data[count] = readl(ctx->cryp->base + STARFIVE_HASH_SHARDR); ++ ++ return 0; ++} ++ ++void starfive_hash_done_task(unsigned long param) ++{ ++ struct starfive_cryp_dev *cryp = (struct starfive_cryp_dev *)param; ++ int err = cryp->err; ++ ++ if (!err) ++ err = starfive_hash_copy_hash(cryp->req.hreq); ++ ++ crypto_finalize_hash_request(cryp->engine, cryp->req.hreq, err); ++} ++ ++static int starfive_hash_check_aligned(struct scatterlist *sg, size_t total, size_t align) ++{ ++ int len = 0; ++ ++ if (!total) ++ return 0; ++ ++ if (!IS_ALIGNED(total, align)) ++ return -EINVAL; ++ ++ while (sg) { ++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) ++ return -EINVAL; ++ ++ if (!IS_ALIGNED(sg->length, align)) ++ return -EINVAL; ++ ++ len += sg->length; ++ sg = sg_next(sg); ++ } ++ ++ if (len != total) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int starfive_hash_one_request(struct crypto_engine *engine, void *areq) ++{ ++ struct ahash_request *req = container_of(areq, struct ahash_request, ++ base); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ ++ if (!cryp) ++ return -ENODEV; ++ ++ return starfive_hash_xmit(ctx); ++} ++ ++static int starfive_hash_init(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_init(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_update(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_update(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_final(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_final(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_finup(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_finup(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_digest_fb(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, req->base.flags, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_digest(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_digest(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ ++ memset(rctx, 0, sizeof(struct starfive_cryp_request_ctx)); ++ ++ cryp->req.hreq = req; ++ rctx->total = req->nbytes; ++ rctx->in_sg = req->src; ++ rctx->blksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); ++ rctx->digsize = crypto_ahash_digestsize(tfm); ++ rctx->in_sg_len = sg_nents_for_len(rctx->in_sg, rctx->total); ++ ctx->rctx = rctx; ++ ++ if (starfive_hash_check_aligned(rctx->in_sg, rctx->total, rctx->blksize)) ++ return starfive_hash_digest_fb(req); ++ ++ return crypto_transfer_hash_request_to_engine(cryp->engine, req); ++} ++ ++static int starfive_hash_export(struct ahash_request *req, void *out) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ return crypto_ahash_export(&rctx->ahash_fbk_req, out); ++} ++ ++static int starfive_hash_import(struct ahash_request *req, const void *in) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ return crypto_ahash_import(&rctx->ahash_fbk_req, in); ++} ++ ++static int starfive_hash_init_tfm(struct crypto_ahash *hash, ++ const char *alg_name, ++ unsigned int mode) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->cryp = starfive_cryp_find_dev(ctx); ++ ++ if (!ctx->cryp) ++ return -ENODEV; ++ ++ ctx->ahash_fbk = crypto_alloc_ahash(alg_name, 0, ++ CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(ctx->ahash_fbk)) ++ return dev_err_probe(ctx->cryp->dev, PTR_ERR(ctx->ahash_fbk), ++ "starfive_hash: Could not load fallback driver.\n"); ++ ++ crypto_ahash_set_statesize(hash, crypto_ahash_statesize(ctx->ahash_fbk)); ++ crypto_ahash_set_reqsize(hash, sizeof(struct starfive_cryp_request_ctx) + ++ crypto_ahash_reqsize(ctx->ahash_fbk)); ++ ++ ctx->keylen = 0; ++ ctx->hash_mode = mode; ++ ++ ctx->enginectx.op.do_one_request = starfive_hash_one_request; ++ ctx->enginectx.op.prepare_request = NULL; ++ ctx->enginectx.op.unprepare_request = NULL; ++ ++ return 0; ++} ++ ++static void starfive_hash_exit_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ crypto_free_ahash(ctx->ahash_fbk); ++ ++ ctx->ahash_fbk = NULL; ++ ctx->enginectx.op.do_one_request = NULL; ++ ctx->enginectx.op.prepare_request = NULL; ++ ctx->enginectx.op.unprepare_request = NULL; ++} ++ ++static int starfive_hash_long_setkey(struct starfive_cryp_ctx *ctx, ++ const u8 *key, unsigned int keylen, ++ const char *alg_name) ++{ ++ struct crypto_wait wait; ++ struct ahash_request *req; ++ struct scatterlist sg; ++ struct crypto_ahash *ahash_tfm; ++ u8 *buf; ++ int ret; ++ ++ ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0); ++ if (IS_ERR(ahash_tfm)) ++ return PTR_ERR(ahash_tfm); ++ ++ req = ahash_request_alloc(ahash_tfm, GFP_KERNEL); ++ if (!req) { ++ ret = -ENOMEM; ++ goto err_free_ahash; ++ } ++ ++ crypto_init_wait(&wait); ++ ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, ++ crypto_req_done, &wait); ++ crypto_ahash_clear_flags(ahash_tfm, ~0); ++ ++ buf = kzalloc(keylen + STARFIVE_HASH_BUFLEN, GFP_KERNEL); ++ if (!buf) { ++ ret = -ENOMEM; ++ goto err_free_req; ++ } ++ ++ memcpy(buf, key, keylen); ++ sg_init_one(&sg, buf, keylen); ++ ahash_request_set_crypt(req, &sg, ctx->key, keylen); ++ ++ ret = crypto_wait_req(crypto_ahash_digest(req), &wait); ++ ++ kfree(buf); ++err_free_req: ++ ahash_request_free(req); ++err_free_ahash: ++ crypto_free_ahash(ahash_tfm); ++ return ret; ++} ++ ++static int starfive_hash_setkey(struct crypto_ahash *hash, ++ const u8 *key, unsigned int keylen) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ unsigned int digestsize = crypto_ahash_digestsize(hash); ++ unsigned int blocksize = crypto_ahash_blocksize(hash); ++ const char *alg_name; ++ ++ crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); ++ ++ if (keylen <= blocksize) { ++ memcpy(ctx->key, key, keylen); ++ ctx->keylen = keylen; ++ return 0; ++ } ++ ++ ctx->keylen = digestsize; ++ ++ switch (digestsize) { ++ case SHA224_DIGEST_SIZE: ++ alg_name = "sha224-starfive"; ++ break; ++ case SHA256_DIGEST_SIZE: ++ if (ctx->hash_mode == STARFIVE_HASH_SM3) ++ alg_name = "sm3-starfive"; ++ else ++ alg_name = "sha256-starfive"; ++ break; ++ case SHA384_DIGEST_SIZE: ++ alg_name = "sha384-starfive"; ++ break; ++ case SHA512_DIGEST_SIZE: ++ alg_name = "sha512-starfive"; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return starfive_hash_long_setkey(ctx, key, keylen, alg_name); ++} ++ ++static int starfive_sha224_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha224-generic", ++ STARFIVE_HASH_SHA224); ++} ++ ++static int starfive_sha256_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha256-generic", ++ STARFIVE_HASH_SHA256); ++} ++ ++static int starfive_sha384_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha384-generic", ++ STARFIVE_HASH_SHA384); ++} ++ ++static int starfive_sha512_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha512-generic", ++ STARFIVE_HASH_SHA512); ++} ++ ++static int starfive_sm3_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sm3-generic", ++ STARFIVE_HASH_SM3); ++} ++ ++static int starfive_hmac_sha224_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha224-generic)", ++ STARFIVE_HASH_SHA224); ++} ++ ++static int starfive_hmac_sha256_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha256-generic)", ++ STARFIVE_HASH_SHA256); ++} ++ ++static int starfive_hmac_sha384_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha384-generic)", ++ STARFIVE_HASH_SHA384); ++} ++ ++static int starfive_hmac_sha512_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha512-generic)", ++ STARFIVE_HASH_SHA512); ++} ++ ++static int starfive_hmac_sm3_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sm3-generic)", ++ STARFIVE_HASH_SM3); ++} ++ ++static struct ahash_alg algs_sha2_sm3[] = { ++{ ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha224_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA224_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha224", ++ .cra_driver_name = "sha224-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA224_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha224_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA224_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "hmac(sha224)", ++ .cra_driver_name = "sha224-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA224_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha256_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "sha256-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha256_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "hmac(sha256)", ++ .cra_driver_name = "sha256-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha384_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha384", ++ .cra_driver_name = "sha384-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha384_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "hmac(sha384)", ++ .cra_driver_name = "sha384-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha512_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha512", ++ .cra_driver_name = "sha512-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha512_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "hmac(sha512)", ++ .cra_driver_name = "sha512-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sm3_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "sm3", ++ .cra_driver_name = "sm3-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sm3_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "hmac(sm3)", ++ .cra_driver_name = "sm3-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, ++}; ++ ++int starfive_hash_register_algs(void) ++{ ++ return crypto_register_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); ++} ++ ++void starfive_hash_unregister_algs(void) ++{ ++ crypto_unregister_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); ++} +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0050-dt-bindings-PWM-Add-StarFive-PWM-module.patch b/srcpkgs/linux6.3/patches/0050-dt-bindings-PWM-Add-StarFive-PWM-module.patch new file mode 100644 index 0000000000000..f0fe0d63473ad --- /dev/null +++ b/srcpkgs/linux6.3/patches/0050-dt-bindings-PWM-Add-StarFive-PWM-module.patch @@ -0,0 +1,77 @@ +From d72e439eb2dc1ca0ea72a6d91992df135573dfec Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Tue, 21 Mar 2023 13:52:27 +0800 +Subject: [PATCH 50/84] dt-bindings: PWM: Add StarFive PWM module + +Add documentation to describe StarFive Pulse Width Modulation +controller driver. + +Signed-off-by: William Qiu +Reviewed-by: Krzysztof Kozlowski +--- + .../bindings/pwm/starfive,jh7110-pwm.yaml | 53 +++++++++++++++++++ + 1 file changed, 53 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml + +diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml +new file mode 100644 +index 000000000000..082b3779fa61 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml +@@ -0,0 +1,53 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pwm/starfive,jh7110-pwm.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive PWM controller ++ ++maintainers: ++ - William Qiu ++ ++description: ++ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates ++ binary signal with user-programmable low and high periods. Clock source for the ++ PWM can be either system clockor external clock. Each PWM timer block provides 8 ++ PWM channels. ++ ++allOf: ++ - $ref: pwm.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pwm ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++ "#pwm-cells": ++ const: 3 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - resets ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pwm@120d0000 { ++ compatible = "starfive,jh7110-pwm"; ++ reg = <0x120d0000 0x10000>; ++ clocks = <&syscrg 121>; ++ resets = <&syscrg 108>; ++ #pwm-cells = <3>; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0051-pwm-starfive-Add-PWM-driver-support.patch b/srcpkgs/linux6.3/patches/0051-pwm-starfive-Add-PWM-driver-support.patch new file mode 100644 index 0000000000000..eb9cfce957f15 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0051-pwm-starfive-Add-PWM-driver-support.patch @@ -0,0 +1,304 @@ +From 1dbcfc420c3251b22150271b0b3aeb24e29b513b Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Tue, 21 Mar 2023 13:52:28 +0800 +Subject: [PATCH 51/84] pwm: starfive: Add PWM driver support + +Add Pulse Width Modulation driver support for StarFive +JH7110 soc. + +Signed-off-by: Hal Feng +Signed-off-by: William Qiu +--- + drivers/pwm/Kconfig | 10 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-starfive-ptc.c | 245 +++++++++++++++++++++++++++++++++ + 3 files changed, 256 insertions(+) + create mode 100644 drivers/pwm/pwm-starfive-ptc.c + +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index dae023d783a2..2307a0099994 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -536,6 +536,16 @@ config PWM_SPRD + To compile this driver as a module, choose M here: the module + will be called pwm-sprd. + ++config PWM_STARFIVE_PTC ++ tristate "StarFive PWM PTC support" ++ depends on OF ++ depends on COMMON_CLK ++ help ++ Generic PWM framework driver for StarFive SoCs. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-starfive-ptc. ++ + config PWM_STI + tristate "STiH4xx PWM support" + depends on ARCH_STI || COMPILE_TEST +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 7bf1a29f02b8..577f69904baa 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -49,6 +49,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o + obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o + obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o + obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o ++obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o + obj-$(CONFIG_PWM_STI) += pwm-sti.o + obj-$(CONFIG_PWM_STM32) += pwm-stm32.o + obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o +diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c +new file mode 100644 +index 000000000000..239df796d240 +--- /dev/null ++++ b/drivers/pwm/pwm-starfive-ptc.c +@@ -0,0 +1,245 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * PWM driver for the StarFive JH7110 SoC ++ * ++ * Copyright (C) 2018 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* how many parameters can be transferred to ptc */ ++#define OF_PWM_N_CELLS 3 ++ ++/* PTC Register offsets */ ++#define REG_RPTC_CNTR 0x0 ++#define REG_RPTC_HRC 0x4 ++#define REG_RPTC_LRC 0x8 ++#define REG_RPTC_CTRL 0xC ++ ++/* Bit for PWM clock */ ++#define BIT_PWM_CLOCK_EN 31 ++ ++/* Bit for clock gen soft reset */ ++#define BIT_CLK_GEN_SOFT_RESET 13 ++ ++#define NS_PER_SECOND 1000000000 ++ ++/* ++ * Access PTC register (cntr hrc lrc and ctrl), ++ * need to replace PWM_BASE_ADDR ++ */ ++#define REG_PTC_BASE_ADDR_SUB(base, N) \ ++((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10))) ++#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N)) ++#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4) ++#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8) ++#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC) ++ ++/* PTC_RPTC_CTRL */ ++#define PTC_EN BIT(0) ++#define PTC_ECLK BIT(1) ++#define PTC_NEC BIT(2) ++#define PTC_OE BIT(3) ++#define PTC_SIGNLE BIT(4) ++#define PTC_INTE BIT(5) ++#define PTC_INT BIT(6) ++#define PTC_CNTRRST BIT(7) ++#define PTC_CAPTE BIT(8) ++ ++struct starfive_pwm_ptc_device { ++ struct pwm_chip chip; ++ struct clk *clk; ++ struct reset_control *rst; ++ void __iomem *regs; ++ int irq; ++ unsigned int approx_freq;/*pwm apb clock frequency*/ ++}; ++ ++static inline ++struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c) ++{ ++ return container_of(c, struct starfive_pwm_ptc_device, chip); ++} ++ ++static int starfive_pwm_ptc_get_state(struct pwm_chip *chip, ++ struct pwm_device *dev, ++ struct pwm_state *state) ++{ ++ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); ++ u32 data_lrc, data_hrc; ++ u32 pwm_clk_ns = 0; ++ ++ data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); ++ data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); ++ ++ pwm_clk_ns = NS_PER_SECOND / pwm->approx_freq; ++ ++ state->period = data_lrc * pwm_clk_ns; ++ state->duty_cycle = data_hrc * pwm_clk_ns; ++ state->polarity = PWM_POLARITY_NORMAL; ++ state->enabled = 1; ++ ++ return 0; ++} ++ ++static int starfive_pwm_ptc_apply(struct pwm_chip *chip, ++ struct pwm_device *dev, ++ struct pwm_state *state) ++{ ++ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); ++ u32 data_hrc = 0; ++ u32 data_lrc = 0; ++ u32 period_data = 0; ++ u32 duty_data = 0; ++ s64 multi = pwm->approx_freq; ++ s64 div = NS_PER_SECOND; ++ void __iomem *reg_addr; ++ ++ if (state->duty_cycle > state->period) ++ state->duty_cycle = state->period; ++ ++ while (multi % 10 == 0 && div % 10 == 0 && multi > 0 && div > 0) { ++ multi /= 10; ++ div /= 10; ++ } ++ ++ period_data = (u32)(state->period * multi / div); ++ if (abs(period_data * div / multi - state->period) ++ > abs((period_data + 1) * div / multi - state->period) || ++ (state->period > 0 && period_data == 0)) ++ period_data += 1; ++ ++ if (state->enabled) { ++ duty_data = (u32)(state->duty_cycle * multi / div); ++ if (abs(duty_data * div / multi - state->duty_cycle) ++ > abs((duty_data + 1) * div / multi - state->duty_cycle) || ++ (state->duty_cycle > 0 && duty_data == 0)) ++ duty_data += 1; ++ } else { ++ duty_data = 0; ++ } ++ ++ if (state->polarity == PWM_POLARITY_NORMAL) ++ data_hrc = period_data - duty_data; ++ else ++ data_hrc = duty_data; ++ ++ data_lrc = period_data; ++ ++ reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm); ++ iowrite32(data_hrc, reg_addr); ++ ++ reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm); ++ iowrite32(data_lrc, reg_addr); ++ ++ reg_addr = REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm); ++ iowrite32(0, reg_addr); ++ ++ reg_addr = REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm); ++ iowrite32(PTC_EN | PTC_OE, reg_addr); ++ ++ return 0; ++} ++ ++static const struct pwm_ops starfive_pwm_ptc_ops = { ++ .get_state = starfive_pwm_ptc_get_state, ++ .apply = (void *)starfive_pwm_ptc_apply, ++ .owner = THIS_MODULE, ++}; ++ ++static int starfive_pwm_ptc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct starfive_pwm_ptc_device *pwm; ++ struct pwm_chip *chip; ++ int ret; ++ ++ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); ++ if (!pwm) ++ return -ENOMEM; ++ ++ chip = &pwm->chip; ++ chip->dev = dev; ++ chip->ops = &starfive_pwm_ptc_ops; ++ chip->npwm = 8; ++ ++ chip->of_pwm_n_cells = OF_PWM_N_CELLS; ++ chip->base = -1; ++ ++ pwm->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pwm->regs)) ++ return dev_err_probe(dev, PTR_ERR(pwm->regs), ++ "Unable to map IO resources\n"); ++ ++ pwm->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(pwm->clk)) ++ return dev_err_probe(dev, PTR_ERR(pwm->clk), ++ "Unable to get pwm clock\n"); ++ ++ pwm->rst = devm_reset_control_get_exclusive(dev, NULL); ++ if (IS_ERR(pwm->rst)) ++ return dev_err_probe(dev, PTR_ERR(pwm->rst), ++ "Unable to get pwm reset\n"); ++ ++ ret = clk_prepare_enable(pwm->clk); ++ if (ret) { ++ dev_err(dev, ++ "Failed to enable pwm clock, %d\n", ret); ++ return ret; ++ } ++ ++ reset_control_deassert(pwm->rst); ++ ++ pwm->approx_freq = (unsigned int)clk_get_rate(pwm->clk); ++ if (!pwm->approx_freq) ++ dev_err(dev, "get pwm apb clock rate failed.\n"); ++ ++ ret = devm_pwmchip_add(dev, chip); ++ if (ret < 0) { ++ dev_err(dev, "cannot register PTC: %d\n", ret); ++ clk_disable_unprepare(pwm->clk); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, pwm); ++ ++ return 0; ++} ++ ++static int starfive_pwm_ptc_remove(struct platform_device *dev) ++{ ++ struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev); ++ struct pwm_chip *chip = &pwm->chip; ++ ++ pwmchip_remove(chip); ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_pwm_ptc_of_match[] = { ++ { .compatible = "starfive,jh7110-pwm" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match); ++ ++static struct platform_driver starfive_pwm_ptc_driver = { ++ .probe = starfive_pwm_ptc_probe, ++ .remove = starfive_pwm_ptc_remove, ++ .driver = { ++ .name = "pwm-starfive-ptc", ++ .of_match_table = starfive_pwm_ptc_of_match, ++ }, ++}; ++module_platform_driver(starfive_pwm_ptc_driver); ++ ++MODULE_AUTHOR("Jenny Zhang "); ++MODULE_AUTHOR("Hal Feng "); ++MODULE_DESCRIPTION("StarFive PWM PTC driver"); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0052-dt-bindings-net-snps-dwmac-Add-dwmac-5.20-version.patch b/srcpkgs/linux6.3/patches/0052-dt-bindings-net-snps-dwmac-Add-dwmac-5.20-version.patch new file mode 100644 index 0000000000000..fe7dad59fd54d --- /dev/null +++ b/srcpkgs/linux6.3/patches/0052-dt-bindings-net-snps-dwmac-Add-dwmac-5.20-version.patch @@ -0,0 +1,53 @@ +From 41dbca9b4f2ee67d57526aa58f79de88f73d6e98 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 17 Apr 2023 18:02:46 +0800 +Subject: [PATCH 52/84] dt-bindings: net: snps,dwmac: Add dwmac-5.20 version + +Add dwmac-5.20 IP version to snps.dwmac.yaml + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Emil Renner Berthing +Signed-off-by: Samin Guo +--- + Documentation/devicetree/bindings/net/snps,dwmac.yaml | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index 16b7d2904696..01b056ab71f7 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -30,6 +30,7 @@ select: + - snps,dwmac-4.10a + - snps,dwmac-4.20a + - snps,dwmac-5.10a ++ - snps,dwmac-5.20 + - snps,dwxgmac + - snps,dwxgmac-2.10 + +@@ -87,6 +88,7 @@ properties: + - snps,dwmac-4.10a + - snps,dwmac-4.20a + - snps,dwmac-5.10a ++ - snps,dwmac-5.20 + - snps,dwxgmac + - snps,dwxgmac-2.10 + +@@ -575,6 +577,7 @@ allOf: + - snps,dwmac-3.50a + - snps,dwmac-4.10a + - snps,dwmac-4.20a ++ - snps,dwmac-5.20 + - snps,dwxgmac + - snps,dwxgmac-2.10 + - st,spear600-gmac +@@ -629,6 +632,7 @@ allOf: + - snps,dwmac-4.10a + - snps,dwmac-4.20a + - snps,dwmac-5.10a ++ - snps,dwmac-5.20 + - snps,dwxgmac + - snps,dwxgmac-2.10 + - st,spear600-gmac +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0053-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch b/srcpkgs/linux6.3/patches/0053-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch new file mode 100644 index 0000000000000..71f308581ba59 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0053-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch @@ -0,0 +1,33 @@ +From 2bda2d83f33c5f8921c12d1a265dd62014172067 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Mon, 17 Apr 2023 18:02:47 +0800 +Subject: [PATCH 53/84] net: stmmac: platform: Add snps,dwmac-5.20 IP + compatible string + +Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid +to define some platform data in the glue layer. + +Tested-by: Tommaso Merciai +Signed-off-by: Emil Renner Berthing +Signed-off-by: Samin Guo +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +index 067a40fe0a23..eb0b2898daa3 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -519,7 +519,8 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) + if (of_device_is_compatible(np, "snps,dwmac-4.00") || + of_device_is_compatible(np, "snps,dwmac-4.10a") || + of_device_is_compatible(np, "snps,dwmac-4.20a") || +- of_device_is_compatible(np, "snps,dwmac-5.10a")) { ++ of_device_is_compatible(np, "snps,dwmac-5.10a") || ++ of_device_is_compatible(np, "snps,dwmac-5.20")) { + plat->has_gmac4 = 1; + plat->has_gmac = 0; + plat->pmt = 1; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0054-dt-bindings-net-snps-dwmac-Add-ahb-reset-reset-name.patch b/srcpkgs/linux6.3/patches/0054-dt-bindings-net-snps-dwmac-Add-ahb-reset-reset-name.patch new file mode 100644 index 0000000000000..96ea55c34845f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0054-dt-bindings-net-snps-dwmac-Add-ahb-reset-reset-name.patch @@ -0,0 +1,50 @@ +From a489177293a294ae7b20400933d3bd3c0628fdf7 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Mon, 17 Apr 2023 18:02:48 +0800 +Subject: [PATCH 54/84] dt-bindings: net: snps,dwmac: Add 'ahb' + reset/reset-name + +According to: +stmmac_platform.c: stmmac_probe_config_dt +stmmac_main.c: stmmac_dvr_probe + +dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb) +reset signals, and the maxItems of resets/reset-names is going to be 2. + +The gmac of Starfive Jh7110 SOC must have two resets. +it uses snps,dwmac-5.20 IP. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Samin Guo +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index 01b056ab71f7..e4519cf722ab 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -133,12 +133,16 @@ properties: + - ptp_ref + + resets: +- maxItems: 1 +- description: +- MAC Reset signal. ++ minItems: 1 ++ items: ++ - description: GMAC stmmaceth reset ++ - description: AHB reset + + reset-names: +- const: stmmaceth ++ minItems: 1 ++ items: ++ - const: stmmaceth ++ - const: ahb + + power-domains: + maxItems: 1 +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0055-dt-bindings-net-Add-support-StarFive-dwmac.patch b/srcpkgs/linux6.3/patches/0055-dt-bindings-net-Add-support-StarFive-dwmac.patch new file mode 100644 index 0000000000000..c48960490a45f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0055-dt-bindings-net-Add-support-StarFive-dwmac.patch @@ -0,0 +1,181 @@ +From 60019b9d1e5b9626ea4f5fdd18c1e31b4c59aec9 Mon Sep 17 00:00:00 2001 +From: Yanhong Wang +Date: Mon, 17 Apr 2023 18:02:49 +0800 +Subject: [PATCH 55/84] dt-bindings: net: Add support StarFive dwmac + +Add documentation to describe StarFive dwmac driver(GMAC). + +Signed-off-by: Yanhong Wang +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Samin Guo +--- + .../devicetree/bindings/net/snps,dwmac.yaml | 1 + + .../bindings/net/starfive,jh7110-dwmac.yaml | 144 ++++++++++++++++++ + 2 files changed, 145 insertions(+) + create mode 100644 Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml + +diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +index e4519cf722ab..245f7d713261 100644 +--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml +@@ -91,6 +91,7 @@ properties: + - snps,dwmac-5.20 + - snps,dwxgmac + - snps,dwxgmac-2.10 ++ - starfive,jh7110-dwmac + + reg: + minItems: 1 +diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +new file mode 100644 +index 000000000000..5e7cfbbebce6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +@@ -0,0 +1,144 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++# Copyright (C) 2022 StarFive Technology Co., Ltd. ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 DWMAC glue layer ++ ++maintainers: ++ - Emil Renner Berthing ++ - Samin Guo ++ ++select: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - starfive,jh7110-dwmac ++ required: ++ - compatible ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - starfive,jh7110-dwmac ++ - const: snps,dwmac-5.20 ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: GMAC main clock ++ - description: GMAC AHB clock ++ - description: PTP clock ++ - description: TX clock ++ - description: GTX clock ++ ++ clock-names: ++ items: ++ - const: stmmaceth ++ - const: pclk ++ - const: ptp_ref ++ - const: tx ++ - const: gtx ++ ++ interrupts: ++ minItems: 3 ++ maxItems: 3 ++ ++ interrupt-names: ++ minItems: 3 ++ maxItems: 3 ++ ++ resets: ++ items: ++ - description: MAC Reset signal. ++ - description: AHB Reset signal. ++ ++ reset-names: ++ items: ++ - const: stmmaceth ++ - const: ahb ++ ++ starfive,tx-use-rgmii-clk: ++ description: ++ Tx clock is provided by external rgmii clock. ++ type: boolean ++ ++ starfive,syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to syscon that configures phy mode ++ - description: Offset of phy mode selection ++ - description: Shift of phy mode selection ++ description: ++ A phandle to syscon with two arguments that configure phy mode. ++ The argument one is the offset of phy mode selection, the ++ argument two is the shift of phy mode selection. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - interrupts ++ - interrupt-names ++ - resets ++ - reset-names ++ ++allOf: ++ - $ref: snps,dwmac.yaml# ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ ethernet@16030000 { ++ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; ++ reg = <0x16030000 0x10000>; ++ clocks = <&clk 3>, <&clk 2>, <&clk 109>, ++ <&clk 6>, <&clk 111>; ++ clock-names = "stmmaceth", "pclk", "ptp_ref", ++ "tx", "gtx"; ++ resets = <&rst 1>, <&rst 2>; ++ reset-names = "stmmaceth", "ahb"; ++ interrupts = <7>, <6>, <5>; ++ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; ++ phy-mode = "rgmii-id"; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <8>; ++ rx-fifo-depth = <2048>; ++ tx-fifo-depth = <2048>; ++ snps,fixed-burst; ++ snps,no-pbl-x8; ++ snps,tso; ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,en-tx-lpi-clockgating; ++ snps,txpbl = <16>; ++ snps,rxpbl = <16>; ++ starfive,syscon = <&aon_syscon 0xc 0x12>; ++ phy-handle = <&phy0>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++ ++ stmmac_axi_setup: stmmac-axi-config { ++ snps,lpi_en; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <4>; ++ snps,blen = <256 128 64 32 0 0 0>; ++ }; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0056-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch b/srcpkgs/linux6.3/patches/0056-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch new file mode 100644 index 0000000000000..ebc956113cd9f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0056-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch @@ -0,0 +1,185 @@ +From 8ffb3f336d56fe37bc9d71f3ff4e371f033019e7 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Mon, 17 Apr 2023 18:02:50 +0800 +Subject: [PATCH 56/84] net: stmmac: Add glue layer for StarFive JH7110 SoC + +This adds StarFive dwmac driver support on the StarFive JH7110 SoC. + +Tested-by: Tommaso Merciai +Co-developed-by: Emil Renner Berthing +Signed-off-by: Emil Renner Berthing +Signed-off-by: Samin Guo +--- + drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 123 ++++++++++++++++++ + 3 files changed, 136 insertions(+) + create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c + +diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig +index f77511fe4e87..5f5a997f21f3 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig ++++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig +@@ -165,6 +165,18 @@ config DWMAC_SOCFPGA + for the stmmac device driver. This driver is used for + arria5 and cyclone5 FPGA SoCs. + ++config DWMAC_STARFIVE ++ tristate "StarFive dwmac support" ++ depends on OF && (ARCH_STARFIVE || COMPILE_TEST) ++ select MFD_SYSCON ++ default m if ARCH_STARFIVE ++ help ++ Support for ethernet controllers on StarFive RISC-V SoCs ++ ++ This selects the StarFive platform specific glue layer support for ++ the stmmac device driver. This driver is used for StarFive JH7110 ++ ethernet controller. ++ + config DWMAC_STI + tristate "STi GMAC support" + default ARCH_STI +diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile +index 057e4bab5c08..8738fdbb4b2d 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/Makefile ++++ b/drivers/net/ethernet/stmicro/stmmac/Makefile +@@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o + obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o + obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o ++obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o + obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o + obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +new file mode 100644 +index 000000000000..4963d4008485 +--- /dev/null ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +@@ -0,0 +1,123 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive DWMAC platform driver ++ * ++ * Copyright (C) 2021 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include "stmmac_platform.h" ++ ++struct starfive_dwmac { ++ struct device *dev; ++ struct clk *clk_tx; ++}; ++ ++static void starfive_dwmac_fix_mac_speed(void *priv, unsigned int speed) ++{ ++ struct starfive_dwmac *dwmac = priv; ++ unsigned long rate; ++ int err; ++ ++ rate = clk_get_rate(dwmac->clk_tx); ++ ++ switch (speed) { ++ case SPEED_1000: ++ rate = 125000000; ++ break; ++ case SPEED_100: ++ rate = 25000000; ++ break; ++ case SPEED_10: ++ rate = 2500000; ++ break; ++ default: ++ dev_err(dwmac->dev, "invalid speed %u\n", speed); ++ break; ++ } ++ ++ err = clk_set_rate(dwmac->clk_tx, rate); ++ if (err) ++ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); ++} ++ ++static int starfive_dwmac_probe(struct platform_device *pdev) ++{ ++ struct plat_stmmacenet_data *plat_dat; ++ struct stmmac_resources stmmac_res; ++ struct starfive_dwmac *dwmac; ++ struct clk *clk_gtx; ++ int err; ++ ++ err = stmmac_get_platform_resources(pdev, &stmmac_res); ++ if (err) ++ return dev_err_probe(&pdev->dev, err, ++ "failed to get resources\n"); ++ ++ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ if (IS_ERR(plat_dat)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat), ++ "dt configuration failed\n"); ++ ++ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); ++ if (!dwmac) ++ return -ENOMEM; ++ ++ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); ++ if (IS_ERR(dwmac->clk_tx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx), ++ "error getting tx clock\n"); ++ ++ clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx"); ++ if (IS_ERR(clk_gtx)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(clk_gtx), ++ "error getting gtx clock\n"); ++ ++ /* Generally, the rgmii_tx clock is provided by the internal clock, ++ * which needs to match the corresponding clock frequency according ++ * to different speeds. If the rgmii_tx clock is provided by the ++ * external rgmii_rxin, there is no need to configure the clock ++ * internally, because rgmii_rxin will be adaptively adjusted. ++ */ ++ if (!device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk")) ++ plat_dat->fix_mac_speed = starfive_dwmac_fix_mac_speed; ++ ++ dwmac->dev = &pdev->dev; ++ plat_dat->bsp_priv = dwmac; ++ plat_dat->dma_cfg->dche = true; ++ ++ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (err) { ++ stmmac_remove_config_dt(pdev, plat_dat); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_dwmac_match[] = { ++ { .compatible = "starfive,jh7110-dwmac" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_dwmac_match); ++ ++static struct platform_driver starfive_dwmac_driver = { ++ .probe = starfive_dwmac_probe, ++ .remove = stmmac_pltfr_remove, ++ .driver = { ++ .name = "starfive-dwmac", ++ .pm = &stmmac_pltfr_pm_ops, ++ .of_match_table = starfive_dwmac_match, ++ }, ++}; ++module_platform_driver(starfive_dwmac_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("StarFive DWMAC platform driver"); ++MODULE_AUTHOR("Emil Renner Berthing "); ++MODULE_AUTHOR("Samin Guo "); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0057-net-stmmac-dwmac-starfive-Add-phy-interface-settings.patch b/srcpkgs/linux6.3/patches/0057-net-stmmac-dwmac-starfive-Add-phy-interface-settings.patch new file mode 100644 index 0000000000000..c06b81bcc1e46 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0057-net-stmmac-dwmac-starfive-Add-phy-interface-settings.patch @@ -0,0 +1,96 @@ +From 01e8db4f0d4bb29a4e86fcc686d79e6f2bae75ea Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Mon, 17 Apr 2023 18:02:51 +0800 +Subject: [PATCH 57/84] net: stmmac: dwmac-starfive: Add phy interface settings + +dwmac supports multiple modess. When working under rmii and rgmii, +you need to set different phy interfaces. + +According to the dwmac document, when working in rmii, it needs to be +set to 0x4, and rgmii needs to be set to 0x1. + +The phy interface needs to be set in syscon, the format is as follows: +starfive,syscon: <&syscon, offset, shift> + +Tested-by: Tommaso Merciai +Signed-off-by: Samin Guo +--- + .../ethernet/stmicro/stmmac/dwmac-starfive.c | 48 +++++++++++++++++++ + 1 file changed, 48 insertions(+) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +index 4963d4008485..4f51a7889642 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c +@@ -13,6 +13,10 @@ + + #include "stmmac_platform.h" + ++#define STARFIVE_DWMAC_PHY_INFT_RGMII 0x1 ++#define STARFIVE_DWMAC_PHY_INFT_RMII 0x4 ++#define STARFIVE_DWMAC_PHY_INFT_FIELD 0x7U ++ + struct starfive_dwmac { + struct device *dev; + struct clk *clk_tx; +@@ -46,6 +50,46 @@ static void starfive_dwmac_fix_mac_speed(void *priv, unsigned int speed) + dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); + } + ++static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat) ++{ ++ struct starfive_dwmac *dwmac = plat_dat->bsp_priv; ++ struct regmap *regmap; ++ unsigned int args[2]; ++ unsigned int mode; ++ int err; ++ ++ switch (plat_dat->interface) { ++ case PHY_INTERFACE_MODE_RMII: ++ mode = STARFIVE_DWMAC_PHY_INFT_RMII; ++ break; ++ ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ mode = STARFIVE_DWMAC_PHY_INFT_RGMII; ++ break; ++ ++ default: ++ dev_err(dwmac->dev, "unsupported interface %d\n", ++ plat_dat->interface); ++ return -EINVAL; ++ } ++ ++ regmap = syscon_regmap_lookup_by_phandle_args(dwmac->dev->of_node, ++ "starfive,syscon", ++ 2, args); ++ if (IS_ERR(regmap)) ++ return dev_err_probe(dwmac->dev, PTR_ERR(regmap), "getting the regmap failed\n"); ++ ++ /* args[0]:offset args[1]: shift */ ++ err = regmap_update_bits(regmap, args[0], ++ STARFIVE_DWMAC_PHY_INFT_FIELD << args[1], ++ mode << args[1]); ++ if (err) ++ return dev_err_probe(dwmac->dev, err, "error setting phy mode\n"); ++ ++ return 0; ++} ++ + static int starfive_dwmac_probe(struct platform_device *pdev) + { + struct plat_stmmacenet_data *plat_dat; +@@ -91,6 +135,10 @@ static int starfive_dwmac_probe(struct platform_device *pdev) + plat_dat->bsp_priv = dwmac; + plat_dat->dma_cfg->dche = true; + ++ err = starfive_dwmac_set_mode(plat_dat); ++ if (err) ++ return err; ++ + err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (err) { + stmmac_remove_config_dt(pdev, plat_dat); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0058-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch b/srcpkgs/linux6.3/patches/0058-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch new file mode 100644 index 0000000000000..416d74473e9d8 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0058-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch @@ -0,0 +1,74 @@ +From 85f1b0fde9d570e37f9b580d9f852a3f3e9c7bbd Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:46 +0800 +Subject: [PATCH 58/84] dt-bindings: phy: Add StarFive JH7110 USB PHY + +Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Rob Herring +--- + .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +new file mode 100644 +index 000000000000..269e9f9f12b6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +@@ -0,0 +1,50 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 USB 2.0 PHY ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-usb-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: PHY 125m ++ - description: app 125m ++ ++ clock-names: ++ items: ++ - const: 125m ++ - const: app_125m ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@10200000 { ++ compatible = "starfive,jh7110-usb-phy"; ++ reg = <0x10200000 0x10000>; ++ clocks = <&syscrg 95>, ++ <&stgcrg 6>; ++ clock-names = "125m", "app_125m"; ++ #phy-cells = <0>; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0059-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch b/srcpkgs/linux6.3/patches/0059-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch new file mode 100644 index 0000000000000..47fa2205ef07d --- /dev/null +++ b/srcpkgs/linux6.3/patches/0059-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch @@ -0,0 +1,83 @@ +From 8bd86dd67db35c4ba55d3bf8edf276901e55d0df Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:47 +0800 +Subject: [PATCH 59/84] dt-bindings: phy: Add StarFive JH7110 PCIe PHY + +Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. +PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Rob Herring +--- + .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ + 1 file changed, 58 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml +new file mode 100644 +index 000000000000..2e83a6164cd1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml +@@ -0,0 +1,58 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe 2.0 PHY ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ starfive,sys-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller sys_syscon node. ++ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. ++ description: ++ The phandle to System Register Controller syscon node and the PHY connect offset ++ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. ++ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@10210000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x10210000 0x10000>; ++ #phy-cells = <0>; ++ starfive,sys-syscon = <&sys_syscon 0x18>; ++ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0060-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch b/srcpkgs/linux6.3/patches/0060-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch new file mode 100644 index 0000000000000..8dcf2b820e3e8 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0060-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch @@ -0,0 +1,185 @@ +From 1df4cb692f3b72df1b16cd0bfdf33f2c3e11cf2b Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:48 +0800 +Subject: [PATCH 60/84] phy: starfive: Add JH7110 USB 2.0 PHY driver + +Add Starfive JH7110 SoC USB 2.0 PHY driver support. +USB 2.0 PHY default connect to Cadence USB controller. + +Signed-off-by: Minda Chen +--- + drivers/phy/starfive/phy-jh7110-usb.c | 162 ++++++++++++++++++++++++++ + 1 file changed, 162 insertions(+) + create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c + +diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c +new file mode 100644 +index 000000000000..4a12df0692cd +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-usb.c +@@ -0,0 +1,162 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 USB 2.0 PHY driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_125M_CLK_RATE 125000000 ++#define USB_LS_KEEPALIVE_OFF 0x4 ++#define USB_LS_KEEPALIVE_ENABLE BIT(4) ++ ++struct jh7110_usb2_phy { ++ struct phy *phy; ++ void __iomem *regs; ++ struct clk *usb_125m_clk; ++ struct clk *app_125m; ++ enum phy_mode mode; ++}; ++ ++static void jh7110_usb2_mode_set(struct jh7110_usb2_phy *phy) ++{ ++ unsigned int val; ++ ++ if (phy->mode != PHY_MODE_USB_HOST) { ++ /* Enable the LS speed keep-alive signal */ ++ val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); ++ val |= USB_LS_KEEPALIVE_ENABLE; ++ writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); ++ } ++} ++ ++static int jh7110_usb2_phy_set_mode(struct phy *_phy, ++ enum phy_mode mode, int submode) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (mode != phy->mode) { ++ dev_info(&_phy->dev, "Changing phy to %d\n", mode); ++ phy->mode = mode; ++ jh7110_usb2_mode_set(phy); ++ } ++ ++ return 0; ++} ++ ++static int jh7110_usb2_phy_init(struct phy *_phy) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ int ret; ++ ++ ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(phy->app_125m); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int jh7110_usb2_phy_exit(struct phy *_phy) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ ++ clk_disable_unprepare(phy->app_125m); ++ ++ return 0; ++} ++ ++static const struct phy_ops jh7110_usb2_phy_ops = { ++ .init = jh7110_usb2_phy_init, ++ .exit = jh7110_usb2_phy_exit, ++ .set_mode = jh7110_usb2_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static int jh7110_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct jh7110_usb2_phy *phy; ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->usb_125m_clk = devm_clk_get(dev, "125m"); ++ if (IS_ERR(phy->usb_125m_clk)) ++ return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk), ++ "Failed to get 125m clock\n"); ++ ++ phy->app_125m = devm_clk_get(dev, "app_125m"); ++ if (IS_ERR(phy->app_125m)) ++ return dev_err_probe(dev, PTR_ERR(phy->app_125m), ++ "Failed to get app 125m clock\n"); ++ ++ phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->regs)) ++ return dev_err_probe(dev, PTR_ERR(phy->regs), ++ "Failed to map phy base\n"); ++ ++ phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops); ++ if (IS_ERR(phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(phy->phy), ++ "Failed to create phy\n"); ++ ++ platform_set_drvdata(pdev, phy); ++ phy_set_drvdata(phy->phy, phy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static int jh7110_usb_phy_remove(struct platform_device *pdev) ++{ ++ struct jh7110_usb2_phy *phy = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(phy->app_125m); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_usb_phy_of_match[] = { ++ { .compatible = "starfive,jh7110-usb-phy" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match); ++ ++static struct platform_driver jh7110_usb_phy_driver = { ++ .probe = jh7110_usb_phy_probe, ++ .remove = jh7110_usb_phy_remove, ++ .driver = { ++ .of_match_table = jh7110_usb_phy_of_match, ++ .name = "jh7110-usb-phy", ++ } ++}; ++module_platform_driver(jh7110_usb_phy_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver"); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0061-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch b/srcpkgs/linux6.3/patches/0061-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch new file mode 100644 index 0000000000000..d251e706e928e --- /dev/null +++ b/srcpkgs/linux6.3/patches/0061-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch @@ -0,0 +1,226 @@ +From fcdc8caafcfbac3678a3b8aee1b241f4d5d37a09 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:49 +0800 +Subject: [PATCH 61/84] phy: starfive: Add JH7110 PCIE 2.0 PHY driver + +Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. +PCIe 2.0 PHY default connect to PCIe controller. +But pcie0 PHY can connect to USB 3.0 controlller. + +Signed-off-by: Minda Chen +--- + drivers/phy/starfive/phy-jh7110-pcie.c | 202 +++++++++++++++++++++++++ + 1 file changed, 202 insertions(+) + create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c + +diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c +new file mode 100644 +index 000000000000..fe029daef62e +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-pcie.c +@@ -0,0 +1,202 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 PCIe 2.0 PHY driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PCIE_KVCO_LEVEL_OFF (0x28) ++#define PCIE_USB3_PHY_PLL_CTL_OFF (0x7c) ++#define PCIE_KVCO_TUNE_SIGNAL_OFF (0x80) ++#define PCIE_USB3_PHY_ENABLE BIT(4) ++#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 ++#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc ++ ++#define USB_PDRSTN_SPLIT BIT(17) ++ ++#define PCIE_PHY_MODE BIT(20) ++#define PCIE_PHY_MODE_MASK GENMASK(21, 20) ++#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) ++#define PCIE_USB3_RATE_MASK GENMASK(6, 5) ++#define PCIE_USB3_RX_STANDBY_MASK BIT(7) ++#define PCIE_USB3_PHY_ENABLE BIT(4) ++ ++struct jh7110_pcie_phy { ++ struct phy *phy; ++ struct regmap *stg_syscon; ++ struct regmap *sys_syscon; ++ void __iomem *regs; ++ u32 sys_phy_connect; ++ u32 stg_pcie_mode; ++ u32 stg_pcie_usb; ++ enum phy_mode mode; ++}; ++ ++static int jh7110_usb3_mode_set(struct jh7110_pcie_phy *data) ++{ ++ if (!data->stg_syscon || !data->sys_syscon) { ++ dev_info(&data->phy->dev, "don't support usb3 mode\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, ++ PCIE_PHY_MODE_MASK, PCIE_PHY_MODE); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_BUS_WIDTH_MASK, 0); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_RATE_MASK, 0); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_RX_STANDBY_MASK, 0); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE); ++ ++ /* Connect usb 3.0 phy mode */ ++ regmap_update_bits(data->sys_syscon, data->sys_phy_connect, ++ USB_PDRSTN_SPLIT, 0); ++ ++ /* Configuare spread-spectrum mode: down-spread-spectrum */ ++ writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); ++ ++ return 0; ++} ++ ++static void jh7110_pcie_mode_set(struct jh7110_pcie_phy *phy) ++{ ++ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ ++ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); ++ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); ++} ++ ++static int jh7110_pcie_phy_set_mode(struct phy *_phy, ++ enum phy_mode mode, int submode) ++{ ++ struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy); ++ int ret; ++ ++ if (mode == phy->mode) ++ return 0; ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ ret = jh7110_usb3_mode_set(phy); ++ if (ret) ++ return ret; ++ break; ++ case PHY_MODE_PCIE: ++ jh7110_pcie_mode_set(phy); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ dev_info(&_phy->dev, "Changing phy mode to %d\n", mode); ++ phy->mode = mode; ++ ++ return 0; ++} ++ ++static int jh7110_pcie_phy_init(struct phy *_phy) ++{ ++ return 0; ++} ++ ++static int jh7110_pcie_phy_exit(struct phy *_phy) ++{ ++ return 0; ++} ++ ++static const struct phy_ops jh7110_pcie_phy_ops = { ++ .init = jh7110_pcie_phy_init, ++ .exit = jh7110_pcie_phy_exit, ++ .set_mode = jh7110_pcie_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static int jh7110_pcie_phy_probe(struct platform_device *pdev) ++{ ++ struct jh7110_pcie_phy *phy; ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ u32 args[2]; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->regs)) ++ return PTR_ERR(phy->regs); ++ ++ phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops); ++ if (IS_ERR(phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(phy->regs), ++ "Failed to map phy base\n"); ++ ++ phy->sys_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,sys-syscon", ++ 1, args); ++ ++ if (!IS_ERR_OR_NULL(phy->sys_syscon)) ++ phy->sys_phy_connect = args[0]; ++ else ++ phy->sys_syscon = NULL; ++ ++ phy->stg_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", ++ 2, args); ++ ++ if (!IS_ERR_OR_NULL(phy->stg_syscon)) { ++ phy->stg_pcie_mode = args[0]; ++ phy->stg_pcie_usb = args[1]; ++ } else { ++ phy->stg_syscon = NULL; ++ } ++ ++ platform_set_drvdata(pdev, phy); ++ phy_set_drvdata(phy->phy, phy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static int jh7110_pcie_phy_remove(struct platform_device *pdev) ++{ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_pcie_phy_of_match[] = { ++ { .compatible = "starfive,jh7110-pcie-phy" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match); ++ ++static struct platform_driver jh7110_pcie_phy_driver = { ++ .probe = jh7110_pcie_phy_probe, ++ .remove = jh7110_pcie_phy_remove, ++ .driver = { ++ .of_match_table = jh7110_pcie_phy_of_match, ++ .name = "jh7110-pcie-phy", ++ } ++}; ++module_platform_driver(jh7110_pcie_phy_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver"); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0062-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch b/srcpkgs/linux6.3/patches/0062-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch new file mode 100644 index 0000000000000..2c45b6c3d0583 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0062-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch @@ -0,0 +1,157 @@ +From a1f1e75a14e3b83ff238b7706129cb4a4d39cfa0 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:50 +0800 +Subject: [PATCH 62/84] dt-bindings: usb: Add StarFive JH7110 USB controller + +StarFive JH7110 platforms USB have a wrapper module around +the Cadence USBSS-DRD controller. Add binding information doc +for that. + +Signed-off-by: Minda Chen +Reviewed-by: Peter Chen +Reviewed-by: Hal Feng +--- + .../bindings/usb/starfive,jh7110-usb.yaml | 131 ++++++++++++++++++ + 1 file changed, 131 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml + +diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml +new file mode 100644 +index 000000000000..e6bd8a583da3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml +@@ -0,0 +1,131 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Cadence USBSS-DRD SoC controller ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-usb ++ ++ reg: ++ items: ++ - description: OTG controller registers ++ - description: XHCI Host controller registers ++ - description: DEVICE controller registers ++ ++ reg-names: ++ items: ++ - const: otg ++ - const: xhci ++ - const: dev ++ ++ interrupts: ++ items: ++ - description: XHCI host controller interrupt ++ - description: Device controller interrupt ++ - description: OTG/DRD controller interrupt ++ ++ interrupt-names: ++ items: ++ - const: host ++ - const: peripheral ++ - const: otg ++ ++ clocks: ++ items: ++ - description: low power clock ++ - description: STB clock ++ - description: APB clock ++ - description: AXI clock ++ - description: UTMI APB clock ++ ++ clock-names: ++ items: ++ - const: lpm ++ - const: stb ++ - const: apb ++ - const: axi ++ - const: utmi_apb ++ ++ resets: ++ items: ++ - description: Power up reset ++ - description: APB clock reset ++ - description: AXI clock reset ++ - description: UTMI APB clock reset ++ ++ reset-names: ++ items: ++ - const: pwrup ++ - const: apb ++ - const: axi ++ - const: utmi_apb ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for USB. ++ ++ dr_mode: ++ enum: [host, otg, peripheral] ++ ++ phys: ++ minItems: 1 ++ maxItems: 2 ++ ++ phy-names: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ anyOf: ++ - const: usb2 ++ - const: usb3 ++ ++required: ++ - compatible ++ - reg ++ - reg-names ++ - interrupts ++ - interrupt-names ++ - clocks ++ - resets ++ - starfive,stg-syscon ++ - dr_mode ++ ++additionalProperties: false ++ ++examples: ++ - | ++ usb@10100000 { ++ compatible = "starfive,jh7110-usb"; ++ reg = <0x10100000 0x10000>, ++ <0x10110000 0x10000>, ++ <0x10120000 0x10000>; ++ reg-names = "otg", "xhci", "dev"; ++ interrupts = <100>, <108>, <110>; ++ interrupt-names = "host", "peripheral", "otg"; ++ clocks = <&syscrg 4>, ++ <&stgcrg 5>, ++ <&stgcrg 1>, ++ <&stgcrg 3>, ++ <&stgcrg 2>; ++ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; ++ resets = <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 7>, ++ <&stgcrg 9>; ++ reset-names = "pwrup", "apb", "axi", "utmi_apb"; ++ starfive,stg-syscon = <&stg_syscon 0x4>; ++ dr_mode = "host"; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0063-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch b/srcpkgs/linux6.3/patches/0063-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch new file mode 100644 index 0000000000000..94a40a35714b2 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0063-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch @@ -0,0 +1,467 @@ +From 5fd1d58c4b06f5a5cccc9c471606ddf6da4adbba Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:51 +0800 +Subject: [PATCH 63/84] usb: cdns3: Add StarFive JH7110 USB driver + +Adds Specific Glue layer to support USB peripherals on +StarFive JH7110 SoC. +There is a Cadence USB3 core for JH7110 SoCs, the cdns +core is the child of this USB wrapper module device. + +Signed-off-by: Minda Chen +Acked-by: Peter Chen +--- + drivers/usb/cdns3/Kconfig | 11 + + drivers/usb/cdns3/Makefile | 1 + + drivers/usb/cdns3/cdns3-starfive.c | 390 +++++++++++++++++++++++++++++ + drivers/usb/cdns3/core.h | 3 + + 4 files changed, 405 insertions(+) + create mode 100644 drivers/usb/cdns3/cdns3-starfive.c + +diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig +index b98ca0a1352a..0a514b591527 100644 +--- a/drivers/usb/cdns3/Kconfig ++++ b/drivers/usb/cdns3/Kconfig +@@ -78,6 +78,17 @@ config USB_CDNS3_IMX + + For example, imx8qm and imx8qxp. + ++config USB_CDNS3_STARFIVE ++ tristate "Cadence USB3 support on StarFive SoC platforms" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ help ++ Say 'Y' or 'M' here if you are building for StarFive SoCs ++ platforms that contain Cadence USB3 controller core. ++ ++ e.g. JH7110. ++ ++ If you choose to build this driver as module it will ++ be dynamically linked and module will be called cdns3-starfive.ko + endif + + if USB_CDNS_SUPPORT +diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile +index 61edb2f89276..48dfae75b5aa 100644 +--- a/drivers/usb/cdns3/Makefile ++++ b/drivers/usb/cdns3/Makefile +@@ -24,6 +24,7 @@ endif + obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o + obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o + obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o ++obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o + + cdnsp-udc-pci-y := cdnsp-pci.o + +diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c +new file mode 100644 +index 000000000000..afe1c6652660 +--- /dev/null ++++ b/drivers/usb/cdns3/cdns3-starfive.c +@@ -0,0 +1,390 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/** ++ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * Author: Yanhong Wang ++ * Author: Mason Huo ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "core.h" ++ ++#define USB_STRAP_HOST BIT(17) ++#define USB_STRAP_DEVICE BIT(18) ++#define USB_STRAP_MASK GENMASK(18, 16) ++ ++#define USB_SUSPENDM_HOST BIT(19) ++#define USB_SUSPENDM_MASK BIT(19) ++#define CDNS_IRQ_WAKEUP_INDEX 3 ++ ++struct cdns_starfive { ++ struct device *dev; ++ struct phy *usb2_phy; ++ struct phy *usb3_phy; ++ struct regmap *stg_syscon; ++ struct reset_control *resets; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ enum phy_mode phy_mode; ++ u32 stg_usb_mode; ++}; ++ ++static int set_phy_power_on(struct cdns_starfive *data) ++{ ++ int ret; ++ ++ ret = phy_power_on(data->usb2_phy); ++ if (ret) ++ return ret; ++ ++ ret = phy_power_on(data->usb3_phy); ++ if (ret) ++ phy_power_off(data->usb2_phy); ++ ++ return ret; ++} ++ ++static void cdns_mode_init(struct platform_device *pdev, ++ struct cdns_starfive *data) ++{ ++ enum usb_dr_mode mode; ++ ++ mode = usb_get_dr_mode(&pdev->dev); ++ ++ switch (mode) { ++ case USB_DR_MODE_HOST: ++ regmap_update_bits(data->stg_syscon, ++ data->stg_usb_mode, ++ USB_STRAP_MASK, ++ USB_STRAP_HOST); ++ regmap_update_bits(data->stg_syscon, ++ data->stg_usb_mode, ++ USB_SUSPENDM_MASK, ++ USB_SUSPENDM_HOST); ++ data->phy_mode = PHY_MODE_USB_HOST; ++ break; ++ ++ case USB_DR_MODE_PERIPHERAL: ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_STRAP_MASK, USB_STRAP_DEVICE); ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_SUSPENDM_MASK, 0); ++ data->phy_mode = PHY_MODE_USB_DEVICE; ++ break; ++ ++ case USB_DR_MODE_OTG: ++ data->phy_mode = PHY_MODE_USB_OTG; ++ default: ++ break; ++ } ++} ++ ++static int cdns_clk_rst_init(struct cdns_starfive *data) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(data->num_clks, data->clks); ++ if (ret) ++ return dev_err_probe(data->dev, ret, ++ "failed to enable clocks\n"); ++ ++ ret = reset_control_deassert(data->resets); ++ if (ret) { ++ dev_err(data->dev, "failed to reset clocks\n"); ++ goto err_clk_init; ++ } ++ ++ return ret; ++ ++err_clk_init: ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++ return ret; ++} ++ ++static void cdns_clk_rst_deinit(struct cdns_starfive *data) ++{ ++ reset_control_assert(data->resets); ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++} ++ ++static int cdns_starfive_phy_init(struct cdns_starfive *data) ++{ ++ int ret; ++ ++ ret = phy_init(data->usb2_phy); ++ if (ret) ++ return ret; ++ ++ ret = phy_init(data->usb3_phy); ++ if (ret) ++ goto err_phy3_init; ++ ++ phy_set_mode(data->usb2_phy, data->phy_mode); ++ phy_set_mode(data->usb3_phy, data->phy_mode); ++ ++ ret = set_phy_power_on(data); ++ if (ret) ++ goto err_phy_power_on; ++ ++ return 0; ++ ++err_phy_power_on: ++ phy_exit(data->usb3_phy); ++err_phy3_init: ++ phy_exit(data->usb2_phy); ++ return ret; ++} ++ ++static void cdns_starfive_phy_deinit(struct cdns_starfive *data) ++{ ++ phy_power_off(data->usb3_phy); ++ phy_power_off(data->usb2_phy); ++ phy_exit(data->usb3_phy); ++ phy_exit(data->usb2_phy); ++} ++ ++static int cdns_starfive_platform_device_add(struct platform_device *pdev, ++ struct cdns_starfive *data) ++{ ++ struct platform_device *cdns3; ++ struct resource cdns_res[CDNS_RESOURCES_NUM], *res; ++ struct device *dev = &pdev->dev; ++ const char *reg_name[CDNS_IOMEM_RESOURCES_NUM] = {"otg", "xhci", "dev"}; ++ const char *irq_name[CDNS_IRQ_RESOURCES_NUM] = {"host", "peripheral", "otg", "wakeup"}; ++ int i, ret, res_idx = 0; ++ ++ cdns3 = platform_device_alloc("cdns-usb3", PLATFORM_DEVID_AUTO); ++ if (!cdns3) ++ return dev_err_probe(dev, -ENOMEM, ++ "couldn't alloc cdns3 usb device\n"); ++ ++ cdns3->dev.parent = dev; ++ memset(cdns_res, 0, sizeof(cdns_res)); ++ ++ for (i = 0; i < CDNS_IOMEM_RESOURCES_NUM; i++) { ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, reg_name[i]); ++ if (!res) { ++ ret = dev_err_probe(dev, ++ -ENXIO, ++ "couldn't get %s reg resource\n", ++ reg_name[i]); ++ goto free_memory; ++ } ++ cdns_res[res_idx] = *res; ++ res_idx++; ++ } ++ ++ for (i = 0; i < CDNS_IRQ_RESOURCES_NUM; i++) { ++ if (i == CDNS_IRQ_WAKEUP_INDEX) { ++ ret = platform_get_irq_byname_optional(pdev, irq_name[i]); ++ if (ret < 0) ++ continue; ++ } else { ++ ret = platform_get_irq_byname(pdev, irq_name[i]); ++ if (ret < 0) { ++ dev_err(dev, "couldn't get %s irq\n", irq_name[i]); ++ goto free_memory; ++ } ++ } ++ cdns_res[res_idx].start = ret; ++ cdns_res[res_idx].end = ret; ++ cdns_res[res_idx].flags = IORESOURCE_IRQ; ++ cdns_res[res_idx].name = irq_name[i]; ++ res_idx++; ++ } ++ ++ ret = platform_device_add_resources(cdns3, cdns_res, res_idx); ++ if (ret) { ++ dev_err(dev, "couldn't add res to cdns3 device\n"); ++ goto free_memory; ++ } ++ ++ ret = platform_device_add(cdns3); ++ if (ret) { ++ dev_err(dev, "failed to register cdns3 device\n"); ++ goto free_memory; ++ } ++ ++ return ret; ++free_memory: ++ platform_device_put(cdns3); ++ return ret; ++} ++ ++static int cdns_starfive_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct cdns_starfive *data; ++ unsigned int args; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, data); ++ ++ data->dev = dev; ++ ++ data->stg_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", 1, &args); ++ ++ if (IS_ERR(data->stg_syscon)) ++ return dev_err_probe(dev, PTR_ERR(data->stg_syscon), ++ "Failed to parse starfive,stg-syscon\n"); ++ ++ data->stg_usb_mode = args; ++ ++ data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks); ++ if (data->num_clks < 0) ++ return dev_err_probe(data->dev, -ENODEV, ++ "Failed to get clocks\n"); ++ ++ data->resets = devm_reset_control_array_get_exclusive(data->dev); ++ if (IS_ERR(data->resets)) ++ return dev_err_probe(data->dev, PTR_ERR(data->resets), ++ "Failed to get resets"); ++ ++ data->usb2_phy = devm_phy_optional_get(dev, "usb2"); ++ if (IS_ERR(data->usb2_phy)) ++ return dev_err_probe(dev, PTR_ERR(data->usb2_phy), ++ "Failed to parse usb2 PHY\n"); ++ ++ data->usb3_phy = devm_phy_optional_get(dev, "usb3"); ++ if (IS_ERR(data->usb3_phy)) ++ return dev_err_probe(dev, PTR_ERR(data->usb3_phy), ++ "Failed to parse usb3 PHY\n"); ++ ++ cdns_mode_init(pdev, data); ++ ++ ret = cdns_clk_rst_init(data); ++ if (ret) ++ return ret; ++ ++ ret = cdns_starfive_phy_init(data); ++ if (ret) { ++ dev_err(dev, "Failed to init PHY\n"); ++ goto err_clk_init; ++ } ++ ++ ret = cdns_starfive_platform_device_add(pdev, data); ++ if (ret) { ++ dev_err(dev, "Failed to create children\n"); ++ goto err_phy_init; ++ } ++ ++ device_set_wakeup_capable(dev, true); ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ ++ dev_info(dev, "usb mode %d probe success\n", data->phy_mode); ++ ++ return 0; ++ ++err_phy_init: ++ cdns_starfive_phy_deinit(data); ++err_clk_init: ++ cdns_clk_rst_deinit(data); ++ return ret; ++} ++ ++static int cdns_starfive_remove_core(struct device *dev, void *c) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ platform_device_unregister(pdev); ++ ++ return 0; ++} ++ ++static int cdns_starfive_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ pm_runtime_get_sync(dev); ++ device_for_each_child(dev, NULL, cdns_starfive_remove_core); ++ ++ cdns_starfive_phy_deinit(data); ++ cdns_clk_rst_deinit(data); ++ pm_runtime_disable(dev); ++ pm_runtime_put_noidle(dev); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int cdns_starfive_resume(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(data->num_clks, data->clks); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_deassert(data->resets); ++ if (ret) { ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++ return ret; ++ } ++ ++ ret = cdns_starfive_phy_init(data); ++ if (ret) ++ cdns_clk_rst_deinit(data); ++ ++ return ret; ++} ++ ++static int cdns_starfive_suspend(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ cdns_starfive_phy_deinit(data); ++ cdns_clk_rst_deinit(data); ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops cdns_starfive_pm_ops = { ++ SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume) ++}; ++ ++static const struct of_device_id cdns_starfive_of_match[] = { ++ { .compatible = "starfive,jh7110-usb", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, cdns_starfive_of_match); ++ ++static struct platform_driver cdns_starfive_driver = { ++ .probe = cdns_starfive_probe, ++ .remove = cdns_starfive_remove, ++ .driver = { ++ .name = "cdns3-starfive", ++ .of_match_table = cdns_starfive_of_match, ++ .pm = &cdns_starfive_pm_ops, ++ }, ++}; ++module_platform_driver(cdns_starfive_driver); ++ ++MODULE_ALIAS("platform:cdns3-starfive"); ++MODULE_AUTHOR("YanHong Wang "); ++MODULE_AUTHOR("Mason Huo "); ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer"); +diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h +index 2d332a788871..8d44ab504898 100644 +--- a/drivers/usb/cdns3/core.h ++++ b/drivers/usb/cdns3/core.h +@@ -38,6 +38,9 @@ struct cdns_role_driver { + }; + + #define CDNS_XHCI_RESOURCES_NUM 2 ++#define CDNS_IOMEM_RESOURCES_NUM 3 ++#define CDNS_IRQ_RESOURCES_NUM 4 ++#define CDNS_RESOURCES_NUM (CDNS_IOMEM_RESOURCES_NUM + CDNS_IRQ_RESOURCES_NUM) + + struct cdns3_platform_data { + int (*platform_suspend)(struct device *dev, +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0064-riscv-dts-starfive-Add-USB-dts-configuration-for-JH7.patch b/srcpkgs/linux6.3/patches/0064-riscv-dts-starfive-Add-USB-dts-configuration-for-JH7.patch new file mode 100644 index 0000000000000..46db6d8cee1d4 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0064-riscv-dts-starfive-Add-USB-dts-configuration-for-JH7.patch @@ -0,0 +1,91 @@ +From b0357b683e37fd821b85488f9ce7ab457857f92a Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 20 Apr 2023 19:00:52 +0800 +Subject: [PATCH 64/84] riscv: dts: starfive: Add USB dts configuration for + JH7110 + +Add USB wrapper layer and Cadence USB3 controller dts +configuration for StarFive JH7110 SoC and VisionFive2 +Board. +USB controller connect to PHY, The PHY dts configuration +are also added. + +Signed-off-by: Minda Chen +--- + .../jh7110-starfive-visionfive-2.dtsi | 7 +++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 44 +++++++++++++++++++ + 2 files changed, 51 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 4cd9b133d0dd..31454e15acfc 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -251,3 +251,10 @@ &U74_3 { + &U74_4 { + cpu-supply = <&vdd_cpu>; + }; ++ ++&usb0 { ++ phys = <&usbphy0>; ++ phy-names = "usb2"; ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index df7a912b73b7..d12ecbba3803 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -399,6 +399,50 @@ i2c2: i2c@10050000 { + status = "disabled"; + }; + ++ usb0: usb@10100000 { ++ compatible = "starfive,jh7110-usb"; ++ reg = <0x0 0x10100000 0x0 0x10000>, ++ <0x0 0x10110000 0x0 0x10000>, ++ <0x0 0x10120000 0x0 0x10000>; ++ reg-names = "otg", "xhci", "dev"; ++ interrupts = <100>, <108>, <110>; ++ interrupt-names = "host", "peripheral", "otg"; ++ clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, ++ <&stgcrg JH7110_STGCLK_USB0_STB>, ++ <&stgcrg JH7110_STGCLK_USB0_APB>, ++ <&stgcrg JH7110_STGCLK_USB0_AXI>, ++ <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; ++ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; ++ resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, ++ <&stgcrg JH7110_STGRST_USB0_APB>, ++ <&stgcrg JH7110_STGRST_USB0_AXI>, ++ <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; ++ reset-names = "pwrup", "apb", "axi", "utmi_apb"; ++ starfive,stg-syscon = <&stg_syscon 0x4>; ++ status = "disabled"; ++ }; ++ ++ usbphy0: phy@10200000 { ++ compatible = "starfive,jh7110-usb-phy"; ++ reg = <0x0 0x10200000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&stgcrg JH7110_STGCLK_USB0_APP_125>; ++ clock-names = "125m", "app_125m"; ++ #phy-cells = <0>; ++ }; ++ ++ pciephy0: phy@10210000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x0 0x10210000 0x0 0x10000>; ++ #phy-cells = <0>; ++ }; ++ ++ pciephy1: phy@10220000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x0 0x10220000 0x0 0x10000>; ++ #phy-cells = <0>; ++ }; ++ + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0065-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch b/srcpkgs/linux6.3/patches/0065-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch new file mode 100644 index 0000000000000..59f8be269df31 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0065-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch @@ -0,0 +1,88 @@ +From 2e23192c5ad85d32625e31ee28135075280c7bde Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Fri, 12 May 2023 10:20:30 +0800 +Subject: [PATCH 65/84] dt-bindings: clock: Add StarFive JH7110 PLL clock + generator + +Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ + 2 files changed, 52 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml +new file mode 100644 +index 000000000000..8aa8c7b8e42f +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml +@@ -0,0 +1,46 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PLL Clock Generator ++ ++description: ++ This PLL are high speed, low jitter frequency synthesizers in JH7110. ++ Each PLL clocks work in integer mode or fraction mode by some dividers, ++ and the configuration registers and dividers are set in several syscon ++ registers. So pll node should be a child of SYS-SYSCON node. ++ The formula for calculating frequency is that, ++ Fvco = Fref * (NI + NF) / M / Q1 ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pll ++ ++ clocks: ++ maxItems: 1 ++ description: Main Oscillator (24 MHz) ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - clocks ++ - '#clock-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pll-clock-controller { ++ compatible = "starfive,jh7110-pll"; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 016227c64a27..ecb5f80d6f23 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -7,6 +7,12 @@ + #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + ++/* PLL clocks */ ++#define JH7110_CLK_PLL0_OUT 0 ++#define JH7110_CLK_PLL1_OUT 1 ++#define JH7110_CLK_PLL2_OUT 2 ++#define JH7110_PLLCLK_END 3 ++ + /* SYSCRG clocks */ + #define JH7110_SYSCLK_CPU_ROOT 0 + #define JH7110_SYSCLK_CPU_CORE 1 +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0066-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch b/srcpkgs/linux6.3/patches/0066-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch new file mode 100644 index 0000000000000..0f92d4f91ba07 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0066-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch @@ -0,0 +1,704 @@ +From 2c2dbadc51b12bfe8dd02b03c158e0879e1dcc30 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Fri, 12 May 2023 10:20:31 +0800 +Subject: [PATCH 66/84] clk: starfive: Add StarFive JH7110 PLL clock driver + +Add driver for the StarFive JH7110 PLL clock controller +and they work by reading and setting syscon registers. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 8 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-pll.c | 309 ++++++++++++++++ + .../clk/starfive/clk-starfive-jh7110-pll.h | 331 ++++++++++++++++++ + 4 files changed, 649 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index b0c7744965d7..abe1de1eafa7 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -21,6 +21,14 @@ config CLK_STARFIVE_JH7100_AUDIO + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. + ++config CLK_STARFIVE_JH7110_PLL ++ bool "StarFive JH7110 PLL clock support" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE ++ help ++ Say yes here to support the PLL clock controller on the ++ StarFive JH7110 SoC. ++ + config CLK_STARFIVE_JH7110_SYS + bool "StarFive JH7110 system clock support" + depends on ARCH_STARFIVE || COMPILE_TEST +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 841377e45bb6..199ac0f37a2f 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o + obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o + obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + ++obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +new file mode 100644 +index 000000000000..f86deddd4bef +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +@@ -0,0 +1,309 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 PLL Clock Generator Driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * This driver is about to register JH7110 PLL clock generator and support ops. ++ * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2. ++ * Each PLL clocks work in integer mode or fraction mode by some dividers, ++ * and the configuration registers and dividers are set in several syscon registers. ++ * The formula for calculating frequency is: ++ * Fvco = Fref * (NI + NF) / M / Q1 ++ * Fref: OSC source clock rate ++ * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]. ++ * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999. ++ * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. ++ * Q1: frequency dividing ratio of post divider, set by postdiv1[1:0], Q1= 1,2,4,8. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110-pll.h" ++ ++struct jh7110_pll_conf_variant { ++ unsigned int pll_nums; ++ struct jh7110_pll_syscon_conf conf[]; ++}; ++ ++static const struct jh7110_pll_conf_variant jh7110_pll_variant = { ++ .pll_nums = JH7110_PLLCLK_END, ++ .conf = { ++ JH7110_PLL(JH7110_CLK_PLL0_OUT, "pll0_out", ++ JH7110_PLL0_FREQ_MAX, jh7110_pll0_syscon_val_preset), ++ JH7110_PLL(JH7110_CLK_PLL1_OUT, "pll1_out", ++ JH7110_PLL1_FREQ_MAX, jh7110_pll1_syscon_val_preset), ++ JH7110_PLL(JH7110_CLK_PLL2_OUT, "pll2_out", ++ JH7110_PLL2_FREQ_MAX, jh7110_pll2_syscon_val_preset), ++ }, ++}; ++ ++static struct jh7110_clk_pll_data *jh7110_pll_data_from(struct clk_hw *hw) ++{ ++ return container_of(hw, struct jh7110_clk_pll_data, hw); ++} ++ ++static struct jh7110_clk_pll_priv *jh7110_pll_priv_from(struct jh7110_clk_pll_data *data) ++{ ++ return container_of(data, struct jh7110_clk_pll_priv, data[data->idx]); ++} ++ ++/* Read register value from syscon and calculate PLL(x) frequency */ ++static unsigned long jh7110_pll_get_freq(struct jh7110_clk_pll_data *data, ++ unsigned long parent_rate) ++{ ++ struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data); ++ struct jh7110_pll_syscon_offset *offset = &data->conf.offsets; ++ struct jh7110_pll_syscon_mask *mask = &data->conf.masks; ++ struct jh7110_pll_syscon_shift *shift = &data->conf.shifts; ++ unsigned long frac_cal; ++ u32 dacpd; ++ u32 dsmpd; ++ u32 fbdiv; ++ u32 prediv; ++ u32 postdiv1; ++ u32 frac; ++ u32 reg_val; ++ ++ regmap_read(priv->syscon_regmap, offset->dacpd, ®_val); ++ dacpd = (reg_val & mask->dacpd) >> shift->dacpd; ++ ++ regmap_read(priv->syscon_regmap, offset->dsmpd, ®_val); ++ dsmpd = (reg_val & mask->dsmpd) >> shift->dsmpd; ++ ++ regmap_read(priv->syscon_regmap, offset->fbdiv, ®_val); ++ fbdiv = (reg_val & mask->fbdiv) >> shift->fbdiv; ++ ++ regmap_read(priv->syscon_regmap, offset->prediv, ®_val); ++ prediv = (reg_val & mask->prediv) >> shift->prediv; ++ ++ regmap_read(priv->syscon_regmap, offset->postdiv1, ®_val); ++ /* postdiv1 = 2 ^ reg_val */ ++ postdiv1 = 1 << ((reg_val & mask->postdiv1) >> shift->postdiv1); ++ ++ regmap_read(priv->syscon_regmap, offset->frac, ®_val); ++ frac = (reg_val & mask->frac) >> shift->frac; ++ ++ /* ++ * Integer Mode (Both 1) or Fraction Mode (Both 0). ++ * And the decimal places are counted by expanding them by ++ * a factor of STARFIVE_PLL_FRAC_PATR_SIZE. ++ */ ++ if (dacpd == 1 && dsmpd == 1) ++ frac_cal = 0; ++ else if (dacpd == 0 && dsmpd == 0) ++ frac_cal = (unsigned long)frac * STARFIVE_PLL_FRAC_PATR_SIZE / (1 << 24); ++ else ++ return 0; ++ ++ /* Fvco = Fref * (NI + NF) / M / Q1 */ ++ return (parent_rate / STARFIVE_PLL_FRAC_PATR_SIZE * ++ (fbdiv * STARFIVE_PLL_FRAC_PATR_SIZE + frac_cal) / prediv / postdiv1); ++} ++ ++static unsigned long jh7110_pll_rate_sub_fabs(unsigned long rate1, unsigned long rate2) ++{ ++ return rate1 > rate2 ? (rate1 - rate2) : (rate2 - rate1); ++} ++ ++/* Select the appropriate frequency from the already configured registers value */ ++static void jh7110_pll_select_near_freq_id(struct jh7110_clk_pll_data *data, ++ unsigned long rate) ++{ ++ const struct jh7110_pll_syscon_val *val; ++ unsigned int id; ++ unsigned long rate_diff; ++ ++ /* compare the frequency one by one from small to large in order */ ++ for (id = 0; id < data->conf.preset_val_nums; id++) { ++ val = &data->conf.preset_val[id]; ++ ++ if (rate == val->freq) ++ goto match_end; ++ ++ /* select near frequency */ ++ if (rate < val->freq) { ++ /* The last frequency is closer to the target rate than this time. */ ++ if (id > 0) ++ if (rate_diff < jh7110_pll_rate_sub_fabs(rate, val->freq)) ++ id--; ++ ++ goto match_end; ++ } else { ++ rate_diff = jh7110_pll_rate_sub_fabs(rate, val->freq); ++ } ++ } ++ ++match_end: ++ data->freq_select_idx = id; ++} ++ ++static int jh7110_pll_set_freq_syscon(struct jh7110_clk_pll_data *data) ++{ ++ struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data); ++ struct jh7110_pll_syscon_offset *offset = &data->conf.offsets; ++ struct jh7110_pll_syscon_mask *mask = &data->conf.masks; ++ struct jh7110_pll_syscon_shift *shift = &data->conf.shifts; ++ const struct jh7110_pll_syscon_val *val = &data->conf.preset_val[data->freq_select_idx]; ++ ++ /* frac: Integer Mode (Both 1) or Fraction Mode (Both 0) */ ++ if (val->dacpd == 0 && val->dsmpd == 0) ++ regmap_update_bits(priv->syscon_regmap, offset->frac, mask->frac, ++ (val->frac << shift->frac)); ++ else if (val->dacpd != val->dsmpd) ++ return -EINVAL; ++ ++ /* fbdiv value should be 8 to 4095 */ ++ if (val->fbdiv < 8) ++ return -EINVAL; ++ ++ regmap_update_bits(priv->syscon_regmap, offset->dacpd, mask->dacpd, ++ (val->dacpd << shift->dacpd)); ++ regmap_update_bits(priv->syscon_regmap, offset->dsmpd, mask->dsmpd, ++ (val->dsmpd << shift->dsmpd)); ++ regmap_update_bits(priv->syscon_regmap, offset->prediv, mask->prediv, ++ (val->prediv << shift->prediv)); ++ regmap_update_bits(priv->syscon_regmap, offset->fbdiv, mask->fbdiv, ++ (val->fbdiv << shift->fbdiv)); ++ regmap_update_bits(priv->syscon_regmap, offset->postdiv1, mask->postdiv1, ++ ((val->postdiv1 >> 1) << shift->postdiv1)); ++ ++ return 0; ++} ++ ++static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw); ++ ++ return jh7110_pll_get_freq(data, parent_rate); ++} ++ ++static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) ++{ ++ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw); ++ ++ jh7110_pll_select_near_freq_id(data, req->rate); ++ req->rate = data->conf.preset_val[data->freq_select_idx].freq; ++ ++ return 0; ++} ++ ++static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw); ++ ++ return jh7110_pll_set_freq_syscon(data); ++} ++ ++#ifdef CONFIG_DEBUG_FS ++static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ static const struct debugfs_reg32 jh7110_clk_pll_reg = { ++ .name = "CTRL", ++ .offset = 0, ++ }; ++ struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw); ++ struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data); ++ struct debugfs_regset32 *regset; ++ ++ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); ++ if (!regset) ++ return; ++ ++ regset->regs = &jh7110_clk_pll_reg; ++ regset->nregs = 1; ++ ++ debugfs_create_regset32("registers", 0400, dentry, regset); ++} ++#else ++#define jh7110_pll_debug_init NULL ++#endif ++ ++static const struct clk_ops jh7110_pll_ops = { ++ .recalc_rate = jh7110_pll_recalc_rate, ++ .determine_rate = jh7110_pll_determine_rate, ++ .set_rate = jh7110_pll_set_rate, ++ .debug_init = jh7110_pll_debug_init, ++}; ++ ++static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh7110_clk_pll_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < priv->pll_nums) ++ return &priv->data[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int jh7110_pll_probe(struct platform_device *pdev) ++{ ++ const struct jh7110_pll_conf_variant *variant; ++ struct jh7110_clk_pll_priv *priv; ++ struct jh7110_clk_pll_data *data; ++ int ret; ++ unsigned int idx; ++ ++ variant = of_device_get_match_data(&pdev->dev); ++ if (!variant) ++ return -ENOMEM; ++ ++ priv = devm_kzalloc(&pdev->dev, struct_size(priv, data, variant->pll_nums), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->dev = &pdev->dev; ++ priv->syscon_regmap = syscon_node_to_regmap(priv->dev->of_node->parent); ++ if (IS_ERR(priv->syscon_regmap)) ++ return PTR_ERR(priv->syscon_regmap); ++ ++ priv->pll_nums = variant->pll_nums; ++ for (idx = 0; idx < priv->pll_nums; idx++) { ++ struct clk_parent_data parents = { ++ .index = 0, ++ }; ++ struct clk_init_data init = { ++ .name = variant->conf[idx].name, ++ .ops = &jh7110_pll_ops, ++ .parent_data = &parents, ++ .num_parents = 1, ++ .flags = 0, ++ }; ++ ++ data = &priv->data[idx]; ++ data->conf = variant->conf[idx]; ++ data->hw.init = &init; ++ data->idx = idx; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &data->hw); ++ if (ret) ++ return ret; ++ } ++ ++ return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv); ++} ++ ++static const struct of_device_id jh7110_pll_match[] = { ++ { .compatible = "starfive,jh7110-pll", .data = &jh7110_pll_variant }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_pll_match); ++ ++static struct platform_driver jh7110_pll_driver = { ++ .driver = { ++ .name = "clk-starfive-jh7110-pll", ++ .of_match_table = jh7110_pll_match, ++ }, ++}; ++builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe); +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h +new file mode 100644 +index 000000000000..526f21670fe3 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h +@@ -0,0 +1,331 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR MIT */ ++/* ++ * StarFive JH7110 PLL Clock Generator Driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef _CLK_STARFIVE_JH7110_PLL_H_ ++#define _CLK_STARFIVE_JH7110_PLL_H_ ++ ++#include ++ ++/* The decimal places are counted by expanding them by a factor of STARFIVE_PLL_FRAC_PATR_SIZE */ ++#define STARFIVE_PLL_FRAC_PATR_SIZE 1000 ++ ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DACPD_OFFSET 0x18 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DACPD_SHIFT 24 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DACPD_MASK BIT(24) ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DSMPD_OFFSET 0x18 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DSMPD_SHIFT 25 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_DSMPD_MASK BIT(25) ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FBDIV_OFFSET 0x1c ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FBDIV_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FBDIV_MASK GENMASK(11, 0) ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FRAC_OFFSET 0x20 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FRAC_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_FRAC_MASK GENMASK(23, 0) ++#define STARFIVE_JH7110_CLK_PLL0_OUT_POSTDIV1_OFFSET 0x20 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_POSTDIV1_SHIFT 28 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_POSTDIV1_MASK GENMASK(29, 28) ++#define STARFIVE_JH7110_CLK_PLL0_OUT_PREDIV_OFFSET 0x24 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_PREDIV_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL0_OUT_PREDIV_MASK GENMASK(5, 0) ++ ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DACPD_OFFSET 0x24 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DACPD_SHIFT 15 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DACPD_MASK BIT(15) ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DSMPD_OFFSET 0x24 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DSMPD_SHIFT 16 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_DSMPD_MASK BIT(16) ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FBDIV_OFFSET 0x24 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FBDIV_SHIFT 17 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FBDIV_MASK GENMASK(28, 17) ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FRAC_OFFSET 0x28 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FRAC_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_FRAC_MASK GENMASK(23, 0) ++#define STARFIVE_JH7110_CLK_PLL1_OUT_POSTDIV1_OFFSET 0x28 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_POSTDIV1_SHIFT 28 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_POSTDIV1_MASK GENMASK(29, 28) ++#define STARFIVE_JH7110_CLK_PLL1_OUT_PREDIV_OFFSET 0x2c ++#define STARFIVE_JH7110_CLK_PLL1_OUT_PREDIV_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL1_OUT_PREDIV_MASK GENMASK(5, 0) ++ ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DACPD_OFFSET 0x2c ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DACPD_SHIFT 15 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DACPD_MASK BIT(15) ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DSMPD_OFFSET 0x2c ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DSMPD_SHIFT 16 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_DSMPD_MASK BIT(16) ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FBDIV_OFFSET 0x2c ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FBDIV_SHIFT 17 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FBDIV_MASK GENMASK(28, 17) ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FRAC_OFFSET 0x30 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FRAC_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_FRAC_MASK GENMASK(23, 0) ++#define STARFIVE_JH7110_CLK_PLL2_OUT_POSTDIV1_OFFSET 0x30 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_POSTDIV1_SHIFT 28 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_POSTDIV1_MASK GENMASK(29, 28) ++#define STARFIVE_JH7110_CLK_PLL2_OUT_PREDIV_OFFSET 0x34 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_PREDIV_SHIFT 0 ++#define STARFIVE_JH7110_CLK_PLL2_OUT_PREDIV_MASK GENMASK(5, 0) ++ ++#define JH7110_PLL(_idx, _name, _nums, _val) \ ++[_idx] = { \ ++ .name = _name, \ ++ .offsets = { \ ++ .dacpd = STARFIVE_##_idx##_DACPD_OFFSET, \ ++ .dsmpd = STARFIVE_##_idx##_DSMPD_OFFSET, \ ++ .fbdiv = STARFIVE_##_idx##_FBDIV_OFFSET, \ ++ .frac = STARFIVE_##_idx##_FRAC_OFFSET, \ ++ .prediv = STARFIVE_##_idx##_PREDIV_OFFSET, \ ++ .postdiv1 = STARFIVE_##_idx##_POSTDIV1_OFFSET, \ ++ }, \ ++ .masks = { \ ++ .dacpd = STARFIVE_##_idx##_DACPD_MASK, \ ++ .dsmpd = STARFIVE_##_idx##_DSMPD_MASK, \ ++ .fbdiv = STARFIVE_##_idx##_FBDIV_MASK, \ ++ .frac = STARFIVE_##_idx##_FRAC_MASK, \ ++ .prediv = STARFIVE_##_idx##_PREDIV_MASK, \ ++ .postdiv1 = STARFIVE_##_idx##_POSTDIV1_MASK, \ ++ }, \ ++ .shifts = { \ ++ .dacpd = STARFIVE_##_idx##_DACPD_SHIFT, \ ++ .dsmpd = STARFIVE_##_idx##_DSMPD_SHIFT, \ ++ .fbdiv = STARFIVE_##_idx##_FBDIV_SHIFT, \ ++ .frac = STARFIVE_##_idx##_FRAC_SHIFT, \ ++ .prediv = STARFIVE_##_idx##_PREDIV_SHIFT, \ ++ .postdiv1 = STARFIVE_##_idx##_POSTDIV1_SHIFT, \ ++ }, \ ++ .preset_val_nums = _nums, \ ++ .preset_val = _val, \ ++} ++ ++struct jh7110_pll_syscon_offset { ++ unsigned int dacpd; ++ unsigned int dsmpd; ++ unsigned int fbdiv; ++ unsigned int frac; ++ unsigned int prediv; ++ unsigned int postdiv1; ++}; ++ ++struct jh7110_pll_syscon_mask { ++ u32 dacpd; ++ u32 dsmpd; ++ u32 fbdiv; ++ u32 frac; ++ u32 prediv; ++ u32 postdiv1; ++}; ++ ++struct jh7110_pll_syscon_shift { ++ char dacpd; ++ char dsmpd; ++ char fbdiv; ++ char frac; ++ char prediv; ++ char postdiv1; ++}; ++ ++struct jh7110_pll_syscon_val { ++ unsigned long freq; ++ u32 prediv; ++ u32 fbdiv; ++ u32 postdiv1; ++/* Both daxpd and dsmpd set 1 while integer mode */ ++/* Both daxpd and dsmpd set 0 while fraction mode */ ++ u32 dacpd; ++ u32 dsmpd; ++/* frac value should be decimals multiplied by 2^24 */ ++ u32 frac; ++}; ++ ++struct jh7110_pll_syscon_conf { ++ char *name; ++ struct jh7110_pll_syscon_offset offsets; ++ struct jh7110_pll_syscon_mask masks; ++ struct jh7110_pll_syscon_shift shifts; ++ unsigned int preset_val_nums; ++ const struct jh7110_pll_syscon_val *preset_val; ++}; ++ ++struct jh7110_clk_pll_data { ++ struct clk_hw hw; ++ unsigned int idx; ++ unsigned int freq_select_idx; ++ struct jh7110_pll_syscon_conf conf; ++}; ++ ++struct jh7110_clk_pll_priv { ++ unsigned int pll_nums; ++ struct device *dev; ++ struct regmap *syscon_regmap; ++ struct jh7110_clk_pll_data data[]; ++}; ++ ++enum jh7110_pll0_freq_index { ++ JH7110_PLL0_FREQ_375 = 0, ++ JH7110_PLL0_FREQ_500, ++ JH7110_PLL0_FREQ_625, ++ JH7110_PLL0_FREQ_750, ++ JH7110_PLL0_FREQ_875, ++ JH7110_PLL0_FREQ_1000, ++ JH7110_PLL0_FREQ_1250, ++ JH7110_PLL0_FREQ_1375, ++ JH7110_PLL0_FREQ_1500, ++ JH7110_PLL0_FREQ_MAX ++}; ++ ++enum jh7110_pll1_freq_index { ++ JH7110_PLL1_FREQ_1066 = 0, ++ JH7110_PLL1_FREQ_1200, ++ JH7110_PLL1_FREQ_1400, ++ JH7110_PLL1_FREQ_1600, ++ JH7110_PLL1_FREQ_MAX ++}; ++ ++enum jh7110_pll2_freq_index { ++ JH7110_PLL2_FREQ_1188 = 0, ++ JH7110_PLL2_FREQ_12288, ++ JH7110_PLL2_FREQ_MAX ++}; ++ ++/* ++ * Because the pll frequency is relatively fixed, ++ * it cannot be set arbitrarily, so it needs a specific configuration. ++ * PLL0 frequency should be multiple of 125MHz (USB frequency). ++ */ ++static const struct jh7110_pll_syscon_val ++ jh7110_pll0_syscon_val_preset[] = { ++ [JH7110_PLL0_FREQ_375] = { ++ .freq = 375000000, ++ .prediv = 8, ++ .fbdiv = 125, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_500] = { ++ .freq = 500000000, ++ .prediv = 6, ++ .fbdiv = 125, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_625] = { ++ .freq = 625000000, ++ .prediv = 24, ++ .fbdiv = 625, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_750] = { ++ .freq = 750000000, ++ .prediv = 4, ++ .fbdiv = 125, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_875] = { ++ .freq = 875000000, ++ .prediv = 24, ++ .fbdiv = 875, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_1000] = { ++ .freq = 1000000000, ++ .prediv = 3, ++ .fbdiv = 125, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_1250] = { ++ .freq = 1250000000, ++ .prediv = 12, ++ .fbdiv = 625, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_1375] = { ++ .freq = 1375000000, ++ .prediv = 24, ++ .fbdiv = 1375, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL0_FREQ_1500] = { ++ .freq = 1500000000, ++ .prediv = 2, ++ .fbdiv = 125, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++}; ++ ++static const struct jh7110_pll_syscon_val ++ jh7110_pll1_syscon_val_preset[] = { ++ [JH7110_PLL1_FREQ_1066] = { ++ .freq = 1066000000, ++ .prediv = 12, ++ .fbdiv = 533, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL1_FREQ_1200] = { ++ .freq = 1200000000, ++ .prediv = 1, ++ .fbdiv = 50, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL1_FREQ_1400] = { ++ .freq = 1400000000, ++ .prediv = 6, ++ .fbdiv = 350, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL1_FREQ_1600] = { ++ .freq = 1600000000, ++ .prediv = 3, ++ .fbdiv = 200, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++}; ++ ++static const struct jh7110_pll_syscon_val ++ jh7110_pll2_syscon_val_preset[] = { ++ [JH7110_PLL2_FREQ_1188] = { ++ .freq = 1188000000, ++ .prediv = 2, ++ .fbdiv = 99, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++ [JH7110_PLL2_FREQ_12288] = { ++ .freq = 1228800000, ++ .prediv = 5, ++ .fbdiv = 256, ++ .postdiv1 = 1, ++ .dacpd = 1, ++ .dsmpd = 1, ++ }, ++}; ++ ++#endif +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0067-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch b/srcpkgs/linux6.3/patches/0067-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch new file mode 100644 index 0000000000000..06a0b281912bd --- /dev/null +++ b/srcpkgs/linux6.3/patches/0067-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch @@ -0,0 +1,79 @@ +From 13def4321ee652ce59571a3171e91b47c92d13fc Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Fri, 12 May 2023 10:20:32 +0800 +Subject: [PATCH 67/84] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs + +Add PLL clock inputs from PLL clock generator. + +Acked-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-syscrg.yaml | 20 +++++++++++++++++-- + 1 file changed, 18 insertions(+), 2 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +index 84373ae31644..fcb363353050 100644 +--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +@@ -27,6 +27,9 @@ properties: + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock ++ - description: PLL0 ++ - description: PLL1 ++ - description: PLL2 + + - items: + - description: Main Oscillator (24 MHz) +@@ -38,6 +41,9 @@ properties: + - description: External I2S RX left/right channel clock + - description: External TDM clock + - description: External audio master clock ++ - description: PLL0 ++ - description: PLL1 ++ - description: PLL2 + + clock-names: + oneOf: +@@ -52,6 +58,9 @@ properties: + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext ++ - const: pll0_out ++ - const: pll1_out ++ - const: pll2_out + + - items: + - const: osc +@@ -63,6 +72,9 @@ properties: + - const: i2srx_lrck_ext + - const: tdm_ext + - const: mclk_ext ++ - const: pll0_out ++ - const: pll1_out ++ - const: pll2_out + + '#clock-cells': + const: 1 +@@ -93,12 +105,16 @@ examples: + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, +- <&tdm_ext>, <&mclk_ext>; ++ <&tdm_ext>, <&mclk_ext>, ++ <&pllclk 0>, ++ <&pllclk 1>, ++ <&pllclk 2>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", +- "tdm_ext", "mclk_ext"; ++ "tdm_ext", "mclk_ext", ++ "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0068-clk-starfive-jh7110-sys-Modify-PLL-clocks-source.patch b/srcpkgs/linux6.3/patches/0068-clk-starfive-jh7110-sys-Modify-PLL-clocks-source.patch new file mode 100644 index 0000000000000..8c575a3c75688 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0068-clk-starfive-jh7110-sys-Modify-PLL-clocks-source.patch @@ -0,0 +1,78 @@ +From e5f2a4ccbab141a4079b5ee8c98cb4264d30b046 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Fri, 12 May 2023 10:20:33 +0800 +Subject: [PATCH 68/84] clk: starfive: jh7110-sys: Modify PLL clocks source + +Modify PLL clocks source to be got from dts instead of +the fixed factor clocks. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 1 + + .../clk/starfive/clk-starfive-jh7110-sys.c | 31 ++++--------------- + 2 files changed, 7 insertions(+), 25 deletions(-) + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index abe1de1eafa7..6818be51c067 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS + select AUXILIARY_BUS + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JH7110 ++ select CLK_STARFIVE_JH7110_PLL + default ARCH_STARFIVE + help + Say yes here to support the system clock controller on the +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +index 5ec210644e1d..439999dc2191 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c ++++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +@@ -395,29 +395,6 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + + dev_set_drvdata(priv->dev, (void *)(&priv->base)); + +- /* +- * These PLL clocks are not actually fixed factor clocks and can be +- * controlled by the syscon registers of JH7110. They will be dropped +- * and registered in the PLL clock driver instead. +- */ +- /* 24MHz -> 1000.0MHz */ +- priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", +- "osc", 0, 125, 3); +- if (IS_ERR(priv->pll[0])) +- return PTR_ERR(priv->pll[0]); +- +- /* 24MHz -> 1066.0MHz */ +- priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", +- "osc", 0, 533, 12); +- if (IS_ERR(priv->pll[1])) +- return PTR_ERR(priv->pll[1]); +- +- /* 24MHz -> 1188.0MHz */ +- priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", +- "osc", 0, 99, 2); +- if (IS_ERR(priv->pll[2])) +- return PTR_ERR(priv->pll[2]); +- + for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { + u32 max = jh7110_sysclk_data[idx].max; + struct clk_parent_data parents[4] = {}; +@@ -455,8 +432,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + parents[i].fw_name = "tdm_ext"; + else if (pidx == JH7110_SYSCLK_MCLK_EXT) + parents[i].fw_name = "mclk_ext"; +- else +- parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; ++ else if (pidx == JH7110_SYSCLK_PLL0_OUT) ++ parents[i].fw_name = "pll0_out"; ++ else if (pidx == JH7110_SYSCLK_PLL1_OUT) ++ parents[i].fw_name = "pll1_out"; ++ else if (pidx == JH7110_SYSCLK_PLL2_OUT) ++ parents[i].fw_name = "pll2_out"; + } + + clk->hw.init = &init; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0069-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch b/srcpkgs/linux6.3/patches/0069-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch new file mode 100644 index 0000000000000..5365c646444d6 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0069-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch @@ -0,0 +1,92 @@ +From 0d7144eadf7d438801636f65613d910be33b9010 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Fri, 12 May 2023 10:20:34 +0800 +Subject: [PATCH 69/84] dt-bindings: soc: starfive: Add StarFive syscon module + +Add documentation to describe StarFive System Controller Registers. + +Co-developed-by: Xingyu Wu +Signed-off-by: Xingyu Wu +Reviewed-by: Rob Herring +Signed-off-by: William Qiu +--- + .../soc/starfive/starfive,jh7110-syscon.yaml | 67 +++++++++++++++++++ + 1 file changed, 67 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + +diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml +new file mode 100644 +index 000000000000..26dc99cb0c89 +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml +@@ -0,0 +1,67 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 SoC system controller ++ ++maintainers: ++ - William Qiu ++ ++description: | ++ The StarFive JH7110 SoC system controller provides register information such ++ as offset, mask and shift to configure related modules such as MMC and PCIe. ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - const: starfive,jh7110-sys-syscon ++ - const: syscon ++ - const: simple-mfd ++ - items: ++ - enum: ++ - starfive,jh7110-aon-syscon ++ - starfive,jh7110-stg-syscon ++ - const: syscon ++ ++ reg: ++ maxItems: 1 ++ ++ clock-controller: ++ $ref: /schemas/clock/starfive,jh7110-pll.yaml# ++ type: object ++ ++ "#power-domain-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: starfive,jh7110-aon-syscon ++ then: ++ required: ++ - "#power-domain-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ syscon@10240000 { ++ compatible = "starfive,jh7110-stg-syscon", "syscon"; ++ reg = <0x10240000 0x1000>; ++ }; ++ ++ syscon@13030000 { ++ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; ++ reg = <0x13030000 0x1000>; ++ }; ++ ++... +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0070-riscv-dts-starfive-jh7110-Add-syscon-nodes.patch b/srcpkgs/linux6.3/patches/0070-riscv-dts-starfive-jh7110-Add-syscon-nodes.patch new file mode 100644 index 0000000000000..d9be7ef08485b --- /dev/null +++ b/srcpkgs/linux6.3/patches/0070-riscv-dts-starfive-jh7110-Add-syscon-nodes.patch @@ -0,0 +1,60 @@ +From 6ef46198edd5873490a5758e8fe4b70309bd7762 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Fri, 12 May 2023 10:20:35 +0800 +Subject: [PATCH 70/84] riscv: dts: starfive: jh7110: Add syscon nodes + +Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc. + +Co-developed-by: Xingyu Wu +Signed-off-by: Xingyu Wu +Reviewed-by: Conor Dooley +Reviewed-by: Emil Renner Berthing +Signed-off-by: William Qiu +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index d12ecbba3803..5d248558e421 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -462,6 +462,11 @@ stgcrg: clock-controller@10230000 { + #reset-cells = <1>; + }; + ++ stg_syscon: syscon@10240000 { ++ compatible = "starfive,jh7110-stg-syscon", "syscon"; ++ reg = <0x0 0x10240000 0x0 0x1000>; ++ }; ++ + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; +@@ -566,6 +571,11 @@ syscrg: clock-controller@13020000 { + #reset-cells = <1>; + }; + ++ sys_syscon: syscon@13030000 { ++ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; ++ reg = <0x0 0x13030000 0x0 0x1000>; ++ }; ++ + sysgpio: pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; +@@ -615,6 +625,12 @@ aoncrg: clock-controller@17000000 { + #reset-cells = <1>; + }; + ++ aon_syscon: syscon@17010000 { ++ compatible = "starfive,jh7110-aon-syscon", "syscon"; ++ reg = <0x0 0x17010000 0x0 0x1000>; ++ #power-domain-cells = <1>; ++ }; ++ + aongpio: pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0071-riscv-dts-starfive-jh7110-Add-PLL-clock-node-and-mod.patch b/srcpkgs/linux6.3/patches/0071-riscv-dts-starfive-jh7110-Add-PLL-clock-node-and-mod.patch new file mode 100644 index 0000000000000..01493956fab49 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0071-riscv-dts-starfive-jh7110-Add-PLL-clock-node-and-mod.patch @@ -0,0 +1,53 @@ +From 406afcb5042f7962d68202e593459b96ea4ae3ea Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Fri, 12 May 2023 10:20:36 +0800 +Subject: [PATCH 71/84] riscv: dts: starfive: jh7110: Add PLL clock node and + modify syscrg node + +Add the PLL clock node for the Starfive JH7110 SoC and +modify the SYSCRG node to add PLL clocks input. + +Signed-off-by: Xingyu Wu +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 5d248558e421..6a72d33b2f5a 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -561,12 +561,16 @@ syscrg: clock-controller@13020000 { + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, +- <&tdm_ext>, <&mclk_ext>; ++ <&tdm_ext>, <&mclk_ext>, ++ <&pllclk JH7110_CLK_PLL0_OUT>, ++ <&pllclk JH7110_CLK_PLL1_OUT>, ++ <&pllclk JH7110_CLK_PLL2_OUT>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", +- "tdm_ext", "mclk_ext"; ++ "tdm_ext", "mclk_ext", ++ "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +@@ -574,6 +578,12 @@ syscrg: clock-controller@13020000 { + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; ++ ++ pllclk: clock-controller { ++ compatible = "starfive,jh7110-pll"; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; + }; + + sysgpio: pinctrl@13040000 { +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0072-dt-bindings-dma-snps-dw-axi-dmac-constrain-the-items.patch b/srcpkgs/linux6.3/patches/0072-dt-bindings-dma-snps-dw-axi-dmac-constrain-the-items.patch new file mode 100644 index 0000000000000..31f6100393b6b --- /dev/null +++ b/srcpkgs/linux6.3/patches/0072-dt-bindings-dma-snps-dw-axi-dmac-constrain-the-items.patch @@ -0,0 +1,67 @@ +From ad9276de65cced8257ca7ffdfe02d9bbac951b3c Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Wed, 22 Mar 2023 17:48:17 +0800 +Subject: [PATCH 72/84] dt-bindings: dma: snps,dw-axi-dmac: constrain the items + of resets for JH7110 dma + +The DMA controller needs two reset items to work properly on JH7110 SoC, +so there is need to constrain the items' value to 2, other platforms +have 1 reset item at most. + +Reviewed-by: Rob Herring +Signed-off-by: Walker Chen +--- + .../bindings/dma/snps,dw-axi-dmac.yaml | 23 ++++++++++++++++++- + 1 file changed, 22 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +index 5c81194e2300..363cf8bd150d 100644 +--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml ++++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +@@ -20,6 +20,7 @@ properties: + enum: + - snps,axi-dma-1.01a + - intel,kmb-axi-dma ++ - starfive,jh7110-axi-dma + + reg: + minItems: 1 +@@ -58,7 +59,8 @@ properties: + maximum: 8 + + resets: +- maxItems: 1 ++ minItems: 1 ++ maxItems: 2 + + snps,dma-masters: + description: | +@@ -109,6 +111,25 @@ required: + - snps,priority + - snps,block-size + ++if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - starfive,jh7110-axi-dma ++then: ++ properties: ++ resets: ++ minItems: 2 ++ items: ++ - description: AXI reset line ++ - description: AHB reset line ++ - description: module reset ++else: ++ properties: ++ resets: ++ maxItems: 1 ++ + additionalProperties: false + + examples: +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0073-dmaengine-dw-axi-dmac-Add-support-for-StarFive-JH711.patch b/srcpkgs/linux6.3/patches/0073-dmaengine-dw-axi-dmac-Add-support-for-StarFive-JH711.patch new file mode 100644 index 0000000000000..8c453ab040219 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0073-dmaengine-dw-axi-dmac-Add-support-for-StarFive-JH711.patch @@ -0,0 +1,128 @@ +From 903f55de900e4998005fcc4db4cab4eceb44a7ee Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Wed, 22 Mar 2023 17:48:18 +0800 +Subject: [PATCH 73/84] dmaengine: dw-axi-dmac: Add support for StarFive JH7110 + DMA + +Add DMA reset operation in device probe and use different configuration +on CH_CFG registers according to match data. Update all uses of +of_device_is_compatible with of_device_get_match_data. + +Signed-off-by: Walker Chen +Reviewed-by: Emil Renner Berthing +--- + .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 38 ++++++++++++++++--- + drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + + 2 files changed, 34 insertions(+), 5 deletions(-) + +diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +index 4169e1d7d5ca..6cfcb541d8c3 100644 +--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c ++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +@@ -21,10 +21,12 @@ + #include + #include + #include ++#include + #include + #include + #include + #include ++#include + #include + #include + +@@ -46,6 +48,10 @@ + DMA_SLAVE_BUSWIDTH_32_BYTES | \ + DMA_SLAVE_BUSWIDTH_64_BYTES) + ++#define AXI_DMA_FLAG_HAS_APB_REGS BIT(0) ++#define AXI_DMA_FLAG_HAS_RESETS BIT(1) ++#define AXI_DMA_FLAG_USE_CFG2 BIT(2) ++ + static inline void + axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) + { +@@ -86,7 +92,8 @@ static inline void axi_chan_config_write(struct axi_dma_chan *chan, + + cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | + config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); +- if (chan->chip->dw->hdata->reg_map_8_channels) { ++ if (chan->chip->dw->hdata->reg_map_8_channels && ++ !chan->chip->dw->hdata->use_cfg2) { + cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | + config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | + config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | +@@ -1367,10 +1374,11 @@ static int parse_device_properties(struct axi_dma_chip *chip) + + static int dw_probe(struct platform_device *pdev) + { +- struct device_node *node = pdev->dev.of_node; + struct axi_dma_chip *chip; + struct dw_axi_dma *dw; + struct dw_axi_dma_hcfg *hdata; ++ struct reset_control *resets; ++ unsigned int flags; + u32 i; + int ret; + +@@ -1398,12 +1406,25 @@ static int dw_probe(struct platform_device *pdev) + if (IS_ERR(chip->regs)) + return PTR_ERR(chip->regs); + +- if (of_device_is_compatible(node, "intel,kmb-axi-dma")) { ++ flags = (uintptr_t)of_device_get_match_data(&pdev->dev); ++ if (flags & AXI_DMA_FLAG_HAS_APB_REGS) { + chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->apb_regs)) + return PTR_ERR(chip->apb_regs); + } + ++ if (flags & AXI_DMA_FLAG_HAS_RESETS) { ++ resets = devm_reset_control_array_get_exclusive(&pdev->dev); ++ if (IS_ERR(resets)) ++ return PTR_ERR(resets); ++ ++ ret = reset_control_deassert(resets); ++ if (ret) ++ return ret; ++ } ++ ++ chip->dw->hdata->use_cfg2 = !!(flags & AXI_DMA_FLAG_USE_CFG2); ++ + chip->core_clk = devm_clk_get(chip->dev, "core-clk"); + if (IS_ERR(chip->core_clk)) + return PTR_ERR(chip->core_clk); +@@ -1554,8 +1575,15 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = { + }; + + static const struct of_device_id dw_dma_of_id_table[] = { +- { .compatible = "snps,axi-dma-1.01a" }, +- { .compatible = "intel,kmb-axi-dma" }, ++ { ++ .compatible = "snps,axi-dma-1.01a" ++ }, { ++ .compatible = "intel,kmb-axi-dma", ++ .data = (void *)AXI_DMA_FLAG_HAS_APB_REGS, ++ }, { ++ .compatible = "starfive,jh7110-axi-dma", ++ .data = (void *)(AXI_DMA_FLAG_HAS_RESETS | AXI_DMA_FLAG_USE_CFG2), ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); +diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +index e9d5eb0fd594..eb267cb24f67 100644 +--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h ++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +@@ -33,6 +33,7 @@ struct dw_axi_dma_hcfg { + /* Register map for DMAX_NUM_CHANNELS <= 8 */ + bool reg_map_8_channels; + bool restrict_axi_burst_len; ++ bool use_cfg2; + }; + + struct axi_dma_chan { +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0074-dmaengine-dw-axi-dmac-Increase-polling-time-to-DMA-t.patch b/srcpkgs/linux6.3/patches/0074-dmaengine-dw-axi-dmac-Increase-polling-time-to-DMA-t.patch new file mode 100644 index 0000000000000..e03238afc216b --- /dev/null +++ b/srcpkgs/linux6.3/patches/0074-dmaengine-dw-axi-dmac-Increase-polling-time-to-DMA-t.patch @@ -0,0 +1,34 @@ +From 57625e97818d19d0ccb37ce831bf193b35a4169b Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Wed, 22 Mar 2023 17:48:19 +0800 +Subject: [PATCH 74/84] dmaengine: dw-axi-dmac: Increase polling time to DMA + transmission completion status + +The bit DMAC_CHEN[0] is automatically cleared by hardware to disable the +channel after the last AMBA transfer of the DMA transfer to the +destination has completed. Software can therefore poll this bit to +determine when this channel is free for a new DMA transfer. +This time requires at least 40 milliseconds on JH7110 SoC, otherwise an +error message 'failed to stop' will be reported. + +Signed-off-by: Walker Chen +--- + drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +index 6cfcb541d8c3..6937cc0c0b65 100644 +--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c ++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +@@ -1147,7 +1147,7 @@ static int dma_chan_terminate_all(struct dma_chan *dchan) + axi_chan_disable(chan); + + ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, +- !(val & chan_active), 1000, 10000); ++ !(val & chan_active), 1000, 50000); + if (ret == -ETIMEDOUT) + dev_warn(dchan2dev(dchan), + "%s failed to stop\n", axi_chan_name(chan)); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0075-riscv-dts-starfive-add-dma-controller-node.patch b/srcpkgs/linux6.3/patches/0075-riscv-dts-starfive-add-dma-controller-node.patch new file mode 100644 index 0000000000000..5bbfb3bd9d755 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0075-riscv-dts-starfive-add-dma-controller-node.patch @@ -0,0 +1,45 @@ +From 701c69434c54c0bb2b0fdf945b4a03023a2d7056 Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Wed, 22 Mar 2023 17:48:20 +0800 +Subject: [PATCH 75/84] riscv: dts: starfive: add dma controller node + +Add the dma controller node for the Starfive JH7110 SoC. + +Reviewed-by: Emil Renner Berthing +Signed-off-by: Walker Chen +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 6a72d33b2f5a..180665ffc6fd 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -618,6 +618,24 @@ timer@13050000 { + "ch2", "ch3"; + }; + ++ dma: dma-controller@16050000 { ++ compatible = "starfive,jh7110-axi-dma"; ++ reg = <0x0 0x16050000 0x0 0x10000>; ++ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, ++ <&stgcrg JH7110_STGCLK_DMA1P_AHB>; ++ clock-names = "core-clk", "cfgr-clk"; ++ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, ++ <&stgcrg JH7110_STGRST_DMA1P_AHB>; ++ interrupts = <73>; ++ #dma-cells = <1>; ++ dma-channels = <4>; ++ snps,dma-masters = <1>; ++ snps,data-width = <3>; ++ snps,block-size = <65536 65536 65536 65536>; ++ snps,priority = <0 1 2 3>; ++ snps,axi-max-burst-len = <16>; ++ }; ++ + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0076-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch b/srcpkgs/linux6.3/patches/0076-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch new file mode 100644 index 0000000000000..7c3858f404d3a --- /dev/null +++ b/srcpkgs/linux6.3/patches/0076-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch @@ -0,0 +1,123 @@ +From 4a9e2dca19402c545e6fea368e7773a200289ae7 Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Thu, 11 May 2023 17:15:47 +0800 +Subject: [PATCH 76/84] ASoC: dt-bindings: Add TDM controller bindings for + StarFive JH7110 + +Add bindings for TDM driver which supports multi-channel audio playback +and capture on JH7110 platform. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Walker Chen +--- + .../bindings/sound/starfive,jh7110-tdm.yaml | 98 +++++++++++++++++++ + 1 file changed, 98 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml + +diff --git a/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml b/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml +new file mode 100644 +index 000000000000..abb373fbfa26 +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml +@@ -0,0 +1,98 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/starfive,jh7110-tdm.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 TDM Controller ++ ++description: | ++ The TDM Controller is a Time Division Multiplexed audio interface ++ integrated in StarFive JH7110 SoC, allowing up to 8 channels of ++ audio over a serial interface. The TDM controller can operate both ++ in master and slave mode. ++ ++maintainers: ++ - Walker Chen ++ ++allOf: ++ - $ref: dai-common.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7110-tdm ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: TDM AHB Clock ++ - description: TDM APB Clock ++ - description: TDM Internal Clock ++ - description: TDM Clock ++ - description: Inner MCLK ++ - description: TDM External Clock ++ ++ clock-names: ++ items: ++ - const: tdm_ahb ++ - const: tdm_apb ++ - const: tdm_internal ++ - const: tdm ++ - const: mclk_inner ++ - const: tdm_ext ++ ++ resets: ++ items: ++ - description: tdm ahb reset line ++ - description: tdm apb reset line ++ - description: tdm core reset line ++ ++ dmas: ++ items: ++ - description: RX DMA Channel ++ - description: TX DMA Channel ++ ++ dma-names: ++ items: ++ - const: rx ++ - const: tx ++ ++ "#sound-dai-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - dmas ++ - dma-names ++ - "#sound-dai-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ tdm@10090000 { ++ compatible = "starfive,jh7110-tdm"; ++ reg = <0x10090000 0x1000>; ++ clocks = <&syscrg 184>, ++ <&syscrg 185>, ++ <&syscrg 186>, ++ <&syscrg 187>, ++ <&syscrg 17>, ++ <&tdm_ext>; ++ clock-names = "tdm_ahb", "tdm_apb", ++ "tdm_internal", "tdm", ++ "mclk_inner", "tdm_ext"; ++ resets = <&syscrg 105>, ++ <&syscrg 107>, ++ <&syscrg 106>; ++ dmas = <&dma 20>, <&dma 21>; ++ dma-names = "rx","tx"; ++ #sound-dai-cells = <0>; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0077-ASoC-starfive-Add-JH7110-TDM-driver.patch b/srcpkgs/linux6.3/patches/0077-ASoC-starfive-Add-JH7110-TDM-driver.patch new file mode 100644 index 0000000000000..ec7570354fb8c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0077-ASoC-starfive-Add-JH7110-TDM-driver.patch @@ -0,0 +1,799 @@ +From 33b90025b16a28b5ee7924dfb2401bfff168db7e Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Thu, 11 May 2023 17:15:48 +0800 +Subject: [PATCH 77/84] ASoC: starfive: Add JH7110 TDM driver + +Add tdm driver support for the StarFive JH7110 SoC. + +Signed-off-by: Walker Chen +--- + MAINTAINERS | 6 + + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/starfive/Kconfig | 15 + + sound/soc/starfive/Makefile | 2 + + sound/soc/starfive/jh7110_tdm.c | 554 ++++++++++++++++++++++++++++++++ + sound/soc/starfive/jh7110_tdm.h | 138 ++++++++ + 7 files changed, 717 insertions(+) + create mode 100644 sound/soc/starfive/Kconfig + create mode 100644 sound/soc/starfive/Makefile + create mode 100644 sound/soc/starfive/jh7110_tdm.c + create mode 100644 sound/soc/starfive/jh7110_tdm.h + +diff --git a/MAINTAINERS b/MAINTAINERS +index 625d259937e9..17830b3a195d 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -19951,6 +19951,12 @@ F: Documentation/devicetree/bindings/power/starfive* + F: drivers/soc/starfive/jh71xx_pmu.c + F: include/dt-bindings/power/starfive,jh7110-pmu.h + ++STARFIVE JH7110 TDM DRIVERS ++M: Walker Chen ++S: Maintained ++F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml ++F: sound/soc/starfive/jh7110-tdm.* ++ + STARFIVE SOC DRIVERS + M: Conor Dooley + S: Maintained +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 848fbae26c3b..8d1d9401ecf2 100644 +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -91,6 +91,7 @@ source "sound/soc/sh/Kconfig" + source "sound/soc/sof/Kconfig" + source "sound/soc/spear/Kconfig" + source "sound/soc/sprd/Kconfig" ++source "sound/soc/starfive/Kconfig" + source "sound/soc/sti/Kconfig" + source "sound/soc/stm/Kconfig" + source "sound/soc/sunxi/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 507eaed1d6a1..65aeb4ef4068 100644 +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -59,6 +59,7 @@ obj-$(CONFIG_SND_SOC) += sh/ + obj-$(CONFIG_SND_SOC) += sof/ + obj-$(CONFIG_SND_SOC) += spear/ + obj-$(CONFIG_SND_SOC) += sprd/ ++obj-$(CONFIG_SND_SOC) += starfive/ + obj-$(CONFIG_SND_SOC) += sti/ + obj-$(CONFIG_SND_SOC) += stm/ + obj-$(CONFIG_SND_SOC) += sunxi/ +diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig +new file mode 100644 +index 000000000000..fafb681f8c0a +--- /dev/null ++++ b/sound/soc/starfive/Kconfig +@@ -0,0 +1,15 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config SND_SOC_STARFIVE ++ tristate "Audio support for StarFive SoC" ++ depends on COMPILE_TEST || ARCH_STARFIVE ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the Starfive SoCs' Audio interfaces. You will also need to ++ select the audio interfaces to support below. ++ ++config SND_SOC_JH7110_TDM ++ tristate "JH7110 TDM device driver" ++ depends on HAVE_CLK && SND_SOC_STARFIVE ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ help ++ Say Y or M if you want to add support for StarFive TDM driver. +diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile +new file mode 100644 +index 000000000000..f7d960211d72 +--- /dev/null ++++ b/sound/soc/starfive/Makefile +@@ -0,0 +1,2 @@ ++# StarFive Platform Support ++obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o +diff --git a/sound/soc/starfive/jh7110_tdm.c b/sound/soc/starfive/jh7110_tdm.c +new file mode 100644 +index 000000000000..1f94cc210140 +--- /dev/null ++++ b/sound/soc/starfive/jh7110_tdm.c +@@ -0,0 +1,554 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * jh7110_tdm.c -- StarFive JH7110 TDM driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * Author: Walker Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "jh7110_tdm.h" ++ ++static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *tdm, u16 reg) ++{ ++ return readl_relaxed(tdm->tdm_base + reg); ++} ++ ++static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *tdm, u16 reg, u32 val) ++{ ++ writel_relaxed(val, tdm->tdm_base + reg); ++} ++ ++static void jh7110_tdm_save_context(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ tdm->saved_pcmtxcr = jh7110_tdm_readl(tdm, TDM_PCMTXCR); ++ else ++ tdm->saved_pcmrxcr = jh7110_tdm_readl(tdm, TDM_PCMRXCR); ++} ++ ++static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ u32 data; ++ ++ data = jh7110_tdm_readl(tdm, TDM_PCMGBCR); ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE); ++ ++ /* restore context */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | PCMTXCR_TXEN); ++ else ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | PCMRXCR_RXEN); ++} ++ ++static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ unsigned int val; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ val = jh7110_tdm_readl(tdm, TDM_PCMTXCR); ++ val &= ~PCMTXCR_TXEN; ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, val); ++ } else { ++ val = jh7110_tdm_readl(tdm, TDM_PCMRXCR); ++ val &= ~PCMRXCR_RXEN; ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, val); ++ } ++} ++ ++static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) ++{ ++ u32 sl, sscale, syncdiv; ++ ++ if (tdm->rx.sl >= tdm->tx.sl) ++ sl = tdm->rx.sl; ++ else ++ sl = tdm->tx.sl; ++ ++ if (tdm->rx.sscale >= tdm->tx.sscale) ++ sscale = tdm->rx.sscale; ++ else ++ sscale = tdm->tx.sscale; ++ ++ syncdiv = tdm->pcmclk / tdm->samplerate - 1; ++ ++ if ((syncdiv + 1) < (sl * sscale)) { ++ dev_err(tdm->dev, "Failed to set syncdiv!\n"); ++ return -EINVAL; ++ } ++ ++ if (tdm->syncm == TDM_SYNCM_LONG && ++ (tdm->rx.sscale <= 1 || tdm->tx.sscale <= 1)) { ++ if ((syncdiv + 1) <= sl) { ++ dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, rx.sl]\n"); ++ return -EINVAL; ++ } ++ } ++ ++ jh7110_tdm_writel(tdm, TDM_PCMDIV, syncdiv); ++ return 0; ++} ++ ++static int jh7110_tdm_config(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ u32 datarx, datatx; ++ int ret; ++ ++ ret = jh7110_tdm_syncdiv(tdm); ++ if (ret) ++ return ret; ++ ++ datarx = (tdm->rx.ifl << IFL_BIT) | ++ (tdm->rx.wl << WL_BIT) | ++ (tdm->rx.sscale << SSCALE_BIT) | ++ (tdm->rx.sl << SL_BIT) | ++ (tdm->rx.lrj << LRJ_BIT); ++ ++ datatx = (tdm->tx.ifl << IFL_BIT) | ++ (tdm->tx.wl << WL_BIT) | ++ (tdm->tx.sscale << SSCALE_BIT) | ++ (tdm->tx.sl << SL_BIT) | ++ (tdm->tx.lrj << LRJ_BIT); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx); ++ else ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, datarx); ++ ++ return 0; ++} ++ ++static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *tdm) ++{ ++ clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); ++} ++ ++static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *tdm) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(tdm->clks), tdm->clks); ++ if (ret) { ++ dev_err(tdm->dev, "Failed to enable tdm clocks\n"); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(tdm->resets); ++ if (ret) { ++ dev_err(tdm->dev, "Failed to deassert tdm resets\n"); ++ goto dis_tdm_clk; ++ } ++ ++ /* select tdm_ext clock as the clock source for tdm */ ++ ret = clk_set_parent(tdm->clks[5].clk, tdm->clks[4].clk); ++ if (ret) { ++ dev_err(tdm->dev, "Can't set clock source for clk_tdm: %d\n", ret); ++ goto dis_tdm_clk; ++ } ++ return 0; ++ ++dis_tdm_clk: ++ clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); ++ ++ return ret; ++} ++ ++static int jh7110_tdm_runtime_suspend(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ jh7110_tdm_clk_disable(tdm); ++ return 0; ++} ++ ++static int jh7110_tdm_runtime_resume(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ return jh7110_tdm_clk_enable(tdm); ++} ++ ++static int __maybe_unused jh7110_tdm_system_suspend(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ /* save context */ ++ tdm->saved_pcmgbcr = jh7110_tdm_readl(tdm, TDM_PCMGBCR); ++ tdm->saved_pcmdiv = jh7110_tdm_readl(tdm, TDM_PCMDIV); ++ ++ return pm_runtime_force_suspend(dev); ++} ++ ++static int __maybe_unused jh7110_tdm_system_resume(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ /* restore context */ ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, tdm->saved_pcmgbcr); ++ jh7110_tdm_writel(tdm, TDM_PCMDIV, tdm->saved_pcmdiv); ++ ++ return pm_runtime_force_resume(dev); ++} ++ ++static const struct snd_soc_component_driver jh7110_tdm_component = { ++ .name = "jh7110-tdm", ++}; ++ ++static int jh7110_tdm_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *cpu_dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); ++ struct snd_soc_dai_link *dai_link = rtd->dai_link; ++ ++ dai_link->stop_dma_first = 1; ++ ++ return 0; ++} ++ ++static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ int chan_wl, chan_sl, chan_nr; ++ unsigned int data_width; ++ unsigned int dma_bus_width; ++ struct snd_dmaengine_dai_dma_data *dma_data = NULL; ++ int ret = 0; ++ ++ data_width = params_width(params); ++ ++ tdm->samplerate = params_rate(params); ++ tdm->pcmclk = params_channels(params) * tdm->samplerate * data_width; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ chan_wl = TDM_16BIT_WORD_LEN; ++ chan_sl = TDM_16BIT_SLOT_LEN; ++ dma_bus_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ ++ case SNDRV_PCM_FORMAT_S32_LE: ++ chan_wl = TDM_32BIT_WORD_LEN; ++ chan_sl = TDM_32BIT_SLOT_LEN; ++ dma_bus_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ ++ default: ++ dev_err(tdm->dev, "tdm: unsupported PCM fmt"); ++ return -EINVAL; ++ } ++ ++ chan_nr = params_channels(params); ++ switch (chan_nr) { ++ case 1: ++ case 2: ++ case 4: ++ case 6: ++ case 8: ++ break; ++ default: ++ dev_err(tdm->dev, "channel not supported\n"); ++ return -EINVAL; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ tdm->tx.wl = chan_wl; ++ tdm->tx.sl = chan_sl; ++ tdm->tx.sscale = chan_nr; ++ tdm->play_dma_data.addr_width = dma_bus_width; ++ dma_data = &tdm->play_dma_data; ++ } else { ++ tdm->rx.wl = chan_wl; ++ tdm->rx.sl = chan_sl; ++ tdm->rx.sscale = chan_nr; ++ tdm->capture_dma_data.addr_width = dma_bus_width; ++ dma_data = &tdm->capture_dma_data; ++ } ++ ++ snd_soc_dai_set_dma_data(dai, substream, dma_data); ++ ++ ret = jh7110_tdm_config(tdm, substream); ++ if (ret) ++ return ret; ++ ++ jh7110_tdm_save_context(tdm, substream); ++ return 0; ++} ++ ++static int jh7110_tdm_trigger(struct snd_pcm_substream *substream, ++ int cmd, struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ jh7110_tdm_start(tdm, substream); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ jh7110_tdm_stop(tdm, substream); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ return ret; ++} ++ ++static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(cpu_dai); ++ unsigned int gbcr; ++ int ret = 0; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { ++ case SND_SOC_DAIFMT_BP_FP: ++ /* cpu is master */ ++ tdm->ms_mode = TDM_AS_MASTER; ++ break; ++ case SND_SOC_DAIFMT_BC_FC: ++ /* codec is master */ ++ tdm->ms_mode = TDM_AS_SLAVE; ++ break; ++ case SND_SOC_DAIFMT_BC_FP: ++ case SND_SOC_DAIFMT_BP_FC: ++ ret = -EINVAL; ++ break; ++ default: ++ dev_dbg(tdm->dev, "dwc : Invalid clock provider format\n"); ++ ret = -EINVAL; ++ break; ++ } ++ ++ gbcr = (tdm->clkpolity << CLKPOL_BIT) | ++ (tdm->elm << ELM_BIT) | ++ (tdm->syncm << SYNCM_BIT) | ++ (tdm->ms_mode << MS_BIT); ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, gbcr); ++ ++ return ret; ++} ++ ++static const struct snd_soc_dai_ops jh7110_tdm_dai_ops = { ++ .startup = jh7110_tdm_startup, ++ .hw_params = jh7110_tdm_hw_params, ++ .trigger = jh7110_tdm_trigger, ++ .set_fmt = jh7110_tdm_set_dai_fmt, ++}; ++ ++static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ ++ snd_soc_dai_init_dma_data(dai, &tdm->play_dma_data, &tdm->capture_dma_data); ++ snd_soc_dai_set_drvdata(dai, tdm); ++ return 0; ++} ++ ++#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000 ++ ++#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ ++static struct snd_soc_dai_driver jh7110_tdm_dai = { ++ .name = "sf_tdm", ++ .id = 0, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = JH7110_TDM_RATES, ++ .formats = JH7110_TDM_FORMATS, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = JH7110_TDM_RATES, ++ .formats = JH7110_TDM_FORMATS, ++ }, ++ .ops = &jh7110_tdm_dai_ops, ++ .probe = jh7110_tdm_dai_probe, ++ .symmetric_rate = 1, ++}; ++ ++static const struct snd_pcm_hardware jh7110_pcm_hardware = { ++ .info = (SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | ++ SNDRV_PCM_INFO_PAUSE | ++ SNDRV_PCM_INFO_RESUME | ++ SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER), ++ .buffer_bytes_max = 192512, ++ .period_bytes_min = 4096, ++ .period_bytes_max = 32768, ++ .periods_min = 1, ++ .periods_max = 48, ++ .fifo_size = 16, ++}; ++ ++static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = { ++ .pcm_hardware = &jh7110_pcm_hardware, ++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, ++ .prealloc_buffer_size = 192512, ++}; ++ ++static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm) ++{ ++ tdm->clkpolity = TDM_TX_RASING_RX_FALLING; ++ tdm->elm = TDM_ELM_LATE; ++ tdm->syncm = TDM_SYNCM_SHORT; ++ ++ tdm->rx.ifl = TDM_FIFO_HALF; ++ tdm->tx.ifl = TDM_FIFO_HALF; ++ tdm->rx.wl = TDM_16BIT_WORD_LEN; ++ tdm->tx.wl = TDM_16BIT_WORD_LEN; ++ tdm->rx.sscale = 2; ++ tdm->tx.sscale = 2; ++ tdm->rx.lrj = TDM_LEFT_JUSTIFT; ++ tdm->tx.lrj = TDM_LEFT_JUSTIFT; ++ ++ tdm->play_dma_data.addr = JH7110_TDM_FIFO; ++ tdm->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ tdm->play_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; ++ tdm->play_dma_data.maxburst = 16; ++ ++ tdm->capture_dma_data.addr = JH7110_TDM_FIFO; ++ tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ tdm->capture_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; ++ tdm->capture_dma_data.maxburst = 8; ++} ++ ++static int jh7110_tdm_clk_reset_init(struct platform_device *pdev, ++ struct jh7110_tdm_dev *tdm) ++{ ++ int ret; ++ ++ tdm->clks[0].id = "mclk_inner"; ++ tdm->clks[1].id = "tdm_ahb"; ++ tdm->clks[2].id = "tdm_apb"; ++ tdm->clks[3].id = "tdm_internal"; ++ tdm->clks[4].id = "tdm_ext"; ++ tdm->clks[5].id = "tdm"; ++ ++ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(tdm->clks), tdm->clks); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to get tdm clocks\n"); ++ return ret; ++ } ++ ++ tdm->resets = devm_reset_control_array_get_exclusive(&pdev->dev); ++ if (IS_ERR(tdm->resets)) { ++ ret = PTR_ERR(tdm->resets); ++ dev_err(&pdev->dev, "Failed to get tdm resets"); ++ return ret; ++ } ++ ++ return jh7110_tdm_clk_enable(tdm); ++} ++ ++static int jh7110_tdm_probe(struct platform_device *pdev) ++{ ++ struct jh7110_tdm_dev *tdm; ++ int ret; ++ ++ tdm = devm_kzalloc(&pdev->dev, sizeof(*tdm), GFP_KERNEL); ++ if (!tdm) ++ return -ENOMEM; ++ ++ tdm->tdm_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(tdm->tdm_base)) ++ return PTR_ERR(tdm->tdm_base); ++ ++ tdm->dev = &pdev->dev; ++ ++ ret = jh7110_tdm_clk_reset_init(pdev, tdm); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable audio-tdm clock\n"); ++ return ret; ++ } ++ ++ jh7110_tdm_init_params(tdm); ++ ++ dev_set_drvdata(&pdev->dev, tdm); ++ ret = devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component, ++ &jh7110_tdm_dai, 1); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to register dai\n"); ++ return ret; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, ++ &jh7110_dmaengine_pcm_config, ++ SND_DMAENGINE_PCM_FLAG_COMPAT); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register pcm: %d\n", ret); ++ return ret; ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++#ifdef CONFIG_PM ++ jh7110_tdm_clk_disable(tdm); ++#endif ++ ++ return 0; ++} ++ ++static int jh7110_tdm_dev_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id jh7110_tdm_of_match[] = { ++ { .compatible = "starfive,jh7110-tdm", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match); ++ ++static const struct dev_pm_ops jh7110_tdm_pm_ops = { ++ SET_RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend, ++ jh7110_tdm_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(jh7110_tdm_system_suspend, ++ jh7110_tdm_system_resume) ++}; ++ ++static struct platform_driver jh7110_tdm_driver = { ++ .driver = { ++ .name = "jh7110-tdm", ++ .of_match_table = jh7110_tdm_of_match, ++ .pm = &jh7110_tdm_pm_ops, ++ }, ++ .probe = jh7110_tdm_probe, ++ .remove = jh7110_tdm_dev_remove, ++}; ++module_platform_driver(jh7110_tdm_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 TDM ASoC Driver"); ++MODULE_AUTHOR("Walker Chen "); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/starfive/jh7110_tdm.h b/sound/soc/starfive/jh7110_tdm.h +new file mode 100644 +index 000000000000..0b7e6d6543c5 +--- /dev/null ++++ b/sound/soc/starfive/jh7110_tdm.h +@@ -0,0 +1,138 @@ ++/* SPDX-License-Identifier: GPL-2.0 ++ * ++ * TDM driver for the StarFive JH7110 SoC ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * Author: Walker Chen ++ */ ++ ++#ifndef __SND_SOC_STARFIVE_TDM_H ++#define __SND_SOC_STARFIVE_TDM_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TDM_PCMGBCR 0x00 ++ #define PCMGBCR_MASK 0x1e ++ #define PCMGBCR_ENABLE BIT(0) ++ #define PCMGBCR_TRITXEN BIT(4) ++ #define CLKPOL_BIT 5 ++ #define TRITXEN_BIT 4 ++ #define ELM_BIT 3 ++ #define SYNCM_BIT 2 ++ #define MS_BIT 1 ++#define TDM_PCMTXCR 0x04 ++ #define PCMTXCR_TXEN BIT(0) ++ #define IFL_BIT 11 ++ #define WL_BIT 8 ++ #define SSCALE_BIT 4 ++ #define SL_BIT 2 ++ #define LRJ_BIT 1 ++#define TDM_PCMRXCR 0x08 ++ #define PCMRXCR_RXEN BIT(0) ++ #define PCMRXCR_RXSL_MASK 0xc ++ #define PCMRXCR_RXSL_16BIT 0x4 ++ #define PCMRXCR_RXSL_32BIT 0x8 ++ #define PCMRXCR_SCALE_MASK 0xf0 ++ #define PCMRXCR_SCALE_1CH 0x10 ++#define TDM_PCMDIV 0x0c ++ ++#define JH7110_TDM_FIFO 0x170c0000 ++#define JH7110_TDM_FIFO_DEPTH 32 ++ ++enum TDM_MASTER_SLAVE_MODE { ++ TDM_AS_MASTER = 0, ++ TDM_AS_SLAVE, ++}; ++ ++enum TDM_CLKPOL { ++ /* tx raising and rx falling */ ++ TDM_TX_RASING_RX_FALLING = 0, ++ /* tx falling and rx raising */ ++ TDM_TX_FALLING_RX_RASING, ++}; ++ ++enum TDM_ELM { ++ /* only work while SYNCM=0 */ ++ TDM_ELM_LATE = 0, ++ TDM_ELM_EARLY, ++}; ++ ++enum TDM_SYNCM { ++ /* short frame sync */ ++ TDM_SYNCM_SHORT = 0, ++ /* long frame sync */ ++ TDM_SYNCM_LONG, ++}; ++ ++enum TDM_IFL { ++ /* FIFO to send or received : half-1/2, Quarter-1/4 */ ++ TDM_FIFO_HALF = 0, ++ TDM_FIFO_QUARTER, ++}; ++ ++enum TDM_WL { ++ /* send or received word length */ ++ TDM_8BIT_WORD_LEN = 0, ++ TDM_16BIT_WORD_LEN, ++ TDM_20BIT_WORD_LEN, ++ TDM_24BIT_WORD_LEN, ++ TDM_32BIT_WORD_LEN, ++}; ++ ++enum TDM_SL { ++ /* send or received slot length */ ++ TDM_8BIT_SLOT_LEN = 0, ++ TDM_16BIT_SLOT_LEN, ++ TDM_32BIT_SLOT_LEN, ++}; ++ ++enum TDM_LRJ { ++ /* left-justify or right-justify */ ++ TDM_RIGHT_JUSTIFY = 0, ++ TDM_LEFT_JUSTIFT, ++}; ++ ++struct tdm_chan_cfg { ++ enum TDM_IFL ifl; ++ enum TDM_WL wl; ++ unsigned char sscale; ++ enum TDM_SL sl; ++ enum TDM_LRJ lrj; ++ unsigned char enable; ++}; ++ ++struct jh7110_tdm_dev { ++ void __iomem *tdm_base; ++ struct device *dev; ++ struct clk_bulk_data clks[6]; ++ struct reset_control *resets; ++ ++ enum TDM_CLKPOL clkpolity; ++ enum TDM_ELM elm; ++ enum TDM_SYNCM syncm; ++ enum TDM_MASTER_SLAVE_MODE ms_mode; ++ ++ struct tdm_chan_cfg tx; ++ struct tdm_chan_cfg rx; ++ ++ u16 syncdiv; ++ u32 samplerate; ++ u32 pcmclk; ++ ++ /* data related to DMA transfers b/w tdm and DMAC */ ++ struct snd_dmaengine_dai_dma_data play_dma_data; ++ struct snd_dmaengine_dai_dma_data capture_dma_data; ++ u32 saved_pcmgbcr; ++ u32 saved_pcmtxcr; ++ u32 saved_pcmrxcr; ++ u32 saved_pcmdiv; ++}; ++ ++#endif /* __SND_SOC_STARFIVE_TDM_H */ +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0078-riscv-dts-starfive-add-the-node-and-pins-configurati.patch b/srcpkgs/linux6.3/patches/0078-riscv-dts-starfive-add-the-node-and-pins-configurati.patch new file mode 100644 index 0000000000000..fdcd179fcb75f --- /dev/null +++ b/srcpkgs/linux6.3/patches/0078-riscv-dts-starfive-add-the-node-and-pins-configurati.patch @@ -0,0 +1,105 @@ +From 27a554efe5dbf3c7d1d7a895b3787ecab253a426 Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Thu, 11 May 2023 17:15:49 +0800 +Subject: [PATCH 78/84] riscv: dts: starfive: add the node and pins + configuration for tdm + +Add the tdm controller node and pins configuration of tdm for the +StarFive JH7110 SoC. + +Signed-off-by: Walker Chen +--- + .../jh7110-starfive-visionfive-2.dtsi | 40 +++++++++++++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 21 ++++++++++ + 2 files changed, 61 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 31454e15acfc..4ccd20303ab5 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -228,6 +228,40 @@ GPOEN_DISABLE, + slew-rate = <0>; + }; + }; ++ ++ tdm0_pins: tdm0-pins { ++ tdm0-pins-tx { ++ pinmux = ; ++ bias-pull-up; ++ drive-strength = <2>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ tdm0-pins-rx { ++ pinmux = ; ++ input-enable; ++ }; ++ ++ tdm0-pins-sync { ++ pinmux = ; ++ input-enable; ++ }; ++ ++ tdm0-pins-pcmclk { ++ pinmux = ; ++ input-enable; ++ }; ++ }; + }; + + &uart0 { +@@ -258,3 +292,9 @@ &usb0 { + dr_mode = "peripheral"; + status = "okay"; + }; ++ ++&tdm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&tdm0_pins>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 180665ffc6fd..d545684958c4 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -399,6 +399,27 @@ i2c2: i2c@10050000 { + status = "disabled"; + }; + ++ tdm: tdm@10090000 { ++ compatible = "starfive,jh7110-tdm"; ++ reg = <0x0 0x10090000 0x0 0x1000>; ++ clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, ++ <&syscrg JH7110_SYSCLK_TDM_APB>, ++ <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, ++ <&syscrg JH7110_SYSCLK_TDM_TDM>, ++ <&syscrg JH7110_SYSCLK_MCLK_INNER>, ++ <&tdm_ext>; ++ clock-names = "tdm_ahb", "tdm_apb", ++ "tdm_internal", "tdm", ++ "mclk_inner", "tdm_ext"; ++ resets = <&syscrg JH7110_SYSRST_TDM_AHB>, ++ <&syscrg JH7110_SYSRST_TDM_APB>, ++ <&syscrg JH7110_SYSRST_TDM_CORE>; ++ dmas = <&dma 20>, <&dma 21>; ++ dma-names = "rx","tx"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + reg = <0x0 0x10100000 0x0 0x10000>, +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0079-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch b/srcpkgs/linux6.3/patches/0079-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch new file mode 100644 index 0000000000000..a6b87d395d5dc --- /dev/null +++ b/srcpkgs/linux6.3/patches/0079-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch @@ -0,0 +1,186 @@ +From 99facf687e4bedf2eba4defadf85d41f6aead9cf Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 6 Apr 2023 19:11:40 +0800 +Subject: [PATCH 79/84] dt-binding: pci: add JH7110 PCIe dt-binding documents. + +Add PCIe controller driver dt-binding documents +for StarFive JH7110 SoC platform. + +Signed-off-by: Minda Chen +--- + .../bindings/pci/starfive,jh7110-pcie.yaml | 163 ++++++++++++++++++ + 1 file changed, 163 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +new file mode 100644 +index 000000000000..fa4829766195 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +@@ -0,0 +1,163 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe 2.0 host controller ++ ++maintainers: ++ - Minda Chen ++ ++allOf: ++ - $ref: /schemas/pci/pci-bus.yaml# ++ - $ref: /schemas/interrupt-controller/msi-controller.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie ++ ++ reg: ++ maxItems: 2 ++ ++ reg-names: ++ items: ++ - const: reg ++ - const: config ++ ++ msi-parent: true ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: noc ++ - const: tl ++ - const: axi_mst0 ++ - const: apb ++ ++ resets: ++ items: ++ - description: AXI MST0 reset ++ - description: AXI SLAVE reset ++ - description: AXI SLAVE0 reset ++ - description: PCIE BRIDGE reset ++ - description: PCIE CORE reset ++ - description: PCIE APB reset ++ ++ reset-names: ++ items: ++ - const: mst0 ++ - const: slv0 ++ - const: slv ++ - const: brg ++ - const: core ++ - const: apb ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset ++ for PCIe. ++ ++ pwren-gpios: ++ description: Should specify the GPIO for controlling the PCI bus device power on. ++ maxItems: 1 ++ ++ reset-gpios: ++ maxItems: 1 ++ ++ phys: ++ maxItems: 1 ++ ++ interrupt-controller: ++ type: object ++ properties: ++ '#address-cells': ++ const: 0 ++ ++ '#interrupt-cells': ++ const: 1 ++ ++ interrupt-controller: true ++ ++ required: ++ - '#address-cells' ++ - '#interrupt-cells' ++ - interrupt-controller ++ ++ additionalProperties: false ++ ++required: ++ - reg ++ - reg-names ++ - "#interrupt-cells" ++ - interrupts ++ - interrupt-map-mask ++ - interrupt-map ++ - clocks ++ - clock-names ++ - resets ++ - msi-controller ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ bus { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie0: pcie@2B000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2B000000 0x0 0x1000000>, ++ <0x9 0x40000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ interrupt-parent = <&plic>; ++ interrupts = <56>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-parent = <&pcie0>; ++ msi-controller; ++ clocks = <&syscrg 86>, ++ <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 9>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg 11>, ++ <&stgcrg 12>, ++ <&stgcrg 13>, ++ <&stgcrg 14>, ++ <&stgcrg 15>, ++ <&stgcrg 16>; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0080-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch b/srcpkgs/linux6.3/patches/0080-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch new file mode 100644 index 0000000000000..95de51f671d3c --- /dev/null +++ b/srcpkgs/linux6.3/patches/0080-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch @@ -0,0 +1,1014 @@ +From 41d0576dd7a7b90c56d3707b7b4c0376d031133b Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 6 Apr 2023 19:11:41 +0800 +Subject: [PATCH 80/84] pcie: starfive: add StarFive JH7110 PCIe driver. + +Add PCIe controller driver for StarFive JH7110 +SoC platform. The PCIe controller is PCIe 2.0, single lane. + +Signed-off-by: Minda Chen +--- + drivers/pci/controller/Kconfig | 8 + + drivers/pci/controller/Makefile | 1 + + drivers/pci/controller/pcie-starfive.c | 958 +++++++++++++++++++++++++ + 3 files changed, 967 insertions(+) + create mode 100644 drivers/pci/controller/pcie-starfive.c + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index 42654035654a..3b39080018a5 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -342,6 +342,14 @@ config PCIE_MT7621 + help + This selects a driver for the MediaTek MT7621 PCIe Controller. + ++config PCIE_STARFIVE ++ tristate "StarFive JH7110 PCIe controller" ++ depends on PCI_MSI && OF ++ select PCI_MSI_IRQ_DOMAIN ++ help ++ Say 'Y' here if you want kernel to support the StarFive JH7110 ++ PCIe Host driver. ++ + source "drivers/pci/controller/dwc/Kconfig" + source "drivers/pci/controller/mobiveil/Kconfig" + source "drivers/pci/controller/cadence/Kconfig" +diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile +index 37c8663de7fe..23708222db8a 100644 +--- a/drivers/pci/controller/Makefile ++++ b/drivers/pci/controller/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o + obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o + obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o + obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o ++obj-$(CONFIG_PCIE_STARFIVE) += pcie-starfive.o + + # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW + obj-y += dwc/ +diff --git a/drivers/pci/controller/pcie-starfive.c b/drivers/pci/controller/pcie-starfive.c +new file mode 100644 +index 000000000000..e1dc8ecc769a +--- /dev/null ++++ b/drivers/pci/controller/pcie-starfive.c +@@ -0,0 +1,958 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * PCIe host controller driver for Starfive JH7110 Soc. ++ * ++ * Based on pcie-altera.c, pcie-altera-msi.c. ++ * ++ * Copyright (C) StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../pci.h" ++ ++#define IMASK_LOCAL 0x180 ++#define ISTATUS_LOCAL 0x184 ++#define IMSI_ADDR 0x190 ++#define ISTATUS_MSI 0x194 ++#define GEN_SETTINGS 0x80 ++#define PCIE_PCI_IDS 0x9C ++#define PCIE_WINROM 0xFC ++#define PMSG_SUPPORT_RX 0x3F0 ++ ++#define PCI_MISC 0xB4 ++ ++#define RP_ENABLE 1 ++ ++#define IDS_CLASS_CODE_SHIFT 16 ++ ++#define DATA_LINK_ACTIVE BIT(5) ++#define PREF_MEM_WIN_64_SUPPORT BIT(3) ++#define PMSG_LTR_SUPPORT BIT(2) ++#define LINK_SPEED_GEN2 BIT(12) ++#define PHY_FUNCTION_DIS BIT(15) ++#define PCIE_FUNC_NUM 4 ++#define PHY_FUNC_SHIFT 9 ++ ++#define XR3PCI_ATR_AXI4_SLV0 0x800 ++#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 ++#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 ++#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 ++#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc ++#define XR3PCI_ATR_TRSL_PARAM 0x10 ++#define XR3PCI_ATR_TABLE_OFFSET 0x20 ++#define XR3PCI_ATR_MAX_TABLE_NUM 8 ++ ++#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 ++#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) ++#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) ++#define XR3PCI_ECAM_SIZE BIT(28) ++#define XR3PCI_ATR_TRSL_DIR BIT(22) ++/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ ++#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0 ++#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1 ++ ++#define INT_AXI_POST_ERROR BIT(16) ++#define INT_AXI_FETCH_ERROR BIT(17) ++#define INT_AXI_DISCARD_ERROR BIT(18) ++#define INT_PCIE_POST_ERROR BIT(20) ++#define INT_PCIE_FETCH_ERROR BIT(21) ++#define INT_PCIE_DISCARD_ERROR BIT(22) ++#define INT_ERRORS (INT_AXI_POST_ERROR | INT_AXI_FETCH_ERROR | \ ++ INT_AXI_DISCARD_ERROR | INT_PCIE_POST_ERROR | \ ++ INT_PCIE_FETCH_ERROR | INT_PCIE_DISCARD_ERROR) ++ ++#define INTA_OFFSET 24 ++#define INTA BIT(24) ++#define INTB BIT(25) ++#define INTC BIT(26) ++#define INTD BIT(27) ++#define INT_MSI BIT(28) ++#define INT_INTX_MASK (INTA | INTB | INTC | INTD) ++#define INT_MASK (INT_INTX_MASK | INT_MSI | INT_ERRORS) ++ ++#define INT_PCI_MSI_NR 32 ++ ++/* system control */ ++#define STG_SYSCON_K_RP_NEP BIT(8) ++#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) ++#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 ++#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) ++#define STG_SYSCON_CLKREQ BIT(22) ++#define STG_SYSCON_CKREF_SRC_SHIFT 18 ++#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) ++ ++/* MSI information */ ++struct jh7110_pcie_msi { ++ DECLARE_BITMAP(used, INT_PCI_MSI_NR); ++ struct irq_domain *msi_domain; ++ struct irq_domain *inner_domain; ++ /* Protect bitmap variable */ ++ struct mutex lock; ++}; ++ ++struct starfive_jh7110_pcie { ++ struct platform_device *pdev; ++ void __iomem *reg_base; ++ void __iomem *config_base; ++ phys_addr_t config_phyaddr; ++ struct regmap *reg_syscon; ++ struct phy *phy; ++ u32 stg_arfun; ++ u32 stg_awfun; ++ u32 stg_rp_nep; ++ u32 stg_lnksta; ++ int irq; ++ struct irq_domain *legacy_irq_domain; ++ struct pci_host_bridge *bridge; ++ struct jh7110_pcie_msi msi; ++ struct reset_control *resets; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ int atr_table_num; ++ struct gpio_desc *power_gpio; ++ struct gpio_desc *reset_gpio; ++}; ++ ++/* ++ * StarFive PCIe port uses BAR0-BAR1 of RC's configuration space as ++ * the translation from PCI bus to native BUS. Entire DDR region ++ * is mapped into PCIe space using these registers, so it can be ++ * reached by DMA from EP devices. The BAR0/1 of bridge should be ++ * hidden during enumeration to avoid the sizing and resource allocation ++ * by PCIe core. ++ */ ++static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, ++ int offset) ++{ ++ if (pci_is_root_bus(bus) && (devfn == 0) ++ && ((offset == PCI_BASE_ADDRESS_0) ++ || (offset == PCI_BASE_ADDRESS_1))) ++ return true; ++ ++ return false; ++} ++ ++void __iomem *starfive_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ struct starfive_jh7110_pcie *pcie = bus->sysdata; ++ ++ return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); ++} ++ ++int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ return pci_generic_config_write(bus, devfn, where, size, value); ++} ++ ++static void starfive_pcie_handle_msi_irq(struct starfive_jh7110_pcie *pcie) ++{ ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 bit; ++ u32 virq; ++ unsigned long status = readl(pcie->reg_base + ISTATUS_MSI); ++ ++ for_each_set_bit(bit, &status, INT_PCI_MSI_NR) { ++ /* Clear interrupts */ ++ writel(1 << bit, pcie->reg_base + ISTATUS_MSI); ++ virq = irq_find_mapping(msi->inner_domain, bit); ++ if (virq) { ++ if (test_bit(bit, msi->used)) ++ generic_handle_irq(virq); ++ else ++ dev_err(&pcie->pdev->dev, ++ "Unhandled MSI, MSI%d virq %d\n", bit, ++ virq); ++ } else ++ dev_err(&pcie->pdev->dev, "Unexpected MSI, MSI%d\n", ++ bit); ++ } ++ writel(INT_MSI, pcie->reg_base + ISTATUS_LOCAL); ++} ++ ++static void starfive_pcie_handle_intx_irq(struct starfive_jh7110_pcie *pcie, ++ unsigned long status) ++{ ++ u32 bit; ++ u32 virq; ++ ++ status >>= INTA_OFFSET; ++ ++ for_each_set_bit(bit, &status, PCI_NUM_INTX) { ++ /* Clear interrupts */ ++ writel(1 << (bit + INTA_OFFSET), pcie->reg_base + ISTATUS_LOCAL); ++ ++ virq = irq_find_mapping(pcie->legacy_irq_domain, bit); ++ if (virq) ++ generic_handle_irq(virq); ++ else ++ dev_err(&pcie->pdev->dev, ++ "unexpected IRQ, INT%d\n", bit); ++ } ++} ++ ++static void starfive_pcie_handle_errors_irq(struct starfive_jh7110_pcie *pcie, u32 status) ++{ ++ if (status & INT_AXI_POST_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI post error\n"); ++ if (status & INT_AXI_FETCH_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI fetch error\n"); ++ if (status & INT_AXI_DISCARD_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI discard error\n"); ++ if (status & INT_PCIE_POST_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe post error\n"); ++ if (status & INT_PCIE_FETCH_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe fetch error\n"); ++ if (status & INT_PCIE_DISCARD_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe discard error\n"); ++ ++ writel(INT_ERRORS, pcie->reg_base + ISTATUS_LOCAL); ++} ++ ++static void starfive_pcie_isr(struct irq_desc *desc) ++{ ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct starfive_jh7110_pcie *pcie; ++ u32 status; ++ ++ chained_irq_enter(chip, desc); ++ pcie = irq_desc_get_handler_data(desc); ++ ++ status = readl(pcie->reg_base + ISTATUS_LOCAL); ++ while ((status = (readl(pcie->reg_base + ISTATUS_LOCAL) & INT_MASK))) { ++ if (status & INT_INTX_MASK) ++ starfive_pcie_handle_intx_irq(pcie, status); ++ ++ if (status & INT_MSI) ++ starfive_pcie_handle_msi_irq(pcie); ++ ++ if (status & INT_ERRORS) ++ starfive_pcie_handle_errors_irq(pcie, status); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++#ifdef CONFIG_PCI_MSI ++static struct irq_chip starfive_pcie_msi_irq_chip = { ++ .name = "StarFive PCIe MSI", ++ .irq_mask = pci_msi_mask_irq, ++ .irq_unmask = pci_msi_unmask_irq, ++}; ++ ++static struct msi_domain_info starfive_pcie_msi_domain_info = { ++ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | ++ MSI_FLAG_PCI_MSIX), ++ .chip = &starfive_pcie_msi_irq_chip, ++}; ++#endif ++ ++static void starfive_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) ++{ ++ struct starfive_jh7110_pcie *pcie = irq_data_get_irq_chip_data(data); ++ phys_addr_t msi_addr = readl(pcie->reg_base + IMSI_ADDR); ++ ++ msg->address_lo = lower_32_bits(msi_addr); ++ msg->address_hi = upper_32_bits(msi_addr); ++ msg->data = data->hwirq; ++ ++ dev_info(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", ++ (int)data->hwirq, msg->address_hi, msg->address_lo); ++} ++ ++static int starfive_pcie_msi_set_affinity(struct irq_data *irq_data, ++ const struct cpumask *mask, bool force) ++{ ++ return -EINVAL; ++} ++ ++static struct irq_chip starfive_irq_chip = { ++ .name = "StarFive MSI", ++ .irq_compose_msi_msg = starfive_pcie_compose_msi_msg, ++ .irq_set_affinity = starfive_pcie_msi_set_affinity, ++}; ++ ++static int starfive_pcie_msi_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *args) ++{ ++ struct starfive_jh7110_pcie *pcie = domain->host_data; ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ int bit; ++ ++ WARN_ON(nr_irqs != 1); ++ mutex_lock(&msi->lock); ++ ++ bit = find_first_zero_bit(msi->used, INT_PCI_MSI_NR); ++ if (bit >= INT_PCI_MSI_NR) { ++ mutex_unlock(&msi->lock); ++ return -ENOSPC; ++ } ++ ++ set_bit(bit, msi->used); ++ ++ irq_domain_set_info(domain, virq, bit, &starfive_irq_chip, ++ domain->host_data, handle_simple_irq, ++ NULL, NULL); ++ mutex_unlock(&msi->lock); ++ ++ return 0; ++} ++ ++static void starfive_pcie_msi_free(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs) ++{ ++ struct irq_data *data = irq_domain_get_irq_data(domain, virq); ++ struct starfive_jh7110_pcie *pcie = irq_data_get_irq_chip_data(data); ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ ++ mutex_lock(&msi->lock); ++ ++ if (!test_bit(data->hwirq, msi->used)) ++ dev_err(&pcie->pdev->dev, "Trying to free unused MSI#%lu\n", ++ data->hwirq); ++ else ++ __clear_bit(data->hwirq, msi->used); ++ ++ writel(0xffffffff, pcie->reg_base + ISTATUS_MSI); ++ mutex_unlock(&msi->lock); ++} ++ ++static const struct irq_domain_ops dev_msi_domain_ops = { ++ .alloc = starfive_pcie_msi_alloc, ++ .free = starfive_pcie_msi_free, ++}; ++ ++static void starfive_pcie_msi_free_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++#ifdef CONFIG_PCI_MSI ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 irq; ++ int i; ++ ++ for (i = 0; i < INT_PCI_MSI_NR; i++) { ++ irq = irq_find_mapping(msi->inner_domain, i); ++ if (irq > 0) ++ irq_dispose_mapping(irq); ++ } ++ ++ if (msi->msi_domain) ++ irq_domain_remove(msi->msi_domain); ++ ++ if (msi->inner_domain) ++ irq_domain_remove(msi->inner_domain); ++#endif ++} ++ ++static void starfive_pcie_free_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++ int i; ++ u32 irq; ++ ++ /* Disable all interrupts */ ++ writel(0, pcie->reg_base + IMASK_LOCAL); ++ ++ if (pcie->legacy_irq_domain) { ++ for (i = 0; i < PCI_NUM_INTX; i++) { ++ irq = irq_find_mapping(pcie->legacy_irq_domain, i); ++ if (irq > 0) ++ irq_dispose_mapping(irq); ++ } ++ irq_domain_remove(pcie->legacy_irq_domain); ++ } ++ ++ if (pci_msi_enabled()) ++ starfive_pcie_msi_free_irq_domain(pcie); ++ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); ++} ++ ++static int starfive_pcie_init_msi_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++#ifdef CONFIG_PCI_MSI ++ struct fwnode_handle *fwn = of_node_to_fwnode(pcie->pdev->dev.of_node); ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ ++ msi->inner_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, ++ &dev_msi_domain_ops, pcie); ++ if (!msi->inner_domain) { ++ dev_err(&pcie->pdev->dev, "Failed to create dev IRQ domain\n"); ++ return -ENOMEM; ++ } ++ msi->msi_domain = pci_msi_create_irq_domain(fwn, &starfive_pcie_msi_domain_info, ++ msi->inner_domain); ++ if (!msi->msi_domain) { ++ dev_err(&pcie->pdev->dev, "Failed to create msi IRQ domain\n"); ++ irq_domain_remove(msi->inner_domain); ++ return -ENOMEM; ++ } ++#endif ++ return 0; ++} ++ ++static int starfive_pcie_enable_msi(struct starfive_jh7110_pcie *pcie, struct pci_bus *bus) ++{ ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 reg; ++ ++ mutex_init(&msi->lock); ++ ++ /* Enable MSI */ ++ reg = readl(pcie->reg_base + IMASK_LOCAL); ++ reg |= INT_MSI; ++ writel(reg, pcie->reg_base + IMASK_LOCAL); ++ return 0; ++} ++ ++static int starfive_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops intx_domain_ops = { ++ .map = starfive_pcie_intx_map, ++ .xlate = pci_irqd_intx_xlate, ++}; ++ ++static int starfive_pcie_init_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ struct device_node *node = dev->of_node; ++ int ret; ++ ++ if (pci_msi_enabled()) { ++ ret = starfive_pcie_init_msi_irq_domain(pcie); ++ if (ret != 0) ++ return -ENOMEM; ++ } ++ ++ /* Setup INTx */ ++ pcie->legacy_irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, ++ &intx_domain_ops, pcie); ++ ++ if (!pcie->legacy_irq_domain) { ++ dev_err(dev, "Failed to get a INTx IRQ domain\n"); ++ return -ENOMEM; ++ } ++ ++ irq_set_chained_handler_and_data(pcie->irq, starfive_pcie_isr, pcie); ++ ++ return 0; ++} ++ ++static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie) ++{ ++ struct resource *cfg_res; ++ struct platform_device *pdev = pcie->pdev; ++ unsigned int args[4]; ++ ++ pcie->reg_base = ++ devm_platform_ioremap_resource_byname(pdev, "reg"); ++ ++ if (IS_ERR(pcie->reg_base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->reg_base), ++ "Failed to map reg memory\n"); ++ ++ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); ++ if (!cfg_res) ++ return dev_err_probe(&pdev->dev, -ENODEV, ++ "Failed to get config memory\n"); ++ ++ pcie->config_base = devm_ioremap_resource(&pdev->dev, cfg_res); ++ if (IS_ERR(pcie->config_base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->config_base), ++ "Failed to map config memory\n"); ++ ++ pcie->config_phyaddr = cfg_res->start; ++ ++ pcie->phy = devm_phy_optional_get(&pdev->dev, NULL); ++ if (IS_ERR(pcie->phy)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->phy), ++ "Failed to get pcie phy\n"); ++ ++ pcie->irq = platform_get_irq(pdev, 0); ++ if (pcie->irq < 0) ++ return dev_err_probe(&pdev->dev, -EINVAL, ++ "Failed to get IRQ: %d\n", pcie->irq); ++ ++ pcie->reg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", 4, args); ++ ++ if (IS_ERR(pcie->reg_syscon)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->reg_syscon), ++ "Failed to parse starfive,stg-syscon\n"); ++ ++ pcie->stg_arfun = args[0]; ++ pcie->stg_awfun = args[1]; ++ pcie->stg_rp_nep = args[2]; ++ pcie->stg_lnksta = args[3]; ++ ++ /* Clear all interrupts */ ++ writel(0xffffffff, pcie->reg_base + ISTATUS_LOCAL); ++ writel(INT_INTX_MASK | INT_ERRORS, pcie->reg_base + IMASK_LOCAL); ++ ++ return 0; ++} ++ ++static struct pci_ops starfive_pcie_ops = { ++ .map_bus = starfive_pcie_map_bus, ++ .read = pci_generic_config_read, ++ .write = starfive_pcie_config_write, ++}; ++ ++static void starfive_pcie_set_atr_entry(struct starfive_jh7110_pcie *pcie, ++ phys_addr_t src_addr, phys_addr_t trsl_addr, ++ size_t window_size, int trsl_param) ++{ ++ void __iomem *base = ++ pcie->reg_base + XR3PCI_ATR_AXI4_SLV0; ++ ++ /* Support AXI4 Slave 0 Address Translation Tables 0-7. */ ++ if (pcie->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) ++ pcie->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1; ++ base += XR3PCI_ATR_TABLE_OFFSET * pcie->atr_table_num; ++ pcie->atr_table_num++; ++ ++ /* ++ * X3PCI_ATR_SRC_ADDR_LOW: ++ * - bit 0: enable entry, ++ * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) ++ * - bits 7-11: reserved ++ * - bits 12-31: start of source address ++ */ ++ writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) | ++ (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1, ++ base + XR3PCI_ATR_SRC_ADDR_LOW); ++ writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH); ++ writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK), ++ base + XR3PCI_ATR_TRSL_ADDR_LOW); ++ writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH); ++ writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); ++ ++ dev_info(&pcie->pdev->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n", ++ src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->", ++ trsl_addr, (u64)window_size, trsl_param); ++} ++ ++static int starfive_pcie_setup_windows(struct starfive_jh7110_pcie *pcie) ++{ ++ struct pci_host_bridge *bridge = pcie->bridge; ++ struct resource_entry *entry; ++ u64 pci_addr; ++ ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ if (resource_type(entry->res) == IORESOURCE_MEM) { ++ pci_addr = entry->res->start - entry->offset; ++ starfive_pcie_set_atr_entry(pcie, ++ entry->res->start, pci_addr, ++ resource_size(entry->res), ++ XR3PCI_ATR_TRSLID_PCIE_MEMORY); ++ } ++ } ++ ++ return 0; ++} ++ ++static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) ++{ ++ int ret; ++ struct device *dev = &pcie->pdev->dev; ++ ++ pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); ++ if (pcie->num_clks < 0) ++ return dev_err_probe(dev, -ENODEV, ++ "Failed to get pcie clocks\n"); ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) ++ return dev_err_probe(&pcie->pdev->dev, ret, ++ "Failed to enable clocks\n"); ++ ++ pcie->resets = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(pcie->resets)) { ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ return dev_err_probe(dev, PTR_ERR(pcie->resets), ++ "Failed to get pcie resets"); ++ } ++ ++ return reset_control_deassert(pcie->resets); ++} ++ ++static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) ++{ ++ reset_control_assert(pcie->resets); ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++} ++ ++int starfive_pcie_gpio_init(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ ++ pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); ++ if (IS_ERR_OR_NULL(pcie->reset_gpio)) { ++ dev_warn(dev, "Failed to get reset-gpio.\n"); ++ return -EINVAL; ++ } ++ ++ pcie->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW); ++ if (IS_ERR_OR_NULL(pcie->power_gpio)) ++ pcie->power_gpio = NULL; ++ ++ return 0; ++} ++ ++static void starfive_pcie_hw_init(struct starfive_jh7110_pcie *pcie) ++{ ++ unsigned int value; ++ int i; ++ ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 1); ++ ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 1); ++ ++ /* Disable physical functions except #0 */ ++ for (i = 1; i < PCIE_FUNC_NUM; i++) { ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_arfun, ++ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, ++ (i << PHY_FUNC_SHIFT) << ++ STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, ++ i << PHY_FUNC_SHIFT); ++ ++ value = readl(pcie->reg_base + PCI_MISC); ++ value |= PHY_FUNCTION_DIS; ++ writel(value, pcie->reg_base + PCI_MISC); ++ } ++ ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_arfun, ++ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, ++ 0); ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, ++ 0); ++ ++ /* Enable root port */ ++ value = readl(pcie->reg_base + GEN_SETTINGS); ++ value |= RP_ENABLE; ++ writel(value, pcie->reg_base + GEN_SETTINGS); ++ ++ /* PCIe PCI Standard Configuration Identification Settings. */ ++ value = (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); ++ writel(value, pcie->reg_base + PCIE_PCI_IDS); ++ ++ /* ++ * The LTR message forwarding of PCIe Message Reception was set by core ++ * as default, but the forward id & addr are also need to be reset. ++ * If we do not disable LTR message forwarding here, or set a legal ++ * forwarding address, the kernel will get stuck after this driver probe. ++ * To workaround, disable the LTR message forwarding support on ++ * PCIe Message Reception. ++ */ ++ value = readl(pcie->reg_base + PMSG_SUPPORT_RX); ++ value &= ~PMSG_LTR_SUPPORT; ++ writel(value, pcie->reg_base + PMSG_SUPPORT_RX); ++ ++ /* Prefetchable memory window 64-bit addressing support */ ++ value = readl(pcie->reg_base + PCIE_WINROM); ++ value |= PREF_MEM_WIN_64_SUPPORT; ++ writel(value, pcie->reg_base + PCIE_WINROM); ++ ++ /* ++ * As the two host bridges in JH7110 soc have the same default ++ * address translation table, this cause the second root port can't ++ * access it's host bridge config space correctly. ++ * To workaround, config the ATR of host bridge config space by SW. ++ */ ++ starfive_pcie_set_atr_entry(pcie, ++ pcie->config_phyaddr, 0, ++ XR3PCI_ECAM_SIZE, ++ XR3PCI_ATR_TRSLID_PCIE_CONFIG); ++ ++ starfive_pcie_setup_windows(pcie); ++ ++ /* Ensure that PERST has been asserted for at least 100 ms */ ++ msleep(300); ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 0); ++} ++ ++static bool starfive_pcie_is_link_up(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ int ret; ++ u32 stg_reg_val; ++ ++ /* 100ms timeout value should be enough for Gen1/2 training */ ++ ret = regmap_read_poll_timeout(pcie->reg_syscon, ++ pcie->stg_lnksta, ++ stg_reg_val, ++ stg_reg_val & DATA_LINK_ACTIVE, ++ 10 * 1000, 100 * 1000); ++ ++ /* If the link is down (no device in slot), then exit. */ ++ if (ret == -ETIMEDOUT) { ++ dev_info(dev, "Port link down, exit.\n"); ++ return false; ++ } else if (ret == 0) { ++ dev_info(dev, "Port link up.\n"); ++ return true; ++ } ++ ++ dev_warn(dev, "Read stg_linksta failed.\n"); ++ ++ return false; ++} ++ ++static int starfive_pcie_enable_phy(struct device *dev, ++ struct starfive_jh7110_pcie *pcie) ++{ ++ int ret; ++ ++ if (!pcie->phy) ++ return 0; ++ ++ ret = phy_init(pcie->phy); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to initialize pcie phy\n"); ++ ++ ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); ++ if (ret) { ++ ret = dev_err_probe(dev, ret, ++ "failed to set pcie mode\n"); ++ goto err_phy_on; ++ } ++ ++ ret = phy_power_on(pcie->phy); ++ if (ret) { ++ ret = dev_err_probe(dev, ret, "failed to power on pcie phy\n"); ++ goto err_phy_on; ++ } ++ ++ return 0; ++ ++err_phy_on: ++ phy_exit(pcie->phy); ++ return ret; ++} ++ ++static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) ++{ ++ phy_power_off(pcie->phy); ++ phy_exit(pcie->phy); ++} ++ ++static int starfive_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct starfive_jh7110_pcie *pcie; ++ struct pci_bus *bus; ++ struct pci_host_bridge *bridge; ++ int ret; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->pdev = pdev; ++ pcie->atr_table_num = 0; ++ ++ ret = starfive_pcie_parse_dt(pcie); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, pcie); ++ ++ ret = starfive_pcie_gpio_init(pcie); ++ if (ret) ++ return ret; ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_rp_nep, ++ STG_SYSCON_K_RP_NEP, ++ STG_SYSCON_K_RP_NEP); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_CKREF_SRC_MASK, ++ 2 << STG_SYSCON_CKREF_SRC_SHIFT); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_CLKREQ, ++ STG_SYSCON_CLKREQ); ++ ++ ret = starfive_pcie_clk_rst_init(pcie); ++ if (ret) ++ return ret; ++ ++ ret = starfive_pcie_init_irq_domain(pcie); ++ if (ret) ++ return ret; ++ ++ bridge = devm_pci_alloc_host_bridge(dev, 0); ++ if (!bridge) ++ return -ENOMEM; ++ ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ ++ /* Set default bus ops */ ++ bridge->ops = &starfive_pcie_ops; ++ bridge->sysdata = pcie; ++ pcie->bridge = bridge; ++ ++ starfive_pcie_hw_init(pcie); ++ ++ if (starfive_pcie_is_link_up(pcie) == false) ++ goto release; ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ ret = starfive_pcie_enable_msi(pcie, bus); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable MSI support: %d\n", ret); ++ goto release; ++ } ++ } ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ goto release; ++ ++ ret = pci_host_probe(bridge); ++ if (ret < 0) { ++ dev_err_probe(dev, ret, "Failed to pci host probe: %d\n", ret); ++ goto err_phy_on; ++ } ++ ++ return ret; ++ ++err_phy_on: ++ starfive_pcie_disable_phy(pcie); ++release: ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 0); ++ ++ starfive_pcie_clk_rst_deinit(pcie); ++ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ pci_free_host_bridge(pcie->bridge); ++ platform_set_drvdata(pdev, NULL); ++ ++ return ret; ++} ++ ++static int starfive_pcie_remove(struct platform_device *pdev) ++{ ++ struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev); ++ ++ starfive_pcie_disable_phy(pcie); ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 0); ++ starfive_pcie_free_irq_domain(pcie); ++ starfive_pcie_clk_rst_deinit(pcie); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int __maybe_unused starfive_pcie_suspend_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ ++ if (!pcie) ++ return 0; ++ ++ starfive_pcie_disable_phy(pcie); ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused starfive_pcie_resume_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ int ret; ++ ++ if (!pcie) ++ return 0; ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to enable clocks\n"); ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ ++ return ret; ++} ++ ++static const struct dev_pm_ops starfive_pcie_pm_ops = { ++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq, ++ starfive_pcie_resume_noirq) ++}; ++#endif ++ ++static const struct of_device_id starfive_pcie_of_match[] = { ++ { .compatible = "starfive,jh7110-pcie"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); ++ ++static struct platform_driver starfive_pcie_driver = { ++ .driver = { ++ .name = "pcie-starfive", ++ .of_match_table = of_match_ptr(starfive_pcie_of_match), ++#ifdef CONFIG_PM_SLEEP ++ .pm = &starfive_pcie_pm_ops, ++#endif ++ }, ++ .probe = starfive_pcie_probe, ++ .remove = starfive_pcie_remove, ++}; ++module_platform_driver(starfive_pcie_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); ++MODULE_AUTHOR("Mason Huo "); ++MODULE_AUTHOR("Kevin Xie "); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL v2"); +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0081-riscv-dts-starfive-add-PCIe-dts-configuration-for-JH.patch b/srcpkgs/linux6.3/patches/0081-riscv-dts-starfive-add-PCIe-dts-configuration-for-JH.patch new file mode 100644 index 0000000000000..d98031caf3301 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0081-riscv-dts-starfive-add-PCIe-dts-configuration-for-JH.patch @@ -0,0 +1,188 @@ +From c4c2ee5edd411f4ccd7947621cfafd9a57ddb271 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 6 Apr 2023 19:11:42 +0800 +Subject: [PATCH 81/84] riscv: dts: starfive: add PCIe dts configuration for + JH7110 + +The PCIe is a PCIe2, single lane PCIe compliant controller. + +Signed-off-by: Minda Chen +--- + .../jh7110-starfive-visionfive-2.dtsi | 58 ++++++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 88 +++++++++++++++++++ + 2 files changed, 146 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 4ccd20303ab5..abca2de931bd 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -205,6 +205,50 @@ GPOEN_SYS_I2C6_DATA, + }; + }; + ++ pcie0_wake_default: pcie0_wake_default { ++ wake-pins { ++ pinmux = ; ++ bias-disable; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie0_clkreq_default: pcie0_clkreq_default { ++ clkreq-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie1_wake_default: pcie1_wake_default { ++ wake-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie1_clkreq_default: pcie1_clkreq_default { ++ clkreq-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ + uart0_pins: uart0-0 { + tx-pins { + pinmux = ; + status = "okay"; + }; ++ ++&pcie0 { ++ pinctrl-names = "default"; ++ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy0>; ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-names = "default"; ++ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy1>; ++ status = "okay"; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index d545684958c4..742fc37c3c5e 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -753,5 +753,93 @@ crypto: crypto@16000000 { + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; + }; ++ ++ pcie0: pcie@2B000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2B000000 0x0 0x1000000 ++ 0x9 0x40000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ interrupts = <56>; ++ interrupt-parent = <&plic>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-parent = <&pcie0>; ++ msi-controller; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE0_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE0_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE0_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE0_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE0_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie1: pcie@2C000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2C000000 0x0 0x1000000 ++ 0x9 0xc0000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; ++ interrupts = <57>; ++ interrupt-parent = <&plic>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; ++ msi-parent = <&pcie1>; ++ msi-controller; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE1_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE1_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE1_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE1_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE1_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; + }; + }; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0082-riscv-dts-starfive-add-pmu-controller-node.patch b/srcpkgs/linux6.3/patches/0082-riscv-dts-starfive-add-pmu-controller-node.patch new file mode 100644 index 0000000000000..a27e46cb37e8d --- /dev/null +++ b/srcpkgs/linux6.3/patches/0082-riscv-dts-starfive-add-pmu-controller-node.patch @@ -0,0 +1,34 @@ +From adbbc3b565f2214d6035696eca69bfdd89b72912 Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Mon, 16 Jan 2023 15:42:59 +0800 +Subject: [PATCH 82/84] riscv: dts: starfive: add pmu controller node + +Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs +to be used by other modules such as VPU, ISP, etc. + +Signed-off-by: Walker Chen +--- + arch/riscv/boot/dts/starfive/jh7110.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 742fc37c3c5e..7eb53c84172e 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -691,6 +691,13 @@ aongpio: pinctrl@17020000 { + #gpio-cells = <2>; + }; + ++ pwrc: power-controller@17030000 { ++ compatible = "starfive,jh7110-pmu"; ++ reg = <0x0 0x17030000 0x0 0x10000>; ++ interrupts = <111>; ++ #power-domain-cells = <1>; ++ }; ++ + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0083-add-missing-include.patch b/srcpkgs/linux6.3/patches/0083-add-missing-include.patch new file mode 100644 index 0000000000000..1904842e38033 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0083-add-missing-include.patch @@ -0,0 +1,24 @@ +From fd91338a0c429c5a393abc44089383a7934c4642 Mon Sep 17 00:00:00 2001 +From: John Zimmermann +Date: Thu, 18 May 2023 00:20:34 +0200 +Subject: [PATCH 83/84] add missing include + +--- + drivers/clk/starfive/clk-starfive-jh7110-pll.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +index f86deddd4bef..b381c807f26c 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110-pll.c ++++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + #include + #include + #include +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/0084-crypto-hash-Add-statesize-to-crypto_ahash.patch b/srcpkgs/linux6.3/patches/0084-crypto-hash-Add-statesize-to-crypto_ahash.patch new file mode 100644 index 0000000000000..1a8e4c9269359 --- /dev/null +++ b/srcpkgs/linux6.3/patches/0084-crypto-hash-Add-statesize-to-crypto_ahash.patch @@ -0,0 +1,70 @@ +From cb7fa885033e37093c8ee6b98f200f317ef7c5b0 Mon Sep 17 00:00:00 2001 +From: Herbert Xu +Date: Thu, 20 Apr 2023 18:05:16 +0800 +Subject: [PATCH 84/84] crypto: hash - Add statesize to crypto_ahash + +As ahash drivers may need to use fallbacks, their state size +is thus variable. Deal with this by making it an attribute +of crypto_ahash. + +Signed-off-by: Herbert Xu +--- + crypto/ahash.c | 2 ++ + include/crypto/hash.h | 3 ++- + include/crypto/internal/hash.h | 6 ++++++ + 3 files changed, 10 insertions(+), 1 deletion(-) + +diff --git a/crypto/ahash.c b/crypto/ahash.c +index ff8c79d975c1..db8655c47a65 100644 +--- a/crypto/ahash.c ++++ b/crypto/ahash.c +@@ -428,6 +428,8 @@ static int crypto_ahash_init_tfm(struct crypto_tfm *tfm) + + hash->setkey = ahash_nosetkey; + ++ crypto_ahash_set_statesize(hash, alg->halg.statesize); ++ + if (tfm->__crt_alg->cra_type != &crypto_ahash_type) + return crypto_init_shash_ops_async(tfm); + +diff --git a/include/crypto/hash.h b/include/crypto/hash.h +index f5841992dc9b..087998da0520 100644 +--- a/include/crypto/hash.h ++++ b/include/crypto/hash.h +@@ -232,6 +232,7 @@ struct crypto_ahash { + int (*setkey)(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen); + ++ unsigned int statesize; + unsigned int reqsize; + struct crypto_tfm base; + }; +@@ -370,7 +371,7 @@ static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm) + */ + static inline unsigned int crypto_ahash_statesize(struct crypto_ahash *tfm) + { +- return crypto_hash_alg_common(tfm)->statesize; ++ return tfm->statesize; + } + + static inline u32 crypto_ahash_get_flags(struct crypto_ahash *tfm) +diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h +index 0b259dbb97af..02cedba84f1a 100644 +--- a/include/crypto/internal/hash.h ++++ b/include/crypto/internal/hash.h +@@ -151,6 +151,12 @@ static inline struct ahash_alg *__crypto_ahash_alg(struct crypto_alg *alg) + halg); + } + ++static inline void crypto_ahash_set_statesize(struct crypto_ahash *tfm, ++ unsigned int size) ++{ ++ tfm->statesize = size; ++} ++ + static inline void crypto_ahash_set_reqsize(struct crypto_ahash *tfm, + unsigned int reqsize) + { +-- +2.40.1 + diff --git a/srcpkgs/linux6.3/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch b/srcpkgs/linux6.3/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch new file mode 100644 index 0000000000000..30054f697d40c --- /dev/null +++ b/srcpkgs/linux6.3/patches/1-2-HID-logitech-dj-add-support-for-the-new-lightspeed-receiver-iteration.patch @@ -0,0 +1,276 @@ +From patchwork Sat Jan 23 18:03:33 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?q?Filipe_La=C3=ADns?= +X-Patchwork-Id: 12041761 +X-Patchwork-Delegate: jikos@jikos.cz +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-23.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, + INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING, + SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham + autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id CAA6BC433E0 + for ; Sat, 23 Jan 2021 18:04:54 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 9274B22DFA + for ; Sat, 23 Jan 2021 18:04:54 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726151AbhAWSEg (ORCPT ); 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+ auth=pass smtp.auth=ffy00 smtp.mailfrom=lains@archlinux.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-input@vger.kernel.org + +From: Filipe Laíns + +Tested with the G Pro X Superlight. libratbag sees the device, as +expected, and input events are passing trough. + +https://github.com/libratbag/libratbag/pull/1122 + +The receiver has a quirk where the moused interface doesn't have a +report ID, I am not sure why, perhaps they forgot. All other interfaces +have report IDs so I am left scratching my head. +Since this driver doesn't have a quirk system, I simply implemented it +as a different receiver type, which is true, it just wouldn't be the +prefered approach :P + +Signed-off-by: Filipe Laíns +--- + drivers/hid/hid-ids.h | 1 + + drivers/hid/hid-logitech-dj.c | 49 +++++++++++++++++++++++++---------- + 2 files changed, 37 insertions(+), 13 deletions(-) + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index 4c5f23640f9c..8eac3c93fa38 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -803,6 +803,7 @@ + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1 0xc539 + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1 0xc53f + #define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY 0xc53a ++#define USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2 0xc547 + #define USB_DEVICE_ID_SPACETRAVELLER 0xc623 + #define USB_DEVICE_ID_SPACENAVIGATOR 0xc626 + #define USB_DEVICE_ID_DINOVO_DESKTOP 0xc704 +diff --git a/drivers/hid/hid-logitech-dj.c b/drivers/hid/hid-logitech-dj.c +index 1401ee2067ca..6596c81947a8 100644 +--- a/drivers/hid/hid-logitech-dj.c ++++ b/drivers/hid/hid-logitech-dj.c +@@ -114,6 +114,7 @@ enum recvr_type { + recvr_type_dj, + recvr_type_hidpp, + recvr_type_gaming_hidpp, ++ recvr_type_gaming_hidpp_missing_mse_report_id, /* lightspeed receiver missing the mouse report ID */ + recvr_type_mouse_only, + recvr_type_27mhz, + recvr_type_bluetooth, +@@ -1360,6 +1361,7 @@ static int logi_dj_ll_parse(struct hid_device *hid) + dbg_hid("%s: sending a mouse descriptor, reports_supported: %llx\n", + __func__, djdev->reports_supported); + if (djdev->dj_receiver_dev->type == recvr_type_gaming_hidpp || ++ djdev->dj_receiver_dev->type == recvr_type_gaming_hidpp_missing_mse_report_id || + djdev->dj_receiver_dev->type == recvr_type_mouse_only) + rdcat(rdesc, &rsize, mse_high_res_descriptor, + sizeof(mse_high_res_descriptor)); +@@ -1692,11 +1692,12 @@ + } + /* + * Mouse-only receivers send unnumbered mouse data. The 27 MHz +- * receiver uses 6 byte packets, the nano receiver 8 bytes. ++ * receiver uses 6 byte packets, the nano receiver 8 bytes. and ++ * some gaming ones are using 16 bytes. + */ + if (djrcv_dev->unnumbered_application == HID_GD_MOUSE && +- size <= 8) { +- u8 mouse_report[9]; ++ size <= 16) { ++ u8 mouse_report[17]; + + /* Prepend report id */ + mouse_report[0] = REPORT_TYPE_MOUSE; +@@ -1688,6 +1706,7 @@ static int logi_dj_probe(struct hid_device *hdev, + case recvr_type_dj: no_dj_interfaces = 3; break; + case recvr_type_hidpp: no_dj_interfaces = 2; break; + case recvr_type_gaming_hidpp: no_dj_interfaces = 3; break; ++ case recvr_type_gaming_hidpp_missing_mse_report_id: no_dj_interfaces = 3; break; + case recvr_type_mouse_only: no_dj_interfaces = 2; break; + case recvr_type_27mhz: no_dj_interfaces = 2; break; + case recvr_type_bluetooth: no_dj_interfaces = 2; break; +@@ -1984,6 +1984,10 @@ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, + USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1), + .driver_data = recvr_type_gaming_hidpp}, ++ { /* Logitech lightspeed receiver (0xc547) */ ++ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, ++ USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_2), ++ .driver_data = recvr_type_gaming_hidpp_missing_mse_report_id}, + + { /* Logitech 27 MHz HID++ 1.0 receiver (0xc513) */ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_MX3000_RECEIVER), +From patchwork Sat Jan 23 18:03:34 2021 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 8bit +X-Patchwork-Submitter: =?utf-8?q?Filipe_La=C3=ADns?= +X-Patchwork-Id: 12041763 +X-Patchwork-Delegate: jikos@jikos.cz +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, + 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bh=pUy5GRn6iAd0774+zrvt/xxLsLy5Gfph7I887BlZzNk=; + b=noC/7x4rdVIF6TIIpPH6gRDnKKvdwV8Dh1v1QhdRRC+my3IExMwH+AujrLW22mX6LXKjM0 + hIi/YnKi2uRn2SAw== +From: =?utf-8?q?Filipe_La=C3=ADns?= +To: Jiri Kosina , + Benjamin Tissoires , + linux-input@vger.kernel.org, linux-kernel@vger.kernel.org +Cc: =?utf-8?q?Filipe_La=C3=ADns?= +Subject: [PATCH 2/2] HID: logitech-hidpp: add support for the G Pro X + Superlight over USB +Date: Sat, 23 Jan 2021 18:03:34 +0000 +Message-Id: <20210123180334.3062995-2-lains@archlinux.org> +X-Mailer: git-send-email 2.30.0 +In-Reply-To: <20210123180334.3062995-1-lains@archlinux.org> +References: <20210123180334.3062995-1-lains@archlinux.org> +MIME-Version: 1.0 +Authentication-Results: mail.archlinux.org; + auth=pass smtp.auth=ffy00 smtp.mailfrom=lains@archlinux.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-input@vger.kernel.org + +From: Filipe Laíns + +Tested and is working :) + +Signed-off-by: Filipe Laíns +--- + drivers/hid/hid-logitech-hidpp.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c +index 291c6b4d26b7..54a289510a7d 100644 +--- a/drivers/hid/hid-logitech-hidpp.c ++++ b/drivers/hid/hid-logitech-hidpp.c +@@ -4268,6 +4268,8 @@ static const struct hid_device_id hidpp_devices[] = { + .driver_data = HIDPP_QUIRK_CLASS_G920 | HIDPP_QUIRK_FORCE_OUTPUT_REPORTS}, + { /* Logitech G Pro Gaming Mouse over USB */ + HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC088) }, ++ { /* Logitech G Pro X Superlight Gaming Mouse over USB */ ++ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, 0xC094) }, + + { /* MX5000 keyboard over Bluetooth */ + HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_LOGITECH, 0xb305), diff --git a/srcpkgs/linux6.3/template b/srcpkgs/linux6.3/template index f2e373f55278d..c3e44930c61ec 100644 --- a/srcpkgs/linux6.3/template +++ b/srcpkgs/linux6.3/template @@ -18,7 +18,7 @@ checksum="ba3491f5ed6bd270a370c440434e3d69085fcdd528922fa01e73d7657db73b1e python_version=3 # XXX Restrict archs until a proper -dotconfig is available in FILESDIR. -archs="x86_64* i686* aarch64*" +archs="x86_64* i686* aarch64* riscv64*" nodebug=yes # -dbg package is generated below manually nostrip=yes From 0d029c32d100b848c58dcff6d1ca765761bba0bf Mon Sep 17 00:00:00 2001 From: John Date: Tue, 11 Jul 2023 08:59:27 +0200 Subject: [PATCH 186/189] linux6.2: remove riscv64 patchset --- ...orm-Add-snps-dwmac-5.20-IP-compatibl.patch | 32 -- ...snps-dwmac-Add-an-optional-resets-si.patch | 48 -- ...ive-jh7110-Add-ethernet-device-nodes.patch | 125 ----- ...d-glue-layer-for-StarFive-JH7110-SoC.patch | 199 -------- ...starfive-jh7110-dwmac-Add-starfive-s.patch | 47 -- ...five_dmac-Add-phy-interface-settings.patch | 97 ---- ...ve-jh7110-Add-syscon-to-support-phy-.patch | 37 -- ...ve-visionfive-2-v1.3b-Add-gmac-phy-s.patch | 55 --- ...ve-visionfive-2-v1.2a-Add-gmac-phy-s.patch | 41 -- ...ve-visionfive-2-Enable-gmac-device-t.patch | 45 -- ...dings-net-Add-support-StarFive-dwmac.patch | 31 -- ...-glue-layer-for-StarFive-JH7110-SoCs.patch | 192 ------- ...et-Add-Motorcomm-yt8xxx-ethernet-phy.patch | 167 ------- ...macro-for-Motorcomm-yt8521-yt8531-gi.patch | 111 ----- ...support-for-Motorcomm-yt8521-gigabit.patch | 347 ------------- ...support-for-Motorcomm-yt8531s-gigabi.patch | 104 ---- ...er-for-Motorcomm-yt8531-gigabit-ethe.patch | 308 ------------ ...dings-hwmon-Add-starfive-jh71x0-temp.patch | 95 ---- ...d-StarFive-JH71x0-temperature-sensor.patch | 467 ------------------ 19 files changed, 2548 deletions(-) delete mode 100644 srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch delete mode 100644 srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch delete mode 100644 srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch delete mode 100644 srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch delete mode 100644 srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch delete mode 100644 srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch delete mode 100644 srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch delete mode 100644 srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch delete mode 100644 srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch delete mode 100644 srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch delete mode 100644 srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch delete mode 100644 srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch delete mode 100644 srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch delete mode 100644 srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch delete mode 100644 srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch delete mode 100644 srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch delete mode 100644 srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch delete mode 100644 srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch delete mode 100644 srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch diff --git a/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch b/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch deleted file mode 100644 index 984f0fe5a5866..0000000000000 --- a/srcpkgs/linux6.2/patches/0051-net-stmmac-platform-Add-snps-dwmac-5.20-IP-compatibl.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 238f315bbcebe9d4168b5d75cff4a9af7b38bc7f Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Fri, 3 Mar 2023 16:59:18 +0800 -Subject: [PATCH 51/70] net: stmmac: platform: Add snps,dwmac-5.20 IP - compatible string - -Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid -to define some platform data in the glue layer. - -Signed-off-by: Emil Renner Berthing -Signed-off-by: Samin Guo ---- - drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -index 0046a4ee6e64..807eca7edf53 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c -@@ -519,7 +519,8 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac) - if (of_device_is_compatible(np, "snps,dwmac-4.00") || - of_device_is_compatible(np, "snps,dwmac-4.10a") || - of_device_is_compatible(np, "snps,dwmac-4.20a") || -- of_device_is_compatible(np, "snps,dwmac-5.10a")) { -+ of_device_is_compatible(np, "snps,dwmac-5.10a") || -+ of_device_is_compatible(np, "snps,dwmac-5.20")) { - plat->has_gmac4 = 1; - plat->has_gmac = 0; - plat->pmt = 1; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch b/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch deleted file mode 100644 index 8a432c21972bc..0000000000000 --- a/srcpkgs/linux6.2/patches/0052-dt-bindings-net-snps-dwmac-Add-an-optional-resets-si.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 4f6a9a8acb9b9da0f3bee80c46800d7593db851d Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:19 +0800 -Subject: [PATCH 52/70] dt-bindings: net: snps,dwmac: Add an optional resets - single 'ahb' - -According to: -stmmac_platform.c: stmmac_probe_config_dt -stmmac_main.c: stmmac_dvr_probe - -dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb) -reset signals, and the maxItems of resets/reset-names is going to be 2. - -Signed-off-by: Samin Guo ---- - .../devicetree/bindings/net/snps,dwmac.yaml | 14 ++++++++++---- - 1 file changed, 10 insertions(+), 4 deletions(-) - -diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -index b4135d5297b4..89099a888f0b 100644 ---- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml -@@ -133,12 +133,18 @@ properties: - - ptp_ref - - resets: -- maxItems: 1 -- description: -- MAC Reset signal. -+ minItems: 1 -+ items: -+ - description: GMAC stmmaceth reset -+ - description: AHB reset - - reset-names: -- const: stmmaceth -+ minItems: 1 -+ maxItems: 2 -+ contains: -+ enum: -+ - stmmaceth -+ - ahb - - power-domains: - maxItems: 1 --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch b/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch deleted file mode 100644 index 0e9b25758ad11..0000000000000 --- a/srcpkgs/linux6.2/patches/0054-riscv-dts-starfive-jh7110-Add-ethernet-device-nodes.patch +++ /dev/null @@ -1,125 +0,0 @@ -From 46355830a010e30b11d02da939d1b7214dd0e4e0 Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:21 +0800 -Subject: [PATCH 54/70] riscv: dts: starfive: jh7110: Add ethernet device nodes - -Add JH7110 ethernet device node to support gmac driver for the JH7110 -RISC-V SoC. - -Signed-off-by: Yanhong Wang -Signed-off-by: Samin Guo ---- - arch/riscv/boot/dts/starfive/jh7110.dtsi | 91 ++++++++++++++++++++++++ - 1 file changed, 91 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi -index 3724c2c9035a..b0e87198808a 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi -@@ -234,6 +234,13 @@ i2srx_lrck_ext: i2srx-lrck-ext-clock { - #clock-cells = <0>; - }; - -+ stmmac_axi_setup: stmmac-axi-config { -+ snps,lpi_en; -+ snps,wr_osr_lmt = <4>; -+ snps,rd_osr_lmt = <4>; -+ snps,blen = <256 128 64 32 0 0 0>; -+ }; -+ - tdm_ext: tdm-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; -@@ -658,5 +665,89 @@ mmc1: mmc@16020000 { - starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; - status = "disabled"; - }; -+ -+ gmac0: ethernet@16030000 { -+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; -+ reg = <0x0 0x16030000 0x0 0x10000>; -+ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, -+ <&aoncrg JH7110_AONCLK_GMAC0_AHB>, -+ <&syscrg JH7110_SYSCLK_GMAC0_PTP>, -+ <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, -+ <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", -+ "tx", "gtx"; -+ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, -+ <&aoncrg JH7110_AONRST_GMAC0_AHB>; -+ reset-names = "stmmaceth", "ahb"; -+ interrupts = <7>, <6>, <5>; -+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; -+ phy-mode = "rgmii-id"; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <8>; -+ rx-fifo-depth = <2048>; -+ tx-fifo-depth = <2048>; -+ snps,fixed-burst; -+ snps,no-pbl-x8; -+ snps,force_thresh_dma_mode; -+ snps,axi-config = <&stmmac_axi_setup>; -+ snps,tso; -+ snps,en-tx-lpi-clockgating; -+ snps,txpbl = <16>; -+ snps,rxpbl = <16>; -+ status = "disabled"; -+ phy-handle = <&phy0>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ -+ phy0: ethernet-phy@0 { -+ reg = <0>; -+ }; -+ }; -+ }; -+ -+ gmac1: ethernet@16040000 { -+ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; -+ reg = <0x0 0x16040000 0x0 0x10000>; -+ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, -+ <&syscrg JH7110_SYSCLK_GMAC1_AHB>, -+ <&syscrg JH7110_SYSCLK_GMAC1_PTP>, -+ <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, -+ <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; -+ clock-names = "stmmaceth", "pclk", "ptp_ref", -+ "tx", "gtx"; -+ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, -+ <&syscrg JH7110_SYSRST_GMAC1_AHB>; -+ reset-names = "stmmaceth", "ahb"; -+ interrupts = <78>, <77>, <76>; -+ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; -+ phy-mode = "rgmii-id"; -+ snps,multicast-filter-bins = <64>; -+ snps,perfect-filter-entries = <8>; -+ rx-fifo-depth = <2048>; -+ tx-fifo-depth = <2048>; -+ snps,fixed-burst; -+ snps,no-pbl-x8; -+ snps,force_thresh_dma_mode; -+ snps,axi-config = <&stmmac_axi_setup>; -+ snps,tso; -+ snps,en-tx-lpi-clockgating; -+ snps,txpbl = <16>; -+ snps,rxpbl = <16>; -+ status = "disabled"; -+ phy-handle = <&phy1>; -+ -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "snps,dwmac-mdio"; -+ -+ phy1: ethernet-phy@1 { -+ reg = <0>; -+ }; -+ }; -+ }; - }; - }; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch b/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch deleted file mode 100644 index 97f1527b27e1c..0000000000000 --- a/srcpkgs/linux6.2/patches/0055-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoC.patch +++ /dev/null @@ -1,199 +0,0 @@ -From bd106dc923482e9c6b8fc96e04ef03ab3f37f47d Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:22 +0800 -Subject: [PATCH 55/70] net: stmmac: Add glue layer for StarFive JH7110 SoC - -This adds StarFive dwmac driver support on the StarFive JH7110 SoC. - -Co-developed-by: Emil Renner Berthing -Signed-off-by: Emil Renner Berthing -Signed-off-by: Samin Guo ---- - MAINTAINERS | 1 + - drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ - drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + - .../ethernet/stmicro/stmmac/dwmac-starfive.c | 125 ++++++++++++++++++ - 4 files changed, 139 insertions(+) - create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index 31560d13afed..8ff112156e1f 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -19915,6 +19915,7 @@ STARFIVE DWMAC GLUE LAYER - M: Emil Renner Berthing - M: Samin Guo - S: Maintained -+F: Documentation/devicetree/bindings/net/dwmac-starfive.c - F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml - - STARFIVE JH71X0 CLOCK DRIVERS -diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig -index f77511fe4e87..47fbccef9d04 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -165,6 +165,18 @@ config DWMAC_SOCFPGA - for the stmmac device driver. This driver is used for - arria5 and cyclone5 FPGA SoCs. - -+config DWMAC_STARFIVE -+ tristate "StarFive dwmac support" -+ depends on OF && (ARCH_STARFIVE || COMPILE_TEST) -+ depends on STMMAC_ETH -+ default ARCH_STARFIVE -+ help -+ Support for ethernet controllers on StarFive RISC-V SoCs -+ -+ This selects the StarFive platform specific glue layer support for -+ the stmmac device driver. This driver is used for StarFive JH7110 -+ ethernet controller. -+ - config DWMAC_STI - tristate "STi GMAC support" - default ARCH_STI -diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile -index 057e4bab5c08..8738fdbb4b2d 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -23,6 +23,7 @@ obj-$(CONFIG_DWMAC_OXNAS) += dwmac-oxnas.o - obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o - obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o - obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o -+obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o - obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o - obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o - obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c -new file mode 100644 -index 000000000000..566378306f67 ---- /dev/null -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c -@@ -0,0 +1,125 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * StarFive DWMAC platform driver -+ * -+ * Copyright (C) 2022 StarFive Technology Co., Ltd. -+ * Copyright (C) 2022 Emil Renner Berthing -+ * -+ */ -+ -+#include -+ -+#include "stmmac_platform.h" -+ -+struct starfive_dwmac { -+ struct device *dev; -+ struct clk *clk_tx; -+ struct clk *clk_gtx; -+ bool tx_use_rgmii_rxin_clk; -+}; -+ -+static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed) -+{ -+ struct starfive_dwmac *dwmac = priv; -+ unsigned long rate; -+ int err; -+ -+ /* Generally, the rgmii_tx clock is provided by the internal clock, -+ * which needs to match the corresponding clock frequency according -+ * to different speeds. If the rgmii_tx clock is provided by the -+ * external rgmii_rxin, there is no need to configure the clock -+ * internally, because rgmii_rxin will be adaptively adjusted. -+ */ -+ if (dwmac->tx_use_rgmii_rxin_clk) -+ return; -+ -+ switch (speed) { -+ case SPEED_1000: -+ rate = 125000000; -+ break; -+ case SPEED_100: -+ rate = 25000000; -+ break; -+ case SPEED_10: -+ rate = 2500000; -+ break; -+ default: -+ dev_err(dwmac->dev, "invalid speed %u\n", speed); -+ break; -+ } -+ -+ err = clk_set_rate(dwmac->clk_tx, rate); -+ if (err) -+ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); -+} -+ -+static int starfive_dwmac_probe(struct platform_device *pdev) -+{ -+ struct plat_stmmacenet_data *plat_dat; -+ struct stmmac_resources stmmac_res; -+ struct starfive_dwmac *dwmac; -+ int err; -+ -+ err = stmmac_get_platform_resources(pdev, &stmmac_res); -+ if (err) -+ return err; -+ -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); -+ if (IS_ERR(plat_dat)) { -+ dev_err(&pdev->dev, "dt configuration failed\n"); -+ return PTR_ERR(plat_dat); -+ } -+ -+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); -+ if (!dwmac) -+ return -ENOMEM; -+ -+ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); -+ if (IS_ERR(dwmac->clk_tx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx), -+ "error getting tx clock\n"); -+ -+ dwmac->clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx"); -+ if (IS_ERR(dwmac->clk_gtx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtx), -+ "error getting gtx clock\n"); -+ -+ if (device_property_read_bool(&pdev->dev, "starfive,tx-use-rgmii-clk")) -+ dwmac->tx_use_rgmii_rxin_clk = true; -+ -+ dwmac->dev = &pdev->dev; -+ plat_dat->fix_mac_speed = starfive_eth_fix_mac_speed; -+ plat_dat->init = NULL; -+ plat_dat->bsp_priv = dwmac; -+ plat_dat->dma_cfg->dche = true; -+ -+ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); -+ if (err) { -+ stmmac_remove_config_dt(pdev, plat_dat); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id starfive_dwmac_match[] = { -+ { .compatible = "starfive,jh7110-dwmac" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, starfive_dwmac_match); -+ -+static struct platform_driver starfive_dwmac_driver = { -+ .probe = starfive_dwmac_probe, -+ .remove = stmmac_pltfr_remove, -+ .driver = { -+ .name = "starfive-dwmac", -+ .pm = &stmmac_pltfr_pm_ops, -+ .of_match_table = starfive_dwmac_match, -+ }, -+}; -+module_platform_driver(starfive_dwmac_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("StarFive DWMAC platform driver"); -+MODULE_AUTHOR("Emil Renner Berthing "); -+MODULE_AUTHOR("Samin Guo "); --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch b/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch deleted file mode 100644 index 2d76a47560ad0..0000000000000 --- a/srcpkgs/linux6.2/patches/0056-dt-bindings-net-starfive-jh7110-dwmac-Add-starfive-s.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 8d53004571daa30044aa83b0fa806762ea628b1b Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:23 +0800 -Subject: [PATCH 56/70] dt-bindings: net: starfive,jh7110-dwmac: Add - starfive,syscon - -A phandle to syscon with two arguments that configure phy mode. - -Signed-off-by: Samin Guo ---- - .../bindings/net/starfive,jh7110-dwmac.yaml | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml -index eb0767da834a..cd313ca8b8cf 100644 ---- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml -+++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml -@@ -54,6 +54,18 @@ properties: - - const: stmmaceth - - const: ahb - -+ starfive,syscon: -+ $ref: /schemas/types.yaml#/definitions/phandle-array -+ items: -+ - items: -+ - description: phandle to syscon that configures phy mode -+ - description: Offset of phy mode selection -+ - description: Mask of phy mode selection -+ description: -+ A phandle to syscon with two arguments that configure phy mode. -+ The argument one is the offset of phy mode selection, the -+ argument two is the mask of phy mode selection. -+ - allOf: - - $ref: snps,dwmac.yaml# - -@@ -92,6 +104,7 @@ examples: - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; -+ starfive,syscon = <&aon_syscon 0xc 0x1c0000>; - phy-handle = <&phy0>; - - mdio { --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch b/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch deleted file mode 100644 index 3d60456065665..0000000000000 --- a/srcpkgs/linux6.2/patches/0057-net-stmmac-starfive_dmac-Add-phy-interface-settings.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 7fe07e3a0d81babf67672ef428756c3098f12a22 Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:24 +0800 -Subject: [PATCH 57/70] net: stmmac: starfive_dmac: Add phy interface settings - -dwmac supports multiple modess. When working under rmii and rgmii, -you need to set different phy interfaces. - -According to the dwmac document, when working in rmii, it needs to be -set to 0x4, and rgmii needs to be set to 0x1. - -The phy interface needs to be set in syscon, the format is as follows: -starfive,syscon: <&syscon, offset, mask> - -Signed-off-by: Samin Guo ---- - .../ethernet/stmicro/stmmac/dwmac-starfive.c | 46 +++++++++++++++++++ - 1 file changed, 46 insertions(+) - -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c -index 566378306f67..40fdd7036127 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c -@@ -7,10 +7,15 @@ - * - */ - -+#include - #include -+#include - - #include "stmmac_platform.h" - -+#define MACPHYC_PHY_INFT_RMII 0x4 -+#define MACPHYC_PHY_INFT_RGMII 0x1 -+ - struct starfive_dwmac { - struct device *dev; - struct clk *clk_tx; -@@ -53,6 +58,46 @@ static void starfive_eth_fix_mac_speed(void *priv, unsigned int speed) - dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); - } - -+static int starfive_dwmac_set_mode(struct plat_stmmacenet_data *plat_dat) -+{ -+ struct starfive_dwmac *dwmac = plat_dat->bsp_priv; -+ struct of_phandle_args args; -+ struct regmap *regmap; -+ unsigned int reg, mask, mode; -+ int err; -+ -+ switch (plat_dat->interface) { -+ case PHY_INTERFACE_MODE_RMII: -+ mode = MACPHYC_PHY_INFT_RMII; -+ break; -+ -+ case PHY_INTERFACE_MODE_RGMII: -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ mode = MACPHYC_PHY_INFT_RGMII; -+ break; -+ -+ default: -+ dev_err(dwmac->dev, "Unsupported interface %d\n", -+ plat_dat->interface); -+ } -+ -+ err = of_parse_phandle_with_fixed_args(dwmac->dev->of_node, -+ "starfive,syscon", 2, 0, &args); -+ if (err) { -+ dev_dbg(dwmac->dev, "syscon reg not found\n"); -+ return -EINVAL; -+ } -+ -+ reg = args.args[0]; -+ mask = args.args[1]; -+ regmap = syscon_node_to_regmap(args.np); -+ of_node_put(args.np); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ return regmap_update_bits(regmap, reg, mask, mode << __ffs(mask)); -+} -+ - static int starfive_dwmac_probe(struct platform_device *pdev) - { - struct plat_stmmacenet_data *plat_dat; -@@ -93,6 +138,7 @@ static int starfive_dwmac_probe(struct platform_device *pdev) - plat_dat->bsp_priv = dwmac; - plat_dat->dma_cfg->dche = true; - -+ starfive_dwmac_set_mode(plat_dat); - err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); - if (err) { - stmmac_remove_config_dt(pdev, plat_dat); --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch b/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch deleted file mode 100644 index 54ff01a2b5c83..0000000000000 --- a/srcpkgs/linux6.2/patches/0058-riscv-dts-starfive-jh7110-Add-syscon-to-support-phy-.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 7a0bac9436e69b30f5b3aaadf8d2ad87d8d04559 Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:25 +0800 -Subject: [PATCH 58/70] riscv: dts: starfive: jh7110: Add syscon to support phy - interface settings - -The phy interface needs to be set in syscon, the format is as follows: -starfive,syscon: <&syscon, offset, mask> - -Signed-off-by: Samin Guo ---- - arch/riscv/boot/dts/starfive/jh7110.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi -index b0e87198808a..8b73d01c226c 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi -@@ -694,6 +694,7 @@ gmac0: ethernet@16030000 { - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; -+ starfive,syscon = <&aon_syscon 0xc 0x1c0000>; - status = "disabled"; - phy-handle = <&phy0>; - -@@ -736,6 +737,7 @@ gmac1: ethernet@16040000 { - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; -+ starfive,syscon = <&sys_syscon 0x90 0x1c>; - status = "disabled"; - phy-handle = <&phy1>; - --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch b/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch deleted file mode 100644 index bb87c6f17bdf6..0000000000000 --- a/srcpkgs/linux6.2/patches/0059-riscv-dts-starfive-visionfive-2-v1.3b-Add-gmac-phy-s.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 11f9513b0475fc7c841a4f50ea15207a90e45940 Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:26 +0800 -Subject: [PATCH 59/70] riscv: dts: starfive: visionfive-2-v1.3b: Add - gmac+phy's delay configuration - -v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and -inverse configurations. - -The tx_clk of v1.3B uses an external clock and needs to be -switched to an external clock source. - -Signed-off-by: Samin Guo ---- - .../jh7110-starfive-visionfive-2-v1.3b.dts | 27 +++++++++++++++++++ - 1 file changed, 27 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -index 9230cc3d8946..32fae0de9a44 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts -@@ -11,3 +11,30 @@ / { - model = "StarFive VisionFive 2 v1.3B"; - compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; - }; -+ -+&gmac0 { -+ starfive,tx-use-rgmii-clk; -+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; -+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; -+}; -+ -+&gmac1 { -+ starfive,tx-use-rgmii-clk; -+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; -+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; -+}; -+ -+&phy0 { -+ motorcomm,tx-clk-adj-enabled; -+ motorcomm,tx-clk-100-inverted; -+ motorcomm,tx-clk-1000-inverted; -+ rx-internal-delay-ps = <1900>; -+ tx-internal-delay-ps = <1500>; -+}; -+ -+&phy1 { -+ motorcomm,tx-clk-adj-enabled; -+ motorcomm,tx-clk-100-inverted; -+ rx-internal-delay-ps = <0>; -+ tx-internal-delay-ps = <0>; -+}; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch b/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch deleted file mode 100644 index d24341f8a476c..0000000000000 --- a/srcpkgs/linux6.2/patches/0060-riscv-dts-starfive-visionfive-2-v1.2a-Add-gmac-phy-s.patch +++ /dev/null @@ -1,41 +0,0 @@ -From de94625d0b77c717ce794a80c41541bb95b0d21b Mon Sep 17 00:00:00 2001 -From: Samin Guo -Date: Fri, 3 Mar 2023 16:59:27 +0800 -Subject: [PATCH 60/70] riscv: dts: starfive: visionfive-2-v1.2a: Add - gmac+phy's delay configuration - -v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay -configurations. - -v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to -switch rx and rx to external clock sources. - -Signed-off-by: Samin Guo ---- - .../starfive/jh7110-starfive-visionfive-2-v1.2a.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts -index 4af3300f3cf3..205a13d8c8b1 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts -@@ -11,3 +11,16 @@ / { - model = "StarFive VisionFive 2 v1.2A"; - compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; - }; -+ -+&gmac1 { -+ phy-mode = "rmii"; -+ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, -+ <&syscrg JH7110_SYSCLK_GMAC1_RX>; -+ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, -+ <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; -+}; -+ -+&phy0 { -+ rx-internal-delay-ps = <1900>; -+ tx-internal-delay-ps = <1350>; -+}; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch b/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch deleted file mode 100644 index 9591d052c9247..0000000000000 --- a/srcpkgs/linux6.2/patches/0061-riscv-dts-starfive-visionfive-2-Enable-gmac-device-t.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 868c93e6035b1a511fe1d105d88b86d66bd5a2b2 Mon Sep 17 00:00:00 2001 -From: Yanhong Wang -Date: Fri, 3 Mar 2023 16:59:28 +0800 -Subject: [PATCH 61/70] riscv: dts: starfive: visionfive 2: Enable gmac device - tree node - -Update gmac device tree node status to okay. - -Signed-off-by: Yanhong Wang -Signed-off-by: Samin Guo ---- - .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - -diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -index 295af73b0d08..3c3dc2a94ff6 100644 ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -12,6 +12,8 @@ - / { - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c5 = &i2c5; -@@ -123,6 +125,14 @@ &uart0 { - status = "okay"; - }; - -+&gmac0 { -+ status = "okay"; -+}; -+ -+&gmac1 { -+ status = "okay"; -+}; -+ - &i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch b/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch deleted file mode 100644 index 00c0877d5fe03..0000000000000 --- a/srcpkgs/linux6.2/patches/0062-dt-bindings-net-Add-support-StarFive-dwmac.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 9345758b8ec31007bd2ce6f116c0154b3f0c1c5c Mon Sep 17 00:00:00 2001 -From: Yanhong Wang -Date: Wed, 18 Jan 2023 14:16:58 +0800 -Subject: [PATCH 62/70] dt-bindings: net: Add support StarFive dwmac - -Add documentation to describe StarFive dwmac driver(GMAC). - -Signed-off-by: Yanhong Wang ---- - MAINTAINERS | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/MAINTAINERS b/MAINTAINERS -index 8ff112156e1f..b27451ff95eb 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -19977,6 +19977,11 @@ F: Documentation/devicetree/bindings/power/starfive* - F: drivers/soc/starfive/jh71xx_pmu.c - F: include/dt-bindings/power/starfive,jh7110-pmu.h - -+STARFIVE DWMAC GLUE LAYER -+M: Yanhong Wang -+S: Maintained -+F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml -+ - STATIC BRANCH/CALL - M: Peter Zijlstra - M: Josh Poimboeuf --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch b/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch deleted file mode 100644 index 600b9c816525a..0000000000000 --- a/srcpkgs/linux6.2/patches/0063-net-stmmac-Add-glue-layer-for-StarFive-JH7110-SoCs.patch +++ /dev/null @@ -1,192 +0,0 @@ -From 1b5b040a5eaec091fd46b64459d4828971b17b66 Mon Sep 17 00:00:00 2001 -From: Yanhong Wang -Date: Wed, 18 Jan 2023 14:16:59 +0800 -Subject: [PATCH 63/70] net: stmmac: Add glue layer for StarFive JH7110 SoCs - -This adds StarFive dwmac driver support on the StarFive JH7110 SoCs. - -Signed-off-by: Yanhong Wang -Co-developed-by: Emil Renner Berthing -Signed-off-by: Emil Renner Berthing ---- - MAINTAINERS | 1 + - drivers/net/ethernet/stmicro/stmmac/Kconfig | 12 ++ - drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + - .../stmicro/stmmac/dwmac-starfive-plat.c | 118 ++++++++++++++++++ - 4 files changed, 132 insertions(+) - create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c - -diff --git a/MAINTAINERS b/MAINTAINERS -index b27451ff95eb..bed2c33be517 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -19980,6 +19980,7 @@ F: include/dt-bindings/power/starfive,jh7110-pmu.h - STARFIVE DWMAC GLUE LAYER - M: Yanhong Wang - S: Maintained -+F: Documentation/devicetree/bindings/net/dwmac-starfive-plat.c - F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml - - STATIC BRANCH/CALL -diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig -index 47fbccef9d04..99f6716d6dc9 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Kconfig -+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig -@@ -256,6 +256,18 @@ config DWMAC_TEGRA - layer on top of the stmmac driver required for these NVIDIA Tegra SoC - devices. - -+config DWMAC_STARFIVE_PLAT -+ tristate "StarFive dwmac support" -+ depends on OF && COMMON_CLK -+ depends on STMMAC_ETH -+ default SOC_STARFIVE -+ help -+ Support for ethernet controllers on StarFive RISC-V SoCs -+ -+ This selects the StarFive platform specific glue layer support for -+ the stmmac device driver. This driver is used for StarFive JH7110 -+ ethernet controller. -+ - config DWMAC_VISCONTI - tristate "Toshiba Visconti DWMAC support" - default ARCH_VISCONTI -diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile -index 8738fdbb4b2d..576d9c5f7954 100644 ---- a/drivers/net/ethernet/stmicro/stmmac/Makefile -+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -32,6 +32,7 @@ obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o - obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o - obj-$(CONFIG_DWMAC_GENERIC) += dwmac-generic.o - obj-$(CONFIG_DWMAC_IMX8) += dwmac-imx.o -+obj-$(CONFIG_DWMAC_STARFIVE_PLAT) += dwmac-starfive-plat.o - obj-$(CONFIG_DWMAC_TEGRA) += dwmac-tegra.o - obj-$(CONFIG_DWMAC_VISCONTI) += dwmac-visconti.o - stmmac-platform-objs:= stmmac_platform.o -diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c -new file mode 100644 -index 000000000000..e441d920933a ---- /dev/null -+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-starfive-plat.c -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * StarFive DWMAC platform driver -+ * -+ * Copyright(C) 2022 StarFive Technology Co., Ltd. -+ * -+ */ -+ -+#include -+ -+#include "stmmac_platform.h" -+ -+struct starfive_dwmac { -+ struct device *dev; -+ struct clk *clk_tx; -+ struct clk *clk_gtx; -+ struct clk *clk_gtxc; -+}; -+ -+static void starfive_eth_plat_fix_mac_speed(void *priv, unsigned int speed) -+{ -+ struct starfive_dwmac *dwmac = priv; -+ unsigned long rate; -+ int err; -+ -+ rate = clk_get_rate(dwmac->clk_gtx); -+ -+ switch (speed) { -+ case SPEED_1000: -+ rate = 125000000; -+ break; -+ case SPEED_100: -+ rate = 25000000; -+ break; -+ case SPEED_10: -+ rate = 2500000; -+ break; -+ default: -+ dev_err(dwmac->dev, "invalid speed %u\n", speed); -+ break; -+ } -+ -+ err = clk_set_rate(dwmac->clk_gtx, rate); -+ if (err) -+ dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate); -+} -+ -+static int starfive_eth_plat_probe(struct platform_device *pdev) -+{ -+ struct plat_stmmacenet_data *plat_dat; -+ struct stmmac_resources stmmac_res; -+ struct starfive_dwmac *dwmac; -+ int err; -+ -+ err = stmmac_get_platform_resources(pdev, &stmmac_res); -+ if (err) -+ return err; -+ -+ plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); -+ if (IS_ERR(plat_dat)) { -+ dev_err(&pdev->dev, "dt configuration failed\n"); -+ return PTR_ERR(plat_dat); -+ } -+ -+ dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); -+ if (!dwmac) -+ return -ENOMEM; -+ -+ dwmac->clk_tx = devm_clk_get_enabled(&pdev->dev, "tx"); -+ if (IS_ERR(dwmac->clk_tx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_tx), -+ "error getting tx clock\n"); -+ -+ dwmac->clk_gtx = devm_clk_get_enabled(&pdev->dev, "gtx"); -+ if (IS_ERR(dwmac->clk_gtx)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtx), -+ "error getting gtx clock\n"); -+ -+ dwmac->clk_gtxc = devm_clk_get_enabled(&pdev->dev, "gtxc"); -+ if (IS_ERR(dwmac->clk_gtxc)) -+ return dev_err_probe(&pdev->dev, PTR_ERR(dwmac->clk_gtxc), -+ "error getting gtxc clock\n"); -+ -+ dwmac->dev = &pdev->dev; -+ plat_dat->fix_mac_speed = starfive_eth_plat_fix_mac_speed; -+ plat_dat->init = NULL; -+ plat_dat->bsp_priv = dwmac; -+ plat_dat->dma_cfg->dche = true; -+ -+ err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); -+ if (err) { -+ stmmac_remove_config_dt(pdev, plat_dat); -+ return err; -+ } -+ -+ return 0; -+} -+ -+static const struct of_device_id starfive_eth_plat_match[] = { -+ { .compatible = "starfive,jh7110-dwmac" }, -+ { } -+}; -+ -+static struct platform_driver starfive_eth_plat_driver = { -+ .probe = starfive_eth_plat_probe, -+ .remove = stmmac_pltfr_remove, -+ .driver = { -+ .name = "starfive-eth-plat", -+ .pm = &stmmac_pltfr_pm_ops, -+ .of_match_table = starfive_eth_plat_match, -+ }, -+}; -+ -+module_platform_driver(starfive_eth_plat_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("StarFive DWMAC platform driver"); -+MODULE_AUTHOR("Yanhong Wang "); --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch b/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch deleted file mode 100644 index 781747a9c5284..0000000000000 --- a/srcpkgs/linux6.2/patches/0064-dt-bindings-net-Add-Motorcomm-yt8xxx-ethernet-phy.patch +++ /dev/null @@ -1,167 +0,0 @@ -From 3365b5995c6b24ce6fe25cc705b864936a19b3bc Mon Sep 17 00:00:00 2001 -From: Frank Sae -Date: Thu, 2 Feb 2023 11:00:33 +0800 -Subject: [PATCH 64/70] dt-bindings: net: Add Motorcomm yt8xxx ethernet phy - -Add a YAML binding document for the Motorcomm yt8xxx Ethernet phy. - -Signed-off-by: Frank Sae -Reviewed-by: Rob Herring ---- - .../bindings/net/motorcomm,yt8xxx.yaml | 117 ++++++++++++++++++ - .../devicetree/bindings/vendor-prefixes.yaml | 2 + - MAINTAINERS | 1 + - 3 files changed, 120 insertions(+) - create mode 100644 Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml - -diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml -new file mode 100644 -index 000000000000..157e3bbcaf6f ---- /dev/null -+++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml -@@ -0,0 +1,117 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/net/motorcomm,yt8xxx.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: MotorComm yt8xxx Ethernet PHY -+ -+maintainers: -+ - Frank Sae -+ -+allOf: -+ - $ref: ethernet-phy.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - ethernet-phy-id4f51.e91a -+ - ethernet-phy-id4f51.e91b -+ -+ rx-internal-delay-ps: -+ description: | -+ RGMII RX Clock Delay used only when PHY operates in RGMII mode with -+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds. -+ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, -+ 1800, 1900, 1950, 2050, 2100, 2200, 2250, 2350, 2500, 2650, 2800, -+ 2950, 3100, 3250, 3400, 3550, 3700, 3850, 4000, 4150 ] -+ default: 1950 -+ -+ tx-internal-delay-ps: -+ description: | -+ RGMII TX Clock Delay used only when PHY operates in RGMII mode with -+ internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds. -+ enum: [ 0, 150, 300, 450, 600, 750, 900, 1050, 1200, 1350, 1500, 1650, 1800, -+ 1950, 2100, 2250 ] -+ default: 1950 -+ -+ motorcomm,clk-out-frequency-hz: -+ description: clock output on clock output pin. -+ enum: [0, 25000000, 125000000] -+ default: 0 -+ -+ motorcomm,keep-pll-enabled: -+ description: | -+ If set, keep the PLL enabled even if there is no link. Useful if you -+ want to use the clock output without an ethernet link. -+ type: boolean -+ -+ motorcomm,auto-sleep-disabled: -+ description: | -+ If set, PHY will not enter sleep mode and close AFE after unplug cable -+ for a timer. -+ type: boolean -+ -+ motorcomm,tx-clk-adj-enabled: -+ description: | -+ This configuration is mainly to adapt to VF2 with JH7110 SoC. -+ Useful if you want to use tx-clk-xxxx-inverted to adj the delay of tx clk. -+ type: boolean -+ -+ motorcomm,tx-clk-10-inverted: -+ description: | -+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII -+ Transmit PHY Clock delay train configuration when speed is 10Mbps. -+ type: boolean -+ -+ motorcomm,tx-clk-100-inverted: -+ description: | -+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII -+ Transmit PHY Clock delay train configuration when speed is 100Mbps. -+ type: boolean -+ -+ motorcomm,tx-clk-1000-inverted: -+ description: | -+ Use original or inverted RGMII Transmit PHY Clock to drive the RGMII -+ Transmit PHY Clock delay train configuration when speed is 1000Mbps. -+ type: boolean -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ phy-mode = "rgmii-id"; -+ ethernet-phy@4 { -+ /* Only needed to make DT lint tools work. Do not copy/paste -+ * into real DTS files. -+ */ -+ compatible = "ethernet-phy-id4f51.e91a"; -+ -+ reg = <4>; -+ rx-internal-delay-ps = <2100>; -+ tx-internal-delay-ps = <150>; -+ motorcomm,clk-out-frequency-hz = <0>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ }; -+ }; -+ - | -+ mdio { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ phy-mode = "rgmii"; -+ ethernet-phy@5 { -+ /* Only needed to make DT lint tools work. Do not copy/paste -+ * into real DTS files. -+ */ -+ compatible = "ethernet-phy-id4f51.e91a"; -+ -+ reg = <5>; -+ motorcomm,clk-out-frequency-hz = <125000000>; -+ motorcomm,keep-pll-enabled; -+ motorcomm,auto-sleep-disabled; -+ }; -+ }; -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 70ffb3780621..8d19157e85b7 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -845,6 +845,8 @@ patternProperties: - description: Moortec Semiconductor Ltd. - "^mosaixtech,.*": - description: Mosaix Technologies, Inc. -+ "^motorcomm,.*": -+ description: MotorComm, Inc. - "^motorola,.*": - description: Motorola, Inc. - "^moxa,.*": -diff --git a/MAINTAINERS b/MAINTAINERS -index bed2c33be517..7c73cdbe1259 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -14169,6 +14169,7 @@ M: Peter Geis - M: Frank - L: netdev@vger.kernel.org - S: Maintained -+F: Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml - F: drivers/net/phy/motorcomm.c - - MOXA SMARTIO/INDUSTIO/INTELLIO SERIAL CARD --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch b/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch deleted file mode 100644 index afd296f9f2f93..0000000000000 --- a/srcpkgs/linux6.2/patches/0065-net-phy-Add-BIT-macro-for-Motorcomm-yt8521-yt8531-gi.patch +++ /dev/null @@ -1,111 +0,0 @@ -From 5e416205a846fef3174ebe0509f6a4926e947580 Mon Sep 17 00:00:00 2001 -From: Frank Sae -Date: Thu, 2 Feb 2023 11:00:34 +0800 -Subject: [PATCH 65/70] net: phy: Add BIT macro for Motorcomm yt8521/yt8531 - gigabit ethernet phy - -Add BIT macro for Motorcomm yt8521/yt8531 gigabit ethernet phy. - This is a preparatory patch. Add BIT macro for 0xA012 reg, and - supplement for 0xA001 and 0xA003 reg. These will be used to support dts. - -Signed-off-by: Frank Sae -Reviewed-by: Andrew Lunn ---- - drivers/net/phy/motorcomm.c | 55 ++++++++++++++++++++++++++++++++++--- - 1 file changed, 51 insertions(+), 4 deletions(-) - -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -index 685190db72de..d8523e33424d 100644 ---- a/drivers/net/phy/motorcomm.c -+++ b/drivers/net/phy/motorcomm.c -@@ -161,6 +161,11 @@ - - #define YT8521_CHIP_CONFIG_REG 0xA001 - #define YT8521_CCR_SW_RST BIT(15) -+/* 1b0 disable 1.9ns rxc clock delay *default* -+ * 1b1 enable 1.9ns rxc clock delay -+ */ -+#define YT8521_CCR_RXC_DLY_EN BIT(8) -+#define YT8521_CCR_RXC_DLY_1_900_NS 1900 - - #define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) - #define YT8521_CCR_MODE_UTP_TO_RGMII 0 -@@ -178,22 +183,41 @@ - #define YT8521_MODE_POLL 0x3 - - #define YT8521_RGMII_CONFIG1_REG 0xA003 -- -+/* 1b0 use original tx_clk_rgmii *default* -+ * 1b1 use inverted tx_clk_rgmii. -+ */ -+#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) - /* TX Gig-E Delay is bits 3:0, default 0x1 - * TX Fast-E Delay is bits 7:4, default 0xf - * RX Delay is bits 13:10, default 0x0 - * Delay = 150ps * N - * On = 2250ps, off = 0ps - */ --#define YT8521_RC1R_RX_DELAY_MASK (0xF << 10) -+#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) - #define YT8521_RC1R_RX_DELAY_EN (0xF << 10) - #define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) --#define YT8521_RC1R_FE_TX_DELAY_MASK (0xF << 4) -+#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) - #define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) - #define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) --#define YT8521_RC1R_GE_TX_DELAY_MASK (0xF << 0) -+#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) - #define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) - #define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) -+#define YT8521_RC1R_RGMII_0_000_NS 0 -+#define YT8521_RC1R_RGMII_0_150_NS 1 -+#define YT8521_RC1R_RGMII_0_300_NS 2 -+#define YT8521_RC1R_RGMII_0_450_NS 3 -+#define YT8521_RC1R_RGMII_0_600_NS 4 -+#define YT8521_RC1R_RGMII_0_750_NS 5 -+#define YT8521_RC1R_RGMII_0_900_NS 6 -+#define YT8521_RC1R_RGMII_1_050_NS 7 -+#define YT8521_RC1R_RGMII_1_200_NS 8 -+#define YT8521_RC1R_RGMII_1_350_NS 9 -+#define YT8521_RC1R_RGMII_1_500_NS 10 -+#define YT8521_RC1R_RGMII_1_650_NS 11 -+#define YT8521_RC1R_RGMII_1_800_NS 12 -+#define YT8521_RC1R_RGMII_1_950_NS 13 -+#define YT8521_RC1R_RGMII_2_100_NS 14 -+#define YT8521_RC1R_RGMII_2_250_NS 15 - - #define YTPHY_MISC_CONFIG_REG 0xA006 - #define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) -@@ -222,6 +246,29 @@ - */ - #define YTPHY_WCR_TYPE_PULSE BIT(0) - -+#define YTPHY_SYNCE_CFG_REG 0xA012 -+#define YT8521_SCR_SYNCE_ENABLE BIT(5) -+/* 1b0 output 25m clock -+ * 1b1 output 125m clock *default* -+ */ -+#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) -+#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) -+#define YT8521_SCR_CLK_SRC_PLL_125M 0 -+#define YT8521_SCR_CLK_SRC_UTP_RX 1 -+#define YT8521_SCR_CLK_SRC_SDS_RX 2 -+#define YT8521_SCR_CLK_SRC_REF_25M 3 -+#define YT8531_SCR_SYNCE_ENABLE BIT(6) -+/* 1b0 output 25m clock *default* -+ * 1b1 output 125m clock -+ */ -+#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) -+#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) -+#define YT8531_SCR_CLK_SRC_PLL_125M 0 -+#define YT8531_SCR_CLK_SRC_UTP_RX 1 -+#define YT8531_SCR_CLK_SRC_SDS_RX 2 -+#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 -+#define YT8531_SCR_CLK_SRC_REF_25M 4 -+#define YT8531_SCR_CLK_SRC_SSC_25M 5 - #define YT8531S_SYNCE_CFG_REG 0xA012 - #define YT8531S_SCR_SYNCE_ENABLE BIT(6) - --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch b/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch deleted file mode 100644 index 206cedbcbd23e..0000000000000 --- a/srcpkgs/linux6.2/patches/0066-net-phy-Add-dts-support-for-Motorcomm-yt8521-gigabit.patch +++ /dev/null @@ -1,347 +0,0 @@ -From 1dd58db7f1ce60c13771a32d553be80112962600 Mon Sep 17 00:00:00 2001 -From: Frank Sae -Date: Thu, 2 Feb 2023 11:00:35 +0800 -Subject: [PATCH 66/70] net: phy: Add dts support for Motorcomm yt8521 gigabit - ethernet phy - -Add dts support for Motorcomm yt8521 gigabit ethernet phy. - Add ytphy_rgmii_clk_delay_config function to support dst config for - the delay of rgmii clk. This funciont is common for yt8521, yt8531s - and yt8531. - This patch has been verified on AM335x platform. - -Signed-off-by: Frank Sae -Reviewed-by: Andrew Lunn ---- - drivers/net/phy/motorcomm.c | 253 ++++++++++++++++++++++++++++-------- - 1 file changed, 199 insertions(+), 54 deletions(-) - -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -index d8523e33424d..fc06fe6ef9ba 100644 ---- a/drivers/net/phy/motorcomm.c -+++ b/drivers/net/phy/motorcomm.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - - #define PHY_ID_YT8511 0x0000010a - #define PHY_ID_YT8521 0x0000011A -@@ -187,21 +188,9 @@ - * 1b1 use inverted tx_clk_rgmii. - */ - #define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) --/* TX Gig-E Delay is bits 3:0, default 0x1 -- * TX Fast-E Delay is bits 7:4, default 0xf -- * RX Delay is bits 13:10, default 0x0 -- * Delay = 150ps * N -- * On = 2250ps, off = 0ps -- */ - #define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) --#define YT8521_RC1R_RX_DELAY_EN (0xF << 10) --#define YT8521_RC1R_RX_DELAY_DIS (0x0 << 10) - #define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) --#define YT8521_RC1R_FE_TX_DELAY_EN (0xF << 4) --#define YT8521_RC1R_FE_TX_DELAY_DIS (0x0 << 4) - #define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) --#define YT8521_RC1R_GE_TX_DELAY_EN (0xF << 0) --#define YT8521_RC1R_GE_TX_DELAY_DIS (0x0 << 0) - #define YT8521_RC1R_RGMII_0_000_NS 0 - #define YT8521_RC1R_RGMII_0_150_NS 1 - #define YT8521_RC1R_RGMII_0_300_NS 2 -@@ -274,6 +263,10 @@ - - /* Extended Register end */ - -+#define YTPHY_DTS_OUTPUT_CLK_DIS 0 -+#define YTPHY_DTS_OUTPUT_CLK_25M 25000000 -+#define YTPHY_DTS_OUTPUT_CLK_125M 125000000 -+ - struct yt8521_priv { - /* combo_advertising is used for case of YT8521 in combo mode, - * this means that yt8521 may work in utp or fiber mode which depends -@@ -640,6 +633,142 @@ static int yt8521_write_page(struct phy_device *phydev, int page) - return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); - }; - -+/** -+ * struct ytphy_cfg_reg_map - map a config value to a register value -+ * @cfg: value in device configuration -+ * @reg: value in the register -+ */ -+struct ytphy_cfg_reg_map { -+ u32 cfg; -+ u32 reg; -+}; -+ -+static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { -+ /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ -+ { 0, YT8521_RC1R_RGMII_0_000_NS }, -+ { 150, YT8521_RC1R_RGMII_0_150_NS }, -+ { 300, YT8521_RC1R_RGMII_0_300_NS }, -+ { 450, YT8521_RC1R_RGMII_0_450_NS }, -+ { 600, YT8521_RC1R_RGMII_0_600_NS }, -+ { 750, YT8521_RC1R_RGMII_0_750_NS }, -+ { 900, YT8521_RC1R_RGMII_0_900_NS }, -+ { 1050, YT8521_RC1R_RGMII_1_050_NS }, -+ { 1200, YT8521_RC1R_RGMII_1_200_NS }, -+ { 1350, YT8521_RC1R_RGMII_1_350_NS }, -+ { 1500, YT8521_RC1R_RGMII_1_500_NS }, -+ { 1650, YT8521_RC1R_RGMII_1_650_NS }, -+ { 1800, YT8521_RC1R_RGMII_1_800_NS }, -+ { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ -+ { 2100, YT8521_RC1R_RGMII_2_100_NS }, -+ { 2250, YT8521_RC1R_RGMII_2_250_NS }, -+ -+ /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ -+ { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, -+ { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, -+ { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, -+ { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, -+ { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, -+ { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, -+ { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, -+ { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, -+ { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, -+ { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, -+ { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, -+ { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, -+ { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, -+ { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, -+ { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, -+ { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } -+}; -+ -+static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, -+ const char *prop_name, -+ const struct ytphy_cfg_reg_map *tbl, -+ int tb_size, -+ u16 *rxc_dly_en, -+ u32 dflt) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ int tb_size_half = tb_size / 2; -+ u32 val; -+ int i; -+ -+ if (of_property_read_u32(node, prop_name, &val)) -+ goto err_dts_val; -+ -+ /* when rxc_dly_en is NULL, it is get the delay for tx, only half of -+ * tb_size is valid. -+ */ -+ if (!rxc_dly_en) -+ tb_size = tb_size_half; -+ -+ for (i = 0; i < tb_size; i++) { -+ if (tbl[i].cfg == val) { -+ if (rxc_dly_en && i < tb_size_half) -+ *rxc_dly_en = 0; -+ return tbl[i].reg; -+ } -+ } -+ -+ phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", -+ val, prop_name, dflt); -+ -+err_dts_val: -+ /* when rxc_dly_en is not NULL, it is get the delay for rx. -+ * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, -+ * so YT8521_CCR_RXC_DLY_EN should not be set. -+ */ -+ if (rxc_dly_en) -+ *rxc_dly_en = 0; -+ -+ return dflt; -+} -+ -+static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) -+{ -+ int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); -+ u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; -+ u32 rx_reg, tx_reg; -+ u16 mask, val = 0; -+ int ret; -+ -+ rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", -+ ytphy_rgmii_delays, tb_size, -+ &rxc_dly_en, -+ YT8521_RC1R_RGMII_1_950_NS); -+ tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", -+ ytphy_rgmii_delays, tb_size, NULL, -+ YT8521_RC1R_RGMII_1_950_NS); -+ -+ switch (phydev->interface) { -+ case PHY_INTERFACE_MODE_RGMII: -+ rxc_dly_en = 0; -+ break; -+ case PHY_INTERFACE_MODE_RGMII_RXID: -+ val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); -+ break; -+ case PHY_INTERFACE_MODE_RGMII_TXID: -+ rxc_dly_en = 0; -+ val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); -+ break; -+ case PHY_INTERFACE_MODE_RGMII_ID: -+ val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | -+ FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); -+ break; -+ default: /* do not support other modes */ -+ return -EOPNOTSUPP; -+ } -+ -+ ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, -+ YT8521_CCR_RXC_DLY_EN, rxc_dly_en); -+ if (ret < 0) -+ return ret; -+ -+ /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ -+ mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; -+ return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); -+} -+ - /** - * yt8521_probe() - read chip config then set suitable polling_mode - * @phydev: a pointer to a &struct phy_device -@@ -648,9 +777,12 @@ static int yt8521_write_page(struct phy_device *phydev, int page) - */ - static int yt8521_probe(struct phy_device *phydev) - { -+ struct device_node *node = phydev->mdio.dev.of_node; - struct device *dev = &phydev->mdio.dev; - struct yt8521_priv *priv; - int chip_config; -+ u16 mask, val; -+ u32 freq; - int ret; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -@@ -695,7 +827,45 @@ static int yt8521_probe(struct phy_device *phydev) - return ret; - } - -- return 0; -+ if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) -+ freq = YTPHY_DTS_OUTPUT_CLK_DIS; -+ -+ if (phydev->drv->phy_id == PHY_ID_YT8521) { -+ switch (freq) { -+ case YTPHY_DTS_OUTPUT_CLK_DIS: -+ mask = YT8521_SCR_SYNCE_ENABLE; -+ val = 0; -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_25M: -+ mask = YT8521_SCR_SYNCE_ENABLE | -+ YT8521_SCR_CLK_SRC_MASK | -+ YT8521_SCR_CLK_FRE_SEL_125M; -+ val = YT8521_SCR_SYNCE_ENABLE | -+ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, -+ YT8521_SCR_CLK_SRC_REF_25M); -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_125M: -+ mask = YT8521_SCR_SYNCE_ENABLE | -+ YT8521_SCR_CLK_SRC_MASK | -+ YT8521_SCR_CLK_FRE_SEL_125M; -+ val = YT8521_SCR_SYNCE_ENABLE | -+ YT8521_SCR_CLK_FRE_SEL_125M | -+ FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, -+ YT8521_SCR_CLK_SRC_PLL_125M); -+ break; -+ default: -+ phydev_warn(phydev, "Freq err:%u\n", freq); -+ return -EINVAL; -+ } -+ } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { -+ return 0; -+ } else { -+ phydev_warn(phydev, "PHY id err\n"); -+ return -EINVAL; -+ } -+ -+ return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, -+ val); - } - - /** -@@ -1180,61 +1350,36 @@ static int yt8521_resume(struct phy_device *phydev) - */ - static int yt8521_config_init(struct phy_device *phydev) - { -+ struct device_node *node = phydev->mdio.dev.of_node; - int old_page; - int ret = 0; -- u16 val; - - old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); - if (old_page < 0) - goto err_restore_page; - -- switch (phydev->interface) { -- case PHY_INTERFACE_MODE_RGMII: -- val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; -- val |= YT8521_RC1R_RX_DELAY_DIS; -- break; -- case PHY_INTERFACE_MODE_RGMII_RXID: -- val = YT8521_RC1R_GE_TX_DELAY_DIS | YT8521_RC1R_FE_TX_DELAY_DIS; -- val |= YT8521_RC1R_RX_DELAY_EN; -- break; -- case PHY_INTERFACE_MODE_RGMII_TXID: -- val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; -- val |= YT8521_RC1R_RX_DELAY_DIS; -- break; -- case PHY_INTERFACE_MODE_RGMII_ID: -- val = YT8521_RC1R_GE_TX_DELAY_EN | YT8521_RC1R_FE_TX_DELAY_EN; -- val |= YT8521_RC1R_RX_DELAY_EN; -- break; -- case PHY_INTERFACE_MODE_SGMII: -- break; -- default: /* do not support other modes */ -- ret = -EOPNOTSUPP; -- goto err_restore_page; -- } -- - /* set rgmii delay mode */ - if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { -- ret = ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, -- (YT8521_RC1R_RX_DELAY_MASK | -- YT8521_RC1R_FE_TX_DELAY_MASK | -- YT8521_RC1R_GE_TX_DELAY_MASK), -- val); -+ ret = ytphy_rgmii_clk_delay_config(phydev); - if (ret < 0) - goto err_restore_page; - } - -- /* disable auto sleep */ -- ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, -- YT8521_ESC1R_SLEEP_SW, 0); -- if (ret < 0) -- goto err_restore_page; -- -- /* enable RXC clock when no wire plug */ -- ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, -- YT8521_CGR_RX_CLK_EN, 0); -- if (ret < 0) -- goto err_restore_page; -+ if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { -+ /* disable auto sleep */ -+ ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, -+ YT8521_ESC1R_SLEEP_SW, 0); -+ if (ret < 0) -+ goto err_restore_page; -+ } - -+ if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { -+ /* enable RXC clock when no wire plug */ -+ ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, -+ YT8521_CGR_RX_CLK_EN, 0); -+ if (ret < 0) -+ goto err_restore_page; -+ } - err_restore_page: - return phy_restore_page(phydev, old_page, ret); - } --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch b/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch deleted file mode 100644 index 2aac9aeb25fa3..0000000000000 --- a/srcpkgs/linux6.2/patches/0067-net-phy-Add-dts-support-for-Motorcomm-yt8531s-gigabi.patch +++ /dev/null @@ -1,104 +0,0 @@ -From 5d942efe006c8d22cf03be7c1423e37667560729 Mon Sep 17 00:00:00 2001 -From: Frank Sae -Date: Thu, 2 Feb 2023 11:00:36 +0800 -Subject: [PATCH 67/70] net: phy: Add dts support for Motorcomm yt8531s gigabit - ethernet phy - -Add dts support for Motorcomm yt8531s gigabit ethernet phy. - Change yt8521_probe to support clk config of yt8531s. Becase - yt8521_probe does the things which yt8531s is needed, so - removed yt8531s function. - This patch has been verified on AM335x platform with yt8531s board. - -Signed-off-by: Frank Sae -Reviewed-by: Andrew Lunn ---- - drivers/net/phy/motorcomm.c | 51 ++++++++++++++++++++----------------- - 1 file changed, 27 insertions(+), 24 deletions(-) - -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -index fc06fe6ef9ba..78392174536b 100644 ---- a/drivers/net/phy/motorcomm.c -+++ b/drivers/net/phy/motorcomm.c -@@ -258,8 +258,6 @@ - #define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 - #define YT8531_SCR_CLK_SRC_REF_25M 4 - #define YT8531_SCR_CLK_SRC_SSC_25M 5 --#define YT8531S_SYNCE_CFG_REG 0xA012 --#define YT8531S_SCR_SYNCE_ENABLE BIT(6) - - /* Extended Register end */ - -@@ -858,7 +856,32 @@ static int yt8521_probe(struct phy_device *phydev) - return -EINVAL; - } - } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { -- return 0; -+ switch (freq) { -+ case YTPHY_DTS_OUTPUT_CLK_DIS: -+ mask = YT8531_SCR_SYNCE_ENABLE; -+ val = 0; -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_25M: -+ mask = YT8531_SCR_SYNCE_ENABLE | -+ YT8531_SCR_CLK_SRC_MASK | -+ YT8531_SCR_CLK_FRE_SEL_125M; -+ val = YT8531_SCR_SYNCE_ENABLE | -+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, -+ YT8531_SCR_CLK_SRC_REF_25M); -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_125M: -+ mask = YT8531_SCR_SYNCE_ENABLE | -+ YT8531_SCR_CLK_SRC_MASK | -+ YT8531_SCR_CLK_FRE_SEL_125M; -+ val = YT8531_SCR_SYNCE_ENABLE | -+ YT8531_SCR_CLK_FRE_SEL_125M | -+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, -+ YT8531_SCR_CLK_SRC_PLL_125M); -+ break; -+ default: -+ phydev_warn(phydev, "Freq err:%u\n", freq); -+ return -EINVAL; -+ } - } else { - phydev_warn(phydev, "PHY id err\n"); - return -EINVAL; -@@ -868,26 +891,6 @@ static int yt8521_probe(struct phy_device *phydev) - val); - } - --/** -- * yt8531s_probe() - read chip config then set suitable polling_mode -- * @phydev: a pointer to a &struct phy_device -- * -- * returns 0 or negative errno code -- */ --static int yt8531s_probe(struct phy_device *phydev) --{ -- int ret; -- -- /* Disable SyncE clock output by default */ -- ret = ytphy_modify_ext_with_lock(phydev, YT8531S_SYNCE_CFG_REG, -- YT8531S_SCR_SYNCE_ENABLE, 0); -- if (ret < 0) -- return ret; -- -- /* same as yt8521_probe */ -- return yt8521_probe(phydev); --} -- - /** - * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp - * @phydev: a pointer to a &struct phy_device -@@ -1970,7 +1973,7 @@ static struct phy_driver motorcomm_phy_drvs[] = { - PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), - .name = "YT8531S Gigabit Ethernet", - .get_features = yt8521_get_features, -- .probe = yt8531s_probe, -+ .probe = yt8521_probe, - .read_page = yt8521_read_page, - .write_page = yt8521_write_page, - .get_wol = ytphy_get_wol, --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch b/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch deleted file mode 100644 index cd63e496448a9..0000000000000 --- a/srcpkgs/linux6.2/patches/0068-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethe.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 4067c531d9ed4ccab0d134fb64856a62ac9044cc Mon Sep 17 00:00:00 2001 -From: Frank Sae -Date: Thu, 2 Feb 2023 11:00:37 +0800 -Subject: [PATCH 68/70] net: phy: Add driver for Motorcomm yt8531 gigabit - ethernet phy - -Add a driver for the motorcomm yt8531 gigabit ethernet phy. We have - verified the driver on AM335x platform with yt8531 board. On the - board, yt8531 gigabit ethernet phy works in utp mode, RGMII - interface, supports 1000M/100M/10M speeds, and wol(magic package). - -Signed-off-by: Frank Sae -Reviewed-by: Andrew Lunn ---- - drivers/net/phy/Kconfig | 2 +- - drivers/net/phy/motorcomm.c | 208 +++++++++++++++++++++++++++++++++++- - 2 files changed, 207 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig -index 1327290decab..6bf557ed0c8e 100644 ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -257,7 +257,7 @@ config MOTORCOMM_PHY - tristate "Motorcomm PHYs" - help - Enables support for Motorcomm network PHYs. -- Currently supports the YT8511, YT8521, YT8531S Gigabit Ethernet PHYs. -+ Currently supports YT85xx Gigabit Ethernet PHYs. - - config NATIONAL_PHY - tristate "National Semiconductor PHYs" -diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c -index 78392174536b..3f96659cab8c 100644 ---- a/drivers/net/phy/motorcomm.c -+++ b/drivers/net/phy/motorcomm.c -@@ -1,6 +1,6 @@ - // SPDX-License-Identifier: GPL-2.0+ - /* -- * Motorcomm 8511/8521/8531S PHY driver. -+ * Motorcomm 8511/8521/8531/8531S PHY driver. - * - * Author: Peter Geis - * Author: Frank -@@ -14,6 +14,7 @@ - - #define PHY_ID_YT8511 0x0000010a - #define PHY_ID_YT8521 0x0000011A -+#define PHY_ID_YT8531 0x4F51E91B - #define PHY_ID_YT8531S 0x4F51E91A - - /* YT8521/YT8531S Register Overview -@@ -517,6 +518,61 @@ static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) - return phy_restore_page(phydev, old_page, ret); - } - -+static int yt8531_set_wol(struct phy_device *phydev, -+ struct ethtool_wolinfo *wol) -+{ -+ const u16 mac_addr_reg[] = { -+ YTPHY_WOL_MACADDR2_REG, -+ YTPHY_WOL_MACADDR1_REG, -+ YTPHY_WOL_MACADDR0_REG, -+ }; -+ const u8 *mac_addr; -+ u16 mask, val; -+ int ret; -+ u8 i; -+ -+ if (wol->wolopts & WAKE_MAGIC) { -+ mac_addr = phydev->attached_dev->dev_addr; -+ -+ /* Store the device address for the magic packet */ -+ for (i = 0; i < 3; i++) { -+ ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], -+ ((mac_addr[i * 2] << 8)) | -+ (mac_addr[i * 2 + 1])); -+ if (ret < 0) -+ return ret; -+ } -+ -+ /* Enable WOL feature */ -+ mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; -+ val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; -+ val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; -+ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, -+ mask, val); -+ if (ret < 0) -+ return ret; -+ -+ /* Enable WOL interrupt */ -+ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, -+ YTPHY_IER_WOL); -+ if (ret < 0) -+ return ret; -+ } else { -+ /* Disable WOL feature */ -+ mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; -+ ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, -+ mask, 0); -+ -+ /* Disable WOL interrupt */ -+ ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, -+ YTPHY_IER_WOL, 0); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ - static int yt8511_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, YT8511_PAGE_SELECT); -@@ -767,6 +823,17 @@ static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) - return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); - } - -+static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) -+{ -+ int ret; -+ -+ phy_lock_mdio_bus(phydev); -+ ret = ytphy_rgmii_clk_delay_config(phydev); -+ phy_unlock_mdio_bus(phydev); -+ -+ return ret; -+} -+ - /** - * yt8521_probe() - read chip config then set suitable polling_mode - * @phydev: a pointer to a &struct phy_device -@@ -891,6 +958,43 @@ static int yt8521_probe(struct phy_device *phydev) - val); - } - -+static int yt8531_probe(struct phy_device *phydev) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ u16 mask, val; -+ u32 freq; -+ -+ if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) -+ freq = YTPHY_DTS_OUTPUT_CLK_DIS; -+ -+ switch (freq) { -+ case YTPHY_DTS_OUTPUT_CLK_DIS: -+ mask = YT8531_SCR_SYNCE_ENABLE; -+ val = 0; -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_25M: -+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | -+ YT8531_SCR_CLK_FRE_SEL_125M; -+ val = YT8531_SCR_SYNCE_ENABLE | -+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, -+ YT8531_SCR_CLK_SRC_REF_25M); -+ break; -+ case YTPHY_DTS_OUTPUT_CLK_125M: -+ mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | -+ YT8531_SCR_CLK_FRE_SEL_125M; -+ val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | -+ FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, -+ YT8531_SCR_CLK_SRC_PLL_125M); -+ break; -+ default: -+ phydev_warn(phydev, "Freq err:%u\n", freq); -+ return -EINVAL; -+ } -+ -+ return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, -+ val); -+} -+ - /** - * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp - * @phydev: a pointer to a &struct phy_device -@@ -1387,6 +1491,94 @@ static int yt8521_config_init(struct phy_device *phydev) - return phy_restore_page(phydev, old_page, ret); - } - -+static int yt8531_config_init(struct phy_device *phydev) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ int ret; -+ -+ ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); -+ if (ret < 0) -+ return ret; -+ -+ if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { -+ /* disable auto sleep */ -+ ret = ytphy_modify_ext_with_lock(phydev, -+ YT8521_EXTREG_SLEEP_CONTROL1_REG, -+ YT8521_ESC1R_SLEEP_SW, 0); -+ if (ret < 0) -+ return ret; -+ } -+ -+ if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { -+ /* enable RXC clock when no wire plug */ -+ ret = ytphy_modify_ext_with_lock(phydev, -+ YT8521_CLOCK_GATING_REG, -+ YT8521_CGR_RX_CLK_EN, 0); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/** -+ * yt8531_link_change_notify() - Adjust the tx clock direction according to -+ * the current speed and dts config. -+ * @phydev: a pointer to a &struct phy_device -+ * -+ * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please -+ * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not -+ * JH7110. -+ */ -+static void yt8531_link_change_notify(struct phy_device *phydev) -+{ -+ struct device_node *node = phydev->mdio.dev.of_node; -+ bool tx_clk_adj_enabled = false; -+ bool tx_clk_1000_inverted; -+ bool tx_clk_100_inverted; -+ bool tx_clk_10_inverted; -+ u16 val = 0; -+ int ret; -+ -+ if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled")) -+ tx_clk_adj_enabled = true; -+ -+ if (!tx_clk_adj_enabled) -+ return; -+ -+ if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted")) -+ tx_clk_10_inverted = true; -+ if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted")) -+ tx_clk_100_inverted = true; -+ if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) -+ tx_clk_1000_inverted = true; -+ -+ if (phydev->speed < 0) -+ return; -+ -+ switch (phydev->speed) { -+ case SPEED_1000: -+ if (tx_clk_1000_inverted) -+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; -+ break; -+ case SPEED_100: -+ if (tx_clk_100_inverted) -+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; -+ break; -+ case SPEED_10: -+ if (tx_clk_10_inverted) -+ val = YT8521_RC1R_TX_CLK_SEL_INVERTED; -+ break; -+ default: -+ return; -+ } -+ -+ ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, -+ YT8521_RC1R_TX_CLK_SEL_INVERTED, val); -+ if (ret < 0) -+ phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); -+} -+ - /** - * yt8521_prepare_fiber_features() - A small helper function that setup - * fiber's features. -@@ -1969,6 +2161,17 @@ static struct phy_driver motorcomm_phy_drvs[] = { - .suspend = yt8521_suspend, - .resume = yt8521_resume, - }, -+ { -+ PHY_ID_MATCH_EXACT(PHY_ID_YT8531), -+ .name = "YT8531 Gigabit Ethernet", -+ .probe = yt8531_probe, -+ .config_init = yt8531_config_init, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .get_wol = ytphy_get_wol, -+ .set_wol = yt8531_set_wol, -+ .link_change_notify = yt8531_link_change_notify, -+ }, - { - PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), - .name = "YT8531S Gigabit Ethernet", -@@ -1990,7 +2193,7 @@ static struct phy_driver motorcomm_phy_drvs[] = { - - module_phy_driver(motorcomm_phy_drvs); - --MODULE_DESCRIPTION("Motorcomm 8511/8521/8531S PHY driver"); -+MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S PHY driver"); - MODULE_AUTHOR("Peter Geis"); - MODULE_AUTHOR("Frank"); - MODULE_LICENSE("GPL"); -@@ -1998,6 +2201,7 @@ MODULE_LICENSE("GPL"); - static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { - { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, - { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, -+ { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, - { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, - { /* sentinal */ } - }; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch b/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch deleted file mode 100644 index 1f9249bda2228..0000000000000 --- a/srcpkgs/linux6.2/patches/0069-dt-bindings-hwmon-Add-starfive-jh71x0-temp.patch +++ /dev/null @@ -1,95 +0,0 @@ -From 240b171ea0dc33255bf53da1ba07c02498acb9ad Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Mon, 27 Feb 2023 21:41:24 +0800 -Subject: [PATCH 69/70] dt-bindings: hwmon: Add starfive,jh71x0-temp - -Add bindings for the temperature sensor on the StarFive JH7100 and -JH7110 SoCs. - -Signed-off-by: Emil Renner Berthing -Signed-off-by: Hal Feng -Reviewed-by: Rob Herring ---- - .../bindings/hwmon/starfive,jh71x0-temp.yaml | 70 +++++++++++++++++++ - 1 file changed, 70 insertions(+) - create mode 100644 Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml - -diff --git a/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml -new file mode 100644 -index 000000000000..f5b34528928d ---- /dev/null -+++ b/Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml -@@ -0,0 +1,70 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: StarFive JH71x0 Temperature Sensor -+ -+maintainers: -+ - Emil Renner Berthing -+ -+description: | -+ StarFive Technology Co. JH71x0 embedded temperature sensor -+ -+properties: -+ compatible: -+ enum: -+ - starfive,jh7100-temp -+ - starfive,jh7110-temp -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 2 -+ maxItems: 2 -+ -+ clock-names: -+ items: -+ - const: "sense" -+ - const: "bus" -+ -+ '#thermal-sensor-cells': -+ const: 0 -+ -+ resets: -+ minItems: 2 -+ maxItems: 2 -+ -+ reset-names: -+ items: -+ - const: "sense" -+ - const: "bus" -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ - resets -+ - reset-names -+ -+additionalProperties: false -+ -+examples: -+ - | -+ #include -+ #include -+ -+ temperature-sensor@124a0000 { -+ compatible = "starfive,jh7100-temp"; -+ reg = <0x124a0000 0x10000>; -+ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, -+ <&clkgen JH7100_CLK_TEMP_APB>; -+ clock-names = "sense", "bus"; -+ #thermal-sensor-cells = <0>; -+ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, -+ <&rstgen JH7100_RSTN_TEMP_APB>; -+ reset-names = "sense", "bus"; -+ }; --- -2.39.2 - diff --git a/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch b/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch deleted file mode 100644 index 51a005d872691..0000000000000 --- a/srcpkgs/linux6.2/patches/0070-hwmon-sfctemp-Add-StarFive-JH71x0-temperature-sensor.patch +++ /dev/null @@ -1,467 +0,0 @@ -From be2917cfa4f7bed92ebfa8d439a4f0fb361f28a2 Mon Sep 17 00:00:00 2001 -From: Emil Renner Berthing -Date: Mon, 27 Feb 2023 21:41:25 +0800 -Subject: [PATCH 70/70] hwmon: (sfctemp) Add StarFive JH71x0 temperature sensor - -Add driver for the StarFive JH71x0 temperature sensor. You -can enable/disable it and read temperature in milli Celcius -through sysfs. - -Signed-off-by: Emil Renner Berthing -Co-developed-by: Samin Guo -Signed-off-by: Samin Guo -Signed-off-by: Hal Feng ---- - Documentation/hwmon/index.rst | 1 + - Documentation/hwmon/sfctemp.rst | 33 ++++ - MAINTAINERS | 8 + - drivers/hwmon/Kconfig | 10 + - drivers/hwmon/Makefile | 1 + - drivers/hwmon/sfctemp.c | 331 ++++++++++++++++++++++++++++++++ - 6 files changed, 384 insertions(+) - create mode 100644 Documentation/hwmon/sfctemp.rst - create mode 100644 drivers/hwmon/sfctemp.c - -diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst -index fe2cc6b73634..a666e3706ea2 100644 ---- a/Documentation/hwmon/index.rst -+++ b/Documentation/hwmon/index.rst -@@ -180,6 +180,7 @@ Hardware Monitoring Kernel Drivers - sch5627 - sch5636 - scpi-hwmon -+ sfctemp - sht15 - sht21 - sht3x -diff --git a/Documentation/hwmon/sfctemp.rst b/Documentation/hwmon/sfctemp.rst -new file mode 100644 -index 000000000000..9fbd5bb1f356 ---- /dev/null -+++ b/Documentation/hwmon/sfctemp.rst -@@ -0,0 +1,33 @@ -+.. SPDX-License-Identifier: GPL-2.0 -+ -+Kernel driver sfctemp -+===================== -+ -+Supported chips: -+ - StarFive JH7100 -+ - StarFive JH7110 -+ -+Authors: -+ - Emil Renner Berthing -+ -+Description -+----------- -+ -+This driver adds support for reading the built-in temperature sensor on the -+JH7100 and JH7110 RISC-V SoCs by StarFive Technology Co. Ltd. -+ -+``sysfs`` interface -+------------------- -+ -+The temperature sensor can be enabled, disabled and queried via the standard -+hwmon interface in sysfs under ``/sys/class/hwmon/hwmonX`` for some value of -+``X``: -+ -+================ ==== ============================================= -+Name Perm Description -+================ ==== ============================================= -+temp1_enable RW Enable or disable temperature sensor. -+ Automatically enabled by the driver, -+ but may be disabled to save power. -+temp1_input RO Temperature reading in milli-degrees Celsius. -+================ ==== ============================================= -diff --git a/MAINTAINERS b/MAINTAINERS -index 7c73cdbe1259..dbc570dda496 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -18918,6 +18918,14 @@ L: netdev@vger.kernel.org - S: Supported - F: drivers/net/ethernet/sfc/ - -+SFCTEMP HWMON DRIVER -+M: Emil Renner Berthing -+L: linux-hwmon@vger.kernel.org -+S: Maintained -+F: Documentation/devicetree/bindings/hwmon/starfive,jh71x0-temp.yaml -+F: Documentation/hwmon/sfctemp.rst -+F: drivers/hwmon/sfctemp.c -+ - SFF/SFP/SFP+ MODULE SUPPORT - M: Russell King - L: netdev@vger.kernel.org -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index 3176c33af6c6..572e1b2541bb 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -1930,6 +1930,16 @@ config SENSORS_STTS751 - This driver can also be built as a module. If so, the module - will be called stts751. - -+config SENSORS_SFCTEMP -+ tristate "Starfive JH71x0 temperature sensor" -+ depends on SOC_STARFIVE || COMPILE_TEST -+ help -+ If you say yes here you get support for temperature sensor -+ on the Starfive JH71x0 SoCs. -+ -+ This driver can also be built as a module. If so, the module -+ will be called sfctemp. -+ - config SENSORS_SMM665 - tristate "Summit Microelectronics SMM665" - depends on I2C -diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index e2e4e87b282f..337e1b19678a 100644 ---- a/drivers/hwmon/Makefile -+++ b/drivers/hwmon/Makefile -@@ -180,6 +180,7 @@ obj-$(CONFIG_SENSORS_SBRMI) += sbrmi.o - obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o - obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o - obj-$(CONFIG_SENSORS_SCH5636) += sch5636.o -+obj-$(CONFIG_SENSORS_SFCTEMP) += sfctemp.o - obj-$(CONFIG_SENSORS_SL28CPLD) += sl28cpld-hwmon.o - obj-$(CONFIG_SENSORS_SHT15) += sht15.o - obj-$(CONFIG_SENSORS_SHT21) += sht21.o -diff --git a/drivers/hwmon/sfctemp.c b/drivers/hwmon/sfctemp.c -new file mode 100644 -index 000000000000..d7484e2b8100 ---- /dev/null -+++ b/drivers/hwmon/sfctemp.c -@@ -0,0 +1,331 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (C) 2021 Emil Renner Berthing -+ * Copyright (C) 2021 Samin Guo -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+ * TempSensor reset. The RSTN can be de-asserted once the analog core has -+ * powered up. Trst(min 100ns) -+ * 0:reset 1:de-assert -+ */ -+#define SFCTEMP_RSTN BIT(0) -+ -+/* -+ * TempSensor analog core power down. The analog core will be powered up -+ * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the -+ * analog core is powered up. -+ * 0:power up 1:power down -+ */ -+#define SFCTEMP_PD BIT(1) -+ -+/* -+ * TempSensor start conversion enable. -+ * 0:disable 1:enable -+ */ -+#define SFCTEMP_RUN BIT(2) -+ -+/* -+ * TempSensor conversion value output. -+ * Temp(C)=DOUT*Y/4094 - K -+ */ -+#define SFCTEMP_DOUT_POS 16 -+#define SFCTEMP_DOUT_MSK GENMASK(27, 16) -+ -+/* DOUT to Celcius conversion constants */ -+#define SFCTEMP_Y1000 237500L -+#define SFCTEMP_Z 4094L -+#define SFCTEMP_K1000 81100L -+ -+struct sfctemp { -+ /* serialize access to hardware register and enabled below */ -+ struct mutex lock; -+ void __iomem *regs; -+ struct clk *clk_sense; -+ struct clk *clk_bus; -+ struct reset_control *rst_sense; -+ struct reset_control *rst_bus; -+ bool enabled; -+}; -+ -+static void sfctemp_power_up(struct sfctemp *sfctemp) -+{ -+ /* make sure we're powered down first */ -+ writel(SFCTEMP_PD, sfctemp->regs); -+ udelay(1); -+ -+ writel(0, sfctemp->regs); -+ /* wait t_pu(50us) + t_rst(100ns) */ -+ usleep_range(60, 200); -+ -+ /* de-assert reset */ -+ writel(SFCTEMP_RSTN, sfctemp->regs); -+ udelay(1); /* wait t_su(500ps) */ -+} -+ -+static void sfctemp_power_down(struct sfctemp *sfctemp) -+{ -+ writel(SFCTEMP_PD, sfctemp->regs); -+} -+ -+static void sfctemp_run(struct sfctemp *sfctemp) -+{ -+ writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs); -+ udelay(1); -+} -+ -+static void sfctemp_stop(struct sfctemp *sfctemp) -+{ -+ writel(SFCTEMP_RSTN, sfctemp->regs); -+} -+ -+static int sfctemp_enable(struct sfctemp *sfctemp) -+{ -+ int ret = 0; -+ -+ mutex_lock(&sfctemp->lock); -+ if (sfctemp->enabled) -+ goto done; -+ -+ ret = clk_prepare_enable(sfctemp->clk_bus); -+ if (ret) -+ goto err; -+ ret = reset_control_deassert(sfctemp->rst_bus); -+ if (ret) -+ goto err_disable_bus; -+ -+ ret = clk_prepare_enable(sfctemp->clk_sense); -+ if (ret) -+ goto err_assert_bus; -+ ret = reset_control_deassert(sfctemp->rst_sense); -+ if (ret) -+ goto err_disable_sense; -+ -+ sfctemp_power_up(sfctemp); -+ sfctemp_run(sfctemp); -+ sfctemp->enabled = true; -+done: -+ mutex_unlock(&sfctemp->lock); -+ return ret; -+ -+err_disable_sense: -+ clk_disable_unprepare(sfctemp->clk_sense); -+err_assert_bus: -+ reset_control_assert(sfctemp->rst_bus); -+err_disable_bus: -+ clk_disable_unprepare(sfctemp->clk_bus); -+err: -+ mutex_unlock(&sfctemp->lock); -+ return ret; -+} -+ -+static int sfctemp_disable(struct sfctemp *sfctemp) -+{ -+ mutex_lock(&sfctemp->lock); -+ if (!sfctemp->enabled) -+ goto done; -+ -+ sfctemp_stop(sfctemp); -+ sfctemp_power_down(sfctemp); -+ reset_control_assert(sfctemp->rst_sense); -+ clk_disable_unprepare(sfctemp->clk_sense); -+ reset_control_assert(sfctemp->rst_bus); -+ clk_disable_unprepare(sfctemp->clk_bus); -+ sfctemp->enabled = false; -+done: -+ mutex_unlock(&sfctemp->lock); -+ return 0; -+} -+ -+static void sfctemp_disable_action(void *data) -+{ -+ sfctemp_disable(data); -+} -+ -+static int sfctemp_convert(struct sfctemp *sfctemp, long *val) -+{ -+ int ret; -+ -+ mutex_lock(&sfctemp->lock); -+ if (!sfctemp->enabled) { -+ ret = -ENODATA; -+ goto out; -+ } -+ -+ /* calculate temperature in milli Celcius */ -+ *val = (long)((readl(sfctemp->regs) & SFCTEMP_DOUT_MSK) >> SFCTEMP_DOUT_POS) -+ * SFCTEMP_Y1000 / SFCTEMP_Z - SFCTEMP_K1000; -+ -+ ret = 0; -+out: -+ mutex_unlock(&sfctemp->lock); -+ return ret; -+} -+ -+static umode_t sfctemp_is_visible(const void *data, enum hwmon_sensor_types type, -+ u32 attr, int channel) -+{ -+ switch (type) { -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_enable: -+ return 0644; -+ case hwmon_temp_input: -+ return 0444; -+ default: -+ return 0; -+ } -+ default: -+ return 0; -+ } -+} -+ -+static int sfctemp_read(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long *val) -+{ -+ struct sfctemp *sfctemp = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_enable: -+ *val = sfctemp->enabled; -+ return 0; -+ case hwmon_temp_input: -+ return sfctemp_convert(sfctemp, val); -+ default: -+ return -EINVAL; -+ } -+ default: -+ return -EINVAL; -+ } -+} -+ -+static int sfctemp_write(struct device *dev, enum hwmon_sensor_types type, -+ u32 attr, int channel, long val) -+{ -+ struct sfctemp *sfctemp = dev_get_drvdata(dev); -+ -+ switch (type) { -+ case hwmon_temp: -+ switch (attr) { -+ case hwmon_temp_enable: -+ if (val == 0) -+ return sfctemp_disable(sfctemp); -+ if (val == 1) -+ return sfctemp_enable(sfctemp); -+ return -EINVAL; -+ default: -+ return -EINVAL; -+ } -+ default: -+ return -EINVAL; -+ } -+} -+ -+static const struct hwmon_channel_info *sfctemp_info[] = { -+ HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ), -+ HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT), -+ NULL -+}; -+ -+static const struct hwmon_ops sfctemp_hwmon_ops = { -+ .is_visible = sfctemp_is_visible, -+ .read = sfctemp_read, -+ .write = sfctemp_write, -+}; -+ -+static const struct hwmon_chip_info sfctemp_chip_info = { -+ .ops = &sfctemp_hwmon_ops, -+ .info = sfctemp_info, -+}; -+ -+static int sfctemp_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device *hwmon_dev; -+ struct sfctemp *sfctemp; -+ int ret; -+ -+ sfctemp = devm_kzalloc(dev, sizeof(*sfctemp), GFP_KERNEL); -+ if (!sfctemp) -+ return -ENOMEM; -+ -+ dev_set_drvdata(dev, sfctemp); -+ mutex_init(&sfctemp->lock); -+ -+ sfctemp->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(sfctemp->regs)) -+ return PTR_ERR(sfctemp->regs); -+ -+ sfctemp->clk_sense = devm_clk_get(dev, "sense"); -+ if (IS_ERR(sfctemp->clk_sense)) -+ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_sense), -+ "error getting sense clock\n"); -+ -+ sfctemp->clk_bus = devm_clk_get(dev, "bus"); -+ if (IS_ERR(sfctemp->clk_bus)) -+ return dev_err_probe(dev, PTR_ERR(sfctemp->clk_bus), -+ "error getting bus clock\n"); -+ -+ sfctemp->rst_sense = devm_reset_control_get_exclusive(dev, "sense"); -+ if (IS_ERR(sfctemp->rst_sense)) -+ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_sense), -+ "error getting sense reset\n"); -+ -+ sfctemp->rst_bus = devm_reset_control_get_exclusive(dev, "bus"); -+ if (IS_ERR(sfctemp->rst_bus)) -+ return dev_err_probe(dev, PTR_ERR(sfctemp->rst_bus), -+ "error getting busreset\n"); -+ -+ ret = reset_control_assert(sfctemp->rst_sense); -+ if (ret) -+ return dev_err_probe(dev, ret, "error asserting sense reset\n"); -+ -+ ret = reset_control_assert(sfctemp->rst_bus); -+ if (ret) -+ return dev_err_probe(dev, ret, "error asserting bus reset\n"); -+ -+ ret = devm_add_action(dev, sfctemp_disable_action, sfctemp); -+ if (ret) -+ return ret; -+ -+ ret = sfctemp_enable(sfctemp); -+ if (ret) -+ return dev_err_probe(dev, ret, "error enabling temperature sensor: %d\n", ret); -+ -+ hwmon_dev = devm_hwmon_device_register_with_info(dev, "sfctemp", sfctemp, -+ &sfctemp_chip_info, NULL); -+ return PTR_ERR_OR_ZERO(hwmon_dev); -+} -+ -+static const struct of_device_id sfctemp_of_match[] = { -+ { .compatible = "starfive,jh7100-temp" }, -+ { .compatible = "starfive,jh7110-temp" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, sfctemp_of_match); -+ -+static struct platform_driver sfctemp_driver = { -+ .probe = sfctemp_probe, -+ .driver = { -+ .name = "sfctemp", -+ .of_match_table = sfctemp_of_match, -+ }, -+}; -+module_platform_driver(sfctemp_driver); -+ -+MODULE_AUTHOR("Emil Renner Berthing"); -+MODULE_DESCRIPTION("StarFive JH71x0 temperature sensor driver"); -+MODULE_LICENSE("GPL"); --- -2.39.2 - From fb001acc590e52f4f4a0022b434327eb17cc70aa Mon Sep 17 00:00:00 2001 From: John Date: Sun, 23 Jul 2023 15:23:57 +0200 Subject: [PATCH 187/189] linux6.4: broken riscv64 bits --- srcpkgs/linux6.4/files/riscv-dotconfig | 10414 +++++++++++++++ .../linux6.4/files/riscv-dotconfig-custom.old | 225 + srcpkgs/linux6.4/files/riscv-dotconfig.old | 10657 ++++++++++++++++ ...k-Add-StarFive-JH7110-System-Top-Gro.patch | 203 + ...-StarFive-JH7110-System-Top-Group-cl.patch | 228 + ...k-Add-StarFive-JH7110-Image-Signal-P.patch | 166 + ...-StarFive-JH7110-Image-Signal-Proces.patch | 305 + ...k-Add-StarFive-JH7110-Video-Output-c.patch | 173 + ...-StarFive-JH7110-Video-Output-clock-.patch | 294 + ...h7110-Add-StarFive-STG-ISP-VOUT-rese.patch | 66 + ...k-Add-StarFive-JH7110-PLL-clock-gene.patch | 89 + ...-starfive-Add-StarFive-syscon-module.patch | 86 + ...k-jh7110-syscrg-Add-PLL-clock-inputs.patch | 89 + ...Add-StarFive-JH7110-PLL-clock-driver.patch | 565 + ...110-sys-Add-PLL-clocks-source-from-D.patch | 113 + ...er-Add-timer-for-StarFive-JH7110-SoC.patch | 120 + ...-clocksource-Add-JH7110-timer-driver.patch | 543 + ...motorcomm-Add-pad-driver-strength-cf.patch | 41 + ...m-Add-pad-drive-strength-cfg-support.patch | 89 + ...-cdns-qspi-nor-Add-clocks-for-StarFi.patch | 65 + ...spi-Add-clock-configuration-for-Star.patch | 80 + ...bindings-pwm-Add-StarFive-PWM-module.patch | 80 + ...-pwm-starfive-Add-PWM-driver-support.patch | 251 + ...o-hash-Add-statesize-to-crypto_ahash.patch | 78 + ...gs-crypto-Add-StarFive-crypto-module.patch | 96 + ...o-starfive-Add-crypto-engine-support.patch | 356 + ...o-starfive-Add-hash-and-HMAC-support.patch | 1150 ++ ...pto-starfive-Fix-driver-dependencies.patch | 38 + ...-Add-select-ARM_AMBA-to-SOC_STARFIVE.patch | 28 + ...-Add-TDM-controller-bindings-for-Sta.patch | 123 + ...-ASoC-starfive-Add-JH7110-TDM-driver.patch | 760 ++ ...-Add-StarFive-JH7110-dummy-PWM-DAC-t.patch | 61 + ...StarFive-JH7110-dummy-PWM-DAC-transm.patch | 142 + ...-Add-StarFive-JH7110-PWM-DAC-control.patch | 100 + ...C-starfive-Add-JH7110-PWM-DAC-driver.patch | 839 ++ ...r-Add-power-domain-header-for-JH7110.patch | 36 + ...lace-SOC_STARFIVE-with-ARCH_STARFIVE.patch | 32 + ...xtract-JH7110-pmu-private-operations.patch | 180 + ...-starfive-Add-JH7110-AON-PMU-support.patch | 123 + ...ings-phy-Add-starfive-jh7110-dphy-rx.patch | 94 + ...hy-starfive-Add-mipi-dphy-rx-support.patch | 380 + ...s-cadence-csi2rx-Convert-to-DT-schem.patch | 315 + ...s-cadence-csi2rx-Add-resets-property.patch | 59 + ...media-cadence-Add-operation-on-reset.patch | 134 + ...adence-Add-support-for-external-dphy.patch | 146 + ...a-cadence-Add-support-for-JH7110-SoC.patch | 28 + ...bindings-Add-JH7110-Camera-Subsystem.patch | 205 + ...e-Add-starfive_camss.rst-for-Starfiv.patch | 118 + ...edia-starfive-camss-Add-basic-driver.patch | 604 + ...edia-starfive-camss-Add-video-driver.patch | 861 ++ ...-media-starfive-camss-Add-ISP-driver.patch | 1674 +++ ...-media-starfive-camss-Add-VIN-driver.patch | 1593 +++ ...lay-Add-yamls-for-JH7110-display-sub.patch | 300 + ...drm-verisilicon-Add-basic-drm-driver.patch | 581 + ...ilicon-Add-gem-driver-for-JH7110-SoC.patch | 520 + ...rm-verisilicon-Add-mode-config-funcs.patch | 261 + ...4-drm-verisilicon-Add-drm-crtc-funcs.patch | 585 + ...-drm-verisilicon-Add-drm-plane-funcs.patch | 559 + ...Add-verisilicon-dc-controller-driver.patch | 3689 ++++++ ...verisilicon-Add-starfive-hdmi-driver.patch | 1318 ++ ...b-Add-StarFive-JH7110-USB-controller.patch | 141 + ...cdns3-Add-StarFive-JH7110-USB-driver.patch | 308 + ...ings-phy-Add-StarFive-JH7110-USB-PHY.patch | 75 + ...ngs-phy-Add-StarFive-JH7110-PCIe-PHY.patch | 84 + ...arfive-Add-JH7110-USB-2.0-PHY-driver.patch | 204 + ...rfive-Add-JH7110-PCIE-2.0-PHY-driver.patch | 261 + ...add-JH7110-PCIe-dt-binding-documents.patch | 186 + ...five-add-StarFive-JH7110-PCIe-driver.patch | 1014 ++ ...tdev-Add-JH7110-SOC-to-the-allowlist.patch | 29 + ...NTAINERS-Update-all-StarFive-entries.patch | 167 + ...ve-Add-full-support-for-JH7110-and-V.patch | 1413 ++ ...add-missing-null-entry-in-vs_drm_dt_.patch | 25 + ...verisilicon-import-DMA_BUF-namespace.patch | 22 + srcpkgs/linux6.4/template | 2 +- 74 files changed, 47038 insertions(+), 1 deletion(-) create mode 100644 srcpkgs/linux6.4/files/riscv-dotconfig create mode 100644 srcpkgs/linux6.4/files/riscv-dotconfig-custom.old create mode 100644 srcpkgs/linux6.4/files/riscv-dotconfig.old create mode 100644 srcpkgs/linux6.4/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch create mode 100644 srcpkgs/linux6.4/patches/0002-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch create mode 100644 srcpkgs/linux6.4/patches/0003-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch create mode 100644 srcpkgs/linux6.4/patches/0004-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch create mode 100644 srcpkgs/linux6.4/patches/0005-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch create mode 100644 srcpkgs/linux6.4/patches/0006-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch create mode 100644 srcpkgs/linux6.4/patches/0007-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch create mode 100644 srcpkgs/linux6.4/patches/0008-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch create mode 100644 srcpkgs/linux6.4/patches/0009-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch create mode 100644 srcpkgs/linux6.4/patches/0010-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch create mode 100644 srcpkgs/linux6.4/patches/0011-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0012-clk-starfive-jh7110-sys-Add-PLL-clocks-source-from-D.patch create mode 100644 srcpkgs/linux6.4/patches/0013-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.4/patches/0014-clocksource-Add-JH7110-timer-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0015-dt-bindings-net-motorcomm-Add-pad-driver-strength-cf.patch create mode 100644 srcpkgs/linux6.4/patches/0016-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch create mode 100644 srcpkgs/linux6.4/patches/0017-dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFi.patch create mode 100644 srcpkgs/linux6.4/patches/0018-spi-cadence-quadspi-Add-clock-configuration-for-Star.patch create mode 100644 srcpkgs/linux6.4/patches/0019-dt-bindings-pwm-Add-StarFive-PWM-module.patch create mode 100644 srcpkgs/linux6.4/patches/0020-pwm-starfive-Add-PWM-driver-support.patch create mode 100644 srcpkgs/linux6.4/patches/0021-crypto-hash-Add-statesize-to-crypto_ahash.patch create mode 100644 srcpkgs/linux6.4/patches/0022-dt-bindings-crypto-Add-StarFive-crypto-module.patch create mode 100644 srcpkgs/linux6.4/patches/0023-crypto-starfive-Add-crypto-engine-support.patch create mode 100644 srcpkgs/linux6.4/patches/0024-crypto-starfive-Add-hash-and-HMAC-support.patch create mode 100644 srcpkgs/linux6.4/patches/0025-crypto-starfive-Fix-driver-dependencies.patch create mode 100644 srcpkgs/linux6.4/patches/0026-riscv-Kconfig-Add-select-ARM_AMBA-to-SOC_STARFIVE.patch create mode 100644 srcpkgs/linux6.4/patches/0027-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch create mode 100644 srcpkgs/linux6.4/patches/0028-ASoC-starfive-Add-JH7110-TDM-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0029-ASoC-dt-bindings-Add-StarFive-JH7110-dummy-PWM-DAC-t.patch create mode 100644 srcpkgs/linux6.4/patches/0030-ASoC-codecs-Add-StarFive-JH7110-dummy-PWM-DAC-transm.patch create mode 100644 srcpkgs/linux6.4/patches/0031-ASoC-dt-bindings-Add-StarFive-JH7110-PWM-DAC-control.patch create mode 100644 srcpkgs/linux6.4/patches/0032-ASoC-starfive-Add-JH7110-PWM-DAC-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0033-dt-bindings-power-Add-power-domain-header-for-JH7110.patch create mode 100644 srcpkgs/linux6.4/patches/0034-soc-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch create mode 100644 srcpkgs/linux6.4/patches/0035-soc-starfive-Extract-JH7110-pmu-private-operations.patch create mode 100644 srcpkgs/linux6.4/patches/0036-soc-starfive-Add-JH7110-AON-PMU-support.patch create mode 100644 srcpkgs/linux6.4/patches/0037-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch create mode 100644 srcpkgs/linux6.4/patches/0038-phy-starfive-Add-mipi-dphy-rx-support.patch create mode 100644 srcpkgs/linux6.4/patches/0039-media-dt-bindings-cadence-csi2rx-Convert-to-DT-schem.patch create mode 100644 srcpkgs/linux6.4/patches/0040-media-dt-bindings-cadence-csi2rx-Add-resets-property.patch create mode 100644 srcpkgs/linux6.4/patches/0041-media-cadence-Add-operation-on-reset.patch create mode 100644 srcpkgs/linux6.4/patches/0042-media-cadence-Add-support-for-external-dphy.patch create mode 100644 srcpkgs/linux6.4/patches/0043-media-cadence-Add-support-for-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.4/patches/0044-media-dt-bindings-Add-JH7110-Camera-Subsystem.patch create mode 100644 srcpkgs/linux6.4/patches/0045-media-admin-guide-Add-starfive_camss.rst-for-Starfiv.patch create mode 100644 srcpkgs/linux6.4/patches/0046-media-starfive-camss-Add-basic-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0047-media-starfive-camss-Add-video-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0048-media-starfive-camss-Add-ISP-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0049-media-starfive-camss-Add-VIN-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0050-dt-bindings-display-Add-yamls-for-JH7110-display-sub.patch create mode 100644 srcpkgs/linux6.4/patches/0051-drm-verisilicon-Add-basic-drm-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0052-drm-verisilicon-Add-gem-driver-for-JH7110-SoC.patch create mode 100644 srcpkgs/linux6.4/patches/0053-drm-verisilicon-Add-mode-config-funcs.patch create mode 100644 srcpkgs/linux6.4/patches/0054-drm-verisilicon-Add-drm-crtc-funcs.patch create mode 100644 srcpkgs/linux6.4/patches/0055-drm-verisilicon-Add-drm-plane-funcs.patch create mode 100644 srcpkgs/linux6.4/patches/0056-drm-verisilicon-Add-verisilicon-dc-controller-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0057-drm-verisilicon-Add-starfive-hdmi-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0058-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch create mode 100644 srcpkgs/linux6.4/patches/0059-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0060-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch create mode 100644 srcpkgs/linux6.4/patches/0061-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch create mode 100644 srcpkgs/linux6.4/patches/0062-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0063-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0064-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch create mode 100644 srcpkgs/linux6.4/patches/0065-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch create mode 100644 srcpkgs/linux6.4/patches/0066-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch create mode 100644 srcpkgs/linux6.4/patches/0067-MAINTAINERS-Update-all-StarFive-entries.patch create mode 100644 srcpkgs/linux6.4/patches/0068-riscv-dts-starfive-Add-full-support-for-JH7110-and-V.patch create mode 100644 srcpkgs/linux6.4/patches/0071-drm-verisilicon-add-missing-null-entry-in-vs_drm_dt_.patch create mode 100644 srcpkgs/linux6.4/patches/0072-drm-verisilicon-import-DMA_BUF-namespace.patch diff --git a/srcpkgs/linux6.4/files/riscv-dotconfig b/srcpkgs/linux6.4/files/riscv-dotconfig new file mode 100644 index 0000000000000..5f641ccd8c6c7 --- /dev/null +++ b/srcpkgs/linux6.4/files/riscv-dotconfig @@ -0,0 +1,10414 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 6.4.3 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-linux-gnu-gcc (GCC) 12.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=120200 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23900 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23900 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=125 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="_1" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_WATCH_QUEUE=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_SIM=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ_FULL=y +CONFIG_CONTEXT_TRACKING_USER=y +CONFIG_CONTEXT_TRACKING_USER_FORCE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_LSM=y +# end of BPF subsystem + +CONFIG_PREEMPT_VOLUNTARY_BUILD=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +CONFIG_RCU_LAZY=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_MEMCG=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_MM_CID=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_FORCE is not set +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_AS_HAS_INSN=y + +# +# SoC selection +# +# CONFIG_SOC_MICROCHIP_POLARFIRE is not set +# CONFIG_ARCH_RENESAS is not set +CONFIG_ARCH_SIFIVE=y +CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_STARFIVE=y +CONFIG_SOC_STARFIVE=y +# CONFIG_ARCH_SUNXI is not set +CONFIG_ARCH_VIRT=y +CONFIG_SOC_VIRT=y +# end of SoC selection + +# +# CPU errata selection +# +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PMU=y +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_NONPORTABLE is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=480 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +# CONFIG_NUMA is not set +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ISA_C=y +# CONFIG_RISCV_ISA_SVNAPOT is not set +# CONFIG_RISCV_ISA_SVPBMT is not set +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_RISCV_ISA_ZBB=y +# CONFIG_RISCV_ISA_ZICBOM is not set +# CONFIG_RISCV_ISA_ZICBOZ is not set +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +# CONFIG_FPU is not set +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_RISCV_SBI_V01 is not set +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_KEXEC=y +# CONFIG_KEXEC_FILE is not set +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +CONFIG_RELOCATABLE=y +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Boot options + +CONFIG_PORTABLE=y + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_DPM_WATCHDOG=y +CONFIG_DPM_WATCHDOG_TIMEOUT=60 +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +CONFIG_ENERGY_MODEL=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +# end of CPU Frequency scaling +# end of CPU Power Management + +# CONFIG_VIRTUALIZATION is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_GENERIC_ENTRY=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_VDSO_DATA=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_FUNCTION_ALIGNMENT=0 +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_DEFERRED_STRUCT_PAGE_INIT=y +CONFIG_PAGE_IDLE_FLAG=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +CONFIG_GET_FREE_REGION=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +# CONFIG_DMAPOOL_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LOCK_MM_AND_FIND_VMA=y + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +# CONFIG_DAMON_LRU_SORT is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XFRM_ESPINTCP=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_NET_HANDSHAKE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_BPF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_NETLABEL=y +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +# CONFIG_BPFILTER_UMH is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_NONE=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_DEBUG=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +# end of AX.25 network device drivers + +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_MTK=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_VIRTIO=m +CONFIG_BT_NXPUART=m +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=y +# CONFIG_RXPERF is not set +CONFIG_AF_KCM=m +CONFIG_STREAM_PARSER=y +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_SPI is not set +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +# end of Near Field Communication (NFC) devices + +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_STARFIVE=m + +# +# Cadence-based PCIe controllers +# +CONFIG_PCIE_CADENCE=y +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_EP=y +CONFIG_PCIE_CADENCE_PLAT=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +# end of Cadence-based PCIe controllers + +# +# DesignWare-based PCIe controllers +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCI_MESON=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_FU740=y +# end of DesignWare-based PCIe controllers + +# +# Mobiveil-based PCIe controllers +# +# end of Mobiveil-based PCIe controllers +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m +CONFIG_PCI_EPF_VNTB=m +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +CONFIG_CXL_BUS=m +CONFIG_CXL_PCI=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PMEM=m +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m + +# +# RapidIO Switch drivers +# +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_UPLOAD=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MOXTET=m +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_FW_CS_DSP=m +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +# CONFIG_SM_FTL is not set +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PSTORE is not set +CONFIG_MTD_SWAP=m +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +CONFIG_MTD_MAP_BANK_WIDTH_16=y +CONFIG_MTD_MAP_BANK_WIDTH_32=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m + +# +# Raw/parallel NAND flash controllers +# +CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m + +# +# Misc +# +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y +CONFIG_MTD_SPI_NAND=m + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_MXIC=y +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +# CONFIG_NVME_AUTH is not set +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_AUTH is not set +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_XILINX_SDFEC=m +CONFIG_MISC_RTSX=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_C2PORT=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_SPI=y +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_ECHO=m +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_GP_PCI1XXXX=m +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_AHCI_CEVA=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +# CONFIG_PATA_OF_PLATFORM is not set +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_DM_AUDIT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_REMOTE_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RIONET_RX_SIZE=128 +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_SUNGEM_PHY=m +# CONFIG_ARCNET is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI_TUNE_BURST=y +CONFIG_ATM_ENI_BURST_TX_16W=y +CONFIG_ATM_ENI_BURST_TX_8W=y +CONFIG_ATM_ENI_BURST_TX_4W=y +CONFIG_ATM_ENI_BURST_TX_2W=y +CONFIG_ATM_ENI_BURST_RX_16W=y +CONFIG_ATM_ENI_BURST_RX_8W=y +CONFIG_ATM_ENI_BURST_RX_4W=y +CONFIG_ATM_ENI_BURST_RX_2W=y +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_NICSTAR_USE_SUNI=y +CONFIG_ATM_NICSTAR_USE_IDT77105=y +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +# CONFIG_CAIF_DRIVERS is not set + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m +CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_SLICOSS=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PDS_CORE=m +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AX88796C_COMPRESSION is not set +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACB_PCI=m +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_CAVIUM_PTP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +CONFIG_NET_VENDOR_CORTINA=y +CONFIG_GEMINI_ETHERNET=m +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +CONFIG_TULIP_NAPI=y +CONFIG_TULIP_NAPI_HW_MITIGATION=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_JME=m +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +# CONFIG_OCTEON_EP is not set +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_EN_MACSEC is not set +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXFW=m +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_VCAP=y +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NI=y +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_NET_IPSEC=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_IONIC=m +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_LL2=y +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +CONFIG_QED_RDMA=y +CONFIG_QED_ISCSI=y +CONFIG_QED_FCOE=y +CONFIG_QED_OOO=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_QCA7000=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_SXGBE_ETH=m +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_LOONGSON=m +CONFIG_STMMAC_PCI=m +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_MSE102X=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_LIBWX=m +CONFIG_NGBE=m +# CONFIG_TXGBE is not set +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_PHYLIB_LEDS=y +CONFIG_FIXED_PHY=y +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIN1100_PHY is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_CBTX_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_NCN26000_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TD510_PHY is not set +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_FLEXCAN=m +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_C_CAN=m +# CONFIG_CAN_C_CAN_PLATFORM is not set +CONFIG_CAN_C_CAN_PCI=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_USB is not set +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set + +# +# MCTP Device Drivers +# +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# end of MCTP Device Drivers + +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +CONFIG_PCS_LYNX=m +CONFIG_PCS_MTK_LYNXI=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ADM8211=m +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +# CONFIG_WIL6210_DEBUGFS is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K_DEBUGFS=y +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATH12K=m +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K_TRACING=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO=m +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +CONFIG_LIBIPW_DEBUG=y +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# CONFIG_IWLEGACY_DEBUGFS is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615_COMMON=m +CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921_COMMON=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7996E=m +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW89=m +CONFIG_RTW89_CORE=m +CONFIG_RTW89_PCI=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852CE=m +# CONFIG_RTW89_DEBUGMSG is not set +# CONFIG_RTW89_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WFX=m +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +# CONFIG_CW1200_WLAN_SPI is not set +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +# CONFIG_WL1251_SPI is not set +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_MAC80211_HWSIM=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=y +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +# CONFIG_IOSM is not set +CONFIG_MTK_T7XX=m +# end of Wireless WAN + +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +# CONFIG_KEYBOARD_SAMSUNG is not set +CONFIG_KEYBOARD_GOLDFISH_EVENTS=y +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_IQS62X=m +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_KEYBOARD_BCM is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUR40=m +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +# CONFIG_INPUT_AD714X_SPI is not set +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MMA8450=m +# CONFIG_INPUT_GPIO_BEEPER is not set +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +# CONFIG_INPUT_IQS7222 is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_AMBAKMI=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=m +CONFIG_SERIAL_AMBA_PL011=m +CONFIG_SERIAL_EARLYCON_SEMIHOST=y +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SC16IS7XX_CORE=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=y +CONFIG_SERIAL_SC16IS7XX_SPI=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_SPRD=y +CONFIG_SERIAL_SPRD_CONSOLE=y +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=y +CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y +CONFIG_IPWIRELESS=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_HVC_DRIVER=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_PANIC_EVENT=y +# CONFIG_IPMI_PANIC_STRING is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM_JH7110=m +CONFIG_APPLICOM=m +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_NOMADIK=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RK3X=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_XILINX=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_VIRTIO=m +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_SLAVE_TESTUNIT=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PL022=m +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y + +# +# HSI controllers +# + +# +# HSI clients +# +CONFIG_HSI_CHAR=m +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PTP_DFL_TOD=m +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CY8C95X0=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_CS47L15=y +CONFIG_PINCTRL_CS47L35=y +CONFIG_PINCTRL_CS47L85=y +CONFIG_PINCTRL_CS47L90=y +CONFIG_PINCTRL_CS47L92=y + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=m +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_REGMAP=m +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_IDIO_16=m + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_74XX_MMIO=m +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +# CONFIG_GPIO_EXAR is not set +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_PL061=m +# CONFIG_GPIO_SIFIVE is not set +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_XILINX=m +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_FXL6408=m +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_TQMX86=m +# CONFIG_GPIO_WM8994 is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +CONFIG_GPIO_MAX3191X=m +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_MOCKUP=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +# end of Virtual GPIO drivers + +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# end of 1-wire Slaves + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_IP5XXX_POWER=m +# CONFIG_TEST_POWER is not set +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_CPCAP=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_QCOM_BATTMGR=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_BQ27XXX_HDQ=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_GPIO=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_BQ2415X is not set +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_BATTERY_UG3105=m +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_SMPRO=m +# CONFIG_SENSORS_AD7314 is not set +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_ADT7310 is not set +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_MAX1111 is not set +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +# CONFIG_SENSORS_MAX197 is not set +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +# CONFIG_SENSORS_MENF21BMC_HWMON is not set +CONFIG_SENSORS_MR75203=m +# CONFIG_SENSORS_ADCXX is not set +CONFIG_SENSORS_LM63=m +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +# CONFIG_SENSORS_NTC_THERMISTOR is not set +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775_I2C is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_OCC_P8_I2C=m +CONFIG_SENSORS_OCC=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_SENSORS_PECI=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ACBEL_FSG032=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +# CONFIG_SENSORS_IR38064_REGULATOR is not set +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +# CONFIG_SENSORS_XDPE152 is not set +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SFCTEMP=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +# CONFIG_SENSORS_ADS7871 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_IDLE_THERMAL is not set +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=m +CONFIG_MAX77620_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_MENF21BMC_WATCHDOG is not set +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_STARFIVE_WATCHDOG=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +CONFIG_MFD_SMPRO=m +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +CONFIG_MFD_ATMEL_HLCDC=m +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_MAX597X=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_MFD_IQS62X=m +# CONFIG_MFD_JANZ_CMODIO is not set +CONFIG_MFD_KEMPLD=m +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m +# CONFIG_MFD_MT6397 is not set +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_OCELOT=m +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +CONFIG_MFD_SY7636A=m +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=m +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SM501 is not set +CONFIG_MFD_SKY81452=m +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +# CONFIG_MFD_LP8788 is not set +CONFIG_MFD_TI_LMU=m +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +# CONFIG_MFD_TPS65218 is not set +CONFIG_MFD_TPS65219=m +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_LM3533=m +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +# CONFIG_RAVE_SP_CORE is not set +CONFIG_MFD_INTEL_M10_BMC_CORE=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_88PG86X=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA9121=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +# CONFIG_REGULATOR_ISL6271A is not set +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +CONFIG_REGULATOR_LP873X=m +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX597X=m +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set +CONFIG_REGULATOR_MAX20411=m +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_ROHM=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65219=m +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y + +# +# CEC support +# +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +# end of CEC support + +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=m +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +# end of Video4Linux options + +# +# Media controller options +# +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y + +# +# Analog TV USB devices +# +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_ZORAN is not set + +# +# Media capture/analog TV support +# +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +# CONFIG_I2C_SI470X is not set +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +CONFIG_VIDEO_CAFE_CCIC=m + +# +# Mediatek media platform drivers +# + +# +# Microchip Technology, Inc. media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# + +# +# StarFive media platform drivers +# +CONFIG_VIDEO_STARFIVE_CAMSS=m + +# +# Sunxi media platform drivers +# + +# +# Texas Instruments drivers +# + +# +# Verisilicon media platform drivers +# + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_VIDEO_XILINX_VTC=m + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VISL=m +# CONFIG_VISL_DEBUGFS is not set +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m +CONFIG_UVC_COMMON=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=m + +# +# Camera sensor devices +# +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_ST_VGXY61=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +# end of Camera sensor devices + +# +# Lens drivers +# +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +# end of Flash devices + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +# end of Video encoders + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +CONFIG_SDR_MAX2175=m +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +# end of Miscellaneous helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_EC100=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_L64781=m +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_STV0297=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_VES1820=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_MN88443X=m +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_DRX39XYJ=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y +CONFIG_DRM=m +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_BUDDY=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_SUBALLOC_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m +# end of I2C encoder or helper chips + +# +# ARM devices +# +CONFIG_DRM_KOMEDA=m +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_DRM_NOUVEAU=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_EBBG_FT8719=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX8394=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_NOVATEK_NT36523=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_SONY_TD4353_JDI=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SAMSUNG_DSIM=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CDNS_DSI_J721E=y +CONFIG_DRM_CDNS_MHDP8546=m +# end of Display Interface Bridges + +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV_THERMAL=y +CONFIG_DRM_LOGICVC=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_SIMPLEDRM=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +CONFIG_DRM_VERISILICON=m +CONFIG_STARFIVE_HDMI=y +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_I740=m +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SMSCUFX=m +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_GOLDFISH is not set +CONFIG_FB_VIRTUAL=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_QAIC=m +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTL_DEBUG is not set +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_PREALLOC_SIZE=1024 +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_IMX_AUDMUX=m +# end of SoC Audio for Freescale CPUs + +CONFIG_SND_I2S_HI6210_I2S=m +# CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_MTK_BTCVSD=m +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_STARFIVE=m +CONFIG_SND_SOC_JH7110_PWMDAC=m +CONFIG_SND_SOC_JH7110_TDM=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m +# CONFIG_SND_SOC_AW88395 is not set +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L56=m +CONFIG_SND_SOC_CS35L56_SHARED=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS35L56_SDW=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_JH7110_PWMDAC_DIT=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +# CONFIG_SND_SOC_INNO_RK3036 is not set +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98090=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PEB2466=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8315=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_VIRTIO=m +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_STEAM_FF=y +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +# end of Special HID drivers + +# +# HID-BPF support +# +# end of HID-BPF support + +# +# USB HID support +# +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +CONFIG_I2C_HID=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_I2C_HID_CORE=m +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_SL811_HCD=m +# CONFIG_USB_SL811_HCD_ISO is not set +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set + +# +# USB dual-mode controller drivers +# +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DUAL_ROLE is not set + +# +# Platform Glue Layer +# + +# +# MUSB DMA mode +# +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC2=m +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=m +# CONFIG_USB_CHIPIDEA_UDC is not set +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_IMX=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_TEGRA=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_DUAL_ROLE is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +# CONFIG_USB_CHAOSKEY is not set +CONFIG_USB_ONBOARD_HUB=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_USB_ISP1301=m +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_U_SERIAL_CONSOLE=y + +# +# USB Peripheral Controller +# +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SNP_UDC_PLAT=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=m +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_TCM=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UCSI_PMIC_GLINK=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_PI3USB30532=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_CRYPTO=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_ARMMMCI=m +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +# CONFIG_MMC_SDHCI_MILBEAUT is not set +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_AM654=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y + +# +# LED drivers +# +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_BD2606MVV=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_TCA6507=m +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_MT6370_FLASH=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m + +# +# RGB LED drivers +# +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m +CONFIG_LEDS_MT6370_RGB=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m + +# +# Simple LED drivers +# +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_SIFIVE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_SD3078=m + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +CONFIG_RTC_DRV_MAX6916=m +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_PCF2127=m +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_RTC_DRV_NTXEC=m + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_PL030=m +CONFIG_RTC_DRV_PL031=m +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_AMBA_PL08X=y +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +CONFIG_PLX_DMA=m +CONFIG_XILINX_XDMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +# CONFIG_SF_PDMA is not set + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_LINEDISP=m +CONFIG_HD44780_COMMON=m +CONFIG_HD44780=m +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PARPORT_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +CONFIG_PANEL=m +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_VIRQFD=y +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_VP_VDPA=m +CONFIG_SNET_VDPA=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_COMEDI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +# CONFIG_COMEDI_MISC_DRIVERS is not set +# CONFIG_COMEDI_ISA_DRIVERS is not set +# CONFIG_COMEDI_PCI_DRIVERS is not set +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_ROUTING=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +CONFIG_FB_SM750=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_SP8870=m +CONFIG_VIDEO_MAX96712=m +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STAGING_BOARD is not set +CONFIG_LTE_GDM724X=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +# CONFIG_VME_BUS is not set +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIPE=m +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SI5341=m +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_SI521XX=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_VC7=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_XILINX_VCU=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_HWSPINLOCK=y + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_RISCV_TIMER=y +CONFIG_STARFIVE_JH7110_TIMER=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=m +CONFIG_ARM_MHU_V2=m +CONFIG_PLATFORM_MHU=m +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_IOMMU_IOVA=m +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_OF_IOMMU=y +CONFIG_IOMMUFD=m + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_QCOM=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +CONFIG_WPCM450_SOC=m + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_PDR_HELPERS=m +CONFIG_QCOM_PMIC_GLINK=m +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +CONFIG_SIFIVE_CCACHE=y +CONFIG_JH71XX_PMU=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_PTN5150=m +# CONFIG_EXTCON_RT8973A is not set +CONFIG_EXTCON_SM5502=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_ARM_PL172_MPMC=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_GTS_HELPER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_KX022A=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_KX022A_I2C=m +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +CONFIG_MC3230=m +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +CONFIG_MMA9551_CORE=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MSA311=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +# end of Accelerometers + +# +# Analog to digital converters +# +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AD4130=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +# CONFIG_CC10001_ADC is not set +CONFIG_CPCAP_ADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +# CONFIG_MAX1027 is not set +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +# CONFIG_MAX1363 is not set +CONFIG_MAX9611=m +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +CONFIG_MCP3911=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MP2629_ADC=m +# CONFIG_NAU7802 is not set +CONFIG_QCOM_VADC_COMMON=m +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RICHTEK_RTQ6056=m +CONFIG_SD_ADC_MODULATOR=m +# CONFIG_TI_ADC081C is not set +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +# CONFIG_TI_ADC128S052 is not set +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS1100=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +# CONFIG_TI_AM335X_ADC is not set +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_XILINX_XADC=m +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +CONFIG_AD74115=m +CONFIG_AD74413R=m +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +CONFIG_IIO_RESCALE=m +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +CONFIG_ADA4250=m +CONFIG_HMC425=m +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +CONFIG_IIO_MS_SENSORS_I2C=m + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +CONFIG_AD3552R=m +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +CONFIG_AD5592R_BASE=m +CONFIG_AD5592R=m +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +CONFIG_LTC2688=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +# CONFIG_AD5755 is not set +CONFIG_AD5758=m +CONFIG_AD5761=m +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +CONFIG_AD7293=m +# CONFIG_AD7303 is not set +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +# CONFIG_MAX517 is not set +CONFIG_MAX5522=m +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Filters +# +CONFIG_ADMV8818=m +# end of Filters + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +# CONFIG_ADRF6780 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +CONFIG_AM2315=m +# CONFIG_DHT11 is not set +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +# end of Inertial measurement units + +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=m +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9960=m +CONFIG_AS73211=m +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +CONFIG_IQS621_ALS=m +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_ROHM_BU27034=m +CONFIG_RPR0521=m +# CONFIG_SENSORS_LM3533 is not set +# CONFIG_LTR501 is not set +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +# CONFIG_STK3310 is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +CONFIG_TSL2591=m +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_US5182D=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +# CONFIG_VEML6070 is not set +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +# end of Light sensors + +# +# Magnetometer sensors +# +CONFIG_AK8974=m +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_RM3100=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_TI_TMAG5273=m +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +CONFIG_IIO_MUX=m +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +CONFIG_IIO_HRTIMER_TRIGGER=m +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +CONFIG_IQS624_POS=m +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +CONFIG_AD5110=m +CONFIG_AD5272=m +# CONFIG_DS1803 is not set +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +# CONFIG_MCP4131 is not set +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +# end of Digital potentiometers + +# +# Digital potentiostats +# +CONFIG_LMP91000=m +# end of Digital potentiostats + +# +# Pressure sensors +# +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +CONFIG_ICP10100=m +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX_COMMON=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +CONFIG_MLX90632=m +# CONFIG_TMP006 is not set +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX30208=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +# end of Temperature sensors + +CONFIG_NTB=y +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +# CONFIG_NTB_PINGPONG is not set +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +# CONFIG_NTB_MSI_TEST is not set +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_STARFIVE_PTC=m +CONFIG_PWM_XILINX=m + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_AL_FIC=y +CONFIG_MADERA_IRQ=m +# CONFIG_XILINX_INTC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m + +# +# PHY drivers for Broadcom platforms +# +CONFIG_BCM_KONA_USB2_PHY=m +# end of PHY drivers for Broadcom platforms + +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_LAN966X_SERDES=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +CONFIG_PHY_STARFIVE_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +CONFIG_RAS=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set + +# +# Android +# +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +CONFIG_LIBNVDIMM=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +CONFIG_OF_PMEM=m +CONFIG_NVDIMM_KEYS=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# Layout Types +# +CONFIG_NVMEM_LAYOUT_SL28_VPD=m +CONFIG_NVMEM_LAYOUT_ONIE_TLV=m +# end of Layout Types + +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_U_BOOT_ENV=m + +# +# HW tracing support +# +CONFIG_STM=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +# CONFIG_STM_DUMMY is not set +CONFIG_STM_SOURCE_CONSOLE=y +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STM_SOURCE_FTRACE=m +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +CONFIG_PECI=m +CONFIG_PECI_CPU=m +CONFIG_HTE=y +# end of Device Drivers + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_SUPPORT_ASCII_CI=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +CONFIG_QNX6FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_ROMFS_FS=m +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_ZSTD_COMPRESS=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_ZONE=m +CONFIG_PSTORE_BLK=m +CONFIG_PSTORE_BLK_BLKDEV="" +CONFIG_PSTORE_BLK_KMSG_SIZE=64 +CONFIG_PSTORE_BLK_MAX_REASON=2 +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EROFS_FS=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_PCPU_KTHREAD=y +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_CRYPTOSYSTEM=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=y +# end of Compression + +# +# Random number generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +# CONFIG_CRYPTO_DEV_CCREE is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +CONFIG_PACKING=y +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=y +CONFIG_CRC4=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=y +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=y +CONFIG_842_DECOMPRESS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_BCH=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_INTERVAL_TREE_SPAN_ITER=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CHECK_SIGNATURE=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +CONFIG_FONT_TER16x32=y +# CONFIG_FONT_6x8 is not set +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_MEMREGION=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +CONFIG_PARMAN=m +CONFIG_OBJAGG=m +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m +CONFIG_POLYNOMIAL=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_NONE is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_BTF=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_PAGE_OWNER=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_TORTURE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +# CONFIG_DEBUG_CGROUP_REF is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_RETHOOK=y +CONFIG_RETHOOK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FPROBE=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_OSNOISE_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y +CONFIG_SYNTH_EVENTS=y +CONFIG_USER_EVENTS=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set +# CONFIG_SAMPLES is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# riscv Debugging +# +# end of riscv Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_TEST_DHRY is not set +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ASYNC_RAID6_TEST=m +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/srcpkgs/linux6.4/files/riscv-dotconfig-custom.old b/srcpkgs/linux6.4/files/riscv-dotconfig-custom.old new file mode 100644 index 0000000000000..c3a3a5bb89b68 --- /dev/null +++ b/srcpkgs/linux6.4/files/riscv-dotconfig-custom.old @@ -0,0 +1,225 @@ +CONFIG_WERROR=y +CONFIG_SYSVIPC=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PSI=y +# CONFIG_CPU_ISOLATION is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=y +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_KCMP=y +CONFIG_PERF_EVENTS=y +CONFIG_ARCH_STARFIVE=y +CONFIG_SOC_STARFIVE=y +CONFIG_ERRATA_SIFIVE=y +CONFIG_SMP=y +# CONFIG_RISCV_ISA_SVPBMT is not set +# CONFIG_COMPAT is not set +CONFIG_CPU_IDLE=y +CONFIG_RISCV_SBI_CPUIDLE=y +CONFIG_JUMP_LABEL=y +# CONFIG_STACKPROTECTOR is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_COMPRESS_ZSTD=y +# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set +CONFIG_BLK_WBT=y +# CONFIG_BLK_DEBUG_FS is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +CONFIG_IOSCHED_BFQ=y +CONFIG_KSM=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_INET_DIAG=m +# CONFIG_IPV6_SIT is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_WIRELESS is not set +# CONFIG_ETHTOOL_NETLINK is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_EFI_DISABLE_RUNTIME=y +CONFIG_ZRAM=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=1 +CONFIG_NETDEVICES=y +CONFIG_STMMAC_ETH=y +CONFIG_DWMAC_DWC_QOS_ETH=y +# CONFIG_DWMAC_GENERIC is not set +CONFIG_DWMAC_STARFIVE=y +CONFIG_MICROCHIP_PHY=y +CONFIG_MOTORCOMM_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LDISC_AUTOLOAD is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_DEVMEM is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_DESIGNWARE_PLATFORM=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=128 +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_SENSORS_SFCTEMP=y +# CONFIG_HID is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_DW=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_BTRFS_FS=y +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_DNOTIFY is not set +CONFIG_FANOTIFY=y +CONFIG_AUTOFS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_EFIVAR_FS=y +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_DEFAULT="iso8859-15" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_15=y +CONFIG_LSM="" +CONFIG_CRYPTO_ZSTD=y +# CONFIG_RAID6_PQ_BENCHMARK is not set +# CONFIG_DEBUG_MISC is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_SECTION_MISMATCH=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_DEBUG_FS=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_PAGE_TABLE_CHECK=y +CONFIG_DEBUG_RODATA_TEST=y +CONFIG_DEBUG_WX=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_STACKTRACE=y +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_EXT4_FS=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_FREQ=y +CONFIG_HIBERNATION=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_SWAP=y +CONFIG_PCIE_STARFIVE=y +CONFIG_PCI_MSI=y +CONFIG_PCI=y +CONFIG_USB_CDNS3_STARFIVE=y +CONFIG_PHY_STARFIVE_JH7110_PCIE=y +CONFIG_PHY_STARFIVE_JH7110_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_SCSI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CDNS_SUPPORT=y +CONFIG_USB_CDNS3=y +CONFIG_USB=y +CONFIG_USB_SUPPORT=y +CONFIG_VIDEO_STARFIVE_CAMSS=y +CONFIG_VIDEO_CADENCE_CSI2RX=y +CONFIG_VIDEO_DEV=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_PHY_STARFIVE_DPHY_RX=y +CONFIG_CRYPTO_DEV_JH7110=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO=y +CONFIG_SND_SOC_JH7110_TDM=y +CONFIG_SND_SOC_STARFIVE=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_SND_SOC=y +CONFIG_SND=y +CONFIG_SOUND=y +CONFIG_DW_AXI_DMAC=y +CONFIG_DMADEVICES=y +CONFIG_HAS_IOMEM=y +CONFIG_PWM_STARFIVE_PTC=y +CONFIG_PWM=y +CONFIG_STARFIVE_TIMER=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_STARFIVE_WATCHDOG=y +CONFIG_WATCHDOG=y +CONFIG_HW_RANDOM_JH7110=y +CONFIG_HW_RANDOM=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI=y +CONFIG_MMC_DW_STARFIVE=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_JH71XX_PMU=y +CONFIG_PM=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_CLINT_TIMER=y +CONFIG_SIFIVE_PLIC=y diff --git a/srcpkgs/linux6.4/files/riscv-dotconfig.old b/srcpkgs/linux6.4/files/riscv-dotconfig.old new file mode 100644 index 0000000000000..53fe004412721 --- /dev/null +++ b/srcpkgs/linux6.4/files/riscv-dotconfig.old @@ -0,0 +1,10657 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 6.4.0-rc4 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="riscv64-linux-musl-gcc (GCC) 12.2.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=120200 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23900 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23900 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y +CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=125 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="_1" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_WATCH_QUEUE=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_INJECTION=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_SIM=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_IRQ_IPI_MUX=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ_FULL=y +CONFIG_CONTEXT_TRACKING_USER=y +CONFIG_CONTEXT_TRACKING_USER_FORCE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT_DEFAULT_ON=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_USERMODE_DRIVER=y +# CONFIG_BPF_PRELOAD is not set +CONFIG_BPF_LSM=y +# end of BPF subsystem + +CONFIG_PREEMPT_VOLUNTARY_BUILD=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_VIRT_CPU_ACCOUNTING=y +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y +# end of CPU/Task time and stats accounting + +CONFIG_CPU_ISOLATION=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +CONFIG_RCU_LAZY=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_IKHEADERS=m +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_PRINTK_INDEX is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# CONFIG_UCLAMP_TASK is not set +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_CC_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_MEMCG=y +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_SCHED_MM_CID=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_TIME_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOT_CONFIG_FORCE is not set +# CONFIG_BOOT_CONFIG_EMBED is not set +CONFIG_INITRAMFS_PRESERVE_MTIME=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_KCMP=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17 +CONFIG_RISCV_SBI=y +CONFIG_MMU=y +CONFIG_PAGE_OFFSET=0xff60000000000000 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=5 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_RISCV_DMA_NONCOHERENT=y +CONFIG_AS_HAS_INSN=y + +# +# SoC selection +# +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_SIFIVE=y +CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_STARFIVE=y +CONFIG_SOC_STARFIVE=y +CONFIG_ARCH_SUNXI=y +CONFIG_ARCH_VIRT=y +CONFIG_SOC_VIRT=y +# end of SoC selection + +# +# CPU errata selection +# +CONFIG_ERRATA_SIFIVE=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_THEAD=y +CONFIG_ERRATA_THEAD_PBMT=y +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_PMU=y +# end of CPU errata selection + +# +# Platform type +# +# CONFIG_NONPORTABLE is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +CONFIG_MODULE_SECTIONS=y +CONFIG_SMP=y +CONFIG_SCHED_MC=y +CONFIG_NR_CPUS=480 +CONFIG_HOTPLUG_CPU=y +CONFIG_TUNE_GENERIC=y +CONFIG_NUMA=y +CONFIG_NODES_SHIFT=6 +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_TOOLCHAIN_HAS_ZBB=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y +CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y +CONFIG_FPU=y +# end of Platform type + +# +# Kernel features +# +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +# CONFIG_RISCV_SBI_V01 is not set +# CONFIG_RISCV_BOOT_SPINWAIT is not set +CONFIG_KEXEC=y +# CONFIG_KEXEC_FILE is not set +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +CONFIG_RELOCATABLE=y +# end of Kernel features + +# +# Boot options +# +CONFIG_CMDLINE="" +CONFIG_EFI_STUB=y +CONFIG_EFI=y +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_STACKPROTECTOR_PER_TASK=y +# end of Boot options + +CONFIG_PORTABLE=y + +# +# Power management options +# +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_PM_SLEEP_DEBUG=y +CONFIG_DPM_WATCHDOG=y +CONFIG_DPM_WATCHDOG_TIMEOUT=60 +CONFIG_PM_CLK=y +CONFIG_PM_GENERIC_DOMAINS=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_CPU_PM=y +CONFIG_ENERGY_MODEL=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_HIBERNATION_HEADER=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_GOV_TEO=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DT_IDLE_GENPD=y + +# +# RISC-V CPU Idle Drivers +# +CONFIG_RISCV_SBI_CPUIDLE=y +# end of RISC-V CPU Idle Drivers +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +# end of CPU Frequency scaling +# end of CPU Power Management + +CONFIG_HAVE_KVM_EVENTFD=y +CONFIG_KVM_MMIO=y +CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y +CONFIG_HAVE_KVM_VCPU_ASYNC_IOCTL=y +CONFIG_KVM_XFER_TO_GUEST_WORK=y +CONFIG_KVM_GENERIC_HARDWARE_ENABLING=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_GENERIC_ENTRY=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_KRETPROBES=y +CONFIG_KRETPROBE_ON_RETHOOK=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_LTO_NONE=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_VDSO_DATA=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_FUNCTION_ALIGNMENT=0 +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_DEBUG is not set +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLK_RQ_ALLOC_TIME=y +CONFIG_BLK_CGROUP_RWSTAT=y +CONFIG_BLK_CGROUP_PUNT_BIO=y +CONFIG_BLK_DEV_BSG_COMMON=y +CONFIG_BLK_ICQ=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_WBT=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_CGROUP_IOLATENCY=y +# CONFIG_BLK_CGROUP_FC_APPID is not set +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEBUG_FS_ZONED=y +# CONFIG_BLK_SED_OPAL is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +CONFIG_OSF_PARTITION=y +# CONFIG_AMIGA_PARTITION is not set +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +CONFIG_BSD_DISKLABEL=y +# CONFIG_MINIX_SUBPARTITION is not set +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_SYSV68_PARTITION=y +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_BLK_PM=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +CONFIG_IOSCHED_BFQ=y +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFQ_CGROUP_DEBUG is not set +# end of IO Schedulers + +CONFIG_PREEMPT_NOTIFIERS=y +CONFIG_PADATA=y +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_MMIOWB=y +CONFIG_MMIOWB=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_ARCH_HAS_BINFMT_FLAT=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_ZPOOL=y +CONFIG_SWAP=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_DEFAULT_ON is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +CONFIG_ZBUD=y +CONFIG_Z3FOLD=m +CONFIG_ZSMALLOC=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set +CONFIG_SLAB_MERGE_DEFAULT=y +CONFIG_SLAB_FREELIST_RANDOM=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_ARCH_WANT_OPTIMIZE_VMEMMAP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_MEMORY_BALLOON=y +CONFIG_BALLOON_COMPACTION=y +CONFIG_COMPACTION=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_PAGE_REPORTING=y +CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_THP_SWAP=y +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMA_AREAS=7 +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_DEFERRED_STRUCT_PAGE_INIT=y +CONFIG_PAGE_IDLE_FLAG=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ZONE_DMA32=y +CONFIG_HMM_MIRROR=y +CONFIG_GET_FREE_REGION=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +# CONFIG_DMAPOOL_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +CONFIG_SECRETMEM=y +CONFIG_ANON_VMA_NAME=y +CONFIG_USERFAULTFD=y +CONFIG_LRU_GEN=y +# CONFIG_LRU_GEN_ENABLED is not set +# CONFIG_LRU_GEN_STATS is not set + +# +# Data Access Monitoring +# +CONFIG_DAMON=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_DBGFS=y +CONFIG_DAMON_RECLAIM=y +# CONFIG_DAMON_LRU_SORT is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_NET_REDIRECT=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=m +CONFIG_PACKET_DIAG=m +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_DIAG=m +CONFIG_TLS=m +CONFIG_TLS_DEVICE=y +# CONFIG_TLS_TOE is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=m +CONFIG_XFRM_USER=m +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=m +CONFIG_XFRM_ESP=m +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_XFRM_ESPINTCP=y +CONFIG_SMC=m +CONFIG_SMC_DIAG=m +CONFIG_XDP_SOCKETS=y +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_NET_HANDSHAKE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IP_TUNNEL=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=m +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_FOU=m +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_ESPINTCP=y +CONFIG_INET_IPCOMP=m +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_BBR=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_IPV6_ILA=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_FOU=m +CONFIG_IPV6_FOU_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_BPF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_NETLABEL=y +CONFIG_MPTCP=y +CONFIG_INET_MPTCP_DIAG=m +CONFIG_MPTCP_IPV6=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_SKIP_EGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_BPF_LINK=y +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CONNTRACK_OVS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_BROADCAST=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_NF_NAT=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NF_NAT_OVS=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_INET=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m +# CONFIG_NF_FLOW_TABLE_PROCFS is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_SET=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m +CONFIG_IP_VS_IPV6=y +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_TAB_BITS=12 + +# +# IPVS transport protocol load balancing support +# +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_AH_ESP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_SCTP=y + +# +# IPVS scheduler +# +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_TWOS=m + +# +# IPVS SH scheduler +# +CONFIG_IP_VS_SH_TAB_BITS=8 + +# +# IPVS MH scheduler +# +CONFIG_IP_VS_MH_TAB_INDEX=12 + +# +# IPVS application helper +# +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_NFCT=y +CONFIG_IP_VS_PE_SIP=m + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BPFILTER=y +# CONFIG_BPFILTER_UMH is not set +CONFIG_IP_DCCP=m +CONFIG_INET_DCCP_DIAG=m + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y +# end of DCCP CCIDs Configuration + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +CONFIG_INET_SCTP_DIAG=m +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +# CONFIG_RDS_DEBUG is not set +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_ATM=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_L2TP=m +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_V3=y +CONFIG_L2TP_IP=m +CONFIG_L2TP_ETH=m +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_MRP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BRIDGE_MRP=y +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=m +CONFIG_NET_DSA_TAG_NONE=m +CONFIG_NET_DSA_TAG_AR9331=m +CONFIG_NET_DSA_TAG_BRCM_COMMON=m +CONFIG_NET_DSA_TAG_BRCM=m +CONFIG_NET_DSA_TAG_BRCM_LEGACY=m +CONFIG_NET_DSA_TAG_BRCM_PREPEND=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_DSA_COMMON=m +CONFIG_NET_DSA_TAG_DSA=m +CONFIG_NET_DSA_TAG_EDSA=m +CONFIG_NET_DSA_TAG_MTK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_QCA=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_LAN9303=m +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +CONFIG_NET_DSA_TAG_XRS700X=m +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_LLC=m +CONFIG_LLC2=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_PHONET=m +CONFIG_6LOWPAN=m +# CONFIG_6LOWPAN_DEBUGFS is not set +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_IEEE802154=m +CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y +CONFIG_IEEE802154_SOCKET=m +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_MQPRIO_LIB=m +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_SKBPRIO=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_CODEL=m +CONFIG_NET_SCH_FQ_CODEL=m +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_ETS=m +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_GACT=m +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_IPT=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_SCH_FIFO=y +CONFIG_DCB=y +CONFIG_DNS_RESOLVER=m +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_DEBUG=y +# CONFIG_BATMAN_ADV_TRACING is not set +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO_VSOCKETS_COMMON=m +CONFIG_NETLINK_DIAG=m +CONFIG_MPLS=y +CONFIG_NET_MPLS_GSO=m +CONFIG_MPLS_ROUTING=m +CONFIG_MPLS_IPTUNNEL=m +CONFIG_NET_NSH=m +CONFIG_HSR=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_QRTR_MHI=m +CONFIG_NET_NCSI=y +CONFIG_NCSI_OEM_CMD_GET_MAC=y +# CONFIG_NCSI_OEM_CMD_KEEP_PHY is not set +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=m +CONFIG_NET_DROP_MONITOR=y +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_NETROM=m +CONFIG_ROSE=m + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +CONFIG_6PACK=m +CONFIG_BPQETHER=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +CONFIG_BAYCOM_PAR=m +CONFIG_YAM=m +# end of AX.25 network device drivers + +CONFIG_CAN=m +CONFIG_CAN_RAW=m +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m +CONFIG_BT=m +CONFIG_BT_BREDR=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LE=y +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +# CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_INTEL=m +CONFIG_BT_BCM=m +CONFIG_BT_RTL=m +CONFIG_BT_QCA=m +CONFIG_BT_MTK=m +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_ATH3K=m +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_HCIRSI=m +CONFIG_BT_VIRTIO=m +CONFIG_BT_NXPUART=m +# end of Bluetooth device drivers + +CONFIG_AF_RXRPC=m +CONFIG_AF_RXRPC_IPV6=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +# CONFIG_AF_RXRPC_DEBUG is not set +CONFIG_RXKAD=y +# CONFIG_RXPERF is not set +CONFIG_AF_KCM=m +CONFIG_STREAM_PARSER=y +CONFIG_MCTP=y +CONFIG_MCTP_FLOWS=y +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y +CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_CFG80211_WEXT_EXPORT=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=m +CONFIG_NET_9P=m +CONFIG_NET_9P_FD=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_RDMA=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_CAIF=m +# CONFIG_CAIF_DEBUG is not set +CONFIG_CAIF_NETDEV=m +CONFIG_CAIF_USB=m +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_NFC=m +CONFIG_NFC_DIGITAL=m +CONFIG_NFC_NCI=m +# CONFIG_NFC_NCI_SPI is not set +CONFIG_NFC_NCI_UART=m +CONFIG_NFC_HCI=m +CONFIG_NFC_SHDLC=y + +# +# Near Field Communication (NFC) devices +# +# CONFIG_NFC_TRF7970A is not set +CONFIG_NFC_SIM=m +CONFIG_NFC_PORT100=m +CONFIG_NFC_VIRTUAL_NCI=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_PN544=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_MICROREAD=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MRVL=m +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_MRVL_UART=m +CONFIG_NFC_MRVL_I2C=m +CONFIG_NFC_ST21NFCA=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST_NCI=m +CONFIG_NFC_ST_NCI_I2C=m +CONFIG_NFC_ST_NCI_SPI=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_S3FWRN5=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_NFC_S3FWRN82_UART=m +CONFIG_NFC_ST95HF=m +# end of Near Field Communication (NFC) devices + +CONFIG_PSAMPLE=m +CONFIG_NET_IFE=m +CONFIG_LWTUNNEL=y +CONFIG_LWTUNNEL_BPF=y +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_SOCK_VALIDATE_XMIT=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_FAILOVER=m +CONFIG_ETHTOOL_NETLINK=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +CONFIG_PCIEAER_INJECT=m +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +CONFIG_PCIE_DPC=y +CONFIG_PCIE_PTM=y +CONFIG_PCI_MSI=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_ATS=y +CONFIG_PCI_DOE=y +CONFIG_PCI_ECAM=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_HOTPLUG_PCI=y +CONFIG_HOTPLUG_PCI_CPCI=y +CONFIG_HOTPLUG_PCI_SHPC=y + +# +# PCI controller drivers +# +CONFIG_PCI_FTPCI100=y +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_PCIE_RCAR_HOST=y +CONFIG_PCIE_RCAR_EP=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_STARFIVE=m + +# +# Cadence-based PCIe controllers +# +CONFIG_PCIE_CADENCE=y +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_EP=y +CONFIG_PCIE_CADENCE_PLAT=y +CONFIG_PCIE_CADENCE_PLAT_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +CONFIG_PCI_J721E=y +CONFIG_PCI_J721E_HOST=y +CONFIG_PCI_J721E_EP=y +# end of Cadence-based PCIe controllers + +# +# DesignWare-based PCIe controllers +# +CONFIG_PCIE_DW=y +CONFIG_PCIE_DW_HOST=y +CONFIG_PCIE_DW_EP=y +CONFIG_PCI_MESON=y +CONFIG_PCIE_DW_PLAT=y +CONFIG_PCIE_DW_PLAT_HOST=y +CONFIG_PCIE_DW_PLAT_EP=y +CONFIG_PCIE_FU740=y +# end of DesignWare-based PCIe controllers + +# +# Mobiveil-based PCIe controllers +# +# end of Mobiveil-based PCIe controllers +# end of PCI controller drivers + +# +# PCI Endpoint +# +CONFIG_PCI_ENDPOINT=y +CONFIG_PCI_ENDPOINT_CONFIGFS=y +CONFIG_PCI_EPF_TEST=m +CONFIG_PCI_EPF_NTB=m +CONFIG_PCI_EPF_VNTB=m +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +CONFIG_PCI_SW_SWITCHTEC=m +# end of PCI switch controller drivers + +CONFIG_CXL_BUS=m +CONFIG_CXL_PCI=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PMEM=m +CONFIG_CXL_MEM=m +CONFIG_CXL_PORT=m +CONFIG_CXL_REGION=y +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_PCCARD=m +CONFIG_PCMCIA=m +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +CONFIG_YENTA=m +CONFIG_YENTA_O2=y +CONFIG_YENTA_RICOH=y +CONFIG_YENTA_TI=y +CONFIG_YENTA_ENE_TUNE=y +CONFIG_YENTA_TOSHIBA=y +CONFIG_PD6729=m +CONFIG_I82092=m +CONFIG_PCCARD_NONSTATIC=y +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_MPORT_CDEV=m + +# +# RapidIO Switch drivers +# +CONFIG_RAPIDIO_CPS_XX=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_RXS_GEN3=m +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_AUXILIARY_BUS=y +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_DEBUG=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_CACHE=y +CONFIG_FW_UPLOAD=y +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +CONFIG_ALLOW_DEV_COREDUMP=y +CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP_SPMI=m +CONFIG_REGMAP_W1=m +CONFIG_REGMAP_MMIO=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_SOUNDWIRE=m +CONFIG_REGMAP_SOUNDWIRE_MBQ=m +CONFIG_REGMAP_SCCB=m +CONFIG_REGMAP_I3C=m +CONFIG_REGMAP_SPI_AVMM=m +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_ARCH_NUMA=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +# end of Generic Driver Options + +# +# Bus devices +# +CONFIG_MOXTET=m +CONFIG_SUN50I_DE2_BUS=y +CONFIG_SUNXI_RSB=m +CONFIG_MHI_BUS=m +# CONFIG_MHI_BUS_DEBUG is not set +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_BUS_EP=m +# end of Bus devices + +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# end of ARM System Control and Management Interface Protocol + +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_SYSFB=y +# CONFIG_SYSFB_SIMPLEFB is not set +CONFIG_FW_CS_DSP=m +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=m +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_PARAMS_FROM_FDT=y +CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB=y +# CONFIG_EFI_ZBOOT is not set +CONFIG_EFI_BOOTLOADER_CONTROL=m +CONFIG_EFI_CAPSULE_LOADER=m +# CONFIG_EFI_TEST is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set +CONFIG_EFI_EARLYCON=y +# CONFIG_EFI_DISABLE_RUNTIME is not set +# CONFIG_EFI_COCO_SECRET is not set +# end of EFI (Extensible Firmware Interface) Support + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_GNSS=m +CONFIG_GNSS_SERIAL=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +CONFIG_MTD=m +CONFIG_MTD_TESTS=m + +# +# Partition parsers +# +CONFIG_MTD_AR7_PARTS=m +CONFIG_MTD_CMDLINE_PARTS=m +CONFIG_MTD_OF_PARTS=m +CONFIG_MTD_REDBOOT_PARTS=m +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 +# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set +# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK_RO=m + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +CONFIG_FTL=m +CONFIG_NFTL=m +CONFIG_NFTL_RW=y +CONFIG_INFTL=m +CONFIG_RFD_FTL=m +CONFIG_SSFDC=m +# CONFIG_SM_FTL is not set +CONFIG_MTD_OOPS=m +# CONFIG_MTD_PSTORE is not set +CONFIG_MTD_SWAP=m +CONFIG_MTD_PARTITIONED_MASTER=y + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_MAP_BANK_WIDTH_8=y +CONFIG_MTD_MAP_BANK_WIDTH_16=y +CONFIG_MTD_MAP_BANK_WIDTH_32=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_I4=y +CONFIG_MTD_CFI_I8=y +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +CONFIG_MTD_RAM=m +CONFIG_MTD_ROM=m +CONFIG_MTD_ABSENT=m +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP_GPIO_ADDR=y +CONFIG_MTD_PCI=m +CONFIG_MTD_PCMCIA=m +# CONFIG_MTD_PCMCIA_ANONYMOUS is not set +CONFIG_MTD_INTEL_VR_NOR=m +CONFIG_MTD_PLATRAM=m +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +CONFIG_MTD_PMC551=m +CONFIG_MTD_PMC551_BUGFIX=y +# CONFIG_MTD_PMC551_DEBUG is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_MCHP23K256=m +CONFIG_MTD_MCHP48L640=m +# CONFIG_MTD_SST25L is not set +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTDRAM_ERASE_SIZE=128 +CONFIG_MTD_BLOCK2MTD=m + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +CONFIG_MTD_NAND_CORE=m +CONFIG_MTD_ONENAND=m +CONFIG_MTD_ONENAND_VERIFY_WRITE=y +CONFIG_MTD_ONENAND_GENERIC=m +CONFIG_MTD_ONENAND_OTP=y +CONFIG_MTD_ONENAND_2X_PROGRAM=y +CONFIG_MTD_RAW_NAND=m + +# +# Raw/parallel NAND flash controllers +# +CONFIG_MTD_NAND_DENALI=m +# CONFIG_MTD_NAND_DENALI_PCI is not set +CONFIG_MTD_NAND_DENALI_DT=m +CONFIG_MTD_NAND_CAFE=m +CONFIG_MTD_NAND_SUNXI=m +CONFIG_MTD_NAND_MXIC=m +CONFIG_MTD_NAND_GPIO=m +CONFIG_MTD_NAND_PLATFORM=m +CONFIG_MTD_NAND_CADENCE=m +CONFIG_MTD_NAND_ARASAN=m +CONFIG_MTD_NAND_INTEL_LGM=m +CONFIG_MTD_NAND_RENESAS=m + +# +# Misc +# +CONFIG_MTD_SM_COMMON=m +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_MTD_NAND_RICOH=m +CONFIG_MTD_NAND_DISKONCHIP=m +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x0 +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y +CONFIG_MTD_SPI_NAND=m + +# +# ECC engine support +# +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_NAND_ECC_MXIC=y +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=m +CONFIG_MTD_UBI_BLOCK=y +CONFIG_MTD_HYPERBUS=m +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_NUMA=y +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +CONFIG_PARPORT_1284=y +CONFIG_PARPORT_NOT_PC=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_CDROM=m +CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m +CONFIG_ZRAM=m +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +CONFIG_ZRAM_DEF_COMP="lzo-rle" +CONFIG_ZRAM_WRITEBACK=y +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_DRBD=m +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=131072 +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +CONFIG_VIRTIO_BLK=m +CONFIG_BLK_DEV_RBD=m +# CONFIG_BLK_DEV_UBLK is not set +CONFIG_BLK_DEV_RNBD=y +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m + +# +# NVME Support +# +CONFIG_NVME_CORE=m +CONFIG_BLK_DEV_NVME=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +CONFIG_NVME_HWMON=y +CONFIG_NVME_FABRICS=m +CONFIG_NVME_RDMA=m +CONFIG_NVME_FC=m +CONFIG_NVME_TCP=m +# CONFIG_NVME_AUTH is not set +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_TCP=m +# CONFIG_NVME_TARGET_AUTH is not set +# end of NVME Support + +# +# Misc devices +# +CONFIG_SENSORS_LIS3LV02D=y +CONFIG_AD525X_DPOT=m +CONFIG_AD525X_DPOT_I2C=m +# CONFIG_AD525X_DPOT_SPI is not set +CONFIG_DUMMY_IRQ=m +CONFIG_PHANTOM=m +CONFIG_TIFM_CORE=m +CONFIG_TIFM_7XX1=m +CONFIG_ICS932S401=m +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_SMPRO_ERRMON=m +CONFIG_SMPRO_MISC=m +CONFIG_HI6421V600_IRQ=m +CONFIG_HP_ILO=m +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +CONFIG_ISL29020=m +CONFIG_SENSORS_TSL2550=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_APDS990X=m +CONFIG_HMC6352=m +CONFIG_DS1682=m +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +CONFIG_DW_XDATA_PCIE=m +CONFIG_PCI_ENDPOINT_TEST=m +CONFIG_XILINX_SDFEC=m +CONFIG_MISC_RTSX=m +CONFIG_HISI_HIKEY_USB=m +CONFIG_OPEN_DICE=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_C2PORT=m + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +CONFIG_EEPROM_MAX6875=m +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_EE1004=m +# end of EEPROM support + +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +CONFIG_CB710_DEBUG_ASSUMPTIONS=y + +# +# Texas Instruments shared transport line discipline +# +CONFIG_TI_ST=m +# end of Texas Instruments shared transport line discipline + +CONFIG_SENSORS_LIS3_SPI=y +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_ALTERA_STAPL=m +CONFIG_GENWQE=m +CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 +CONFIG_ECHO=m +CONFIG_BCM_VK=m +# CONFIG_BCM_VK_TTY is not set +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_UACCE=m +CONFIG_PVPANIC=y +CONFIG_PVPANIC_MMIO=m +CONFIG_PVPANIC_PCI=m +CONFIG_GP_PCI1XXXX=m +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +CONFIG_RAID_ATTRS=m +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_NETLINK=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_ST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_BLK_DEV_BSG=y +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SRP_ATTRS=m +# end of SCSI Transports + +CONFIG_SCSI_LOWLEVEL=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_BE2ISCSI=m +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_ACARD=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_AIC7XXX=m +CONFIG_AIC7XXX_CMDS_PER_DEVICE=32 +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +CONFIG_AIC7XXX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC79XX=m +CONFIG_AIC79XX_CMDS_PER_DEVICE=32 +CONFIG_AIC79XX_RESET_DELAY_MS=5000 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +CONFIG_AIC79XX_REG_PRETTY_PRINT=y +CONFIG_SCSI_AIC94XX=m +# CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_ADVANSYS=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_ESAS2R=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_SAS=m +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_SMARTPQI=m +CONFIG_SCSI_HPTIOP=m +CONFIG_SCSI_BUSLOGIC=m +# CONFIG_SCSI_FLASHPOINT is not set +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_FCOE=m +CONFIG_SCSI_SNIC=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_DMX3191D=m +CONFIG_SCSI_FDOMAIN=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_IPS=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_QLA_FC=m +CONFIG_TCM_QLA2XXX=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_QEDI=m +CONFIG_QEDF=m +CONFIG_SCSI_LPFC=m +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_PMCRAID=m +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_LOWLEVEL_PCMCIA=y +CONFIG_PCMCIA_AHA152X=m +CONFIG_PCMCIA_FDOMAIN=m +CONFIG_PCMCIA_QLOGIC=m +CONFIG_PCMCIA_SYM53C500=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_AHCI_DWC=m +CONFIG_AHCI_CEVA=m +CONFIG_AHCI_SUNXI=m +CONFIG_SATA_INIC162X=m +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_SIL24=m +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_PDC_ADMA=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SX4=m +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=m +CONFIG_SATA_DWC=m +CONFIG_SATA_DWC_OLD_DMA=y +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PROMISE=m +CONFIG_SATA_RCAR=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m + +# +# PATA SFF controllers with BMDMA +# +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +CONFIG_PATA_ATIIXP=m +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CYPRESS=m +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +CONFIG_PATA_HPT3X3=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +CONFIG_PATA_MARVELL=m +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87415=m +CONFIG_PATA_OLDPIIX=m +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +CONFIG_PATA_RADISYS=m +CONFIG_PATA_RDC=m +CONFIG_PATA_SCH=m +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +CONFIG_PATA_TOSHIBA=m +CONFIG_PATA_TRIFLEX=m +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m + +# +# PIO-only SFF controllers +# +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_MPIIX=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_OPTI=m +CONFIG_PATA_PCMCIA=m +# CONFIG_PATA_OF_PLATFORM is not set +CONFIG_PATA_RZ1000=m + +# +# Generic fallback / legacy drivers +# +CONFIG_ATA_GENERIC=m +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_MD_CLUSTER=m +CONFIG_BCACHE=m +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_BUFIO=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +CONFIG_DM_BIO_PRISON=m +CONFIG_DM_PERSISTENT_DATA=m +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_WRITECACHE=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_CLONE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +CONFIG_DM_VERITY=m +# CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG is not set +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_SWITCH=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_INTEGRITY=m +CONFIG_DM_ZONED=m +CONFIG_DM_AUDIT=y +CONFIG_TARGET_CORE=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_PSCSI=m +CONFIG_TCM_USER2=m +CONFIG_LOOPBACK_TARGET=m +CONFIG_TCM_FC=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_SBP_TARGET=m +CONFIG_REMOTE_TARGET=m +CONFIG_FUSION=y +CONFIG_FUSION_SPI=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_SAS=m +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_CTL=m +CONFIG_FUSION_LAN=m +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +CONFIG_FIREWIRE=m +CONFIG_FIREWIRE_OHCI=m +CONFIG_FIREWIRE_SBP2=m +CONFIG_FIREWIRE_NET=m +CONFIG_FIREWIRE_NOSY=m +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=m +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_EQUALIZER=m +CONFIG_NET_FC=y +CONFIG_IFB=m +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN_L3S=y +CONFIG_IPVLAN=m +CONFIG_IPVTAP=m +CONFIG_VXLAN=m +CONFIG_GENEVE=m +CONFIG_BAREUDP=m +CONFIG_GTP=m +CONFIG_AMT=m +CONFIG_MACSEC=m +CONFIG_NETCONSOLE=m +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NTB_NETDEV=m +CONFIG_RIONET=m +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RIONET_RX_SIZE=128 +CONFIG_TUN=m +CONFIG_TAP=m +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_MHI_NET=m +CONFIG_SUNGEM_PHY=m +# CONFIG_ARCNET is not set +CONFIG_ATM_DRIVERS=y +CONFIG_ATM_DUMMY=m +CONFIG_ATM_TCP=m +CONFIG_ATM_LANAI=m +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI_TUNE_BURST=y +CONFIG_ATM_ENI_BURST_TX_16W=y +CONFIG_ATM_ENI_BURST_TX_8W=y +CONFIG_ATM_ENI_BURST_TX_4W=y +CONFIG_ATM_ENI_BURST_TX_2W=y +CONFIG_ATM_ENI_BURST_RX_16W=y +CONFIG_ATM_ENI_BURST_RX_8W=y +CONFIG_ATM_ENI_BURST_RX_4W=y +CONFIG_ATM_ENI_BURST_RX_2W=y +CONFIG_ATM_NICSTAR=m +CONFIG_ATM_NICSTAR_USE_SUNI=y +CONFIG_ATM_NICSTAR_USE_IDT77105=y +CONFIG_ATM_IDT77252=m +# CONFIG_ATM_IDT77252_DEBUG is not set +# CONFIG_ATM_IDT77252_RCV_ALL is not set +CONFIG_ATM_IDT77252_USE_SUNI=y +CONFIG_ATM_IA=m +# CONFIG_ATM_IA_DEBUG is not set +CONFIG_ATM_FORE200E=m +CONFIG_ATM_FORE200E_USE_TASKLET=y +CONFIG_ATM_FORE200E_TX_RETRY=16 +CONFIG_ATM_FORE200E_DEBUG=0 +CONFIG_ATM_HE=m +CONFIG_ATM_HE_USE_SUNI=y +CONFIG_ATM_SOLOS=m +# CONFIG_CAIF_DRIVERS is not set + +# +# Distributed Switch Architecture drivers +# +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +CONFIG_NET_DSA_LANTIQ_GSWIP=m +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +CONFIG_NET_DSA_MV88E6060=m +CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_SPI is not set +CONFIG_NET_DSA_MICROCHIP_KSZ_PTP=y +CONFIG_NET_DSA_MICROCHIP_KSZ8863_SMI=m +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=m +CONFIG_NET_DSA_MSCC_OCELOT_EXT=m +CONFIG_NET_DSA_MSCC_SEVILLE=m +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_SJA1105=m +CONFIG_NET_DSA_SJA1105_PTP=y +CONFIG_NET_DSA_SJA1105_TAS=y +CONFIG_NET_DSA_SJA1105_VL=y +CONFIG_NET_DSA_XRS700X=m +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_DSA_REALTEK=m +CONFIG_NET_DSA_REALTEK_MDIO=m +CONFIG_NET_DSA_REALTEK_SMI=m +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +CONFIG_NET_DSA_SMSC_LAN9303=m +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +CONFIG_NET_DSA_VITESSE_VSC73XX=m +CONFIG_NET_DSA_VITESSE_VSC73XX_SPI=m +CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM=m +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_PCMCIA_3C574=m +CONFIG_PCMCIA_3C589=m +CONFIG_VORTEX=m +CONFIG_TYPHOON=m +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_ADAPTEC_STARFIRE=m +CONFIG_NET_VENDOR_AGERE=y +CONFIG_ET131X=m +CONFIG_NET_VENDOR_ALACRITECH=y +CONFIG_SLICOSS=m +CONFIG_NET_VENDOR_ALLWINNER=y +CONFIG_SUN4I_EMAC=m +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_ENA_ETHERNET=m +CONFIG_NET_VENDOR_AMD=y +CONFIG_AMD8111_ETH=m +CONFIG_PCNET32=m +CONFIG_PCMCIA_NMCLAN=m +CONFIG_PDS_CORE=m +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_AQTION=m +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AX88796C_COMPRESSION is not set +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_ATL2=m +CONFIG_ATL1=m +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_ALX=m +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_BCMGENET=m +CONFIG_BNX2=m +CONFIG_CNIC=m +CONFIG_TIGON3=m +CONFIG_TIGON3_HWMON=y +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_SYSTEMPORT=m +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_HWMON=y +CONFIG_NET_VENDOR_CADENCE=y +CONFIG_MACB=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MACB_PCI=m +CONFIG_NET_VENDOR_CAVIUM=y +CONFIG_THUNDER_NIC_PF=m +CONFIG_THUNDER_NIC_VF=m +CONFIG_THUNDER_NIC_BGX=m +CONFIG_THUNDER_NIC_RGX=m +CONFIG_CAVIUM_PTP=m +CONFIG_LIQUIDIO=m +CONFIG_LIQUIDIO_VF=m +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4_DCB=y +CONFIG_CHELSIO_T4_FCOE=y +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_LIB=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_NET_VENDOR_CISCO=y +CONFIG_ENIC=m +CONFIG_NET_VENDOR_CORTINA=y +CONFIG_GEMINI_ETHERNET=m +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_DM9051=m +CONFIG_DNET=m +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +CONFIG_DE2104X=m +CONFIG_DE2104X_DSL=0 +CONFIG_TULIP=m +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_MMIO is not set +CONFIG_TULIP_NAPI=y +CONFIG_TULIP_NAPI_HW_MITIGATION=y +CONFIG_WINBOND_840=m +CONFIG_DM9102=m +CONFIG_ULI526X=m +CONFIG_PCMCIA_XIRCOM=m +CONFIG_NET_VENDOR_DLINK=y +CONFIG_DL2K=m +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_BE2NET=m +CONFIG_BE2NET_HWMON=y +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET_SKYHAWK=y +CONFIG_NET_VENDOR_ENGLEDER=y +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_FUJITSU=y +CONFIG_PCMCIA_FMVJ18X=m +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_FUN_CORE=m +CONFIG_FUN_ETH=m +CONFIG_NET_VENDOR_GOOGLE=y +CONFIG_NET_VENDOR_HUAWEI=y +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=m +CONFIG_E1000=m +CONFIG_E1000E=m +CONFIG_IGB=m +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=m +CONFIG_IXGBE=m +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_I40E=m +CONFIG_I40E_DCB=y +CONFIG_IAVF=m +CONFIG_I40EVF=m +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_FM10K=m +CONFIG_IGC=m +CONFIG_JME=m +CONFIG_NET_VENDOR_ADI=y +CONFIG_ADIN1110=m +CONFIG_NET_VENDOR_LITEX=y +CONFIG_LITEX_LITEETH=m +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_MVMDIO=m +CONFIG_SKGE=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKY2=m +# CONFIG_SKY2_DEBUG is not set +# CONFIG_OCTEON_EP is not set +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_ESWITCH=y +CONFIG_MLX5_BRIDGE=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_IPOIB=y +# CONFIG_MLX5_EN_MACSEC is not set +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SF_MANAGER=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXFW=m +CONFIG_NET_VENDOR_MICREL=y +CONFIG_KS8842=m +CONFIG_KS8851=m +CONFIG_KS8851_MLL=m +CONFIG_KSZ884X_PCI=m +CONFIG_NET_VENDOR_MICROCHIP=y +CONFIG_ENC28J60=m +# CONFIG_ENC28J60_WRITEVERIFY is not set +CONFIG_ENCX24J600=m +CONFIG_LAN743X=m +CONFIG_LAN966X_SWITCH=m +CONFIG_VCAP=y +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_MSCC_OCELOT_SWITCH_LIB=m +CONFIG_MSCC_OCELOT_SWITCH=m +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_MYRI10GE=m +CONFIG_FEALNX=m +CONFIG_NET_VENDOR_NI=y +CONFIG_NI_XGE_MANAGEMENT_ENET=m +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NATSEMI=m +CONFIG_NS83820=m +CONFIG_NET_VENDOR_NETERION=y +CONFIG_S2IO=m +CONFIG_NET_VENDOR_NETRONOME=y +CONFIG_NFP=m +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_APP_ABM_NIC=y +CONFIG_NFP_NET_IPSEC=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NET_VENDOR_8390=y +CONFIG_PCMCIA_AXNET=m +CONFIG_NE2K_PCI=m +CONFIG_PCMCIA_PCNET=m +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=m +CONFIG_NET_VENDOR_OKI=y +CONFIG_ETHOC=m +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_HAMACHI=m +CONFIG_YELLOWFIN=m +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_IONIC=m +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_NETXEN_NIC=m +CONFIG_QED=m +CONFIG_QED_LL2=y +CONFIG_QED_SRIOV=y +CONFIG_QEDE=m +CONFIG_QED_RDMA=y +CONFIG_QED_ISCSI=y +CONFIG_QED_FCOE=y +CONFIG_QED_OOO=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_BNA=m +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_QCA7000=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_QCOM_EMAC=m +CONFIG_RMNET=m +CONFIG_NET_VENDOR_RDC=y +CONFIG_R6040=m +CONFIG_NET_VENDOR_REALTEK=y +CONFIG_8139CP=m +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_8139TOO_8129=y +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=m +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_SH_ETH=m +CONFIG_RAVB=m +CONFIG_RENESAS_ETHER_SWITCH=m +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_ROCKER=m +CONFIG_NET_VENDOR_SAMSUNG=y +CONFIG_SXGBE_ETH=m +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SILAN=y +CONFIG_SC92031=m +CONFIG_NET_VENDOR_SIS=y +CONFIG_SIS900=m +CONFIG_SIS190=m +CONFIG_NET_VENDOR_SOLARFLARE=y +CONFIG_SFC=m +CONFIG_SFC_MTD=y +CONFIG_SFC_MCDI_MON=y +CONFIG_SFC_SRIOV=y +CONFIG_SFC_MCDI_LOGGING=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC_SIENA is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_PCMCIA_SMC91C92=m +CONFIG_EPIC100=m +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_SELFTESTS is not set +CONFIG_STMMAC_PLATFORM=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_SUNXI=m +CONFIG_DWMAC_SUN8I=m +CONFIG_DWMAC_INTEL_PLAT=m +CONFIG_DWMAC_LOONGSON=m +CONFIG_STMMAC_PCI=m +CONFIG_NET_VENDOR_SUN=y +CONFIG_HAPPYMEAL=m +CONFIG_SUNGEM=m +CONFIG_CASSINI=m +CONFIG_NIU=m +CONFIG_NET_VENDOR_SYNOPSYS=y +CONFIG_DWC_XLGMAC=m +CONFIG_DWC_XLGMAC_PCI=m +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_TEHUTI=m +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +CONFIG_TLAN=m +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_MSE102X=m +CONFIG_NET_VENDOR_VIA=y +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_LIBWX=m +CONFIG_NGBE=m +# CONFIG_TXGBE is not set +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5300=m +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_WIZNET_W5100_SPI=m +CONFIG_NET_VENDOR_XILINX=y +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_AXI_EMAC=m +CONFIG_XILINX_LL_TEMAC=m +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_PCMCIA_XIRC2PS=m +CONFIG_FDDI=m +CONFIG_DEFXX=m +CONFIG_SKFP=m +CONFIG_HIPPI=y +CONFIG_ROADRUNNER=m +# CONFIG_ROADRUNNER_LARGE_RINGS is not set +CONFIG_PHYLINK=m +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +CONFIG_LED_TRIGGER_PHY=y +CONFIG_PHYLIB_LEDS=y +CONFIG_FIXED_PHY=y +CONFIG_SFP=m + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIN1100_PHY is not set +CONFIG_AQUANTIA_PHY=m +CONFIG_AX88796B_PHY=m +CONFIG_BROADCOM_PHY=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +CONFIG_BCM84881_PHY=y +CONFIG_BCM87XX_PHY=m +CONFIG_BCM_NET_PHYLIB=m +CONFIG_CICADA_PHY=m +CONFIG_CORTINA_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_ICPLUS_PHY=m +CONFIG_LXT_PHY=m +CONFIG_INTEL_XWAY_PHY=m +CONFIG_LSI_ET1011C_PHY=m +CONFIG_MARVELL_PHY=m +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROCHIP_PHY=m +CONFIG_MICROCHIP_T1_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MOTORCOMM_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_NXP_CBTX_PHY=m +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_TJA11XX_PHY=m +CONFIG_NCN26000_PHY=m +CONFIG_AT803X_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_RENESAS_PHY=m +CONFIG_ROCKCHIP_PHY=m +CONFIG_SMSC_PHY=m +CONFIG_STE10XP=m +CONFIG_TERANETICS_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83TC811_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TD510_PHY is not set +CONFIG_VITESSE_PHY=m +CONFIG_XILINX_GMII2RGMII=m +CONFIG_MICREL_KS8995MA=m +# CONFIG_PSE_CONTROLLER is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_RX_OFFLOAD=y +# CONFIG_CAN_CAN327 is not set +CONFIG_CAN_FLEXCAN=m +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_KVASER_PCIEFD=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_C_CAN=m +# CONFIG_CAN_C_CAN_PLATFORM is not set +CONFIG_CAN_C_CAN_PCI=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_CTUCANFD_PCI is not set +# CONFIG_CAN_CTUCANFD_PLATFORM is not set +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +CONFIG_CAN_M_CAN_PLATFORM=m +CONFIG_CAN_M_CAN_TCAN4X5X=m +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_RCAR=m +CONFIG_CAN_RCAR_CANFD=m +CONFIG_CAN_SJA1000=m +CONFIG_CAN_EMS_PCI=m +CONFIG_CAN_EMS_PCMCIA=m +CONFIG_CAN_F81601=m +CONFIG_CAN_KVASER_PCI=m +CONFIG_CAN_PEAK_PCI=m +CONFIG_CAN_PEAK_PCIEC=y +CONFIG_CAN_PEAK_PCMCIA=m +CONFIG_CAN_PLX_PCI=m +# CONFIG_CAN_SJA1000_ISA is not set +# CONFIG_CAN_SJA1000_PLATFORM is not set +CONFIG_CAN_SOFTING=m +CONFIG_CAN_SOFTING_CS=m + +# +# CAN SPI interfaces +# +CONFIG_CAN_HI311X=m +# CONFIG_CAN_MCP251X is not set +# CONFIG_CAN_MCP251XFD is not set +# end of CAN SPI interfaces + +# +# CAN USB interfaces +# +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_USB is not set +CONFIG_CAN_ETAS_ES58X=m +CONFIG_CAN_GS_USB=m +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_UCAN=m +# end of CAN USB interfaces + +# CONFIG_CAN_DEBUG_DEVICES is not set + +# +# MCTP Device Drivers +# +CONFIG_MCTP_SERIAL=m +CONFIG_MCTP_TRANSPORT_I2C=m +# end of MCTP Device Drivers + +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_SUN4I=m +CONFIG_MDIO_BITBANG=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_CAVIUM=m +CONFIG_MDIO_GPIO=m +CONFIG_MDIO_HISI_FEMAC=m +CONFIG_MDIO_I2C=m +CONFIG_MDIO_MVUSB=m +CONFIG_MDIO_MSCC_MIIM=m +CONFIG_MDIO_OCTEON=m +CONFIG_MDIO_IPQ4019=m +CONFIG_MDIO_IPQ8064=m +CONFIG_MDIO_THUNDER=m + +# +# MDIO Multiplexers +# +CONFIG_MDIO_BUS_MUX=m +CONFIG_MDIO_BUS_MUX_GPIO=m +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=m +CONFIG_MDIO_BUS_MUX_MMIOREG=m + +# +# PCS device drivers +# +CONFIG_PCS_XPCS=m +CONFIG_PCS_LYNX=m +CONFIG_PCS_MTK_LYNXI=m +# end of PCS device drivers + +CONFIG_PLIP=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y + +# +# Host-side USB support is needed for USB Network Adapter support +# +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_CDC_PHONET=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_ADM8211=m +CONFIG_ATH_COMMON=m +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH5K_PCI=y +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +# CONFIG_ATH9K_DEBUGFS is not set +# CONFIG_ATH9K_DYNACK is not set +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_RFKILL=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HWRNG=y +CONFIG_CARL9170=m +CONFIG_CARL9170_LEDS=y +# CONFIG_CARL9170_DEBUGFS is not set +CONFIG_CARL9170_WPC=y +CONFIG_CARL9170_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +# CONFIG_ATH6KL_DEBUG is not set +# CONFIG_ATH6KL_TRACING is not set +CONFIG_AR5523=m +CONFIG_WIL6210=m +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210_TRACING=y +# CONFIG_WIL6210_DEBUGFS is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_USB=m +# CONFIG_ATH10K_DEBUG is not set +# CONFIG_ATH10K_DEBUGFS is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_WCN36XX=m +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_AHB=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K_DEBUGFS=y +# CONFIG_ATH11K_TRACING is not set +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATH12K=m +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K_TRACING=y +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PCMCIA_ATMEL=m +CONFIG_AT76C50X_USB=m +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_B43=m +CONFIG_B43_BCMA=y +CONFIG_B43_SSB=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_SDIO=y +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_PIO=y +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_N=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMSMAC=m +CONFIG_BRCMSMAC_LEDS=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PROTO_BCDC=y +CONFIG_BRCMFMAC_PROTO_MSGBUF=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMFMAC_PCIE=y +# CONFIG_BRCM_TRACING is not set +# CONFIG_BRCMDBG is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_AIRO=m +CONFIG_AIRO_CS=m +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_IPW2100=m +CONFIG_IPW2100_MONITOR=y +CONFIG_IPW2100_DEBUG=y +CONFIG_IPW2200=m +CONFIG_IPW2200_MONITOR=y +CONFIG_IPW2200_RADIOTAP=y +CONFIG_IPW2200_PROMISCUOUS=y +CONFIG_IPW2200_QOS=y +CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +CONFIG_LIBIPW_DEBUG=y +CONFIG_IWLEGACY=m +CONFIG_IWL4965=m +CONFIG_IWL3945=m + +# +# iwl3945 / iwl4965 Debugging Options +# +# CONFIG_IWLEGACY_DEBUG is not set +# CONFIG_IWLEGACY_DEBUGFS is not set +# end of iwl3945 / iwl4965 Debugging Options + +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_LEDS=y +CONFIG_IWLDVM=m +CONFIG_IWLMVM=m +CONFIG_IWLWIFI_OPMODE_MODULAR=y + +# +# Debugging Options +# +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEBUGFS=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +# end of Debugging Options + +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m +CONFIG_HOSTAP_CS=m +CONFIG_HERMES=m +CONFIG_HERMES_PRISM=y +CONFIG_HERMES_CACHE_FW_ON_INIT=y +CONFIG_PLX_HERMES=m +CONFIG_TMD_HERMES=m +CONFIG_NORTEL_HERMES=m +CONFIG_PCI_HERMES=m +CONFIG_PCMCIA_HERMES=m +CONFIG_PCMCIA_SPECTRUM=m +CONFIG_ORINOCO_USB=m +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +CONFIG_P54_PCI=m +# CONFIG_P54_SPI is not set +CONFIG_P54_LEDS=y +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_CS=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +CONFIG_LIBERTAS_MESH=y +CONFIG_LIBERTAS_THINFIRM=m +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_MT7601U=m +CONFIG_MT76_CORE=m +CONFIG_MT76_LEDS=y +CONFIG_MT76_USB=m +CONFIG_MT76_SDIO=m +CONFIG_MT76x02_LIB=m +CONFIG_MT76x02_USB=m +CONFIG_MT76_CONNAC_LIB=m +CONFIG_MT76x0_COMMON=m +CONFIG_MT76x0U=m +CONFIG_MT76x0E=m +CONFIG_MT76x2_COMMON=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7603E=m +CONFIG_MT7615_COMMON=m +CONFIG_MT7615E=m +CONFIG_MT7663_USB_SDIO_COMMON=m +CONFIG_MT7663U=m +CONFIG_MT7663S=m +CONFIG_MT7915E=m +CONFIG_MT7921_COMMON=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7996E=m +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WLAN_VENDOR_PURELIFI=y +# CONFIG_PLFXLC is not set +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2800_LIB_MMIO=m +CONFIG_RT2X00_LIB_MMIO=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_LIB_DEBUGFS is not set +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8187_LEDS=y +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CE=m +CONFIG_RTL8192SE=m +CONFIG_RTL8192DE=m +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192EE=m +CONFIG_RTL8821AE=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_PCI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +CONFIG_RTL8723_COMMON=m +CONFIG_RTLBTCOEXIST=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTW88=m +CONFIG_RTW88_CORE=m +CONFIG_RTW88_PCI=m +CONFIG_RTW88_SDIO=m +CONFIG_RTW88_USB=m +CONFIG_RTW88_8822B=m +CONFIG_RTW88_8822C=m +CONFIG_RTW88_8723D=m +CONFIG_RTW88_8821C=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +# CONFIG_RTW88_DEBUG is not set +# CONFIG_RTW88_DEBUGFS is not set +CONFIG_RTW89=m +CONFIG_RTW89_CORE=m +CONFIG_RTW89_PCI=m +CONFIG_RTW89_8852A=m +CONFIG_RTW89_8852B=m +CONFIG_RTW89_8852C=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852CE=m +# CONFIG_RTW89_DEBUGMSG is not set +# CONFIG_RTW89_DEBUGFS is not set +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_RSI_91X=m +# CONFIG_RSI_DEBUGFS is not set +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RSI_COEX=y +CONFIG_WLAN_VENDOR_SILABS=y +CONFIG_WFX=m +CONFIG_WLAN_VENDOR_ST=y +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +# CONFIG_CW1200_WLAN_SPI is not set +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WL1251=m +# CONFIG_WL1251_SPI is not set +CONFIG_WL1251_SDIO=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +CONFIG_WLCORE=m +# CONFIG_WLCORE_SPI is not set +CONFIG_WLCORE_SDIO=m +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_QTNFMAC=m +CONFIG_QTNFMAC_PCIE=m +CONFIG_PCMCIA_RAYCS=m +CONFIG_PCMCIA_WL3501=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_MAC80211_HWSIM=m +CONFIG_VIRT_WIFI=m +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_AT86RF230 is not set +# CONFIG_IEEE802154_MRF24J40 is not set +# CONFIG_IEEE802154_CC2520 is not set +# CONFIG_IEEE802154_ATUSB is not set +CONFIG_IEEE802154_ADF7242=m +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CA8210_DEBUGFS=y +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_HWSIM=m + +# +# Wireless WAN +# +CONFIG_WWAN=y +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +CONFIG_RPMSG_WWAN_CTRL=m +# CONFIG_IOSM is not set +CONFIG_MTK_T7XX=m +# end of Wireless WAN + +CONFIG_VMXNET3=m +CONFIG_USB4_NET=m +CONFIG_NETDEVSIM=m +CONFIG_NET_FAILOVER=m +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_VIVALDIFMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADC is not set +CONFIG_KEYBOARD_ADP5588=m +CONFIG_KEYBOARD_ADP5589=m +CONFIG_KEYBOARD_ATKBD=y +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_QT2160=m +CONFIG_KEYBOARD_DLINK_DIR685=m +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m +CONFIG_KEYBOARD_TCA6416=m +CONFIG_KEYBOARD_TCA8418=m +CONFIG_KEYBOARD_MATRIX=m +CONFIG_KEYBOARD_LM8323=m +CONFIG_KEYBOARD_LM8333=m +CONFIG_KEYBOARD_MAX7359=m +CONFIG_KEYBOARD_MCS=m +CONFIG_KEYBOARD_MPR121=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_OPENCORES=m +CONFIG_KEYBOARD_PINEPHONE=m +# CONFIG_KEYBOARD_SAMSUNG is not set +CONFIG_KEYBOARD_GOLDFISH_EVENTS=y +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_SUN4I_LRADC=m +CONFIG_KEYBOARD_IQS62X=m +# CONFIG_KEYBOARD_OMAP4 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_KEYBOARD_CAP11XX=m +# CONFIG_KEYBOARD_BCM is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_SENTELIC=y +CONFIG_MOUSE_PS2_TOUCHKIT=y +CONFIG_MOUSE_PS2_FOCALTECH=y +CONFIG_MOUSE_PS2_SMBUS=y +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +CONFIG_MOUSE_VSXXXAA=m +CONFIG_MOUSE_GPIO=m +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_TWIDJOY=m +CONFIG_JOYSTICK_ZHENHUA=m +CONFIG_JOYSTICK_DB9=m +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_TURBOGRAFX=m +CONFIG_JOYSTICK_AS5011=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_WALKERA0701=m +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +CONFIG_JOYSTICK_FSIA6B=m +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_INPUT_TABLET=y +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +CONFIG_TOUCHSCREEN_AD7879=m +CONFIG_TOUCHSCREEN_AD7879_I2C=m +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +CONFIG_TOUCHSCREEN_ADC=m +CONFIG_TOUCHSCREEN_AR1021_I2C=m +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_ATMEL_MXT_T37=y +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +CONFIG_TOUCHSCREEN_BU21013=m +CONFIG_TOUCHSCREEN_BU21029=m +CONFIG_TOUCHSCREEN_CHIPONE_ICN8318=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +CONFIG_TOUCHSCREEN_CY8CTMG110=m +CONFIG_TOUCHSCREEN_CYTTSP_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m +CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m +# CONFIG_TOUCHSCREEN_CYTTSP4_SPI is not set +CONFIG_TOUCHSCREEN_CYTTSP5=m +CONFIG_TOUCHSCREEN_DYNAPRO=m +CONFIG_TOUCHSCREEN_HAMPSHIRE=m +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_EGALAX is not set +CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m +CONFIG_TOUCHSCREEN_EXC3000=m +CONFIG_TOUCHSCREEN_FUJITSU=m +CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_HIDEEP=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_S6SY761=m +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_TOUCHSCREEN_EKTF2127=m +CONFIG_TOUCHSCREEN_ELAN=m +CONFIG_TOUCHSCREEN_ELO=m +CONFIG_TOUCHSCREEN_WACOM_W8001=m +CONFIG_TOUCHSCREEN_WACOM_I2C=m +CONFIG_TOUCHSCREEN_MAX11801=m +CONFIG_TOUCHSCREEN_MCS5000=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MELFAS_MIP4=m +CONFIG_TOUCHSCREEN_MSG2638=m +CONFIG_TOUCHSCREEN_MTOUCH=m +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +CONFIG_TOUCHSCREEN_INEXIO=m +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_PENMOUNT=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m +CONFIG_TOUCHSCREEN_TOUCHWIN=m +# CONFIG_TOUCHSCREEN_TI_AM335X_TSC is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_WDT87XX_I2C=m +CONFIG_TOUCHSCREEN_WM97XX=m +CONFIG_TOUCHSCREEN_WM9705=y +CONFIG_TOUCHSCREEN_WM9712=y +CONFIG_TOUCHSCREEN_WM9713=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_TOUCHIT213=m +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC200X_CORE=m +CONFIG_TOUCHSCREEN_TSC2004=m +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007=m +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_RM_TS=m +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +CONFIG_TOUCHSCREEN_STMFTS=m +CONFIG_TOUCHSCREEN_SUN4I=m +CONFIG_TOUCHSCREEN_SUR40=m +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +CONFIG_TOUCHSCREEN_SX8654=m +CONFIG_TOUCHSCREEN_TPS6507X=m +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_ROHM_BU21023=m +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_ZINITIX=m +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +# CONFIG_INPUT_AD714X_SPI is not set +CONFIG_INPUT_ATC260X_ONKEY=m +CONFIG_INPUT_ATMEL_CAPTOUCH=m +CONFIG_INPUT_BMA150=m +# CONFIG_INPUT_E3X0_BUTTON is not set +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MMA8450=m +# CONFIG_INPUT_GPIO_BEEPER is not set +CONFIG_INPUT_GPIO_DECODER=m +CONFIG_INPUT_GPIO_VIBRA=m +CONFIG_INPUT_CPCAP_PWRBUTTON=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_TPS65219_PWRBUTTON=m +CONFIG_INPUT_AXP20X_PEK=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +CONFIG_INPUT_PWM_BEEPER=m +CONFIG_INPUT_PWM_VIBRA=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_DA7280_HAPTICS=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_IBM_PANEL=m +CONFIG_INPUT_IMS_PCU=m +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +# CONFIG_INPUT_IQS7222 is not set +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_DRV260X_HAPTICS=m +CONFIG_INPUT_DRV2665_HAPTICS=m +CONFIG_INPUT_DRV2667_HAPTICS=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_STPMIC1_ONKEY=m +CONFIG_RMI4_CORE=m +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SPI=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F03_SERIO=m +CONFIG_RMI4_2D_SENSOR=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +CONFIG_RMI4_F54=y +CONFIG_RMI4_F55=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_PARKBD=m +CONFIG_SERIO_AMBAKMI=m +CONFIG_SERIO_PCIPS2=m +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m +CONFIG_SERIO_PS2MULT=m +# CONFIG_SERIO_ARC_PS2 is not set +CONFIG_SERIO_APBPS2=m +CONFIG_SERIO_SUN4I_PS2=m +CONFIG_SERIO_GPIO_PS2=m +CONFIG_USERIO=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=0 +CONFIG_LEGACY_TIOCSTI=y +CONFIG_LDISC_AUTOLOAD=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCILIB=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_CS=m +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_MANY_PORTS is not set +CONFIG_SERIAL_8250_PCI1XXXX=m +CONFIG_SERIAL_8250_SHARE_IRQ=y +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set +CONFIG_SERIAL_8250_DWLIB=y +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_EM=m +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_PERICOM=m +CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_AMBA_PL010=m +CONFIG_SERIAL_AMBA_PL011=m +CONFIG_SERIAL_EARLYCON_SEMIHOST=y +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_SH_SCI=m +CONFIG_SERIAL_SH_SCI_NR_UARTS=18 +CONFIG_SERIAL_SH_SCI_DMA=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +CONFIG_SERIAL_JSM=m +CONFIG_SERIAL_SIFIVE=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SC16IS7XX_CORE=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_I2C=y +CONFIG_SERIAL_SC16IS7XX_SPI=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +# CONFIG_SERIAL_ARC is not set +CONFIG_SERIAL_RP2=m +CONFIG_SERIAL_RP2_NR_UARTS=32 +CONFIG_SERIAL_FSL_LPUART=m +CONFIG_SERIAL_FSL_LINFLEXUART=y +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_SPRD=y +CONFIG_SERIAL_SPRD_CONSOLE=y +# end of Serial drivers + +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_MOXA_INTELLIO=m +CONFIG_MOXA_SMARTIO=m +CONFIG_SYNCLINK_GT=m +CONFIG_N_HDLC=m +CONFIG_GOLDFISH_TTY=y +CONFIG_GOLDFISH_TTY_EARLY_CONSOLE=y +CONFIG_IPWIRELESS=m +CONFIG_N_GSM=m +CONFIG_NOZOMI=m +CONFIG_NULL_TTY=m +CONFIG_HVC_DRIVER=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +CONFIG_PPDEV=m +CONFIG_VIRTIO_CONSOLE=y +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_PLAT_DATA=y +CONFIG_IPMI_PANIC_EVENT=y +# CONFIG_IPMI_PANIC_STRING is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_IPMB=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IPMI_POWEROFF=m +CONFIG_SSIF_IPMI_BMC=m +CONFIG_IPMB_DEVICE_INTERFACE=m +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_BA431=m +CONFIG_HW_RANDOM_VIRTIO=m +CONFIG_HW_RANDOM_POLARFIRE_SOC=m +CONFIG_HW_RANDOM_CCTRNG=m +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM_JH7110=m +CONFIG_APPLICOM=m +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_TCG_TPM=y +CONFIG_HW_RANDOM_TPM=y +CONFIG_TCG_TIS_CORE=y +CONFIG_TCG_TIS=y +CONFIG_TCG_TIS_SPI=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_ATMEL=m +CONFIG_TCG_VTPM_PROXY=m +CONFIG_TCG_TIS_ST33ZP24=m +CONFIG_TCG_TIS_ST33ZP24_I2C=m +CONFIG_TCG_TIS_ST33ZP24_SPI=m +CONFIG_XILLYBUS_CLASS=m +CONFIG_XILLYBUS=m +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYBUS_OF=m +CONFIG_XILLYUSB=m +# end of Character devices + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX=m + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX_PCA9541=m +CONFIG_I2C_MUX_PCA954x=m +# CONFIG_I2C_MUX_PINCTRL is not set +CONFIG_I2C_MUX_REG=m +CONFIG_I2C_DEMUX_PINCTRL=m +CONFIG_I2C_MUX_MLXCPLD=m +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_CCGX_UCSI=m +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_CBUS_GPIO=m +CONFIG_I2C_DESIGNWARE_CORE=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_PCI=m +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=m +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +CONFIG_I2C_KEMPLD=m +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_I2C_MV64XXX=m +CONFIG_I2C_NOMADIK=m +CONFIG_I2C_OCORES=m +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_RIIC=m +CONFIG_I2C_RK3X=m +CONFIG_I2C_RZV2M=m +CONFIG_I2C_SH_MOBILE=m +# CONFIG_I2C_SIMTEC is not set +CONFIG_I2C_XILINX=m +CONFIG_I2C_RCAR=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +CONFIG_I2C_CP2615=m +CONFIG_I2C_PARPORT=m +CONFIG_I2C_PCI1XXXX=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TAOS_EVM=m +CONFIG_I2C_TINY_USB=m +CONFIG_I2C_VIPERBOARD=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_VIRTIO=m +# end of I2C Hardware Bus support + +CONFIG_I2C_STUB=m +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SLAVE_EEPROM=m +CONFIG_I2C_SLAVE_TESTUNIT=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +CONFIG_I3C=m +CONFIG_CDNS_I3C_MASTER=m +CONFIG_DW_I3C_MASTER=m +CONFIG_SVC_I3C_MASTER=m +CONFIG_MIPI_I3C_HCI=m +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_CADENCE=m +CONFIG_SPI_CADENCE_QUADSPI=m +CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_DESIGNWARE=m +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_PCI=m +CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_DLN2=m +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +CONFIG_SPI_FSL_LIB=y +CONFIG_SPI_FSL_SPI=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_OC_TINY=m +CONFIG_SPI_PCI1XXXX=m +CONFIG_SPI_PL022=m +# CONFIG_SPI_PXA2XX is not set +CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m +CONFIG_SPI_SC18IS602=m +CONFIG_SPI_SH_MSIOF=m +CONFIG_SPI_SH_HSPI=m +CONFIG_SPI_SIFIVE=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_SUN4I=m +CONFIG_SPI_SUN6I=m +CONFIG_SPI_MXIC=m +CONFIG_SPI_XCOMM=m +CONFIG_SPI_XILINX=m +CONFIG_SPI_ZYNQMP_GQSPI=m +CONFIG_SPI_AMD=m + +# +# SPI Multiplexer support +# +CONFIG_SPI_MUX=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_LOOPBACK_TEST=m +# CONFIG_SPI_TLE62X0 is not set +CONFIG_SPI_SLAVE=y +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_DYNAMIC=y +CONFIG_SPMI=m +CONFIG_SPMI_HISI3670=m +CONFIG_HSI=m +CONFIG_HSI_BOARDINFO=y + +# +# HSI controllers +# + +# +# HSI clients +# +CONFIG_HSI_CHAR=m +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_PARPORT=m +CONFIG_PPS_CLIENT_GPIO=m + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +CONFIG_PTP_1588_CLOCK_OCP=m +CONFIG_PTP_DFL_TOD=m +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_PINMUX=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CY8C95X0=m +CONFIG_PINCTRL_MAX77620=m +CONFIG_PINCTRL_MCP23S08_I2C=m +CONFIG_PINCTRL_MCP23S08_SPI=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_RK805=m +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_STMFX=m +CONFIG_PINCTRL_SX150X=y +CONFIG_PINCTRL_LOCHNAGAR=m +CONFIG_PINCTRL_MADERA=m +CONFIG_PINCTRL_CS47L15=y +CONFIG_PINCTRL_CS47L35=y +CONFIG_PINCTRL_CS47L85=y +CONFIG_PINCTRL_CS47L90=y +CONFIG_PINCTRL_CS47L92=y + +# +# Renesas pinctrl drivers +# +CONFIG_PINCTRL_RENESAS=y +CONFIG_PINCTRL_RZG2L=y +# end of Renesas pinctrl drivers + +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=m +CONFIG_PINCTRL_SUNXI=y +CONFIG_PINCTRL_SUN4I_A10=y +CONFIG_PINCTRL_SUN5I=y +CONFIG_PINCTRL_SUN6I_A31=y +CONFIG_PINCTRL_SUN6I_A31_R=y +CONFIG_PINCTRL_SUN8I_A23=y +CONFIG_PINCTRL_SUN8I_A33=y +CONFIG_PINCTRL_SUN8I_A83T=y +CONFIG_PINCTRL_SUN8I_A83T_R=y +CONFIG_PINCTRL_SUN8I_A23_R=y +CONFIG_PINCTRL_SUN8I_H3=y +CONFIG_PINCTRL_SUN8I_H3_R=y +CONFIG_PINCTRL_SUN8I_V3S=y +# CONFIG_PINCTRL_SUN9I_A80 is not set +CONFIG_PINCTRL_SUN9I_A80_R=y +CONFIG_PINCTRL_SUN20I_D1=y +CONFIG_PINCTRL_SUN50I_A64=y +CONFIG_PINCTRL_SUN50I_A64_R=y +CONFIG_PINCTRL_SUN50I_A100=y +CONFIG_PINCTRL_SUN50I_A100_R=y +CONFIG_PINCTRL_SUN50I_H5=y +CONFIG_PINCTRL_SUN50I_H6=y +CONFIG_PINCTRL_SUN50I_H6_R=y +CONFIG_PINCTRL_SUN50I_H616=y +CONFIG_PINCTRL_SUN50I_H616_R=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_REGMAP=m +CONFIG_GPIO_MAX730X=m +CONFIG_GPIO_IDIO_16=m + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_74XX_MMIO=m +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_DWAPB=m +# CONFIG_GPIO_EXAR is not set +CONFIG_GPIO_FTGPIO010=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_GRGPIO=m +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +CONFIG_GPIO_MB86S7X=m +CONFIG_GPIO_PL061=m +CONFIG_GPIO_RCAR=m +# CONFIG_GPIO_SIFIVE is not set +CONFIG_GPIO_SYSCON=m +CONFIG_GPIO_XILINX=m +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_FXL6408=m +CONFIG_GPIO_GW_PLD=m +CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_MAX732X=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCA9570=m +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_TPIC2810=m +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +CONFIG_GPIO_BD71815=m +CONFIG_GPIO_BD71828=m +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_KEMPLD=m +CONFIG_GPIO_LP3943=m +CONFIG_GPIO_LP873X=m +CONFIG_GPIO_LP87565=m +CONFIG_GPIO_MADERA=m +CONFIG_GPIO_MAX77620=m +CONFIG_GPIO_MAX77650=m +CONFIG_GPIO_TQMX86=m +# CONFIG_GPIO_WM8994 is not set +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +CONFIG_GPIO_PCI_IDIO_16=m +CONFIG_GPIO_PCIE_IDIO_24=m +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +CONFIG_GPIO_MAX3191X=m +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_PISOSR=m +CONFIG_GPIO_XRA1403=m +CONFIG_GPIO_MOXTET=m +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +CONFIG_GPIO_VIPERBOARD=m +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +CONFIG_GPIO_AGGREGATOR=m +CONFIG_GPIO_LATCH=m +CONFIG_GPIO_MOCKUP=m +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_SIM=m +# end of Virtual GPIO drivers + +CONFIG_W1=m +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_MATROX=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_GPIO=m +# CONFIG_W1_MASTER_SGI is not set +# end of 1-wire Bus Masters + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2408_READBACK=y +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS250X=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m +# end of 1-wire Slaves + +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_ATC260X=m +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_LTC2952=y +CONFIG_POWER_RESET_REGULATOR=y +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_REBOOT_MODE=m +CONFIG_SYSCON_REBOOT_MODE=m +CONFIG_NVMEM_REBOOT_MODE=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_GENERIC_ADC_BATTERY is not set +CONFIG_IP5XXX_POWER=m +# CONFIG_TEST_POWER is not set +CONFIG_CHARGER_ADP5061=m +CONFIG_BATTERY_CPCAP=m +CONFIG_BATTERY_CW2015=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_DS2780=m +CONFIG_BATTERY_DS2781=m +CONFIG_BATTERY_DS2782=m +CONFIG_BATTERY_QCOM_BATTMGR=m +# CONFIG_BATTERY_SAMSUNG_SDI is not set +CONFIG_BATTERY_SBS=m +CONFIG_CHARGER_SBS=m +CONFIG_MANAGER_SBS=m +CONFIG_BATTERY_BQ27XXX=m +CONFIG_BATTERY_BQ27XXX_I2C=m +CONFIG_BATTERY_BQ27XXX_HDQ=m +# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_BATTERY_AXP20X=m +CONFIG_AXP20X_POWER=m +CONFIG_BATTERY_MAX17040=m +CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1721X=m +CONFIG_CHARGER_ISP1704=m +CONFIG_CHARGER_MAX8903=m +CONFIG_CHARGER_LP8727=m +CONFIG_CHARGER_GPIO=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +CONFIG_CHARGER_DETECTOR_MAX14656=m +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +CONFIG_CHARGER_MP2629=m +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_BQ2415X is not set +CONFIG_CHARGER_BQ24190=m +CONFIG_CHARGER_BQ24257=m +CONFIG_CHARGER_BQ24735=m +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ25890=m +CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_BQ256XX=m +CONFIG_CHARGER_RK817=m +CONFIG_CHARGER_SMB347=m +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_RT9455=m +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARGER_BD99954=m +CONFIG_BATTERY_UG3105=m +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_SMPRO=m +# CONFIG_SENSORS_AD7314 is not set +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM1177=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7X10=m +# CONFIG_SENSORS_ADT7310 is not set +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_AHT10=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +CONFIG_SENSORS_AS370=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_I5K_AMB=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_GSC=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_HIH6130=m +CONFIG_SENSORS_IBMAEM=m +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LOCHNAGAR=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2992=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_MAX1111 is not set +CONFIG_SENSORS_MAX127=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +# CONFIG_SENSORS_MAX197 is not set +CONFIG_SENSORS_MAX31722=m +CONFIG_SENSORS_MAX31730=m +CONFIG_SENSORS_MAX31760=m +CONFIG_SENSORS_MAX6620=m +CONFIG_SENSORS_MAX6621=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TPS23861=m +# CONFIG_SENSORS_MENF21BMC_HWMON is not set +CONFIG_SENSORS_MR75203=m +# CONFIG_SENSORS_ADCXX is not set +CONFIG_SENSORS_LM63=m +# CONFIG_SENSORS_LM70 is not set +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +# CONFIG_SENSORS_NTC_THERMISTOR is not set +CONFIG_SENSORS_NCT6683=m +# CONFIG_SENSORS_NCT6775_I2C is not set +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_SMART2=m +CONFIG_SENSORS_OCC_P8_I2C=m +CONFIG_SENSORS_OCC=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PECI_CPUTEMP=m +CONFIG_SENSORS_PECI_DIMMTEMP=m +CONFIG_SENSORS_PECI=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_ACBEL_FSG032=m +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_FSP_3Y=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_INSPUR_IPSPS=m +CONFIG_SENSORS_IR35221=m +CONFIG_SENSORS_IR36021=m +CONFIG_SENSORS_IR38064=m +# CONFIG_SENSORS_IR38064_REGULATOR is not set +CONFIG_SENSORS_IRPS5401=m +CONFIG_SENSORS_ISL68137=m +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_MAX15301=m +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16601=m +CONFIG_SENSORS_MAX20730=m +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31785=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PXE1610=m +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_STPDDC60=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +# CONFIG_SENSORS_XDPE152 is not set +CONFIG_SENSORS_XDPE122=m +CONFIG_SENSORS_XDPE122_REGULATOR=y +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SBRMI=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_STTS751=m +CONFIG_SENSORS_SFCTEMP=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADS7828=m +# CONFIG_SENSORS_ADS7871 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA3221=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +CONFIG_THERMAL=y +CONFIG_THERMAL_NETLINK=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y +CONFIG_CPU_THERMAL=y +CONFIG_CPU_FREQ_THERMAL=y +# CONFIG_CPU_IDLE_THERMAL is not set +CONFIG_DEVFREQ_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_THERMAL_MMIO=m +CONFIG_MAX77620_THERMAL=m +CONFIG_SUN8I_THERMAL=m +CONFIG_RCAR_THERMAL=m +CONFIG_RCAR_GEN3_THERMAL=m +CONFIG_RZG2L_THERMAL=m +CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set + +# +# Watchdog Pretimeout Governors +# +CONFIG_WATCHDOG_PRETIMEOUT_GOV=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m +CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=y +CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=m +CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y +# CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC is not set + +# +# Watchdog Device Drivers +# +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y +CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_MENF21BMC_WATCHDOG is not set +CONFIG_XILINX_WATCHDOG=m +CONFIG_ZIIRAVE_WATCHDOG=m +CONFIG_CADENCE_WATCHDOG=m +CONFIG_DW_WATCHDOG=m +CONFIG_SUNXI_WATCHDOG=m +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_MAX77620_WATCHDOG=m +CONFIG_RENESAS_WDT=m +CONFIG_RENESAS_RZAWDT=m +CONFIG_RENESAS_RZN1WDT=m +CONFIG_RENESAS_RZG2LWDT=m +CONFIG_STPMIC1_WATCHDOG=m +CONFIG_ALIM7101_WDT=m +CONFIG_I6300ESB_WDT=m +CONFIG_KEMPLD_WDT=m +CONFIG_MEN_A21_WDT=m +CONFIG_STARFIVE_WATCHDOG=m + +# +# PCI-based Watchdog Cards +# +CONFIG_PCIPCWATCHDOG=m +CONFIG_WDTPCI=m + +# +# USB-based Watchdog Cards +# +CONFIG_USBPCWATCHDOG=m +CONFIG_SSB_POSSIBLE=y +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_BLOCKIO=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +CONFIG_SSB_PCMCIAHOST=y +CONFIG_SSB_SDIOHOST_POSSIBLE=y +CONFIG_SSB_SDIOHOST=y +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_BCMA_POSSIBLE=y +CONFIG_BCMA=m +CONFIG_BCMA_BLOCKIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_PCI=y +CONFIG_BCMA_SFLASH=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +# CONFIG_BCMA_DEBUG is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +CONFIG_MFD_SUN4I_GPADC=m +# CONFIG_MFD_AS3711 is not set +CONFIG_MFD_SMPRO=m +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +CONFIG_MFD_ATMEL_HLCDC=m +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_AC100=m +CONFIG_MFD_AXP20X=m +CONFIG_MFD_AXP20X_I2C=m +CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_MADERA=m +CONFIG_MFD_MADERA_I2C=m +CONFIG_MFD_MADERA_SPI=m +CONFIG_MFD_MAX597X=m +CONFIG_MFD_CS47L15=y +CONFIG_MFD_CS47L35=y +CONFIG_MFD_CS47L85=y +CONFIG_MFD_CS47L90=y +CONFIG_MFD_CS47L92=y +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_GATEWORKS_GSC=m +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +CONFIG_MFD_MP2629=m +CONFIG_MFD_HI6421_PMIC=m +CONFIG_MFD_HI6421_SPMI=m +CONFIG_LPC_ICH=m +CONFIG_LPC_SCH=m +CONFIG_MFD_IQS62X=m +# CONFIG_MFD_JANZ_CMODIO is not set +CONFIG_MFD_KEMPLD=m +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX77620=y +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +CONFIG_MFD_MT6370=m +# CONFIG_MFD_MT6397 is not set +CONFIG_MFD_MENF21BMC=m +CONFIG_MFD_OCELOT=m +# CONFIG_EZX_PCAP is not set +CONFIG_MFD_CPCAP=m +CONFIG_MFD_VIPERBOARD=m +CONFIG_MFD_NTXEC=m +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +CONFIG_MFD_SY7636A=m +# CONFIG_MFD_RDC321X is not set +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_RC5T583 is not set +CONFIG_MFD_RK808=m +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SM501 is not set +CONFIG_MFD_SKY81452=m +# CONFIG_RZ_MTU3 is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SUN6I_PRCM is not set +CONFIG_MFD_SYSCON=y +CONFIG_MFD_TI_AM335X_TSCADC=m +CONFIG_MFD_LP3943=m +# CONFIG_MFD_LP8788 is not set +CONFIG_MFD_TI_LMU=m +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +CONFIG_TPS65010=m +CONFIG_TPS6507X=m +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +CONFIG_MFD_TI_LP873X=m +CONFIG_MFD_TI_LP87565=m +# CONFIG_MFD_TPS65218 is not set +CONFIG_MFD_TPS65219=m +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_MFD_WL1273_CORE=m +CONFIG_MFD_LM3533=m +# CONFIG_MFD_TC3589X is not set +CONFIG_MFD_TQMX86=m +CONFIG_MFD_VX855=m +CONFIG_MFD_LOCHNAGAR=y +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=m +CONFIG_MFD_ROHM_BD718XX=m +CONFIG_MFD_ROHM_BD71828=m +CONFIG_MFD_ROHM_BD957XMUF=m +CONFIG_MFD_STPMIC1=m +CONFIG_MFD_STMFX=m +CONFIG_MFD_ATC260X=m +CONFIG_MFD_ATC260X_I2C=m +CONFIG_MFD_QCOM_PM8008=m +# CONFIG_RAVE_SP_CORE is not set +CONFIG_MFD_INTEL_M10_BMC_CORE=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +# end of Multifunction device drivers + +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_88PG86X=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_ATC260X=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD71815=m +CONFIG_REGULATOR_BD71828=m +CONFIG_REGULATOR_BD718XX=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD957XMUF=m +CONFIG_REGULATOR_CPCAP=m +CONFIG_REGULATOR_DA9121=m +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +CONFIG_REGULATOR_FAN53555=m +CONFIG_REGULATOR_FAN53880=m +CONFIG_REGULATOR_GPIO=m +CONFIG_REGULATOR_HI6421=m +CONFIG_REGULATOR_HI6421V530=m +CONFIG_REGULATOR_HI6421V600=m +CONFIG_REGULATOR_ISL9305=m +# CONFIG_REGULATOR_ISL6271A is not set +CONFIG_REGULATOR_LM363X=m +CONFIG_REGULATOR_LOCHNAGAR=m +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +CONFIG_REGULATOR_LP873X=m +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_LP87565=m +CONFIG_REGULATOR_LTC3589=m +CONFIG_REGULATOR_LTC3676=m +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX597X=m +CONFIG_REGULATOR_MAX77620=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_MAX20086 is not set +CONFIG_REGULATOR_MAX20411=m +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MCP16502=m +CONFIG_REGULATOR_MP5416=m +CONFIG_REGULATOR_MP8859=m +CONFIG_REGULATOR_MP886X=m +CONFIG_REGULATOR_MPQ7920=m +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6315=m +CONFIG_REGULATOR_MT6370=m +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=m +CONFIG_REGULATOR_QCOM_SPMI=m +CONFIG_REGULATOR_QCOM_USB_VBUS=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m +CONFIG_REGULATOR_RK808=m +CONFIG_REGULATOR_ROHM=m +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_SKY81452=m +CONFIG_REGULATOR_SLG51000=m +CONFIG_REGULATOR_STPMIC1=m +CONFIG_REGULATOR_SY7636A=m +CONFIG_REGULATOR_SY8106A=m +CONFIG_REGULATOR_SY8824X=m +CONFIG_REGULATOR_SY8827N=m +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS6286X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_TPS65132=m +CONFIG_REGULATOR_TPS65219=m +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_VCTRL=m +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_RC_CORE=m +CONFIG_LIRC=y +CONFIG_RC_MAP=m +CONFIG_RC_DECODERS=y +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_SUNXI=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_LOOPBACK=m +CONFIG_RC_XBOX_DVD=m +CONFIG_CEC_CORE=m +CONFIG_CEC_NOTIFIER=y + +# +# CEC support +# +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_CEC_CH7322=m +CONFIG_USB_PULSE8_CEC=m +CONFIG_USB_RAINSHADOW_CEC=m +# end of CEC support + +CONFIG_MEDIA_SUPPORT=m +# CONFIG_MEDIA_SUPPORT_FILTER is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +CONFIG_VIDEO_DEV=m +CONFIG_MEDIA_CONTROLLER=y +CONFIG_DVB_CORE=m +# end of Media core support + +# +# Video4Linux options +# +CONFIG_VIDEO_V4L2_I2C=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_TUNER=m +CONFIG_V4L2_H264=m +CONFIG_V4L2_VP9=m +CONFIG_V4L2_MEM2MEM_DEV=m +CONFIG_V4L2_FLASH_LED_CLASS=m +CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_ASYNC=m +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_DMA_SG=m +# end of Video4Linux options + +# +# Media controller options +# +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER_REQUEST_API=y +# end of Media controller options + +# +# Digital TV options +# +# CONFIG_DVB_MMAP is not set +CONFIG_DVB_NET=y +CONFIG_DVB_MAX_ADAPTERS=8 +CONFIG_DVB_DYNAMIC_MINORS=y +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_USB_GL860=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y + +# +# Analog TV USB devices +# +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m + +# +# Analog/digital TV USB devices +# +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_V4L2=y +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m + +# +# Digital TV USB devices +# +CONFIG_DVB_AS102=m +CONFIG_DVB_B2C2_FLEXCOP_USB=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DVB_USB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_DIB0700=m +CONFIG_DVB_USB_DIB3000MC=m +CONFIG_DVB_USB_DIBUSB_MB=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m + +# +# Webcam, TV (analog/digital) USB devices +# +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=m + +# +# Software defined radio USB devices +# +CONFIG_USB_AIRSPY=m +CONFIG_USB_HACKRF=m +CONFIG_USB_MSI2500=m +CONFIG_MEDIA_PCI_SUPPORT=y + +# +# Media capture support +# +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_TW5864=m +CONFIG_VIDEO_TW68=m +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_ZORAN is not set + +# +# Media capture/analog TV support +# +CONFIG_VIDEO_DT3155=m +CONFIG_VIDEO_IVTV=m +CONFIG_VIDEO_IVTV_ALSA=m +CONFIG_VIDEO_FB_IVTV=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_MXB=m + +# +# Media capture/analog/hybrid TV support +# +CONFIG_VIDEO_BT848=m +CONFIG_DVB_BT8XX=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX23885=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_VIDEO_CX25821=m +CONFIG_VIDEO_CX25821_ALSA=m +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_CX88_MPEG=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7164=m + +# +# Media digital TV PCI Adapters +# +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +CONFIG_DVB_DM1105=m +CONFIG_MANTIS_CORE=m +CONFIG_DVB_MANTIS=m +CONFIG_DVB_HOPPER=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NGENE=m +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +CONFIG_DVB_PT3=m +CONFIG_DVB_SMIPCIE=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA575X=m +CONFIG_RADIO_TEA5764=m +CONFIG_RADIO_TEF6862=m +CONFIG_RADIO_WL1273=m +CONFIG_USB_DSBR=m +CONFIG_USB_KEENE=m +CONFIG_USB_MA901=m +CONFIG_USB_MR800=m +CONFIG_USB_RAREMONO=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +# CONFIG_I2C_SI470X is not set +CONFIG_USB_SI4713=m +CONFIG_PLATFORM_SI4713=m +CONFIG_I2C_SI4713=m +CONFIG_RADIO_WL128X=m +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_SDR_PLATFORM_DRIVERS=y +CONFIG_DVB_PLATFORM_DRIVERS=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m +CONFIG_VIDEO_MUX=m + +# +# Allegro DVT media platform drivers +# + +# +# Amlogic media platform drivers +# + +# +# Amphion drivers +# + +# +# Aspeed media platform drivers +# + +# +# Atmel media platform drivers +# + +# +# Cadence media platform drivers +# +CONFIG_VIDEO_CADENCE_CSI2RX=m +CONFIG_VIDEO_CADENCE_CSI2TX=m + +# +# Chips&Media media platform drivers +# + +# +# Intel media platform drivers +# + +# +# Marvell media platform drivers +# +CONFIG_VIDEO_CAFE_CCIC=m + +# +# Mediatek media platform drivers +# + +# +# Microchip Technology, Inc. media platform drivers +# + +# +# NVidia media platform drivers +# + +# +# NXP media platform drivers +# + +# +# Qualcomm media platform drivers +# + +# +# Renesas media platform drivers +# +CONFIG_VIDEO_RCAR_ISP=m +CONFIG_VIDEO_RCAR_CSI2=m +CONFIG_VIDEO_RCAR_VIN=m +CONFIG_VIDEO_RZG2L_CSI2=m +CONFIG_VIDEO_RZG2L_CRU=m +CONFIG_VIDEO_RENESAS_FCP=m +CONFIG_VIDEO_RENESAS_FDP1=m +CONFIG_VIDEO_RENESAS_JPU=m +CONFIG_VIDEO_RENESAS_VSP1=m +CONFIG_VIDEO_RCAR_DRIF=m + +# +# Rockchip media platform drivers +# + +# +# Samsung media platform drivers +# + +# +# STMicroelectronics media platform drivers +# + +# +# Starfive media platform drivers +# +CONFIG_VIDEO_STARFIVE_CAMSS=m + +# +# Sunxi media platform drivers +# +CONFIG_VIDEO_SUN4I_CSI=m +CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_SUN6I_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2=m +CONFIG_VIDEO_SUN8I_DEINTERLACE=m +CONFIG_VIDEO_SUN8I_ROTATE=m + +# +# Texas Instruments drivers +# + +# +# Verisilicon media platform drivers +# +CONFIG_VIDEO_HANTRO=m +CONFIG_VIDEO_HANTRO_SUNXI=y + +# +# VIA media platform drivers +# + +# +# Xilinx media platform drivers +# +CONFIG_VIDEO_XILINX=m +CONFIG_VIDEO_XILINX_CSI2RXSS=m +CONFIG_VIDEO_XILINX_TPG=m +CONFIG_VIDEO_XILINX_VTC=m + +# +# MMC/SDIO DVB adapters +# +CONFIG_SMS_SDIO_DRV=m +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VISL=m +# CONFIG_VISL_DEBUGFS is not set +# CONFIG_DVB_TEST_DRIVERS is not set + +# +# FireWire (IEEE 1394) Adapters +# +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_FIREDTV_INPUT=y +CONFIG_MEDIA_COMMON_OPTIONS=y + +# +# common driver options +# +CONFIG_CYPRESS_FIRMWARE=m +CONFIG_TTPCI_EEPROM=m +CONFIG_UVC_COMMON=m +CONFIG_VIDEO_CX2341X=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_DVB_B2C2_FLEXCOP=m +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_VIDEO_V4L2_TPG=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_V4L2=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_DMA_CONTIG=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_DVB=m +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y + +# +# IR I2C driver auto-selected by 'Autoselect ancillary drivers' +# +CONFIG_VIDEO_IR_I2C=m + +# +# Camera sensor devices +# +CONFIG_VIDEO_APTINA_PLL=m +CONFIG_VIDEO_CCS_PLL=m +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +CONFIG_VIDEO_MAX9271_LIB=m +CONFIG_VIDEO_MT9M001=m +CONFIG_VIDEO_MT9M111=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +CONFIG_VIDEO_OV7670=m +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_RDACM20=m +CONFIG_VIDEO_RDACM21=m +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_ST_VGXY61=m +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_ET8EK8=m +# end of Camera sensor devices + +# +# Lens drivers +# +CONFIG_VIDEO_AD5820=m +CONFIG_VIDEO_AK7375=m +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# end of Lens drivers + +# +# Flash devices +# +CONFIG_VIDEO_ADP1653=m +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +# end of Flash devices + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_CS3308=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_TDA1997X=m +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +CONFIG_VIDEO_TLV320AIC23B=m +CONFIG_VIDEO_TVAUDIO=m +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_VP27SMPX=m +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_ADV7183=m +CONFIG_VIDEO_ADV748X=m +CONFIG_VIDEO_ADV7604=m +CONFIG_VIDEO_ADV7604_CEC=y +CONFIG_VIDEO_ADV7842=m +CONFIG_VIDEO_ADV7842_CEC=y +CONFIG_VIDEO_BT819=m +CONFIG_VIDEO_BT856=m +CONFIG_VIDEO_BT866=m +CONFIG_VIDEO_ISL7998X=m +CONFIG_VIDEO_KS0127=m +CONFIG_VIDEO_MAX9286=m +CONFIG_VIDEO_ML86V7667=m +CONFIG_VIDEO_SAA7110=m +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TC358743_CEC=y +CONFIG_VIDEO_TC358746=m +CONFIG_VIDEO_TVP514X=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TVP7002=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +CONFIG_VIDEO_TW9910=m +CONFIG_VIDEO_VPX3220=m + +# +# Video and audio decoders +# +CONFIG_VIDEO_SAA717X=m +CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +CONFIG_VIDEO_ADV7170=m +CONFIG_VIDEO_ADV7175=m +CONFIG_VIDEO_ADV7343=m +CONFIG_VIDEO_ADV7393=m +CONFIG_VIDEO_AK881X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7185=m +CONFIG_VIDEO_THS8200=m +# end of Video encoders + +# +# Video improvement chips +# +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# +CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +CONFIG_SDR_MAX2175=m +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +CONFIG_VIDEO_I2C=m +CONFIG_VIDEO_M52790=m +CONFIG_VIDEO_ST_MIPID02=m +CONFIG_VIDEO_THS7303=m +# end of Miscellaneous helper chips + +# +# Media SPI Adapters +# +CONFIG_CXD2880_SPI_DRV=m +CONFIG_VIDEO_GS1662=m +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=m + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_E4000=m +CONFIG_MEDIA_TUNER_FC0011=m +CONFIG_MEDIA_TUNER_FC0012=m +CONFIG_MEDIA_TUNER_FC0013=m +CONFIG_MEDIA_TUNER_FC2580=m +CONFIG_MEDIA_TUNER_IT913X=m +CONFIG_MEDIA_TUNER_M88RS6000T=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MSI001=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2063=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MXL301RF=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_QM1D1B0004=m +CONFIG_MEDIA_TUNER_QM1D1C0042=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_R820T=m +CONFIG_MEDIA_TUNER_SI2157=m +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18250=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_TUA9001=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_M88DS3103=m +CONFIG_DVB_MXL5XX=m +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV0910=m +CONFIG_DVB_STV6110x=m +CONFIG_DVB_STV6111=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_SI2165=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_CX24117=m +CONFIG_DVB_CX24120=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_MT312=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_TDA10071=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TS2020=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_AF9013=m +CONFIG_DVB_AS102_FE=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_CXD2820R=m +CONFIG_DVB_CXD2841ER=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_EC100=m +CONFIG_DVB_GP8PSK_FE=m +CONFIG_DVB_L64781=m +CONFIG_DVB_MT352=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_RTL2832_SDR=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_SI2168=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_ZD1301_DEMOD=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_CXD2880=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_STV0297=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_VES1820=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_AU8522=m +CONFIG_DVB_AU8522_DTV=m +CONFIG_DVB_AU8522_V4L=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LG2160=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_LGDT3306A=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_MXL692=m +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m +CONFIG_DVB_S921=m + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +CONFIG_DVB_MN88443X=m +CONFIG_DVB_TC90522=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_A8293=m +CONFIG_DVB_AF9033=m +CONFIG_DVB_ASCOT2E=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_HELENE=m +CONFIG_DVB_HORUS3A=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_LNBH25=m +CONFIG_DVB_LNBH29=m +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_M88RS2000=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_DRX39XYJ=m + +# +# Common Interface (EN50221) controller drivers +# +CONFIG_DVB_CXD2099=m +CONFIG_DVB_SP2=m +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +CONFIG_DVB_DUMMY_FE=m +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_APERTURE_HELPERS=y +CONFIG_VIDEO_CMDLINE=y +CONFIG_VIDEO_NOMODESET=y +CONFIG_DRM=m +CONFIG_DRM_MIPI_DBI=m +CONFIG_DRM_MIPI_DSI=y +CONFIG_DRM_KMS_HELPER=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_DP_AUX_BUS=m +CONFIG_DRM_DISPLAY_HELPER=m +CONFIG_DRM_DISPLAY_DP_HELPER=y +CONFIG_DRM_DISPLAY_HDCP_HELPER=y +CONFIG_DRM_DISPLAY_HDMI_HELPER=y +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +CONFIG_DRM_TTM=m +CONFIG_DRM_BUDDY=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m +CONFIG_DRM_GEM_DMA_HELPER=m +CONFIG_DRM_GEM_SHMEM_HELPER=m +CONFIG_DRM_SUBALLOC_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +CONFIG_DRM_I2C_CH7006=m +CONFIG_DRM_I2C_SIL164=m +CONFIG_DRM_I2C_NXP_TDA998X=m +CONFIG_DRM_I2C_NXP_TDA9950=m +# end of I2C encoder or helper chips + +# +# ARM devices +# +CONFIG_DRM_KOMEDA=m +# end of ARM devices + +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y + +# +# ACP (Audio CoProcessor) Configuration +# +CONFIG_DRM_AMD_ACP=y +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_SI=y +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_DRM_NOUVEAU=m +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +# CONFIG_DRM_VGEM is not set +CONFIG_DRM_VKMS=m +CONFIG_DRM_UDL=m +CONFIG_DRM_AST=m +CONFIG_DRM_MGAG200=m +CONFIG_DRM_RZG2L_MIPI_DSI=m +CONFIG_DRM_SUN4I=m +CONFIG_DRM_SUN6I_DSI=m +CONFIG_DRM_SUN8I_DW_HDMI=m +CONFIG_DRM_SUN8I_MIXER=m +CONFIG_DRM_SUN8I_TCON_TOP=m +CONFIG_DRM_QXL=m +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +CONFIG_DRM_PANEL_ABT_Y030XX067A=m +CONFIG_DRM_PANEL_ARM_VERSATILE=m +CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596=m +CONFIG_DRM_PANEL_AUO_A030JTN01=m +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_EBBG_FT8719=m +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX8394=m +CONFIG_DRM_PANEL_ILITEK_IL9322=m +CONFIG_DRM_PANEL_ILITEK_ILI9341=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_JDI_R63452=m +CONFIG_DRM_PANEL_KHADAS_TS050=m +CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m +CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W=m +CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m +CONFIG_DRM_PANEL_SAMSUNG_LD9040=m +CONFIG_DRM_PANEL_LG_LB035Q02=m +CONFIG_DRM_PANEL_LG_LG4573=m +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m +CONFIG_DRM_PANEL_NEC_NL8048HL11=m +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +CONFIG_DRM_PANEL_NEWVISION_NV3052C=m +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +CONFIG_DRM_PANEL_NOVATEK_NT36523=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT39016=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m +CONFIG_DRM_PANEL_ORISETECH_OTA5601A=m +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=m +CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_RAYDIUM_RM67191=m +CONFIG_DRM_PANEL_RAYDIUM_RM68200=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m +CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m +CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_DSI=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m +CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m +CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m +CONFIG_DRM_PANEL_SHARP_LS043T1LE01=m +CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m +CONFIG_DRM_PANEL_SITRONIX_ST7703=m +CONFIG_DRM_PANEL_SITRONIX_ST7789V=m +CONFIG_DRM_PANEL_SONY_ACX565AKM=m +CONFIG_DRM_PANEL_SONY_TD4353_JDI=m +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_TDO_TL070WSH30=m +CONFIG_DRM_PANEL_TPO_TD028TTEC1=m +CONFIG_DRM_PANEL_TPO_TD043MTEA1=m +CONFIG_DRM_PANEL_TPO_TPG110=m +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +CONFIG_DRM_PANEL_XINPENG_XPP055C272=m +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_ITE_IT6505=m +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_ITE_IT66121=m +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW=m +CONFIG_DRM_NWL_MIPI_DSI=m +CONFIG_DRM_NXP_PTN3460=m +CONFIG_DRM_PARADE_PS8622=m +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_SAMSUNG_DSIM=m +CONFIG_DRM_SIL_SII8620=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_THINE_THC63LVD1024=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +CONFIG_DRM_TOSHIBA_TC358767=m +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +CONFIG_DRM_TI_DLPC3433=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_SN65DSI83=m +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +CONFIG_DRM_ANALOGIX_DP=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_I2C_ADV7511=m +CONFIG_DRM_I2C_ADV7511_AUDIO=y +CONFIG_DRM_I2C_ADV7511_CEC=y +CONFIG_DRM_CDNS_DSI=m +CONFIG_DRM_CDNS_DSI_J721E=y +CONFIG_DRM_CDNS_MHDP8546=m +CONFIG_DRM_DW_HDMI=m +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m +# CONFIG_DRM_DW_HDMI_GP_AUDIO is not set +CONFIG_DRM_DW_HDMI_CEC=m +# end of Display Interface Bridges + +CONFIG_DRM_ETNAVIV=m +CONFIG_DRM_ETNAVIV_THERMAL=y +CONFIG_DRM_LOGICVC=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_BOCHS=m +CONFIG_DRM_CIRRUS_QEMU=m +CONFIG_DRM_GM12U320=m +CONFIG_DRM_PANEL_MIPI_DBI=m +CONFIG_DRM_SIMPLEDRM=m +CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9163=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m +CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m +CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X_SPI=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +CONFIG_FB_DDC=m +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=m +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=m +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +CONFIG_FB_UVESA=m +CONFIG_FB_EFI=y +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +CONFIG_FB_I740=m +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SH_MOBILE_LCDC=m +CONFIG_FB_SMSCUFX=m +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_GOLDFISH is not set +CONFIG_FB_VIRTUAL=m +CONFIG_FB_METRONOME=m +CONFIG_FB_MB862XX=m +CONFIG_FB_MB862XX_PCI_GDC=y +CONFIG_FB_MB862XX_I2C=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_LCD_OTM3225A=m +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_KTD253=m +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LM3533=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_QCOM_WLED=m +CONFIG_BACKLIGHT_RT4831=m +CONFIG_BACKLIGHT_ADP8860=m +CONFIG_BACKLIGHT_ADP8870=m +CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_LM3639=m +CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_SKY81452=m +CONFIG_BACKLIGHT_GPIO=m +CONFIG_BACKLIGHT_LV5207LP=m +CONFIG_BACKLIGHT_BD6107=m +CONFIG_BACKLIGHT_ARCXCNN=m +CONFIG_BACKLIGHT_LED=m +# end of Backlight & LCD device support + +CONFIG_VGASTATE=m +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +CONFIG_DRM_ACCEL=y +CONFIG_DRM_ACCEL_QAIC=m +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_PCM_ELD=y +CONFIG_SND_PCM_IEC958=y +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_HWDEP=m +CONFIG_SND_SEQ_DEVICE=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_JACK=y +CONFIG_SND_JACK_INPUT_DEV=y +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_HRTIMER=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_MAX_CARDS=32 +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_PROC_FS=y +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_DEBUG=y +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTL_DEBUG is not set +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_CTL_LED=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQ_MIDI_EVENT=m +CONFIG_SND_SEQ_MIDI=m +CONFIG_SND_SEQ_MIDI_EMUL=m +CONFIG_SND_SEQ_VIRMIDI=m +CONFIG_SND_MPU401_UART=m +CONFIG_SND_OPL3_LIB=m +CONFIG_SND_OPL3_LIB_SEQ=m +CONFIG_SND_VX_LIB=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_ALOOP=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_MPU401=m +CONFIG_SND_PORTMAN2X4=m +CONFIG_SND_AC97_POWER_SAVE=y +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_PCI=y +CONFIG_SND_AD1889=m +CONFIG_SND_ATIIXP=m +CONFIG_SND_ATIIXP_MODEM=m +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AW2=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_OXYGEN_LIB=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_GINA20=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_DARLA24=m +CONFIG_SND_GINA24=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_MONA=m +CONFIG_SND_MIA=m +CONFIG_SND_ECHO3G=m +CONFIG_SND_INDIGO=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_ICE1724=m +CONFIG_SND_INTEL8X0=m +CONFIG_SND_INTEL8X0M=m +CONFIG_SND_KORG1212=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND_MIXART=m +CONFIG_SND_NM256=m +CONFIG_SND_PCXHR=m +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME96=m +CONFIG_SND_RME9652=m +CONFIG_SND_VIA82XX=m +CONFIG_SND_VIA82XX_MODEM=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +CONFIG_SND_YMFPCI=m + +# +# HD-Audio +# +CONFIG_SND_HDA=m +CONFIG_SND_HDA_GENERIC_LEDS=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=1 +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +# CONFIG_SND_HDA_CTL_DEV_ID is not set +# end of HD-Audio + +CONFIG_SND_HDA_CORE=m +CONFIG_SND_HDA_DSP_LOADER=y +CONFIG_SND_HDA_COMPONENT=y +CONFIG_SND_HDA_EXT_CORE=m +CONFIG_SND_HDA_PREALLOC_SIZE=1024 +CONFIG_SND_INTEL_DSP_CONFIG=m +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_BCD2000=m +CONFIG_SND_USB_LINE6=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_FIREWIRE=y +CONFIG_SND_FIREWIRE_LIB=m +CONFIG_SND_DICE=m +CONFIG_SND_OXFW=m +CONFIG_SND_ISIGHT=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_BEBOB=m +CONFIG_SND_FIREWIRE_DIGI00X=m +CONFIG_SND_FIREWIRE_TASCAM=m +CONFIG_SND_FIREWIRE_MOTU=m +CONFIG_SND_FIREFACE=m +CONFIG_SND_PCMCIA=y +CONFIG_SND_VXPOCKET=m +CONFIG_SND_PDAUDIOCF=m +CONFIG_SND_SOC=m +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +CONFIG_SND_SOC_COMPRESS=y +CONFIG_SND_SOC_ADI=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_AMD_ACP=m +CONFIG_SND_SOC_AMD_CZ_RT5645_MACH=m +CONFIG_SND_AMD_ACP_CONFIG=m +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_BCM63XX_I2S_WHISTLER=m +CONFIG_SND_DESIGNWARE_I2S=m +CONFIG_SND_DESIGNWARE_PCM=y + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +CONFIG_SND_SOC_FSL_ASRC=m +CONFIG_SND_SOC_FSL_SAI=m +CONFIG_SND_SOC_FSL_MQS=m +CONFIG_SND_SOC_FSL_AUDMIX=m +CONFIG_SND_SOC_FSL_SSI=m +CONFIG_SND_SOC_FSL_SPDIF=m +CONFIG_SND_SOC_FSL_ESAI=m +CONFIG_SND_SOC_FSL_MICFIL=m +CONFIG_SND_SOC_FSL_EASRC=m +CONFIG_SND_SOC_FSL_XCVR=m +CONFIG_SND_SOC_FSL_UTILS=m +CONFIG_SND_SOC_FSL_RPMSG=m +CONFIG_SND_SOC_IMX_AUDMUX=m +# end of SoC Audio for Freescale CPUs + +CONFIG_SND_I2S_HI6210_I2S=m +# CONFIG_SND_SOC_IMG is not set +CONFIG_SND_SOC_MTK_BTCVSD=m + +# +# SoC Audio support for Renesas SoCs +# +CONFIG_SND_SOC_SH4_FSI=m +CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SOC_RZ=m +# end of SoC Audio support for Renesas SoCs + +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SOF_PCI=m +CONFIG_SND_SOC_SOF_OF=m +CONFIG_SND_SOC_STARFIVE=m +CONFIG_SND_SOC_JH7110_TDM=m + +# +# STMicroelectronics STM32 SOC audio support +# +# end of STMicroelectronics STM32 SOC audio support + +# +# Allwinner SoC Audio support +# +CONFIG_SND_SUN4I_CODEC=m +CONFIG_SND_SUN4I_I2S=m +CONFIG_SND_SUN4I_SPDIF=m +CONFIG_SND_SUN50I_DMIC=m +# end of Allwinner SoC Audio support + +CONFIG_SND_SOC_XILINX_I2S=m +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m +CONFIG_SND_SOC_XILINX_SPDIF=m +CONFIG_SND_SOC_XTFPGA_I2S=m +CONFIG_SND_SOC_I2C_AND_SPI=m + +# +# CODEC drivers +# +CONFIG_SND_SOC_WM_ADSP=m +CONFIG_SND_SOC_AC97_CODEC=m +CONFIG_SND_SOC_ADAU_UTILS=m +CONFIG_SND_SOC_ADAU1372=m +CONFIG_SND_SOC_ADAU1372_I2C=m +CONFIG_SND_SOC_ADAU1372_SPI=m +CONFIG_SND_SOC_ADAU1701=m +CONFIG_SND_SOC_ADAU17X1=m +CONFIG_SND_SOC_ADAU1761=m +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_AK4104=m +CONFIG_SND_SOC_AK4118=m +CONFIG_SND_SOC_AK4375=m +CONFIG_SND_SOC_AK4458=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_AK4613=m +CONFIG_SND_SOC_AK4642=m +CONFIG_SND_SOC_AK5386=m +CONFIG_SND_SOC_AK5558=m +CONFIG_SND_SOC_ALC5623=m +CONFIG_SND_SOC_AW8738=m +# CONFIG_SND_SOC_AW88395 is not set +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CPCAP=m +CONFIG_SND_SOC_CS35L32=m +CONFIG_SND_SOC_CS35L33=m +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +CONFIG_SND_SOC_CS35L41_LIB=m +CONFIG_SND_SOC_CS35L41=m +CONFIG_SND_SOC_CS35L41_SPI=m +CONFIG_SND_SOC_CS35L41_I2C=m +CONFIG_SND_SOC_CS35L45=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L56=m +CONFIG_SND_SOC_CS35L56_SHARED=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS35L56_SDW=m +CONFIG_SND_SOC_CS42L42_CORE=m +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L51=m +CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_CS42L52=m +CONFIG_SND_SOC_CS42L56=m +CONFIG_SND_SOC_CS42L73=m +CONFIG_SND_SOC_CS42L83=m +CONFIG_SND_SOC_CS4234=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_CS4270=m +CONFIG_SND_SOC_CS4271=m +CONFIG_SND_SOC_CS4271_I2C=m +CONFIG_SND_SOC_CS4271_SPI=m +CONFIG_SND_SOC_CS42XX8=m +CONFIG_SND_SOC_CS42XX8_I2C=m +CONFIG_SND_SOC_CS43130=m +CONFIG_SND_SOC_CS4341=m +CONFIG_SND_SOC_CS4349=m +CONFIG_SND_SOC_CS53L30=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_HDMI_CODEC=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_ES8316=m +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328_SPI=m +CONFIG_SND_SOC_GTM601=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_IDT821034=m +# CONFIG_SND_SOC_INNO_RK3036 is not set +CONFIG_SND_SOC_LOCHNAGAR_SC=m +CONFIG_SND_SOC_MAX98088=m +CONFIG_SND_SOC_MAX98090=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_MAX98504=m +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +CONFIG_SND_SOC_MAX98520=m +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +CONFIG_SND_SOC_MAX9860=m +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +CONFIG_SND_SOC_PCM1681=m +CONFIG_SND_SOC_PCM1789=m +CONFIG_SND_SOC_PCM1789_I2C=m +CONFIG_SND_SOC_PCM179X=m +CONFIG_SND_SOC_PCM179X_I2C=m +CONFIG_SND_SOC_PCM179X_SPI=m +CONFIG_SND_SOC_PCM186X=m +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +CONFIG_SND_SOC_PCM5102A=m +CONFIG_SND_SOC_PCM512x=m +CONFIG_SND_SOC_PCM512x_I2C=m +CONFIG_SND_SOC_PCM512x_SPI=m +CONFIG_SND_SOC_PEB2466=m +CONFIG_SND_SOC_RK3328=m +CONFIG_SND_SOC_RK817=m +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1308_SDW=m +CONFIG_SND_SOC_RT1316_SDW=m +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT5616=m +CONFIG_SND_SOC_RT5631=m +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5645=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5682=m +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +CONFIG_SND_SOC_RT715=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT9120=m +CONFIG_SND_SOC_SDW_MOCKUP=m +CONFIG_SND_SOC_SGTL5000=m +CONFIG_SND_SOC_SIGMADSP=m +CONFIG_SND_SOC_SIGMADSP_I2C=m +CONFIG_SND_SOC_SIGMADSP_REGMAP=m +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +CONFIG_SND_SOC_SMA1303=m +CONFIG_SND_SOC_SPDIF=m +CONFIG_SND_SOC_SRC4XXX_I2C=m +CONFIG_SND_SOC_SRC4XXX=m +CONFIG_SND_SOC_SSM2305=m +CONFIG_SND_SOC_SSM2518=m +CONFIG_SND_SOC_SSM2602=m +CONFIG_SND_SOC_SSM2602_SPI=m +CONFIG_SND_SOC_SSM2602_I2C=m +CONFIG_SND_SOC_SSM4567=m +CONFIG_SND_SOC_STA32X=m +CONFIG_SND_SOC_STA350=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TAS2552=m +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS5086=m +CONFIG_SND_SOC_TAS571X=m +CONFIG_SND_SOC_TAS5720=m +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +CONFIG_SND_SOC_TFA9879=m +CONFIG_SND_SOC_TFA989X=m +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320AIC23=m +CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_TLV320AIC23_SPI=m +CONFIG_SND_SOC_TLV320AIC31XX=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +CONFIG_SND_SOC_TLV320AIC3X=m +CONFIG_SND_SOC_TLV320AIC3X_I2C=m +CONFIG_SND_SOC_TLV320AIC3X_SPI=m +CONFIG_SND_SOC_TLV320ADCX140=m +CONFIG_SND_SOC_TS3A227E=m +CONFIG_SND_SOC_TSCS42XX=m +CONFIG_SND_SOC_TSCS454=m +CONFIG_SND_SOC_UDA1334=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD938X=m +CONFIG_SND_SOC_WCD938X_SDW=m +CONFIG_SND_SOC_WM8510=m +CONFIG_SND_SOC_WM8523=m +CONFIG_SND_SOC_WM8524=m +CONFIG_SND_SOC_WM8580=m +CONFIG_SND_SOC_WM8711=m +CONFIG_SND_SOC_WM8728=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731_SPI=m +CONFIG_SND_SOC_WM8737=m +CONFIG_SND_SOC_WM8741=m +CONFIG_SND_SOC_WM8750=m +CONFIG_SND_SOC_WM8753=m +CONFIG_SND_SOC_WM8770=m +CONFIG_SND_SOC_WM8776=m +CONFIG_SND_SOC_WM8782=m +CONFIG_SND_SOC_WM8804=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804_SPI=m +CONFIG_SND_SOC_WM8903=m +CONFIG_SND_SOC_WM8904=m +CONFIG_SND_SOC_WM8940=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8961=m +CONFIG_SND_SOC_WM8962=m +CONFIG_SND_SOC_WM8974=m +CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_WM8985=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MT6351=m +CONFIG_SND_SOC_MT6358=m +CONFIG_SND_SOC_MT6660=m +CONFIG_SND_SOC_NAU8315=m +CONFIG_SND_SOC_NAU8540=m +CONFIG_SND_SOC_NAU8810=m +CONFIG_SND_SOC_NAU8821=m +CONFIG_SND_SOC_NAU8822=m +CONFIG_SND_SOC_NAU8824=m +CONFIG_SND_SOC_TPA6130A2=m +CONFIG_SND_SOC_LPASS_MACRO_COMMON=m +CONFIG_SND_SOC_LPASS_WSA_MACRO=m +CONFIG_SND_SOC_LPASS_VA_MACRO=m +CONFIG_SND_SOC_LPASS_RX_MACRO=m +CONFIG_SND_SOC_LPASS_TX_MACRO=m +# end of CODEC drivers + +CONFIG_SND_SIMPLE_CARD_UTILS=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_TEST_COMPONENT=m +CONFIG_SND_VIRTIO=m +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_GENERIC=m + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_ASUS=m +CONFIG_HID_AUREAL=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_MACALLY=m +CONFIG_HID_PRODIKEYS=m +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +CONFIG_HID_HOLTEK=m +CONFIG_HOLTEK_FF=y +CONFIG_HID_VIVALDI_COMMON=m +CONFIG_HID_VIVALDI=m +CONFIG_HID_GT683R=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KYE=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_WALTOP=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VRC2=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_GYRATION=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_HID_MAGICMOUSE=m +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_REDRAGON=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_NINTENDO_FF=y +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_PLAYSTATION_FF=y +CONFIG_HID_PXRC=m +CONFIG_HID_RAZER=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_RETRODE=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SONY=m +CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_STEAM_FF=y +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_RMI=m +CONFIG_HID_GREENASIA=m +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TOPRE=m +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_THRUSTMASTER_FF=y +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_WACOM=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_XINMO=m +CONFIG_HID_ZEROPLUS=m +CONFIG_ZEROPLUS_FF=y +CONFIG_HID_ZYDACRON=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_CUSTOM_SENSOR=m +CONFIG_HID_ALPS=m +CONFIG_HID_MCP2221=m +# end of Special HID drivers + +# +# HID-BPF support +# +# end of HID-BPF support + +# +# USB HID support +# +CONFIG_USB_HID=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +CONFIG_I2C_HID=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_ELAN=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_I2C_HID_CORE=m +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_CONN_GPIO=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_PCI=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_MON=m + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +CONFIG_USB_XHCI_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=m +CONFIG_USB_XHCI_PCI_RENESAS=m +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XHCI_RCAR=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=m +CONFIG_USB_EHCI_FSL=m +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OXU210HP_HCD=m +CONFIG_USB_ISP116X_HCD=m +CONFIG_USB_MAX3421_HCD=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PCI=m +CONFIG_USB_OHCI_HCD_SSB=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_UHCI_HCD=m +CONFIG_USB_SL811_HCD=m +# CONFIG_USB_SL811_HCD_ISO is not set +CONFIG_USB_SL811_CS=m +CONFIG_USB_R8A66597_HCD=m +CONFIG_USB_RENESAS_USBHS_HCD=m +CONFIG_USB_HCD_BCMA=m +CONFIG_USB_HCD_SSB=m +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_RENESAS_USBHS=m + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_REALTEK_AUTOPM=y +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_UAS=m + +# +# USB Imaging devices +# +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USBIP_CORE=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m +# CONFIG_USBIP_DEBUG is not set + +# +# USB dual-mode controller drivers +# +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3_STARFIVE=m +CONFIG_USB_MUSB_HDRC=m +CONFIG_USB_MUSB_HOST=y +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_DUAL_ROLE is not set + +# +# Platform Glue Layer +# +CONFIG_USB_MUSB_SUNXI=m +CONFIG_USB_MUSB_POLARFIRE_SOC=m + +# +# MUSB DMA mode +# +CONFIG_MUSB_PIO_ONLY=y +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y + +# +# Platform Glue Driver Support +# +CONFIG_USB_DWC3_HAPS=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC2=m +# CONFIG_USB_DWC2_HOST is not set + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_PERIPHERAL is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_CHIPIDEA=m +# CONFIG_USB_CHIPIDEA_UDC is not set +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_IMX=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_TEGRA=m +CONFIG_USB_ISP1760=m +CONFIG_USB_ISP1760_HCD=y +CONFIG_USB_ISP1760_HOST_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_DUAL_ROLE is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_METRO=m +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7715_PARPORT=y +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MXUPORT=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_WWAN=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL_WISHBONE=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +CONFIG_USB_USS720=m +CONFIG_USB_EMI62=m +CONFIG_USB_EMI26=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_SEVSEG=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_APPLE_MFI_FASTCHARGE=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_IOWARRIOR=m +# CONFIG_USB_TEST is not set +CONFIG_USB_EHSET_TEST_FIXTURE=m +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_YUREX=m +CONFIG_USB_EZUSB_FX2=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_LINK_LAYER_TEST=m +# CONFIG_USB_CHAOSKEY is not set +CONFIG_USB_ONBOARD_HUB=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m + +# +# USB Physical Layer drivers +# +CONFIG_USB_PHY=y +CONFIG_NOP_USB_XCEIV=m +# CONFIG_USB_GPIO_VBUS is not set +CONFIG_USB_ISP1301=m +# end of USB Physical Layer drivers + +CONFIG_USB_GADGET=m +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_U_SERIAL_CONSOLE=y + +# +# USB Peripheral Controller +# +# CONFIG_USB_GR_UDC is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_RENESAS_USBHS_UDC=m +CONFIG_USB_RENESAS_USB3=m +CONFIG_USB_RENESAS_USBF=m +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +CONFIG_USB_SNP_CORE=m +CONFIG_USB_SNP_UDC_PLAT=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_BDC_UDC=m +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +CONFIG_USB_GADGET_XILINX=m +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_DUMMY_HCD is not set +# end of USB Peripheral Controller + +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_U_ETHER=m +CONFIG_USB_U_AUDIO=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_F_NCM=m +CONFIG_USB_F_ECM=m +CONFIG_USB_F_PHONET=m +CONFIG_USB_F_EEM=m +CONFIG_USB_F_SUBSET=m +CONFIG_USB_F_RNDIS=m +CONFIG_USB_F_MASS_STORAGE=m +CONFIG_USB_F_FS=m +CONFIG_USB_F_UAC1=m +CONFIG_USB_F_UAC2=m +CONFIG_USB_F_UVC=m +CONFIG_USB_F_MIDI=m +CONFIG_USB_F_HID=m +CONFIG_USB_F_PRINTER=m +CONFIG_USB_F_TCM=m +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_PHONET=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_UAC1=y +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +CONFIG_USB_CONFIGFS_F_UAC2=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_USB_CONFIGFS_F_TCM=y + +# +# USB Gadget precomposed configurations +# +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +# CONFIG_GADGET_UAC1 is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +CONFIG_USB_ETH_EEM=y +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +CONFIG_USB_FUNCTIONFS_ETH=y +CONFIG_USB_FUNCTIONFS_RNDIS=y +CONFIG_USB_FUNCTIONFS_GENERIC=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_GADGET_TARGET=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +CONFIG_USB_G_NOKIA=m +CONFIG_USB_G_ACM_MS=m +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +CONFIG_USB_G_MULTI_CDC=y +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +# CONFIG_USB_G_DBGP_PRINTK is not set +CONFIG_USB_G_DBGP_SERIAL=y +CONFIG_USB_G_WEBCAM=m +CONFIG_USB_RAW_GADGET=m +# end of USB Gadget precomposed configurations + +CONFIG_TYPEC=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_RT1711H=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_UCSI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UCSI_PMIC_GLINK=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_ANX7411=m +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_WUSB3801=m + +# +# USB Type-C Multiplexer/DeMultiplexer Switch support +# +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_PI3USB30532=m +# end of USB Type-C Multiplexer/DeMultiplexer Switch support + +# +# USB Type-C Alternate Mode drivers +# +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# end of USB Type-C Alternate Mode drivers + +CONFIG_USB_ROLE_SWITCH=m +CONFIG_MMC=m +CONFIG_PWRSEQ_EMMC=m +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set +CONFIG_MMC_CRYPTO=y + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_ARMMMCI=m +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMC_SDHCI=m +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_PLTFM=m +CONFIG_MMC_SDHCI_OF_ARASAN=m +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_CADENCE=m +CONFIG_MMC_SDHCI_F_SDH30=m +# CONFIG_MMC_SDHCI_MILBEAUT is not set +CONFIG_MMC_ALCOR=m +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_SPI is not set +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_TMIO_CORE=m +CONFIG_MMC_SDHI=m +CONFIG_MMC_SDHI_SYS_DMAC=m +CONFIG_MMC_CB710=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_BLUEFIELD=m +CONFIG_MMC_DW_EXYNOS=m +CONFIG_MMC_DW_HI3798CV200=m +CONFIG_MMC_DW_K3=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_STARFIVE=m +CONFIG_MMC_SH_MMCIF=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_USHC=m +CONFIG_MMC_USDHI6ROL0=m +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_SUNXI=m +CONFIG_MMC_CQHCI=m +CONFIG_MMC_HSQ=m +CONFIG_MMC_TOSHIBA_PCI=m +CONFIG_MMC_MTK=m +CONFIG_MMC_SDHCI_XENON=m +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_AM654=m +CONFIG_SCSI_UFSHCD=m +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CRYPTO=y +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_UFSHCD_PCI=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +CONFIG_SCSI_UFSHCD_PLATFORM=m +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +CONFIG_SCSI_UFS_RENESAS=m +CONFIG_MEMSTICK=m +# CONFIG_MEMSTICK_DEBUG is not set + +# +# MemoryStick drivers +# +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MS_BLOCK=m + +# +# MemoryStick Host Controller Drivers +# +CONFIG_MEMSTICK_TIFM_MS=m +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y + +# +# LED drivers +# +CONFIG_LEDS_AN30259A=m +CONFIG_LEDS_AW2013=m +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_EL15203000=m +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +CONFIG_LEDS_LM3533=m +CONFIG_LEDS_LM3642=m +CONFIG_LEDS_LM3692X=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y +CONFIG_LEDS_GPIO=m +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +CONFIG_LEDS_LP55XX_COMMON=m +CONFIG_LEDS_LP5521=m +CONFIG_LEDS_LP5523=m +CONFIG_LEDS_LP5562=m +CONFIG_LEDS_LP8501=m +CONFIG_LEDS_LP8860=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_PCA955X_GPIO=y +CONFIG_LEDS_PCA963X=m +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=m +# CONFIG_LEDS_REGULATOR is not set +CONFIG_LEDS_BD2606MVV=m +CONFIG_LEDS_BD2802=m +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_TCA6507=m +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_LM355x=m +CONFIG_LEDS_MENF21BMC=m +CONFIG_LEDS_IS31FL319X=m +CONFIG_LEDS_IS31FL32XX=m + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_SYSCON=y +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_USER=m +CONFIG_LEDS_SPI_BYTE=m +CONFIG_LEDS_TI_LMU_COMMON=m +CONFIG_LEDS_LM3697=m +CONFIG_LEDS_LM36274=m + +# +# Flash and Torch LED drivers +# +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AS3645A=m +# CONFIG_LEDS_KTD2692 is not set +CONFIG_LEDS_LM3601X=m +CONFIG_LEDS_MT6370_FLASH=m +CONFIG_LEDS_RT4505=m +CONFIG_LEDS_RT8515=m +CONFIG_LEDS_SGM3140=m + +# +# RGB LED drivers +# +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_QCOM_LPG=m +CONFIG_LEDS_MT6370_RGB=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + +# +# iptables trigger is under Netfilter config (LED target) +# +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_TTY=m + +# +# Simple LED drivers +# +CONFIG_ACCESSIBILITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y + +# +# Speakup console speech +# +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +CONFIG_SPEAKUP_SYNTH_DECTLK=m +CONFIG_SPEAKUP_SYNTH_DECEXT=m +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPEAKUP_SYNTH_DUMMY=m +# end of Speakup console speech + +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MEM=y +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_ADDR_TRANS=y +CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +CONFIG_INFINIBAND_VIRT_DMA=y +CONFIG_INFINIBAND_BNXT_RE=m +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_QEDR=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND_RTRS=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_EDAC_SUPPORT=y +CONFIG_EDAC=y +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_SIFIVE=y +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_ABB5ZES3=m +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_AC100=m +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1307_CENTURY=y +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1672=m +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_RK808=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_ISL1208=m +# CONFIG_RTC_DRV_ISL12022 is not set +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_X1205=m +CONFIG_RTC_DRV_PCF8523=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF85363=m +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_BD70528=m +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_S35390A=m +CONFIG_RTC_DRV_FM3130=m +CONFIG_RTC_DRV_RX8010=m +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3032=m +CONFIG_RTC_DRV_RV8803=y +CONFIG_RTC_DRV_SD3078=m + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +CONFIG_RTC_DRV_MAX6916=m +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_DS3232_HWMON=y +CONFIG_RTC_DRV_PCF2127=m +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +CONFIG_RTC_DRV_EFI=y +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_RTC_DRV_NTXEC=m + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_SH=m +CONFIG_RTC_DRV_PL030=m +CONFIG_RTC_DRV_PL031=m +CONFIG_RTC_DRV_SUN6I=y +CONFIG_RTC_DRV_CADENCE=m +CONFIG_RTC_DRV_FTRTC010=m +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_CPCAP=m + +# +# HID Sensor RTC drivers +# +CONFIG_RTC_DRV_HID_SENSOR_TIME=m +CONFIG_RTC_DRV_GOLDFISH=y +CONFIG_RTC_DRV_POLARFIRE_SOC=m +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DMA_OF=y +CONFIG_ALTERA_MSGDMA=m +CONFIG_AMBA_PL08X=y +CONFIG_DMA_SUN6I=m +CONFIG_DW_AXI_DMAC=m +CONFIG_FSL_EDMA=m +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_PL330_DMA is not set +CONFIG_PLX_DMA=m +CONFIG_XILINX_XDMA=m +CONFIG_XILINX_ZYNQMP_DPDMA=m +CONFIG_QCOM_HIDMA_MGMT=m +CONFIG_QCOM_HIDMA=m +CONFIG_DW_DMAC_CORE=m +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +# CONFIG_SF_PDMA is not set +CONFIG_RENESAS_DMA=y +CONFIG_RCAR_DMAC=m +CONFIG_RENESAS_USB_DMAC=m +CONFIG_RZ_DMAC=m + +# +# DMA Clients +# +CONFIG_ASYNC_TX_DMA=y +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +CONFIG_SW_SYNC=y +CONFIG_UDMABUF=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +CONFIG_AUXDISPLAY=y +CONFIG_CHARLCD=m +CONFIG_LINEDISP=m +CONFIG_HD44780_COMMON=m +CONFIG_HD44780=m +# CONFIG_IMG_ASCII_LCD is not set +CONFIG_HT16K33=m +CONFIG_LCD2S=m +CONFIG_PARPORT_PANEL=m +CONFIG_PANEL_PARPORT=0 +CONFIG_PANEL_PROFILE=5 +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHARLCD_BL_FLASH=y +CONFIG_PANEL=m +CONFIG_UIO=m +CONFIG_UIO_CIF=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m +CONFIG_UIO_NETX=m +# CONFIG_UIO_PRUSS is not set +CONFIG_UIO_MF624=m +CONFIG_UIO_DFL=m +CONFIG_VFIO=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_VIRQFD=y +CONFIG_VFIO_PCI_CORE=m +CONFIG_VFIO_PCI_MMAP=y +CONFIG_VFIO_PCI_INTX=y +CONFIG_VFIO_PCI=m +CONFIG_MLX5_VFIO_PCI=m +CONFIG_IRQ_BYPASS_MANAGER=m +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_ANCHOR=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI_LIB=y +CONFIG_VIRTIO_PCI_LIB_LEGACY=y +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_PMEM=m +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_INPUT=m +CONFIG_VIRTIO_MMIO=m +# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set +CONFIG_VIRTIO_DMA_SHARED_BUFFER=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_USER=m +CONFIG_IFCVF=m +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_VP_VDPA=m +CONFIG_SNET_VDPA=m +CONFIG_VHOST_IOTLB=m +CONFIG_VHOST_RING=m +CONFIG_VHOST_TASK=y +CONFIG_VHOST=m +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VSOCK=m +CONFIG_VHOST_VDPA=m +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +CONFIG_COMEDI=m +# CONFIG_COMEDI_DEBUG is not set +CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 +CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 +# CONFIG_COMEDI_MISC_DRIVERS is not set +# CONFIG_COMEDI_ISA_DRIVERS is not set +# CONFIG_COMEDI_PCI_DRIVERS is not set +CONFIG_COMEDI_PCMCIA_DRIVERS=m +CONFIG_COMEDI_CB_DAS16_CS=m +CONFIG_COMEDI_DAS08_CS=m +CONFIG_COMEDI_NI_DAQ_700_CS=m +CONFIG_COMEDI_NI_DAQ_DIO24_CS=m +CONFIG_COMEDI_NI_LABPC_CS=m +CONFIG_COMEDI_NI_MIO_CS=m +CONFIG_COMEDI_QUATECH_DAQP_CS=m +CONFIG_COMEDI_USB_DRIVERS=m +CONFIG_COMEDI_DT9812=m +CONFIG_COMEDI_NI_USB6501=m +CONFIG_COMEDI_USBDUX=m +CONFIG_COMEDI_USBDUXFAST=m +CONFIG_COMEDI_USBDUXSIGMA=m +CONFIG_COMEDI_VMK80XX=m +CONFIG_COMEDI_8254=m +CONFIG_COMEDI_8255=m +CONFIG_COMEDI_8255_SA=m +CONFIG_COMEDI_KCOMEDILIB=m +CONFIG_COMEDI_DAS08=m +CONFIG_COMEDI_NI_LABPC=m +CONFIG_COMEDI_NI_TIO=m +CONFIG_COMEDI_NI_ROUTING=m +# CONFIG_COMEDI_TESTS is not set +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_RTL8192U=m +CONFIG_RTLLIB=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTL8192E=m +CONFIG_RTL8723BS=m +CONFIG_R8712U=m +CONFIG_RTS5208=m +CONFIG_VT6655=m +CONFIG_VT6656=m + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16240 is not set +# end of Accelerometers + +# +# Analog to digital converters +# +# CONFIG_AD7816 is not set +# end of Analog to digital converters + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set +# end of Analog digital bi-direction converters + +# +# Direct Digital Synthesis +# +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# end of Direct Digital Synthesis + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set +# end of Network Analyzer, Impedance Converters + +# +# Resolver to digital converters +# +# CONFIG_AD2S1210 is not set +# end of Resolver to digital converters +# end of IIO staging drivers + +CONFIG_FB_SM750=m +CONFIG_USB_EMXX=m +CONFIG_STAGING_MEDIA=y +CONFIG_DVB_AV7110_IR=y +CONFIG_DVB_AV7110=m +CONFIG_DVB_AV7110_OSD=y +CONFIG_DVB_BUDGET_PATCH=m +CONFIG_DVB_SP8870=m +CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_SUNXI=y +CONFIG_VIDEO_SUNXI_CEDRUS=m +CONFIG_VIDEO_SUN6I_ISP=m +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +# CONFIG_STAGING_BOARD is not set +CONFIG_LTE_GDM724X=m +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m +CONFIG_FB_TFT_HX8340BN=m +CONFIG_FB_TFT_HX8347D=m +CONFIG_FB_TFT_HX8353D=m +CONFIG_FB_TFT_HX8357D=m +CONFIG_FB_TFT_ILI9163=m +CONFIG_FB_TFT_ILI9320=m +CONFIG_FB_TFT_ILI9325=m +CONFIG_FB_TFT_ILI9340=m +CONFIG_FB_TFT_ILI9341=m +CONFIG_FB_TFT_ILI9481=m +CONFIG_FB_TFT_ILI9486=m +CONFIG_FB_TFT_PCD8544=m +CONFIG_FB_TFT_RA8875=m +CONFIG_FB_TFT_S6D02A1=m +CONFIG_FB_TFT_S6D1121=m +CONFIG_FB_TFT_SEPS525=m +CONFIG_FB_TFT_SH1106=m +CONFIG_FB_TFT_SSD1289=m +CONFIG_FB_TFT_SSD1305=m +CONFIG_FB_TFT_SSD1306=m +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m +CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m +CONFIG_KS7010=m +CONFIG_PI433=m +CONFIG_XIL_AXIS_FIFO=m +CONFIG_FIELDBUS_DEV=m +CONFIG_HMS_ANYBUSS_BUS=m +CONFIG_ARCX_ANYBUS_CONTROLLER=m +CONFIG_HMS_PROFINET=m +CONFIG_QLGE=m +# CONFIG_VME_BUS is not set +CONFIG_GOLDFISH=y +CONFIG_GOLDFISH_PIPE=m +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y +CONFIG_LMK04832=m +CONFIG_COMMON_CLK_MAX77686=m +CONFIG_COMMON_CLK_MAX9485=m +CONFIG_COMMON_CLK_RK808=m +CONFIG_COMMON_CLK_SI5341=m +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI514=m +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_CDCE706=m +CONFIG_COMMON_CLK_CDCE925=m +CONFIG_COMMON_CLK_CS2000_CP=m +CONFIG_COMMON_CLK_AXI_CLKGEN=m +CONFIG_COMMON_CLK_LOCHNAGAR=m +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +CONFIG_COMMON_CLK_SI521XX=m +CONFIG_COMMON_CLK_VC5=m +CONFIG_COMMON_CLK_VC7=m +CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_FIXED_MMIO=y +CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y +CONFIG_MCHP_CLK_MPFS=y +CONFIG_CLK_RENESAS=y +CONFIG_CLK_R9A07G043=y +# CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set +CONFIG_CLK_RZG2L=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_STARFIVE_JH71X0=y +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7100_AUDIO=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_SUNXI_CCU=m +CONFIG_SUN20I_D1_CCU=m +CONFIG_SUN20I_D1_R_CCU=m +CONFIG_SUN6I_RTC_CCU=m +CONFIG_SUN8I_DE2_CCU=m +CONFIG_XILINX_VCU=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_SUN6I=m + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_CLKSRC_MMIO=y +CONFIG_SUN4I_TIMER=y +CONFIG_RENESAS_OSTM=y +CONFIG_RISCV_TIMER=y +CONFIG_STARFIVE_TIMER=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_ARM_MHU=m +CONFIG_ARM_MHU_V2=m +CONFIG_PLATFORM_MHU=m +# CONFIG_PL320_MBOX is not set +# CONFIG_ALTERA_MBOX is not set +# CONFIG_MAILBOX_TEST is not set +CONFIG_POLARFIRE_SOC_MAILBOX=m +CONFIG_SUN6I_MSGBOX=m +CONFIG_IOMMU_IOVA=m +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set +CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y +CONFIG_OF_IOMMU=y +CONFIG_IOMMUFD=m +CONFIG_SUN50I_IOMMU=y +# CONFIG_IPMMU_VMSA is not set + +# +# Remoteproc drivers +# +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_RCAR_REMOTEPROC=m +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +CONFIG_RPMSG=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG_NS=m +CONFIG_RPMSG_QCOM_GLINK=m +CONFIG_RPMSG_QCOM_GLINK_RPM=m +CONFIG_RPMSG_VIRTIO=m +# end of Rpmsg drivers + +CONFIG_SOUNDWIRE=y + +# +# SoundWire Devices +# +CONFIG_SOUNDWIRE_QCOM=m + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +CONFIG_POLARFIRE_SOC_SYS_CTRL=m +CONFIG_WPCM450_SOC=m + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_PDR_HELPERS=m +CONFIG_QCOM_PMIC_GLINK=m +CONFIG_QCOM_QMI_HELPERS=m +# end of Qualcomm SoC drivers + +CONFIG_SOC_RENESAS=y +CONFIG_ARCH_RZG2L=y +CONFIG_ARCH_R9A07G043=y +CONFIG_SIFIVE_CCACHE=y +CONFIG_JH71XX_PMU=y +CONFIG_SUNXI_SRAM=y +CONFIG_SUN20I_PPU=y +CONFIG_SOC_TI=y + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=m +CONFIG_DEVFREQ_GOV_POWERSAVE=m +CONFIG_DEVFREQ_GOV_USERSPACE=m +CONFIG_DEVFREQ_GOV_PASSIVE=y + +# +# DEVFREQ Drivers +# +CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_EXTCON=y + +# +# Extcon Device Drivers +# +# CONFIG_EXTCON_ADC_JACK is not set +CONFIG_EXTCON_FSA9480=m +CONFIG_EXTCON_GPIO=m +CONFIG_EXTCON_MAX3355=m +CONFIG_EXTCON_PTN5150=m +# CONFIG_EXTCON_RT8973A is not set +CONFIG_EXTCON_SM5502=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON_USBC_TUSB320=m +CONFIG_MEMORY=y +CONFIG_ARM_PL172_MPMC=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_RENESAS_RPCIF=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_GTS_HELPER=m +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +CONFIG_IIO_TRIGGERED_EVENT=m + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16209 is not set +CONFIG_ADXL313=m +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +CONFIG_ADXL355=m +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL372=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_BMA220=m +CONFIG_BMA400=m +CONFIG_BMA400_I2C=m +CONFIG_BMA400_SPI=m +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_ACCEL_I2C=m +CONFIG_BMC150_ACCEL_SPI=m +CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_SPI=m +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DMARD06=m +CONFIG_DMARD09=m +CONFIG_DMARD10=m +CONFIG_FXLS8962AF=m +CONFIG_FXLS8962AF_I2C=m +CONFIG_FXLS8962AF_SPI=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_IIO_KX022A=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO_KX022A_I2C=m +# CONFIG_KXSD9 is not set +# CONFIG_KXCJK1013 is not set +CONFIG_MC3230=m +CONFIG_MMA7455=m +CONFIG_MMA7455_I2C=m +CONFIG_MMA7455_SPI=m +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +CONFIG_MMA9551_CORE=m +CONFIG_MMA9551=m +CONFIG_MMA9553=m +CONFIG_MSA311=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_STK8312=m +CONFIG_STK8BA50=m +# end of Accelerometers + +# +# Analog to digital converters +# +CONFIG_AD_SIGMA_DELTA=m +CONFIG_AD4130=m +CONFIG_AD7091R5=m +CONFIG_AD7124=m +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +# CONFIG_AD7298 is not set +# CONFIG_AD7476 is not set +CONFIG_AD7606=m +CONFIG_AD7606_IFACE_PARALLEL=m +CONFIG_AD7606_IFACE_SPI=m +CONFIG_AD7766=m +CONFIG_AD7768_1=m +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +CONFIG_AD9467=m +CONFIG_ADI_AXI_ADC=m +CONFIG_AXP20X_ADC=m +CONFIG_AXP288_ADC=m +# CONFIG_CC10001_ADC is not set +CONFIG_CPCAP_ADC=m +CONFIG_DLN2_ADC=m +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_HI8435=m +CONFIG_HX711=m +CONFIG_INA2XX_ADC=m +CONFIG_LTC2471=m +CONFIG_LTC2485=m +CONFIG_LTC2496=m +CONFIG_LTC2497=m +# CONFIG_MAX1027 is not set +CONFIG_MAX11100=m +CONFIG_MAX1118=m +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +# CONFIG_MAX1363 is not set +CONFIG_MAX9611=m +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +CONFIG_MCP3911=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MP2629_ADC=m +# CONFIG_NAU7802 is not set +CONFIG_QCOM_VADC_COMMON=m +# CONFIG_QCOM_SPMI_IADC is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_RICHTEK_RTQ6056=m +CONFIG_RZG2L_ADC=m +CONFIG_SD_ADC_MODULATOR=m +CONFIG_SUN4I_GPADC=m +# CONFIG_TI_ADC081C is not set +CONFIG_TI_ADC0832=m +CONFIG_TI_ADC084S021=m +CONFIG_TI_ADC12138=m +CONFIG_TI_ADC108S102=m +# CONFIG_TI_ADC128S052 is not set +CONFIG_TI_ADC161S626=m +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS7924=m +CONFIG_TI_ADS1100=m +CONFIG_TI_ADS7950=m +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +CONFIG_TI_ADS124S08=m +CONFIG_TI_ADS131E08=m +# CONFIG_TI_AM335X_ADC is not set +CONFIG_TI_LMP92064=m +CONFIG_TI_TLC4541=m +CONFIG_TI_TSC2046=m +# CONFIG_VF610_ADC is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_XILINX_XADC=m +# end of Analog to digital converters + +# +# Analog to digital and digital to analog converters +# +CONFIG_AD74115=m +CONFIG_AD74413R=m +# end of Analog to digital and digital to analog converters + +# +# Analog Front Ends +# +CONFIG_IIO_RESCALE=m +# end of Analog Front Ends + +# +# Amplifiers +# +# CONFIG_AD8366 is not set +CONFIG_ADA4250=m +CONFIG_HMC425=m +# end of Amplifiers + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7746 is not set +# end of Capacitance to digital converters + +# +# Chemical Sensors +# +CONFIG_ATLAS_PH_SENSOR=m +CONFIG_ATLAS_EZO_SENSOR=m +CONFIG_BME680=m +CONFIG_BME680_I2C=m +CONFIG_BME680_SPI=m +CONFIG_CCS811=m +CONFIG_IAQCORE=m +CONFIG_PMS7003=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +CONFIG_SCD4X=m +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +CONFIG_SPS30=m +CONFIG_SPS30_I2C=m +CONFIG_SPS30_SERIAL=m +CONFIG_SENSEAIR_SUNRISE_CO2=m +CONFIG_VZ89X=m +# end of Chemical Sensors + +# +# Hid Sensor IIO Common +# +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +# end of Hid Sensor IIO Common + +CONFIG_IIO_MS_SENSORS_I2C=m + +# +# IIO SCMI Sensors +# +# end of IIO SCMI Sensors + +# +# SSP Sensor Common +# +# CONFIG_IIO_SSP_SENSORHUB is not set +# end of SSP Sensor Common + +CONFIG_IIO_ST_SENSORS_I2C=m +CONFIG_IIO_ST_SENSORS_SPI=m +CONFIG_IIO_ST_SENSORS_CORE=m + +# +# Digital to analog converters +# +CONFIG_AD3552R=m +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +CONFIG_AD5592R_BASE=m +CONFIG_AD5592R=m +# CONFIG_AD5593R is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5624R_SPI is not set +CONFIG_LTC2688=m +CONFIG_AD5686=m +CONFIG_AD5686_SPI=m +CONFIG_AD5696_I2C=m +# CONFIG_AD5755 is not set +CONFIG_AD5758=m +CONFIG_AD5761=m +# CONFIG_AD5764 is not set +# CONFIG_AD5766 is not set +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +CONFIG_AD7293=m +# CONFIG_AD7303 is not set +CONFIG_AD8801=m +CONFIG_DPOT_DAC=m +CONFIG_DS4424=m +CONFIG_LTC1660=m +CONFIG_LTC2632=m +CONFIG_M62332=m +# CONFIG_MAX517 is not set +CONFIG_MAX5522=m +# CONFIG_MAX5821 is not set +# CONFIG_MCP4725 is not set +# CONFIG_MCP4922 is not set +CONFIG_TI_DAC082S085=m +CONFIG_TI_DAC5571=m +CONFIG_TI_DAC7311=m +CONFIG_TI_DAC7612=m +# CONFIG_VF610_DAC is not set +# end of Digital to analog converters + +# +# IIO dummy driver +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# end of IIO dummy driver + +# +# Filters +# +CONFIG_ADMV8818=m +# end of Filters + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set +# end of Clock Generator/Distribution + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set +CONFIG_ADF4371=m +CONFIG_ADF4377=m +CONFIG_ADMV1013=m +CONFIG_ADMV1014=m +CONFIG_ADMV4420=m +# CONFIG_ADRF6780 is not set +# end of Phase-Locked Loop (PLL) frequency synthesizers +# end of Frequency Synthesizers DDS/PLL + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16260 is not set +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +# CONFIG_BMG160 is not set +CONFIG_FXAS21002C=m +CONFIG_FXAS21002C_I2C=m +CONFIG_FXAS21002C_SPI=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_MPU3050=m +CONFIG_MPU3050_I2C=m +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set +# end of Digital gyroscope sensors + +# +# Health Sensors +# + +# +# Heart Rate Monitors +# +CONFIG_AFE4403=m +CONFIG_AFE4404=m +CONFIG_MAX30100=m +CONFIG_MAX30102=m +# end of Heart Rate Monitors +# end of Health Sensors + +# +# Humidity sensors +# +CONFIG_AM2315=m +# CONFIG_DHT11 is not set +CONFIG_HDC100X=m +CONFIG_HDC2010=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HTS221=m +CONFIG_HTS221_I2C=m +CONFIG_HTS221_SPI=m +CONFIG_HTU21=m +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# end of Humidity sensors + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +CONFIG_ADIS16460=m +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +CONFIG_BMI160=m +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BOSCH_BNO055=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_FXOS8700=m +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_KMX61=m +CONFIG_INV_ICM42600=m +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +CONFIG_INV_MPU6050_IIO=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_INV_MPU6050_SPI=m +CONFIG_IIO_ST_LSM6DSX=m +CONFIG_IIO_ST_LSM6DSX_I2C=m +CONFIG_IIO_ST_LSM6DSX_SPI=m +CONFIG_IIO_ST_LSM6DSX_I3C=m +# end of Inertial measurement units + +CONFIG_IIO_ADIS_LIB=m +CONFIG_IIO_ADIS_LIB_BUFFER=y + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +CONFIG_ADUX1020=m +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9960=m +CONFIG_AS73211=m +# CONFIG_BH1750 is not set +# CONFIG_BH1780 is not set +# CONFIG_CM32181 is not set +CONFIG_CM3232=m +CONFIG_CM3323=m +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +CONFIG_IQS621_ALS=m +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_ISL29125 is not set +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_PROX=m +CONFIG_JSA1212=m +CONFIG_ROHM_BU27034=m +CONFIG_RPR0521=m +# CONFIG_SENSORS_LM3533 is not set +# CONFIG_LTR501 is not set +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +CONFIG_NOA1305=m +CONFIG_OPT3001=m +CONFIG_PA12203001=m +CONFIG_SI1133=m +CONFIG_SI1145=m +# CONFIG_STK3310 is not set +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25_SPI=m +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set +CONFIG_TSL2591=m +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_US5182D=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VEML6030=m +# CONFIG_VEML6070 is not set +CONFIG_VL6180=m +CONFIG_ZOPT2201=m +# end of Light sensors + +# +# Magnetometer sensors +# +CONFIG_AK8974=m +# CONFIG_AK8975 is not set +# CONFIG_AK09911 is not set +# CONFIG_BMC150_MAGN_I2C is not set +# CONFIG_BMC150_MAGN_SPI is not set +# CONFIG_MAG3110 is not set +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_MMC35240 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_RM3100=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +CONFIG_TI_TMAG5273=m +# CONFIG_YAMAHA_YAS530 is not set +# end of Magnetometer sensors + +# +# Multiplexers +# +CONFIG_IIO_MUX=m +# end of Multiplexers + +# +# Inclinometer sensors +# +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +# end of Inclinometer sensors + +# +# Triggers - standalone +# +CONFIG_IIO_HRTIMER_TRIGGER=m +# CONFIG_IIO_INTERRUPT_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +# end of Triggers - standalone + +# +# Linear and angular position sensors +# +CONFIG_IQS624_POS=m +# CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE is not set +# end of Linear and angular position sensors + +# +# Digital potentiometers +# +CONFIG_AD5110=m +CONFIG_AD5272=m +# CONFIG_DS1803 is not set +CONFIG_MAX5432=m +CONFIG_MAX5481=m +CONFIG_MAX5487=m +CONFIG_MCP4018=m +# CONFIG_MCP4131 is not set +CONFIG_MCP4531=m +CONFIG_MCP41010=m +CONFIG_TPL0102=m +# end of Digital potentiometers + +# +# Digital potentiostats +# +CONFIG_LMP91000=m +# end of Digital potentiostats + +# +# Pressure sensors +# +CONFIG_ABP060MG=m +CONFIG_BMP280=m +CONFIG_BMP280_I2C=m +CONFIG_BMP280_SPI=m +CONFIG_DLHL60D=m +CONFIG_DPS310=m +CONFIG_HID_SENSOR_PRESS=m +# CONFIG_HP03 is not set +CONFIG_ICP10100=m +CONFIG_MPL115=m +CONFIG_MPL115_I2C=m +CONFIG_MPL115_SPI=m +# CONFIG_MPL3115 is not set +# CONFIG_MS5611 is not set +CONFIG_MS5637=m +CONFIG_IIO_ST_PRESS=m +CONFIG_IIO_ST_PRESS_I2C=m +CONFIG_IIO_ST_PRESS_SPI=m +# CONFIG_T5403 is not set +# CONFIG_HP206C is not set +CONFIG_ZPA2326=m +CONFIG_ZPA2326_I2C=m +CONFIG_ZPA2326_SPI=m +# end of Pressure sensors + +# +# Lightning sensors +# +# CONFIG_AS3935 is not set +# end of Lightning sensors + +# +# Proximity and distance sensors +# +CONFIG_ISL29501=m +CONFIG_LIDAR_LITE_V2=m +CONFIG_MB1232=m +CONFIG_PING=m +CONFIG_RFD77402=m +CONFIG_SRF04=m +CONFIG_SX_COMMON=m +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +CONFIG_SX9500=m +CONFIG_SRF08=m +CONFIG_VCNL3020=m +CONFIG_VL53L0X_I2C=m +# end of Proximity and distance sensors + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# end of Resolver to digital converters + +# +# Temperature sensors +# +CONFIG_IQS620AT_TEMP=m +CONFIG_LTC2983=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_HID_SENSOR_TEMP=m +# CONFIG_MLX90614 is not set +CONFIG_MLX90632=m +# CONFIG_TMP006 is not set +CONFIG_TMP007=m +CONFIG_TMP117=m +CONFIG_TSYS01=m +CONFIG_TSYS02D=m +CONFIG_MAX30208=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +# end of Temperature sensors + +CONFIG_NTB=y +CONFIG_NTB_MSI=y +CONFIG_NTB_IDT=m +# CONFIG_NTB_EPF is not set +CONFIG_NTB_SWITCHTEC=m +# CONFIG_NTB_PINGPONG is not set +# CONFIG_NTB_TOOL is not set +CONFIG_NTB_PERF=m +# CONFIG_NTB_MSI_TEST is not set +CONFIG_NTB_TRANSPORT=m +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_ATMEL_HLCDC_PWM=m +CONFIG_PWM_ATMEL_TCB=m +CONFIG_PWM_CLK=m +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_IQS620A=m +CONFIG_PWM_LP3943=m +CONFIG_PWM_NTXEC=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_RCAR=m +CONFIG_PWM_RENESAS_TPU=m +CONFIG_PWM_SIFIVE=m +CONFIG_PWM_STARFIVE_PTC=m +CONFIG_PWM_SUN4I=m +CONFIG_PWM_XILINX=m + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_AL_FIC=y +CONFIG_MADERA_IRQ=m +CONFIG_RENESAS_RZG2L_IRQC=y +# CONFIG_XILINX_INTC is not set +CONFIG_RISCV_INTC=y +CONFIG_SIFIVE_PLIC=y +# end of IRQ chip support + +CONFIG_IPACK_BUS=m +CONFIG_BOARD_TPCI200=m +CONFIG_SERIAL_IPOCTAL=m +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_POLARFIRE_SOC=y +CONFIG_RESET_RZG2L_USBPHY_CTRL=m +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_SUNXI=y +CONFIG_RESET_TI_SYSCON=m +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESET_STARFIVE_JH71X0=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PHY_MIPI_DPHY=y +CONFIG_PHY_CAN_TRANSCEIVER=m +CONFIG_PHY_SUN4I_USB=m +CONFIG_PHY_SUN6I_MIPI_DPHY=m +CONFIG_PHY_SUN9I_USB=m +CONFIG_PHY_SUN50I_USB3=m + +# +# PHY drivers for Broadcom platforms +# +CONFIG_BCM_KONA_USB2_PHY=m +# end of PHY drivers for Broadcom platforms + +CONFIG_PHY_CADENCE_TORRENT=m +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_PXA_28NM_HSIC=m +CONFIG_PHY_PXA_28NM_USB2=m +CONFIG_PHY_LAN966X_SERDES=m +CONFIG_PHY_CPCAP_USB=m +CONFIG_PHY_MAPPHONE_MDM6600=m +CONFIG_PHY_OCELOT_SERDES=m +CONFIG_PHY_QCOM_USB_HS=m +CONFIG_PHY_QCOM_USB_HSIC=m +CONFIG_PHY_R8A779F0_ETHERNET_SERDES=m +CONFIG_PHY_RCAR_GEN2=m +CONFIG_PHY_RCAR_GEN3_PCIE=m +CONFIG_PHY_RCAR_GEN3_USB2=m +CONFIG_PHY_RCAR_GEN3_USB3=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +CONFIG_PHY_STARFIVE_DPHY_RX=m +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_TUSB1210 is not set +# end of PHY Subsystem + +CONFIG_POWERCAP=y +CONFIG_IDLE_INJECT=y +# CONFIG_DTPM is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +# end of Performance monitor support + +CONFIG_RAS=y +CONFIG_USB4=m +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set + +# +# Android +# +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_ANDROID_BINDER_DEVICES="" +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# end of Android + +CONFIG_LIBNVDIMM=m +CONFIG_BLK_DEV_PMEM=m +CONFIG_ND_CLAIM=y +CONFIG_ND_BTT=m +CONFIG_BTT=y +CONFIG_OF_PMEM=m +CONFIG_NVDIMM_KEYS=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +CONFIG_DAX=y +CONFIG_DEV_DAX=m +CONFIG_DEV_DAX_CXL=m +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# Layout Types +# +CONFIG_NVMEM_LAYOUT_SL28_VPD=m +CONFIG_NVMEM_LAYOUT_ONIE_TLV=m +# end of Layout Types + +# CONFIG_NVMEM_RMEM is not set +CONFIG_NVMEM_SPMI_SDAM=m +CONFIG_NVMEM_SUNXI_SID=m +CONFIG_NVMEM_U_BOOT_ENV=m + +# +# HW tracing support +# +CONFIG_STM=y +CONFIG_STM_PROTO_BASIC=m +CONFIG_STM_PROTO_SYS_T=m +# CONFIG_STM_DUMMY is not set +CONFIG_STM_SOURCE_CONSOLE=y +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STM_SOURCE_FTRACE=m +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +CONFIG_FPGA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +CONFIG_FPGA_BRIDGE=m +CONFIG_ALTERA_FREEZE_BRIDGE=m +CONFIG_XILINX_PR_DECOUPLER=m +CONFIG_FPGA_REGION=m +CONFIG_OF_FPGA_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL_AFU=m +# CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000 is not set +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_MICROCHIP_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +# CONFIG_FSI is not set +CONFIG_MULTIPLEXER=m + +# +# Multiplexer drivers +# +CONFIG_MUX_ADG792A=m +CONFIG_MUX_ADGS1408=m +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# end of Multiplexer drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +CONFIG_INTERCONNECT=y +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +CONFIG_PECI=m +CONFIG_PECI_CPU=m +CONFIG_HTE=y +# end of Device Drivers + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +CONFIG_LEGACY_DIRECT_IO=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_SUPPORT_ASCII_CI=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCFS2_FS_STATS=y +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +# CONFIG_OCFS2_DEBUG_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_FS_REF_VERIFY is not set +CONFIG_NILFS2_FS=m +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +# CONFIG_F2FS_FS_COMPRESSION is not set +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_ZONEFS_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FS_ENCRYPTION_ALGS=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_VIRTIO_FS=m +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_NETFS_SUPPORT=m +CONFIG_NETFS_STATS=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +# CONFIG_CACHEFILES_ONDEMAND is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_EXFAT_FS=m +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_NTFS3_FS=m +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS3_FS_POSIX_ACL is not set +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS_INODE64=y +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +CONFIG_EFIVAR_FS=m +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +CONFIG_AFFS_FS=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +# CONFIG_BEFS_DEBUG is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +CONFIG_CRAMFS=m +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_DECOMP_SINGLE=y +CONFIG_SQUASHFS_DECOMP_MULTI=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y +CONFIG_SQUASHFS_MOUNT_DECOMP_THREADS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +CONFIG_HPFS_FS=m +# CONFIG_QNX4FS_FS is not set +CONFIG_QNX6FS_FS=m +# CONFIG_QNX6FS_DEBUG is not set +CONFIG_ROMFS_FS=m +# CONFIG_ROMFS_BACKED_BY_BLOCK is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_BACKED_BY_BOTH=y +CONFIG_ROMFS_ON_BLOCK=y +CONFIG_ROMFS_ON_MTD=y +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_842_COMPRESS is not set +CONFIG_PSTORE_ZSTD_COMPRESS=y +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE_ZONE=m +CONFIG_PSTORE_BLK=m +CONFIG_PSTORE_BLK_BLKDEV="" +CONFIG_PSTORE_BLK_KMSG_SIZE=64 +CONFIG_PSTORE_BLK_MAX_REASON=2 +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_EROFS_FS=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_PCPU_KTHREAD=y +CONFIG_EROFS_FS_PCPU_KTHREAD_HIPRI=y +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V2=m +CONFIG_NFS_V3=m +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=m +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_PNFS_FILE_LAYOUT=m +CONFIG_PNFS_BLOCK=m +CONFIG_PNFS_FLEXFILE_LAYOUT=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_SECURITY_LABEL=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DEBUG=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFSD=m +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_GRACE_PERIOD=m +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_NFS_V4_2_SSC_HELPER=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC_BACKCHANNEL=y +CONFIG_SUNRPC_SWAP=y +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPCSEC_GSS_KRB5_CRYPTOSYSTEM=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_CEPH_FS=m +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS_POSIX_ACL=y +# CONFIG_CEPH_FS_SECURITY_LABEL is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_SWN_UPCALL=y +# CONFIG_CIFS_SMB_DIRECT is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMBFS=m +CONFIG_CODA_FS=m +# CONFIG_AFS_FS is not set +CONFIG_9P_FS=m +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UTF8=m +CONFIG_DLM=m +CONFIG_DLM_DEBUG=y +CONFIG_UNICODE=y +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_IO_WQ=y +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_TRUSTED_KEYS=m +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_USER_DECRYPTED_DATA is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_INFINIBAND is not set +# CONFIG_SECURITY_NETWORK_XFRM is not set +CONFIG_SECURITY_PATH=y +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +# CONFIG_STATIC_USERMODEHELPER is not set +# CONFIG_SECURITY_SELINUX is not set +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY_APPARMOR=y +# CONFIG_SECURITY_APPARMOR_DEBUG is not set +CONFIG_SECURITY_APPARMOR_INTROSPECT_POLICY=y +CONFIG_SECURITY_APPARMOR_HASH=y +CONFIG_SECURITY_APPARMOR_HASH_DEFAULT=y +CONFIG_SECURITY_APPARMOR_EXPORT_BINARY=y +CONFIG_SECURITY_APPARMOR_PARANOID_LOAD=y +# CONFIG_SECURITY_LOADPIN is not set +CONFIG_SECURITY_YAMA=y +# CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set +CONFIG_SECURITY_LANDLOCK=y +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_APPARMOR=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="landlock,yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y +CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_STACK_ALL_PATTERN is not set +# CONFIG_INIT_STACK_ALL_ZERO is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y +# CONFIG_ZERO_CALL_USED_REGS is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_ENGINE=m +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_ECC=m +CONFIG_CRYPTO_ECDH=m +CONFIG_CRYPTO_ECDSA=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_SM2=m +CONFIG_CRYPTO_CURVE25519=m +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARIA=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_BLOWFISH_COMMON=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST_COMMON=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SM4=m +CONFIG_CRYPTO_SM4_GENERIC=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=m +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_OFB=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XCTR=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_NHPOLY1305=m +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ESSIV=m +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +CONFIG_CRYPTO_BLAKE2B=m +CONFIG_CRYPTO_CMAC=m +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_POLYVAL=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=m +CONFIG_CRYPTO_SM3=m +CONFIG_CRYPTO_SM3_GENERIC=m +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XXHASH=m +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_CRC64_ROCKSOFT=y +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_ZSTD=y +# end of Compression + +# +# Random number generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KDF800108_CTR=y +# end of Random number generation + +# +# Userspace interface +# +CONFIG_CRYPTO_USER_API=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y +# CONFIG_CRYPTO_STATS is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_ALLWINNER=y +CONFIG_CRYPTO_DEV_SUN4I_SS=m +CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y +# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE=m +# CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y +CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS=m +# CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG is not set +CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y +CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y +CONFIG_CRYPTO_DEV_ATMEL_I2C=m +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_NITROX=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +CONFIG_CRYPTO_DEV_QAT=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_CHELSIO=m +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DEV_SAFEXCEL=m +CONFIG_CRYPTO_DEV_CCREE=m +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL_DEBUG is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_RAID6_PQ_BENCHMARK=y +CONFIG_LINEAR_RANGES=y +CONFIG_PACKING=y +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_CORDIC=m +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=m +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m +CONFIG_CRYPTO_LIB_CHACHA=m +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_DES=m +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m +CONFIG_CRYPTO_LIB_POLY1305=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC64_ROCKSOFT=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC64=y +CONFIG_CRC4=m +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_CRC8=y +CONFIG_XXHASH=y +CONFIG_AUDIT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_842_COMPRESS=y +CONFIG_842_DECOMPRESS=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=m +CONFIG_LZ4HC_COMPRESS=m +CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_COMMON=y +CONFIG_ZSTD_COMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=m +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_REED_SOLOMON_DEC16=y +CONFIG_BCH=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_BTREE=y +CONFIG_INTERVAL_TREE=y +CONFIG_INTERVAL_TREE_SPAN_ITER=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_DMA_DEFAULT_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_CMA=y +CONFIG_DMA_PERNUMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=0 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +CONFIG_CHECK_SIGNATURE=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_LRU_CACHE=m +CONFIG_CLZ_TAB=y +CONFIG_IRQ_POLL=y +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_6x10 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +CONFIG_FONT_TER16x32=y +# CONFIG_FONT_6x8 is not set +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_MEMREGION=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_SBITMAP=y +CONFIG_PARMAN=m +CONFIG_OBJAGG=m +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_PLDMFW=y +CONFIG_ASN1_ENCODER=m +CONFIG_POLYNOMIAL=m + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_NONE is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO_BTF=y +CONFIG_PAHOLE_HAS_SPLIT_BTF=y +CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_GDB_SCRIPTS is not set +CONFIG_FRAME_WARN=2048 +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_KGDB_QXFER_PKT=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_KCSAN_COMPILER=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_PAGE_OWNER=y +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +CONFIG_DEBUG_WX=y +CONFIG_GENERIC_PTDUMP=y +CONFIG_PTDUMP_CORE=y +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +# end of Scheduler Debugging + +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set + +# +# Debug kernel data structures +# +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_TORTURE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_REF_SCALE_TEST=m +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +CONFIG_LATENCYTOP=y +# CONFIG_DEBUG_CGROUP_REF is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_RETHOOK=y +CONFIG_RETHOOK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FPROBE=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_OSNOISE_TRACER=y +CONFIG_TIMERLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y +CONFIG_SYNTH_EVENTS=y +CONFIG_USER_EVENTS=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_RV is not set +# CONFIG_SAMPLES is not set +CONFIG_STRICT_DEVMEM=y +CONFIG_IO_STRICT_DEVMEM=y + +# +# riscv Debugging +# +# end of riscv Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_TEST_DHRY is not set +# CONFIG_LKDTM is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +CONFIG_ASYNC_RAID6_TEST=m +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_STRING_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_IDA is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_KMOD is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_FREE_PAGES is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff --git a/srcpkgs/linux6.4/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch b/srcpkgs/linux6.4/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch new file mode 100644 index 0000000000000..6dfb612487575 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0001-dt-bindings-clock-Add-StarFive-JH7110-System-Top-Gro.patch @@ -0,0 +1,203 @@ +From d906d3e64817687e5f26ba1b8621bff53009a26e Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:24 +0800 +Subject: [PATCH 01/72] dt-bindings: clock: Add StarFive JH7110 + System-Top-Group clock and reset generator + +Add bindings for the System-Top-Group clock and reset generator (STGCRG) +on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-stgcrg.yaml | 82 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 34 ++++++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 28 +++++++ + 3 files changed, 144 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml +new file mode 100644 +index 000000000000..b64ccd84200a +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml +@@ -0,0 +1,82 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 System-Top-Group Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-stgcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Main Oscillator (24 MHz) ++ - description: HIFI4 core ++ - description: STG AXI/AHB ++ - description: USB (125 MHz) ++ - description: CPU Bus ++ - description: HIFI4 Axi ++ - description: NOC STG Bus ++ - description: APB Bus ++ ++ clock-names: ++ items: ++ - const: osc ++ - const: hifi4_core ++ - const: stg_axiahb ++ - const: usb_125m ++ - const: cpu_bus ++ - const: hifi4_axi ++ - const: nocstg_bus ++ - const: apb_bus ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - '#clock-cells' ++ - '#reset-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ stgcrg: clock-controller@10230000 { ++ compatible = "starfive,jh7110-stgcrg"; ++ reg = <0x10230000 0x10000>; ++ clocks = <&osc>, ++ <&syscrg JH7110_SYSCLK_HIFI4_CORE>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&syscrg JH7110_SYSCLK_CPU_BUS>, ++ <&syscrg JH7110_SYSCLK_HIFI4_AXI>, ++ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>; ++ clock-names = "osc", "hifi4_core", ++ "stg_axiahb", "usb_125m", ++ "cpu_bus", "hifi4_axi", ++ "nocstg_bus", "apb_bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 06257bfd9ac1..6c8e8b4cf1f6 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ + /* + * Copyright 2022 Emil Renner Berthing ++ * Copyright 2022 StarFive Technology Co., Ltd. + */ + + #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +@@ -218,4 +219,37 @@ + + #define JH7110_AONCLK_END 14 + ++/* STGCRG clocks */ ++#define JH7110_STGCLK_HIFI4_CLK_CORE 0 ++#define JH7110_STGCLK_USB0_APB 1 ++#define JH7110_STGCLK_USB0_UTMI_APB 2 ++#define JH7110_STGCLK_USB0_AXI 3 ++#define JH7110_STGCLK_USB0_LPM 4 ++#define JH7110_STGCLK_USB0_STB 5 ++#define JH7110_STGCLK_USB0_APP_125 6 ++#define JH7110_STGCLK_USB0_REFCLK 7 ++#define JH7110_STGCLK_PCIE0_AXI_MST0 8 ++#define JH7110_STGCLK_PCIE0_APB 9 ++#define JH7110_STGCLK_PCIE0_TL 10 ++#define JH7110_STGCLK_PCIE1_AXI_MST0 11 ++#define JH7110_STGCLK_PCIE1_APB 12 ++#define JH7110_STGCLK_PCIE1_TL 13 ++#define JH7110_STGCLK_PCIE_SLV_MAIN 14 ++#define JH7110_STGCLK_SEC_AHB 15 ++#define JH7110_STGCLK_SEC_MISC_AHB 16 ++#define JH7110_STGCLK_GRP0_MAIN 17 ++#define JH7110_STGCLK_GRP0_BUS 18 ++#define JH7110_STGCLK_GRP0_STG 19 ++#define JH7110_STGCLK_GRP1_MAIN 20 ++#define JH7110_STGCLK_GRP1_BUS 21 ++#define JH7110_STGCLK_GRP1_STG 22 ++#define JH7110_STGCLK_GRP1_HIFI 23 ++#define JH7110_STGCLK_E2_RTC 24 ++#define JH7110_STGCLK_E2_CORE 25 ++#define JH7110_STGCLK_E2_DBG 26 ++#define JH7110_STGCLK_DMA1P_AXI 27 ++#define JH7110_STGCLK_DMA1P_AHB 28 ++ ++#define JH7110_STGCLK_END 29 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index d78e38690ceb..4e96ab81dd8e 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -1,6 +1,7 @@ + /* SPDX-License-Identifier: GPL-2.0 OR MIT */ + /* + * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + + #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ +@@ -151,4 +152,31 @@ + + #define JH7110_AONRST_END 8 + ++/* STGCRG resets */ ++#define JH7110_STGRST_SYSCON 0 ++#define JH7110_STGRST_HIFI4_CORE 1 ++#define JH7110_STGRST_HIFI4_AXI 2 ++#define JH7110_STGRST_SEC_AHB 3 ++#define JH7110_STGRST_E24_CORE 4 ++#define JH7110_STGRST_DMA1P_AXI 5 ++#define JH7110_STGRST_DMA1P_AHB 6 ++#define JH7110_STGRST_USB0_AXI 7 ++#define JH7110_STGRST_USB0_APB 8 ++#define JH7110_STGRST_USB0_UTMI_APB 9 ++#define JH7110_STGRST_USB0_PWRUP 10 ++#define JH7110_STGRST_PCIE0_AXI_MST0 11 ++#define JH7110_STGRST_PCIE0_AXI_SLV0 12 ++#define JH7110_STGRST_PCIE0_AXI_SLV 13 ++#define JH7110_STGRST_PCIE0_BRG 14 ++#define JH7110_STGRST_PCIE0_CORE 15 ++#define JH7110_STGRST_PCIE0_APB 16 ++#define JH7110_STGRST_PCIE1_AXI_MST0 17 ++#define JH7110_STGRST_PCIE1_AXI_SLV0 18 ++#define JH7110_STGRST_PCIE1_AXI_SLV 19 ++#define JH7110_STGRST_PCIE1_BRG 20 ++#define JH7110_STGRST_PCIE1_CORE 21 ++#define JH7110_STGRST_PCIE1_APB 22 ++ ++#define JH7110_STGRST_END 23 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0002-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch b/srcpkgs/linux6.4/patches/0002-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch new file mode 100644 index 0000000000000..d0ba3d1e83e37 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0002-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch @@ -0,0 +1,228 @@ +From c33ae0897a16ac9c3d5fdcd032de6dd005a1b222 Mon Sep 17 00:00:00 2001 +From: Emil Renner Berthing +Date: Thu, 18 May 2023 18:12:25 +0800 +Subject: [PATCH 02/72] clk: starfive: Add StarFive JH7110 System-Top-Group + clock driver + +Add driver for the StarFive JH7110 System-Top-Group clock controller. + +Co-developed-by: Xingyu Wu +Signed-off-by: Xingyu Wu +Signed-off-by: Emil Renner Berthing +--- + drivers/clk/starfive/Kconfig | 11 ++ + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-stg.c | 173 ++++++++++++++++++ + 3 files changed, 185 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 5d2333106f13..d252c03bfb81 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -39,3 +39,14 @@ config CLK_STARFIVE_JH7110_AON + help + Say yes here to support the always-on clock controller on the + StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_STG ++ tristate "StarFive JH7110 System-Top-Group clock support" ++ depends on CLK_STARFIVE_JH7110_SYS ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the System-Top-Group clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index f3df7d957b1e..b81e97ee2659 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -6,3 +6,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c +new file mode 100644 +index 000000000000..dafcb7190592 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c +@@ -0,0 +1,173 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 System-Top-Group Clock Driver ++ * ++ * Copyright (C) 2022 Emil Renner Berthing ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_STGCLK_OSC (JH7110_STGCLK_END + 0) ++#define JH7110_STGCLK_HIFI4_CORE (JH7110_STGCLK_END + 1) ++#define JH7110_STGCLK_STG_AXIAHB (JH7110_STGCLK_END + 2) ++#define JH7110_STGCLK_USB_125M (JH7110_STGCLK_END + 3) ++#define JH7110_STGCLK_CPU_BUS (JH7110_STGCLK_END + 4) ++#define JH7110_STGCLK_HIFI4_AXI (JH7110_STGCLK_END + 5) ++#define JH7110_STGCLK_NOCSTG_BUS (JH7110_STGCLK_END + 6) ++#define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7) ++#define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8) ++ ++static const struct jh71x0_clk_data jh7110_stgclk_data[] = { ++ /* hifi4 */ ++ JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, ++ JH7110_STGCLK_HIFI4_CORE), ++ /* usb */ ++ JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), ++ JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), ++ JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), ++ JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), ++ /* pci-e */ ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), ++ JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ /* security */ ++ JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++ /* stg mtrx */ ++ JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_CPU_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, ++ JH7110_STGCLK_NOCSTG_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, ++ JH7110_STGCLK_CPU_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, ++ JH7110_STGCLK_NOCSTG_BUS), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, ++ JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, ++ JH7110_STGCLK_HIFI4_AXI), ++ /* e24_rvpi */ ++ JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), ++ JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), ++ /* dw_sgdma1p */ ++ JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), ++ JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), ++}; ++ ++static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_STGCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int jh7110_stgcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ for (idx = 0; idx < JH7110_STGCLK_END; idx++) { ++ u32 max = jh7110_stgclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_stgclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_stgclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = { ++ "osc", ++ "hifi4_core", ++ "stg_axiahb", ++ "usb_125m", ++ "cpu_bus", ++ "hifi4_axi", ++ "nocstg_bus", ++ "apb_bus" ++ }; ++ unsigned int i; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_stgclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_STGCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx < JH7110_STGCLK_EXT_END) ++ parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ return ret; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv); ++ if (ret) ++ return ret; ++ ++ return jh7110_reset_controller_register(priv, "rst-stg", 2); ++} ++ ++static const struct of_device_id jh7110_stgcrg_match[] = { ++ { .compatible = "starfive,jh7110-stgcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match); ++ ++static struct platform_driver jh7110_stgcrg_driver = { ++ .probe = jh7110_stgcrg_probe, ++ .driver = { ++ .name = "clk-starfive-jh7110-stg", ++ .of_match_table = jh7110_stgcrg_match, ++ }, ++}; ++module_platform_driver(jh7110_stgcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_AUTHOR("Emil Renner Berthing "); ++MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0003-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch b/srcpkgs/linux6.4/patches/0003-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch new file mode 100644 index 0000000000000..5c75104894c25 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0003-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch @@ -0,0 +1,166 @@ +From 7ef5d2d038dcba492f80da35eba2890c2e7289e0 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:26 +0800 +Subject: [PATCH 03/72] dt-bindings: clock: Add StarFive JH7110 + Image-Signal-Process clock and reset generator + +Add bindings for the Image-Signal-Process clock and reset +generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-ispcrg.yaml | 87 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 18 ++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++ + 3 files changed, 121 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml +new file mode 100644 +index 000000000000..3b8b85be5cd0 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml +@@ -0,0 +1,87 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-ispcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: ISP Top core ++ - description: ISP Top Axi ++ - description: NOC ISP Bus ++ - description: external DVP ++ ++ clock-names: ++ items: ++ - const: isp_top_core ++ - const: isp_top_axi ++ - const: noc_bus_isp_axi ++ - const: dvp_clk ++ ++ resets: ++ items: ++ - description: ISP Top core ++ - description: ISP Top Axi ++ - description: NOC ISP Bus ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ power-domains: ++ maxItems: 1 ++ description: ++ ISP domain power ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - '#clock-cells' ++ - '#reset-cells' ++ - power-domains ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ ispcrg: clock-controller@19810000 { ++ compatible = "starfive,jh7110-ispcrg"; ++ reg = <0x19810000 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, ++ <&dvp_clk>; ++ clock-names = "isp_top_core", "isp_top_axi", ++ "noc_bus_isp_axi", "dvp_clk"; ++ resets = <&syscrg JH7110_SYSRST_ISP_TOP>, ++ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_ISP>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 6c8e8b4cf1f6..39acf30db491 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -252,4 +252,22 @@ + + #define JH7110_STGCLK_END 29 + ++/* ISPCRG clocks */ ++#define JH7110_ISPCLK_DOM4_APB_FUNC 0 ++#define JH7110_ISPCLK_MIPI_RX0_PXL 1 ++#define JH7110_ISPCLK_DVP_INV 2 ++#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 ++#define JH7110_ISPCLK_M31DPHY_REF_IN 4 ++#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 ++#define JH7110_ISPCLK_VIN_APB 6 ++#define JH7110_ISPCLK_VIN_SYS 7 ++#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 ++#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 ++#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 ++#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 ++#define JH7110_ISPCLK_VIN_P_AXI_WR 12 ++#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 ++ ++#define JH7110_ISPCLK_END 14 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index 4e96ab81dd8e..2c5d9dcefffa 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -179,4 +179,20 @@ + + #define JH7110_STGRST_END 23 + ++/* ISPCRG resets */ ++#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 ++#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 ++#define JH7110_ISPRST_M31DPHY_HW 2 ++#define JH7110_ISPRST_M31DPHY_B09_AON 3 ++#define JH7110_ISPRST_VIN_APB 4 ++#define JH7110_ISPRST_VIN_PIXEL_IF0 5 ++#define JH7110_ISPRST_VIN_PIXEL_IF1 6 ++#define JH7110_ISPRST_VIN_PIXEL_IF2 7 ++#define JH7110_ISPRST_VIN_PIXEL_IF3 8 ++#define JH7110_ISPRST_VIN_SYS 9 ++#define JH7110_ISPRST_VIN_P_AXI_RD 10 ++#define JH7110_ISPRST_VIN_P_AXI_WR 11 ++ ++#define JH7110_ISPRST_END 12 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0004-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch b/srcpkgs/linux6.4/patches/0004-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch new file mode 100644 index 0000000000000..c057a417fa91e --- /dev/null +++ b/srcpkgs/linux6.4/patches/0004-clk-starfive-Add-StarFive-JH7110-Image-Signal-Proces.patch @@ -0,0 +1,305 @@ +From 2ad306ce7b3b759e2430a8028a2ce8afc5927e32 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:27 +0800 +Subject: [PATCH 04/72] clk: starfive: Add StarFive JH7110 Image-Signal-Process + clock driver + +Add driver for the StarFive JH7110 Image-Signal-Process clock controller. +And these clock controllers should power on and enable the clocks from +SYSCRG first before registering. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 11 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-isp.c | 232 ++++++++++++++++++ + drivers/clk/starfive/clk-starfive-jh7110.h | 6 + + 4 files changed, 250 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-isp.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index d252c03bfb81..0a63a47e4b97 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -50,3 +50,14 @@ config CLK_STARFIVE_JH7110_STG + help + Say yes here to support the System-Top-Group clock controller + on the StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_ISP ++ tristate "StarFive JH7110 Image-Signal-Process clock support" ++ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the Image-Signal-Process clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index b81e97ee2659..76fb9f8d628b 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c +new file mode 100644 +index 000000000000..7e51447060fe +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c +@@ -0,0 +1,232 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 Image-Signal-Process Clock Driver ++ * ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_ISPCLK_ISP_TOP_CORE (JH7110_ISPCLK_END + 0) ++#define JH7110_ISPCLK_ISP_TOP_AXI (JH7110_ISPCLK_END + 1) ++#define JH7110_ISPCLK_NOC_BUS_ISP_AXI (JH7110_ISPCLK_END + 2) ++#define JH7110_ISPCLK_DVP_CLK (JH7110_ISPCLK_END + 3) ++#define JH7110_ISPCLK_EXT_END (JH7110_ISPCLK_END + 4) ++ ++static struct clk_bulk_data jh7110_isp_top_clks[] = { ++ { .id = "isp_top_core" }, ++ { .id = "isp_top_axi" } ++}; ++ ++static const struct jh71x0_clk_data jh7110_ispclk_data[] = { ++ /* syscon */ ++ JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, ++ JH7110_ISPCLK_ISP_TOP_AXI), ++ JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), ++ /* vin */ ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, ++ JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, ++ JH7110_ISPCLK_DOM4_APB_FUNC), ++ JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, ++ JH7110_ISPCLK_MIPI_RX0_PXL), ++ JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, ++ JH7110_ISPCLK_MIPI_RX0_PXL, ++ JH7110_ISPCLK_DVP_INV), ++ /* ispv2_top_wrapper */ ++ JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, ++ JH7110_ISPCLK_MIPI_RX0_PXL, ++ JH7110_ISPCLK_DVP_INV), ++}; ++ ++static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) ++{ ++ struct reset_control *top_rsts; ++ ++ /* The resets should be shared and other ISP modules will use its. */ ++ top_rsts = devm_reset_control_array_get_shared(priv->dev); ++ if (IS_ERR(top_rsts)) ++ return dev_err_probe(priv->dev, PTR_ERR(top_rsts), ++ "failed to get top resets\n"); ++ ++ return reset_control_deassert(top_rsts); ++} ++ ++static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_ISPCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++#ifdef CONFIG_PM ++static int jh7110_ispcrg_suspend(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); ++ ++ return 0; ++} ++ ++static int jh7110_ispcrg_resume(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); ++} ++#endif ++ ++static const struct dev_pm_ops jh7110_ispcrg_pm_ops = { ++ SET_RUNTIME_PM_OPS(jh7110_ispcrg_suspend, jh7110_ispcrg_resume, NULL) ++}; ++ ++static int jh7110_ispcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ struct top_sysclk *top; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_ISPCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); ++ if (!top) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ top->top_clks = jh7110_isp_top_clks; ++ top->top_clks_num = ARRAY_SIZE(jh7110_isp_top_clks); ++ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, "failed to get main clocks\n"); ++ dev_set_drvdata(priv->dev, top); ++ ++ /* enable power domain and clocks */ ++ pm_runtime_enable(priv->dev); ++ ret = pm_runtime_get_sync(priv->dev); ++ if (ret < 0) ++ return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); ++ ++ ret = jh7110_isp_top_rst_init(priv); ++ if (ret) ++ goto err_exit; ++ ++ for (idx = 0; idx < JH7110_ISPCLK_END; idx++) { ++ u32 max = jh7110_ispclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_ispclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_ispclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = { ++ "isp_top_core", ++ "isp_top_axi", ++ "noc_bus_isp_axi", ++ "dvp_clk" ++ }; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_ispclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_ISPCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else ++ parents[i].fw_name = fw_name[pidx - JH7110_ISPCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ goto err_exit; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_ispclk_get, priv); ++ if (ret) ++ goto err_exit; ++ ++ ret = jh7110_reset_controller_register(priv, "rst-isp", 3); ++ if (ret) ++ goto err_exit; ++ ++ return 0; ++ ++err_exit: ++ pm_runtime_put_sync(priv->dev); ++ pm_runtime_disable(priv->dev); ++ return ret; ++} ++ ++static int jh7110_ispcrg_remove(struct platform_device *pdev) ++{ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_ispcrg_match[] = { ++ { .compatible = "starfive,jh7110-ispcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_ispcrg_match); ++ ++static struct platform_driver jh7110_ispcrg_driver = { ++ .probe = jh7110_ispcrg_probe, ++ .remove = jh7110_ispcrg_remove, ++ .driver = { ++ .name = "clk-starfive-jh7110-isp", ++ .of_match_table = jh7110_ispcrg_match, ++ .pm = &jh7110_ispcrg_pm_ops, ++ }, ++}; ++module_platform_driver(jh7110_ispcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive JH7110 Image-Signal-Process clock driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h +index f29682b8d400..5425fd89394a 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110.h ++++ b/drivers/clk/starfive/clk-starfive-jh7110.h +@@ -4,6 +4,12 @@ + + #include "clk-starfive-jh71x0.h" + ++/* top clocks of ISP/VOUT domain from SYSCRG */ ++struct top_sysclk { ++ struct clk_bulk_data *top_clks; ++ int top_clks_num; ++}; ++ + int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, + const char *adev_name, + u32 adev_id); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0005-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch b/srcpkgs/linux6.4/patches/0005-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch new file mode 100644 index 0000000000000..8cbfb46d8bfc7 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0005-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch @@ -0,0 +1,173 @@ +From 277cf58bd957d7ea052da0126ac9af70b9269779 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:28 +0800 +Subject: [PATCH 05/72] dt-bindings: clock: Add StarFive JH7110 Video-Output + clock and reset generator + +Add bindings for the Video-Output clock and reset generator (VOUTCRG) +on the JH7110 RISC-V SoC by StarFive Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-voutcrg.yaml | 90 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 22 +++++ + .../dt-bindings/reset/starfive,jh7110-crg.h | 16 ++++ + 3 files changed, 128 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml +new file mode 100644 +index 000000000000..af77bd8c86b1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml +@@ -0,0 +1,90 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Video-Output Clock and Reset Generator ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-voutcrg ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Vout Top core ++ - description: Vout Top Ahb ++ - description: Vout Top Axi ++ - description: Vout Top HDMI MCLK ++ - description: I2STX0 BCLK ++ - description: external HDMI pixel ++ ++ clock-names: ++ items: ++ - const: vout_src ++ - const: vout_top_ahb ++ - const: vout_top_axi ++ - const: vout_top_hdmitx0_mclk ++ - const: i2stx0_bclk ++ - const: hdmitx0_pixelclk ++ ++ resets: ++ maxItems: 1 ++ description: Vout Top core ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ '#reset-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++ power-domains: ++ maxItems: 1 ++ description: ++ Vout domain power ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - '#clock-cells' ++ - '#reset-cells' ++ - power-domains ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ #include ++ #include ++ ++ voutcrg: clock-controller@295C0000 { ++ compatible = "starfive,jh7110-voutcrg"; ++ reg = <0x295C0000 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, ++ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "vout_src", "vout_top_ahb", ++ "vout_top_axi", "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", "hdmitx0_pixelclk"; ++ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_VOUT>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 39acf30db491..016227c64a27 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -270,4 +270,26 @@ + + #define JH7110_ISPCLK_END 14 + ++/* VOUTCRG clocks */ ++#define JH7110_VOUTCLK_APB 0 ++#define JH7110_VOUTCLK_DC8200_PIX 1 ++#define JH7110_VOUTCLK_DSI_SYS 2 ++#define JH7110_VOUTCLK_TX_ESC 3 ++#define JH7110_VOUTCLK_DC8200_AXI 4 ++#define JH7110_VOUTCLK_DC8200_CORE 5 ++#define JH7110_VOUTCLK_DC8200_AHB 6 ++#define JH7110_VOUTCLK_DC8200_PIX0 7 ++#define JH7110_VOUTCLK_DC8200_PIX1 8 ++#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 ++#define JH7110_VOUTCLK_DSITX_APB 10 ++#define JH7110_VOUTCLK_DSITX_SYS 11 ++#define JH7110_VOUTCLK_DSITX_DPI 12 ++#define JH7110_VOUTCLK_DSITX_TXESC 13 ++#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 ++#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 ++#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 ++#define JH7110_VOUTCLK_HDMI_TX_SYS 17 ++ ++#define JH7110_VOUTCLK_END 18 ++ + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ +diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h +index 2c5d9dcefffa..eaf4a0d84f6a 100644 +--- a/include/dt-bindings/reset/starfive,jh7110-crg.h ++++ b/include/dt-bindings/reset/starfive,jh7110-crg.h +@@ -195,4 +195,20 @@ + + #define JH7110_ISPRST_END 12 + ++/* VOUTCRG resets */ ++#define JH7110_VOUTRST_DC8200_AXI 0 ++#define JH7110_VOUTRST_DC8200_AHB 1 ++#define JH7110_VOUTRST_DC8200_CORE 2 ++#define JH7110_VOUTRST_DSITX_DPI 3 ++#define JH7110_VOUTRST_DSITX_APB 4 ++#define JH7110_VOUTRST_DSITX_RXESC 5 ++#define JH7110_VOUTRST_DSITX_SYS 6 ++#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 ++#define JH7110_VOUTRST_DSITX_TXESC 8 ++#define JH7110_VOUTRST_HDMI_TX_HDMI 9 ++#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 ++#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 ++ ++#define JH7110_VOUTRST_END 12 ++ + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0006-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch b/srcpkgs/linux6.4/patches/0006-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch new file mode 100644 index 0000000000000..e7a5ddc8f5130 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0006-clk-starfive-Add-StarFive-JH7110-Video-Output-clock-.patch @@ -0,0 +1,294 @@ +From 5978e767e61784d721c4e3a7aa3dd39e14a81e78 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:29 +0800 +Subject: [PATCH 06/72] clk: starfive: Add StarFive JH7110 Video-Output clock + driver + +Add driver for the StarFive JH7110 Video-Output clock controller. +And these clock controllers should power on and enable the clocks from +SYSCRG first before registering. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 11 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-vout.c | 239 ++++++++++++++++++ + 3 files changed, 251 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 0a63a47e4b97..c506de9346c5 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -61,3 +61,14 @@ config CLK_STARFIVE_JH7110_ISP + help + Say yes here to support the Image-Signal-Process clock controller + on the StarFive JH7110 SoC. ++ ++config CLK_STARFIVE_JH7110_VOUT ++ tristate "StarFive JH7110 Video-Output clock support" ++ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU ++ select AUXILIARY_BUS ++ select CLK_STARFIVE_JH71X0 ++ select RESET_STARFIVE_JH7110 ++ default m if ARCH_STARFIVE ++ help ++ Say yes here to support the Video-Output clock controller ++ on the StarFive JH7110 SoC. +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 76fb9f8d628b..841377e45bb6 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o ++obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c +new file mode 100644 +index 000000000000..743840e03d81 +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c +@@ -0,0 +1,239 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 Video-Output Clock Driver ++ * ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clk-starfive-jh7110.h" ++ ++/* external clocks */ ++#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0) ++#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1) ++#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2) ++#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3) ++#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4) ++#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5) ++#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6) ++ ++static struct clk_bulk_data jh7110_vout_top_clks[] = { ++ { .id = "vout_src" }, ++ { .id = "vout_top_ahb" } ++}; ++ ++static const struct jh71x0_clk_data jh7110_voutclk_data[] = { ++ /* divider */ ++ JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), ++ JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), ++ JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ /* dc8200 */ ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), ++ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), ++ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ /* LCD */ ++ JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX0, ++ JH7110_VOUTCLK_DC8200_PIX1), ++ /* dsiTx */ ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), ++ JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, ++ JH7110_VOUTCLK_DC8200_PIX, ++ JH7110_VOUTCLK_HDMITX0_PIXELCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), ++ /* mipitx DPHY */ ++ JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, ++ JH7110_VOUTCLK_TX_ESC), ++ /* hdmi */ ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, ++ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, ++ JH7110_VOUTCLK_I2STX0_BCLK), ++ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), ++}; ++ ++static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) ++{ ++ struct reset_control *top_rst; ++ ++ /* The reset should be shared and other Vout modules will use its. */ ++ top_rst = devm_reset_control_get_shared(priv->dev, NULL); ++ if (IS_ERR(top_rst)) ++ return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n"); ++ ++ return reset_control_deassert(top_rst); ++} ++ ++static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh71x0_clk_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_VOUTCLK_END) ++ return &priv->reg[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++#ifdef CONFIG_PM ++static int jh7110_voutcrg_suspend(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks); ++ ++ return 0; ++} ++ ++static int jh7110_voutcrg_resume(struct device *dev) ++{ ++ struct top_sysclk *top = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks); ++} ++#endif ++ ++static const struct dev_pm_ops jh7110_voutcrg_pm_ops = { ++ SET_RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL) ++}; ++ ++static int jh7110_voutcrg_probe(struct platform_device *pdev) ++{ ++ struct jh71x0_clk_priv *priv; ++ struct top_sysclk *top; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, ++ struct_size(priv, reg, JH7110_VOUTCLK_END), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL); ++ if (!top) ++ return -ENOMEM; ++ ++ spin_lock_init(&priv->rmw_lock); ++ priv->dev = &pdev->dev; ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return PTR_ERR(priv->base); ++ ++ top->top_clks = jh7110_vout_top_clks; ++ top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks); ++ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n"); ++ dev_set_drvdata(priv->dev, top); ++ ++ /* enable power domain and clocks */ ++ pm_runtime_enable(priv->dev); ++ ret = pm_runtime_get_sync(priv->dev); ++ if (ret < 0) ++ return dev_err_probe(priv->dev, ret, "failed to turn on power\n"); ++ ++ ret = jh7110_vout_top_rst_init(priv); ++ if (ret) ++ goto err_exit; ++ ++ for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) { ++ u32 max = jh7110_voutclk_data[idx].max; ++ struct clk_parent_data parents[4] = {}; ++ struct clk_init_data init = { ++ .name = jh7110_voutclk_data[idx].name, ++ .ops = starfive_jh71x0_clk_ops(max), ++ .parent_data = parents, ++ .num_parents = ++ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, ++ .flags = jh7110_voutclk_data[idx].flags, ++ }; ++ struct jh71x0_clk *clk = &priv->reg[idx]; ++ unsigned int i; ++ const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = { ++ "vout_src", ++ "vout_top_ahb", ++ "vout_top_axi", ++ "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", ++ "hdmitx0_pixelclk" ++ }; ++ ++ for (i = 0; i < init.num_parents; i++) { ++ unsigned int pidx = jh7110_voutclk_data[idx].parents[i]; ++ ++ if (pidx < JH7110_VOUTCLK_END) ++ parents[i].hw = &priv->reg[pidx].hw; ++ else if (pidx < JH7110_VOUTCLK_EXT_END) ++ parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END]; ++ } ++ ++ clk->hw.init = &init; ++ clk->idx = idx; ++ clk->max_div = max & JH71X0_CLK_DIV_MASK; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clk->hw); ++ if (ret) ++ goto err_exit; ++ } ++ ++ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv); ++ if (ret) ++ goto err_exit; ++ ++ ret = jh7110_reset_controller_register(priv, "rst-vo", 4); ++ if (ret) ++ goto err_exit; ++ ++ return 0; ++ ++err_exit: ++ pm_runtime_put_sync(priv->dev); ++ pm_runtime_disable(priv->dev); ++ return ret; ++} ++ ++static int jh7110_voutcrg_remove(struct platform_device *pdev) ++{ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id jh7110_voutcrg_match[] = { ++ { .compatible = "starfive,jh7110-voutcrg" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match); ++ ++static struct platform_driver jh7110_voutcrg_driver = { ++ .probe = jh7110_voutcrg_probe, ++ .remove = jh7110_voutcrg_remove, ++ .driver = { ++ .name = "clk-starfive-jh7110-vout", ++ .of_match_table = jh7110_voutcrg_match, ++ .pm = &jh7110_voutcrg_pm_ops, ++ }, ++}; ++module_platform_driver(jh7110_voutcrg_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0007-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch b/srcpkgs/linux6.4/patches/0007-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch new file mode 100644 index 0000000000000..75a568bfb382a --- /dev/null +++ b/srcpkgs/linux6.4/patches/0007-reset-starfive-jh7110-Add-StarFive-STG-ISP-VOUT-rese.patch @@ -0,0 +1,66 @@ +From 9aefccb22c50e8f98aa9a4603c03f4e6ac1994a1 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Thu, 18 May 2023 18:12:31 +0800 +Subject: [PATCH 07/72] reset: starfive: jh7110: Add StarFive STG/ISP/VOUT + resets support + +Add new struct members and auxiliary_device_id of resets to support +System-Top-Group, Image-Signal-Process and Video-Output on the StarFive +JH7110 SoC. + +Signed-off-by: Xingyu Wu +--- + .../reset/starfive/reset-starfive-jh7110.c | 30 +++++++++++++++++++ + 1 file changed, 30 insertions(+) + +diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c +index 2d26ae95c8cc..29a43f0f2ad6 100644 +--- a/drivers/reset/starfive/reset-starfive-jh7110.c ++++ b/drivers/reset/starfive/reset-starfive-jh7110.c +@@ -31,6 +31,24 @@ static const struct jh7110_reset_info jh7110_aon_info = { + .status_offset = 0x3C, + }; + ++static const struct jh7110_reset_info jh7110_stg_info = { ++ .nr_resets = JH7110_STGRST_END, ++ .assert_offset = 0x74, ++ .status_offset = 0x78, ++}; ++ ++static const struct jh7110_reset_info jh7110_isp_info = { ++ .nr_resets = JH7110_ISPRST_END, ++ .assert_offset = 0x38, ++ .status_offset = 0x3C, ++}; ++ ++static const struct jh7110_reset_info jh7110_vout_info = { ++ .nr_resets = JH7110_VOUTRST_END, ++ .assert_offset = 0x48, ++ .status_offset = 0x4C, ++}; ++ + static int jh7110_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) + { +@@ -58,6 +76,18 @@ static const struct auxiliary_device_id jh7110_reset_ids[] = { + .name = "clk_starfive_jh7110_sys.rst-aon", + .driver_data = (kernel_ulong_t)&jh7110_aon_info, + }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-stg", ++ .driver_data = (kernel_ulong_t)&jh7110_stg_info, ++ }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-isp", ++ .driver_data = (kernel_ulong_t)&jh7110_isp_info, ++ }, ++ { ++ .name = "clk_starfive_jh7110_sys.rst-vo", ++ .driver_data = (kernel_ulong_t)&jh7110_vout_info, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0008-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch b/srcpkgs/linux6.4/patches/0008-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch new file mode 100644 index 0000000000000..3d7bf2f040ea4 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0008-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch @@ -0,0 +1,89 @@ +From a7ae866c219ecd2c7857e3bf9f2e76d7d3657e01 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 13 Jun 2023 20:58:46 +0800 +Subject: [PATCH 08/72] dt-bindings: clock: Add StarFive JH7110 PLL clock + generator + +Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +Reviewed-by: Conor Dooley +--- + .../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++ + .../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++ + 2 files changed, 52 insertions(+) + create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml +new file mode 100644 +index 000000000000..8aa8c7b8e42f +--- /dev/null ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml +@@ -0,0 +1,46 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PLL Clock Generator ++ ++description: ++ This PLL are high speed, low jitter frequency synthesizers in JH7110. ++ Each PLL clocks work in integer mode or fraction mode by some dividers, ++ and the configuration registers and dividers are set in several syscon ++ registers. So pll node should be a child of SYS-SYSCON node. ++ The formula for calculating frequency is that, ++ Fvco = Fref * (NI + NF) / M / Q1 ++ ++maintainers: ++ - Xingyu Wu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pll ++ ++ clocks: ++ maxItems: 1 ++ description: Main Oscillator (24 MHz) ++ ++ '#clock-cells': ++ const: 1 ++ description: ++ See for valid indices. ++ ++required: ++ - compatible ++ - clocks ++ - '#clock-cells' ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pll-clock-controller { ++ compatible = "starfive,jh7110-pll"; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; +diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h +index 016227c64a27..ecb5f80d6f23 100644 +--- a/include/dt-bindings/clock/starfive,jh7110-crg.h ++++ b/include/dt-bindings/clock/starfive,jh7110-crg.h +@@ -7,6 +7,12 @@ + #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ + ++/* PLL clocks */ ++#define JH7110_CLK_PLL0_OUT 0 ++#define JH7110_CLK_PLL1_OUT 1 ++#define JH7110_CLK_PLL2_OUT 2 ++#define JH7110_PLLCLK_END 3 ++ + /* SYSCRG clocks */ + #define JH7110_SYSCLK_CPU_ROOT 0 + #define JH7110_SYSCLK_CPU_CORE 1 +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0009-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch b/srcpkgs/linux6.4/patches/0009-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch new file mode 100644 index 0000000000000..96f7fdde7374a --- /dev/null +++ b/srcpkgs/linux6.4/patches/0009-dt-bindings-soc-starfive-Add-StarFive-syscon-module.patch @@ -0,0 +1,86 @@ +From 3756f6d92f996d709c7672df69c94058c63c988a Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Tue, 13 Jun 2023 20:58:47 +0800 +Subject: [PATCH 09/72] dt-bindings: soc: starfive: Add StarFive syscon module + +Add documentation to describe StarFive System Controller Registers. + +Co-developed-by: Xingyu Wu +Signed-off-by: Xingyu Wu +Signed-off-by: William Qiu +--- + .../soc/starfive/starfive,jh7110-syscon.yaml | 62 +++++++++++++++++++ + 1 file changed, 62 insertions(+) + create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + +diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml +new file mode 100644 +index 000000000000..a81190f8a54d +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml +@@ -0,0 +1,62 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 SoC system controller ++ ++maintainers: ++ - William Qiu ++ ++description: | ++ The StarFive JH7110 SoC system controller provides register information such ++ as offset, mask and shift to configure related modules such as MMC and PCIe. ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - const: starfive,jh7110-sys-syscon ++ - const: syscon ++ - const: simple-mfd ++ - items: ++ - enum: ++ - starfive,jh7110-aon-syscon ++ - starfive,jh7110-stg-syscon ++ - const: syscon ++ ++ reg: ++ maxItems: 1 ++ ++ clock-controller: ++ $ref: /schemas/clock/starfive,jh7110-pll.yaml# ++ type: object ++ ++ "#power-domain-cells": ++ const: 1 ++ ++required: ++ - compatible ++ - reg ++ ++allOf: ++ - if: ++ properties: ++ compatible: ++ contains: ++ const: starfive,jh7110-aon-syscon ++ then: ++ required: ++ - "#power-domain-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ syscon@10240000 { ++ compatible = "starfive,jh7110-stg-syscon", "syscon"; ++ reg = <0x10240000 0x1000>; ++ }; ++ ++... +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0010-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch b/srcpkgs/linux6.4/patches/0010-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch new file mode 100644 index 0000000000000..40ffb3578a177 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0010-dt-bindings-clock-jh7110-syscrg-Add-PLL-clock-inputs.patch @@ -0,0 +1,89 @@ +From 5e3adb380c6eb8f9ba218623a9f47ceb0d22c8b1 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 13 Jun 2023 20:58:48 +0800 +Subject: [PATCH 10/72] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs + +Add optional PLL clock inputs from PLL clock generator. + +Signed-off-by: Xingyu Wu +--- + .../clock/starfive,jh7110-syscrg.yaml | 56 +++++++++++++++++++ + 1 file changed, 56 insertions(+) + +diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +index 84373ae31644..5536e5f9e20b 100644 +--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml ++++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +@@ -39,6 +39,33 @@ properties: + - description: External TDM clock + - description: External audio master clock + ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC1 RMII reference or GMAC1 RGMII RX ++ - description: External I2S TX bit clock ++ - description: External I2S TX left/right channel clock ++ - description: External I2S RX bit clock ++ - description: External I2S RX left/right channel clock ++ - description: External TDM clock ++ - description: External audio master clock ++ - description: PLL0 ++ - description: PLL1 ++ - description: PLL2 ++ ++ - items: ++ - description: Main Oscillator (24 MHz) ++ - description: GMAC1 RMII reference ++ - description: GMAC1 RGMII RX ++ - description: External I2S TX bit clock ++ - description: External I2S TX left/right channel clock ++ - description: External I2S RX bit clock ++ - description: External I2S RX left/right channel clock ++ - description: External TDM clock ++ - description: External audio master clock ++ - description: PLL0 ++ - description: PLL1 ++ - description: PLL2 ++ + clock-names: + oneOf: + - items: +@@ -64,6 +91,35 @@ properties: + - const: tdm_ext + - const: mclk_ext + ++ - items: ++ - const: osc ++ - enum: ++ - gmac1_rmii_refin ++ - gmac1_rgmii_rxin ++ - const: i2stx_bclk_ext ++ - const: i2stx_lrck_ext ++ - const: i2srx_bclk_ext ++ - const: i2srx_lrck_ext ++ - const: tdm_ext ++ - const: mclk_ext ++ - const: pll0_out ++ - const: pll1_out ++ - const: pll2_out ++ ++ - items: ++ - const: osc ++ - const: gmac1_rmii_refin ++ - const: gmac1_rgmii_rxin ++ - const: i2stx_bclk_ext ++ - const: i2stx_lrck_ext ++ - const: i2srx_bclk_ext ++ - const: i2srx_lrck_ext ++ - const: tdm_ext ++ - const: mclk_ext ++ - const: pll0_out ++ - const: pll1_out ++ - const: pll2_out ++ + '#clock-cells': + const: 1 + description: +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0011-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch b/srcpkgs/linux6.4/patches/0011-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch new file mode 100644 index 0000000000000..e7b3e23441bf8 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0011-clk-starfive-Add-StarFive-JH7110-PLL-clock-driver.patch @@ -0,0 +1,565 @@ +From 4795c993f23ba6f6878f41862601aafb9c175630 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 13 Jun 2023 20:58:49 +0800 +Subject: [PATCH 11/72] clk: starfive: Add StarFive JH7110 PLL clock driver + +Add driver for the StarFive JH7110 PLL clock controller +and they work by reading and setting syscon registers. + +Co-developed-by: Emil Renner Berthing +Signed-off-by: Emil Renner Berthing +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 8 + + drivers/clk/starfive/Makefile | 1 + + .../clk/starfive/clk-starfive-jh7110-pll.c | 507 ++++++++++++++++++ + 3 files changed, 516 insertions(+) + create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index c506de9346c5..9baabd2df506 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -21,6 +21,14 @@ config CLK_STARFIVE_JH7100_AUDIO + Say Y or M here to support the audio clocks on the StarFive JH7100 + SoC. + ++config CLK_STARFIVE_JH7110_PLL ++ bool "StarFive JH7110 PLL clock support" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE ++ help ++ Say yes here to support the PLL clock controller on the ++ StarFive JH7110 SoC. ++ + config CLK_STARFIVE_JH7110_SYS + bool "StarFive JH7110 system clock support" + depends on ARCH_STARFIVE || COMPILE_TEST +diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile +index 841377e45bb6..199ac0f37a2f 100644 +--- a/drivers/clk/starfive/Makefile ++++ b/drivers/clk/starfive/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o + obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o + obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o + ++obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL) += clk-starfive-jh7110-pll.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o + obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +new file mode 100644 +index 000000000000..b10c142d456d +--- /dev/null ++++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c +@@ -0,0 +1,507 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * StarFive JH7110 PLL Clock Generator Driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * Copyright (C) 2023 Emil Renner Berthing ++ * ++ * This driver is about to register JH7110 PLL clock generator and support ops. ++ * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2. ++ * Each PLL clocks work in integer mode or fraction mode by some dividers, ++ * and the configuration registers and dividers are set in several syscon registers. ++ * The formula for calculating frequency is: ++ * Fvco = Fref * (NI + NF) / M / Q1 ++ * Fref: OSC source clock rate ++ * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0]. ++ * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999. ++ * M: frequency dividing ratio of pre-divider, set by prediv[5:0]. ++ * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* this driver expects a 24MHz input frequency from the oscillator */ ++#define JH7110_PLL_OSC_RATE 24000000UL ++ ++#define JH7110_PLL0_PD_OFFSET 0x18 ++#define JH7110_PLL0_DACPD_SHIFT 24 ++#define JH7110_PLL0_DACPD_MASK BIT(24) ++#define JH7110_PLL0_DSMPD_SHIFT 25 ++#define JH7110_PLL0_DSMPD_MASK BIT(25) ++#define JH7110_PLL0_FBDIV_OFFSET 0x1c ++#define JH7110_PLL0_FBDIV_SHIFT 0 ++#define JH7110_PLL0_FBDIV_MASK GENMASK(11, 0) ++#define JH7110_PLL0_FRAC_OFFSET 0x20 ++#define JH7110_PLL0_PREDIV_OFFSET 0x24 ++ ++#define JH7110_PLL1_PD_OFFSET 0x24 ++#define JH7110_PLL1_DACPD_SHIFT 15 ++#define JH7110_PLL1_DACPD_MASK BIT(15) ++#define JH7110_PLL1_DSMPD_SHIFT 16 ++#define JH7110_PLL1_DSMPD_MASK BIT(16) ++#define JH7110_PLL1_FBDIV_OFFSET 0x24 ++#define JH7110_PLL1_FBDIV_SHIFT 17 ++#define JH7110_PLL1_FBDIV_MASK GENMASK(28, 17) ++#define JH7110_PLL1_FRAC_OFFSET 0x28 ++#define JH7110_PLL1_PREDIV_OFFSET 0x2c ++ ++#define JH7110_PLL2_PD_OFFSET 0x2c ++#define JH7110_PLL2_DACPD_SHIFT 15 ++#define JH7110_PLL2_DACPD_MASK BIT(15) ++#define JH7110_PLL2_DSMPD_SHIFT 16 ++#define JH7110_PLL2_DSMPD_MASK BIT(16) ++#define JH7110_PLL2_FBDIV_OFFSET 0x2c ++#define JH7110_PLL2_FBDIV_SHIFT 17 ++#define JH7110_PLL2_FBDIV_MASK GENMASK(28, 17) ++#define JH7110_PLL2_FRAC_OFFSET 0x30 ++#define JH7110_PLL2_PREDIV_OFFSET 0x34 ++ ++#define JH7110_PLL_FRAC_SHIFT 0 ++#define JH7110_PLL_FRAC_MASK GENMASK(23, 0) ++#define JH7110_PLL_POSTDIV1_SHIFT 28 ++#define JH7110_PLL_POSTDIV1_MASK GENMASK(29, 28) ++#define JH7110_PLL_PREDIV_SHIFT 0 ++#define JH7110_PLL_PREDIV_MASK GENMASK(5, 0) ++ ++enum jh7110_pll_mode { ++ JH7110_PLL_MODE_FRACTION, ++ JH7110_PLL_MODE_INTEGER, ++}; ++ ++struct jh7110_pll_preset { ++ unsigned long freq; ++ u32 frac; /* frac value should be decimals multiplied by 2^24 */ ++ unsigned fbdiv : 12; /* fbdiv value should be 8 to 4095 */ ++ unsigned prediv : 6; ++ unsigned postdiv1 : 2; ++ unsigned mode : 1; ++}; ++ ++struct jh7110_pll_info { ++ char *name; ++ const struct jh7110_pll_preset *presets; ++ unsigned int npresets; ++ struct { ++ unsigned int pd; ++ unsigned int fbdiv; ++ unsigned int frac; ++ unsigned int prediv; ++ } offsets; ++ struct { ++ u32 dacpd; ++ u32 dsmpd; ++ u32 fbdiv; ++ } masks; ++ struct { ++ char dacpd; ++ char dsmpd; ++ char fbdiv; ++ } shifts; ++}; ++ ++#define _JH7110_PLL(_idx, _name, _presets) \ ++ [_idx] = { \ ++ .name = _name, \ ++ .presets = _presets, \ ++ .npresets = ARRAY_SIZE(_presets), \ ++ .offsets = { \ ++ .pd = JH7110_PLL##_idx##_PD_OFFSET, \ ++ .fbdiv = JH7110_PLL##_idx##_FBDIV_OFFSET, \ ++ .frac = JH7110_PLL##_idx##_FRAC_OFFSET, \ ++ .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \ ++ }, \ ++ .masks = { \ ++ .dacpd = JH7110_PLL##_idx##_DACPD_MASK, \ ++ .dsmpd = JH7110_PLL##_idx##_DSMPD_MASK, \ ++ .fbdiv = JH7110_PLL##_idx##_FBDIV_MASK, \ ++ }, \ ++ .shifts = { \ ++ .dacpd = JH7110_PLL##_idx##_DACPD_SHIFT, \ ++ .dsmpd = JH7110_PLL##_idx##_DSMPD_SHIFT, \ ++ .fbdiv = JH7110_PLL##_idx##_FBDIV_SHIFT, \ ++ }, \ ++ } ++#define JH7110_PLL(idx, name, presets) _JH7110_PLL(idx, name, presets) ++ ++struct jh7110_pll_data { ++ struct clk_hw hw; ++ unsigned int idx; ++}; ++ ++struct jh7110_pll_priv { ++ struct device *dev; ++ struct regmap *regmap; ++ struct jh7110_pll_data pll[JH7110_PLLCLK_END]; ++}; ++ ++struct jh7110_pll_regvals { ++ u32 dacpd; ++ u32 dsmpd; ++ u32 fbdiv; ++ u32 frac; ++ u32 postdiv1; ++ u32 prediv; ++}; ++ ++/* ++ * Because the pll frequency is relatively fixed, ++ * it cannot be set arbitrarily, so it needs a specific configuration. ++ * PLL0 frequency should be multiple of 125MHz (USB frequency). ++ */ ++static const struct jh7110_pll_preset jh7110_pll0_presets[] = { ++ { ++ .freq = 375000000, ++ .fbdiv = 125, ++ .prediv = 8, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 500000000, ++ .fbdiv = 125, ++ .prediv = 6, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 625000000, ++ .fbdiv = 625, ++ .prediv = 24, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 750000000, ++ .fbdiv = 125, ++ .prediv = 4, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 875000000, ++ .fbdiv = 875, ++ .prediv = 24, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1000000000, ++ .fbdiv = 125, ++ .prediv = 3, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1250000000, ++ .fbdiv = 625, ++ .prediv = 12, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1375000000, ++ .fbdiv = 1375, ++ .prediv = 24, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1500000000, ++ .fbdiv = 125, ++ .prediv = 2, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, ++}; ++ ++static const struct jh7110_pll_preset jh7110_pll1_presets[] = { ++ { ++ .freq = 1066000000, ++ .fbdiv = 533, ++ .prediv = 12, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1200000000, ++ .fbdiv = 50, ++ .prediv = 1, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1400000000, ++ .fbdiv = 350, ++ .prediv = 6, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1600000000, ++ .fbdiv = 200, ++ .prediv = 3, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, ++}; ++ ++static const struct jh7110_pll_preset jh7110_pll2_presets[] = { ++ { ++ .freq = 1188000000, ++ .fbdiv = 99, ++ .prediv = 2, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, { ++ .freq = 1228800000, ++ .fbdiv = 256, ++ .prediv = 5, ++ .postdiv1 = 0, ++ .mode = JH7110_PLL_MODE_INTEGER, ++ }, ++}; ++ ++static const struct jh7110_pll_info jh7110_plls[JH7110_PLLCLK_END] = { ++ JH7110_PLL(JH7110_CLK_PLL0_OUT, "pll0_out", jh7110_pll0_presets), ++ JH7110_PLL(JH7110_CLK_PLL1_OUT, "pll1_out", jh7110_pll1_presets), ++ JH7110_PLL(JH7110_CLK_PLL2_OUT, "pll2_out", jh7110_pll2_presets), ++}; ++ ++static struct jh7110_pll_data *jh7110_pll_data_from(struct clk_hw *hw) ++{ ++ return container_of(hw, struct jh7110_pll_data, hw); ++} ++ ++static struct jh7110_pll_priv *jh7110_pll_priv_from(struct jh7110_pll_data *pll) ++{ ++ return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]); ++} ++ ++static void jh7110_pll_regvals_get(struct regmap *regmap, ++ const struct jh7110_pll_info *info, ++ struct jh7110_pll_regvals *ret) ++{ ++ u32 val; ++ ++ regmap_read(regmap, info->offsets.pd, &val); ++ ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; ++ ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd; ++ ++ regmap_read(regmap, info->offsets.fbdiv, &val); ++ ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv; ++ ++ regmap_read(regmap, info->offsets.frac, &val); ++ ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT; ++ ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT; ++ ++ regmap_read(regmap, info->offsets.prediv, &val); ++ ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT; ++} ++ ++static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); ++ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); ++ struct jh7110_pll_regvals val; ++ unsigned long rate; ++ ++ jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val); ++ ++ /* ++ * dacpd = dsmpd = 0: fraction mode ++ * dacpd = dsmpd = 1: integer mode, frac value ignored ++ * ++ * rate = parent * (fbdiv + frac/2^24) / prediv / 2^postdiv1 ++ * = (parent * fbdiv + parent * frac / 2^24) / (prediv * 2^postdiv1) ++ */ ++ if (val.dacpd == 0 && val.dsmpd == 0) ++ rate = parent_rate * val.frac / (1UL << 24); ++ else if (val.dacpd == 1 && val.dsmpd == 1) ++ rate = 0; ++ else ++ return 0; ++ ++ rate += parent_rate * val.fbdiv; ++ rate /= val.prediv << val.postdiv1; ++ ++ return rate; ++} ++ ++static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) ++{ ++ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); ++ const struct jh7110_pll_info *info = &jh7110_plls[pll->idx]; ++ const struct jh7110_pll_preset *selected = &info->presets[0]; ++ unsigned int idx; ++ ++ /* if the parent rate doesn't match our expectations the presets won't work */ ++ if (req->best_parent_rate != JH7110_PLL_OSC_RATE) { ++ req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate); ++ return 0; ++ } ++ ++ /* find highest rate lower or equal to the requested rate */ ++ for (idx = 1; idx < info->npresets; idx++) { ++ const struct jh7110_pll_preset *val = &info->presets[idx]; ++ ++ if (req->rate < val->freq) ++ break; ++ ++ selected = val; ++ } ++ ++ req->rate = selected->freq; ++ return 0; ++} ++ ++static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); ++ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); ++ const struct jh7110_pll_info *info = &jh7110_plls[pll->idx]; ++ const struct jh7110_pll_preset *val; ++ unsigned int idx; ++ ++ /* if the parent rate doesn't match our expectations the presets won't work */ ++ if (parent_rate != JH7110_PLL_OSC_RATE) ++ return -EINVAL; ++ ++ for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) { ++ if (val->freq == rate) ++ goto found; ++ } ++ return -EINVAL; ++ ++found: ++ if (val->mode == JH7110_PLL_MODE_FRACTION) ++ regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK, ++ val->frac << JH7110_PLL_FRAC_SHIFT); ++ ++ regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd, ++ (u32)val->mode << info->shifts.dacpd); ++ regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd, ++ (u32)val->mode << info->shifts.dsmpd); ++ regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK, ++ (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT); ++ regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv, ++ val->fbdiv << info->shifts.fbdiv); ++ regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK, ++ (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_DEBUG_FS ++static int jh7110_pll_registers_read(struct seq_file *s, void *unused) ++{ ++ struct jh7110_pll_data *pll = s->private; ++ struct jh7110_pll_priv *priv = jh7110_pll_priv_from(pll); ++ struct jh7110_pll_regvals val; ++ ++ jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val); ++ ++ seq_printf(s, "fbdiv=%u\n" ++ "frac=%u\n" ++ "prediv=%u\n" ++ "postdiv1=%u\n" ++ "dacpd=%u\n" ++ "dsmpd=%u\n", ++ val.fbdiv, val.frac, val.prediv, val.postdiv1, ++ val.dacpd, val.dsmpd); ++ ++ return 0; ++} ++ ++static int jh7110_pll_registers_open(struct inode *inode, struct file *f) ++{ ++ return single_open(f, jh7110_pll_registers_read, inode->i_private); ++} ++ ++static const struct file_operations jh7110_pll_registers_ops = { ++ .owner = THIS_MODULE, ++ .open = jh7110_pll_registers_open, ++ .release = single_release, ++ .read = seq_read, ++ .llseek = seq_lseek ++}; ++ ++static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ struct jh7110_pll_data *pll = jh7110_pll_data_from(hw); ++ ++ debugfs_create_file("registers", 0400, dentry, pll, ++ &jh7110_pll_registers_ops); ++} ++#else ++#define jh7110_pll_debug_init NULL ++#endif ++ ++static const struct clk_ops jh7110_pll_ops = { ++ .recalc_rate = jh7110_pll_recalc_rate, ++ .determine_rate = jh7110_pll_determine_rate, ++ .set_rate = jh7110_pll_set_rate, ++ .debug_init = jh7110_pll_debug_init, ++}; ++ ++static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data) ++{ ++ struct jh7110_pll_priv *priv = data; ++ unsigned int idx = clkspec->args[0]; ++ ++ if (idx < JH7110_PLLCLK_END) ++ return &priv->pll[idx].hw; ++ ++ return ERR_PTR(-EINVAL); ++} ++ ++static int jh7110_pll_probe(struct platform_device *pdev) ++{ ++ struct jh7110_pll_priv *priv; ++ unsigned int idx; ++ int ret; ++ ++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->dev = &pdev->dev; ++ priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent); ++ if (IS_ERR(priv->regmap)) ++ return PTR_ERR(priv->regmap); ++ ++ for (idx = 0; idx < JH7110_PLLCLK_END; idx++) { ++ struct clk_parent_data parents = { ++ .index = 0, ++ }; ++ struct clk_init_data init = { ++ .name = jh7110_plls[idx].name, ++ .ops = &jh7110_pll_ops, ++ .parent_data = &parents, ++ .num_parents = 1, ++ .flags = 0, ++ }; ++ struct jh7110_pll_data *pll = &priv->pll[idx]; ++ ++ pll->hw.init = &init; ++ pll->idx = idx; ++ ++ ret = devm_clk_hw_register(&pdev->dev, &pll->hw); ++ if (ret) ++ return ret; ++ } ++ ++ return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv); ++} ++ ++static const struct of_device_id jh7110_pll_match[] = { ++ { .compatible = "starfive,jh7110-pll" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_pll_match); ++ ++static struct platform_driver jh7110_pll_driver = { ++ .driver = { ++ .name = "clk-starfive-jh7110-pll", ++ .of_match_table = jh7110_pll_match, ++ }, ++}; ++builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0012-clk-starfive-jh7110-sys-Add-PLL-clocks-source-from-D.patch b/srcpkgs/linux6.4/patches/0012-clk-starfive-jh7110-sys-Add-PLL-clocks-source-from-D.patch new file mode 100644 index 0000000000000..3ac6aeb2f5d99 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0012-clk-starfive-jh7110-sys-Add-PLL-clocks-source-from-D.patch @@ -0,0 +1,113 @@ +From e89c503bab46753e9c424d708c4440543b264b55 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 13 Jun 2023 20:58:50 +0800 +Subject: [PATCH 12/72] clk: starfive: jh7110-sys: Add PLL clocks source from + DTS + +Modify PLL clocks source to be got from DTS or +the fixed factor clocks. + +Signed-off-by: Xingyu Wu +--- + drivers/clk/starfive/Kconfig | 1 + + .../clk/starfive/clk-starfive-jh7110-sys.c | 45 +++++++++++-------- + 2 files changed, 28 insertions(+), 18 deletions(-) + +diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig +index 9baabd2df506..2e8539774620 100644 +--- a/drivers/clk/starfive/Kconfig ++++ b/drivers/clk/starfive/Kconfig +@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS + select AUXILIARY_BUS + select CLK_STARFIVE_JH71X0 + select RESET_STARFIVE_JH7110 if RESET_CONTROLLER ++ select CLK_STARFIVE_JH7110_PLL + default ARCH_STARFIVE + help + Say yes here to support the system clock controller on the +diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +index e6031345ef05..d56f48013388 100644 +--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c ++++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c +@@ -7,6 +7,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -386,6 +387,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); + + static int __init jh7110_syscrg_probe(struct platform_device *pdev) + { ++ bool use_fixed_pll = true; /* PLL clocks use fixed factor clocks or PLL driver */ + struct jh71x0_clk_priv *priv; + unsigned int idx; + int ret; +@@ -402,28 +404,29 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + +- /* +- * These PLL clocks are not actually fixed factor clocks and can be +- * controlled by the syscon registers of JH7110. They will be dropped +- * and registered in the PLL clock driver instead. +- */ ++ if (!IS_ERR(devm_clk_get(priv->dev, "pll0_out"))) ++ use_fixed_pll = false; /* can get pll clocks from PLL driver */ ++ ++ /* Use fixed factor clocks if can not get the PLL clocks from DTS */ ++ if (use_fixed_pll) { + /* 24MHz -> 1000.0MHz */ +- priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", +- "osc", 0, 125, 3); +- if (IS_ERR(priv->pll[0])) +- return PTR_ERR(priv->pll[0]); ++ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", ++ "osc", 0, 125, 3); ++ if (IS_ERR(priv->pll[0])) ++ return PTR_ERR(priv->pll[0]); + + /* 24MHz -> 1066.0MHz */ +- priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", +- "osc", 0, 533, 12); +- if (IS_ERR(priv->pll[1])) +- return PTR_ERR(priv->pll[1]); ++ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", ++ "osc", 0, 533, 12); ++ if (IS_ERR(priv->pll[1])) ++ return PTR_ERR(priv->pll[1]); + + /* 24MHz -> 1188.0MHz */ +- priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", +- "osc", 0, 99, 2); +- if (IS_ERR(priv->pll[2])) +- return PTR_ERR(priv->pll[2]); ++ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", ++ "osc", 0, 99, 2); ++ if (IS_ERR(priv->pll[2])) ++ return PTR_ERR(priv->pll[2]); ++ } + + for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { + u32 max = jh7110_sysclk_data[idx].max; +@@ -462,8 +465,14 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) + parents[i].fw_name = "tdm_ext"; + else if (pidx == JH7110_SYSCLK_MCLK_EXT) + parents[i].fw_name = "mclk_ext"; +- else ++ else if (use_fixed_pll) + parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; ++ else if (pidx == JH7110_SYSCLK_PLL0_OUT) ++ parents[i].fw_name = "pll0_out"; ++ else if (pidx == JH7110_SYSCLK_PLL1_OUT) ++ parents[i].fw_name = "pll1_out"; ++ else if (pidx == JH7110_SYSCLK_PLL2_OUT) ++ parents[i].fw_name = "pll2_out"; + } + + clk->hw.init = &init; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0013-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch b/srcpkgs/linux6.4/patches/0013-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch new file mode 100644 index 0000000000000..a00af76680258 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0013-dt-bindings-timer-Add-timer-for-StarFive-JH7110-SoC.patch @@ -0,0 +1,120 @@ +From 23b5035575426b1bd19bb6871ce3086cd72e3f0b Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 27 Jun 2023 13:53:11 +0800 +Subject: [PATCH 13/72] dt-bindings: timer: Add timer for StarFive JH7110 SoC + +Add bindings for the timer on the JH7110 RISC-V SoC +by StarFive Technology Ltd. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Xingyu Wu +--- + .../bindings/timer/starfive,jh7110-timer.yaml | 96 +++++++++++++++++++ + 1 file changed, 96 insertions(+) + create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml + +diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +new file mode 100644 +index 000000000000..9a2dac11eb06 +--- /dev/null ++++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +@@ -0,0 +1,96 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Timer ++ ++maintainers: ++ - Xingyu Wu ++ - Samin Guo ++ ++description: ++ This timer has four free-running 32 bit counters in StarFive JH7110 SoC. ++ And each channel(counter) triggers an interrupt when timeout. They support ++ one-shot mode and continuous-run mode. ++ ++properties: ++ compatible: ++ const: starfive,jh7110-timer ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ items: ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ clocks: ++ items: ++ - description: timer APB ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: ch0 ++ - const: ch1 ++ - const: ch2 ++ - const: ch3 ++ ++ resets: ++ items: ++ - description: timer APB ++ - description: channel 0 ++ - description: channel 1 ++ - description: channel 2 ++ - description: channel 3 ++ ++ reset-names: ++ items: ++ - const: apb ++ - const: ch0 ++ - const: ch1 ++ - const: ch2 ++ - const: ch3 ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ timer@13050000 { ++ compatible = "starfive,jh7110-timer"; ++ reg = <0x13050000 0x10000>; ++ interrupts = <69>, <70>, <71> ,<72>; ++ clocks = <&clk 124>, ++ <&clk 125>, ++ <&clk 126>, ++ <&clk 127>, ++ <&clk 128>; ++ clock-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ resets = <&rst 117>, ++ <&rst 118>, ++ <&rst 119>, ++ <&rst 120>, ++ <&rst 121>; ++ reset-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ }; ++ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0014-clocksource-Add-JH7110-timer-driver.patch b/srcpkgs/linux6.4/patches/0014-clocksource-Add-JH7110-timer-driver.patch new file mode 100644 index 0000000000000..9ecb5feb5a1d1 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0014-clocksource-Add-JH7110-timer-driver.patch @@ -0,0 +1,543 @@ +From 8ad3a78b870a147c4ef73ddca242fa0eff502d05 Mon Sep 17 00:00:00 2001 +From: Xingyu Wu +Date: Tue, 27 Jun 2023 13:53:12 +0800 +Subject: [PATCH 14/72] clocksource: Add JH7110 timer driver + +Add timer driver for the StarFive JH7110 SoC. + +Signed-off-by: Xingyu Wu +--- + drivers/clocksource/Kconfig | 11 + + drivers/clocksource/Makefile | 1 + + drivers/clocksource/timer-jh7110.c | 485 +++++++++++++++++++++++++++++ + 3 files changed, 497 insertions(+) + create mode 100644 drivers/clocksource/timer-jh7110.c + +diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig +index 526382dc7482..a1393ec074c0 100644 +--- a/drivers/clocksource/Kconfig ++++ b/drivers/clocksource/Kconfig +@@ -639,6 +639,17 @@ config RISCV_TIMER + is accessed via both the SBI and the rdcycle instruction. This is + required for all RISC-V systems. + ++config STARFIVE_JH7110_TIMER ++ bool "Timer for the STARFIVE JH7110 SoC" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ select TIMER_OF ++ select CLKSRC_MMIO ++ default ARCH_STARFIVE ++ help ++ This enables the timer for StarFive JH7110 SoCs. On RISC-V platform, ++ the system has started RISCV_TIMER. But you can also use this timer ++ which can provides four channels to do a lot more on JH7110 SoC. ++ + config CLINT_TIMER + bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST + depends on GENERIC_SCHED_CLOCK && RISCV +diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile +index f12d3987a960..791fb3379f50 100644 +--- a/drivers/clocksource/Makefile ++++ b/drivers/clocksource/Makefile +@@ -81,6 +81,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o + obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o + obj-$(CONFIG_X86_NUMACHIP) += numachip.o + obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o ++obj-$(CONFIG_STARFIVE_JH7110_TIMER) += timer-jh7110.o + obj-$(CONFIG_CLINT_TIMER) += timer-clint.o + obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o + obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o +diff --git a/drivers/clocksource/timer-jh7110.c b/drivers/clocksource/timer-jh7110.c +new file mode 100644 +index 000000000000..b88334a916fb +--- /dev/null ++++ b/drivers/clocksource/timer-jh7110.c +@@ -0,0 +1,485 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Starfive JH7110 Timer driver ++ * ++ * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * ++ * Author: ++ * Xingyu Wu ++ * Samin Guo ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */ ++#define JH7110_TIMER_CH_LEN 0x40 ++#define JH7110_TIMER_CH_BASE(x) ((x) * JH7110_TIMER_CH_LEN) ++ ++#define JH7110_CLOCK_SOURCE_RATING 200 ++#define JH7110_VALID_BITS 32 ++#define JH7110_DELAY_US 0 ++#define JH7110_TIMEOUT_US 10000 ++#define JH7110_CLOCKEVENT_RATING 300 ++#define JH7110_TIMER_MAX_TICKS 0xffffffff ++#define JH7110_TIMER_MIN_TICKS 0xf ++#define JH7110_TIMER_NAME_NUM 20 ++ ++#define JH7110_TIMER_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */ ++#define JH7110_TIMER_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */ ++#define JH7110_TIMER_LOAD 0x08 /* RW: load value to counter */ ++#define JH7110_TIMER_ENABLE 0x10 /* RW[0]: timer enable register */ ++#define JH7110_TIMER_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */ ++#define JH7110_TIMER_VALUE 0x18 /* RO: timer value register */ ++#define JH7110_TIMER_INT_CLR 0x20 /* RW: timer interrupt clear register */ ++#define JH7110_TIMER_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */ ++#define JH7110_TIMER_INT_CLR_AVA_MASK BIT(1) ++ ++enum JH7110_TIMER_CH { ++ JH7110_TIMER_CH_0 = 0, ++ JH7110_TIMER_CH_1, ++ JH7110_TIMER_CH_2, ++ JH7110_TIMER_CH_3, ++ JH7110_TIMER_CH_MAX ++}; ++ ++enum JH7110_TIMER_INTMASK { ++ JH7110_TIMER_INTMASK_DIS = 0, ++ JH7110_TIMER_INTMASK_ENA = 1 ++}; ++ ++enum JH7110_TIMER_MOD { ++ JH7110_TIMER_MOD_CONTIN = 0, ++ JH7110_TIMER_MOD_SINGLE = 1 ++}; ++ ++enum JH7110_TIMER_CTL_EN { ++ JH7110_TIMER_DIS = 0, ++ JH7110_TIMER_ENA = 1 ++}; ++ ++struct jh7110_timer_info { ++ /* Resgister */ ++ unsigned int ctrl; ++ unsigned int load; ++ unsigned int enable; ++ unsigned int reload; ++ unsigned int value; ++ unsigned int intclr; ++ unsigned int intmask; ++ unsigned int channel_base[JH7110_TIMER_CH_MAX]; ++}; ++ ++struct jh7110_clkevt { ++ struct clock_event_device evt; ++ struct clocksource cs; ++ struct clk *clk; ++ char name[JH7110_TIMER_NAME_NUM]; ++ int irq; ++ u32 periodic; ++ u32 rate; ++ u32 reload_val; ++ void __iomem *base; ++ void __iomem *ctrl; ++ void __iomem *load; ++ void __iomem *enable; ++ void __iomem *reload; ++ void __iomem *value; ++ void __iomem *intclr; ++ void __iomem *intmask; ++}; ++ ++struct jh7110_timer_priv { ++ struct device *dev; ++ void __iomem *base; ++ struct jh7110_clkevt clkevt[JH7110_TIMER_CH_MAX]; ++}; ++ ++static const struct jh7110_timer_info jh7110_timer_data = { ++ .ctrl = JH7110_TIMER_CTL, ++ .load = JH7110_TIMER_LOAD, ++ .enable = JH7110_TIMER_ENABLE, ++ .reload = JH7110_TIMER_RELOAD, ++ .value = JH7110_TIMER_VALUE, ++ .intclr = JH7110_TIMER_INT_CLR, ++ .intmask = JH7110_TIMER_INT_MASK, ++ .channel_base = {JH7110_TIMER_CH_BASE(JH7110_TIMER_CH_0), ++ JH7110_TIMER_CH_BASE(JH7110_TIMER_CH_1), ++ JH7110_TIMER_CH_BASE(JH7110_TIMER_CH_2), ++ JH7110_TIMER_CH_BASE(JH7110_TIMER_CH_3)}, ++}; ++ ++static inline struct jh7110_clkevt *to_jh7110_clkevt(struct clock_event_device *evt) ++{ ++ return container_of(evt, struct jh7110_clkevt, evt); ++} ++ ++/* 0:continuous-run mode, 1:single-run mode */ ++static inline void jh7110_timer_set_mod(struct jh7110_clkevt *clkevt, int mod) ++{ ++ writel(mod, clkevt->ctrl); ++} ++ ++/* Interrupt Mask Register, 0:Unmask, 1:Mask */ ++static inline void jh7110_timer_int_enable(struct jh7110_clkevt *clkevt) ++{ ++ writel(JH7110_TIMER_INTMASK_DIS, clkevt->intmask); ++} ++ ++static inline void jh7110_timer_int_disable(struct jh7110_clkevt *clkevt) ++{ ++ writel(JH7110_TIMER_INTMASK_ENA, clkevt->intmask); ++} ++ ++/* ++ * BIT(0): Read value represent channel intr status. ++ * Write 1 to this bit to clear interrupt. Write 0 has no effects. ++ * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written. ++ */ ++static inline int jh7110_timer_int_clear(struct jh7110_clkevt *clkevt) ++{ ++ u32 value; ++ int ret; ++ ++ /* waiting interrupt can be to clearing */ ++ ret = readl_poll_timeout_atomic(clkevt->intclr, value, ++ !(value & JH7110_TIMER_INT_CLR_AVA_MASK), ++ JH7110_DELAY_US, JH7110_TIMEOUT_US); ++ if (!ret) ++ writel(0x1, clkevt->intclr); ++ ++ return ret; ++} ++ ++/* ++ * The initial value to be loaded into the ++ * counter and is also used as the reload value. ++ * val = clock rate --> 1s ++ */ ++static inline void jh7110_timer_set_load(struct jh7110_clkevt *clkevt, u32 val) ++{ ++ writel(val, clkevt->load); ++} ++ ++static inline u32 jh7110_timer_get_val(struct jh7110_clkevt *clkevt) ++{ ++ return readl(clkevt->value); ++} ++ ++/* ++ * Write RELOAD register to reload preset value to counter. ++ * Write 0 and write 1 are both ok. ++ */ ++static inline void jh7110_timer_set_reload(struct jh7110_clkevt *clkevt) ++{ ++ writel(0, clkevt->reload); ++} ++ ++static inline void jh7110_timer_enable(struct jh7110_clkevt *clkevt) ++{ ++ writel(JH7110_TIMER_ENA, clkevt->enable); ++} ++ ++static inline void jh7110_timer_disable(struct jh7110_clkevt *clkevt) ++{ ++ writel(JH7110_TIMER_DIS, clkevt->enable); ++} ++ ++static int jh7110_timer_int_init_enable(struct jh7110_clkevt *clkevt) ++{ ++ int ret; ++ ++ jh7110_timer_int_disable(clkevt); ++ ret = jh7110_timer_int_clear(clkevt); ++ if (ret) ++ return ret; ++ ++ jh7110_timer_int_enable(clkevt); ++ jh7110_timer_enable(clkevt); ++ ++ return 0; ++} ++ ++static int jh7110_timer_shutdown(struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ jh7110_timer_disable(clkevt); ++ return jh7110_timer_int_clear(clkevt); ++} ++ ++static void jh7110_timer_suspend(struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ clkevt->reload_val = jh7110_timer_get_val(clkevt); ++ jh7110_timer_shutdown(evt); ++} ++ ++static void jh7110_timer_resume(struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ jh7110_timer_set_load(clkevt, clkevt->reload_val); ++ jh7110_timer_set_reload(clkevt); ++ jh7110_timer_int_enable(clkevt); ++ jh7110_timer_enable(clkevt); ++} ++ ++static int jh7110_timer_tick_resume(struct clock_event_device *evt) ++{ ++ jh7110_timer_resume(evt); ++ ++ return 0; ++} ++ ++static u64 jh7110_timer_clocksource_read(struct clocksource *cs) ++{ ++ struct jh7110_clkevt *clkevt = container_of(cs, struct jh7110_clkevt, cs); ++ ++ return (u64)jh7110_timer_get_val(clkevt); ++} ++ ++static int jh7110_clocksource_init(struct jh7110_clkevt *clkevt) ++{ ++ int ret; ++ ++ jh7110_timer_set_mod(clkevt, JH7110_TIMER_MOD_CONTIN); ++ jh7110_timer_set_load(clkevt, JH7110_TIMER_MAX_TICKS); ++ ++ ret = jh7110_timer_int_init_enable(clkevt); ++ if (ret) ++ return ret; ++ ++ clkevt->cs.name = clkevt->name; ++ clkevt->cs.rating = JH7110_CLOCK_SOURCE_RATING; ++ clkevt->cs.read = jh7110_timer_clocksource_read; ++ clkevt->cs.mask = CLOCKSOURCE_MASK(JH7110_VALID_BITS); ++ clkevt->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; ++ ++ return clocksource_register_hz(&clkevt->cs, clkevt->rate); ++} ++ ++/* IRQ handler for the timer */ ++static irqreturn_t jh7110_timer_interrupt(int irq, void *priv) ++{ ++ struct clock_event_device *evt = (struct clock_event_device *)priv; ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ if (jh7110_timer_int_clear(clkevt)) ++ return IRQ_NONE; ++ ++ if (evt->event_handler) ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static int jh7110_timer_set_periodic(struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ); ++ jh7110_timer_disable(clkevt); ++ jh7110_timer_set_mod(clkevt, JH7110_TIMER_MOD_CONTIN); ++ jh7110_timer_set_load(clkevt, clkevt->periodic); ++ ++ return jh7110_timer_int_init_enable(clkevt); ++} ++ ++static int jh7110_timer_set_oneshot(struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ jh7110_timer_disable(clkevt); ++ jh7110_timer_set_mod(clkevt, JH7110_TIMER_MOD_SINGLE); ++ jh7110_timer_set_load(clkevt, JH7110_TIMER_MAX_TICKS); ++ ++ return jh7110_timer_int_init_enable(clkevt); ++} ++ ++static int jh7110_timer_set_next_event(unsigned long next, ++ struct clock_event_device *evt) ++{ ++ struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); ++ ++ jh7110_timer_disable(clkevt); ++ jh7110_timer_set_mod(clkevt, JH7110_TIMER_MOD_SINGLE); ++ jh7110_timer_set_load(clkevt, next); ++ jh7110_timer_enable(clkevt); ++ ++ return 0; ++} ++ ++static void jh7110_set_clockevent(struct clock_event_device *evt) ++{ ++ evt->features = CLOCK_EVT_FEAT_PERIODIC | ++ CLOCK_EVT_FEAT_ONESHOT | ++ CLOCK_EVT_FEAT_DYNIRQ; ++ evt->set_state_shutdown = jh7110_timer_shutdown; ++ evt->set_state_periodic = jh7110_timer_set_periodic; ++ evt->set_state_oneshot = jh7110_timer_set_oneshot; ++ evt->set_state_oneshot_stopped = jh7110_timer_shutdown; ++ evt->tick_resume = jh7110_timer_tick_resume; ++ evt->set_next_event = jh7110_timer_set_next_event; ++ evt->suspend = jh7110_timer_suspend; ++ evt->resume = jh7110_timer_resume; ++ evt->rating = JH7110_CLOCKEVENT_RATING; ++} ++ ++static void jh7110_clockevents_register(struct jh7110_clkevt *clkevt) ++{ ++ clkevt->rate = clk_get_rate(clkevt->clk); ++ ++ jh7110_set_clockevent(&clkevt->evt); ++ clkevt->evt.name = clkevt->name; ++ clkevt->evt.irq = clkevt->irq; ++ clkevt->evt.cpumask = cpu_possible_mask; ++ ++ clockevents_config_and_register(&clkevt->evt, clkevt->rate, ++ JH7110_TIMER_MIN_TICKS, JH7110_TIMER_MAX_TICKS); ++} ++ ++static void jh7110_clkevt_base_init(const struct jh7110_timer_info *data, ++ struct jh7110_clkevt *clkevt, ++ void __iomem *base, int ch) ++{ ++ void __iomem *channel_base; ++ ++ channel_base = base + data->channel_base[ch]; ++ clkevt->base = channel_base; ++ clkevt->ctrl = channel_base + data->ctrl; ++ clkevt->load = channel_base + data->load; ++ clkevt->enable = channel_base + data->enable; ++ clkevt->reload = channel_base + data->reload; ++ clkevt->value = channel_base + data->value; ++ clkevt->intclr = channel_base + data->intclr; ++ clkevt->intmask = channel_base + data->intmask; ++} ++ ++static int jh7110_timer_probe(struct platform_device *pdev) ++{ ++ const struct jh7110_timer_info *data = of_device_get_match_data(&pdev->dev); ++ char name[JH7110_TIMER_NAME_NUM]; ++ struct jh7110_timer_priv *priv; ++ struct jh7110_clkevt *clkevt; ++ struct clk *pclk; ++ struct reset_control *rst; ++ int ch; ++ int ret; ++ ++ if (!data) ++ return -ENOENT; ++ ++ priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, JH7110_TIMER_CH_MAX), ++ GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(priv->base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(priv->base), ++ "failed to map registers\n"); ++ ++ rst = devm_reset_control_get_exclusive(&pdev->dev, "apb"); ++ if (IS_ERR(rst)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n"); ++ ++ pclk = devm_clk_get_enabled(&pdev->dev, "apb"); ++ if (IS_ERR(pclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pclk), ++ "failed to get & enable apb clock\n"); ++ ++ ret = reset_control_deassert(rst); ++ if (ret) ++ goto err; ++ ++ priv->dev = &pdev->dev; ++ platform_set_drvdata(pdev, priv); ++ ++ for (ch = 0; ch < JH7110_TIMER_CH_MAX; ch++) { ++ clkevt = &priv->clkevt[ch]; ++ snprintf(name, sizeof(name), "ch%d", ch); ++ ++ jh7110_clkevt_base_init(data, clkevt, priv->base, ch); ++ /* Ensure timers are disabled */ ++ jh7110_timer_disable(clkevt); ++ ++ rst = devm_reset_control_get_exclusive(&pdev->dev, name); ++ if (IS_ERR(rst)) { ++ ret = PTR_ERR(rst); ++ goto err; ++ } ++ ++ clkevt->clk = devm_clk_get_enabled(&pdev->dev, name); ++ if (IS_ERR(clkevt->clk)) { ++ ret = PTR_ERR(clkevt->clk); ++ goto err; ++ } ++ ++ ret = reset_control_deassert(rst); ++ if (ret) ++ goto ch_err; ++ ++ clkevt->irq = platform_get_irq(pdev, ch); ++ if (clkevt->irq < 0) { ++ ret = clkevt->irq; ++ goto ch_err; ++ } ++ ++ snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch); ++ jh7110_clockevents_register(clkevt); ++ ++ ret = devm_request_irq(&pdev->dev, clkevt->irq, jh7110_timer_interrupt, ++ IRQF_TIMER | IRQF_IRQPOLL, ++ clkevt->name, &clkevt->evt); ++ if (ret) ++ goto ch_err; ++ ++ ret = jh7110_clocksource_init(clkevt); ++ if (ret) ++ goto ch_err; ++ } ++ ++ return 0; ++ ++ch_err: ++ for (; ch < 0; ch--) ++ clk_disable_unprepare(priv->clkevt[ch].clk); ++err: ++ clk_disable_unprepare(pclk); ++ ++ return ret; ++} ++ ++static const struct of_device_id jh7110_timer_match[] = { ++ { .compatible = "starfive,jh7110-timer", .data = &jh7110_timer_data }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_timer_match); ++ ++static struct platform_driver jh7110_timer_driver = { ++ .probe = jh7110_timer_probe, ++ .driver = { ++ .name = "jh7110-timer", ++ .of_match_table = jh7110_timer_match, ++ }, ++}; ++module_platform_driver(jh7110_timer_driver); ++ ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_DESCRIPTION("StarFive JH7110 timer driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0015-dt-bindings-net-motorcomm-Add-pad-driver-strength-cf.patch b/srcpkgs/linux6.4/patches/0015-dt-bindings-net-motorcomm-Add-pad-driver-strength-cf.patch new file mode 100644 index 0000000000000..0ff41c05e49cf --- /dev/null +++ b/srcpkgs/linux6.4/patches/0015-dt-bindings-net-motorcomm-Add-pad-driver-strength-cf.patch @@ -0,0 +1,41 @@ +From 83bd6d988e201b86a0615496fdd26197bb059b2e Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Tue, 25 Apr 2023 18:51:15 +0800 +Subject: [PATCH 15/72] dt-bindings: net: motorcomm: Add pad driver strength + cfg + +The motorcomm phy (YT8531) supports the ability to adjust the drive +strength of the rx_clk/rx_data, the value range of pad driver +strength is 0 to 7. + +Signed-off-by: Samin Guo +--- + .../devicetree/bindings/net/motorcomm,yt8xxx.yaml | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +index 157e3bbcaf6f..29a1997a1577 100644 +--- a/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml ++++ b/Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml +@@ -52,6 +52,18 @@ properties: + for a timer. + type: boolean + ++ motorcomm,rx-clk-driver-strength: ++ description: drive strength of rx_clk pad. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] ++ default: 3 ++ ++ motorcomm,rx-data-driver-strength: ++ description: drive strength of rx_data/rx_ctl rgmii pad. ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ] ++ default: 3 ++ + motorcomm,tx-clk-adj-enabled: + description: | + This configuration is mainly to adapt to VF2 with JH7110 SoC. +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0016-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch b/srcpkgs/linux6.4/patches/0016-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch new file mode 100644 index 0000000000000..77385778f2169 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0016-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch @@ -0,0 +1,89 @@ +From f6659ebf467f3ab6daab696d0f89a6a0540b61c0 Mon Sep 17 00:00:00 2001 +From: Samin Guo +Date: Tue, 25 Apr 2023 18:43:29 +0800 +Subject: [PATCH 16/72] net: phy: motorcomm: Add pad drive strength cfg support + +The motorcomm phy (YT8531) supports the ability to adjust the drive +strength of the rx_clk/rx_data, and the default strength may not be +suitable for all boards. So add configurable options to better match +the boards.(e.g. StarFive VisionFive 2) + +Signed-off-by: Samin Guo +--- + drivers/net/phy/motorcomm.c | 46 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c +index 2fa5a90e073b..e5d6b491046e 100644 +--- a/drivers/net/phy/motorcomm.c ++++ b/drivers/net/phy/motorcomm.c +@@ -236,6 +236,15 @@ + */ + #define YTPHY_WCR_TYPE_PULSE BIT(0) + ++#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 ++#define YT8531_RGMII_RXC_DS_DEFAULT 0x3 ++#define YT8531_RGMII_RXC_DS_MAX 0x7 ++#define YT8531_RGMII_RXC_DS GENMASK(15, 13) ++#define YT8531_RGMII_RXD_DS_DEFAULT 0x3 ++#define YT8531_RGMII_RXD_DS_MAX 0x7 ++#define YT8531_RGMII_RXD_DS_LOW GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ ++#define YT8531_RGMII_RXD_DS_HI BIT(12) /* Bit 2 of rxd_ds */ ++ + #define YTPHY_SYNCE_CFG_REG 0xA012 + #define YT8521_SCR_SYNCE_ENABLE BIT(5) + /* 1b0 output 25m clock +@@ -1494,6 +1503,7 @@ static int yt8521_config_init(struct phy_device *phydev) + static int yt8531_config_init(struct phy_device *phydev) + { + struct device_node *node = phydev->mdio.dev.of_node; ++ u32 ds, val; + int ret; + + ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); +@@ -1518,6 +1528,42 @@ static int yt8531_config_init(struct phy_device *phydev) + return ret; + } + ++ ds = YT8531_RGMII_RXC_DS_DEFAULT; ++ if (!of_property_read_u32(node, "motorcomm,rx-clk-driver-strength", &val)) { ++ if (val > YT8531_RGMII_RXC_DS_MAX) ++ return -EINVAL; ++ ++ ds = val; ++ } ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXC_DS, ++ FIELD_PREP(YT8531_RGMII_RXC_DS, ds)); ++ if (ret < 0) ++ return ret; ++ ++ ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, YT8531_RGMII_RXD_DS_DEFAULT); ++ if (!of_property_read_u32(node, "motorcomm,rx-data-driver-strength", &val)) { ++ if (val > YT8531_RGMII_RXD_DS_MAX) ++ return -EINVAL; ++ ++ if (val > FIELD_MAX(YT8531_RGMII_RXD_DS_LOW)) { ++ ds = val & FIELD_MAX(YT8531_RGMII_RXD_DS_LOW); ++ ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, ds); ++ ds |= YT8531_RGMII_RXD_DS_HI; ++ } else { ++ ds = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW, val); ++ } ++ } ++ ++ ret = ytphy_modify_ext_with_lock(phydev, ++ YTPHY_PAD_DRIVE_STRENGTH_REG, ++ YT8531_RGMII_RXD_DS_LOW | YT8531_RGMII_RXD_DS_HI, ++ ds); ++ if (ret < 0) ++ return ret; ++ + return 0; + } + +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0017-dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFi.patch b/srcpkgs/linux6.4/patches/0017-dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFi.patch new file mode 100644 index 0000000000000..c3ec07073685e --- /dev/null +++ b/srcpkgs/linux6.4/patches/0017-dt-bindings-qspi-cdns-qspi-nor-Add-clocks-for-StarFi.patch @@ -0,0 +1,65 @@ +From 73fe835ff572cfc6d1eacfda81722b099ad29298 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Mon, 19 Jun 2023 16:35:15 +0800 +Subject: [PATCH 17/72] dt-bindings: qspi: cdns,qspi-nor: Add clocks for + StarFive JH7110 SoC + +The QSPI controller needs three clock items to work properly on StarFive +JH7110 SoC, so there is need to change the maxItems's value to 3. Other +platforms do not have this constraint. + +Signed-off-by: William Qiu +Reviewed-by: Hal Feng +Reviewed-by: Conor Dooley +--- + .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- + 1 file changed, 19 insertions(+), 1 deletion(-) + +diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +index b310069762dd..1b83cbb9a086 100644 +--- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml ++++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +@@ -26,6 +26,15 @@ allOf: + const: starfive,jh7110-qspi + then: + properties: ++ clocks: ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: ref ++ - const: ahb ++ - const: apb ++ + resets: + minItems: 2 + maxItems: 3 +@@ -38,6 +47,9 @@ allOf: + + else: + properties: ++ clocks: ++ maxItems: 1 ++ + resets: + maxItems: 2 + +@@ -70,7 +82,13 @@ properties: + maxItems: 1 + + clocks: +- maxItems: 1 ++ maxItems: 3 ++ ++ clock-names: ++ items: ++ - const: ref ++ - const: ahb ++ - const: apb + + cdns,fifo-depth: + description: +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0018-spi-cadence-quadspi-Add-clock-configuration-for-Star.patch b/srcpkgs/linux6.4/patches/0018-spi-cadence-quadspi-Add-clock-configuration-for-Star.patch new file mode 100644 index 0000000000000..a381e0220b009 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0018-spi-cadence-quadspi-Add-clock-configuration-for-Star.patch @@ -0,0 +1,80 @@ +From 88ecfcfde5f230eaee509dd19c37b6b811a37a7f Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Mon, 19 Jun 2023 16:35:16 +0800 +Subject: [PATCH 18/72] spi: cadence-quadspi: Add clock configuration for + StarFive JH7110 QSPI + +Add QSPI clock operation in device probe. + +Signed-off-by: William Qiu +Reviewed-by: Hal Feng +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/ +Reported-by: Julia Lawall +Closes: https://lore.kernel.org/r/202306040644.6ZHs55x4-lkp@intel.com/ +--- + drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c +index 32449bef4415..dfd2d0b9aaba 100644 +--- a/drivers/spi/spi-cadence-quadspi.c ++++ b/drivers/spi/spi-cadence-quadspi.c +@@ -63,6 +63,8 @@ struct cqspi_st { + struct platform_device *pdev; + struct spi_master *master; + struct clk *clk; ++ struct clk_bulk_data *clks; ++ int num_clks; + unsigned int sclk; + + void __iomem *iobase; +@@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) + } + + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { ++ cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); ++ if (cqspi->num_clks < 0) { ++ dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks); ++ return -EINVAL; ++ } ++ ++ ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); ++ if (ret) ++ dev_err(dev, "Cannot enable clock clks\n"); ++ + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); + if (IS_ERR(rstc_ref)) { + ret = PTR_ERR(rstc_ref); +@@ -1819,6 +1831,9 @@ static void cqspi_remove(struct platform_device *pdev) + + clk_disable_unprepare(cqspi->clk); + ++ if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) ++ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); ++ + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); + } +@@ -1834,6 +1849,9 @@ static int cqspi_suspend(struct device *dev) + + clk_disable_unprepare(cqspi->clk); + ++ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) ++ clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); ++ + return ret; + } + +@@ -1843,6 +1861,8 @@ static int cqspi_resume(struct device *dev) + struct spi_master *master = dev_get_drvdata(dev); + + clk_prepare_enable(cqspi->clk); ++ if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) ++ clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); + cqspi_wait_idle(cqspi); + cqspi_controller_init(cqspi); + +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0019-dt-bindings-pwm-Add-StarFive-PWM-module.patch b/srcpkgs/linux6.4/patches/0019-dt-bindings-pwm-Add-StarFive-PWM-module.patch new file mode 100644 index 0000000000000..64c7470d36af8 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0019-dt-bindings-pwm-Add-StarFive-PWM-module.patch @@ -0,0 +1,80 @@ +From 6919efb1e26a69f152c5b27f3e5d8a2266b68d73 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Thu, 1 Jun 2023 16:51:51 +0800 +Subject: [PATCH 19/72] dt-bindings: pwm: Add StarFive PWM module + +Add documentation to describe StarFive Pulse Width Modulation +controller driver. + +Signed-off-by: William Qiu +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Hal Feng +--- + .../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++ + 1 file changed, 55 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml + +diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml +new file mode 100644 +index 000000000000..6f1937beb962 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml +@@ -0,0 +1,55 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7100 and JH7110 PWM controller ++ ++maintainers: ++ - William Qiu ++ ++description: ++ StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates ++ binary signal with user-programmable low and high periods. Clock source for the ++ PWM can be either system clock or external clock. Each PWM timer block provides 8 ++ PWM channels. ++ ++allOf: ++ - $ref: pwm.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7100-pwm ++ - starfive,jh7110-pwm ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++ "#pwm-cells": ++ const: 3 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - resets ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pwm@12490000 { ++ compatible = "starfive,jh7100-pwm"; ++ reg = <0x12490000 0x10000>; ++ clocks = <&clkgen 181>; ++ resets = <&rstgen 109>; ++ #pwm-cells = <3>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0020-pwm-starfive-Add-PWM-driver-support.patch b/srcpkgs/linux6.4/patches/0020-pwm-starfive-Add-PWM-driver-support.patch new file mode 100644 index 0000000000000..ff58a13562801 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0020-pwm-starfive-Add-PWM-driver-support.patch @@ -0,0 +1,251 @@ +From 786982106a9e3ccb9037f39d8c8d45c762289187 Mon Sep 17 00:00:00 2001 +From: William Qiu +Date: Thu, 1 Jun 2023 16:51:52 +0800 +Subject: [PATCH 20/72] pwm: starfive: Add PWM driver support + +Add Pulse Width Modulation driver support for StarFive +JH7100 and JH7110 SoC. + +Co-developed-by: Hal Feng +Signed-off-by: Hal Feng +Signed-off-by: William Qiu +--- + drivers/pwm/Kconfig | 9 ++ + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-starfive-ptc.c | 192 +++++++++++++++++++++++++++++++++ + 3 files changed, 202 insertions(+) + create mode 100644 drivers/pwm/pwm-starfive-ptc.c + +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 8df861b1f4a3..df2bc4ce3f1f 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -548,6 +548,15 @@ config PWM_SPRD + To compile this driver as a module, choose M here: the module + will be called pwm-sprd. + ++config PWM_STARFIVE_PTC ++ tristate "StarFive PWM PTC support" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ help ++ Generic PWM framework driver for StarFive SoCs. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-starfive-ptc. ++ + config PWM_STI + tristate "STiH4xx PWM support" + depends on ARCH_STI || COMPILE_TEST +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index 19899b912e00..994104aaa9b4 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -50,6 +50,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o + obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o + obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o + obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o ++obj-$(CONFIG_PWM_STARFIVE_PTC) += pwm-starfive-ptc.o + obj-$(CONFIG_PWM_STI) += pwm-sti.o + obj-$(CONFIG_PWM_STM32) += pwm-stm32.o + obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o +diff --git a/drivers/pwm/pwm-starfive-ptc.c b/drivers/pwm/pwm-starfive-ptc.c +new file mode 100644 +index 000000000000..57b5736f6732 +--- /dev/null ++++ b/drivers/pwm/pwm-starfive-ptc.c +@@ -0,0 +1,192 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * PWM driver for the StarFive JH71x0 SoC ++ * ++ * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Access PTC register (CNTR, HRC, LRC and CTRL) */ ++#define REG_PTC_BASE_ADDR_SUB(base, N) \ ++((base) + (((N) > 3) ? (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10))) ++#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N)) ++#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4) ++#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8) ++#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC) ++ ++/* PTC_RPTC_CTRL register bits*/ ++#define PTC_EN BIT(0) ++#define PTC_ECLK BIT(1) ++#define PTC_NEC BIT(2) ++#define PTC_OE BIT(3) ++#define PTC_SIGNLE BIT(4) ++#define PTC_INTE BIT(5) ++#define PTC_INT BIT(6) ++#define PTC_CNTRRST BIT(7) ++#define PTC_CAPTE BIT(8) ++ ++struct starfive_pwm_ptc_device { ++ struct pwm_chip chip; ++ struct clk *clk; ++ struct reset_control *rst; ++ void __iomem *regs; ++ u32 clk_rate; /* PWM APB clock frequency */ ++}; ++ ++static inline ++struct starfive_pwm_ptc_device *chip_to_starfive_ptc(struct pwm_chip *c) ++{ ++ return container_of(c, struct starfive_pwm_ptc_device, chip); ++} ++ ++static int starfive_pwm_ptc_get_state(struct pwm_chip *chip, ++ struct pwm_device *dev, ++ struct pwm_state *state) ++{ ++ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); ++ u32 period_data, duty_data, ctrl_data; ++ ++ period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); ++ duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); ++ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); ++ ++ state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate); ++ state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate); ++ state->polarity = PWM_POLARITY_INVERSED; ++ state->enabled = (ctrl_data & PTC_EN) ? true : false; ++ ++ return 0; ++} ++ ++static int starfive_pwm_ptc_apply(struct pwm_chip *chip, ++ struct pwm_device *dev, ++ const struct pwm_state *state) ++{ ++ struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); ++ u32 period_data, duty_data, ctrl_data = 0; ++ ++ if (state->polarity != PWM_POLARITY_INVERSED) ++ return -EINVAL; ++ ++ period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, ++ NSEC_PER_SEC); ++ duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, ++ NSEC_PER_SEC); ++ ++ writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); ++ writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); ++ writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm)); ++ ++ ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); ++ if (state->enabled) ++ writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); ++ else ++ writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); ++ ++ return 0; ++} ++ ++static const struct pwm_ops starfive_pwm_ptc_ops = { ++ .get_state = starfive_pwm_ptc_get_state, ++ .apply = starfive_pwm_ptc_apply, ++ .owner = THIS_MODULE, ++}; ++ ++static int starfive_pwm_ptc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct starfive_pwm_ptc_device *pwm; ++ struct pwm_chip *chip; ++ int ret; ++ ++ pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); ++ if (!pwm) ++ return -ENOMEM; ++ ++ chip = &pwm->chip; ++ chip->dev = dev; ++ chip->ops = &starfive_pwm_ptc_ops; ++ chip->npwm = 8; ++ chip->of_pwm_n_cells = 3; ++ ++ pwm->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pwm->regs)) ++ return dev_err_probe(dev, PTR_ERR(pwm->regs), ++ "Unable to map IO resources\n"); ++ ++ pwm->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(pwm->clk)) ++ return dev_err_probe(dev, PTR_ERR(pwm->clk), ++ "Unable to get pwm's clock\n"); ++ ++ pwm->rst = devm_reset_control_get_exclusive(dev, NULL); ++ if (IS_ERR(pwm->rst)) ++ return dev_err_probe(dev, PTR_ERR(pwm->rst), ++ "Unable to get pwm's reset\n"); ++ ++ ret = clk_prepare_enable(pwm->clk); ++ if (ret) { ++ dev_err(dev, ++ "Failed to enable clock for pwm: %d\n", ret); ++ return ret; ++ } ++ ++ reset_control_deassert(pwm->rst); ++ ++ pwm->clk_rate = clk_get_rate(pwm->clk); ++ if (pwm->clk_rate <= 0) { ++ dev_warn(dev, "Failed to get APB clock rate\n"); ++ return -EINVAL; ++ } ++ ++ ret = devm_pwmchip_add(dev, chip); ++ if (ret < 0) { ++ dev_err(dev, "Cannot register PTC: %d\n", ret); ++ clk_disable_unprepare(pwm->clk); ++ reset_control_assert(pwm->rst); ++ return ret; ++ } ++ ++ platform_set_drvdata(pdev, pwm); ++ ++ return 0; ++} ++ ++static int starfive_pwm_ptc_remove(struct platform_device *dev) ++{ ++ struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev); ++ ++ reset_control_assert(pwm->rst); ++ clk_disable_unprepare(pwm->clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_pwm_ptc_of_match[] = { ++ { .compatible = "starfive,jh7100-pwm" }, ++ { .compatible = "starfive,jh7110-pwm" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match); ++ ++static struct platform_driver starfive_pwm_ptc_driver = { ++ .probe = starfive_pwm_ptc_probe, ++ .remove = starfive_pwm_ptc_remove, ++ .driver = { ++ .name = "pwm-starfive-ptc", ++ .of_match_table = starfive_pwm_ptc_of_match, ++ }, ++}; ++module_platform_driver(starfive_pwm_ptc_driver); ++ ++MODULE_AUTHOR("Jieqin Chen"); ++MODULE_AUTHOR("Hal Feng "); ++MODULE_DESCRIPTION("StarFive PWM PTC driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0021-crypto-hash-Add-statesize-to-crypto_ahash.patch b/srcpkgs/linux6.4/patches/0021-crypto-hash-Add-statesize-to-crypto_ahash.patch new file mode 100644 index 0000000000000..1f41cbea5c462 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0021-crypto-hash-Add-statesize-to-crypto_ahash.patch @@ -0,0 +1,78 @@ +From 949dbd1099fdf6ba3854983049ded49496f16ad1 Mon Sep 17 00:00:00 2001 +From: Herbert Xu +Date: Thu, 20 Apr 2023 18:05:16 +0800 +Subject: [PATCH 21/72] crypto: hash - Add statesize to crypto_ahash + +As ahash drivers may need to use fallbacks, their state size +is thus variable. Deal with this by making it an attribute +of crypto_ahash. + +Signed-off-by: Herbert Xu +--- + crypto/ahash.c | 3 +++ + include/crypto/hash.h | 3 ++- + include/crypto/internal/hash.h | 6 ++++++ + 3 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/crypto/ahash.c b/crypto/ahash.c +index 324651040446..99867382abaa 100644 +--- a/crypto/ahash.c ++++ b/crypto/ahash.c +@@ -432,6 +432,8 @@ static int crypto_ahash_init_tfm(struct crypto_tfm *tfm) + + hash->setkey = ahash_nosetkey; + ++ crypto_ahash_set_statesize(hash, alg->halg.statesize); ++ + if (tfm->__crt_alg->cra_type != &crypto_ahash_type) + return crypto_init_shash_ops_async(tfm); + +@@ -573,6 +575,7 @@ struct crypto_ahash *crypto_clone_ahash(struct crypto_ahash *hash) + nhash->import = hash->import; + nhash->setkey = hash->setkey; + nhash->reqsize = hash->reqsize; ++ nhash->statesize = hash->statesize; + + if (tfm->__crt_alg->cra_type != &crypto_ahash_type) + return crypto_clone_shash_ops_async(nhash, hash); +diff --git a/include/crypto/hash.h b/include/crypto/hash.h +index e69542d86a2b..f7c2a22cd776 100644 +--- a/include/crypto/hash.h ++++ b/include/crypto/hash.h +@@ -260,6 +260,7 @@ struct crypto_ahash { + int (*setkey)(struct crypto_ahash *tfm, const u8 *key, + unsigned int keylen); + ++ unsigned int statesize; + unsigned int reqsize; + struct crypto_tfm base; + }; +@@ -400,7 +401,7 @@ static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm) + */ + static inline unsigned int crypto_ahash_statesize(struct crypto_ahash *tfm) + { +- return crypto_hash_alg_common(tfm)->statesize; ++ return tfm->statesize; + } + + static inline u32 crypto_ahash_get_flags(struct crypto_ahash *tfm) +diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h +index 37edf3f4e8af..b925f82206ef 100644 +--- a/include/crypto/internal/hash.h ++++ b/include/crypto/internal/hash.h +@@ -149,6 +149,12 @@ static inline struct ahash_alg *__crypto_ahash_alg(struct crypto_alg *alg) + halg); + } + ++static inline void crypto_ahash_set_statesize(struct crypto_ahash *tfm, ++ unsigned int size) ++{ ++ tfm->statesize = size; ++} ++ + static inline void crypto_ahash_set_reqsize(struct crypto_ahash *tfm, + unsigned int reqsize) + { +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0022-dt-bindings-crypto-Add-StarFive-crypto-module.patch b/srcpkgs/linux6.4/patches/0022-dt-bindings-crypto-Add-StarFive-crypto-module.patch new file mode 100644 index 0000000000000..28c6a1769c0e9 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0022-dt-bindings-crypto-Add-StarFive-crypto-module.patch @@ -0,0 +1,96 @@ +From 241a3d69f2e713ad267d7d70f7496a797df8128e Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Mon, 15 May 2023 20:53:52 +0800 +Subject: [PATCH 22/72] dt-bindings: crypto: Add StarFive crypto module + +Add documentation to describe StarFive cryptographic engine. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +Reviewed-by: Rob Herring +Signed-off-by: Herbert Xu +--- + .../crypto/starfive,jh7110-crypto.yaml | 70 +++++++++++++++++++ + 1 file changed, 70 insertions(+) + create mode 100644 Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml + +diff --git a/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml +new file mode 100644 +index 000000000000..71a2876bd6e4 +--- /dev/null ++++ b/Documentation/devicetree/bindings/crypto/starfive,jh7110-crypto.yaml +@@ -0,0 +1,70 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive Cryptographic Module ++ ++maintainers: ++ - Jia Jie Ho ++ - William Qiu ++ ++properties: ++ compatible: ++ const: starfive,jh7110-crypto ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: Hardware reference clock ++ - description: AHB reference clock ++ ++ clock-names: ++ items: ++ - const: hclk ++ - const: ahb ++ ++ interrupts: ++ maxItems: 1 ++ ++ resets: ++ maxItems: 1 ++ ++ dmas: ++ items: ++ - description: TX DMA channel ++ - description: RX DMA channel ++ ++ dma-names: ++ items: ++ - const: tx ++ - const: rx ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - dmas ++ - dma-names ++ ++additionalProperties: false ++ ++examples: ++ - | ++ crypto: crypto@16000000 { ++ compatible = "starfive,jh7110-crypto"; ++ reg = <0x16000000 0x4000>; ++ clocks = <&clk 15>, <&clk 16>; ++ clock-names = "hclk", "ahb"; ++ interrupts = <28>; ++ resets = <&reset 3>; ++ dmas = <&dma 1 2>, ++ <&dma 0 2>; ++ dma-names = "tx", "rx"; ++ }; ++... +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0023-crypto-starfive-Add-crypto-engine-support.patch b/srcpkgs/linux6.4/patches/0023-crypto-starfive-Add-crypto-engine-support.patch new file mode 100644 index 0000000000000..7fd3ea5df36a1 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0023-crypto-starfive-Add-crypto-engine-support.patch @@ -0,0 +1,356 @@ +From fd3829d8b2cfa5c1652418aff2e619abbcaf7dbc Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Mon, 15 May 2023 20:53:53 +0800 +Subject: [PATCH 23/72] crypto: starfive - Add crypto engine support + +Adding device probe and DMA init for StarFive cryptographic module. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +Signed-off-by: Herbert Xu +--- + drivers/crypto/Kconfig | 1 + + drivers/crypto/Makefile | 1 + + drivers/crypto/starfive/Kconfig | 17 +++ + drivers/crypto/starfive/Makefile | 4 + + drivers/crypto/starfive/jh7110-cryp.c | 201 ++++++++++++++++++++++++++ + drivers/crypto/starfive/jh7110-cryp.h | 63 ++++++++ + 6 files changed, 287 insertions(+) + create mode 100644 drivers/crypto/starfive/Kconfig + create mode 100644 drivers/crypto/starfive/Makefile + create mode 100644 drivers/crypto/starfive/jh7110-cryp.c + create mode 100644 drivers/crypto/starfive/jh7110-cryp.h + +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index 9c440cd0fed0..9f5b2d28bff5 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -807,5 +807,6 @@ config CRYPTO_DEV_SA2UL + acceleration for cryptographic algorithms on these devices. + + source "drivers/crypto/aspeed/Kconfig" ++source "drivers/crypto/starfive/Kconfig" + + endif # CRYPTO_HW +diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile +index 51d36701e785..d859d6a5f3a4 100644 +--- a/drivers/crypto/Makefile ++++ b/drivers/crypto/Makefile +@@ -50,3 +50,4 @@ obj-y += xilinx/ + obj-y += hisilicon/ + obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/ + obj-y += intel/ ++obj-y += starfive/ +diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig +new file mode 100644 +index 000000000000..7a5a5d9f90ed +--- /dev/null ++++ b/drivers/crypto/starfive/Kconfig +@@ -0,0 +1,17 @@ ++# ++# StarFive crypto drivers configuration ++# ++ ++config CRYPTO_DEV_JH7110 ++ tristate "StarFive JH7110 cryptographic engine driver" ++ depends on SOC_STARFIVE || COMPILE_TEST ++ select CRYPTO_ENGINE ++ select ARM_AMBA ++ select DMADEVICES ++ select AMBA_PL08X ++ help ++ Support for StarFive JH7110 crypto hardware acceleration engine. ++ This module provides acceleration for public key algo, ++ skciphers, AEAD and hash functions. ++ ++ If you choose 'M' here, this module will be called jh7110-crypto. +diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Makefile +new file mode 100644 +index 000000000000..41221acaee39 +--- /dev/null ++++ b/drivers/crypto/starfive/Makefile +@@ -0,0 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++obj-$(CONFIG_CRYPTO_DEV_JH7110) += jh7110-crypto.o ++jh7110-crypto-objs := jh7110-cryp.o +diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c +new file mode 100644 +index 000000000000..4b2505c23168 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-cryp.c +@@ -0,0 +1,201 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Cryptographic API. ++ * ++ * Support for StarFive hardware cryptographic engine. ++ * Copyright (c) 2022 StarFive Technology ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "jh7110-cryp.h" ++ ++#define DRIVER_NAME "jh7110-crypto" ++ ++struct starfive_dev_list { ++ struct list_head dev_list; ++ spinlock_t lock; /* protect dev_list */ ++}; ++ ++static struct starfive_dev_list dev_list = { ++ .dev_list = LIST_HEAD_INIT(dev_list.dev_list), ++ .lock = __SPIN_LOCK_UNLOCKED(dev_list.lock), ++}; ++ ++struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = NULL, *tmp; ++ ++ spin_lock_bh(&dev_list.lock); ++ if (!ctx->cryp) { ++ list_for_each_entry(tmp, &dev_list.dev_list, list) { ++ cryp = tmp; ++ break; ++ } ++ ctx->cryp = cryp; ++ } else { ++ cryp = ctx->cryp; ++ } ++ ++ spin_unlock_bh(&dev_list.lock); ++ ++ return cryp; ++} ++ ++static int starfive_dma_init(struct starfive_cryp_dev *cryp) ++{ ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ dma_cap_set(DMA_SLAVE, mask); ++ ++ cryp->tx = dma_request_chan(cryp->dev, "tx"); ++ if (IS_ERR(cryp->tx)) ++ return dev_err_probe(cryp->dev, PTR_ERR(cryp->tx), ++ "Error requesting tx dma channel.\n"); ++ ++ cryp->rx = dma_request_chan(cryp->dev, "rx"); ++ if (IS_ERR(cryp->rx)) { ++ dma_release_channel(cryp->tx); ++ return dev_err_probe(cryp->dev, PTR_ERR(cryp->rx), ++ "Error requesting rx dma channel.\n"); ++ } ++ ++ return 0; ++} ++ ++static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) ++{ ++ dma_release_channel(cryp->tx); ++ dma_release_channel(cryp->rx); ++} ++ ++static int starfive_cryp_probe(struct platform_device *pdev) ++{ ++ struct starfive_cryp_dev *cryp; ++ struct resource *res; ++ int ret; ++ ++ cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); ++ if (!cryp) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, cryp); ++ cryp->dev = &pdev->dev; ++ ++ cryp->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(cryp->base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), ++ "Error remapping memory for platform device\n"); ++ ++ cryp->phys_base = res->start; ++ cryp->dma_maxburst = 32; ++ ++ cryp->hclk = devm_clk_get(&pdev->dev, "hclk"); ++ if (IS_ERR(cryp->hclk)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->hclk), ++ "Error getting hardware reference clock\n"); ++ ++ cryp->ahb = devm_clk_get(&pdev->dev, "ahb"); ++ if (IS_ERR(cryp->ahb)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb), ++ "Error getting ahb reference clock\n"); ++ ++ cryp->rst = devm_reset_control_get_shared(cryp->dev, NULL); ++ if (IS_ERR(cryp->rst)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), ++ "Error getting hardware reset line\n"); ++ ++ clk_prepare_enable(cryp->hclk); ++ clk_prepare_enable(cryp->ahb); ++ reset_control_deassert(cryp->rst); ++ ++ spin_lock(&dev_list.lock); ++ list_add(&cryp->list, &dev_list.dev_list); ++ spin_unlock(&dev_list.lock); ++ ++ ret = starfive_dma_init(cryp); ++ if (ret) { ++ if (ret == -EPROBE_DEFER) ++ goto err_probe_defer; ++ else ++ goto err_dma_init; ++ } ++ ++ /* Initialize crypto engine */ ++ cryp->engine = crypto_engine_alloc_init(&pdev->dev, 1); ++ if (!cryp->engine) { ++ ret = -ENOMEM; ++ goto err_engine; ++ } ++ ++ ret = crypto_engine_start(cryp->engine); ++ if (ret) ++ goto err_engine_start; ++ ++ return 0; ++ ++err_engine_start: ++ crypto_engine_exit(cryp->engine); ++err_engine: ++ starfive_dma_cleanup(cryp); ++err_dma_init: ++ spin_lock(&dev_list.lock); ++ list_del(&cryp->list); ++ spin_unlock(&dev_list.lock); ++ ++ clk_disable_unprepare(cryp->hclk); ++ clk_disable_unprepare(cryp->ahb); ++ reset_control_assert(cryp->rst); ++err_probe_defer: ++ return ret; ++} ++ ++static int starfive_cryp_remove(struct platform_device *pdev) ++{ ++ struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev); ++ ++ crypto_engine_stop(cryp->engine); ++ crypto_engine_exit(cryp->engine); ++ ++ starfive_dma_cleanup(cryp); ++ ++ spin_lock(&dev_list.lock); ++ list_del(&cryp->list); ++ spin_unlock(&dev_list.lock); ++ ++ clk_disable_unprepare(cryp->hclk); ++ clk_disable_unprepare(cryp->ahb); ++ reset_control_assert(cryp->rst); ++ ++ return 0; ++} ++ ++static const struct of_device_id starfive_dt_ids[] __maybe_unused = { ++ { .compatible = "starfive,jh7110-crypto", .data = NULL}, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, starfive_dt_ids); ++ ++static struct platform_driver starfive_cryp_driver = { ++ .probe = starfive_cryp_probe, ++ .remove = starfive_cryp_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .of_match_table = starfive_dt_ids, ++ }, ++}; ++ ++module_platform_driver(starfive_cryp_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("StarFive JH7110 Cryptographic Module"); +diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfive/jh7110-cryp.h +new file mode 100644 +index 000000000000..393efd38b098 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-cryp.h +@@ -0,0 +1,63 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef __STARFIVE_STR_H__ ++#define __STARFIVE_STR_H__ ++ ++#include ++#include ++#include ++ ++#include ++ ++#define STARFIVE_ALG_CR_OFFSET 0x0 ++#define STARFIVE_ALG_FIFO_OFFSET 0x4 ++#define STARFIVE_IE_MASK_OFFSET 0x8 ++#define STARFIVE_IE_FLAG_OFFSET 0xc ++#define STARFIVE_DMA_IN_LEN_OFFSET 0x10 ++#define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 ++ ++#define STARFIVE_MSG_BUFFER_SIZE SZ_16K ++ ++union starfive_alg_cr { ++ u32 v; ++ struct { ++ u32 start :1; ++ u32 aes_dma_en :1; ++ u32 rsvd_0 :1; ++ u32 hash_dma_en :1; ++ u32 alg_done :1; ++ u32 rsvd_1 :3; ++ u32 clear :1; ++ u32 rsvd_2 :23; ++ }; ++}; ++ ++struct starfive_cryp_ctx { ++ struct crypto_engine_ctx enginectx; ++ struct starfive_cryp_dev *cryp; ++}; ++ ++struct starfive_cryp_dev { ++ struct list_head list; ++ struct device *dev; ++ ++ struct clk *hclk; ++ struct clk *ahb; ++ struct reset_control *rst; ++ ++ void __iomem *base; ++ phys_addr_t phys_base; ++ ++ u32 dma_maxburst; ++ struct dma_chan *tx; ++ struct dma_chan *rx; ++ struct dma_slave_config cfg_in; ++ struct dma_slave_config cfg_out; ++ ++ struct crypto_engine *engine; ++ ++ union starfive_alg_cr alg_cr; ++}; ++ ++struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx); ++ ++#endif +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0024-crypto-starfive-Add-hash-and-HMAC-support.patch b/srcpkgs/linux6.4/patches/0024-crypto-starfive-Add-hash-and-HMAC-support.patch new file mode 100644 index 0000000000000..02fd6ef745c87 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0024-crypto-starfive-Add-hash-and-HMAC-support.patch @@ -0,0 +1,1150 @@ +From 280cb438c90b4937d5d845dbd0532a172aea2905 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Mon, 15 May 2023 20:53:55 +0800 +Subject: [PATCH 24/72] crypto: starfive - Add hash and HMAC support + +Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic +module. + +Co-developed-by: Huan Feng +Signed-off-by: Huan Feng +Signed-off-by: Jia Jie Ho +Signed-off-by: Herbert Xu +--- + drivers/crypto/starfive/Kconfig | 4 + + drivers/crypto/starfive/Makefile | 2 +- + drivers/crypto/starfive/jh7110-cryp.c | 39 ++ + drivers/crypto/starfive/jh7110-cryp.h | 70 +- + drivers/crypto/starfive/jh7110-hash.c | 892 ++++++++++++++++++++++++++ + 5 files changed, 1003 insertions(+), 4 deletions(-) + create mode 100644 drivers/crypto/starfive/jh7110-hash.c + +diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig +index 7a5a5d9f90ed..be58d1473523 100644 +--- a/drivers/crypto/starfive/Kconfig ++++ b/drivers/crypto/starfive/Kconfig +@@ -6,6 +6,10 @@ config CRYPTO_DEV_JH7110 + tristate "StarFive JH7110 cryptographic engine driver" + depends on SOC_STARFIVE || COMPILE_TEST + select CRYPTO_ENGINE ++ select CRYPTO_HMAC ++ select CRYPTO_SHA256 ++ select CRYPTO_SHA512 ++ select CRYPTO_SM3_GENERIC + select ARM_AMBA + select DMADEVICES + select AMBA_PL08X +diff --git a/drivers/crypto/starfive/Makefile b/drivers/crypto/starfive/Makefile +index 41221acaee39..2af49062e36d 100644 +--- a/drivers/crypto/starfive/Makefile ++++ b/drivers/crypto/starfive/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + + obj-$(CONFIG_CRYPTO_DEV_JH7110) += jh7110-crypto.o +-jh7110-crypto-objs := jh7110-cryp.o ++jh7110-crypto-objs := jh7110-cryp.o jh7110-hash.o +diff --git a/drivers/crypto/starfive/jh7110-cryp.c b/drivers/crypto/starfive/jh7110-cryp.c +index 4b2505c23168..279b19f51cb4 100644 +--- a/drivers/crypto/starfive/jh7110-cryp.c ++++ b/drivers/crypto/starfive/jh7110-cryp.c +@@ -79,10 +79,25 @@ static void starfive_dma_cleanup(struct starfive_cryp_dev *cryp) + dma_release_channel(cryp->rx); + } + ++static irqreturn_t starfive_cryp_irq(int irq, void *priv) ++{ ++ u32 status; ++ struct starfive_cryp_dev *cryp = (struct starfive_cryp_dev *)priv; ++ ++ status = readl(cryp->base + STARFIVE_IE_FLAG_OFFSET); ++ if (status & STARFIVE_IE_FLAG_HASH_DONE) { ++ writel(STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); ++ tasklet_schedule(&cryp->hash_done); ++ } ++ ++ return IRQ_HANDLED; ++} ++ + static int starfive_cryp_probe(struct platform_device *pdev) + { + struct starfive_cryp_dev *cryp; + struct resource *res; ++ int irq; + int ret; + + cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL); +@@ -97,6 +112,8 @@ static int starfive_cryp_probe(struct platform_device *pdev) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->base), + "Error remapping memory for platform device\n"); + ++ tasklet_init(&cryp->hash_done, starfive_hash_done_task, (unsigned long)cryp); ++ + cryp->phys_base = res->start; + cryp->dma_maxburst = 32; + +@@ -115,6 +132,16 @@ static int starfive_cryp_probe(struct platform_device *pdev) + return dev_err_probe(&pdev->dev, PTR_ERR(cryp->rst), + "Error getting hardware reset line\n"); + ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) ++ return irq; ++ ++ ret = devm_request_irq(&pdev->dev, irq, starfive_cryp_irq, 0, pdev->name, ++ (void *)cryp); ++ if (ret) ++ return dev_err_probe(&pdev->dev, irq, ++ "Failed to register interrupt handler\n"); ++ + clk_prepare_enable(cryp->hclk); + clk_prepare_enable(cryp->ahb); + reset_control_deassert(cryp->rst); +@@ -142,8 +169,14 @@ static int starfive_cryp_probe(struct platform_device *pdev) + if (ret) + goto err_engine_start; + ++ ret = starfive_hash_register_algs(); ++ if (ret) ++ goto err_algs_hash; ++ + return 0; + ++err_algs_hash: ++ crypto_engine_stop(cryp->engine); + err_engine_start: + crypto_engine_exit(cryp->engine); + err_engine: +@@ -156,6 +189,8 @@ static int starfive_cryp_probe(struct platform_device *pdev) + clk_disable_unprepare(cryp->hclk); + clk_disable_unprepare(cryp->ahb); + reset_control_assert(cryp->rst); ++ ++ tasklet_kill(&cryp->hash_done); + err_probe_defer: + return ret; + } +@@ -164,6 +199,10 @@ static int starfive_cryp_remove(struct platform_device *pdev) + { + struct starfive_cryp_dev *cryp = platform_get_drvdata(pdev); + ++ starfive_hash_unregister_algs(); ++ ++ tasklet_kill(&cryp->hash_done); ++ + crypto_engine_stop(cryp->engine); + crypto_engine_exit(cryp->engine); + +diff --git a/drivers/crypto/starfive/jh7110-cryp.h b/drivers/crypto/starfive/jh7110-cryp.h +index 393efd38b098..021d6e24bc86 100644 +--- a/drivers/crypto/starfive/jh7110-cryp.h ++++ b/drivers/crypto/starfive/jh7110-cryp.h +@@ -7,6 +7,8 @@ + #include + + #include ++#include ++#include + + #define STARFIVE_ALG_CR_OFFSET 0x0 + #define STARFIVE_ALG_FIFO_OFFSET 0x4 +@@ -15,7 +17,43 @@ + #define STARFIVE_DMA_IN_LEN_OFFSET 0x10 + #define STARFIVE_DMA_OUT_LEN_OFFSET 0x14 + ++#define STARFIVE_IE_MASK_HASH_DONE 0x4 ++#define STARFIVE_IE_FLAG_HASH_DONE 0x4 ++ + #define STARFIVE_MSG_BUFFER_SIZE SZ_16K ++#define MAX_KEY_SIZE SHA512_BLOCK_SIZE ++ ++union starfive_hash_csr { ++ u32 v; ++ struct { ++ u32 start :1; ++ u32 reset :1; ++ u32 ie :1; ++ u32 firstb :1; ++#define STARFIVE_HASH_SM3 0x0 ++#define STARFIVE_HASH_SHA224 0x3 ++#define STARFIVE_HASH_SHA256 0x4 ++#define STARFIVE_HASH_SHA384 0x5 ++#define STARFIVE_HASH_SHA512 0x6 ++#define STARFIVE_HASH_MODE_MASK 0x7 ++ u32 mode :3; ++ u32 rsvd_1 :1; ++ u32 final :1; ++ u32 rsvd_2 :2; ++#define STARFIVE_HASH_HMAC_FLAGS 0x800 ++ u32 hmac :1; ++ u32 rsvd_3 :1; ++#define STARFIVE_HASH_KEY_DONE BIT(13) ++ u32 key_done :1; ++ u32 key_flag :1; ++ u32 hmac_done :1; ++#define STARFIVE_HASH_BUSY BIT(16) ++ u32 busy :1; ++ u32 hashdone :1; ++ u32 rsvd_4 :14; ++ }; ++}; ++ + + union starfive_alg_cr { + u32 v; +@@ -34,12 +72,18 @@ union starfive_alg_cr { + struct starfive_cryp_ctx { + struct crypto_engine_ctx enginectx; + struct starfive_cryp_dev *cryp; ++ struct starfive_cryp_request_ctx *rctx; ++ ++ unsigned int hash_mode; ++ u8 key[MAX_KEY_SIZE]; ++ int keylen; ++ bool is_hmac; ++ struct crypto_ahash *ahash_fbk; + }; + + struct starfive_cryp_dev { + struct list_head list; + struct device *dev; +- + struct clk *hclk; + struct clk *ahb; + struct reset_control *rst; +@@ -52,12 +96,32 @@ struct starfive_cryp_dev { + struct dma_chan *rx; + struct dma_slave_config cfg_in; + struct dma_slave_config cfg_out; +- + struct crypto_engine *engine; +- ++ struct tasklet_struct hash_done; ++ int err; + union starfive_alg_cr alg_cr; ++ union { ++ struct ahash_request *hreq; ++ } req; ++}; ++ ++struct starfive_cryp_request_ctx { ++ union { ++ union starfive_hash_csr hash; ++ } csr; ++ ++ struct scatterlist *in_sg; ++ struct ahash_request ahash_fbk_req; ++ size_t total; ++ unsigned int blksize; ++ unsigned int digsize; ++ unsigned long in_sg_len; + }; + + struct starfive_cryp_dev *starfive_cryp_find_dev(struct starfive_cryp_ctx *ctx); + ++int starfive_hash_register_algs(void); ++void starfive_hash_unregister_algs(void); ++ ++void starfive_hash_done_task(unsigned long param); + #endif +diff --git a/drivers/crypto/starfive/jh7110-hash.c b/drivers/crypto/starfive/jh7110-hash.c +new file mode 100644 +index 000000000000..3801e44f2f33 +--- /dev/null ++++ b/drivers/crypto/starfive/jh7110-hash.c +@@ -0,0 +1,892 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Hash function and HMAC support for StarFive driver ++ * ++ * Copyright (c) 2022 StarFive Technology ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "jh7110-cryp.h" ++ ++#define STARFIVE_HASH_REGS_OFFSET 0x300 ++#define STARFIVE_HASH_SHACSR (STARFIVE_HASH_REGS_OFFSET + 0x0) ++#define STARFIVE_HASH_SHAWDR (STARFIVE_HASH_REGS_OFFSET + 0x4) ++#define STARFIVE_HASH_SHARDR (STARFIVE_HASH_REGS_OFFSET + 0x8) ++#define STARFIVE_HASH_SHAWSR (STARFIVE_HASH_REGS_OFFSET + 0xC) ++#define STARFIVE_HASH_SHAWLEN3 (STARFIVE_HASH_REGS_OFFSET + 0x10) ++#define STARFIVE_HASH_SHAWLEN2 (STARFIVE_HASH_REGS_OFFSET + 0x14) ++#define STARFIVE_HASH_SHAWLEN1 (STARFIVE_HASH_REGS_OFFSET + 0x18) ++#define STARFIVE_HASH_SHAWLEN0 (STARFIVE_HASH_REGS_OFFSET + 0x1C) ++#define STARFIVE_HASH_SHAWKR (STARFIVE_HASH_REGS_OFFSET + 0x20) ++#define STARFIVE_HASH_SHAWKLEN (STARFIVE_HASH_REGS_OFFSET + 0x24) ++ ++#define STARFIVE_HASH_BUFLEN SHA512_BLOCK_SIZE ++ ++static inline int starfive_hash_wait_busy(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ u32 status; ++ ++ return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, ++ !(status & STARFIVE_HASH_BUSY), 10, 100000); ++} ++ ++static inline int starfive_hash_wait_key_done(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ u32 status; ++ ++ return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, ++ (status & STARFIVE_HASH_KEY_DONE), 10, 100000); ++} ++ ++static int starfive_hash_hmac_key(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ int klen = ctx->keylen, loop; ++ unsigned int *key = (unsigned int *)ctx->key; ++ unsigned char *cl; ++ ++ writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN); ++ ++ rctx->csr.hash.hmac = 1; ++ rctx->csr.hash.key_flag = 1; ++ ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ ++ for (loop = 0; loop < klen / sizeof(unsigned int); loop++, key++) ++ writel(*key, cryp->base + STARFIVE_HASH_SHAWKR); ++ ++ if (klen & 0x3) { ++ cl = (unsigned char *)key; ++ for (loop = 0; loop < (klen & 0x3); loop++, cl++) ++ writeb(*cl, cryp->base + STARFIVE_HASH_SHAWKR); ++ } ++ ++ if (starfive_hash_wait_key_done(ctx)) ++ return dev_err_probe(cryp->dev, -ETIMEDOUT, "starfive_hash_wait_key_done error\n"); ++ ++ return 0; ++} ++ ++static void starfive_hash_start(void *param) ++{ ++ struct starfive_cryp_ctx *ctx = param; ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ union starfive_alg_cr alg_cr; ++ union starfive_hash_csr csr; ++ ++ dma_unmap_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE); ++ ++ alg_cr.v = 0; ++ alg_cr.clear = 1; ++ ++ writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); ++ ++ csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR); ++ csr.firstb = 0; ++ csr.final = 1; ++ ++ writel(~STARFIVE_IE_MASK_HASH_DONE, cryp->base + STARFIVE_IE_MASK_OFFSET); ++ writel(csr.v, cryp->base + STARFIVE_HASH_SHACSR); ++} ++ ++static int starfive_hash_xmit_dma(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ struct dma_async_tx_descriptor *in_desc; ++ union starfive_alg_cr alg_cr; ++ int total_len; ++ int ret; ++ ++ if (!rctx->total) { ++ starfive_hash_start(ctx); ++ return 0; ++ } ++ ++ writel(rctx->total, cryp->base + STARFIVE_DMA_IN_LEN_OFFSET); ++ ++ total_len = rctx->total; ++ total_len = (total_len & 0x3) ? (((total_len >> 2) + 1) << 2) : total_len; ++ sg_dma_len(rctx->in_sg) = total_len; ++ ++ alg_cr.v = 0; ++ alg_cr.start = 1; ++ alg_cr.hash_dma_en = 1; ++ ++ writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); ++ ++ ret = dma_map_sg(cryp->dev, rctx->in_sg, rctx->in_sg_len, DMA_TO_DEVICE); ++ if (!ret) ++ return dev_err_probe(cryp->dev, -EINVAL, "dma_map_sg() error\n"); ++ ++ cryp->cfg_in.direction = DMA_MEM_TO_DEV; ++ cryp->cfg_in.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cryp->cfg_in.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cryp->cfg_in.src_maxburst = cryp->dma_maxburst; ++ cryp->cfg_in.dst_maxburst = cryp->dma_maxburst; ++ cryp->cfg_in.dst_addr = cryp->phys_base + STARFIVE_ALG_FIFO_OFFSET; ++ ++ dmaengine_slave_config(cryp->tx, &cryp->cfg_in); ++ ++ in_desc = dmaengine_prep_slave_sg(cryp->tx, rctx->in_sg, ++ ret, DMA_MEM_TO_DEV, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ ++ if (!in_desc) ++ return -EINVAL; ++ ++ in_desc->callback = starfive_hash_start; ++ in_desc->callback_param = ctx; ++ ++ dmaengine_submit(in_desc); ++ dma_async_issue_pending(cryp->tx); ++ ++ return 0; ++} ++ ++static int starfive_hash_xmit(struct starfive_cryp_ctx *ctx) ++{ ++ struct starfive_cryp_request_ctx *rctx = ctx->rctx; ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ int ret = 0; ++ ++ rctx->csr.hash.v = 0; ++ rctx->csr.hash.reset = 1; ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ ++ if (starfive_hash_wait_busy(ctx)) ++ return dev_err_probe(cryp->dev, -ETIMEDOUT, "Error resetting engine.\n"); ++ ++ rctx->csr.hash.v = 0; ++ rctx->csr.hash.mode = ctx->hash_mode; ++ rctx->csr.hash.ie = 1; ++ ++ if (ctx->is_hmac) { ++ ret = starfive_hash_hmac_key(ctx); ++ if (ret) ++ return ret; ++ } else { ++ rctx->csr.hash.start = 1; ++ rctx->csr.hash.firstb = 1; ++ writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); ++ } ++ ++ return starfive_hash_xmit_dma(ctx); ++} ++ ++static int starfive_hash_copy_hash(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); ++ int count, *data; ++ int mlen; ++ ++ if (!req->result) ++ return 0; ++ ++ mlen = rctx->digsize / sizeof(u32); ++ data = (u32 *)req->result; ++ ++ for (count = 0; count < mlen; count++) ++ data[count] = readl(ctx->cryp->base + STARFIVE_HASH_SHARDR); ++ ++ return 0; ++} ++ ++void starfive_hash_done_task(unsigned long param) ++{ ++ struct starfive_cryp_dev *cryp = (struct starfive_cryp_dev *)param; ++ int err = cryp->err; ++ ++ if (!err) ++ err = starfive_hash_copy_hash(cryp->req.hreq); ++ ++ crypto_finalize_hash_request(cryp->engine, cryp->req.hreq, err); ++} ++ ++static int starfive_hash_check_aligned(struct scatterlist *sg, size_t total, size_t align) ++{ ++ int len = 0; ++ ++ if (!total) ++ return 0; ++ ++ if (!IS_ALIGNED(total, align)) ++ return -EINVAL; ++ ++ while (sg) { ++ if (!IS_ALIGNED(sg->offset, sizeof(u32))) ++ return -EINVAL; ++ ++ if (!IS_ALIGNED(sg->length, align)) ++ return -EINVAL; ++ ++ len += sg->length; ++ sg = sg_next(sg); ++ } ++ ++ if (len != total) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int starfive_hash_one_request(struct crypto_engine *engine, void *areq) ++{ ++ struct ahash_request *req = container_of(areq, struct ahash_request, ++ base); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ ++ if (!cryp) ++ return -ENODEV; ++ ++ return starfive_hash_xmit(ctx); ++} ++ ++static int starfive_hash_init(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_init(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_update(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_update(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_final(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_final(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_finup(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_finup(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_digest_fb(struct ahash_request *req) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, req->base.flags, ++ req->base.complete, req->base.data); ++ ++ ahash_request_set_crypt(&rctx->ahash_fbk_req, req->src, ++ req->result, req->nbytes); ++ ++ return crypto_ahash_digest(&rctx->ahash_fbk_req); ++} ++ ++static int starfive_hash_digest(struct ahash_request *req) ++{ ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct starfive_cryp_dev *cryp = ctx->cryp; ++ ++ memset(rctx, 0, sizeof(struct starfive_cryp_request_ctx)); ++ ++ cryp->req.hreq = req; ++ rctx->total = req->nbytes; ++ rctx->in_sg = req->src; ++ rctx->blksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm)); ++ rctx->digsize = crypto_ahash_digestsize(tfm); ++ rctx->in_sg_len = sg_nents_for_len(rctx->in_sg, rctx->total); ++ ctx->rctx = rctx; ++ ++ if (starfive_hash_check_aligned(rctx->in_sg, rctx->total, rctx->blksize)) ++ return starfive_hash_digest_fb(req); ++ ++ return crypto_transfer_hash_request_to_engine(cryp->engine, req); ++} ++ ++static int starfive_hash_export(struct ahash_request *req, void *out) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ return crypto_ahash_export(&rctx->ahash_fbk_req, out); ++} ++ ++static int starfive_hash_import(struct ahash_request *req, const void *in) ++{ ++ struct starfive_cryp_request_ctx *rctx = ahash_request_ctx(req); ++ struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(tfm); ++ ++ ahash_request_set_tfm(&rctx->ahash_fbk_req, ctx->ahash_fbk); ++ ahash_request_set_callback(&rctx->ahash_fbk_req, ++ req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP, ++ req->base.complete, req->base.data); ++ ++ return crypto_ahash_import(&rctx->ahash_fbk_req, in); ++} ++ ++static int starfive_hash_init_tfm(struct crypto_ahash *hash, ++ const char *alg_name, ++ unsigned int mode) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->cryp = starfive_cryp_find_dev(ctx); ++ ++ if (!ctx->cryp) ++ return -ENODEV; ++ ++ ctx->ahash_fbk = crypto_alloc_ahash(alg_name, 0, ++ CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(ctx->ahash_fbk)) ++ return dev_err_probe(ctx->cryp->dev, PTR_ERR(ctx->ahash_fbk), ++ "starfive_hash: Could not load fallback driver.\n"); ++ ++ crypto_ahash_set_statesize(hash, crypto_ahash_statesize(ctx->ahash_fbk)); ++ crypto_ahash_set_reqsize(hash, sizeof(struct starfive_cryp_request_ctx) + ++ crypto_ahash_reqsize(ctx->ahash_fbk)); ++ ++ ctx->keylen = 0; ++ ctx->hash_mode = mode; ++ ++ ctx->enginectx.op.do_one_request = starfive_hash_one_request; ++ ctx->enginectx.op.prepare_request = NULL; ++ ctx->enginectx.op.unprepare_request = NULL; ++ ++ return 0; ++} ++ ++static void starfive_hash_exit_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ crypto_free_ahash(ctx->ahash_fbk); ++ ++ ctx->ahash_fbk = NULL; ++ ctx->enginectx.op.do_one_request = NULL; ++ ctx->enginectx.op.prepare_request = NULL; ++ ctx->enginectx.op.unprepare_request = NULL; ++} ++ ++static int starfive_hash_long_setkey(struct starfive_cryp_ctx *ctx, ++ const u8 *key, unsigned int keylen, ++ const char *alg_name) ++{ ++ struct crypto_wait wait; ++ struct ahash_request *req; ++ struct scatterlist sg; ++ struct crypto_ahash *ahash_tfm; ++ u8 *buf; ++ int ret; ++ ++ ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0); ++ if (IS_ERR(ahash_tfm)) ++ return PTR_ERR(ahash_tfm); ++ ++ req = ahash_request_alloc(ahash_tfm, GFP_KERNEL); ++ if (!req) { ++ ret = -ENOMEM; ++ goto err_free_ahash; ++ } ++ ++ crypto_init_wait(&wait); ++ ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, ++ crypto_req_done, &wait); ++ crypto_ahash_clear_flags(ahash_tfm, ~0); ++ ++ buf = kzalloc(keylen + STARFIVE_HASH_BUFLEN, GFP_KERNEL); ++ if (!buf) { ++ ret = -ENOMEM; ++ goto err_free_req; ++ } ++ ++ memcpy(buf, key, keylen); ++ sg_init_one(&sg, buf, keylen); ++ ahash_request_set_crypt(req, &sg, ctx->key, keylen); ++ ++ ret = crypto_wait_req(crypto_ahash_digest(req), &wait); ++ ++ kfree(buf); ++err_free_req: ++ ahash_request_free(req); ++err_free_ahash: ++ crypto_free_ahash(ahash_tfm); ++ return ret; ++} ++ ++static int starfive_hash_setkey(struct crypto_ahash *hash, ++ const u8 *key, unsigned int keylen) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ unsigned int digestsize = crypto_ahash_digestsize(hash); ++ unsigned int blocksize = crypto_ahash_blocksize(hash); ++ const char *alg_name; ++ ++ crypto_ahash_setkey(ctx->ahash_fbk, key, keylen); ++ ++ if (keylen <= blocksize) { ++ memcpy(ctx->key, key, keylen); ++ ctx->keylen = keylen; ++ return 0; ++ } ++ ++ ctx->keylen = digestsize; ++ ++ switch (digestsize) { ++ case SHA224_DIGEST_SIZE: ++ alg_name = "sha224-starfive"; ++ break; ++ case SHA256_DIGEST_SIZE: ++ if (ctx->hash_mode == STARFIVE_HASH_SM3) ++ alg_name = "sm3-starfive"; ++ else ++ alg_name = "sha256-starfive"; ++ break; ++ case SHA384_DIGEST_SIZE: ++ alg_name = "sha384-starfive"; ++ break; ++ case SHA512_DIGEST_SIZE: ++ alg_name = "sha512-starfive"; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return starfive_hash_long_setkey(ctx, key, keylen, alg_name); ++} ++ ++static int starfive_sha224_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha224-generic", ++ STARFIVE_HASH_SHA224); ++} ++ ++static int starfive_sha256_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha256-generic", ++ STARFIVE_HASH_SHA256); ++} ++ ++static int starfive_sha384_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha384-generic", ++ STARFIVE_HASH_SHA384); ++} ++ ++static int starfive_sha512_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sha512-generic", ++ STARFIVE_HASH_SHA512); ++} ++ ++static int starfive_sm3_init_tfm(struct crypto_ahash *hash) ++{ ++ return starfive_hash_init_tfm(hash, "sm3-generic", ++ STARFIVE_HASH_SM3); ++} ++ ++static int starfive_hmac_sha224_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha224-generic)", ++ STARFIVE_HASH_SHA224); ++} ++ ++static int starfive_hmac_sha256_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha256-generic)", ++ STARFIVE_HASH_SHA256); ++} ++ ++static int starfive_hmac_sha384_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha384-generic)", ++ STARFIVE_HASH_SHA384); ++} ++ ++static int starfive_hmac_sha512_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sha512-generic)", ++ STARFIVE_HASH_SHA512); ++} ++ ++static int starfive_hmac_sm3_init_tfm(struct crypto_ahash *hash) ++{ ++ struct starfive_cryp_ctx *ctx = crypto_ahash_ctx(hash); ++ ++ ctx->is_hmac = true; ++ ++ return starfive_hash_init_tfm(hash, "hmac(sm3-generic)", ++ STARFIVE_HASH_SM3); ++} ++ ++static struct ahash_alg algs_sha2_sm3[] = { ++{ ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha224_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA224_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha224", ++ .cra_driver_name = "sha224-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA224_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha224_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA224_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "hmac(sha224)", ++ .cra_driver_name = "sha224-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA224_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha256_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "sha256-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha256_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "hmac(sha256)", ++ .cra_driver_name = "sha256-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha384_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha384", ++ .cra_driver_name = "sha384-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha384_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA384_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "hmac(sha384)", ++ .cra_driver_name = "sha384-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA384_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sha512_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "sha512", ++ .cra_driver_name = "sha512-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sha512_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SHA512_DIGEST_SIZE, ++ .statesize = sizeof(struct sha512_state), ++ .base = { ++ .cra_name = "hmac(sha512)", ++ .cra_driver_name = "sha512-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA512_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_sm3_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "sm3", ++ .cra_driver_name = "sm3-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, { ++ .init = starfive_hash_init, ++ .update = starfive_hash_update, ++ .final = starfive_hash_final, ++ .finup = starfive_hash_finup, ++ .digest = starfive_hash_digest, ++ .export = starfive_hash_export, ++ .import = starfive_hash_import, ++ .init_tfm = starfive_hmac_sm3_init_tfm, ++ .exit_tfm = starfive_hash_exit_tfm, ++ .setkey = starfive_hash_setkey, ++ .halg = { ++ .digestsize = SM3_DIGEST_SIZE, ++ .statesize = sizeof(struct sm3_state), ++ .base = { ++ .cra_name = "hmac(sm3)", ++ .cra_driver_name = "sm3-hmac-starfive", ++ .cra_priority = 200, ++ .cra_flags = CRYPTO_ALG_ASYNC | ++ CRYPTO_ALG_TYPE_AHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SM3_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct starfive_cryp_ctx), ++ .cra_alignmask = 3, ++ .cra_module = THIS_MODULE, ++ } ++ } ++}, ++}; ++ ++int starfive_hash_register_algs(void) ++{ ++ return crypto_register_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); ++} ++ ++void starfive_hash_unregister_algs(void) ++{ ++ crypto_unregister_ahashes(algs_sha2_sm3, ARRAY_SIZE(algs_sha2_sm3)); ++} +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0025-crypto-starfive-Fix-driver-dependencies.patch b/srcpkgs/linux6.4/patches/0025-crypto-starfive-Fix-driver-dependencies.patch new file mode 100644 index 0000000000000..d820c9858532b --- /dev/null +++ b/srcpkgs/linux6.4/patches/0025-crypto-starfive-Fix-driver-dependencies.patch @@ -0,0 +1,38 @@ +From c0eb35b2f3c5c07f392d9281de3ae28af9a83174 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Fri, 19 May 2023 21:42:33 +0800 +Subject: [PATCH 25/72] crypto: starfive - Fix driver dependencies + +Kconfig updated to depend on DMADEVICES instead of selecting it. + +Reported-by: kernel test robot +Link: https://lore.kernel.org/oe-kbuild-all/202305191929.Eq4OVZ6D-lkp@intel.com/ +Signed-off-by: Jia Jie Ho +Signed-off-by: Herbert Xu +--- + drivers/crypto/starfive/Kconfig | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/starfive/Kconfig b/drivers/crypto/starfive/Kconfig +index be58d1473523..908c162ba79a 100644 +--- a/drivers/crypto/starfive/Kconfig ++++ b/drivers/crypto/starfive/Kconfig +@@ -4,14 +4,13 @@ + + config CRYPTO_DEV_JH7110 + tristate "StarFive JH7110 cryptographic engine driver" +- depends on SOC_STARFIVE || COMPILE_TEST ++ depends on (SOC_STARFIVE || COMPILE_TEST) && DMADEVICES + select CRYPTO_ENGINE + select CRYPTO_HMAC + select CRYPTO_SHA256 + select CRYPTO_SHA512 + select CRYPTO_SM3_GENERIC + select ARM_AMBA +- select DMADEVICES + select AMBA_PL08X + help + Support for StarFive JH7110 crypto hardware acceleration engine. +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0026-riscv-Kconfig-Add-select-ARM_AMBA-to-SOC_STARFIVE.patch b/srcpkgs/linux6.4/patches/0026-riscv-Kconfig-Add-select-ARM_AMBA-to-SOC_STARFIVE.patch new file mode 100644 index 0000000000000..db319ca8e793f --- /dev/null +++ b/srcpkgs/linux6.4/patches/0026-riscv-Kconfig-Add-select-ARM_AMBA-to-SOC_STARFIVE.patch @@ -0,0 +1,28 @@ +From d5f4827212c915e3d93ae3ee9b66776035ecc8a4 Mon Sep 17 00:00:00 2001 +From: Jia Jie Ho +Date: Thu, 25 May 2023 14:18:36 +0800 +Subject: [PATCH 26/72] riscv: Kconfig: Add select ARM_AMBA to SOC_STARFIVE + +Selects ARM_AMBA platform support for StarFive SoCs required by spi and +crypto dma engine. + +Signed-off-by: Jia Jie Ho +--- + arch/riscv/Kconfig.socs | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs +index 1cf69f958f10..381cd46e6373 100644 +--- a/arch/riscv/Kconfig.socs ++++ b/arch/riscv/Kconfig.socs +@@ -29,6 +29,7 @@ config SOC_STARFIVE + bool "StarFive SoCs" + select PINCTRL + select RESET_CONTROLLER ++ select ARM_AMBA + help + This enables support for StarFive SoC platform hardware. + +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0027-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch b/srcpkgs/linux6.4/patches/0027-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch new file mode 100644 index 0000000000000..2e3e4cfda6003 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0027-ASoC-dt-bindings-Add-TDM-controller-bindings-for-Sta.patch @@ -0,0 +1,123 @@ +From aa565c51304fc1cfee016bc466baeb979a7c225d Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Fri, 26 May 2023 22:54:00 +0800 +Subject: [PATCH 27/72] ASoC: dt-bindings: Add TDM controller bindings for + StarFive JH7110 + +Add bindings for TDM driver which supports multi-channel audio playback +and capture on JH7110 platform. + +Reviewed-by: Krzysztof Kozlowski +Signed-off-by: Walker Chen +--- + .../bindings/sound/starfive,jh7110-tdm.yaml | 98 +++++++++++++++++++ + 1 file changed, 98 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml + +diff --git a/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml b/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml +new file mode 100644 +index 000000000000..abb373fbfa26 +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml +@@ -0,0 +1,98 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/starfive,jh7110-tdm.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 TDM Controller ++ ++description: | ++ The TDM Controller is a Time Division Multiplexed audio interface ++ integrated in StarFive JH7110 SoC, allowing up to 8 channels of ++ audio over a serial interface. The TDM controller can operate both ++ in master and slave mode. ++ ++maintainers: ++ - Walker Chen ++ ++allOf: ++ - $ref: dai-common.yaml# ++ ++properties: ++ compatible: ++ enum: ++ - starfive,jh7110-tdm ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: TDM AHB Clock ++ - description: TDM APB Clock ++ - description: TDM Internal Clock ++ - description: TDM Clock ++ - description: Inner MCLK ++ - description: TDM External Clock ++ ++ clock-names: ++ items: ++ - const: tdm_ahb ++ - const: tdm_apb ++ - const: tdm_internal ++ - const: tdm ++ - const: mclk_inner ++ - const: tdm_ext ++ ++ resets: ++ items: ++ - description: tdm ahb reset line ++ - description: tdm apb reset line ++ - description: tdm core reset line ++ ++ dmas: ++ items: ++ - description: RX DMA Channel ++ - description: TX DMA Channel ++ ++ dma-names: ++ items: ++ - const: rx ++ - const: tx ++ ++ "#sound-dai-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - dmas ++ - dma-names ++ - "#sound-dai-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ tdm@10090000 { ++ compatible = "starfive,jh7110-tdm"; ++ reg = <0x10090000 0x1000>; ++ clocks = <&syscrg 184>, ++ <&syscrg 185>, ++ <&syscrg 186>, ++ <&syscrg 187>, ++ <&syscrg 17>, ++ <&tdm_ext>; ++ clock-names = "tdm_ahb", "tdm_apb", ++ "tdm_internal", "tdm", ++ "mclk_inner", "tdm_ext"; ++ resets = <&syscrg 105>, ++ <&syscrg 107>, ++ <&syscrg 106>; ++ dmas = <&dma 20>, <&dma 21>; ++ dma-names = "rx","tx"; ++ #sound-dai-cells = <0>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0028-ASoC-starfive-Add-JH7110-TDM-driver.patch b/srcpkgs/linux6.4/patches/0028-ASoC-starfive-Add-JH7110-TDM-driver.patch new file mode 100644 index 0000000000000..287fd75dfe4de --- /dev/null +++ b/srcpkgs/linux6.4/patches/0028-ASoC-starfive-Add-JH7110-TDM-driver.patch @@ -0,0 +1,760 @@ +From f437f44b7a45a84abac8e5f19ca3a01992d1ce11 Mon Sep 17 00:00:00 2001 +From: Walker Chen +Date: Fri, 26 May 2023 22:54:01 +0800 +Subject: [PATCH 28/72] ASoC: starfive: Add JH7110 TDM driver + +Add tdm driver support for the StarFive JH7110 SoC. + +Signed-off-by: Walker Chen +--- + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/starfive/Kconfig | 15 + + sound/soc/starfive/Makefile | 2 + + sound/soc/starfive/jh7110_tdm.c | 679 ++++++++++++++++++++++++++++++++ + 5 files changed, 698 insertions(+) + create mode 100644 sound/soc/starfive/Kconfig + create mode 100644 sound/soc/starfive/Makefile + create mode 100644 sound/soc/starfive/jh7110_tdm.c + +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 848fbae26c3b..8d1d9401ecf2 100644 +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -91,6 +91,7 @@ source "sound/soc/sh/Kconfig" + source "sound/soc/sof/Kconfig" + source "sound/soc/spear/Kconfig" + source "sound/soc/sprd/Kconfig" ++source "sound/soc/starfive/Kconfig" + source "sound/soc/sti/Kconfig" + source "sound/soc/stm/Kconfig" + source "sound/soc/sunxi/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 507eaed1d6a1..65aeb4ef4068 100644 +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -59,6 +59,7 @@ obj-$(CONFIG_SND_SOC) += sh/ + obj-$(CONFIG_SND_SOC) += sof/ + obj-$(CONFIG_SND_SOC) += spear/ + obj-$(CONFIG_SND_SOC) += sprd/ ++obj-$(CONFIG_SND_SOC) += starfive/ + obj-$(CONFIG_SND_SOC) += sti/ + obj-$(CONFIG_SND_SOC) += stm/ + obj-$(CONFIG_SND_SOC) += sunxi/ +diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig +new file mode 100644 +index 000000000000..fafb681f8c0a +--- /dev/null ++++ b/sound/soc/starfive/Kconfig +@@ -0,0 +1,15 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config SND_SOC_STARFIVE ++ tristate "Audio support for StarFive SoC" ++ depends on COMPILE_TEST || ARCH_STARFIVE ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the Starfive SoCs' Audio interfaces. You will also need to ++ select the audio interfaces to support below. ++ ++config SND_SOC_JH7110_TDM ++ tristate "JH7110 TDM device driver" ++ depends on HAVE_CLK && SND_SOC_STARFIVE ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ help ++ Say Y or M if you want to add support for StarFive TDM driver. +diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile +new file mode 100644 +index 000000000000..f7d960211d72 +--- /dev/null ++++ b/sound/soc/starfive/Makefile +@@ -0,0 +1,2 @@ ++# StarFive Platform Support ++obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o +diff --git a/sound/soc/starfive/jh7110_tdm.c b/sound/soc/starfive/jh7110_tdm.c +new file mode 100644 +index 000000000000..973b910d2d3e +--- /dev/null ++++ b/sound/soc/starfive/jh7110_tdm.c +@@ -0,0 +1,679 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * jh7110_tdm.c -- StarFive JH7110 TDM driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * Author: Walker Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TDM_PCMGBCR 0x00 ++ #define PCMGBCR_MASK 0x1e ++ #define PCMGBCR_ENABLE BIT(0) ++ #define PCMGBCR_TRITXEN BIT(4) ++ #define CLKPOL_BIT 5 ++ #define TRITXEN_BIT 4 ++ #define ELM_BIT 3 ++ #define SYNCM_BIT 2 ++ #define MS_BIT 1 ++#define TDM_PCMTXCR 0x04 ++ #define PCMTXCR_TXEN BIT(0) ++ #define IFL_BIT 11 ++ #define WL_BIT 8 ++ #define SSCALE_BIT 4 ++ #define SL_BIT 2 ++ #define LRJ_BIT 1 ++#define TDM_PCMRXCR 0x08 ++ #define PCMRXCR_RXEN BIT(0) ++ #define PCMRXCR_RXSL_MASK 0xc ++ #define PCMRXCR_RXSL_16BIT 0x4 ++ #define PCMRXCR_RXSL_32BIT 0x8 ++ #define PCMRXCR_SCALE_MASK 0xf0 ++ #define PCMRXCR_SCALE_1CH 0x10 ++#define TDM_PCMDIV 0x0c ++ ++#define JH7110_TDM_FIFO 0x170c0000 ++#define JH7110_TDM_FIFO_DEPTH 32 ++ ++enum TDM_MASTER_SLAVE_MODE { ++ TDM_AS_MASTER = 0, ++ TDM_AS_SLAVE, ++}; ++ ++enum TDM_CLKPOL { ++ /* tx raising and rx falling */ ++ TDM_TX_RASING_RX_FALLING = 0, ++ /* tx falling and rx raising */ ++ TDM_TX_FALLING_RX_RASING, ++}; ++ ++enum TDM_ELM { ++ /* only work while SYNCM=0 */ ++ TDM_ELM_LATE = 0, ++ TDM_ELM_EARLY, ++}; ++ ++enum TDM_SYNCM { ++ /* short frame sync */ ++ TDM_SYNCM_SHORT = 0, ++ /* long frame sync */ ++ TDM_SYNCM_LONG, ++}; ++ ++enum TDM_IFL { ++ /* FIFO to send or received : half-1/2, Quarter-1/4 */ ++ TDM_FIFO_HALF = 0, ++ TDM_FIFO_QUARTER, ++}; ++ ++enum TDM_WL { ++ /* send or received word length */ ++ TDM_8BIT_WORD_LEN = 0, ++ TDM_16BIT_WORD_LEN, ++ TDM_20BIT_WORD_LEN, ++ TDM_24BIT_WORD_LEN, ++ TDM_32BIT_WORD_LEN, ++}; ++ ++enum TDM_SL { ++ /* send or received slot length */ ++ TDM_8BIT_SLOT_LEN = 0, ++ TDM_16BIT_SLOT_LEN, ++ TDM_32BIT_SLOT_LEN, ++}; ++ ++enum TDM_LRJ { ++ /* left-justify or right-justify */ ++ TDM_RIGHT_JUSTIFY = 0, ++ TDM_LEFT_JUSTIFT, ++}; ++ ++struct tdm_chan_cfg { ++ enum TDM_IFL ifl; ++ enum TDM_WL wl; ++ unsigned char sscale; ++ enum TDM_SL sl; ++ enum TDM_LRJ lrj; ++ unsigned char enable; ++}; ++ ++struct jh7110_tdm_dev { ++ void __iomem *tdm_base; ++ struct device *dev; ++ struct clk_bulk_data clks[6]; ++ struct reset_control *resets; ++ ++ enum TDM_CLKPOL clkpolity; ++ enum TDM_ELM elm; ++ enum TDM_SYNCM syncm; ++ enum TDM_MASTER_SLAVE_MODE ms_mode; ++ ++ struct tdm_chan_cfg tx; ++ struct tdm_chan_cfg rx; ++ ++ u16 syncdiv; ++ u32 samplerate; ++ u32 pcmclk; ++ ++ /* data related to DMA transfers b/w tdm and DMAC */ ++ struct snd_dmaengine_dai_dma_data play_dma_data; ++ struct snd_dmaengine_dai_dma_data capture_dma_data; ++ u32 saved_pcmgbcr; ++ u32 saved_pcmtxcr; ++ u32 saved_pcmrxcr; ++ u32 saved_pcmdiv; ++}; ++ ++static inline u32 jh7110_tdm_readl(struct jh7110_tdm_dev *tdm, u16 reg) ++{ ++ return readl_relaxed(tdm->tdm_base + reg); ++} ++ ++static inline void jh7110_tdm_writel(struct jh7110_tdm_dev *tdm, u16 reg, u32 val) ++{ ++ writel_relaxed(val, tdm->tdm_base + reg); ++} ++ ++static void jh7110_tdm_save_context(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ tdm->saved_pcmtxcr = jh7110_tdm_readl(tdm, TDM_PCMTXCR); ++ else ++ tdm->saved_pcmrxcr = jh7110_tdm_readl(tdm, TDM_PCMRXCR); ++} ++ ++static void jh7110_tdm_start(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ u32 data; ++ ++ data = jh7110_tdm_readl(tdm, TDM_PCMGBCR); ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, data | PCMGBCR_ENABLE); ++ ++ /* restore context */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, tdm->saved_pcmtxcr | PCMTXCR_TXEN); ++ else ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, tdm->saved_pcmrxcr | PCMRXCR_RXEN); ++} ++ ++static void jh7110_tdm_stop(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ unsigned int val; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ val = jh7110_tdm_readl(tdm, TDM_PCMTXCR); ++ val &= ~PCMTXCR_TXEN; ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, val); ++ } else { ++ val = jh7110_tdm_readl(tdm, TDM_PCMRXCR); ++ val &= ~PCMRXCR_RXEN; ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, val); ++ } ++} ++ ++static int jh7110_tdm_syncdiv(struct jh7110_tdm_dev *tdm) ++{ ++ u32 sl, sscale, syncdiv; ++ ++ if (tdm->rx.sl >= tdm->tx.sl) ++ sl = tdm->rx.sl; ++ else ++ sl = tdm->tx.sl; ++ ++ if (tdm->rx.sscale >= tdm->tx.sscale) ++ sscale = tdm->rx.sscale; ++ else ++ sscale = tdm->tx.sscale; ++ ++ syncdiv = tdm->pcmclk / tdm->samplerate - 1; ++ ++ if ((syncdiv + 1) < (sl * sscale)) { ++ dev_err(tdm->dev, "Failed to set syncdiv!\n"); ++ return -EINVAL; ++ } ++ ++ if (tdm->syncm == TDM_SYNCM_LONG && ++ (tdm->rx.sscale <= 1 || tdm->tx.sscale <= 1) && ++ ((syncdiv + 1) <= sl)) { ++ dev_err(tdm->dev, "Wrong syncdiv! It must be (syncdiv+1) > max[tx.sl, rx.sl]\n"); ++ return -EINVAL; ++ } ++ ++ jh7110_tdm_writel(tdm, TDM_PCMDIV, syncdiv); ++ return 0; ++} ++ ++static int jh7110_tdm_config(struct jh7110_tdm_dev *tdm, ++ struct snd_pcm_substream *substream) ++{ ++ u32 datarx, datatx; ++ int ret; ++ ++ ret = jh7110_tdm_syncdiv(tdm); ++ if (ret) ++ return ret; ++ ++ datarx = (tdm->rx.ifl << IFL_BIT) | ++ (tdm->rx.wl << WL_BIT) | ++ (tdm->rx.sscale << SSCALE_BIT) | ++ (tdm->rx.sl << SL_BIT) | ++ (tdm->rx.lrj << LRJ_BIT); ++ ++ datatx = (tdm->tx.ifl << IFL_BIT) | ++ (tdm->tx.wl << WL_BIT) | ++ (tdm->tx.sscale << SSCALE_BIT) | ++ (tdm->tx.sl << SL_BIT) | ++ (tdm->tx.lrj << LRJ_BIT); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ jh7110_tdm_writel(tdm, TDM_PCMTXCR, datatx); ++ else ++ jh7110_tdm_writel(tdm, TDM_PCMRXCR, datarx); ++ ++ return 0; ++} ++ ++static void jh7110_tdm_clk_disable(struct jh7110_tdm_dev *tdm) ++{ ++ clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); ++} ++ ++static int jh7110_tdm_clk_enable(struct jh7110_tdm_dev *tdm) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(tdm->clks), tdm->clks); ++ if (ret) { ++ dev_err(tdm->dev, "Failed to enable tdm clocks\n"); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(tdm->resets); ++ if (ret) { ++ dev_err(tdm->dev, "Failed to deassert tdm resets\n"); ++ goto dis_tdm_clk; ++ } ++ ++ /* select tdm_ext clock as the clock source for tdm */ ++ ret = clk_set_parent(tdm->clks[5].clk, tdm->clks[4].clk); ++ if (ret) { ++ dev_err(tdm->dev, "Can't set extern clock source for clk_tdm\n"); ++ goto dis_tdm_clk; ++ } ++ ++ return 0; ++ ++dis_tdm_clk: ++ clk_bulk_disable_unprepare(ARRAY_SIZE(tdm->clks), tdm->clks); ++ ++ return ret; ++} ++ ++static int jh7110_tdm_runtime_suspend(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ jh7110_tdm_clk_disable(tdm); ++ return 0; ++} ++ ++static int jh7110_tdm_runtime_resume(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ return jh7110_tdm_clk_enable(tdm); ++} ++ ++static int jh7110_tdm_system_suspend(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ /* save context */ ++ tdm->saved_pcmgbcr = jh7110_tdm_readl(tdm, TDM_PCMGBCR); ++ tdm->saved_pcmdiv = jh7110_tdm_readl(tdm, TDM_PCMDIV); ++ ++ return pm_runtime_force_suspend(dev); ++} ++ ++static int jh7110_tdm_system_resume(struct device *dev) ++{ ++ struct jh7110_tdm_dev *tdm = dev_get_drvdata(dev); ++ ++ /* restore context */ ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, tdm->saved_pcmgbcr); ++ jh7110_tdm_writel(tdm, TDM_PCMDIV, tdm->saved_pcmdiv); ++ ++ return pm_runtime_force_resume(dev); ++} ++ ++static const struct snd_soc_component_driver jh7110_tdm_component = { ++ .name = "jh7110-tdm", ++}; ++ ++static int jh7110_tdm_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *cpu_dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); ++ struct snd_soc_dai_link *dai_link = rtd->dai_link; ++ ++ dai_link->stop_dma_first = 1; ++ ++ return 0; ++} ++ ++static int jh7110_tdm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ int chan_wl, chan_sl, chan_nr; ++ unsigned int data_width; ++ unsigned int dma_bus_width; ++ struct snd_dmaengine_dai_dma_data *dma_data = NULL; ++ int ret; ++ ++ data_width = params_width(params); ++ ++ tdm->samplerate = params_rate(params); ++ tdm->pcmclk = params_channels(params) * tdm->samplerate * data_width; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ chan_wl = TDM_16BIT_WORD_LEN; ++ chan_sl = TDM_16BIT_SLOT_LEN; ++ dma_bus_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ ++ case SNDRV_PCM_FORMAT_S32_LE: ++ chan_wl = TDM_32BIT_WORD_LEN; ++ chan_sl = TDM_32BIT_SLOT_LEN; ++ dma_bus_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ ++ default: ++ dev_err(tdm->dev, "tdm: unsupported PCM fmt"); ++ return -EINVAL; ++ } ++ ++ chan_nr = params_channels(params); ++ switch (chan_nr) { ++ case 1: ++ case 2: ++ case 4: ++ case 6: ++ case 8: ++ break; ++ default: ++ dev_err(tdm->dev, "channel not supported\n"); ++ return -EINVAL; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ tdm->tx.wl = chan_wl; ++ tdm->tx.sl = chan_sl; ++ tdm->tx.sscale = chan_nr; ++ tdm->play_dma_data.addr_width = dma_bus_width; ++ dma_data = &tdm->play_dma_data; ++ } else { ++ tdm->rx.wl = chan_wl; ++ tdm->rx.sl = chan_sl; ++ tdm->rx.sscale = chan_nr; ++ tdm->capture_dma_data.addr_width = dma_bus_width; ++ dma_data = &tdm->capture_dma_data; ++ } ++ ++ snd_soc_dai_set_dma_data(dai, substream, dma_data); ++ ++ ret = jh7110_tdm_config(tdm, substream); ++ if (ret) ++ return ret; ++ ++ jh7110_tdm_save_context(tdm, substream); ++ return 0; ++} ++ ++static int jh7110_tdm_trigger(struct snd_pcm_substream *substream, ++ int cmd, struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ jh7110_tdm_start(tdm, substream); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ jh7110_tdm_stop(tdm, substream); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int jh7110_tdm_set_dai_fmt(struct snd_soc_dai *cpu_dai, ++ unsigned int fmt) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(cpu_dai); ++ unsigned int gbcr; ++ ++ /* set master/slave audio interface */ ++ switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { ++ case SND_SOC_DAIFMT_BP_FP: ++ /* cpu is master */ ++ tdm->ms_mode = TDM_AS_MASTER; ++ break; ++ case SND_SOC_DAIFMT_BC_FC: ++ /* codec is master */ ++ tdm->ms_mode = TDM_AS_SLAVE; ++ break; ++ case SND_SOC_DAIFMT_BC_FP: ++ case SND_SOC_DAIFMT_BP_FC: ++ return -EINVAL; ++ default: ++ dev_dbg(tdm->dev, "dwc : Invalid clock provider format\n"); ++ return -EINVAL; ++ } ++ ++ gbcr = (tdm->clkpolity << CLKPOL_BIT) | ++ (tdm->elm << ELM_BIT) | ++ (tdm->syncm << SYNCM_BIT) | ++ (tdm->ms_mode << MS_BIT); ++ jh7110_tdm_writel(tdm, TDM_PCMGBCR, gbcr); ++ ++ return 0; ++} ++ ++static const struct snd_soc_dai_ops jh7110_tdm_dai_ops = { ++ .startup = jh7110_tdm_startup, ++ .hw_params = jh7110_tdm_hw_params, ++ .trigger = jh7110_tdm_trigger, ++ .set_fmt = jh7110_tdm_set_dai_fmt, ++}; ++ ++static int jh7110_tdm_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct jh7110_tdm_dev *tdm = snd_soc_dai_get_drvdata(dai); ++ ++ snd_soc_dai_init_dma_data(dai, &tdm->play_dma_data, &tdm->capture_dma_data); ++ snd_soc_dai_set_drvdata(dai, tdm); ++ return 0; ++} ++ ++#define JH7110_TDM_RATES SNDRV_PCM_RATE_8000_48000 ++ ++#define JH7110_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ ++ SNDRV_PCM_FMTBIT_S32_LE) ++ ++static struct snd_soc_dai_driver jh7110_tdm_dai = { ++ .name = "sf_tdm", ++ .id = 0, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = JH7110_TDM_RATES, ++ .formats = JH7110_TDM_FORMATS, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 8, ++ .rates = JH7110_TDM_RATES, ++ .formats = JH7110_TDM_FORMATS, ++ }, ++ .ops = &jh7110_tdm_dai_ops, ++ .probe = jh7110_tdm_dai_probe, ++ .symmetric_rate = 1, ++}; ++ ++static const struct snd_pcm_hardware jh7110_pcm_hardware = { ++ .info = (SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID | ++ SNDRV_PCM_INFO_PAUSE | ++ SNDRV_PCM_INFO_RESUME | ++ SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER), ++ .buffer_bytes_max = 192512, ++ .period_bytes_min = 4096, ++ .period_bytes_max = 32768, ++ .periods_min = 1, ++ .periods_max = 48, ++ .fifo_size = 16, ++}; ++ ++static const struct snd_dmaengine_pcm_config jh7110_dmaengine_pcm_config = { ++ .pcm_hardware = &jh7110_pcm_hardware, ++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, ++ .prealloc_buffer_size = 192512, ++}; ++ ++static void jh7110_tdm_init_params(struct jh7110_tdm_dev *tdm) ++{ ++ tdm->clkpolity = TDM_TX_RASING_RX_FALLING; ++ tdm->elm = TDM_ELM_LATE; ++ tdm->syncm = TDM_SYNCM_SHORT; ++ ++ tdm->rx.ifl = TDM_FIFO_HALF; ++ tdm->tx.ifl = TDM_FIFO_HALF; ++ tdm->rx.wl = TDM_16BIT_WORD_LEN; ++ tdm->tx.wl = TDM_16BIT_WORD_LEN; ++ tdm->rx.sscale = 2; ++ tdm->tx.sscale = 2; ++ tdm->rx.lrj = TDM_LEFT_JUSTIFT; ++ tdm->tx.lrj = TDM_LEFT_JUSTIFT; ++ ++ tdm->play_dma_data.addr = JH7110_TDM_FIFO; ++ tdm->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ tdm->play_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; ++ tdm->play_dma_data.maxburst = 16; ++ ++ tdm->capture_dma_data.addr = JH7110_TDM_FIFO; ++ tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ tdm->capture_dma_data.fifo_size = JH7110_TDM_FIFO_DEPTH / 2; ++ tdm->capture_dma_data.maxburst = 8; ++} ++ ++static int jh7110_tdm_clk_reset_get(struct platform_device *pdev, ++ struct jh7110_tdm_dev *tdm) ++{ ++ int ret; ++ ++ tdm->clks[0].id = "mclk_inner"; ++ tdm->clks[1].id = "tdm_ahb"; ++ tdm->clks[2].id = "tdm_apb"; ++ tdm->clks[3].id = "tdm_internal"; ++ tdm->clks[4].id = "tdm_ext"; ++ tdm->clks[5].id = "tdm"; ++ ++ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(tdm->clks), tdm->clks); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to get tdm clocks\n"); ++ return ret; ++ } ++ ++ tdm->resets = devm_reset_control_array_get_exclusive(&pdev->dev); ++ if (IS_ERR_OR_NULL(tdm->resets)) { ++ ret = PTR_ERR(tdm->resets); ++ dev_err(&pdev->dev, "Failed to get tdm resets"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int jh7110_tdm_probe(struct platform_device *pdev) ++{ ++ struct jh7110_tdm_dev *tdm; ++ int ret; ++ ++ tdm = devm_kzalloc(&pdev->dev, sizeof(*tdm), GFP_KERNEL); ++ if (!tdm) ++ return -ENOMEM; ++ ++ tdm->tdm_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(tdm->tdm_base)) ++ return PTR_ERR(tdm->tdm_base); ++ ++ tdm->dev = &pdev->dev; ++ ++ ret = jh7110_tdm_clk_reset_get(pdev, tdm); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to enable audio-tdm clock\n"); ++ return ret; ++ } ++ ++ jh7110_tdm_init_params(tdm); ++ ++ dev_set_drvdata(&pdev->dev, tdm); ++ ret = devm_snd_soc_register_component(&pdev->dev, &jh7110_tdm_component, ++ &jh7110_tdm_dai, 1); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to register dai\n"); ++ return ret; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, ++ &jh7110_dmaengine_pcm_config, ++ SND_DMAENGINE_PCM_FLAG_COMPAT); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register pcm: %d\n", ret); ++ return ret; ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ if (!pm_runtime_enabled(&pdev->dev)) { ++ ret = jh7110_tdm_runtime_resume(&pdev->dev); ++ if (ret) ++ goto err_pm_disable; ++ } ++ ++ return 0; ++ ++err_pm_disable: ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int jh7110_tdm_dev_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id jh7110_tdm_of_match[] = { ++ { .compatible = "starfive,jh7110-tdm", }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, jh7110_tdm_of_match); ++ ++static const struct dev_pm_ops jh7110_tdm_pm_ops = { ++ RUNTIME_PM_OPS(jh7110_tdm_runtime_suspend, ++ jh7110_tdm_runtime_resume, NULL) ++ SYSTEM_SLEEP_PM_OPS(jh7110_tdm_system_suspend, ++ jh7110_tdm_system_resume) ++}; ++ ++static struct platform_driver jh7110_tdm_driver = { ++ .driver = { ++ .name = "jh7110-tdm", ++ .of_match_table = jh7110_tdm_of_match, ++ .pm = pm_ptr(&jh7110_tdm_pm_ops), ++ }, ++ .probe = jh7110_tdm_probe, ++ .remove = jh7110_tdm_dev_remove, ++}; ++module_platform_driver(jh7110_tdm_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 TDM ASoC Driver"); ++MODULE_AUTHOR("Walker Chen "); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0029-ASoC-dt-bindings-Add-StarFive-JH7110-dummy-PWM-DAC-t.patch b/srcpkgs/linux6.4/patches/0029-ASoC-dt-bindings-Add-StarFive-JH7110-dummy-PWM-DAC-t.patch new file mode 100644 index 0000000000000..6dcf00f6bf354 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0029-ASoC-dt-bindings-Add-StarFive-JH7110-dummy-PWM-DAC-t.patch @@ -0,0 +1,61 @@ +From d8b9c810238fa7152955067de7f69a5d09208f62 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Wed, 21 Jun 2023 16:21:59 +0800 +Subject: [PATCH 29/72] ASoC: dt-bindings: Add StarFive JH7110 dummy PWM-DAC + transmitter + +Add bindings for StarFive JH7110 dummy PWM-DAC transmitter. + +Signed-off-by: Hal Feng +--- + .../sound/starfive,jh7110-pwmdac-dit.yaml | 38 +++++++++++++++++++ + 1 file changed, 38 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac-dit.yaml + +diff --git a/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac-dit.yaml b/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac-dit.yaml +new file mode 100644 +index 000000000000..bc43e3b1e9d2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac-dit.yaml +@@ -0,0 +1,38 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac-dit.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 Dummy PWM-DAC Transmitter ++ ++maintainers: ++ - Hal Feng ++ ++allOf: ++ - $ref: dai-common.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pwmdac-dit ++ ++ "#sound-dai-cells": ++ const: 0 ++ ++ sound-name-prefix: true ++ ++required: ++ - compatible ++ - "#sound-dai-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pwmdac-dit { ++ compatible = "starfive,jh7110-pwmdac-dit"; ++ #sound-dai-cells = <0>; ++ }; ++ ++... ++ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0030-ASoC-codecs-Add-StarFive-JH7110-dummy-PWM-DAC-transm.patch b/srcpkgs/linux6.4/patches/0030-ASoC-codecs-Add-StarFive-JH7110-dummy-PWM-DAC-transm.patch new file mode 100644 index 0000000000000..1ac0d3ad42b1d --- /dev/null +++ b/srcpkgs/linux6.4/patches/0030-ASoC-codecs-Add-StarFive-JH7110-dummy-PWM-DAC-transm.patch @@ -0,0 +1,142 @@ +From e31c750e015bdd738af6c977e1441d0e8554b140 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Wed, 21 Jun 2023 17:10:39 +0800 +Subject: [PATCH 30/72] ASoC: codecs: Add StarFive JH7110 dummy PWM-DAC + transmitter driver + +Add a dummy transmitter driver for StarFive JH7110 PWM-DAC module. +StarFive JH7110 PWM-DAC controller uses this driver. + +Signed-off-by: Hal Feng +--- + sound/soc/codecs/Kconfig | 4 ++ + sound/soc/codecs/Makefile | 2 + + sound/soc/codecs/jh7110_pwmdac_transmitter.c | 74 ++++++++++++++++++++ + 3 files changed, 80 insertions(+) + create mode 100644 sound/soc/codecs/jh7110_pwmdac_transmitter.c + +diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig +index 8020097d4e4c..f2cd8f999649 100644 +--- a/sound/soc/codecs/Kconfig ++++ b/sound/soc/codecs/Kconfig +@@ -115,6 +115,7 @@ config SND_SOC_ALL_CODECS + imply SND_SOC_IDT821034 + imply SND_SOC_INNO_RK3036 + imply SND_SOC_ISABELLE ++ imply SND_SOC_JH7110_PWMDAC_DIT + imply SND_SOC_JZ4740_CODEC + imply SND_SOC_JZ4725B_CODEC + imply SND_SOC_JZ4760_CODEC +@@ -903,6 +904,9 @@ config SND_SOC_CX2072X + help + Enable support for Conexant CX20721 and CX20723 codec chips. + ++config SND_SOC_JH7110_PWMDAC_DIT ++ tristate "StarFive JH7110 dummy PWM-DAC transmitter" ++ + config SND_SOC_JZ4740_CODEC + depends on MACH_INGENIC || COMPILE_TEST + depends on OF +diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile +index 5cdbae88e6e3..8e0e12d7b959 100644 +--- a/sound/soc/codecs/Makefile ++++ b/sound/soc/codecs/Makefile +@@ -122,6 +122,7 @@ snd-soc-ics43432-objs := ics43432.o + snd-soc-idt821034-objs := idt821034.o + snd-soc-inno-rk3036-objs := inno_rk3036.o + snd-soc-isabelle-objs := isabelle.o ++snd-soc-jh7110-pwmdac-dit-objs := jh7110_pwmdac_transmitter.o + snd-soc-jz4740-codec-objs := jz4740.o + snd-soc-jz4725b-codec-objs := jz4725b.o + snd-soc-jz4760-codec-objs := jz4760.o +@@ -496,6 +497,7 @@ obj-$(CONFIG_SND_SOC_ICS43432) += snd-soc-ics43432.o + obj-$(CONFIG_SND_SOC_IDT821034) += snd-soc-idt821034.o + obj-$(CONFIG_SND_SOC_INNO_RK3036) += snd-soc-inno-rk3036.o + obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o ++obj-$(CONFIG_SND_SOC_JH7110_PWMDAC_DIT) += snd-soc-jh7110-pwmdac-dit.o + obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o + obj-$(CONFIG_SND_SOC_JZ4725B_CODEC) += snd-soc-jz4725b-codec.o + obj-$(CONFIG_SND_SOC_JZ4760_CODEC) += snd-soc-jz4760-codec.o +diff --git a/sound/soc/codecs/jh7110_pwmdac_transmitter.c b/sound/soc/codecs/jh7110_pwmdac_transmitter.c +new file mode 100644 +index 000000000000..69077be840c7 +--- /dev/null ++++ b/sound/soc/codecs/jh7110_pwmdac_transmitter.c +@@ -0,0 +1,74 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Dummy PWM-DAC transmitter driver for the StarFive JH7110 SoC ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRV_NAME "pwmdac-dit" ++ ++static const struct snd_soc_dapm_widget dit_widgets[] = { ++ SND_SOC_DAPM_OUTPUT("pwmdac-out"), ++}; ++ ++static const struct snd_soc_dapm_route dit_routes[] = { ++ { "pwmdac-out", NULL, "Playback" }, ++}; ++ ++static const struct snd_soc_component_driver soc_codec_pwmdac_dit = { ++ .dapm_widgets = dit_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(dit_widgets), ++ .dapm_routes = dit_routes, ++ .num_dapm_routes = ARRAY_SIZE(dit_routes), ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++}; ++ ++static struct snd_soc_dai_driver dit_stub_dai = { ++ .name = "pwmdac-dit-hifi", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 384, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ }, ++}; ++ ++static int pwmdac_dit_probe(struct platform_device *pdev) ++{ ++ return devm_snd_soc_register_component(&pdev->dev, ++ &soc_codec_pwmdac_dit, ++ &dit_stub_dai, 1); ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id pwmdac_dit_dt_ids[] = { ++ { .compatible = "starfive,jh7110-pwmdac-dit", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pwmdac_dit_dt_ids); ++#endif ++ ++static struct platform_driver pwmdac_dit_driver = { ++ .probe = pwmdac_dit_probe, ++ .driver = { ++ .name = DRV_NAME, ++ .of_match_table = of_match_ptr(pwmdac_dit_dt_ids), ++ }, ++}; ++ ++module_platform_driver(pwmdac_dit_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 dummy PWM-DAC transmitter driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:" DRV_NAME); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0031-ASoC-dt-bindings-Add-StarFive-JH7110-PWM-DAC-control.patch b/srcpkgs/linux6.4/patches/0031-ASoC-dt-bindings-Add-StarFive-JH7110-PWM-DAC-control.patch new file mode 100644 index 0000000000000..c89eac4b7db08 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0031-ASoC-dt-bindings-Add-StarFive-JH7110-PWM-DAC-control.patch @@ -0,0 +1,100 @@ +From 458f4293dc2425aa73341a9d1b554d01a177f1c2 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Mon, 19 Jun 2023 09:31:16 +0800 +Subject: [PATCH 31/72] ASoC: dt-bindings: Add StarFive JH7110 PWM-DAC + controller + +Add bindings for the PWM-DAC controller on the JH7110 +RISC-V SoC by StarFive Ltd. + +Signed-off-by: Hal Feng +--- + .../sound/starfive,jh7110-pwmdac.yaml | 76 +++++++++++++++++++ + 1 file changed, 76 insertions(+) + create mode 100644 Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac.yaml + +diff --git a/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac.yaml b/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac.yaml +new file mode 100644 +index 000000000000..91a4213f2bd8 +--- /dev/null ++++ b/Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac.yaml +@@ -0,0 +1,76 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/sound/starfive,jh7110-pwmdac.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PWM-DAC Controller ++ ++description: | ++ The PWM-DAC Controller uses PWM square wave generators plus RC filters to ++ form a DAC for audio play in StarFive JH7110 SoC. This audio play controller ++ supports 16 bit audio format, up to 48K sampling frequency , up to left ++ and right dual channels. ++ ++maintainers: ++ - Hal Feng ++ ++allOf: ++ - $ref: dai-common.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pwmdac ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: PWMDAC APB ++ - description: PWMDAC CORE ++ ++ clock-names: ++ items: ++ - const: apb ++ - const: core ++ ++ resets: ++ maxItems: 1 ++ description: PWMDAC APB ++ ++ dmas: ++ maxItems: 1 ++ description: TX DMA Channel ++ ++ dma-names: ++ const: tx ++ ++ "#sound-dai-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - dmas ++ - dma-names ++ - "#sound-dai-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pwmdac@100b0000 { ++ compatible = "starfive,jh7110-pwmdac"; ++ reg = <0x100b0000 0x1000>; ++ clocks = <&syscrg 157>, ++ <&syscrg 158>; ++ clock-names = "apb", "core"; ++ resets = <&syscrg 96>; ++ dmas = <&dma 22>; ++ dma-names = "tx"; ++ #sound-dai-cells = <0>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0032-ASoC-starfive-Add-JH7110-PWM-DAC-driver.patch b/srcpkgs/linux6.4/patches/0032-ASoC-starfive-Add-JH7110-PWM-DAC-driver.patch new file mode 100644 index 0000000000000..b8a0a78b5a7f7 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0032-ASoC-starfive-Add-JH7110-PWM-DAC-driver.patch @@ -0,0 +1,839 @@ +From 10d7c6258983e203bcc2305332a6f4557d5a068a Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Wed, 17 May 2023 09:56:38 +0800 +Subject: [PATCH 32/72] ASoC: starfive: Add JH7110 PWM-DAC driver + +Add PWM-DAC driver support for the StarFive JH7110 SoC. + +Signed-off-by: Hal Feng +--- + sound/soc/starfive/Kconfig | 9 + + sound/soc/starfive/Makefile | 1 + + sound/soc/starfive/jh7110_pwmdac.c | 787 +++++++++++++++++++++++++++++ + 3 files changed, 797 insertions(+) + create mode 100644 sound/soc/starfive/jh7110_pwmdac.c + +diff --git a/sound/soc/starfive/Kconfig b/sound/soc/starfive/Kconfig +index fafb681f8c0a..fabef377db8c 100644 +--- a/sound/soc/starfive/Kconfig ++++ b/sound/soc/starfive/Kconfig +@@ -7,6 +7,15 @@ config SND_SOC_STARFIVE + the Starfive SoCs' Audio interfaces. You will also need to + select the audio interfaces to support below. + ++config SND_SOC_JH7110_PWMDAC ++ tristate "JH7110 PWM-DAC device driver" ++ depends on HAVE_CLK && SND_SOC_STARFIVE ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_JH7110_PWMDAC_DIT ++ help ++ Say Y or M if you want to add support for StarFive JH7110 ++ PWM-DAC driver. ++ + config SND_SOC_JH7110_TDM + tristate "JH7110 TDM device driver" + depends on HAVE_CLK && SND_SOC_STARFIVE +diff --git a/sound/soc/starfive/Makefile b/sound/soc/starfive/Makefile +index f7d960211d72..9e958f70ef51 100644 +--- a/sound/soc/starfive/Makefile ++++ b/sound/soc/starfive/Makefile +@@ -1,2 +1,3 @@ + # StarFive Platform Support ++obj-$(CONFIG_SND_SOC_JH7110_PWMDAC) += jh7110_pwmdac.o + obj-$(CONFIG_SND_SOC_JH7110_TDM) += jh7110_tdm.o +diff --git a/sound/soc/starfive/jh7110_pwmdac.c b/sound/soc/starfive/jh7110_pwmdac.c +new file mode 100644 +index 000000000000..c3123bd6ea45 +--- /dev/null ++++ b/sound/soc/starfive/jh7110_pwmdac.c +@@ -0,0 +1,787 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * jh7110_pwmdac.c -- StarFive JH7110 PWM-DAC driver ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ * ++ * Authors: Jenny Zhang ++ * Curry Zhang ++ * Xingyu Wu ++ * Hal Feng ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define JH7110_PWMDAC_WDATA 0x00 ++#define JH7110_PWMDAC_CTRL 0x04 ++ #define JH7110_PWMDAC_ENABLE BIT(0) ++ #define JH7110_PWMDAC_SHIFT BIT(1) ++ #define JH7110_PWMDAC_DUTY_CYCLE_SHIFT 2 ++ #define JH7110_PWMDAC_DUTY_CYCLE_MASK GENMASK(3, 2) ++ #define JH7110_PWMDAC_CNT_N_SHIFT 4 ++ #define JH7110_PWMDAC_CNT_N_MASK GENMASK(12, 4) ++ #define JH7110_PWMDAC_DATA_CHANGE BIT(13) ++ #define JH7110_PWMDAC_DATA_MODE BIT(14) ++ #define JH7110_PWMDAC_DATA_SHIFT_SHIFT 15 ++ #define JH7110_PWMDAC_DATA_SHIFT_MASK GENMASK(17, 15) ++ ++enum JH7110_PWMDAC_SHIFT_VAL { ++ PWMDAC_SHIFT_8 = 0, ++ PWMDAC_SHIFT_10, ++}; ++ ++enum JH7110_PWMDAC_DUTY_CYCLE_VAL { ++ PWMDAC_CYCLE_LEFT = 0, ++ PWMDAC_CYCLE_RIGHT, ++ PWMDAC_CYCLE_CENTER, ++}; ++ ++enum JH7110_PWMDAC_CNT_N_VAL { ++ PWMDAC_SAMPLE_CNT_1 = 1, ++ PWMDAC_SAMPLE_CNT_2, ++ PWMDAC_SAMPLE_CNT_3, ++ PWMDAC_SAMPLE_CNT_512 = 512, /* max */ ++}; ++ ++enum JH7110_PWMDAC_DATA_CHANGE_VAL { ++ NO_CHANGE = 0, ++ CHANGE, ++}; ++ ++enum JH7110_PWMDAC_DATA_MODE_VAL { ++ UNSIGNED_DATA = 0, ++ INVERTER_DATA_MSB, ++}; ++ ++enum JH7110_PWMDAC_DATA_SHIFT_VAL { ++ PWMDAC_DATA_LEFT_SHIFT_BIT_0 = 0, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_1, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_2, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_3, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_4, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_5, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_6, ++ PWMDAC_DATA_LEFT_SHIFT_BIT_7, ++}; ++ ++struct jh7110_pwmdac_dev { ++ void __iomem *base; ++ resource_size_t mapbase; ++ u8 shift; ++ u8 duty_cycle; ++ u8 cnt_n; ++ u8 data_change; ++ u8 data_mode; ++ u8 data_shift; ++ ++ struct clk_bulk_data clks[2]; ++ struct reset_control *rst_apb; ++ struct device *dev; ++ struct snd_dmaengine_dai_dma_data play_dma_data; ++ u32 saved_ctrl; ++}; ++ ++enum jh7110_ct_pwmdac_name { ++ PWMDAC_CT_SHIFT = 0, ++ PWMDAC_CT_DUTY_CYCLE, ++ PWMDAC_CT_DATA_CHANGE, ++ PWMDAC_CT_DATA_MODE, ++ PWMDAC_CT_DATA_SHIFT, ++}; ++ ++struct jh7110_ct_pwmdac { ++ char *name; ++ unsigned int vals; ++}; ++ ++static const struct jh7110_ct_pwmdac pwmdac_ct_shift[] = { ++ { .name = "8bit", .vals = PWMDAC_SHIFT_8 }, ++ { .name = "10bit", .vals = PWMDAC_SHIFT_10 } ++}; ++ ++static const struct jh7110_ct_pwmdac pwmdac_ct_duty_cycle[] = { ++ { .name = "left", .vals = PWMDAC_CYCLE_LEFT }, ++ { .name = "right", .vals = PWMDAC_CYCLE_RIGHT }, ++ { .name = "center", .vals = PWMDAC_CYCLE_CENTER } ++}; ++ ++static const struct jh7110_ct_pwmdac pwmdac_ct_data_change[] = { ++ { .name = "no_change", .vals = NO_CHANGE }, ++ { .name = "change", .vals = CHANGE } ++}; ++ ++static const struct jh7110_ct_pwmdac pwmdac_ct_data_mode[] = { ++ { .name = "unsigned", .vals = UNSIGNED_DATA }, ++ { .name = "inverter", .vals = INVERTER_DATA_MSB } ++}; ++ ++static const struct jh7110_ct_pwmdac pwmdac_ct_data_shift[] = { ++ { .name = "left 0 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_0 }, ++ { .name = "left 1 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_1 }, ++ { .name = "left 2 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_2 }, ++ { .name = "left 3 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_3 }, ++ { .name = "left 4 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_4 }, ++ { .name = "left 5 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_5 }, ++ { .name = "left 6 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_6 }, ++ { .name = "left 7 bit", .vals = PWMDAC_DATA_LEFT_SHIFT_BIT_7 } ++}; ++ ++static int jh7110_pwmdac_info(struct snd_ctl_elem_info *uinfo, int pwmdac_ct) ++{ ++ unsigned int items; ++ ++ if (pwmdac_ct == PWMDAC_CT_SHIFT) { ++ items = ARRAY_SIZE(pwmdac_ct_shift); ++ strcpy(uinfo->value.enumerated.name, ++ pwmdac_ct_shift[uinfo->value.enumerated.item].name); ++ } else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) { ++ items = ARRAY_SIZE(pwmdac_ct_duty_cycle); ++ strcpy(uinfo->value.enumerated.name, ++ pwmdac_ct_duty_cycle[uinfo->value.enumerated.item].name); ++ } else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) { ++ items = ARRAY_SIZE(pwmdac_ct_data_change); ++ strcpy(uinfo->value.enumerated.name, ++ pwmdac_ct_data_change[uinfo->value.enumerated.item].name); ++ } else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) { ++ items = ARRAY_SIZE(pwmdac_ct_data_mode); ++ strcpy(uinfo->value.enumerated.name, ++ pwmdac_ct_data_mode[uinfo->value.enumerated.item].name); ++ } else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) { ++ items = ARRAY_SIZE(pwmdac_ct_data_shift); ++ strcpy(uinfo->value.enumerated.name, ++ pwmdac_ct_data_shift[uinfo->value.enumerated.item].name); ++ } ++ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; ++ uinfo->count = 1; ++ uinfo->value.enumerated.items = items; ++ if (uinfo->value.enumerated.item >= items) ++ uinfo->value.enumerated.item = items - 1; ++ ++ return 0; ++} ++ ++static int jh7110_pwmdac_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol, ++ int pwmdac_ct) ++{ ++ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); ++ struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component); ++ ++ if (pwmdac_ct == PWMDAC_CT_SHIFT) ++ ucontrol->value.enumerated.item[0] = dev->shift; ++ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) ++ ucontrol->value.enumerated.item[0] = dev->duty_cycle; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) ++ ucontrol->value.enumerated.item[0] = dev->data_change; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) ++ ucontrol->value.enumerated.item[0] = dev->data_mode; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) ++ ucontrol->value.enumerated.item[0] = dev->data_shift; ++ ++ return 0; ++} ++ ++static int jh7110_pwmdac_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol, ++ int pwmdac_ct) ++{ ++ struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); ++ struct jh7110_pwmdac_dev *dev = snd_soc_component_get_drvdata(component); ++ int sel = ucontrol->value.enumerated.item[0]; ++ unsigned int items; ++ ++ if (pwmdac_ct == PWMDAC_CT_SHIFT) ++ items = ARRAY_SIZE(pwmdac_ct_shift); ++ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) ++ items = ARRAY_SIZE(pwmdac_ct_duty_cycle); ++ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) ++ items = ARRAY_SIZE(pwmdac_ct_data_change); ++ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) ++ items = ARRAY_SIZE(pwmdac_ct_data_mode); ++ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) ++ items = ARRAY_SIZE(pwmdac_ct_data_shift); ++ ++ if (sel >= items) ++ return -EINVAL; ++ ++ if (pwmdac_ct == PWMDAC_CT_SHIFT) ++ dev->shift = pwmdac_ct_shift[sel].vals; ++ else if (pwmdac_ct == PWMDAC_CT_DUTY_CYCLE) ++ dev->duty_cycle = pwmdac_ct_duty_cycle[sel].vals; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_CHANGE) ++ dev->data_change = pwmdac_ct_data_change[sel].vals; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_MODE) ++ dev->data_mode = pwmdac_ct_data_mode[sel].vals; ++ else if (pwmdac_ct == PWMDAC_CT_DATA_SHIFT) ++ dev->data_shift = pwmdac_ct_data_shift[sel].vals; ++ ++ return 0; ++} ++ ++static int jh7110_pwmdac_shift_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_SHIFT); ++} ++ ++static int jh7110_pwmdac_shift_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_SHIFT); ++} ++ ++static int jh7110_pwmdac_shift_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_SHIFT); ++} ++ ++static int jh7110_pwmdac_duty_cycle_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DUTY_CYCLE); ++} ++ ++static int jh7110_pwmdac_duty_cycle_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE); ++} ++ ++static int jh7110_pwmdac_duty_cycle_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DUTY_CYCLE); ++} ++ ++static int jh7110_pwmdac_data_change_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_CHANGE); ++} ++ ++static int jh7110_pwmdac_data_change_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE); ++} ++ ++static int jh7110_pwmdac_data_change_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_CHANGE); ++} ++ ++static int jh7110_pwmdac_data_mode_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_MODE); ++} ++ ++static int jh7110_pwmdac_data_mode_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE); ++} ++ ++static int jh7110_pwmdac_data_mode_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_MODE); ++} ++ ++static int jh7110_pwmdac_data_shift_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ return jh7110_pwmdac_info(uinfo, PWMDAC_CT_DATA_SHIFT); ++} ++ ++static int jh7110_pwmdac_data_shift_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_get(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT); ++} ++ ++static int jh7110_pwmdac_data_shift_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ return jh7110_pwmdac_put(kcontrol, ucontrol, PWMDAC_CT_DATA_SHIFT); ++} ++ ++static inline void jh7110_pwmdac_write_reg(void __iomem *io_base, int reg, u32 val) ++{ ++ writel(val, io_base + reg); ++} ++ ++static inline u32 jh7110_pwmdac_read_reg(void __iomem *io_base, int reg) ++{ ++ return readl(io_base + reg); ++} ++ ++static void jh7110_pwmdac_set_enable(struct jh7110_pwmdac_dev *dev, bool enable) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ if (enable) ++ value |= JH7110_PWMDAC_ENABLE; ++ else ++ value &= ~JH7110_PWMDAC_ENABLE; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_shift(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ if (dev->shift == PWMDAC_SHIFT_8) ++ value &= ~JH7110_PWMDAC_SHIFT; ++ else if (dev->shift == PWMDAC_SHIFT_10) ++ value |= JH7110_PWMDAC_SHIFT; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_duty_cycle(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ value &= ~JH7110_PWMDAC_DUTY_CYCLE_MASK; ++ value |= (dev->duty_cycle & 0x3) << JH7110_PWMDAC_DUTY_CYCLE_SHIFT; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_cnt_n(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ value &= ~JH7110_PWMDAC_CNT_N_MASK; ++ value |= ((dev->cnt_n - 1) & 0x1ff) << JH7110_PWMDAC_CNT_N_SHIFT; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_data_change(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ if (dev->data_change == NO_CHANGE) ++ value &= ~JH7110_PWMDAC_DATA_CHANGE; ++ else if (dev->data_change == CHANGE) ++ value |= JH7110_PWMDAC_DATA_CHANGE; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_data_mode(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ if (dev->data_mode == UNSIGNED_DATA) ++ value &= ~JH7110_PWMDAC_DATA_MODE; ++ else if (dev->data_mode == INVERTER_DATA_MSB) ++ value |= JH7110_PWMDAC_DATA_MODE; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set_data_shift(struct jh7110_pwmdac_dev *dev) ++{ ++ u32 value; ++ ++ value = jh7110_pwmdac_read_reg(dev->base, JH7110_PWMDAC_CTRL); ++ value &= ~JH7110_PWMDAC_DATA_SHIFT_MASK; ++ value |= (dev->data_shift & 0x7) << JH7110_PWMDAC_DATA_SHIFT_SHIFT; ++ ++ jh7110_pwmdac_write_reg(dev->base, JH7110_PWMDAC_CTRL, value); ++} ++ ++static void jh7110_pwmdac_set(struct jh7110_pwmdac_dev *dev) ++{ ++ jh7110_pwmdac_set_shift(dev); ++ jh7110_pwmdac_set_duty_cycle(dev); ++ jh7110_pwmdac_set_cnt_n(dev); ++ jh7110_pwmdac_set_enable(dev, true); ++ ++ jh7110_pwmdac_set_data_change(dev); ++ jh7110_pwmdac_set_data_mode(dev); ++ jh7110_pwmdac_set_data_shift(dev); ++} ++ ++static void jh7110_pwmdac_stop(struct jh7110_pwmdac_dev *dev) ++{ ++ jh7110_pwmdac_set_enable(dev, false); ++} ++ ++static int jh7110_pwmdac_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); ++ struct snd_soc_dai_link *dai_link = rtd->dai_link; ++ ++ dai_link->stop_dma_first = 1; ++ ++ return 0; ++} ++ ++static int jh7110_pwmdac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ unsigned long core_clk_rate; ++ int ret; ++ struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev); ++ ++ switch (params_rate(params)) { ++ case 8000: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_3; ++ core_clk_rate = 6144000; ++ break; ++ case 11025: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_2; ++ core_clk_rate = 5644800; ++ break; ++ case 16000: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_3; ++ core_clk_rate = 12288000; ++ break; ++ case 22050: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_1; ++ core_clk_rate = 5644800; ++ break; ++ case 32000: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_1; ++ core_clk_rate = 8192000; ++ break; ++ case 44100: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_1; ++ core_clk_rate = 11289600; ++ break; ++ case 48000: ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_1; ++ core_clk_rate = 12288000; ++ break; ++ default: ++ dev_err(dai->dev, "%d rate not supported\n", ++ params_rate(params)); ++ return -EINVAL; ++ } ++ ++ switch (params_channels(params)) { ++ case 1: ++ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ case 2: ++ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ default: ++ dev_err(dai->dev, "%d channels not supported\n", ++ params_channels(params)); ++ return -EINVAL; ++ } ++ ++ /* ++ * The clock rate always rounds down when using clk_set_rate() ++ * so increase the rate a bit ++ */ ++ core_clk_rate += 64; ++ jh7110_pwmdac_set(dev); ++ ++ ret = clk_set_rate(dev->clks[1].clk, core_clk_rate); ++ if (ret) { ++ dev_err(dai->dev, ++ "failed to set rate %lu for core clock\n", ++ core_clk_rate); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int jh7110_pwmdac_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct jh7110_pwmdac_dev *dev = snd_soc_dai_get_drvdata(dai); ++ int ret = 0; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ jh7110_pwmdac_set(dev); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ jh7110_pwmdac_stop(dev); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int jh7110_pwmdac_crg_enable(struct jh7110_pwmdac_dev *dev, bool enable) ++{ ++ int ret; ++ ++ if (enable) { ++ ret = clk_bulk_prepare_enable(ARRAY_SIZE(dev->clks), dev->clks); ++ if (ret) { ++ dev_err(dev->dev, "failed to enable pwmdac clocks\n"); ++ return ret; ++ } ++ ++ ret = reset_control_deassert(dev->rst_apb); ++ if (ret) { ++ dev_err(dev->dev, "failed to deassert pwmdac apb reset\n"); ++ goto err_rst_apb; ++ } ++ } else { ++ clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks); ++ } ++ ++ return 0; ++ ++err_rst_apb: ++ clk_bulk_disable_unprepare(ARRAY_SIZE(dev->clks), dev->clks); ++ ++ return ret; ++} ++ ++static int jh7110_pwmdac_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct jh7110_pwmdac_dev *dev = dev_get_drvdata(dai->dev); ++ ++ dev->play_dma_data.addr = dev->mapbase + JH7110_PWMDAC_WDATA; ++ dev->play_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ dev->play_dma_data.fifo_size = 1; ++ dev->play_dma_data.maxburst = 16; ++ ++ snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, NULL); ++ snd_soc_dai_set_drvdata(dai, dev); ++ ++ return 0; ++} ++ ++#define JH7110_PWMDAC_ENUM_DECL(xname, xinfo, xget, xput) \ ++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ ++ .info = xinfo, .get = xget, .put = xput,} ++ ++static const struct snd_kcontrol_new jh7110_pwmdac_snd_controls[] = { ++ JH7110_PWMDAC_ENUM_DECL("shift", jh7110_pwmdac_shift_info, ++ jh7110_pwmdac_shift_get, ++ jh7110_pwmdac_shift_put), ++ JH7110_PWMDAC_ENUM_DECL("duty_cycle", jh7110_pwmdac_duty_cycle_info, ++ jh7110_pwmdac_duty_cycle_get, ++ jh7110_pwmdac_duty_cycle_put), ++ JH7110_PWMDAC_ENUM_DECL("data_change", jh7110_pwmdac_data_change_info, ++ jh7110_pwmdac_data_change_get, ++ jh7110_pwmdac_data_change_put), ++ JH7110_PWMDAC_ENUM_DECL("data_mode", jh7110_pwmdac_data_mode_info, ++ jh7110_pwmdac_data_mode_get, ++ jh7110_pwmdac_data_mode_put), ++ JH7110_PWMDAC_ENUM_DECL("data_shift", jh7110_pwmdac_data_shift_info, ++ jh7110_pwmdac_data_shift_get, ++ jh7110_pwmdac_data_shift_put), ++}; ++ ++static int jh7110_pwmdac_component_probe(struct snd_soc_component *component) ++{ ++ snd_soc_add_component_controls(component, jh7110_pwmdac_snd_controls, ++ ARRAY_SIZE(jh7110_pwmdac_snd_controls)); ++ return 0; ++} ++ ++static const struct snd_soc_dai_ops jh7110_pwmdac_dai_ops = { ++ .startup = jh7110_pwmdac_startup, ++ .hw_params = jh7110_pwmdac_hw_params, ++ .trigger = jh7110_pwmdac_trigger, ++}; ++ ++static const struct snd_soc_component_driver jh7110_pwmdac_component = { ++ .name = "jh7110-pwmdac", ++ .probe = jh7110_pwmdac_component_probe, ++}; ++ ++static struct snd_soc_dai_driver jh7110_pwmdac_dai = { ++ .name = "jh7110-pwmdac", ++ .id = 0, ++ .probe = jh7110_pwmdac_dai_probe, ++ .playback = { ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ }, ++ .ops = &jh7110_pwmdac_dai_ops, ++}; ++ ++static int jh7110_pwmdac_runtime_suspend(struct device *dev) ++{ ++ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); ++ ++ return jh7110_pwmdac_crg_enable(pwmdac, false); ++} ++ ++static int jh7110_pwmdac_runtime_resume(struct device *dev) ++{ ++ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); ++ ++ return jh7110_pwmdac_crg_enable(pwmdac, true); ++} ++ ++static int jh7110_pwmdac_system_suspend(struct device *dev) ++{ ++ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); ++ ++ /* save the CTRL register value */ ++ pwmdac->saved_ctrl = jh7110_pwmdac_read_reg(pwmdac->base, ++ JH7110_PWMDAC_CTRL); ++ return pm_runtime_force_suspend(dev); ++} ++ ++static int jh7110_pwmdac_system_resume(struct device *dev) ++{ ++ struct jh7110_pwmdac_dev *pwmdac = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = pm_runtime_force_resume(dev); ++ if (ret) ++ return ret; ++ ++ /* restore the CTRL register value */ ++ jh7110_pwmdac_write_reg(pwmdac->base, JH7110_PWMDAC_CTRL, ++ pwmdac->saved_ctrl); ++ return 0; ++} ++ ++static const struct dev_pm_ops jh7110_pwmdac_pm_ops = { ++ RUNTIME_PM_OPS(jh7110_pwmdac_runtime_suspend, ++ jh7110_pwmdac_runtime_resume, NULL) ++ SYSTEM_SLEEP_PM_OPS(jh7110_pwmdac_system_suspend, ++ jh7110_pwmdac_system_resume) ++}; ++ ++static int jh7110_pwmdac_probe(struct platform_device *pdev) ++{ ++ struct jh7110_pwmdac_dev *dev; ++ struct resource *res; ++ int ret; ++ ++ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ ++ dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ if (IS_ERR(dev->base)) ++ return PTR_ERR(dev->base); ++ ++ dev->mapbase = res->start; ++ ++ dev->clks[0].id = "apb"; ++ dev->clks[1].id = "core"; ++ ++ ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(dev->clks), dev->clks); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to get pwmdac clocks\n"); ++ return ret; ++ } ++ ++ dev->rst_apb = devm_reset_control_get_exclusive(&pdev->dev, NULL); ++ if (IS_ERR(dev->rst_apb)) { ++ dev_err(&pdev->dev, "failed to get pwmdac apb reset\n"); ++ return PTR_ERR(dev->rst_apb); ++ } ++ ++ dev->dev = &pdev->dev; ++ dev->shift = PWMDAC_SHIFT_8; ++ dev->duty_cycle = PWMDAC_CYCLE_CENTER; ++ dev->cnt_n = PWMDAC_SAMPLE_CNT_1; ++ dev->data_change = NO_CHANGE; ++ dev->data_mode = INVERTER_DATA_MSB; ++ dev->data_shift = PWMDAC_DATA_LEFT_SHIFT_BIT_0; ++ ++ dev_set_drvdata(&pdev->dev, dev); ++ ret = devm_snd_soc_register_component(&pdev->dev, ++ &jh7110_pwmdac_component, ++ &jh7110_pwmdac_dai, 1); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register dai\n"); ++ return ret; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to register pcm\n"); ++ return ret; ++ } ++ ++ pm_runtime_enable(dev->dev); ++ if (!pm_runtime_enabled(&pdev->dev)) { ++ ret = jh7110_pwmdac_runtime_resume(&pdev->dev); ++ if (ret) ++ goto err_pm_disable; ++ } ++ ++ return 0; ++ ++err_pm_disable: ++ pm_runtime_disable(&pdev->dev); ++ ++ return ret; ++} ++ ++static int jh7110_pwmdac_remove(struct platform_device *pdev) ++{ ++ pm_runtime_disable(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id jh7110_pwmdac_of_match[] = { ++ { .compatible = "starfive,jh7110-pwmdac" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, jh7110_pwmdac_of_match); ++ ++static struct platform_driver jh7110_pwmdac_driver = { ++ .driver = { ++ .name = "jh7110-pwmdac", ++ .of_match_table = jh7110_pwmdac_of_match, ++ .pm = pm_ptr(&jh7110_pwmdac_pm_ops), ++ }, ++ .probe = jh7110_pwmdac_probe, ++ .remove = jh7110_pwmdac_remove, ++}; ++module_platform_driver(jh7110_pwmdac_driver); ++ ++MODULE_AUTHOR("Jenny Zhang"); ++MODULE_AUTHOR("Curry Zhang"); ++MODULE_AUTHOR("Xingyu Wu "); ++MODULE_AUTHOR("Hal Feng "); ++MODULE_DESCRIPTION("StarFive JH7110 PWM-DAC driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0033-dt-bindings-power-Add-power-domain-header-for-JH7110.patch b/srcpkgs/linux6.4/patches/0033-dt-bindings-power-Add-power-domain-header-for-JH7110.patch new file mode 100644 index 0000000000000..25a9ebd46f9ff --- /dev/null +++ b/srcpkgs/linux6.4/patches/0033-dt-bindings-power-Add-power-domain-header-for-JH7110.patch @@ -0,0 +1,36 @@ +From 15ff9b7ba72359d584ff41f381b81d373f5adc47 Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Thu, 18 May 2023 23:01:59 -0700 +Subject: [PATCH 33/72] dt-bindings: power: Add power-domain header for JH7110 + +Add power-domain header for JH7110 SoC, it can use to operate dphy +power. + +Signed-off-by: Changhuang Liang +--- + include/dt-bindings/power/starfive,jh7110-pmu.h | 5 ++++- + 1 file changed, 4 insertions(+), 1 deletion(-) + +diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h +index 132bfe401fc8..341e2a0676ba 100644 +--- a/include/dt-bindings/power/starfive,jh7110-pmu.h ++++ b/include/dt-bindings/power/starfive,jh7110-pmu.h +@@ -1,6 +1,6 @@ + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + /* +- * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: Walker Chen + */ + #ifndef __DT_BINDINGS_POWER_JH7110_POWER_H__ +@@ -14,4 +14,7 @@ + #define JH7110_PD_ISP 5 + #define JH7110_PD_VENC 6 + ++#define JH7110_PD_DPHY_TX 0 ++#define JH7110_PD_DPHY_RX 1 ++ + #endif +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0034-soc-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch b/srcpkgs/linux6.4/patches/0034-soc-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch new file mode 100644 index 0000000000000..98d3a0b44c639 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0034-soc-starfive-Replace-SOC_STARFIVE-with-ARCH_STARFIVE.patch @@ -0,0 +1,32 @@ +From 442a639c06410455a19c7c7496fb79f9f37252c6 Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Thu, 18 May 2023 23:02:00 -0700 +Subject: [PATCH 34/72] soc: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE + +Using ARCH_FOO symbol is preferred than SOC_FOO. + +Reviewed-by: Conor Dooley +Reviewed-by: Walker Chen +Signed-off-by: Changhuang Liang +--- + drivers/soc/starfive/Kconfig | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig +index bdb96dc4c989..1e9b0c414fec 100644 +--- a/drivers/soc/starfive/Kconfig ++++ b/drivers/soc/starfive/Kconfig +@@ -3,8 +3,8 @@ + config JH71XX_PMU + bool "Support PMU for StarFive JH71XX Soc" + depends on PM +- depends on SOC_STARFIVE || COMPILE_TEST +- default SOC_STARFIVE ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ default ARCH_STARFIVE + select PM_GENERIC_DOMAINS + help + Say 'y' here to enable support power domain support. +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0035-soc-starfive-Extract-JH7110-pmu-private-operations.patch b/srcpkgs/linux6.4/patches/0035-soc-starfive-Extract-JH7110-pmu-private-operations.patch new file mode 100644 index 0000000000000..e276798a03ea9 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0035-soc-starfive-Extract-JH7110-pmu-private-operations.patch @@ -0,0 +1,180 @@ +From f54790b6cd934e6b82a2eb9323ad7af0789f5650 Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Thu, 18 May 2023 23:02:01 -0700 +Subject: [PATCH 35/72] soc: starfive: Extract JH7110 pmu private operations + +Move JH7110 private operation into private data of compatible. Convenient +to add AON PMU which would not have interrupts property. + +Signed-off-by: Changhuang Liang +Reviewed-by: Walker Chen +--- + drivers/soc/starfive/jh71xx_pmu.c | 89 +++++++++++++++++++++---------- + 1 file changed, 62 insertions(+), 27 deletions(-) + +diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c +index 7d5f50d71c0d..0dbdcc0d2c91 100644 +--- a/drivers/soc/starfive/jh71xx_pmu.c ++++ b/drivers/soc/starfive/jh71xx_pmu.c +@@ -51,9 +51,17 @@ struct jh71xx_domain_info { + u8 bit; + }; + ++struct jh71xx_pmu; ++struct jh71xx_pmu_dev; ++ + struct jh71xx_pmu_match_data { + const struct jh71xx_domain_info *domain_info; + int num_domains; ++ unsigned int pmu_status; ++ int (*pmu_parse_irq)(struct platform_device *pdev, ++ struct jh71xx_pmu *pmu); ++ int (*pmu_set_state)(struct jh71xx_pmu_dev *pmd, ++ u32 mask, bool on); + }; + + struct jh71xx_pmu { +@@ -79,12 +87,12 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o + if (!mask) + return -EINVAL; + +- *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; ++ *is_on = readl(pmu->base + pmu->match_data->pmu_status) & mask; + + return 0; + } + +-static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) ++static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) + { + struct jh71xx_pmu *pmu = pmd->pmu; + unsigned long flags; +@@ -92,22 +100,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) + u32 mode; + u32 encourage_lo; + u32 encourage_hi; +- bool is_on; + int ret; + +- ret = jh71xx_pmu_get_state(pmd, mask, &is_on); +- if (ret) { +- dev_dbg(pmu->dev, "unable to get current state for %s\n", +- pmd->genpd.name); +- return ret; +- } +- +- if (is_on == on) { +- dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", +- pmd->genpd.name, on ? "en" : "dis"); +- return 0; +- } +- + spin_lock_irqsave(&pmu->lock, flags); + + /* +@@ -166,6 +160,29 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) + return 0; + } + ++static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) ++{ ++ struct jh71xx_pmu *pmu = pmd->pmu; ++ const struct jh71xx_pmu_match_data *match_data = pmu->match_data; ++ bool is_on; ++ int ret; ++ ++ ret = jh71xx_pmu_get_state(pmd, mask, &is_on); ++ if (ret) { ++ dev_dbg(pmu->dev, "unable to get current state for %s\n", ++ pmd->genpd.name); ++ return ret; ++ } ++ ++ if (is_on == on) { ++ dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", ++ pmd->genpd.name, on ? "en" : "dis"); ++ return 0; ++ } ++ ++ return match_data->pmu_set_state(pmd, mask, on); ++} ++ + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) + { + struct jh71xx_pmu_dev *pmd = container_of(genpd, +@@ -226,6 +243,25 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) + return IRQ_HANDLED; + } + ++static int jh7110_pmu_parse_irq(struct platform_device *pdev, struct jh71xx_pmu *pmu) ++{ ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ pmu->irq = platform_get_irq(pdev, 0); ++ if (pmu->irq < 0) ++ return pmu->irq; ++ ++ ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, ++ 0, pdev->name, pmu); ++ if (ret) ++ dev_err(dev, "failed to request irq\n"); ++ ++ jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); ++ ++ return 0; ++} ++ + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) + { + struct jh71xx_pmu_dev *pmd; +@@ -275,19 +311,18 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + +- pmu->irq = platform_get_irq(pdev, 0); +- if (pmu->irq < 0) +- return pmu->irq; +- +- ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, +- 0, pdev->name, pmu); +- if (ret) +- dev_err(dev, "failed to request irq\n"); ++ spin_lock_init(&pmu->lock); + + match_data = of_device_get_match_data(dev); + if (!match_data) + return -EINVAL; + ++ ret = match_data->pmu_parse_irq(pdev, pmu); ++ if (ret) { ++ dev_err(dev, "failed to parse irq\n"); ++ return ret; ++ } ++ + pmu->genpd = devm_kcalloc(dev, match_data->num_domains, + sizeof(struct generic_pm_domain *), + GFP_KERNEL); +@@ -307,9 +342,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) + } + } + +- spin_lock_init(&pmu->lock); +- jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); +- + ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data); + if (ret) { + dev_err(dev, "failed to register genpd driver: %d\n", ret); +@@ -357,6 +389,9 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = { + static const struct jh71xx_pmu_match_data jh7110_pmu = { + .num_domains = ARRAY_SIZE(jh7110_power_domains), + .domain_info = jh7110_power_domains, ++ .pmu_status = JH71XX_PMU_CURR_POWER_MODE, ++ .pmu_parse_irq = jh7110_pmu_parse_irq, ++ .pmu_set_state = jh7110_pmu_set_state, + }; + + static const struct of_device_id jh71xx_pmu_of_match[] = { +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0036-soc-starfive-Add-JH7110-AON-PMU-support.patch b/srcpkgs/linux6.4/patches/0036-soc-starfive-Add-JH7110-AON-PMU-support.patch new file mode 100644 index 0000000000000..76167e337a836 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0036-soc-starfive-Add-JH7110-AON-PMU-support.patch @@ -0,0 +1,123 @@ +From 0db61188e521cc64e39cbebba814c9b40dbe1c2b Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Thu, 18 May 2023 23:02:02 -0700 +Subject: [PATCH 36/72] soc: starfive: Add JH7110 AON PMU support + +Add AON PMU for StarFive JH7110 SoC. It can be used to turn on/off the +dphy rx/tx power switch. + +Reviewed-by: Walker Chen +Signed-off-by: Changhuang Liang +--- + drivers/soc/starfive/jh71xx_pmu.c | 57 ++++++++++++++++++++++++++++--- + 1 file changed, 52 insertions(+), 5 deletions(-) + +diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c +index 0dbdcc0d2c91..c7b474409cf7 100644 +--- a/drivers/soc/starfive/jh71xx_pmu.c ++++ b/drivers/soc/starfive/jh71xx_pmu.c +@@ -2,7 +2,7 @@ + /* + * StarFive JH71XX PMU (Power Management Unit) Controller Driver + * +- * Copyright (C) 2022 StarFive Technology Co., Ltd. ++ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + */ + + #include +@@ -24,6 +24,9 @@ + #define JH71XX_PMU_EVENT_STATUS 0x88 + #define JH71XX_PMU_INT_STATUS 0x8C + ++/* aon pmu register offset */ ++#define JH71XX_AON_PMU_SWITCH 0x00 ++ + /* sw encourage cfg */ + #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 + #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 +@@ -160,6 +163,26 @@ static int jh7110_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) + return 0; + } + ++static int jh7110_aon_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) ++{ ++ struct jh71xx_pmu *pmu = pmd->pmu; ++ unsigned long flags; ++ u32 val; ++ ++ spin_lock_irqsave(&pmu->lock, flags); ++ val = readl(pmu->base + JH71XX_AON_PMU_SWITCH); ++ ++ if (on) ++ val |= mask; ++ else ++ val &= ~mask; ++ ++ writel(val, pmu->base + JH71XX_AON_PMU_SWITCH); ++ spin_unlock_irqrestore(&pmu->lock, flags); ++ ++ return 0; ++} ++ + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) + { + struct jh71xx_pmu *pmu = pmd->pmu; +@@ -317,10 +340,12 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) + if (!match_data) + return -EINVAL; + +- ret = match_data->pmu_parse_irq(pdev, pmu); +- if (ret) { +- dev_err(dev, "failed to parse irq\n"); +- return ret; ++ if (match_data->pmu_parse_irq) { ++ ret = match_data->pmu_parse_irq(pdev, pmu); ++ if (ret) { ++ dev_err(dev, "failed to parse irq\n"); ++ return ret; ++ } + } + + pmu->genpd = devm_kcalloc(dev, match_data->num_domains, +@@ -394,10 +419,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = { + .pmu_set_state = jh7110_pmu_set_state, + }; + ++static const struct jh71xx_domain_info jh7110_aon_power_domains[] = { ++ [JH7110_PD_DPHY_TX] = { ++ .name = "DPHY-TX", ++ .bit = 30, ++ }, ++ [JH7110_PD_DPHY_RX] = { ++ .name = "DPHY-RX", ++ .bit = 31, ++ }, ++}; ++ ++static const struct jh71xx_pmu_match_data jh7110_aon_pmu = { ++ .num_domains = ARRAY_SIZE(jh7110_aon_power_domains), ++ .domain_info = jh7110_aon_power_domains, ++ .pmu_status = JH71XX_AON_PMU_SWITCH, ++ .pmu_set_state = jh7110_aon_pmu_set_state, ++}; ++ + static const struct of_device_id jh71xx_pmu_of_match[] = { + { + .compatible = "starfive,jh7110-pmu", + .data = (void *)&jh7110_pmu, ++ }, { ++ .compatible = "starfive,jh7110-aon-syscon", ++ .data = (void *)&jh7110_aon_pmu, + }, { + /* sentinel */ + } +@@ -414,5 +460,6 @@ static struct platform_driver jh71xx_pmu_driver = { + builtin_platform_driver(jh71xx_pmu_driver); + + MODULE_AUTHOR("Walker Chen "); ++MODULE_AUTHOR("Changhuang Liang "); + MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); + MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0037-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch b/srcpkgs/linux6.4/patches/0037-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch new file mode 100644 index 0000000000000..98c9baac04b37 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0037-dt-bindings-phy-Add-starfive-jh7110-dphy-rx.patch @@ -0,0 +1,94 @@ +From 3394fdd665dbc419e4efa75285adcf45ce036943 Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Mon, 29 May 2023 05:15:01 -0700 +Subject: [PATCH 37/72] dt-bindings: phy: Add starfive,jh7110-dphy-rx + +StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on +a M31 IP. Add a binding for it. + +Signed-off-by: Changhuang Liang +--- + .../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++ + 1 file changed, 71 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml + +diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml +new file mode 100644 +index 000000000000..46fd370188e8 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml +@@ -0,0 +1,71 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive SoC MIPI D-PHY Rx Controller ++ ++maintainers: ++ - Jack Zhu ++ - Changhuang Liang ++ ++description: ++ The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer ++ CSI camera data. ++ ++properties: ++ compatible: ++ const: starfive,jh7110-dphy-rx ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: config clock ++ - description: reference clock ++ - description: escape mode transmit clock ++ ++ clock-names: ++ items: ++ - const: cfg ++ - const: ref ++ - const: tx ++ ++ resets: ++ items: ++ - description: DPHY_HW reset ++ - description: DPHY_B09_ALWAYS_ON reset ++ ++ power-domains: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - resets ++ - power-domains ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@19820000 { ++ compatible = "starfive,jh7110-dphy-rx"; ++ reg = <0x19820000 0x10000>; ++ clocks = <&ispcrg 3>, ++ <&ispcrg 4>, ++ <&ispcrg 5>; ++ clock-names = "cfg", "ref", "tx"; ++ resets = <&ispcrg 2>, ++ <&ispcrg 3>; ++ power-domains = <&dphy_pwrc 1>; ++ #phy-cells = <0>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0038-phy-starfive-Add-mipi-dphy-rx-support.patch b/srcpkgs/linux6.4/patches/0038-phy-starfive-Add-mipi-dphy-rx-support.patch new file mode 100644 index 0000000000000..e3865a4092620 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0038-phy-starfive-Add-mipi-dphy-rx-support.patch @@ -0,0 +1,380 @@ +From e836f0941c35e285b4e5b9e3e413fdac8a903047 Mon Sep 17 00:00:00 2001 +From: Changhuang Liang +Date: Mon, 29 May 2023 05:15:02 -0700 +Subject: [PATCH 38/72] phy: starfive: Add mipi dphy rx support + +Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to +transfer CSI camera data. + +Signed-off-by: Changhuang Liang +--- + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/starfive/Kconfig | 13 + + drivers/phy/starfive/Makefile | 2 + + drivers/phy/starfive/phy-starfive-dphy-rx.c | 300 ++++++++++++++++++++ + 5 files changed, 317 insertions(+) + create mode 100644 drivers/phy/starfive/Kconfig + create mode 100644 drivers/phy/starfive/Makefile + create mode 100644 drivers/phy/starfive/phy-starfive-dphy-rx.c + +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index f46e3148d286..0000149edbc4 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig" + source "drivers/phy/samsung/Kconfig" + source "drivers/phy/socionext/Kconfig" + source "drivers/phy/st/Kconfig" ++source "drivers/phy/starfive/Kconfig" + source "drivers/phy/sunplus/Kconfig" + source "drivers/phy/tegra/Kconfig" + source "drivers/phy/ti/Kconfig" +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index 54f312c10a40..fb3dc9de6111 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -31,6 +31,7 @@ obj-y += allwinner/ \ + samsung/ \ + socionext/ \ + st/ \ ++ starfive/ \ + sunplus/ \ + tegra/ \ + ti/ \ +diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig +new file mode 100644 +index 000000000000..f989b8ff8bcb +--- /dev/null ++++ b/drivers/phy/starfive/Kconfig +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++# ++# Phy drivers for StarFive platforms ++# ++ ++config PHY_STARFIVE_DPHY_RX ++ tristate "StarFive D-PHY RX Support" ++ select GENERIC_PHY ++ select GENERIC_PHY_MIPI_DPHY ++ help ++ Choose this option if you have a StarFive D-PHY in your ++ system. If M is selected, the module will be called ++ phy-starfive-dphy-rx. +diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile +new file mode 100644 +index 000000000000..7ec576cb30ae +--- /dev/null ++++ b/drivers/phy/starfive/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o +diff --git a/drivers/phy/starfive/phy-starfive-dphy-rx.c b/drivers/phy/starfive/phy-starfive-dphy-rx.c +new file mode 100644 +index 000000000000..6974ed904d0d +--- /dev/null ++++ b/drivers/phy/starfive/phy-starfive-dphy-rx.c +@@ -0,0 +1,300 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * DPHY driver for the StarFive JH7110 SoC ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define STF_DPHY_APBCFGSAIF_SYSCFG(x) (x) ++ ++#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN BIT(6) ++#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN GENMASK(12, 7) ++#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN BIT(19) ++#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN GENMASK(25, 20) ++ ++#define STF_DPHY_DATA_BUS16_8 BIT(8) ++#define STF_DPHY_DEBUG_MODE_SEL GENMASK(15, 9) ++ ++#define STF_DPHY_ENABLE_CLK BIT(6) ++#define STF_DPHY_ENABLE_CLK1 BIT(7) ++#define STF_DPHY_ENABLE_LAN0 BIT(8) ++#define STF_DPHY_ENABLE_LAN1 BIT(9) ++#define STF_DPHY_ENABLE_LAN2 BIT(10) ++#define STF_DPHY_ENABLE_LAN3 BIT(11) ++#define STF_DPHY_GPI_EN GENMASK(17, 12) ++#define STF_DPHY_HS_FREQ_CHANGE_CLK BIT(18) ++#define STF_DPHY_HS_FREQ_CHANGE_CLK1 BIT(19) ++#define STF_DPHY_LANE_SWAP_CLK GENMASK(22, 20) ++#define STF_DPHY_LANE_SWAP_CLK1 GENMASK(25, 23) ++#define STF_DPHY_LANE_SWAP_LAN0 GENMASK(28, 26) ++#define STF_DPHY_LANE_SWAP_LAN1 GENMASK(31, 29) ++ ++#define STF_DPHY_LANE_SWAP_LAN2 GENMASK(2, 0) ++#define STF_DPHY_LANE_SWAP_LAN3 GENMASK(5, 3) ++#define STF_DPHY_MP_TEST_EN BIT(6) ++#define STF_DPHY_MP_TEST_MODE_SEL GENMASK(11, 7) ++#define STF_DPHY_PLL_CLK_SEL GENMASK(21, 12) ++#define STF_DPHY_PRECOUNTER_IN_CLK GENMASK(29, 22) ++ ++#define STF_DPHY_PRECOUNTER_IN_CLK1 GENMASK(7, 0) ++#define STF_DPHY_PRECOUNTER_IN_LAN0 GENMASK(15, 8) ++#define STF_DPHY_PRECOUNTER_IN_LAN1 GENMASK(23, 16) ++#define STF_DPHY_PRECOUNTER_IN_LAN2 GENMASK(31, 24) ++ ++#define STF_DPHY_PRECOUNTER_IN_LAN3 GENMASK(7, 0) ++#define STF_DPHY_RX_1C2C_SEL BIT(8) ++ ++#define STF_MAP_LANES_NUM 6 ++ ++struct regval { ++ u32 addr; ++ u32 val; ++}; ++ ++struct stf_dphy_info { ++ /** ++ * @maps: ++ * ++ * Physical lanes and logic lanes mapping table. ++ * ++ * The default order is: ++ * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1] ++ */ ++ u8 maps[STF_MAP_LANES_NUM]; ++}; ++ ++struct stf_dphy { ++ struct device *dev; ++ void __iomem *regs; ++ struct clk *cfg_clk; ++ struct clk *ref_clk; ++ struct clk *tx_clk; ++ struct reset_control *rstc; ++ struct regulator *mipi_0p9; ++ struct phy *phy; ++ const struct stf_dphy_info *info; ++}; ++ ++static const struct regval stf_dphy_init_list[] = { ++ { STF_DPHY_APBCFGSAIF_SYSCFG(4), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(8), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(12), 0x0000fff0 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(16), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(20), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(24), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(28), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(32), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(36), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(48), 0x24000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(52), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(56), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(60), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(64), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(68), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(72), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(76), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(80), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(84), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(88), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(92), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(96), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(100), 0x02000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(104), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(108), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(112), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(116), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(120), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(124), 0x0000000c }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(128), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(132), 0xcc500000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(136), 0x000000cc }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(140), 0x00000000 }, ++ { STF_DPHY_APBCFGSAIF_SYSCFG(144), 0x00000000 }, ++}; ++ ++static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts) ++{ ++ struct stf_dphy *dphy = phy_get_drvdata(phy); ++ const struct stf_dphy_info *info = dphy->info; ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(stf_dphy_init_list); i++) ++ writel(stf_dphy_init_list[i].val, ++ dphy->regs + stf_dphy_init_list[i].addr); ++ ++ writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) | ++ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) | ++ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) | ++ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(0)); ++ ++ writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) | ++ FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(184)); ++ ++ writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) | ++ FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) | ++ FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) | ++ FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) | ++ FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) | ++ FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) | ++ FIELD_PREP(STF_DPHY_GPI_EN, 0) | ++ FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK, 0) | ++ FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK1, 0) | ++ FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) | ++ FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) | ++ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) | ++ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188)); ++ ++ writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) | ++ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, info->maps[4]) | ++ FIELD_PREP(STF_DPHY_MP_TEST_EN, 0) | ++ FIELD_PREP(STF_DPHY_MP_TEST_MODE_SEL, 0) | ++ FIELD_PREP(STF_DPHY_PLL_CLK_SEL, 0x37c) | ++ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192)); ++ ++ writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) | ++ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) | ++ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) | ++ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196)); ++ ++ writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7) | ++ FIELD_PREP(STF_DPHY_RX_1C2C_SEL, 0), ++ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200)); ++ ++ return 0; ++} ++ ++static int stf_dphy_power_on(struct phy *phy) ++{ ++ struct stf_dphy *dphy = phy_get_drvdata(phy); ++ int ret; ++ ++ pm_runtime_get_sync(dphy->dev); ++ ++ ret = regulator_enable(dphy->mipi_0p9); ++ if (ret) ++ return ret; ++ ++ clk_set_rate(dphy->cfg_clk, 99000000); ++ clk_set_rate(dphy->ref_clk, 49500000); ++ clk_set_rate(dphy->tx_clk, 19800000); ++ reset_control_deassert(dphy->rstc); ++ ++ return 0; ++} ++ ++static int stf_dphy_power_off(struct phy *phy) ++{ ++ struct stf_dphy *dphy = phy_get_drvdata(phy); ++ ++ reset_control_assert(dphy->rstc); ++ ++ regulator_disable(dphy->mipi_0p9); ++ ++ pm_runtime_put_sync(dphy->dev); ++ ++ return 0; ++} ++ ++static const struct phy_ops stf_dphy_ops = { ++ .configure = stf_dphy_configure, ++ .power_on = stf_dphy_power_on, ++ .power_off = stf_dphy_power_off, ++}; ++ ++static int stf_dphy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider; ++ struct stf_dphy *dphy; ++ ++ dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); ++ if (!dphy) ++ return -ENOMEM; ++ ++ dphy->info = of_device_get_match_data(&pdev->dev); ++ ++ dev_set_drvdata(&pdev->dev, dphy); ++ dphy->dev = &pdev->dev; ++ ++ dphy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(dphy->regs)) ++ return PTR_ERR(dphy->regs); ++ ++ dphy->cfg_clk = devm_clk_get(&pdev->dev, "cfg"); ++ if (IS_ERR(dphy->cfg_clk)) ++ return PTR_ERR(dphy->cfg_clk); ++ ++ dphy->ref_clk = devm_clk_get(&pdev->dev, "ref"); ++ if (IS_ERR(dphy->ref_clk)) ++ return PTR_ERR(dphy->ref_clk); ++ ++ dphy->tx_clk = devm_clk_get(&pdev->dev, "tx"); ++ if (IS_ERR(dphy->tx_clk)) ++ return PTR_ERR(dphy->tx_clk); ++ ++ dphy->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); ++ if (IS_ERR(dphy->rstc)) ++ return PTR_ERR(dphy->rstc); ++ ++ dphy->mipi_0p9 = devm_regulator_get(&pdev->dev, "mipi_0p9"); ++ if (IS_ERR(dphy->mipi_0p9)) ++ return PTR_ERR(dphy->mipi_0p9); ++ ++ dphy->phy = devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops); ++ if (IS_ERR(dphy->phy)) { ++ dev_err(&pdev->dev, "Failed to create PHY\n"); ++ return PTR_ERR(dphy->phy); ++ } ++ ++ pm_runtime_enable(&pdev->dev); ++ ++ phy_set_drvdata(dphy->phy, dphy); ++ phy_provider = devm_of_phy_provider_register(&pdev->dev, ++ of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct stf_dphy_info starfive_dphy_info = { ++ .maps = {4, 0, 1, 2, 3, 5}, ++}; ++ ++static const struct of_device_id stf_dphy_dt_ids[] = { ++ { ++ .compatible = "starfive,jh7110-dphy-rx", ++ .data = &starfive_dphy_info, ++ }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids); ++ ++static struct platform_driver stf_dphy_driver = { ++ .probe = stf_dphy_probe, ++ .driver = { ++ .name = "starfive-dphy-rx", ++ .of_match_table = stf_dphy_dt_ids, ++ }, ++}; ++module_platform_driver(stf_dphy_driver); ++ ++MODULE_AUTHOR("Jack Zhu "); ++MODULE_AUTHOR("Changhuang Liang "); ++MODULE_DESCRIPTION("StarFive DPHY RX driver"); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0039-media-dt-bindings-cadence-csi2rx-Convert-to-DT-schem.patch b/srcpkgs/linux6.4/patches/0039-media-dt-bindings-cadence-csi2rx-Convert-to-DT-schem.patch new file mode 100644 index 0000000000000..878f9e1d9baa4 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0039-media-dt-bindings-cadence-csi2rx-Convert-to-DT-schem.patch @@ -0,0 +1,315 @@ +From 0dcb113de2559fc354c37fccca58bfa7cf23fe06 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Tue, 23 May 2023 16:56:22 +0800 +Subject: [PATCH 39/72] media: dt-bindings: cadence-csi2rx: Convert to DT + schema + +Convert DT bindings document for Cadence MIPI-CSI2 RX controller to +DT schema format. + +For compatible, new compatibles should not be messed with conversion, +but the original binding did not specify any SoC-specific compatible +string, so add the StarFive compatible string. + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + .../devicetree/bindings/media/cdns,csi2rx.txt | 100 ---------- + .../bindings/media/cdns,csi2rx.yaml | 177 ++++++++++++++++++ + 2 files changed, 177 insertions(+), 100 deletions(-) + delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt + create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml + +diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt +deleted file mode 100644 +index 6b02a0657ad9..000000000000 +--- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt ++++ /dev/null +@@ -1,100 +0,0 @@ +-Cadence MIPI-CSI2 RX controller +-=============================== +- +-The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI +-lanes in input, and 4 different pixel streams in output. +- +-Required properties: +- - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible +- - reg: base address and size of the memory mapped region +- - clocks: phandles to the clocks driving the controller +- - clock-names: must contain: +- * sys_clk: main clock +- * p_clk: register bank clock +- * pixel_if[0-3]_clk: pixel stream output clock, one for each stream +- implemented in hardware, between 0 and 3 +- +-Optional properties: +- - phys: phandle to the external D-PHY, phy-names must be provided +- - phy-names: must contain "dphy", if the implementation uses an +- external D-PHY +- +-Required subnodes: +- - ports: A ports node with one port child node per device input and output +- port, in accordance with the video interface bindings defined in +- Documentation/devicetree/bindings/media/video-interfaces.txt. The +- port nodes are numbered as follows: +- +- Port Description +- ----------------------------- +- 0 CSI-2 input +- 1 Stream 0 output +- 2 Stream 1 output +- 3 Stream 2 output +- 4 Stream 3 output +- +- The stream output port nodes are optional if they are not +- connected to anything at the hardware level or implemented +- in the design.Since there is only one endpoint per port, +- the endpoints are not numbered. +- +- +-Example: +- +-csi2rx: csi-bridge@0d060000 { +- compatible = "cdns,csi2rx"; +- reg = <0x0d060000 0x1000>; +- clocks = <&byteclock>, <&byteclock> +- <&coreclock>, <&coreclock>, +- <&coreclock>, <&coreclock>; +- clock-names = "sys_clk", "p_clk", +- "pixel_if0_clk", "pixel_if1_clk", +- "pixel_if2_clk", "pixel_if3_clk"; +- +- ports { +- #address-cells = <1>; +- #size-cells = <0>; +- +- port@0 { +- reg = <0>; +- +- csi2rx_in_sensor: endpoint { +- remote-endpoint = <&sensor_out_csi2rx>; +- clock-lanes = <0>; +- data-lanes = <1 2>; +- }; +- }; +- +- port@1 { +- reg = <1>; +- +- csi2rx_out_grabber0: endpoint { +- remote-endpoint = <&grabber0_in_csi2rx>; +- }; +- }; +- +- port@2 { +- reg = <2>; +- +- csi2rx_out_grabber1: endpoint { +- remote-endpoint = <&grabber1_in_csi2rx>; +- }; +- }; +- +- port@3 { +- reg = <3>; +- +- csi2rx_out_grabber2: endpoint { +- remote-endpoint = <&grabber2_in_csi2rx>; +- }; +- }; +- +- port@4 { +- reg = <4>; +- +- csi2rx_out_grabber3: endpoint { +- remote-endpoint = <&grabber3_in_csi2rx>; +- }; +- }; +- }; +-}; +diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml +new file mode 100644 +index 000000000000..aba1191b3e77 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml +@@ -0,0 +1,177 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Cadence MIPI-CSI2 RX controller ++ ++maintainers: ++ - Maxime Ripard ++ ++description: ++ The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI ++ lanes in input, and 4 different pixel streams in output. ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - starfive,jh7110-csi2rx ++ - const: cdns,csi2rx ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ items: ++ - description: CSI2Rx system clock ++ - description: Gated Register bank clock for APB interface ++ - description: pixel Clock for Stream interface 0 ++ - description: pixel Clock for Stream interface 1 ++ - description: pixel Clock for Stream interface 2 ++ - description: pixel Clock for Stream interface 3 ++ ++ clock-names: ++ items: ++ - const: sys_clk ++ - const: p_clk ++ - const: pixel_if0_clk ++ - const: pixel_if1_clk ++ - const: pixel_if2_clk ++ - const: pixel_if3_clk ++ ++ phys: ++ maxItems: 1 ++ description: MIPI D-PHY ++ ++ phy-names: ++ items: ++ - const: dphy ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/$defs/port-base ++ unevaluatedProperties: false ++ description: ++ Input port node, single endpoint describing the CSI-2 transmitter. ++ ++ properties: ++ endpoint: ++ $ref: video-interfaces.yaml# ++ unevaluatedProperties: false ++ ++ properties: ++ bus-type: ++ const: 4 ++ ++ clock-lanes: ++ const: 0 ++ ++ data-lanes: ++ minItems: 1 ++ maxItems: 4 ++ items: ++ maximum: 4 ++ ++ required: ++ - data-lanes ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Stream 0 Output port node ++ ++ port@2: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Stream 1 Output port node ++ ++ port@3: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Stream 2 Output port node ++ ++ port@4: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Stream 3 Output port node ++ ++ required: ++ - port@0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - ports ++ ++additionalProperties: false ++ ++examples: ++ - | ++ csi@d060000 { ++ compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; ++ reg = <0x0d060000 0x1000>; ++ clocks = <&byteclock 7>, <&byteclock 6>, ++ <&coreclock 8>, <&coreclock 9>, ++ <&coreclock 10>, <&coreclock 11>; ++ clock-names = "sys_clk", "p_clk", ++ "pixel_if0_clk", "pixel_if1_clk", ++ "pixel_if2_clk", "pixel_if3_clk"; ++ phys = <&csi_phy>; ++ phy-names = "dphy"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ csi2rx_in_sensor: endpoint { ++ remote-endpoint = <&sensor_out_csi2rx>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ csi2rx_out_grabber0: endpoint { ++ remote-endpoint = <&grabber0_in_csi2rx>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ csi2rx_out_grabber1: endpoint { ++ remote-endpoint = <&grabber1_in_csi2rx>; ++ }; ++ }; ++ ++ port@3 { ++ reg = <3>; ++ ++ csi2rx_out_grabber2: endpoint { ++ remote-endpoint = <&grabber2_in_csi2rx>; ++ }; ++ }; ++ ++ port@4 { ++ reg = <4>; ++ ++ csi2rx_out_grabber3: endpoint { ++ remote-endpoint = <&grabber3_in_csi2rx>; ++ }; ++ }; ++ }; ++ }; ++ ++... +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0040-media-dt-bindings-cadence-csi2rx-Add-resets-property.patch b/srcpkgs/linux6.4/patches/0040-media-dt-bindings-cadence-csi2rx-Add-resets-property.patch new file mode 100644 index 0000000000000..52fdd7c6559e3 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0040-media-dt-bindings-cadence-csi2rx-Add-resets-property.patch @@ -0,0 +1,59 @@ +From ce9b8abfc45d1dbeecd408156a4bd39dafdb48c5 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Tue, 23 May 2023 16:56:23 +0800 +Subject: [PATCH 40/72] media: dt-bindings: cadence-csi2rx: Add resets property + +Add resets property for Cadence MIPI-CSI2 RX controller + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + .../bindings/media/cdns,csi2rx.yaml | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml +index aba1191b3e77..30a335b10762 100644 +--- a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml ++++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml +@@ -41,6 +41,24 @@ properties: + - const: pixel_if2_clk + - const: pixel_if3_clk + ++ resets: ++ items: ++ - description: CSI2Rx system reset ++ - description: Gated Register bank reset for APB interface ++ - description: pixel reset for Stream interface 0 ++ - description: pixel reset for Stream interface 1 ++ - description: pixel reset for Stream interface 2 ++ - description: pixel reset for Stream interface 3 ++ ++ reset-names: ++ items: ++ - const: sys ++ - const: reg_bank ++ - const: pixel_if0 ++ - const: pixel_if1 ++ - const: pixel_if2 ++ - const: pixel_if3 ++ + phys: + maxItems: 1 + description: MIPI D-PHY +@@ -123,6 +141,12 @@ examples: + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; ++ resets = <&bytereset 9>, <&bytereset 4>, ++ <&corereset 5>, <&corereset 6>, ++ <&corereset 7>, <&corereset 8>; ++ reset-names = "sys", "reg_bank", ++ "pixel_if0", "pixel_if1", ++ "pixel_if2", "pixel_if3"; + phys = <&csi_phy>; + phy-names = "dphy"; + +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0041-media-cadence-Add-operation-on-reset.patch b/srcpkgs/linux6.4/patches/0041-media-cadence-Add-operation-on-reset.patch new file mode 100644 index 0000000000000..d41ba5f45afe9 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0041-media-cadence-Add-operation-on-reset.patch @@ -0,0 +1,134 @@ +From 73f8619221c28e90244c4597ddc9bca1e846480d Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Tue, 23 May 2023 16:56:24 +0800 +Subject: [PATCH 41/72] media: cadence: Add operation on reset + +Add operation on reset for Cadence MIPI-CSI2 RX Controller. + +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + drivers/media/platform/cadence/cdns-csi2rx.c | 40 +++++++++++++++++--- + 1 file changed, 35 insertions(+), 5 deletions(-) + +diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c +index 9755d1c8ceb9..c9b80ac5cca5 100644 +--- a/drivers/media/platform/cadence/cdns-csi2rx.c ++++ b/drivers/media/platform/cadence/cdns-csi2rx.c +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + + #include +@@ -68,6 +69,9 @@ struct csi2rx_priv { + struct clk *sys_clk; + struct clk *p_clk; + struct clk *pixel_clk[CSI2RX_STREAMS_MAX]; ++ struct reset_control *sys_rst; ++ struct reset_control *p_rst; ++ struct reset_control *pixel_rst[CSI2RX_STREAMS_MAX]; + struct phy *dphy; + + u8 lanes[CSI2RX_LANES_MAX]; +@@ -112,6 +116,7 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) + if (ret) + return ret; + ++ reset_control_deassert(csi2rx->p_rst); + csi2rx_reset(csi2rx); + + reg = csi2rx->num_lanes << 8; +@@ -154,6 +159,8 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) + if (ret) + goto err_disable_pixclk; + ++ reset_control_deassert(csi2rx->pixel_rst[i]); ++ + writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, + csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); + +@@ -169,13 +176,16 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) + if (ret) + goto err_disable_pixclk; + ++ reset_control_deassert(csi2rx->sys_rst); + clk_disable_unprepare(csi2rx->p_clk); + + return 0; + + err_disable_pixclk: +- for (; i > 0; i--) ++ for (; i > 0; i--) { ++ reset_control_assert(csi2rx->pixel_rst[i - 1]); + clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); ++ } + + err_disable_pclk: + clk_disable_unprepare(csi2rx->p_clk); +@@ -188,14 +198,17 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) + unsigned int i; + + clk_prepare_enable(csi2rx->p_clk); ++ reset_control_assert(csi2rx->sys_rst); + clk_disable_unprepare(csi2rx->sys_clk); + + for (i = 0; i < csi2rx->max_streams; i++) { + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + ++ reset_control_assert(csi2rx->pixel_rst[i]); + clk_disable_unprepare(csi2rx->pixel_clk[i]); + } + ++ reset_control_assert(csi2rx->p_rst); + clk_disable_unprepare(csi2rx->p_clk); + + if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) +@@ -299,6 +312,16 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, + return PTR_ERR(csi2rx->p_clk); + } + ++ csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, ++ "sys"); ++ if (IS_ERR(csi2rx->sys_rst)) ++ return PTR_ERR(csi2rx->sys_rst); ++ ++ csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, ++ "reg_bank"); ++ if (IS_ERR(csi2rx->p_rst)) ++ return PTR_ERR(csi2rx->p_rst); ++ + csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy"); + if (IS_ERR(csi2rx->dphy)) { + dev_err(&pdev->dev, "Couldn't get external D-PHY\n"); +@@ -349,14 +372,21 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, + } + + for (i = 0; i < csi2rx->max_streams; i++) { +- char clk_name[16]; ++ char name[16]; + +- snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i); +- csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name); ++ snprintf(name, sizeof(name), "pixel_if%u_clk", i); ++ csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); + if (IS_ERR(csi2rx->pixel_clk[i])) { +- dev_err(&pdev->dev, "Couldn't get clock %s\n", clk_name); ++ dev_err(&pdev->dev, "Couldn't get clock %s\n", name); + return PTR_ERR(csi2rx->pixel_clk[i]); + } ++ ++ snprintf(name, sizeof(name), "pixel_if%u", i); ++ csi2rx->pixel_rst[i] = ++ devm_reset_control_get_optional_exclusive(&pdev->dev, ++ name); ++ if (IS_ERR(csi2rx->pixel_rst[i])) ++ return PTR_ERR(csi2rx->pixel_rst[i]); + } + + return 0; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0042-media-cadence-Add-support-for-external-dphy.patch b/srcpkgs/linux6.4/patches/0042-media-cadence-Add-support-for-external-dphy.patch new file mode 100644 index 0000000000000..2be4837e0e6db --- /dev/null +++ b/srcpkgs/linux6.4/patches/0042-media-cadence-Add-support-for-external-dphy.patch @@ -0,0 +1,146 @@ +From 7408ea246a5f96031e6a091db263545efbbd787f Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Tue, 23 May 2023 16:56:25 +0800 +Subject: [PATCH 42/72] media: cadence: Add support for external dphy + +Add support for external MIPI D-PHY. + +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + drivers/media/platform/cadence/cdns-csi2rx.c | 66 +++++++++++++++++--- + 1 file changed, 56 insertions(+), 10 deletions(-) + +diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c +index c9b80ac5cca5..a562c27906e1 100644 +--- a/drivers/media/platform/cadence/cdns-csi2rx.c ++++ b/drivers/media/platform/cadence/cdns-csi2rx.c +@@ -31,6 +31,12 @@ + #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) + #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) + ++#define CSI2RX_DPHY_LANE_CTRL_REG 0x40 ++#define CSI2RX_DPHY_CL_RST BIT(16) ++#define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12) ++#define CSI2RX_DPHY_CL_EN BIT(4) ++#define CSI2RX_DPHY_DL_EN(i) BIT(i) ++ + #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) + + #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +@@ -105,6 +111,24 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) + writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + } + ++static int csi2rx_configure_ext_dphy(struct csi2rx_priv *csi2rx) ++{ ++ union phy_configure_opts opts = { }; ++ int ret; ++ ++ ret = phy_power_on(csi2rx->dphy); ++ if (ret) ++ return ret; ++ ++ ret = phy_configure(csi2rx->dphy, &opts); ++ if (ret) { ++ phy_power_off(csi2rx->dphy); ++ return ret; ++ } ++ ++ return 0; ++} ++ + static int csi2rx_start(struct csi2rx_priv *csi2rx) + { + unsigned int i; +@@ -144,6 +168,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) + if (ret) + goto err_disable_pclk; + ++ /* Enable DPHY clk and data lanes. */ ++ if (csi2rx->dphy) { ++ reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; ++ for (i = 0; i < csi2rx->num_lanes; i++) { ++ reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); ++ reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); ++ } ++ ++ writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); ++ } ++ + /* + * Create a static mapping between the CSI virtual channels + * and the output stream. +@@ -177,10 +212,22 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) + goto err_disable_pixclk; + + reset_control_deassert(csi2rx->sys_rst); ++ ++ if (csi2rx->dphy) { ++ ret = csi2rx_configure_ext_dphy(csi2rx); ++ if (ret) { ++ dev_err(csi2rx->dev, ++ "Failed to configure external DPHY: %d\n", ret); ++ goto err_disable_sysclk; ++ } ++ } ++ + clk_disable_unprepare(csi2rx->p_clk); + + return 0; + ++err_disable_sysclk: ++ clk_disable_unprepare(csi2rx->sys_clk); + err_disable_pixclk: + for (; i > 0; i--) { + reset_control_assert(csi2rx->pixel_rst[i - 1]); +@@ -213,6 +260,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) + + if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) + dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); ++ ++ if (csi2rx->dphy) { ++ writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); ++ ++ if (phy_power_off(csi2rx->dphy)) ++ dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); ++ } + } + + static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) +@@ -328,15 +382,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, + return PTR_ERR(csi2rx->dphy); + } + +- /* +- * FIXME: Once we'll have external D-PHY support, the check +- * will need to be removed. +- */ +- if (csi2rx->dphy) { +- dev_err(&pdev->dev, "External D-PHY not supported yet\n"); +- return -EINVAL; +- } +- + ret = clk_prepare_enable(csi2rx->p_clk); + if (ret) { + dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n"); +@@ -366,7 +411,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, + * FIXME: Once we'll have internal D-PHY support, the check + * will need to be removed. + */ +- if (csi2rx->has_internal_dphy) { ++ if (!csi2rx->dphy && csi2rx->has_internal_dphy) { + dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); + return -EINVAL; + } +@@ -492,6 +537,7 @@ static int csi2rx_probe(struct platform_device *pdev) + dev_info(&pdev->dev, + "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", + csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, ++ csi2rx->dphy ? "external" : + csi2rx->has_internal_dphy ? "internal" : "no"); + + return 0; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0043-media-cadence-Add-support-for-JH7110-SoC.patch b/srcpkgs/linux6.4/patches/0043-media-cadence-Add-support-for-JH7110-SoC.patch new file mode 100644 index 0000000000000..5eae35bf72617 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0043-media-cadence-Add-support-for-JH7110-SoC.patch @@ -0,0 +1,28 @@ +From c77d5ba97055bf02c66aadbdd923a85048e43576 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Tue, 23 May 2023 16:56:26 +0800 +Subject: [PATCH 43/72] media: cadence: Add support for JH7110 SoC + +Add support for Starfive JH7110 SoC which has the cadence csi2 receiver. + +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + drivers/media/platform/cadence/cdns-csi2rx.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c +index a562c27906e1..f2b4574b8216 100644 +--- a/drivers/media/platform/cadence/cdns-csi2rx.c ++++ b/drivers/media/platform/cadence/cdns-csi2rx.c +@@ -558,6 +558,7 @@ static void csi2rx_remove(struct platform_device *pdev) + } + + static const struct of_device_id csi2rx_of_table[] = { ++ { .compatible = "starfive,jh7110-csi2rx" }, + { .compatible = "cdns,csi2rx" }, + { }, + }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0044-media-dt-bindings-Add-JH7110-Camera-Subsystem.patch b/srcpkgs/linux6.4/patches/0044-media-dt-bindings-Add-JH7110-Camera-Subsystem.patch new file mode 100644 index 0000000000000..278ec4555550d --- /dev/null +++ b/srcpkgs/linux6.4/patches/0044-media-dt-bindings-Add-JH7110-Camera-Subsystem.patch @@ -0,0 +1,205 @@ +From a10467eb6099f0b7829b93f5bc096b925f499173 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:33 +0800 +Subject: [PATCH 44/72] media: dt-bindings: Add JH7110 Camera Subsystem + +Add the bindings documentation for Starfive JH7110 Camera Subsystem +which is used for handing image sensor data. + +Reviewed-by: Krzysztof Kozlowski +Reviewed-by: Laurent Pinchart +Signed-off-by: Jack Zhu +--- + .../bindings/media/starfive,jh7110-camss.yaml | 180 ++++++++++++++++++ + 1 file changed, 180 insertions(+) + create mode 100644 Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml + +diff --git a/Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml b/Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml +new file mode 100644 +index 000000000000..c66586d90fa2 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml +@@ -0,0 +1,180 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Starfive SoC CAMSS ISP ++ ++maintainers: ++ - Jack Zhu ++ - Changhuang Liang ++ ++description: ++ The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It ++ consists of a VIN controller (Video In Controller, a top-level control unit) ++ and an ISP. ++ ++properties: ++ compatible: ++ const: starfive,jh7110-camss ++ ++ reg: ++ maxItems: 2 ++ ++ reg-names: ++ items: ++ - const: syscon ++ - const: isp ++ ++ clocks: ++ maxItems: 7 ++ ++ clock-names: ++ items: ++ - const: apb_func ++ - const: wrapper_clk_c ++ - const: dvp_inv ++ - const: axiwr ++ - const: mipi_rx0_pxl ++ - const: ispcore_2x ++ - const: isp_axi ++ ++ resets: ++ maxItems: 6 ++ ++ reset-names: ++ items: ++ - const: wrapper_p ++ - const: wrapper_c ++ - const: axird ++ - const: axiwr ++ - const: isp_top_n ++ - const: isp_top_axi ++ ++ power-domains: ++ items: ++ - description: JH7110 ISP Power Domain Switch Controller. ++ ++ interrupts: ++ maxItems: 4 ++ ++ ports: ++ $ref: /schemas/graph.yaml#/properties/ports ++ ++ properties: ++ port@0: ++ $ref: /schemas/graph.yaml#/$defs/port-base ++ unevaluatedProperties: false ++ description: Input port for receiving DVP data. ++ ++ properties: ++ endpoint: ++ $ref: video-interfaces.yaml# ++ unevaluatedProperties: false ++ ++ properties: ++ bus-type: ++ enum: [5, 6] ++ ++ bus-width: ++ enum: [8, 10, 12] ++ ++ data-shift: ++ enum: [0, 2] ++ default: 0 ++ ++ hsync-active: ++ enum: [0, 1] ++ default: 1 ++ ++ vsync-active: ++ enum: [0, 1] ++ default: 1 ++ ++ required: ++ - bus-type ++ - bus-width ++ ++ port@1: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: Input port for receiving CSI data. ++ ++ required: ++ - port@0 ++ - port@1 ++ ++required: ++ - compatible ++ - reg ++ - reg-names ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - power-domains ++ - interrupts ++ - ports ++ ++additionalProperties: false ++ ++examples: ++ - | ++ isp@19840000 { ++ compatible = "starfive,jh7110-camss"; ++ reg = <0x19840000 0x10000>, ++ <0x19870000 0x30000>; ++ reg-names = "syscon", "isp"; ++ clocks = <&ispcrg 0>, ++ <&ispcrg 13>, ++ <&ispcrg 2>, ++ <&ispcrg 12>, ++ <&ispcrg 1>, ++ <&syscrg 51>, ++ <&syscrg 52>; ++ clock-names = "apb_func", ++ "wrapper_clk_c", ++ "dvp_inv", ++ "axiwr", ++ "mipi_rx0_pxl", ++ "ispcore_2x", ++ "isp_axi"; ++ resets = <&ispcrg 0>, ++ <&ispcrg 1>, ++ <&ispcrg 10>, ++ <&ispcrg 11>, ++ <&syscrg 41>, ++ <&syscrg 42>; ++ reset-names = "wrapper_p", ++ "wrapper_c", ++ "axird", ++ "axiwr", ++ "isp_top_n", ++ "isp_top_axi"; ++ power-domains = <&pwrc 5>; ++ interrupts = <92>, <87>, <88>, <90>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port@0 { ++ reg = <0>; ++ vin_from_sc2235: endpoint { ++ remote-endpoint = <&sc2235_to_vin>; ++ bus-type = <5>; ++ bus-width = <8>; ++ data-shift = <2>; ++ hsync-active = <1>; ++ vsync-active = <0>; ++ pclk-sample = <1>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ vin_from_csi2rx: endpoint { ++ remote-endpoint = <&csi2rx_to_vin>; ++ }; ++ }; ++ }; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0045-media-admin-guide-Add-starfive_camss.rst-for-Starfiv.patch b/srcpkgs/linux6.4/patches/0045-media-admin-guide-Add-starfive_camss.rst-for-Starfiv.patch new file mode 100644 index 0000000000000..e60c44095ee62 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0045-media-admin-guide-Add-starfive_camss.rst-for-Starfiv.patch @@ -0,0 +1,118 @@ +From 41178db5eed8a567447b9a62a6e97038f8c51559 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:34 +0800 +Subject: [PATCH 45/72] media: admin-guide: Add starfive_camss.rst for Starfive + Camera Subsystem + +Add starfive_camss.rst file that documents the Starfive Camera +Subsystem driver which is used for handing image sensor data. + +Signed-off-by: Jack Zhu +--- + .../admin-guide/media/starfive_camss.rst | 57 +++++++++++++++++++ + .../media/starfive_camss_graph.dot | 16 ++++++ + .../admin-guide/media/v4l-drivers.rst | 1 + + 3 files changed, 74 insertions(+) + create mode 100644 Documentation/admin-guide/media/starfive_camss.rst + create mode 100644 Documentation/admin-guide/media/starfive_camss_graph.dot + +diff --git a/Documentation/admin-guide/media/starfive_camss.rst b/Documentation/admin-guide/media/starfive_camss.rst +new file mode 100644 +index 000000000000..a6378849384f +--- /dev/null ++++ b/Documentation/admin-guide/media/starfive_camss.rst +@@ -0,0 +1,57 @@ ++.. SPDX-License-Identifier: GPL-2.0 ++ ++.. include:: ++ ++================================ ++Starfive Camera Subsystem driver ++================================ ++ ++Introduction ++------------ ++ ++This file documents the driver for the Starfive Camera Subsystem found on ++Starfive JH7110 SoC. The driver is located under drivers/media/platform/ ++starfive. ++ ++The driver implements V4L2, Media controller and v4l2_subdev interfaces. ++Camera sensor using V4L2 subdev interface in the kernel is supported. ++ ++The driver has been successfully used on the Gstreamer 1.18.5 with ++v4l2src plugin. ++ ++ ++Starfive Camera Subsystem hardware ++---------------------------------- ++ ++The Starfive Camera Subsystem hardware consists of: ++ ++- MIPI DPHY Receiver: receives mipi data from a MIPI camera sensor. ++- MIPI CSIRx Controller: is responsible for handling and decoding CSI2 protocol ++ based camera sensor data stream. ++- ISP: handles the image data streams from the MIPI CSIRx Controller. ++- VIN(Video In): a top-level module, is responsible for controlling power ++ and clocks to other modules, dumps the input data to memory or transfers the ++ input data to ISP. ++ ++ ++Topology ++-------- ++ ++The media controller pipeline graph is as follows: ++ ++.. _starfive_camss_graph: ++ ++.. kernel-figure:: starfive_camss_graph.dot ++ :alt: starfive_camss_graph.dot ++ :align: center ++ ++The driver has 2 video devices: ++ ++- stf_vin0_wr_video0: capture device for images directly from the VIN module. ++- stf_vin0_isp0_video1: capture device for images without scaling. ++ ++The driver has 3 subdevices: ++ ++- stf_isp0: is responsible for all the isp operations. ++- stf_vin0_wr: used to dump RAW images to memory. ++- stf_vin0_isp0: used to capture images for the stf_vin0_isp0_video1 device. +diff --git a/Documentation/admin-guide/media/starfive_camss_graph.dot b/Documentation/admin-guide/media/starfive_camss_graph.dot +new file mode 100644 +index 000000000000..275661b720dc +--- /dev/null ++++ b/Documentation/admin-guide/media/starfive_camss_graph.dot +@@ -0,0 +1,16 @@ ++digraph board { ++ rankdir=TB ++ n00000001 [label="{{ 0} | stf_isp0\n/dev/v4l-subdev0 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] ++ n00000001:port1 -> n0000000d:port0 [style=dashed] ++ n00000004 [label="{{ 0} | stf_vin0_wr\n/dev/v4l-subdev1 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] ++ n00000004:port1 -> n00000007 [style=bold] ++ n00000007 [label="stf_vin0_wr_video0\n/dev/video0", shape=box, style=filled, fillcolor=yellow] ++ n0000000d [label="{{ 0} | stf_vin0_isp0\n/dev/v4l-subdev2 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] ++ n0000000d:port1 -> n00000010 [style=bold] ++ n00000010 [label="stf_vin0_isp0_video1\n/dev/video1", shape=box, style=filled, fillcolor=yellow] ++ n00000018 [label="{{ 0} | cdns_csi2rx.19800000.csi-bridge\n | { 1 | 2 | 3 | 4}}", shape=Mrecord, style=filled, fillcolor=green] ++ n00000018:port1 -> n00000004:port0 [style=dashed] ++ n00000018:port1 -> n00000001:port0 [style=dashed] ++ n00000022 [label="{{} | imx219 6-0010\n/dev/v4l-subdev3 | { 0}}", shape=Mrecord, style=filled, fillcolor=green] ++ n00000022:port0 -> n00000018:port0 [style=bold] ++} +diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst +index 1c41f87c3917..2274fd29c1d7 100644 +--- a/Documentation/admin-guide/media/v4l-drivers.rst ++++ b/Documentation/admin-guide/media/v4l-drivers.rst +@@ -27,6 +27,7 @@ Video4Linux (V4L) driver-specific documentation + si470x + si4713 + si476x ++ starfive_camss + vimc + visl + vivid +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0046-media-starfive-camss-Add-basic-driver.patch b/srcpkgs/linux6.4/patches/0046-media-starfive-camss-Add-basic-driver.patch new file mode 100644 index 0000000000000..f76d82790dc08 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0046-media-starfive-camss-Add-basic-driver.patch @@ -0,0 +1,604 @@ +From 8f7314bc5eefe6ed216f857dc37e093862ca719b Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:35 +0800 +Subject: [PATCH 46/72] media: starfive: camss: Add basic driver + +Add basic platform driver for StarFive Camera Subsystem. + +Reviewed-by: Bryan O'Donoghue +Signed-off-by: Jack Zhu +--- + drivers/media/platform/Kconfig | 1 + + drivers/media/platform/Makefile | 1 + + drivers/media/platform/starfive/Kconfig | 5 + + drivers/media/platform/starfive/Makefile | 2 + + drivers/media/platform/starfive/camss/Kconfig | 16 + + .../media/platform/starfive/camss/Makefile | 8 + + .../media/platform/starfive/camss/stf_camss.c | 338 ++++++++++++++++++ + .../media/platform/starfive/camss/stf_camss.h | 146 ++++++++ + 8 files changed, 517 insertions(+) + create mode 100644 drivers/media/platform/starfive/Kconfig + create mode 100644 drivers/media/platform/starfive/Makefile + create mode 100644 drivers/media/platform/starfive/camss/Kconfig + create mode 100644 drivers/media/platform/starfive/camss/Makefile + create mode 100644 drivers/media/platform/starfive/camss/stf_camss.c + create mode 100644 drivers/media/platform/starfive/camss/stf_camss.h + +diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig +index ee579916f874..627eaa0ab3ee 100644 +--- a/drivers/media/platform/Kconfig ++++ b/drivers/media/platform/Kconfig +@@ -80,6 +80,7 @@ source "drivers/media/platform/renesas/Kconfig" + source "drivers/media/platform/rockchip/Kconfig" + source "drivers/media/platform/samsung/Kconfig" + source "drivers/media/platform/st/Kconfig" ++source "drivers/media/platform/starfive/Kconfig" + source "drivers/media/platform/sunxi/Kconfig" + source "drivers/media/platform/ti/Kconfig" + source "drivers/media/platform/verisilicon/Kconfig" +diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile +index 5453bb868e67..5a038498a370 100644 +--- a/drivers/media/platform/Makefile ++++ b/drivers/media/platform/Makefile +@@ -23,6 +23,7 @@ obj-y += renesas/ + obj-y += rockchip/ + obj-y += samsung/ + obj-y += st/ ++obj-y += starfive/ + obj-y += sunxi/ + obj-y += ti/ + obj-y += verisilicon/ +diff --git a/drivers/media/platform/starfive/Kconfig b/drivers/media/platform/starfive/Kconfig +new file mode 100644 +index 000000000000..7955c2a0a4a3 +--- /dev/null ++++ b/drivers/media/platform/starfive/Kconfig +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++comment "StarFive media platform drivers" ++ ++source "drivers/media/platform/starfive/camss/Kconfig" +diff --git a/drivers/media/platform/starfive/Makefile b/drivers/media/platform/starfive/Makefile +new file mode 100644 +index 000000000000..4639fa1bca32 +--- /dev/null ++++ b/drivers/media/platform/starfive/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++obj-y += camss/ +diff --git a/drivers/media/platform/starfive/camss/Kconfig b/drivers/media/platform/starfive/camss/Kconfig +new file mode 100644 +index 000000000000..dafe1d24324b +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/Kconfig +@@ -0,0 +1,16 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++config VIDEO_STARFIVE_CAMSS ++ tristate "Starfive Camera Subsystem driver" ++ depends on V4L_PLATFORM_DRIVERS ++ depends on VIDEO_DEV && OF ++ depends on HAS_DMA ++ select MEDIA_CONTROLLER ++ select VIDEO_V4L2_SUBDEV_API ++ select VIDEOBUF2_DMA_CONTIG ++ select V4L2_FWNODE ++ help ++ Enable this to support for the Starfive Camera subsystem ++ found on Starfive JH7110 SoC. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called stf-camss. +diff --git a/drivers/media/platform/starfive/camss/Makefile b/drivers/media/platform/starfive/camss/Makefile +new file mode 100644 +index 000000000000..d56ddd078a71 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/Makefile +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# ++# Makefile for StarFive Camera Subsystem driver ++# ++ ++starfive-camss-objs += stf_camss.o ++ ++obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive-camss.o +diff --git a/drivers/media/platform/starfive/camss/stf_camss.c b/drivers/media/platform/starfive/camss/stf_camss.c +new file mode 100644 +index 000000000000..dc2b5dba7bd4 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_camss.c +@@ -0,0 +1,338 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_camss.c ++ * ++ * Starfive Camera Subsystem driver ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "stf_camss.h" ++ ++static const char * const stfcamss_clocks[] = { ++ "clk_apb_func", ++ "clk_wrapper_clk_c", ++ "clk_dvp_inv", ++ "clk_axiwr", ++ "clk_mipi_rx0_pxl", ++ "clk_ispcore_2x", ++ "clk_isp_axi", ++}; ++ ++static const char * const stfcamss_resets[] = { ++ "rst_wrapper_p", ++ "rst_wrapper_c", ++ "rst_axird", ++ "rst_axiwr", ++ "rst_isp_top_n", ++ "rst_isp_top_axi", ++}; ++ ++static int stfcamss_get_mem_res(struct platform_device *pdev, ++ struct stfcamss *stfcamss) ++{ ++ stfcamss->syscon_base = ++ devm_platform_ioremap_resource_byname(pdev, "syscon"); ++ if (IS_ERR(stfcamss->syscon_base)) ++ return PTR_ERR(stfcamss->syscon_base); ++ ++ stfcamss->isp_base = ++ devm_platform_ioremap_resource_byname(pdev, "isp"); ++ if (IS_ERR(stfcamss->isp_base)) ++ return PTR_ERR(stfcamss->isp_base); ++ ++ return 0; ++} ++ ++/* ++ * stfcamss_of_parse_endpoint_node - Parse port endpoint node ++ * @dev: Device ++ * @node: Device node to be parsed ++ * @csd: Parsed data from port endpoint node ++ * ++ * Return 0 on success or a negative error code on failure ++ */ ++static int stfcamss_of_parse_endpoint_node(struct device *dev, ++ struct device_node *node, ++ struct stfcamss_async_subdev *csd) ++{ ++ struct v4l2_fwnode_endpoint vep = { { 0 } }; ++ ++ v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep); ++ dev_dbg(dev, "vep.base.port = %d, id = %d\n", ++ vep.base.port, vep.base.id); ++ ++ csd->port = vep.base.port; ++ ++ return 0; ++} ++ ++/* ++ * stfcamss_of_parse_ports - Parse ports node ++ * @stfcamss: STFCAMSS device ++ * ++ * Return number of "port" nodes found in "ports" node ++ */ ++static int stfcamss_of_parse_ports(struct stfcamss *stfcamss) ++{ ++ struct device *dev = stfcamss->dev; ++ struct device_node *node = NULL; ++ int ret, num_subdevs = 0; ++ ++ for_each_endpoint_of_node(dev->of_node, node) { ++ struct stfcamss_async_subdev *csd; ++ ++ if (!of_device_is_available(node)) ++ continue; ++ ++ csd = v4l2_async_nf_add_fwnode_remote(&stfcamss->notifier, ++ of_fwnode_handle(node), ++ struct stfcamss_async_subdev); ++ if (IS_ERR(csd)) { ++ ret = PTR_ERR(csd); ++ goto err_cleanup; ++ } ++ ++ ret = stfcamss_of_parse_endpoint_node(dev, node, csd); ++ if (ret < 0) ++ goto err_cleanup; ++ ++ num_subdevs++; ++ } ++ ++ return num_subdevs; ++ ++err_cleanup: ++ of_node_put(node); ++ return ret; ++} ++ ++static int stfcamss_subdev_notifier_bound(struct v4l2_async_notifier *async, ++ struct v4l2_subdev *subdev, ++ struct v4l2_async_subdev *asd) ++{ ++ struct media_pad *pad[STF_PADS_NUM]; ++ unsigned int i, pad_num = 0; ++ ++ for (i = 0; i < pad_num; ++i) { ++ int ret; ++ ++ ret = v4l2_create_fwnode_links_to_pad(subdev, pad[i], 0); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int stfcamss_subdev_notifier_complete(struct v4l2_async_notifier *ntf) ++{ ++ struct stfcamss *stfcamss = ++ container_of(ntf, struct stfcamss, notifier); ++ ++ return v4l2_device_register_subdev_nodes(&stfcamss->v4l2_dev); ++} ++ ++static const struct v4l2_async_notifier_operations ++stfcamss_subdev_notifier_ops = { ++ .bound = stfcamss_subdev_notifier_bound, ++ .complete = stfcamss_subdev_notifier_complete, ++}; ++ ++static const struct media_device_ops stfcamss_media_ops = { ++ .link_notify = v4l2_pipeline_link_notify, ++}; ++ ++static void stfcamss_mc_init(struct platform_device *pdev, ++ struct stfcamss *stfcamss) ++{ ++ stfcamss->media_dev.dev = stfcamss->dev; ++ strscpy(stfcamss->media_dev.model, "Starfive Camera Subsystem", ++ sizeof(stfcamss->media_dev.model)); ++ stfcamss->media_dev.ops = &stfcamss_media_ops; ++ media_device_init(&stfcamss->media_dev); ++ ++ stfcamss->v4l2_dev.mdev = &stfcamss->media_dev; ++} ++ ++/* ++ * stfcamss_probe - Probe STFCAMSS platform device ++ * @pdev: Pointer to STFCAMSS platform device ++ * ++ * Return 0 on success or a negative error code on failure ++ */ ++static int stfcamss_probe(struct platform_device *pdev) ++{ ++ struct stfcamss *stfcamss; ++ struct device *dev = &pdev->dev; ++ int ret, num_subdevs; ++ unsigned int i; ++ ++ stfcamss = devm_kzalloc(dev, sizeof(*stfcamss), GFP_KERNEL); ++ if (!stfcamss) ++ return -ENOMEM; ++ ++ for (i = 0; i < ARRAY_SIZE(stfcamss->irq); ++i) { ++ stfcamss->irq[i] = platform_get_irq(pdev, i); ++ if (stfcamss->irq[i] < 0) ++ return dev_err_probe(&pdev->dev, stfcamss->irq[i], ++ "Failed to get irq%d", i); ++ } ++ ++ stfcamss->nclks = ARRAY_SIZE(stfcamss->sys_clk); ++ for (i = 0; i < stfcamss->nclks; ++i) ++ stfcamss->sys_clk[i].id = stfcamss_clocks[i]; ++ ret = devm_clk_bulk_get(dev, stfcamss->nclks, stfcamss->sys_clk); ++ if (ret) { ++ dev_err(dev, "Failed to get clk controls\n"); ++ return ret; ++ } ++ ++ stfcamss->nrsts = ARRAY_SIZE(stfcamss->sys_rst); ++ for (i = 0; i < stfcamss->nrsts; ++i) ++ stfcamss->sys_rst[i].id = stfcamss_resets[i]; ++ ret = devm_reset_control_bulk_get_shared(dev, stfcamss->nrsts, ++ stfcamss->sys_rst); ++ if (ret) { ++ dev_err(dev, "Failed to get reset controls\n"); ++ return ret; ++ } ++ ++ ret = stfcamss_get_mem_res(pdev, stfcamss); ++ if (ret) { ++ dev_err(dev, "Could not map registers\n"); ++ return ret; ++ } ++ ++ stfcamss->dev = dev; ++ platform_set_drvdata(pdev, stfcamss); ++ ++ v4l2_async_nf_init(&stfcamss->notifier); ++ ++ num_subdevs = stfcamss_of_parse_ports(stfcamss); ++ if (num_subdevs < 0) { ++ ret = -ENODEV; ++ goto err_cleanup_notifier; ++ } ++ ++ stfcamss_mc_init(pdev, stfcamss); ++ ++ ret = v4l2_device_register(stfcamss->dev, &stfcamss->v4l2_dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to register V4L2 device: %d\n", ret); ++ goto err_cleanup_notifier; ++ } ++ ++ ret = media_device_register(&stfcamss->media_dev); ++ if (ret) { ++ dev_err(dev, "Failed to register media device: %d\n", ret); ++ goto err_unregister_device; ++ } ++ ++ pm_runtime_enable(dev); ++ ++ stfcamss->notifier.ops = &stfcamss_subdev_notifier_ops; ++ ret = v4l2_async_nf_register(&stfcamss->v4l2_dev, &stfcamss->notifier); ++ if (ret) { ++ dev_err(dev, "Failed to register async subdev nodes: %d\n", ++ ret); ++ goto err_unregister_media_dev; ++ } ++ ++ return 0; ++ ++err_unregister_media_dev: ++ media_device_unregister(&stfcamss->media_dev); ++err_unregister_device: ++ v4l2_device_unregister(&stfcamss->v4l2_dev); ++err_cleanup_notifier: ++ v4l2_async_nf_cleanup(&stfcamss->notifier); ++ return ret; ++} ++ ++/* ++ * stfcamss_remove - Remove STFCAMSS platform device ++ * @pdev: Pointer to STFCAMSS platform device ++ * ++ * Always returns 0. ++ */ ++static int stfcamss_remove(struct platform_device *pdev) ++{ ++ struct stfcamss *stfcamss = platform_get_drvdata(pdev); ++ ++ v4l2_device_unregister(&stfcamss->v4l2_dev); ++ media_device_cleanup(&stfcamss->media_dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ return 0; ++} ++ ++static const struct of_device_id stfcamss_of_match[] = { ++ { .compatible = "starfive,jh7110-camss" }, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, stfcamss_of_match); ++ ++static int __maybe_unused stfcamss_runtime_suspend(struct device *dev) ++{ ++ struct stfcamss *stfcamss = dev_get_drvdata(dev); ++ ++ reset_control_assert(stfcamss->sys_rst[STF_RST_AXIWR].rstc); ++ reset_control_assert(stfcamss->sys_rst[STF_RST_ISP_TOP_AXI].rstc); ++ reset_control_assert(stfcamss->sys_rst[STF_RST_ISP_TOP_N].rstc); ++ clk_disable_unprepare(stfcamss->sys_clk[STF_CLK_ISP_AXI].clk); ++ clk_disable_unprepare(stfcamss->sys_clk[STF_CLK_ISPCORE_2X].clk); ++ ++ return 0; ++} ++ ++static int __maybe_unused stfcamss_runtime_resume(struct device *dev) ++{ ++ struct stfcamss *stfcamss = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = clk_prepare_enable(stfcamss->sys_clk[STF_CLK_ISPCORE_2X].clk); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(stfcamss->sys_clk[STF_CLK_ISP_AXI].clk); ++ if (ret) ++ return ret; ++ ++ reset_control_deassert(stfcamss->sys_rst[STF_RST_ISP_TOP_N].rstc); ++ reset_control_deassert(stfcamss->sys_rst[STF_RST_ISP_TOP_AXI].rstc); ++ reset_control_deassert(stfcamss->sys_rst[STF_RST_AXIWR].rstc); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops stfcamss_pm_ops = { ++ SET_RUNTIME_PM_OPS(stfcamss_runtime_suspend, ++ stfcamss_runtime_resume, ++ NULL) ++}; ++ ++static struct platform_driver stfcamss_driver = { ++ .probe = stfcamss_probe, ++ .remove = stfcamss_remove, ++ .driver = { ++ .name = "starfive-camss", ++ .pm = &stfcamss_pm_ops, ++ .of_match_table = of_match_ptr(stfcamss_of_match), ++ }, ++}; ++ ++module_platform_driver(stfcamss_driver); ++ ++MODULE_AUTHOR("StarFive Corporation"); ++MODULE_DESCRIPTION("StarFive Camera Subsystem driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/media/platform/starfive/camss/stf_camss.h b/drivers/media/platform/starfive/camss/stf_camss.h +new file mode 100644 +index 000000000000..15c4f34b9054 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_camss.h +@@ -0,0 +1,146 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * stf_camss.h ++ * ++ * Starfive Camera Subsystem driver ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef STF_CAMSS_H ++#define STF_CAMSS_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define STF_DVP_NAME "stf_dvp" ++#define STF_CSI_NAME "cdns_csi2rx" ++#define STF_ISP_NAME "stf_isp" ++#define STF_VIN_NAME "stf_vin" ++ ++#define STF_PAD_SINK 0 ++#define STF_PAD_SRC 1 ++#define STF_PADS_NUM 2 ++ ++enum stf_port_num { ++ STF_PORT_DVP = 0, ++ STF_PORT_CSI2RX ++}; ++ ++enum stf_clk { ++ STF_CLK_APB_FUNC = 0, ++ STF_CLK_WRAPPER_CLK_C, ++ STF_CLK_DVP_INV, ++ STF_CLK_AXIWR, ++ STF_CLK_MIPI_RX0_PXL, ++ STF_CLK_ISPCORE_2X, ++ STF_CLK_ISP_AXI, ++ STF_CLK_NUM ++}; ++ ++enum stf_rst { ++ STF_RST_WRAPPER_P = 0, ++ STF_RST_WRAPPER_C, ++ STF_RST_AXIRD, ++ STF_RST_AXIWR, ++ STF_RST_ISP_TOP_N, ++ STF_RST_ISP_TOP_AXI, ++ STF_RST_NUM ++}; ++ ++enum stf_irq { ++ STF_IRQ_VINWR = 0, ++ STF_IRQ_ISP, ++ STF_IRQ_ISPCSIL, ++ STF_IRQ_NUM ++}; ++ ++struct stfcamss { ++ struct v4l2_device v4l2_dev; ++ struct media_device media_dev; ++ struct media_pipeline pipe; ++ struct device *dev; ++ struct v4l2_async_notifier notifier; ++ void __iomem *syscon_base; ++ void __iomem *isp_base; ++ int irq[STF_IRQ_NUM]; ++ struct clk_bulk_data sys_clk[STF_CLK_NUM]; ++ int nclks; ++ struct reset_control_bulk_data sys_rst[STF_RST_NUM]; ++ int nrsts; ++}; ++ ++struct stfcamss_async_subdev { ++ struct v4l2_async_subdev asd; /* must be first */ ++ enum stf_port_num port; ++}; ++ ++static inline u32 stf_isp_reg_read(struct stfcamss *stfcamss, u32 reg) ++{ ++ return ioread32(stfcamss->isp_base + reg); ++} ++ ++static inline void stf_isp_reg_write(struct stfcamss *stfcamss, ++ u32 reg, u32 val) ++{ ++ iowrite32(val, stfcamss->isp_base + reg); ++} ++ ++static inline void stf_isp_reg_write_delay(struct stfcamss *stfcamss, ++ u32 reg, u32 val, u32 delay) ++{ ++ iowrite32(val, stfcamss->isp_base + reg); ++ usleep_range(1000 * delay, 1000 * delay + 100); ++} ++ ++static inline void stf_isp_reg_set_bit(struct stfcamss *stfcamss, ++ u32 reg, u32 mask, u32 val) ++{ ++ u32 value; ++ ++ value = ioread32(stfcamss->isp_base + reg) & ~mask; ++ val &= mask; ++ val |= value; ++ iowrite32(val, stfcamss->isp_base + reg); ++} ++ ++static inline void stf_isp_reg_set(struct stfcamss *stfcamss, u32 reg, u32 mask) ++{ ++ iowrite32(ioread32(stfcamss->isp_base + reg) | mask, ++ stfcamss->isp_base + reg); ++} ++ ++static inline u32 stf_syscon_reg_read(struct stfcamss *stfcamss, u32 reg) ++{ ++ return ioread32(stfcamss->syscon_base + reg); ++} ++ ++static inline void stf_syscon_reg_write(struct stfcamss *stfcamss, ++ u32 reg, u32 val) ++{ ++ iowrite32(val, stfcamss->syscon_base + reg); ++} ++ ++static inline void stf_syscon_reg_set_bit(struct stfcamss *stfcamss, ++ u32 reg, u32 bit_mask) ++{ ++ u32 value; ++ ++ value = ioread32(stfcamss->syscon_base + reg); ++ iowrite32(value | bit_mask, stfcamss->syscon_base + reg); ++} ++ ++static inline void stf_syscon_reg_clear_bit(struct stfcamss *stfcamss, ++ u32 reg, u32 bit_mask) ++{ ++ u32 value; ++ ++ value = ioread32(stfcamss->syscon_base + reg); ++ iowrite32(value & ~bit_mask, stfcamss->syscon_base + reg); ++} ++#endif /* STF_CAMSS_H */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0047-media-starfive-camss-Add-video-driver.patch b/srcpkgs/linux6.4/patches/0047-media-starfive-camss-Add-video-driver.patch new file mode 100644 index 0000000000000..b285f69843a25 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0047-media-starfive-camss-Add-video-driver.patch @@ -0,0 +1,861 @@ +From 44624a005ede8faf28e490dfd1cd89f3f726ea4d Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:36 +0800 +Subject: [PATCH 47/72] media: starfive: camss: Add video driver + +Add video driver for StarFive Camera Subsystem. + +Signed-off-by: Jack Zhu +--- + .../media/platform/starfive/camss/Makefile | 4 +- + .../media/platform/starfive/camss/stf_video.c | 724 ++++++++++++++++++ + .../media/platform/starfive/camss/stf_video.h | 92 +++ + 3 files changed, 819 insertions(+), 1 deletion(-) + create mode 100644 drivers/media/platform/starfive/camss/stf_video.c + create mode 100644 drivers/media/platform/starfive/camss/stf_video.h + +diff --git a/drivers/media/platform/starfive/camss/Makefile b/drivers/media/platform/starfive/camss/Makefile +index d56ddd078a71..eb457917a914 100644 +--- a/drivers/media/platform/starfive/camss/Makefile ++++ b/drivers/media/platform/starfive/camss/Makefile +@@ -3,6 +3,8 @@ + # Makefile for StarFive Camera Subsystem driver + # + +-starfive-camss-objs += stf_camss.o ++starfive-camss-objs += \ ++ stf_camss.o \ ++ stf_video.o + + obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive-camss.o +diff --git a/drivers/media/platform/starfive/camss/stf_video.c b/drivers/media/platform/starfive/camss/stf_video.c +new file mode 100644 +index 000000000000..2e6472fe51c6 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_video.c +@@ -0,0 +1,724 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_video.c ++ * ++ * StarFive Camera Subsystem - V4L2 device node ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "stf_camss.h" ++#include "stf_video.h" ++ ++static const struct stfcamss_format_info formats_pix_wr[] = { ++ { ++ .code = MEDIA_BUS_FMT_SRGGB10_1X10, ++ .pixelformat = V4L2_PIX_FMT_SRGGB10, ++ .planes = 1, ++ .vsub = { 1 }, ++ .bpp = 10, ++ }, ++ { ++ .code = MEDIA_BUS_FMT_SGRBG10_1X10, ++ .pixelformat = V4L2_PIX_FMT_SGRBG10, ++ .planes = 1, ++ .vsub = { 1 }, ++ .bpp = 10, ++ }, ++ { ++ .code = MEDIA_BUS_FMT_SGBRG10_1X10, ++ .pixelformat = V4L2_PIX_FMT_SGBRG10, ++ .planes = 1, ++ .vsub = { 1 }, ++ .bpp = 10, ++ }, ++ { ++ .code = MEDIA_BUS_FMT_SBGGR10_1X10, ++ .pixelformat = V4L2_PIX_FMT_SBGGR10, ++ .planes = 1, ++ .vsub = { 1 }, ++ .bpp = 10, ++ }, ++}; ++ ++static const struct stfcamss_format_info formats_pix_isp[] = { ++ { ++ .code = MEDIA_BUS_FMT_Y12_1X12, ++ .pixelformat = V4L2_PIX_FMT_NV12, ++ .planes = 2, ++ .vsub = { 1, 2 }, ++ .bpp = 8, ++ }, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * Helper functions ++ */ ++ ++static int video_find_format(u32 code, u32 pixelformat, ++ struct stfcamss_video *video) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < video->nformats; ++i) { ++ if (video->formats[i].code == code && ++ video->formats[i].pixelformat == pixelformat) ++ return i; ++ } ++ ++ for (i = 0; i < video->nformats; ++i) ++ if (video->formats[i].code == code) ++ return i; ++ ++ for (i = 0; i < video->nformats; ++i) ++ if (video->formats[i].pixelformat == pixelformat) ++ return i; ++ ++ return -EINVAL; ++} ++ ++static int __video_try_fmt(struct stfcamss_video *video, struct v4l2_format *f) ++{ ++ struct v4l2_pix_format *pix; ++ const struct stfcamss_format_info *fi; ++ u32 width, height; ++ u32 bpl; ++ unsigned int i; ++ ++ pix = &f->fmt.pix; ++ ++ for (i = 0; i < video->nformats; i++) ++ if (pix->pixelformat == video->formats[i].pixelformat) ++ break; ++ ++ if (i == video->nformats) ++ i = 0; /* default format */ ++ ++ fi = &video->formats[i]; ++ width = pix->width; ++ height = pix->height; ++ ++ memset(pix, 0, sizeof(*pix)); ++ ++ pix->pixelformat = fi->pixelformat; ++ pix->width = clamp_t(u32, width, STFCAMSS_FRAME_MIN_WIDTH, ++ STFCAMSS_FRAME_MAX_WIDTH); ++ pix->height = clamp_t(u32, height, STFCAMSS_FRAME_MIN_HEIGHT, ++ STFCAMSS_FRAME_MAX_HEIGHT); ++ bpl = pix->width * fi->bpp / 8; ++ bpl = ALIGN(bpl, video->bpl_alignment); ++ pix->bytesperline = bpl; ++ ++ for (i = 0; i < fi->planes; ++i) ++ pix->sizeimage += bpl * pix->height / fi->vsub[i]; ++ ++ pix->field = V4L2_FIELD_NONE; ++ pix->colorspace = V4L2_COLORSPACE_SRGB; ++ pix->flags = 0; ++ pix->ycbcr_enc = ++ V4L2_MAP_YCBCR_ENC_DEFAULT(pix->colorspace); ++ pix->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(true, ++ pix->colorspace, ++ pix->ycbcr_enc); ++ pix->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(pix->colorspace); ++ ++ return 0; ++} ++ ++static int stf_video_init_format(struct stfcamss_video *video) ++{ ++ int ret; ++ struct v4l2_format format = { ++ .type = video->type, ++ .fmt.pix = { ++ .width = 1920, ++ .height = 1080, ++ .pixelformat = V4L2_PIX_FMT_RGB565, ++ }, ++ }; ++ ++ ret = __video_try_fmt(video, &format); ++ ++ if (ret < 0) ++ return ret; ++ ++ video->active_fmt = format; ++ ++ return 0; ++} ++ ++/* ----------------------------------------------------------------------------- ++ * Video queue operations ++ */ ++ ++static int video_queue_setup(struct vb2_queue *q, ++ unsigned int *num_buffers, ++ unsigned int *num_planes, ++ unsigned int sizes[], ++ struct device *alloc_devs[]) ++{ ++ struct stfcamss_video *video = vb2_get_drv_priv(q); ++ const struct v4l2_pix_format *format = &video->active_fmt.fmt.pix; ++ ++ if (*num_planes) { ++ if (*num_planes != 1) ++ return -EINVAL; ++ ++ if (sizes[0] < format->sizeimage) ++ return -EINVAL; ++ } ++ ++ *num_planes = 1; ++ sizes[0] = format->sizeimage; ++ if (!sizes[0]) ++ dev_err(video->stfcamss->dev, ++ "%s: error size is zero!!!\n", __func__); ++ ++ dev_dbg(video->stfcamss->dev, "planes = %d, size = %d\n", ++ *num_planes, sizes[0]); ++ ++ return 0; ++} ++ ++static int video_buf_init(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue); ++ struct stfcamss_buffer *buffer = ++ container_of(vbuf, struct stfcamss_buffer, vb); ++ const struct v4l2_pix_format *fmt = &video->active_fmt.fmt.pix; ++ dma_addr_t *paddr; ++ ++ paddr = vb2_plane_cookie(vb, 0); ++ buffer->addr[0] = *paddr; ++ ++ if (fmt->pixelformat == V4L2_PIX_FMT_NV12 || ++ fmt->pixelformat == V4L2_PIX_FMT_NV21 || ++ fmt->pixelformat == V4L2_PIX_FMT_NV16 || ++ fmt->pixelformat == V4L2_PIX_FMT_NV61) ++ buffer->addr[1] = ++ buffer->addr[0] + fmt->bytesperline * fmt->height; ++ ++ return 0; ++} ++ ++static int video_buf_prepare(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue); ++ const struct v4l2_pix_format *fmt = &video->active_fmt.fmt.pix; ++ ++ if (fmt->sizeimage > vb2_plane_size(vb, 0)) { ++ dev_err(video->stfcamss->dev, ++ "sizeimage = %d, plane size = %d\n", ++ fmt->sizeimage, (unsigned int)vb2_plane_size(vb, 0)); ++ return -EINVAL; ++ } ++ vb2_set_plane_payload(vb, 0, fmt->sizeimage); ++ ++ vbuf->field = V4L2_FIELD_NONE; ++ ++ return 0; ++} ++ ++static void video_buf_queue(struct vb2_buffer *vb) ++{ ++ struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); ++ struct stfcamss_video *video = vb2_get_drv_priv(vb->vb2_queue); ++ struct stfcamss_buffer *buffer = ++ container_of(vbuf, struct stfcamss_buffer, vb); ++ ++ video->ops->queue_buffer(video, buffer); ++} ++ ++/* ++ * video_mbus_to_pix - Convert v4l2_mbus_framefmt to v4l2_pix_format ++ * @mbus: v4l2_mbus_framefmt format (input) ++ * @pix: v4l2_pix_format_mplane format (output) ++ * @f: a pointer to formats array element to be used for the conversion ++ * @alignment: bytesperline alignment value ++ * ++ * Fill the output pix structure with information from the input mbus format. ++ * ++ * Return 0 on success or a negative error code otherwise ++ */ ++static int video_mbus_to_pix(const struct v4l2_mbus_framefmt *mbus, ++ struct v4l2_pix_format *pix, ++ const struct stfcamss_format_info *f, ++ unsigned int alignment) ++{ ++ u32 bytesperline; ++ unsigned int i; ++ ++ memset(pix, 0, sizeof(*pix)); ++ v4l2_fill_pix_format(pix, mbus); ++ pix->pixelformat = f->pixelformat; ++ bytesperline = pix->width * f->bpp / 8; ++ bytesperline = ALIGN(bytesperline, alignment); ++ pix->bytesperline = bytesperline; ++ ++ for (i = 0; i < f->planes; ++i) ++ pix->sizeimage += bytesperline * pix->height / f->vsub[i]; ++ ++ return 0; ++} ++ ++static struct v4l2_subdev *video_remote_subdev(struct stfcamss_video *video, ++ u32 *pad) ++{ ++ struct media_pad *remote; ++ ++ remote = media_pad_remote_pad_first(&video->pad); ++ ++ if (!remote || !is_media_entity_v4l2_subdev(remote->entity)) ++ return NULL; ++ ++ if (pad) ++ *pad = remote->index; ++ ++ return media_entity_to_v4l2_subdev(remote->entity); ++} ++ ++static int video_get_subdev_format(struct stfcamss_video *video, ++ struct v4l2_format *format) ++{ ++ struct v4l2_pix_format *pix = &video->active_fmt.fmt.pix; ++ struct v4l2_subdev_format fmt; ++ struct v4l2_subdev *subdev; ++ u32 pixelformat; ++ u32 pad; ++ int ret; ++ ++ subdev = video_remote_subdev(video, &pad); ++ if (!subdev) ++ return -EPIPE; ++ ++ fmt.pad = pad; ++ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; ++ ++ ret = v4l2_subdev_call(subdev, pad, get_fmt, NULL, &fmt); ++ if (ret) ++ return ret; ++ ++ pixelformat = pix->pixelformat; ++ ret = video_find_format(fmt.format.code, pixelformat, video); ++ if (ret < 0) ++ return ret; ++ ++ format->type = video->type; ++ ++ return video_mbus_to_pix(&fmt.format, &format->fmt.pix, ++ &video->formats[ret], video->bpl_alignment); ++} ++ ++static int video_check_format(struct stfcamss_video *video) ++{ ++ struct v4l2_pix_format *pix = &video->active_fmt.fmt.pix; ++ struct v4l2_format format; ++ struct v4l2_pix_format *sd_pix = &format.fmt.pix; ++ int ret; ++ ++ sd_pix->pixelformat = pix->pixelformat; ++ ret = video_get_subdev_format(video, &format); ++ if (ret < 0) ++ return ret; ++ ++ if (pix->pixelformat != sd_pix->pixelformat || ++ pix->height != sd_pix->height || ++ pix->width != sd_pix->width || ++ pix->field != format.fmt.pix.field) { ++ dev_err(video->stfcamss->dev, ++ "not match:\n" ++ "pixelformat: 0x%x <-> 0x%x\n" ++ "height: %d <-> %d\n" ++ "field: %d <-> %d\n", ++ pix->pixelformat, sd_pix->pixelformat, ++ pix->height, sd_pix->height, ++ pix->field, format.fmt.pix.field); ++ return -EPIPE; ++ } ++ ++ return 0; ++} ++ ++static int video_start_streaming(struct vb2_queue *q, unsigned int count) ++{ ++ struct stfcamss_video *video = vb2_get_drv_priv(q); ++ struct video_device *vdev = &video->vdev; ++ struct media_entity *entity; ++ struct media_pad *pad; ++ struct v4l2_subdev *subdev; ++ int ret; ++ ++ ret = video_device_pipeline_start(vdev, &video->stfcamss->pipe); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, ++ "Failed to media_pipeline_start: %d\n", ret); ++ return ret; ++ } ++ ++ ret = video_check_format(video); ++ if (ret < 0) ++ goto error; ++ ++ ret = pm_runtime_resume_and_get(video->stfcamss->dev); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, "power up failed %d\n", ret); ++ goto error; ++ } ++ ++ entity = &vdev->entity; ++ while (1) { ++ pad = &entity->pads[0]; ++ if (!(pad->flags & MEDIA_PAD_FL_SINK)) ++ break; ++ ++ pad = media_pad_remote_pad_first(pad); ++ if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) ++ break; ++ ++ entity = pad->entity; ++ subdev = media_entity_to_v4l2_subdev(entity); ++ ++ ret = v4l2_subdev_call(subdev, video, s_stream, 1); ++ if (ret < 0 && ret != -ENOIOCTLCMD) ++ goto err_pm_put; ++ } ++ return 0; ++ ++err_pm_put: ++ pm_runtime_put(video->stfcamss->dev); ++error: ++ video_device_pipeline_stop(vdev); ++ video->ops->flush_buffers(video, VB2_BUF_STATE_QUEUED); ++ return ret; ++} ++ ++static void video_stop_streaming(struct vb2_queue *q) ++{ ++ struct stfcamss_video *video = vb2_get_drv_priv(q); ++ struct video_device *vdev = &video->vdev; ++ struct media_entity *entity; ++ struct media_pad *pad; ++ struct v4l2_subdev *subdev; ++ int ret; ++ ++ entity = &vdev->entity; ++ while (1) { ++ pad = &entity->pads[0]; ++ if (!(pad->flags & MEDIA_PAD_FL_SINK)) ++ break; ++ ++ pad = media_pad_remote_pad_first(pad); ++ if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) ++ break; ++ ++ entity = pad->entity; ++ subdev = media_entity_to_v4l2_subdev(entity); ++ ++ v4l2_subdev_call(subdev, video, s_stream, 0); ++ } ++ ++ ret = pm_runtime_put(video->stfcamss->dev); ++ if (ret < 0) ++ dev_err(video->stfcamss->dev, "power down failed:%d\n", ret); ++ ++ video_device_pipeline_stop(vdev); ++ video->ops->flush_buffers(video, VB2_BUF_STATE_ERROR); ++} ++ ++static const struct vb2_ops stf_video_vb2_q_ops = { ++ .queue_setup = video_queue_setup, ++ .wait_prepare = vb2_ops_wait_prepare, ++ .wait_finish = vb2_ops_wait_finish, ++ .buf_init = video_buf_init, ++ .buf_prepare = video_buf_prepare, ++ .buf_queue = video_buf_queue, ++ .start_streaming = video_start_streaming, ++ .stop_streaming = video_stop_streaming, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * V4L2 ioctls ++ */ ++ ++static int video_querycap(struct file *file, void *fh, ++ struct v4l2_capability *cap) ++{ ++ strscpy(cap->driver, "stf camss", sizeof(cap->driver)); ++ strscpy(cap->card, "Starfive Camera Subsystem", sizeof(cap->card)); ++ ++ return 0; ++} ++ ++static int video_get_pfmt_by_index(struct stfcamss_video *video, int ndx) ++{ ++ int i, j, k; ++ ++ /* find index "i" of "k"th unique pixelformat in formats array */ ++ k = -1; ++ for (i = 0; i < video->nformats; i++) { ++ for (j = 0; j < i; j++) { ++ if (video->formats[i].pixelformat == ++ video->formats[j].pixelformat) ++ break; ++ } ++ ++ if (j == i) ++ k++; ++ ++ if (k == ndx) ++ return i; ++ } ++ ++ return -EINVAL; ++} ++ ++static int video_get_pfmt_by_mcode(struct stfcamss_video *video, u32 mcode) ++{ ++ int i; ++ ++ for (i = 0; i < video->nformats; i++) { ++ if (video->formats[i].code == mcode) ++ return i; ++ } ++ ++ return -EINVAL; ++} ++ ++static int video_enum_fmt(struct file *file, void *fh, struct v4l2_fmtdesc *f) ++{ ++ struct stfcamss_video *video = video_drvdata(file); ++ int i; ++ ++ if (f->type != video->type) ++ return -EINVAL; ++ if (f->index >= video->nformats) ++ return -EINVAL; ++ ++ if (f->mbus_code) { ++ /* Each entry in formats[] table has unique mbus_code */ ++ if (f->index > 0) ++ return -EINVAL; ++ ++ i = video_get_pfmt_by_mcode(video, f->mbus_code); ++ } else { ++ i = video_get_pfmt_by_index(video, f->index); ++ } ++ ++ if (i < 0) ++ return -EINVAL; ++ ++ f->pixelformat = video->formats[i].pixelformat; ++ ++ return 0; ++} ++ ++static int video_enum_framesizes(struct file *file, void *fh, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ struct stfcamss_video *video = video_drvdata(file); ++ int i; ++ ++ if (fsize->index) ++ return -EINVAL; ++ ++ for (i = 0; i < video->nformats; i++) { ++ if (video->formats[i].pixelformat == fsize->pixel_format) ++ break; ++ } ++ ++ if (i == video->nformats) ++ return -EINVAL; ++ ++ fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; ++ fsize->stepwise.min_width = STFCAMSS_FRAME_MIN_WIDTH; ++ fsize->stepwise.max_width = STFCAMSS_FRAME_MAX_WIDTH; ++ fsize->stepwise.min_height = STFCAMSS_FRAME_MIN_HEIGHT; ++ fsize->stepwise.max_height = STFCAMSS_FRAME_MAX_HEIGHT; ++ fsize->stepwise.step_width = 1; ++ fsize->stepwise.step_height = 1; ++ ++ return 0; ++} ++ ++static int video_g_fmt(struct file *file, void *fh, struct v4l2_format *f) ++{ ++ struct stfcamss_video *video = video_drvdata(file); ++ ++ *f = video->active_fmt; ++ ++ return 0; ++} ++ ++static int video_s_fmt(struct file *file, void *fh, struct v4l2_format *f) ++{ ++ struct stfcamss_video *video = video_drvdata(file); ++ int ret; ++ ++ if (vb2_is_busy(&video->vb2_q)) ++ return -EBUSY; ++ ++ ret = __video_try_fmt(video, f); ++ if (ret < 0) ++ return ret; ++ ++ video->active_fmt = *f; ++ ++ return 0; ++} ++ ++static int video_try_fmt(struct file *file, void *fh, struct v4l2_format *f) ++{ ++ struct stfcamss_video *video = video_drvdata(file); ++ ++ return __video_try_fmt(video, f); ++} ++ ++static const struct v4l2_ioctl_ops stf_vid_ioctl_ops = { ++ .vidioc_querycap = video_querycap, ++ .vidioc_enum_fmt_vid_cap = video_enum_fmt, ++ .vidioc_enum_fmt_vid_out = video_enum_fmt, ++ .vidioc_enum_framesizes = video_enum_framesizes, ++ .vidioc_g_fmt_vid_cap = video_g_fmt, ++ .vidioc_s_fmt_vid_cap = video_s_fmt, ++ .vidioc_try_fmt_vid_cap = video_try_fmt, ++ .vidioc_g_fmt_vid_out = video_g_fmt, ++ .vidioc_s_fmt_vid_out = video_s_fmt, ++ .vidioc_try_fmt_vid_out = video_try_fmt, ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_expbuf = vb2_ioctl_expbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * V4L2 file operations ++ */ ++ ++static const struct v4l2_file_operations stf_vid_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = video_ioctl2, ++ .open = v4l2_fh_open, ++ .release = vb2_fop_release, ++ .poll = vb2_fop_poll, ++ .mmap = vb2_fop_mmap, ++ .read = vb2_fop_read, ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * STFCAMSS video core ++ */ ++ ++static void stf_video_release(struct video_device *vdev) ++{ ++ struct stfcamss_video *video = video_get_drvdata(vdev); ++ ++ media_entity_cleanup(&vdev->entity); ++ ++ mutex_destroy(&video->q_lock); ++ mutex_destroy(&video->lock); ++} ++ ++int stf_video_register(struct stfcamss_video *video, ++ struct v4l2_device *v4l2_dev, const char *name) ++{ ++ struct video_device *vdev; ++ struct vb2_queue *q; ++ struct media_pad *pad = &video->pad; ++ int ret; ++ ++ vdev = &video->vdev; ++ ++ mutex_init(&video->q_lock); ++ ++ q = &video->vb2_q; ++ q->drv_priv = video; ++ q->mem_ops = &vb2_dma_contig_memops; ++ q->ops = &stf_video_vb2_q_ops; ++ q->type = video->type; ++ q->io_modes = VB2_DMABUF | VB2_MMAP | VB2_READ; ++ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ++ q->buf_struct_size = sizeof(struct stfcamss_buffer); ++ q->dev = video->stfcamss->dev; ++ q->lock = &video->q_lock; ++ q->min_buffers_needed = STFCAMSS_MIN_BUFFERS; ++ ret = vb2_queue_init(q); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, ++ "Failed to init vb2 queue: %d\n", ret); ++ goto err_vb2_init; ++ } ++ ++ pad->flags = MEDIA_PAD_FL_SINK; ++ ret = media_entity_pads_init(&vdev->entity, 1, pad); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, ++ "Failed to init video entity: %d\n", ret); ++ goto err_vb2_init; ++ } ++ ++ mutex_init(&video->lock); ++ ++ if (video->id == STF_V_LINE_WR) { ++ video->formats = formats_pix_wr; ++ video->nformats = ARRAY_SIZE(formats_pix_wr); ++ video->bpl_alignment = 8; ++ } else { ++ video->formats = formats_pix_isp; ++ video->nformats = ARRAY_SIZE(formats_pix_isp); ++ video->bpl_alignment = 1; ++ } ++ ++ ret = stf_video_init_format(video); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, ++ "Failed to init format: %d\n", ret); ++ goto err_vid_init_format; ++ } ++ ++ vdev->fops = &stf_vid_fops; ++ vdev->ioctl_ops = &stf_vid_ioctl_ops; ++ vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE; ++ vdev->vfl_dir = VFL_DIR_RX; ++ vdev->device_caps |= V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; ++ vdev->release = stf_video_release; ++ vdev->v4l2_dev = v4l2_dev; ++ vdev->queue = &video->vb2_q; ++ vdev->lock = &video->lock; ++ strscpy(vdev->name, name, sizeof(vdev->name)); ++ ++ ret = video_register_device(vdev, VFL_TYPE_VIDEO, video->id); ++ if (ret < 0) { ++ dev_err(video->stfcamss->dev, ++ "Failed to register video device: %d\n", ret); ++ goto err_vid_reg; ++ } ++ ++ video_set_drvdata(vdev, video); ++ return 0; ++ ++err_vid_reg: ++err_vid_init_format: ++ media_entity_cleanup(&vdev->entity); ++ mutex_destroy(&video->lock); ++err_vb2_init: ++ mutex_destroy(&video->q_lock); ++ return ret; ++} ++ ++void stf_video_unregister(struct stfcamss_video *video) ++{ ++ vb2_video_unregister_device(&video->vdev); ++} +diff --git a/drivers/media/platform/starfive/camss/stf_video.h b/drivers/media/platform/starfive/camss/stf_video.h +new file mode 100644 +index 000000000000..60323c23a40c +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_video.h +@@ -0,0 +1,92 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * stf_video.h ++ * ++ * StarFive Camera Subsystem - V4L2 device node ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef STF_VIDEO_H ++#define STF_VIDEO_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define STFCAMSS_FRAME_MIN_WIDTH 64 ++#define STFCAMSS_FRAME_MAX_WIDTH 1920 ++#define STFCAMSS_FRAME_MIN_HEIGHT 64 ++#define STFCAMSS_FRAME_MAX_HEIGHT 1080 ++#define STFCAMSS_FRAME_WIDTH_ALIGN_8 8 ++#define STFCAMSS_FRAME_WIDTH_ALIGN_128 128 ++#define STFCAMSS_MIN_BUFFERS 2 ++ ++#define STFCAMSS_MAX_ENTITY_NAME_LEN 27 ++ ++enum stf_v_line_id { ++ STF_V_LINE_WR = 0, ++ STF_V_LINE_ISP, ++ STF_V_LINE_MAX, ++}; ++ ++struct stfcamss_buffer { ++ struct vb2_v4l2_buffer vb; ++ dma_addr_t addr[3]; ++ struct list_head queue; ++}; ++ ++struct fract { ++ u8 numerator; ++ u8 denominator; ++}; ++ ++/* ++ * struct stfcamss_format_info - ISP media bus format information ++ * @code: V4L2 media bus format code ++ * @pixelformat: V4L2 pixel format FCC identifier ++ * @planes: Number of planes ++ * @vsub: Vertical subsampling (for each plane) ++ * @bpp: Bits per pixel when stored in memory (for each plane) ++ */ ++struct stfcamss_format_info { ++ u32 code; ++ u32 pixelformat; ++ u8 planes; ++ u8 vsub[3]; ++ u8 bpp; ++}; ++ ++struct stfcamss_video { ++ struct stfcamss *stfcamss; ++ u8 id; ++ struct vb2_queue vb2_q; ++ struct video_device vdev; ++ struct media_pad pad; ++ struct v4l2_format active_fmt; ++ enum v4l2_buf_type type; ++ const struct stfcamss_video_ops *ops; ++ struct mutex lock; /* serialize device access */ ++ struct mutex q_lock; /* protects the queue */ ++ unsigned int bpl_alignment; ++ const struct stfcamss_format_info *formats; ++ unsigned int nformats; ++}; ++ ++struct stfcamss_video_ops { ++ int (*queue_buffer)(struct stfcamss_video *vid, ++ struct stfcamss_buffer *buf); ++ int (*flush_buffers)(struct stfcamss_video *vid, ++ enum vb2_buffer_state state); ++}; ++ ++int stf_video_register(struct stfcamss_video *video, ++ struct v4l2_device *v4l2_dev, const char *name); ++ ++void stf_video_unregister(struct stfcamss_video *video); ++ ++#endif /* STF_VIDEO_H */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0048-media-starfive-camss-Add-ISP-driver.patch b/srcpkgs/linux6.4/patches/0048-media-starfive-camss-Add-ISP-driver.patch new file mode 100644 index 0000000000000..d858044819edd --- /dev/null +++ b/srcpkgs/linux6.4/patches/0048-media-starfive-camss-Add-ISP-driver.patch @@ -0,0 +1,1674 @@ +From 646ca4ece4da54fcc899c37e8553e1e2e4ed9717 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:37 +0800 +Subject: [PATCH 48/72] media: starfive: camss: Add ISP driver + +Add ISP driver for StarFive Camera Subsystem. + +Signed-off-by: Jack Zhu +--- + .../media/platform/starfive/camss/Makefile | 2 + + .../media/platform/starfive/camss/stf_camss.c | 76 ++- + .../media/platform/starfive/camss/stf_camss.h | 3 + + .../media/platform/starfive/camss/stf_isp.c | 519 ++++++++++++++++++ + .../media/platform/starfive/camss/stf_isp.h | 479 ++++++++++++++++ + .../platform/starfive/camss/stf_isp_hw_ops.c | 468 ++++++++++++++++ + 6 files changed, 1544 insertions(+), 3 deletions(-) + create mode 100644 drivers/media/platform/starfive/camss/stf_isp.c + create mode 100644 drivers/media/platform/starfive/camss/stf_isp.h + create mode 100644 drivers/media/platform/starfive/camss/stf_isp_hw_ops.c + +diff --git a/drivers/media/platform/starfive/camss/Makefile b/drivers/media/platform/starfive/camss/Makefile +index eb457917a914..cdf57e8c9546 100644 +--- a/drivers/media/platform/starfive/camss/Makefile ++++ b/drivers/media/platform/starfive/camss/Makefile +@@ -5,6 +5,8 @@ + + starfive-camss-objs += \ + stf_camss.o \ ++ stf_isp.o \ ++ stf_isp_hw_ops.o \ + stf_video.o + + obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive-camss.o +diff --git a/drivers/media/platform/starfive/camss/stf_camss.c b/drivers/media/platform/starfive/camss/stf_camss.c +index dc2b5dba7bd4..6f56b45f57db 100644 +--- a/drivers/media/platform/starfive/camss/stf_camss.c ++++ b/drivers/media/platform/starfive/camss/stf_camss.c +@@ -115,12 +115,65 @@ static int stfcamss_of_parse_ports(struct stfcamss *stfcamss) + return ret; + } + ++/* ++ * stfcamss_init_subdevices - Initialize subdev structures and resources ++ * @stfcamss: STFCAMSS device ++ * ++ * Return 0 on success or a negative error code on failure ++ */ ++static int stfcamss_init_subdevices(struct stfcamss *stfcamss) ++{ ++ int ret; ++ ++ ret = stf_isp_subdev_init(stfcamss); ++ if (ret < 0) { ++ dev_err(stfcamss->dev, "Failed to init isp subdev: %d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static int stfcamss_register_subdevices(struct stfcamss *stfcamss) ++{ ++ int ret; ++ struct stf_isp_dev *isp_dev = &stfcamss->isp_dev; ++ ++ ret = stf_isp_register(isp_dev, &stfcamss->v4l2_dev); ++ if (ret < 0) { ++ dev_err(stfcamss->dev, ++ "Failed to register stf isp%d entity: %d\n", 0, ret); ++ return ret; ++ } ++ ++ return ret; ++} ++ ++static void stfcamss_unregister_subdevices(struct stfcamss *stfcamss) ++{ ++ stf_isp_unregister(&stfcamss->isp_dev); ++} ++ + static int stfcamss_subdev_notifier_bound(struct v4l2_async_notifier *async, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) + { ++ struct stfcamss *stfcamss = ++ container_of(async, struct stfcamss, notifier); ++ struct stfcamss_async_subdev *csd = ++ container_of(asd, struct stfcamss_async_subdev, asd); ++ enum stf_port_num port = csd->port; ++ struct stf_isp_dev *isp_dev = &stfcamss->isp_dev; + struct media_pad *pad[STF_PADS_NUM]; +- unsigned int i, pad_num = 0; ++ unsigned int i, pad_num; ++ ++ if (port == STF_PORT_CSI2RX) { ++ pad[0] = &isp_dev->pads[STF_PAD_SINK]; ++ pad_num = 1; ++ } else if (port == STF_PORT_DVP) { ++ dev_err(stfcamss->dev, "Not support DVP sensor\n"); ++ return -EPERM; ++ } + + for (i = 0; i < pad_num; ++i) { + int ret; +@@ -223,12 +276,18 @@ static int stfcamss_probe(struct platform_device *pdev) + goto err_cleanup_notifier; + } + ++ ret = stfcamss_init_subdevices(stfcamss); ++ if (ret < 0) { ++ dev_err(dev, "Failed to init subdevice: %d\n", ret); ++ goto err_cleanup_notifier; ++ } ++ + stfcamss_mc_init(pdev, stfcamss); + + ret = v4l2_device_register(stfcamss->dev, &stfcamss->v4l2_dev); + if (ret < 0) { + dev_err(dev, "Failed to register V4L2 device: %d\n", ret); +- goto err_cleanup_notifier; ++ goto err_cleanup_media_device; + } + + ret = media_device_register(&stfcamss->media_dev); +@@ -237,6 +296,12 @@ static int stfcamss_probe(struct platform_device *pdev) + goto err_unregister_device; + } + ++ ret = stfcamss_register_subdevices(stfcamss); ++ if (ret < 0) { ++ dev_err(dev, "Failed to register subdevice: %d\n", ret); ++ goto err_unregister_media_dev; ++ } ++ + pm_runtime_enable(dev); + + stfcamss->notifier.ops = &stfcamss_subdev_notifier_ops; +@@ -244,15 +309,19 @@ static int stfcamss_probe(struct platform_device *pdev) + if (ret) { + dev_err(dev, "Failed to register async subdev nodes: %d\n", + ret); +- goto err_unregister_media_dev; ++ goto err_unregister_subdevs; + } + + return 0; + ++err_unregister_subdevs: ++ stfcamss_unregister_subdevices(stfcamss); + err_unregister_media_dev: + media_device_unregister(&stfcamss->media_dev); + err_unregister_device: + v4l2_device_unregister(&stfcamss->v4l2_dev); ++err_cleanup_media_device: ++ media_device_cleanup(&stfcamss->media_dev); + err_cleanup_notifier: + v4l2_async_nf_cleanup(&stfcamss->notifier); + return ret; +@@ -268,6 +337,7 @@ static int stfcamss_remove(struct platform_device *pdev) + { + struct stfcamss *stfcamss = platform_get_drvdata(pdev); + ++ stfcamss_unregister_subdevices(stfcamss); + v4l2_device_unregister(&stfcamss->v4l2_dev); + media_device_cleanup(&stfcamss->media_dev); + pm_runtime_disable(&pdev->dev); +diff --git a/drivers/media/platform/starfive/camss/stf_camss.h b/drivers/media/platform/starfive/camss/stf_camss.h +index 15c4f34b9054..9482081288fa 100644 +--- a/drivers/media/platform/starfive/camss/stf_camss.h ++++ b/drivers/media/platform/starfive/camss/stf_camss.h +@@ -18,6 +18,8 @@ + #include + #include + ++#include "stf_isp.h" ++ + #define STF_DVP_NAME "stf_dvp" + #define STF_CSI_NAME "cdns_csi2rx" + #define STF_ISP_NAME "stf_isp" +@@ -65,6 +67,7 @@ struct stfcamss { + struct media_device media_dev; + struct media_pipeline pipe; + struct device *dev; ++ struct stf_isp_dev isp_dev; + struct v4l2_async_notifier notifier; + void __iomem *syscon_base; + void __iomem *isp_base; +diff --git a/drivers/media/platform/starfive/camss/stf_isp.c b/drivers/media/platform/starfive/camss/stf_isp.c +new file mode 100644 +index 000000000000..933a583b398c +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_isp.c +@@ -0,0 +1,519 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_isp.c ++ * ++ * StarFive Camera Subsystem - ISP Module ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++#include ++#include ++ ++#include "stf_camss.h" ++ ++#define SINK_FORMATS_INDEX 0 ++#define UO_FORMATS_INDEX 1 ++ ++static int isp_set_selection(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_selection *sel); ++ ++static const struct isp_format isp_formats_sink[] = { ++ { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, ++ { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, ++ { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, ++ { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, ++}; ++ ++static const struct isp_format isp_formats_uo[] = { ++ { MEDIA_BUS_FMT_Y12_1X12, 8 }, ++}; ++ ++static const struct isp_format_table isp_formats_st7110[] = { ++ { isp_formats_sink, ARRAY_SIZE(isp_formats_sink) }, ++ { isp_formats_uo, ARRAY_SIZE(isp_formats_uo) }, ++}; ++ ++int stf_isp_subdev_init(struct stfcamss *stfcamss) ++{ ++ struct stf_isp_dev *isp_dev = &stfcamss->isp_dev; ++ ++ isp_dev->stfcamss = stfcamss; ++ isp_dev->formats = isp_formats_st7110; ++ isp_dev->nformats = ARRAY_SIZE(isp_formats_st7110); ++ ++ mutex_init(&isp_dev->stream_lock); ++ return 0; ++} ++ ++static struct v4l2_mbus_framefmt * ++__isp_get_format(struct stf_isp_dev *isp_dev, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ enum v4l2_subdev_format_whence which) ++{ ++ if (which == V4L2_SUBDEV_FORMAT_TRY) ++ return v4l2_subdev_get_try_format(&isp_dev->subdev, state, pad); ++ ++ return &isp_dev->fmt[pad]; ++} ++ ++static int isp_set_stream(struct v4l2_subdev *sd, int enable) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ int ret = 0; ++ struct v4l2_mbus_framefmt *fmt; ++ struct v4l2_event src_ch = { 0 }; ++ ++ fmt = __isp_get_format(isp_dev, NULL, STF_ISP_PAD_SINK, ++ V4L2_SUBDEV_FORMAT_ACTIVE); ++ mutex_lock(&isp_dev->stream_lock); ++ if (enable) { ++ if (isp_dev->stream_count == 0) { ++ stf_isp_clk_enable(isp_dev); ++ stf_isp_reset(isp_dev); ++ stf_isp_init_cfg(isp_dev); ++ stf_isp_settings(isp_dev, isp_dev->rect, fmt->code); ++ stf_isp_stream_set(isp_dev); ++ } ++ isp_dev->stream_count++; ++ } else { ++ if (isp_dev->stream_count == 0) ++ goto exit; ++ ++ if (isp_dev->stream_count == 1) ++ stf_isp_clk_disable(isp_dev); ++ ++ isp_dev->stream_count--; ++ } ++ src_ch.type = V4L2_EVENT_SOURCE_CHANGE, ++ src_ch.u.src_change.changes = isp_dev->stream_count, ++ ++ v4l2_subdev_notify_event(sd, &src_ch); ++exit: ++ mutex_unlock(&isp_dev->stream_lock); ++ ++ return ret; ++} ++ ++static void isp_try_format(struct stf_isp_dev *isp_dev, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ struct v4l2_mbus_framefmt *fmt, ++ enum v4l2_subdev_format_whence which) ++{ ++ const struct isp_format_table *formats; ++ struct stf_isp_crop *rect; ++ unsigned int i; ++ ++ if (pad == STF_ISP_PAD_SINK) { ++ /* Set format on sink pad */ ++ formats = &isp_dev->formats[SINK_FORMATS_INDEX]; ++ rect = &isp_dev->rect[SINK_FORMATS_INDEX]; ++ } else if (pad == STF_ISP_PAD_SRC) { ++ formats = &isp_dev->formats[UO_FORMATS_INDEX]; ++ rect = &isp_dev->rect[UO_FORMATS_INDEX]; ++ } ++ ++ fmt->width = clamp_t(u32, fmt->width, STFCAMSS_FRAME_MIN_WIDTH, ++ STFCAMSS_FRAME_MAX_WIDTH); ++ fmt->height = clamp_t(u32, fmt->height, STFCAMSS_FRAME_MIN_HEIGHT, ++ STFCAMSS_FRAME_MAX_HEIGHT); ++ fmt->height &= ~0x1; ++ fmt->field = V4L2_FIELD_NONE; ++ fmt->colorspace = V4L2_COLORSPACE_SRGB; ++ fmt->flags = 0; ++ ++ for (i = 0; i < formats->nfmts; i++) { ++ if (fmt->code == formats->fmts[i].code) ++ break; ++ } ++ ++ if (i >= formats->nfmts) { ++ fmt->code = formats->fmts[0].code; ++ rect->bpp = formats->fmts[0].bpp; ++ } else { ++ rect->bpp = formats->fmts[i].bpp; ++ } ++} ++ ++static int isp_enum_mbus_code(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_mbus_code_enum *code) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ const struct isp_format_table *formats; ++ ++ if (code->index >= isp_dev->nformats) ++ return -EINVAL; ++ if (code->pad == STF_ISP_PAD_SINK) { ++ formats = &isp_dev->formats[SINK_FORMATS_INDEX]; ++ code->code = formats->fmts[code->index].code; ++ } else { ++ struct v4l2_mbus_framefmt *sink_fmt; ++ ++ sink_fmt = __isp_get_format(isp_dev, state, STF_ISP_PAD_SINK, ++ code->which); ++ ++ code->code = sink_fmt->code; ++ if (!code->code) ++ return -EINVAL; ++ } ++ code->flags = 0; ++ ++ return 0; ++} ++ ++static int isp_enum_frame_size(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_frame_size_enum *fse) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt format; ++ ++ if (fse->index != 0) ++ return -EINVAL; ++ ++ format.code = fse->code; ++ format.width = 1; ++ format.height = 1; ++ isp_try_format(isp_dev, state, fse->pad, &format, fse->which); ++ fse->min_width = format.width; ++ fse->min_height = format.height; ++ ++ if (format.code != fse->code) ++ return -EINVAL; ++ ++ format.code = fse->code; ++ format.width = -1; ++ format.height = -1; ++ isp_try_format(isp_dev, state, fse->pad, &format, fse->which); ++ fse->max_width = format.width; ++ fse->max_height = format.height; ++ ++ return 0; ++} ++ ++static int isp_get_format(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_format *fmt) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt *format; ++ ++ format = __isp_get_format(isp_dev, state, fmt->pad, fmt->which); ++ if (!format) ++ return -EINVAL; ++ ++ fmt->format = *format; ++ ++ return 0; ++} ++ ++static int isp_set_format(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_format *fmt) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt *format; ++ ++ format = __isp_get_format(isp_dev, state, fmt->pad, fmt->which); ++ if (!format) ++ return -EINVAL; ++ ++ mutex_lock(&isp_dev->stream_lock); ++ ++ isp_try_format(isp_dev, state, fmt->pad, &fmt->format, fmt->which); ++ *format = fmt->format; ++ ++ mutex_unlock(&isp_dev->stream_lock); ++ ++ /* Propagate to in crop */ ++ if (fmt->pad == STF_ISP_PAD_SINK) { ++ struct v4l2_subdev_selection sel = { 0 }; ++ int ret; ++ ++ /* Reset sink pad compose selection */ ++ sel.which = fmt->which; ++ sel.pad = STF_ISP_PAD_SINK; ++ sel.target = V4L2_SEL_TGT_CROP; ++ sel.r.width = fmt->format.width; ++ sel.r.height = fmt->format.height; ++ ret = isp_set_selection(sd, state, &sel); ++ if (ret < 0) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static struct v4l2_rect * ++__isp_get_crop(struct stf_isp_dev *isp_dev, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ enum v4l2_subdev_format_whence which) ++{ ++ if (which == V4L2_SUBDEV_FORMAT_TRY) ++ return v4l2_subdev_get_try_crop(&isp_dev->subdev, state, ++ STF_ISP_PAD_SINK); ++ ++ return &isp_dev->rect[pad].rect; ++} ++ ++static void isp_try_crop(struct stf_isp_dev *isp_dev, ++ struct v4l2_subdev_state *state, ++ struct v4l2_rect *rect, ++ enum v4l2_subdev_format_whence which) ++{ ++ struct v4l2_mbus_framefmt *fmt; ++ ++ fmt = __isp_get_format(isp_dev, state, STF_ISP_PAD_SINK, which); ++ ++ if (rect->width > fmt->width) ++ rect->width = fmt->width; ++ ++ if (rect->width + rect->left > fmt->width) ++ rect->left = fmt->width - rect->width; ++ ++ if (rect->height > fmt->height) ++ rect->height = fmt->height; ++ ++ if (rect->height + rect->top > fmt->height) ++ rect->top = fmt->height - rect->height; ++ ++ if (rect->width < STFCAMSS_FRAME_MIN_WIDTH) { ++ rect->left = 0; ++ rect->width = STFCAMSS_FRAME_MAX_WIDTH; ++ } ++ ++ if (rect->height < STFCAMSS_FRAME_MIN_HEIGHT) { ++ rect->top = 0; ++ rect->height = STFCAMSS_FRAME_MAX_HEIGHT; ++ } ++ rect->height &= ~0x1; ++} ++ ++static int isp_get_selection(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ struct v4l2_subdev_format fmt = { 0 }; ++ struct v4l2_rect *rect; ++ int ret; ++ ++ switch (sel->target) { ++ case V4L2_SEL_TGT_CROP_BOUNDS: ++ if (sel->pad == STF_ISP_PAD_SINK) { ++ fmt.pad = sel->pad; ++ fmt.which = sel->which; ++ ret = isp_get_format(sd, state, &fmt); ++ if (ret < 0) ++ return ret; ++ ++ sel->r.left = 0; ++ sel->r.top = 0; ++ sel->r.width = fmt.format.width; ++ sel->r.height = fmt.format.height; ++ } else if (sel->pad == STF_ISP_PAD_SRC) { ++ rect = __isp_get_crop(isp_dev, state, ++ sel->pad, sel->which); ++ sel->r = *rect; ++ } ++ break; ++ ++ case V4L2_SEL_TGT_CROP: ++ rect = __isp_get_crop(isp_dev, state, sel->pad, sel->which); ++ if (!rect) ++ return -EINVAL; ++ ++ sel->r = *rect; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int isp_set_selection(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_selection *sel) ++{ ++ struct stf_isp_dev *isp_dev = v4l2_get_subdevdata(sd); ++ struct v4l2_rect *rect; ++ int ret = 0; ++ ++ if (sel->target == V4L2_SEL_TGT_CROP && ++ sel->pad == STF_ISP_PAD_SINK) { ++ struct v4l2_subdev_selection crop = { 0 }; ++ ++ rect = __isp_get_crop(isp_dev, state, sel->pad, sel->which); ++ if (!rect) ++ return -EINVAL; ++ ++ mutex_lock(&isp_dev->stream_lock); ++ isp_try_crop(isp_dev, state, &sel->r, sel->which); ++ *rect = sel->r; ++ mutex_unlock(&isp_dev->stream_lock); ++ ++ /* Reset source crop selection */ ++ crop.which = sel->which; ++ crop.pad = STF_ISP_PAD_SRC; ++ crop.target = V4L2_SEL_TGT_CROP; ++ crop.r = *rect; ++ ret = isp_set_selection(sd, state, &crop); ++ } else if (sel->target == V4L2_SEL_TGT_CROP && ++ sel->pad == STF_ISP_PAD_SRC) { ++ struct v4l2_subdev_format fmt = { 0 }; ++ ++ rect = __isp_get_crop(isp_dev, state, sel->pad, sel->which); ++ if (!rect) ++ return -EINVAL; ++ ++ mutex_lock(&isp_dev->stream_lock); ++ isp_try_crop(isp_dev, state, &sel->r, sel->which); ++ *rect = sel->r; ++ mutex_unlock(&isp_dev->stream_lock); ++ ++ /* Reset source pad format width and height */ ++ fmt.which = sel->which; ++ fmt.pad = STF_ISP_PAD_SRC; ++ fmt.format.width = rect->width; ++ fmt.format.height = rect->height; ++ ret = isp_set_format(sd, state, &fmt); ++ if (ret < 0) ++ return ret; ++ } ++ ++ dev_dbg(isp_dev->stfcamss->dev, "pad: %d sel(%d,%d)/%dx%d\n", ++ sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height); ++ ++ return 0; ++} ++ ++static int isp_init_formats(struct v4l2_subdev *sd, ++ struct v4l2_subdev_fh *fh) ++{ ++ struct v4l2_subdev_format format = { ++ .pad = STF_ISP_PAD_SINK, ++ .which = ++ fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE, ++ .format = { ++ .code = MEDIA_BUS_FMT_RGB565_2X8_LE, ++ .width = 1920, ++ .height = 1080 ++ } ++ }; ++ ++ return isp_set_format(sd, fh ? fh->state : NULL, &format); ++} ++ ++static int isp_link_setup(struct media_entity *entity, ++ const struct media_pad *local, ++ const struct media_pad *remote, u32 flags) ++{ ++ if (flags & MEDIA_LNK_FL_ENABLED) ++ if (media_pad_remote_pad_first(local)) ++ return -EBUSY; ++ return 0; ++} ++ ++static int stf_isp_subscribe_event(struct v4l2_subdev *sd, ++ struct v4l2_fh *fh, ++ struct v4l2_event_subscription *sub) ++{ ++ switch (sub->type) { ++ case V4L2_EVENT_SOURCE_CHANGE: ++ return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); ++ default: ++ return -EINVAL; ++ } ++} ++ ++static const struct v4l2_subdev_core_ops isp_core_ops = { ++ .subscribe_event = stf_isp_subscribe_event, ++ .unsubscribe_event = v4l2_event_subdev_unsubscribe, ++}; ++ ++static const struct v4l2_subdev_video_ops isp_video_ops = { ++ .s_stream = isp_set_stream, ++}; ++ ++static const struct v4l2_subdev_pad_ops isp_pad_ops = { ++ .enum_mbus_code = isp_enum_mbus_code, ++ .enum_frame_size = isp_enum_frame_size, ++ .get_fmt = isp_get_format, ++ .set_fmt = isp_set_format, ++ .get_selection = isp_get_selection, ++ .set_selection = isp_set_selection, ++}; ++ ++static const struct v4l2_subdev_ops isp_v4l2_ops = { ++ .core = &isp_core_ops, ++ .video = &isp_video_ops, ++ .pad = &isp_pad_ops, ++}; ++ ++static const struct v4l2_subdev_internal_ops isp_v4l2_internal_ops = { ++ .open = isp_init_formats, ++}; ++ ++static const struct media_entity_operations isp_media_ops = { ++ .link_setup = isp_link_setup, ++ .link_validate = v4l2_subdev_link_validate, ++}; ++ ++int stf_isp_register(struct stf_isp_dev *isp_dev, struct v4l2_device *v4l2_dev) ++{ ++ struct v4l2_subdev *sd = &isp_dev->subdev; ++ struct media_pad *pads = isp_dev->pads; ++ int ret; ++ ++ v4l2_subdev_init(sd, &isp_v4l2_ops); ++ sd->internal_ops = &isp_v4l2_internal_ops; ++ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; ++ snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", STF_ISP_NAME, 0); ++ v4l2_set_subdevdata(sd, isp_dev); ++ ++ ret = isp_init_formats(sd, NULL); ++ if (ret < 0) { ++ dev_err(isp_dev->stfcamss->dev, "Failed to init format: %d\n", ++ ret); ++ return ret; ++ } ++ ++ pads[STF_ISP_PAD_SINK].flags = MEDIA_PAD_FL_SINK; ++ pads[STF_ISP_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; ++ ++ sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; ++ sd->entity.ops = &isp_media_ops; ++ ret = media_entity_pads_init(&sd->entity, STF_ISP_PAD_MAX, pads); ++ if (ret < 0) { ++ dev_err(isp_dev->stfcamss->dev, ++ "Failed to init media entity: %d\n", ret); ++ return ret; ++ } ++ ++ ret = v4l2_device_register_subdev(v4l2_dev, sd); ++ if (ret < 0) { ++ dev_err(isp_dev->stfcamss->dev, ++ "Failed to register subdev: %d\n", ret); ++ goto err_sreg; ++ } ++ ++ return 0; ++ ++err_sreg: ++ media_entity_cleanup(&sd->entity); ++ return ret; ++} ++ ++int stf_isp_unregister(struct stf_isp_dev *isp_dev) ++{ ++ v4l2_device_unregister_subdev(&isp_dev->subdev); ++ media_entity_cleanup(&isp_dev->subdev.entity); ++ mutex_destroy(&isp_dev->stream_lock); ++ return 0; ++} +diff --git a/drivers/media/platform/starfive/camss/stf_isp.h b/drivers/media/platform/starfive/camss/stf_isp.h +new file mode 100644 +index 000000000000..1e5c98482350 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_isp.h +@@ -0,0 +1,479 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * stf_isp.h ++ * ++ * StarFive Camera Subsystem - ISP Module ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef STF_ISP_H ++#define STF_ISP_H ++ ++#include ++ ++#include "stf_video.h" ++ ++#define ISP_RAW_DATA_BITS 12 ++#define SCALER_RATIO_MAX 1 ++#define STF_ISP_REG_OFFSET_MAX 0x0fff ++#define STF_ISP_REG_DELAY_MAX 100 ++ ++/* isp registers */ ++#define ISP_REG_CSI_INPUT_EN_AND_STATUS 0x000 ++#define CSI_SCD_ERR BIT(6) ++#define CSI_ITU656_ERR BIT(4) ++#define CSI_ITU656_F BIT(3) ++#define CSI_SCD_DONE BIT(2) ++#define CSI_BUSY_S BIT(1) ++#define CSI_EN_S BIT(0) ++ ++#define ISP_REG_CSIINTS 0x008 ++#define CSI_INTS(n) ((n) << 16) ++#define CSI_SHA_M(n) ((n) << 0) ++#define CSI_INTS_MASK GENMASK(17, 16) ++ ++#define ISP_REG_CSI_MODULE_CFG 0x010 ++#define CSI_DUMP_EN BIT(19) ++#define CSI_VS_EN BIT(18) ++#define CSI_SC_EN BIT(17) ++#define CSI_OBA_EN BIT(16) ++#define CSI_AWB_EN BIT(7) ++#define CSI_LCCF_EN BIT(6) ++#define CSI_OECFHM_EN BIT(5) ++#define CSI_OECF_EN BIT(4) ++#define CSI_LCBQ_EN BIT(3) ++#define CSI_OBC_EN BIT(2) ++#define CSI_DEC_EN BIT(1) ++#define CSI_DC_EN BIT(0) ++ ++#define ISP_REG_SENSOR 0x014 ++#define DVP_SYNC_POL(n) ((n) << 2) ++#define ITU656_EN(n) ((n) << 1) ++#define IMAGER_SEL(n) ((n) << 0) ++ ++#define ISP_REG_RAW_FORMAT_CFG 0x018 ++#define SMY13(n) ((n) << 14) ++#define SMY12(n) ((n) << 12) ++#define SMY11(n) ((n) << 10) ++#define SMY10(n) ((n) << 8) ++#define SMY3(n) ((n) << 6) ++#define SMY2(n) ((n) << 4) ++#define SMY1(n) ((n) << 2) ++#define SMY0(n) ((n) << 0) ++ ++#define ISP_REG_PIC_CAPTURE_START_CFG 0x01c ++#define VSTART_CAP(n) ((n) << 16) ++#define HSTART_CAP(n) ((n) << 0) ++ ++#define ISP_REG_PIC_CAPTURE_END_CFG 0x020 ++#define VEND_CAP(n) ((n) << 16) ++#define HEND_CAP(n) ((n) << 0) ++ ++#define ISP_REG_DUMP_CFG_0 0x024 ++#define ISP_REG_DUMP_CFG_1 0x028 ++#define DUMP_ID(n) ((n) << 24) ++#define DUMP_SHT(n) ((n) << 20) ++#define DUMP_BURST_LEN(n) ((n) << 16) ++#define DUMP_SD(n) ((n) << 0) ++#define DUMP_BURST_LEN_MASK GENMASK(17, 16) ++#define DUMP_SD_MASK GENMASK(15, 0) ++ ++#define ISP_REG_DEC_CFG 0x030 ++#define DEC_V_KEEP(n) ((n) << 24) ++#define DEC_V_PERIOD(n) ((n) << 16) ++#define DEC_H_KEEP(n) ((n) << 8) ++#define DEC_H_PERIOD(n) ((n) << 0) ++ ++#define ISP_REG_OBC_CFG 0x034 ++#define OBC_W_H(y) ((y) << 4) ++#define OBC_W_W(x) ((x) << 0) ++ ++#define ISP_REG_DC_CFG_1 0x044 ++#define DC_AXI_ID(n) ((n) << 0) ++ ++#define ISP_REG_LCCF_CFG_0 0x050 ++#define Y_DISTANCE(y) ((y) << 16) ++#define X_DISTANCE(x) ((x) << 0) ++ ++#define ISP_REG_LCCF_CFG_1 0x058 ++#define LCCF_MAX_DIS(n) ((n) << 0) ++ ++#define ISP_REG_LCBQ_CFG_0 0x074 ++#define H_LCBQ(y) ((y) << 12) ++#define W_LCBQ(x) ((x) << 8) ++ ++#define ISP_REG_LCBQ_CFG_1 0x07c ++#define Y_COOR(y) ((y) << 16) ++#define X_COOR(x) ((x) << 0) ++ ++#define ISP_REG_LCCF_CFG_2 0x0e0 ++#define ISP_REG_LCCF_CFG_3 0x0e4 ++#define ISP_REG_LCCF_CFG_4 0x0e8 ++#define ISP_REG_LCCF_CFG_5 0x0ec ++#define LCCF_F2_PAR(n) ((n) << 16) ++#define LCCF_F1_PAR(n) ((n) << 0) ++ ++#define ISP_REG_OECF_X0_CFG0 0x100 ++#define ISP_REG_OECF_X0_CFG1 0x104 ++#define ISP_REG_OECF_X0_CFG2 0x108 ++#define ISP_REG_OECF_X0_CFG3 0x10c ++#define ISP_REG_OECF_X0_CFG4 0x110 ++#define ISP_REG_OECF_X0_CFG5 0x114 ++#define ISP_REG_OECF_X0_CFG6 0x118 ++#define ISP_REG_OECF_X0_CFG7 0x11c ++ ++#define ISP_REG_OECF_Y3_CFG0 0x1e0 ++#define ISP_REG_OECF_Y3_CFG1 0x1e4 ++#define ISP_REG_OECF_Y3_CFG2 0x1e8 ++#define ISP_REG_OECF_Y3_CFG3 0x1ec ++#define ISP_REG_OECF_Y3_CFG4 0x1f0 ++#define ISP_REG_OECF_Y3_CFG5 0x1f4 ++#define ISP_REG_OECF_Y3_CFG6 0x1f8 ++#define ISP_REG_OECF_Y3_CFG7 0x1fc ++ ++#define ISP_REG_OECF_S0_CFG0 0x200 ++#define ISP_REG_OECF_S3_CFG7 0x27c ++#define OCEF_PAR_H(n) ((n) << 16) ++#define OCEF_PAR_L(n) ((n) << 0) ++ ++#define ISP_REG_AWB_X0_CFG_0 0x280 ++#define ISP_REG_AWB_X0_CFG_1 0x284 ++#define ISP_REG_AWB_X1_CFG_0 0x288 ++#define ISP_REG_AWB_X1_CFG_1 0x28c ++#define ISP_REG_AWB_X2_CFG_0 0x290 ++#define ISP_REG_AWB_X2_CFG_1 0x294 ++#define ISP_REG_AWB_X3_CFG_0 0x298 ++#define ISP_REG_AWB_X3_CFG_1 0x29c ++#define AWB_X_SYMBOL_H(n) ((n) << 16) ++#define AWB_X_SYMBOL_L(n) ((n) << 0) ++ ++#define ISP_REG_AWB_Y0_CFG_0 0x2a0 ++#define ISP_REG_AWB_Y0_CFG_1 0x2a4 ++#define ISP_REG_AWB_Y1_CFG_0 0x2a8 ++#define ISP_REG_AWB_Y1_CFG_1 0x2ac ++#define ISP_REG_AWB_Y2_CFG_0 0x2b0 ++#define ISP_REG_AWB_Y2_CFG_1 0x2b4 ++#define ISP_REG_AWB_Y3_CFG_0 0x2b8 ++#define ISP_REG_AWB_Y3_CFG_1 0x2bc ++#define AWB_Y_SYMBOL_H(n) ((n) << 16) ++#define AWB_Y_SYMBOL_L(n) ((n) << 0) ++ ++#define ISP_REG_AWB_S0_CFG_0 0x2c0 ++#define ISP_REG_AWB_S0_CFG_1 0x2c4 ++#define ISP_REG_AWB_S1_CFG_0 0x2c8 ++#define ISP_REG_AWB_S1_CFG_1 0x2cc ++#define ISP_REG_AWB_S2_CFG_0 0x2d0 ++#define ISP_REG_AWB_S2_CFG_1 0x2d4 ++#define ISP_REG_AWB_S3_CFG_0 0x2d8 ++#define ISP_REG_AWB_S3_CFG_1 0x2dc ++#define AWB_S_SYMBOL_H(n) ((n) << 16) ++#define AWB_S_SYMBOL_L(n) ((n) << 0) ++ ++#define ISP_REG_OBCG_CFG_0 0x2e0 ++#define ISP_REG_OBCG_CFG_1 0x2e4 ++#define ISP_REG_OBCG_CFG_2 0x2e8 ++#define ISP_REG_OBCG_CFG_3 0x2ec ++#define ISP_REG_OBCO_CFG_0 0x2f0 ++#define ISP_REG_OBCO_CFG_1 0x2f4 ++#define ISP_REG_OBCO_CFG_2 0x2f8 ++#define ISP_REG_OBCO_CFG_3 0x2fc ++#define GAIN_D_POINT(x) ((x) << 24) ++#define GAIN_C_POINT(x) ((x) << 16) ++#define GAIN_B_POINT(x) ((x) << 8) ++#define GAIN_A_POINT(x) ((x) << 0) ++#define OFFSET_D_POINT(x) ((x) << 24) ++#define OFFSET_C_POINT(x) ((x) << 16) ++#define OFFSET_B_POINT(x) ((x) << 8) ++#define OFFSET_A_POINT(x) ((x) << 0) ++ ++#define ISP_REG_ISP_CTRL_0 0xa00 ++#define ISPC_SCFEINT BIT(27) ++#define ISPC_VSFWINT BIT(26) ++#define ISPC_VSINT BIT(25) ++#define ISPC_INTS BIT(24) ++#define ISPC_ENUO BIT(20) ++#define ISPC_ENLS BIT(17) ++#define ISPC_ENSS1 BIT(12) ++#define ISPC_ENSS0 BIT(11) ++#define ISPC_RST BIT(1) ++#define ISPC_EN BIT(0) ++#define ISPC_RST_MASK BIT(1) ++ ++#define ISP_REG_ISP_CTRL_1 0xa08 ++#define CTRL_SAT(n) ((n) << 28) ++#define CTRL_DBC BIT(22) ++#define CTRL_CTC BIT(21) ++#define CTRL_YHIST BIT(20) ++#define CTRL_YCURVE BIT(19) ++#define CTRL_CTM BIT(18) ++#define CTRL_BIYUV BIT(17) ++#define CTRL_SCE BIT(8) ++#define CTRL_EE BIT(7) ++#define CTRL_CCE BIT(5) ++#define CTRL_RGE BIT(4) ++#define CTRL_CME BIT(3) ++#define CTRL_AE BIT(2) ++#define CTRL_CE BIT(1) ++#define CTRL_SAT_MASK GENMASK(31, 28) ++ ++#define ISP_REG_PIPELINE_XY_SIZE 0xa0c ++#define H_ACT_CAP(n) ((n) << 16) ++#define W_ACT_CAP(n) ((n) << 0) ++ ++#define ISP_REG_ICTC 0xa10 ++#define GF_MODE(n) ((n) << 30) ++#define MAXGT(n) ((n) << 16) ++#define MINGT(n) ((n) << 0) ++ ++#define ISP_REG_IDBC 0xa14 ++#define BADGT(n) ((n) << 16) ++#define BADXT(n) ((n) << 0) ++ ++#define ISP_REG_ICFAM 0xa1c ++#define CROSS_COV(n) ((n) << 4) ++#define HV_W(n) ((n) << 0) ++ ++#define ISP_REG_CS_GAIN 0xa30 ++#define CMAD(n) ((n) << 16) ++#define CMAB(n) ((n) << 0) ++ ++#define ISP_REG_CS_THRESHOLD 0xa34 ++#define CMD(n) ((n) << 16) ++#define CMB(n) ((n) << 0) ++ ++#define ISP_REG_CS_OFFSET 0xa38 ++#define VOFF(n) ((n) << 16) ++#define UOFF(n) ((n) << 0) ++ ++#define ISP_REG_CS_HUE_F 0xa3c ++#define SIN(n) ((n) << 16) ++#define COS(n) ((n) << 0) ++ ++#define ISP_REG_CS_SCALE 0xa40 ++#define CMSF(n) ((n) << 0) ++ ++#define ISP_REG_IESHD 0xa50 ++#define SHAD_UP_M BIT(1) ++#define SHAD_UP_EN BIT(0) ++ ++#define ISP_REG_YADJ0 0xa54 ++#define YOIR(n) ((n) << 16) ++#define YIMIN(n) ((n) << 0) ++ ++#define ISP_REG_YADJ1 0xa58 ++#define YOMAX(n) ((n) << 16) ++#define YOMIN(n) ((n) << 0) ++ ++#define ISP_REG_Y_PLANE_START_ADDR 0xa80 ++#define ISP_REG_UV_PLANE_START_ADDR 0xa84 ++ ++#define ISP_REG_STRIDE 0xa88 ++#define IMG_STR(n) ((n) << 0) ++ ++#define ISP_REG_ITIIWSR 0xb20 ++#define ITI_HSIZE(n) ((n) << 16) ++#define ITI_WSIZE(n) ((n) << 0) ++ ++#define ISP_REG_ITIDWLSR 0xb24 ++#define ITI_WSTRIDE(n) ((n) << 0) ++ ++#define ISP_REG_ITIPDFR 0xb38 ++#define ITI_PACKAGE_FMT(n) ((n) << 0) ++ ++#define ISP_REG_ITIDRLSR 0xb3C ++#define ITI_STRIDE_L(n) ((n) << 0) ++ ++#define ISP_REG_DNYUV_YSWR0 0xc00 ++#define ISP_REG_DNYUV_YSWR1 0xc04 ++#define ISP_REG_DNYUV_CSWR0 0xc08 ++#define ISP_REG_DNYUV_CSWR1 0xc0c ++#define YUVSW5(n) ((n) << 20) ++#define YUVSW4(n) ((n) << 16) ++#define YUVSW3(n) ((n) << 12) ++#define YUVSW2(n) ((n) << 8) ++#define YUVSW1(n) ((n) << 4) ++#define YUVSW0(n) ((n) << 0) ++ ++#define ISP_REG_DNYUV_YDR0 0xc10 ++#define ISP_REG_DNYUV_YDR1 0xc14 ++#define ISP_REG_DNYUV_YDR2 0xc18 ++#define ISP_REG_DNYUV_CDR0 0xc1c ++#define ISP_REG_DNYUV_CDR1 0xc20 ++#define ISP_REG_DNYUV_CDR2 0xc24 ++#define CURVE_D_H(n) ((n) << 16) ++#define CURVE_D_L(n) ((n) << 0) ++ ++#define ISP_REG_ICAMD_0 0xc40 ++#define DNRM_F(n) ((n) << 16) ++#define ISP_REG_ICAMD_12 0xc70 ++#define ISP_REG_ICAMD_20 0xc90 ++#define ISP_REG_ICAMD_24 0xca0 ++#define ISP_REG_ICAMD_25 0xca4 ++#define CCM_M_DAT(n) ((n) << 0) ++ ++#define ISP_REG_GAMMA_VAL0 0xe00 ++#define ISP_REG_GAMMA_VAL1 0xe04 ++#define ISP_REG_GAMMA_VAL2 0xe08 ++#define ISP_REG_GAMMA_VAL3 0xe0c ++#define ISP_REG_GAMMA_VAL4 0xe10 ++#define ISP_REG_GAMMA_VAL5 0xe14 ++#define ISP_REG_GAMMA_VAL6 0xe18 ++#define ISP_REG_GAMMA_VAL7 0xe1c ++#define ISP_REG_GAMMA_VAL8 0xe20 ++#define ISP_REG_GAMMA_VAL9 0xe24 ++#define ISP_REG_GAMMA_VAL10 0xe28 ++#define ISP_REG_GAMMA_VAL11 0xe2c ++#define ISP_REG_GAMMA_VAL12 0xe30 ++#define ISP_REG_GAMMA_VAL13 0xe34 ++#define ISP_REG_GAMMA_VAL14 0xe38 ++#define GAMMA_S_VAL(n) ((n) << 16) ++#define GAMMA_VAL(n) ((n) << 0) ++ ++#define ISP_REG_R2Y_0 0xe40 ++#define ISP_REG_R2Y_1 0xe44 ++#define ISP_REG_R2Y_2 0xe48 ++#define ISP_REG_R2Y_3 0xe4c ++#define ISP_REG_R2Y_4 0xe50 ++#define ISP_REG_R2Y_5 0xe54 ++#define ISP_REG_R2Y_6 0xe58 ++#define ISP_REG_R2Y_7 0xe5c ++#define ISP_REG_R2Y_8 0xe60 ++#define CSC_M(n) ((n) << 0) ++ ++#define ISP_REG_SHARPEN0 0xe80 ++#define ISP_REG_SHARPEN1 0xe84 ++#define ISP_REG_SHARPEN2 0xe88 ++#define ISP_REG_SHARPEN3 0xe8c ++#define ISP_REG_SHARPEN4 0xe90 ++#define ISP_REG_SHARPEN5 0xe94 ++#define ISP_REG_SHARPEN6 0xe98 ++#define ISP_REG_SHARPEN7 0xe9c ++#define ISP_REG_SHARPEN8 0xea0 ++#define ISP_REG_SHARPEN9 0xea4 ++#define ISP_REG_SHARPEN10 0xea8 ++#define ISP_REG_SHARPEN11 0xeac ++#define ISP_REG_SHARPEN12 0xeb0 ++#define ISP_REG_SHARPEN13 0xeb4 ++#define ISP_REG_SHARPEN14 0xeb8 ++#define S_DELTA(n) ((n) << 16) ++#define S_WEIGHT(n) ((n) << 8) ++ ++#define ISP_REG_SHARPEN_FS0 0xebc ++#define ISP_REG_SHARPEN_FS1 0xec0 ++#define ISP_REG_SHARPEN_FS2 0xec4 ++#define ISP_REG_SHARPEN_FS3 0xec8 ++#define ISP_REG_SHARPEN_FS4 0xecc ++#define ISP_REG_SHARPEN_FS5 0xed0 ++#define S_FACTOR(n) ((n) << 24) ++#define S_SLOPE(n) ((n) << 0) ++ ++#define ISP_REG_SHARPEN_WN 0xed4 ++#define PDIRF(n) ((n) << 28) ++#define NDIRF(n) ((n) << 24) ++#define WSUM(n) ((n) << 0) ++ ++#define ISP_REG_IUVS1 0xed8 ++#define UVDIFF2(n) ((n) << 16) ++#define UVDIFF1(n) ((n) << 0) ++ ++#define ISP_REG_IUVS2 0xedc ++#define UVF(n) ((n) << 24) ++#define UVSLOPE(n) ((n) << 0) ++ ++#define ISP_REG_IUVCKS1 0xee0 ++#define UVCKDIFF2(n) ((n) << 16) ++#define UVCKDIFF1(n) ((n) << 0) ++ ++#define ISP_REG_IUVCKS2 0xee4 ++#define UVCKSLOPE(n) ((n) << 0) ++ ++#define ISP_REG_ISHRPET 0xee8 ++#define TH(n) ((n) << 8) ++#define EN(n) ((n) << 0) ++ ++#define ISP_REG_YCURVE_0 0xf00 ++#define ISP_REG_YCURVE_63 0xffc ++#define L_PARAM(n) ((n) << 0) ++ ++#define IMAGE_MAX_WIDTH 1920 ++#define IMAGE_MAX_HEIGH 1080 ++ ++/* The output line of ISP */ ++enum isp_line_id { ++ STF_ISP_LINE_INVALID = -1, ++ STF_ISP_LINE_SRC = 1, ++ STF_ISP_LINE_MAX = STF_ISP_LINE_SRC ++}; ++ ++/* pad id for media framework */ ++enum isp_pad_id { ++ STF_ISP_PAD_SINK = 0, ++ STF_ISP_PAD_SRC, ++ STF_ISP_PAD_MAX ++}; ++ ++enum { ++ EN_INT_NONE = 0, ++ EN_INT_ISP_DONE = (0x1 << 24), ++ EN_INT_CSI_DONE = (0x1 << 25), ++ EN_INT_SC_DONE = (0x1 << 26), ++ EN_INT_LINE_INT = (0x1 << 27), ++ EN_INT_ALL = (0xF << 24), ++}; ++ ++enum { ++ INTERFACE_DVP = 0, ++ INTERFACE_CSI, ++}; ++ ++struct isp_format { ++ u32 code; ++ u8 bpp; ++}; ++ ++struct isp_format_table { ++ const struct isp_format *fmts; ++ int nfmts; ++}; ++ ++struct regval_t { ++ u32 addr; ++ u32 val; ++ u32 delay_ms; ++}; ++ ++struct reg_table { ++ const struct regval_t *regval; ++ int regval_num; ++}; ++ ++struct stf_isp_crop { ++ struct v4l2_rect rect; ++ u32 bpp; ++}; ++ ++struct stf_isp_dev { ++ struct stfcamss *stfcamss; ++ struct v4l2_subdev subdev; ++ struct media_pad pads[STF_ISP_PAD_MAX]; ++ struct v4l2_mbus_framefmt fmt[STF_ISP_PAD_MAX]; ++ struct stf_isp_crop rect[STF_ISP_PAD_MAX]; ++ const struct isp_format_table *formats; ++ unsigned int nformats; ++ struct mutex stream_lock; /* serialize stream control */ ++ int stream_count; ++}; ++ ++int stf_isp_clk_enable(struct stf_isp_dev *isp_dev); ++int stf_isp_clk_disable(struct stf_isp_dev *isp_dev); ++int stf_isp_reset(struct stf_isp_dev *isp_dev); ++void stf_isp_init_cfg(struct stf_isp_dev *isp_dev); ++void stf_isp_settings(struct stf_isp_dev *isp_dev, ++ struct stf_isp_crop *crop_array, u32 mcode); ++void stf_isp_stream_set(struct stf_isp_dev *isp_dev); ++int stf_isp_subdev_init(struct stfcamss *stfcamss); ++int stf_isp_register(struct stf_isp_dev *isp_dev, struct v4l2_device *v4l2_dev); ++int stf_isp_unregister(struct stf_isp_dev *isp_dev); ++ ++#endif /* STF_ISP_H */ +diff --git a/drivers/media/platform/starfive/camss/stf_isp_hw_ops.c b/drivers/media/platform/starfive/camss/stf_isp_hw_ops.c +new file mode 100644 +index 000000000000..2088b6bd0d61 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_isp_hw_ops.c +@@ -0,0 +1,468 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_isp_hw_ops.c ++ * ++ * Register interface file for StarFive ISP driver ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ * ++ */ ++ ++#include "stf_camss.h" ++ ++static void stf_isp_config_obc(struct stfcamss *stfcamss) ++{ ++ u32 reg_val, reg_add; ++ ++ stf_isp_reg_write(stfcamss, ISP_REG_OBC_CFG, OBC_W_H(11) | OBC_W_W(11)); ++ ++ reg_val = GAIN_D_POINT(0x40) | GAIN_C_POINT(0x40) | ++ GAIN_B_POINT(0x40) | GAIN_A_POINT(0x40); ++ for (reg_add = ISP_REG_OBCG_CFG_0; reg_add <= ISP_REG_OBCG_CFG_3;) { ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ } ++ ++ reg_val = OFFSET_D_POINT(0) | OFFSET_C_POINT(0) | ++ OFFSET_B_POINT(0) | OFFSET_A_POINT(0); ++ for (reg_add = ISP_REG_OBCO_CFG_0; reg_add <= ISP_REG_OBCO_CFG_3;) { ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ } ++} ++ ++static void stf_isp_config_oecf(struct stfcamss *stfcamss) ++{ ++ u32 reg_add, par_val; ++ u16 par_h, par_l; ++ ++ par_h = 0x10; par_l = 0; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG0; reg_add <= ISP_REG_OECF_Y3_CFG0;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x40; par_l = 0x20; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG1; reg_add <= ISP_REG_OECF_Y3_CFG1;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x80; par_l = 0x60; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG2; reg_add <= ISP_REG_OECF_Y3_CFG2;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0xc0; par_l = 0xa0; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG3; reg_add <= ISP_REG_OECF_Y3_CFG3;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x100; par_l = 0xe0; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG4; reg_add <= ISP_REG_OECF_Y3_CFG4;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x200; par_l = 0x180; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG5; reg_add <= ISP_REG_OECF_Y3_CFG5;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x300; par_l = 0x280; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG6; reg_add <= ISP_REG_OECF_Y3_CFG6;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x3fe; par_l = 0x380; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_X0_CFG7; reg_add <= ISP_REG_OECF_Y3_CFG7;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 0x20; ++ } ++ ++ par_h = 0x80; par_l = 0x80; ++ par_val = OCEF_PAR_H(par_h) | OCEF_PAR_L(par_l); ++ for (reg_add = ISP_REG_OECF_S0_CFG0; reg_add <= ISP_REG_OECF_S3_CFG7;) { ++ stf_isp_reg_write(stfcamss, reg_add, par_val); ++ reg_add += 4; ++ } ++} ++ ++static void stf_isp_config_lccf(struct stfcamss *stfcamss) ++{ ++ u32 reg_add; ++ ++ stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_0, ++ Y_DISTANCE(0x21C) | X_DISTANCE(0x3C0)); ++ stf_isp_reg_write(stfcamss, ISP_REG_LCCF_CFG_1, LCCF_MAX_DIS(0xb)); ++ ++ for (reg_add = ISP_REG_LCCF_CFG_2; reg_add <= ISP_REG_LCCF_CFG_5;) { ++ stf_isp_reg_write(stfcamss, reg_add, ++ LCCF_F2_PAR(0x0) | LCCF_F1_PAR(0x0)); ++ reg_add += 4; ++ } ++} ++ ++static void stf_isp_config_awb(struct stfcamss *stfcamss) ++{ ++ u32 reg_val, reg_add; ++ u16 symbol_h, symbol_l; ++ ++ symbol_h = 0x0; symbol_l = 0x0; ++ reg_val = AWB_X_SYMBOL_H(symbol_h) | AWB_X_SYMBOL_L(symbol_l); ++ ++ for (reg_add = ISP_REG_AWB_X0_CFG_0; reg_add <= ISP_REG_AWB_X3_CFG_1;) { ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ } ++ ++ symbol_h = 0x0, symbol_l = 0x0; ++ reg_val = AWB_Y_SYMBOL_H(symbol_h) | AWB_Y_SYMBOL_L(symbol_l); ++ ++ for (reg_add = ISP_REG_AWB_Y0_CFG_0; reg_add <= ISP_REG_AWB_Y3_CFG_1;) { ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ } ++ ++ symbol_h = 0x80, symbol_l = 0x80; ++ reg_val = AWB_S_SYMBOL_H(symbol_h) | AWB_S_SYMBOL_L(symbol_l); ++ ++ for (reg_add = ISP_REG_AWB_S0_CFG_0; reg_add <= ISP_REG_AWB_S3_CFG_1;) { ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ } ++} ++ ++static void stf_isp_config_grgb(struct stfcamss *stfcamss) ++{ ++ stf_isp_reg_write(stfcamss, ISP_REG_ICTC, ++ GF_MODE(1) | MAXGT(0x140) | MINGT(0x40)); ++ stf_isp_reg_write(stfcamss, ISP_REG_IDBC, BADGT(0x200) | BADXT(0x200)); ++} ++ ++static void stf_isp_config_cfa(struct stfcamss *stfcamss) ++{ ++ stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG, ++ SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) | SMY3(2) | ++ SMY2(3) | SMY1(2) | SMY0(3)); ++ stf_isp_reg_write(stfcamss, ISP_REG_ICFAM, CROSS_COV(3) | HV_W(2)); ++} ++ ++static void stf_isp_config_ccm(struct stfcamss *stfcamss) ++{ ++ u32 reg_add; ++ ++ stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_0, DNRM_F(6) | CCM_M_DAT(0)); ++ ++ for (reg_add = ISP_REG_ICAMD_12; reg_add <= ISP_REG_ICAMD_20;) { ++ stf_isp_reg_write(stfcamss, reg_add, CCM_M_DAT(0x80)); ++ reg_add += 0x10; ++ } ++ ++ stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_24, CCM_M_DAT(0x700)); ++ stf_isp_reg_write(stfcamss, ISP_REG_ICAMD_25, CCM_M_DAT(0x200)); ++} ++ ++static void stf_isp_config_gamma(struct stfcamss *stfcamss) ++{ ++ u32 reg_val, reg_add; ++ u16 gamma_slope_v, gamma_v; ++ ++ gamma_slope_v = 0x2400; gamma_v = 0x0; ++ reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v); ++ stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL0, reg_val); ++ ++ gamma_slope_v = 0x800; gamma_v = 0x20; ++ for (reg_add = ISP_REG_GAMMA_VAL1; reg_add <= ISP_REG_GAMMA_VAL7;) { ++ reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v); ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ gamma_v += 0x20; ++ } ++ ++ gamma_v = 0x100; ++ for (reg_add = ISP_REG_GAMMA_VAL8; reg_add <= ISP_REG_GAMMA_VAL13;) { ++ reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v); ++ stf_isp_reg_write(stfcamss, reg_add, reg_val); ++ reg_add += 4; ++ gamma_v += 0x80; ++ } ++ ++ gamma_v = 0x3fe; ++ reg_val = GAMMA_S_VAL(gamma_slope_v) | GAMMA_VAL(gamma_v); ++ stf_isp_reg_write(stfcamss, ISP_REG_GAMMA_VAL14, reg_val); ++} ++ ++static void stf_isp_config_r2y(struct stfcamss *stfcamss) ++{ ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_0, CSC_M(0x4C)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_1, CSC_M(0x97)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_2, CSC_M(0x1d)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_3, CSC_M(0x1d5)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_4, CSC_M(0x1ac)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_5, CSC_M(0x80)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_6, CSC_M(0x80)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_7, CSC_M(0x194)); ++ stf_isp_reg_write(stfcamss, ISP_REG_R2Y_8, CSC_M(0x1ec)); ++} ++ ++static void stf_isp_config_y_curve(struct stfcamss *stfcamss) ++{ ++ u32 reg_add; ++ u16 y_curve; ++ ++ y_curve = 0x0; ++ for (reg_add = ISP_REG_YCURVE_0; reg_add <= ISP_REG_YCURVE_63;) { ++ stf_isp_reg_write(stfcamss, reg_add, y_curve); ++ reg_add += 4; ++ y_curve += 0x10; ++ } ++} ++ ++static void stf_isp_config_sharpen(struct stfcamss *sc) ++{ ++ u32 reg_add; ++ ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN0, S_DELTA(0x7) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN1, S_DELTA(0x18) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN2, S_DELTA(0x80) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN3, S_DELTA(0x100) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN4, S_DELTA(0x10) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN5, S_DELTA(0x60) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN6, S_DELTA(0x100) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN7, S_DELTA(0x190) | S_WEIGHT(0xf)); ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN8, S_DELTA(0x0) | S_WEIGHT(0xf)); ++ ++ for (reg_add = ISP_REG_SHARPEN9; reg_add <= ISP_REG_SHARPEN14;) { ++ stf_isp_reg_write(sc, reg_add, S_WEIGHT(0xf)); ++ reg_add += 4; ++ } ++ ++ for (reg_add = ISP_REG_SHARPEN_FS0; reg_add <= ISP_REG_SHARPEN_FS5;) { ++ stf_isp_reg_write(sc, reg_add, S_FACTOR(0x10) | S_SLOPE(0x0)); ++ reg_add += 4; ++ } ++ ++ stf_isp_reg_write(sc, ISP_REG_SHARPEN_WN, ++ PDIRF(0x8) | NDIRF(0x8) | WSUM(0xd7c)); ++ stf_isp_reg_write(sc, ISP_REG_IUVS1, UVDIFF2(0xC0) | UVDIFF1(0x40)); ++ stf_isp_reg_write(sc, ISP_REG_IUVS2, UVF(0xff) | UVSLOPE(0x0)); ++ stf_isp_reg_write(sc, ISP_REG_IUVCKS1, ++ UVCKDIFF2(0xa0) | UVCKDIFF1(0x40)); ++} ++ ++static void stf_isp_config_dnyuv(struct stfcamss *stfcamss) ++{ ++ u32 reg_val; ++ ++ reg_val = YUVSW5(7) | YUVSW4(7) | YUVSW3(7) | YUVSW2(7) | ++ YUVSW1(7) | YUVSW0(7); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR0, reg_val); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR0, reg_val); ++ ++ reg_val = YUVSW3(7) | YUVSW2(7) | YUVSW1(7) | YUVSW0(7); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YSWR1, reg_val); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CSWR1, reg_val); ++ ++ reg_val = CURVE_D_H(0x60) | CURVE_D_L(0x40); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR0, reg_val); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR0, reg_val); ++ ++ reg_val = CURVE_D_H(0xd8) | CURVE_D_L(0x90); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR1, reg_val); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR1, reg_val); ++ ++ reg_val = CURVE_D_H(0x1e6) | CURVE_D_L(0x144); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_YDR2, reg_val); ++ stf_isp_reg_write(stfcamss, ISP_REG_DNYUV_CDR2, reg_val); ++} ++ ++static void stf_isp_config_sat(struct stfcamss *stfcamss) ++{ ++ stf_isp_reg_write(stfcamss, ISP_REG_CS_GAIN, CMAD(0x0) | CMAB(0x100)); ++ stf_isp_reg_write(stfcamss, ISP_REG_CS_THRESHOLD, CMD(0x1f) | CMB(0x1)); ++ stf_isp_reg_write(stfcamss, ISP_REG_CS_OFFSET, VOFF(0x0) | UOFF(0x0)); ++ stf_isp_reg_write(stfcamss, ISP_REG_CS_HUE_F, SIN(0x0) | COS(0x100)); ++ stf_isp_reg_write(stfcamss, ISP_REG_CS_SCALE, CMSF(0x8)); ++ stf_isp_reg_write(stfcamss, ISP_REG_YADJ0, YOIR(0x401) | YIMIN(0x1)); ++ stf_isp_reg_write(stfcamss, ISP_REG_YADJ1, YOMAX(0x3ff) | YOMIN(0x1)); ++} ++ ++int stf_isp_clk_enable(struct stf_isp_dev *isp_dev) ++{ ++ struct stfcamss *stfcamss = isp_dev->stfcamss; ++ ++ clk_prepare_enable(stfcamss->sys_clk[STF_CLK_WRAPPER_CLK_C].clk); ++ reset_control_deassert(stfcamss->sys_rst[STF_RST_WRAPPER_C].rstc); ++ reset_control_deassert(stfcamss->sys_rst[STF_RST_WRAPPER_P].rstc); ++ ++ return 0; ++} ++ ++int stf_isp_clk_disable(struct stf_isp_dev *isp_dev) ++{ ++ struct stfcamss *stfcamss = isp_dev->stfcamss; ++ ++ reset_control_assert(stfcamss->sys_rst[STF_RST_WRAPPER_C].rstc); ++ reset_control_assert(stfcamss->sys_rst[STF_RST_WRAPPER_P].rstc); ++ clk_disable_unprepare(stfcamss->sys_clk[STF_CLK_WRAPPER_CLK_C].clk); ++ ++ return 0; ++} ++ ++int stf_isp_reset(struct stf_isp_dev *isp_dev) ++{ ++ stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0, ++ ISPC_RST_MASK, ISPC_RST); ++ stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_ISP_CTRL_0, ++ ISPC_RST_MASK, 0); ++ ++ return 0; ++} ++ ++void stf_isp_init_cfg(struct stf_isp_dev *isp_dev) ++{ ++ stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DC_CFG_1, DC_AXI_ID(0x0)); ++ stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_DEC_CFG, ++ DEC_V_KEEP(0x0) | ++ DEC_V_PERIOD(0x0) | ++ DEC_H_KEEP(0x0) | ++ DEC_H_PERIOD(0x0)); ++ ++ stf_isp_config_obc(isp_dev->stfcamss); ++ stf_isp_config_oecf(isp_dev->stfcamss); ++ stf_isp_config_lccf(isp_dev->stfcamss); ++ stf_isp_config_awb(isp_dev->stfcamss); ++ stf_isp_config_grgb(isp_dev->stfcamss); ++ stf_isp_config_cfa(isp_dev->stfcamss); ++ stf_isp_config_ccm(isp_dev->stfcamss); ++ stf_isp_config_gamma(isp_dev->stfcamss); ++ stf_isp_config_r2y(isp_dev->stfcamss); ++ stf_isp_config_y_curve(isp_dev->stfcamss); ++ stf_isp_config_sharpen(isp_dev->stfcamss); ++ stf_isp_config_dnyuv(isp_dev->stfcamss); ++ stf_isp_config_sat(isp_dev->stfcamss); ++ ++ stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_CSI_MODULE_CFG, ++ CSI_DUMP_EN | CSI_SC_EN | CSI_AWB_EN | ++ CSI_LCCF_EN | CSI_OECF_EN | CSI_OBC_EN | CSI_DEC_EN); ++ stf_isp_reg_write(isp_dev->stfcamss, ISP_REG_ISP_CTRL_1, ++ CTRL_SAT(1) | CTRL_DBC | CTRL_CTC | CTRL_YHIST | ++ CTRL_YCURVE | CTRL_BIYUV | CTRL_SCE | CTRL_EE | ++ CTRL_CCE | CTRL_RGE | CTRL_CME | CTRL_AE | CTRL_CE); ++} ++ ++static void stf_isp_config_crop(struct stfcamss *stfcamss, ++ struct stf_isp_crop *crop) ++{ ++ struct v4l2_rect *rect = &crop[STF_ISP_PAD_SRC].rect; ++ u32 bpp = crop[STF_ISP_PAD_SRC].bpp; ++ u32 val; ++ ++ val = VSTART_CAP(rect->top) | HSTART_CAP(rect->left); ++ stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_START_CFG, val); ++ ++ val = VEND_CAP(rect->height + rect->top - 1) | ++ HEND_CAP(rect->width + rect->left - 1); ++ stf_isp_reg_write(stfcamss, ISP_REG_PIC_CAPTURE_END_CFG, val); ++ ++ val = H_ACT_CAP(rect->height) | W_ACT_CAP(rect->width); ++ stf_isp_reg_write(stfcamss, ISP_REG_PIPELINE_XY_SIZE, val); ++ ++ val = ALIGN(rect->width * bpp / 8, STFCAMSS_FRAME_WIDTH_ALIGN_8); ++ stf_isp_reg_write(stfcamss, ISP_REG_STRIDE, val); ++} ++ ++static void stf_isp_config_raw_fmt(struct stfcamss *stfcamss, u32 mcode) ++{ ++ u32 val, val1; ++ ++ switch (mcode) { ++ case MEDIA_BUS_FMT_SRGGB10_1X10: ++ case MEDIA_BUS_FMT_SRGGB8_1X8: ++ /* 3 2 3 2 1 0 1 0 B Gb B Gb Gr R Gr R */ ++ val = SMY13(3) | SMY12(2) | SMY11(3) | SMY10(2) | ++ SMY3(1) | SMY2(0) | SMY1(1) | SMY0(0); ++ val1 = CTRL_SAT(0x0); ++ break; ++ case MEDIA_BUS_FMT_SGRBG10_1X10: ++ case MEDIA_BUS_FMT_SGRBG8_1X8: ++ /* 2 3 2 3 0 1 0 1, Gb B Gb B R Gr R Gr */ ++ val = SMY13(2) | SMY12(3) | SMY11(2) | SMY10(3) | ++ SMY3(0) | SMY2(1) | SMY1(0) | SMY0(1); ++ val1 = CTRL_SAT(0x2); ++ break; ++ case MEDIA_BUS_FMT_SGBRG10_1X10: ++ case MEDIA_BUS_FMT_SGBRG8_1X8: ++ /* 1 0 1 0 3 2 3 2, Gr R Gr R B Gb B Gb */ ++ val = SMY13(1) | SMY12(0) | SMY11(1) | SMY10(0) | ++ SMY3(3) | SMY2(2) | SMY1(3) | SMY0(2); ++ val1 = CTRL_SAT(0x3); ++ break; ++ case MEDIA_BUS_FMT_SBGGR10_1X10: ++ case MEDIA_BUS_FMT_SBGGR8_1X8: ++ /* 0 1 0 1 2 3 2 3 R Gr R Gr Gb B Gb B */ ++ val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) | ++ SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3); ++ val1 = CTRL_SAT(0x1); ++ break; ++ default: ++ val = SMY13(0) | SMY12(1) | SMY11(0) | SMY10(1) | ++ SMY3(2) | SMY2(3) | SMY1(2) | SMY0(3); ++ val1 = CTRL_SAT(0x1); ++ break; ++ } ++ stf_isp_reg_write(stfcamss, ISP_REG_RAW_FORMAT_CFG, val); ++ stf_isp_reg_set_bit(stfcamss, ISP_REG_ISP_CTRL_1, CTRL_SAT_MASK, val1); ++} ++ ++void stf_isp_settings(struct stf_isp_dev *isp_dev, ++ struct stf_isp_crop *crop, u32 mcode) ++{ ++ struct stfcamss *stfcamss = isp_dev->stfcamss; ++ ++ stf_isp_config_crop(stfcamss, crop); ++ stf_isp_config_raw_fmt(stfcamss, mcode); ++ ++ stf_isp_reg_set_bit(stfcamss, ISP_REG_DUMP_CFG_1, ++ DUMP_BURST_LEN_MASK | DUMP_SD_MASK, ++ DUMP_BURST_LEN(3)); ++ ++ stf_isp_reg_write(stfcamss, ISP_REG_ITIIWSR, ++ ITI_HSIZE(IMAGE_MAX_HEIGH) | ++ ITI_WSIZE(IMAGE_MAX_WIDTH)); ++ stf_isp_reg_write(stfcamss, ISP_REG_ITIDWLSR, ITI_WSTRIDE(0x960)); ++ stf_isp_reg_write(stfcamss, ISP_REG_ITIDRLSR, ITI_STRIDE_L(0x960)); ++ stf_isp_reg_write(stfcamss, ISP_REG_SENSOR, 0x1); ++} ++ ++void stf_isp_stream_set(struct stf_isp_dev *isp_dev) ++{ ++ struct stfcamss *stfcamss = isp_dev->stfcamss; ++ ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0, ++ ISPC_ENUO | ISPC_ENLS | ISPC_RST, 10); ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0, ++ ISPC_ENUO | ISPC_ENLS, 10); ++ stf_isp_reg_write(stfcamss, ISP_REG_IESHD, SHAD_UP_M); ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_ISP_CTRL_0, ++ ISPC_ENUO | ISPC_ENLS | ISPC_EN, 10); ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS, ++ CSI_INTS(1) | CSI_SHA_M(4), 10); ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_CSIINTS, ++ CSI_INTS(2) | CSI_SHA_M(4), 10); ++ stf_isp_reg_write_delay(stfcamss, ISP_REG_CSI_INPUT_EN_AND_STATUS, ++ CSI_EN_S, 10); ++} +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0049-media-starfive-camss-Add-VIN-driver.patch b/srcpkgs/linux6.4/patches/0049-media-starfive-camss-Add-VIN-driver.patch new file mode 100644 index 0000000000000..2a64fbbfef395 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0049-media-starfive-camss-Add-VIN-driver.patch @@ -0,0 +1,1593 @@ +From 9e5926e1c1f4c684156a850cc94b23b9286dd8b9 Mon Sep 17 00:00:00 2001 +From: Jack Zhu +Date: Mon, 19 Jun 2023 19:28:38 +0800 +Subject: [PATCH 49/72] media: starfive: camss: Add VIN driver + +Add Video In Controller driver for StarFive Camera Subsystem. + +Signed-off-by: Jack Zhu +--- + .../media/platform/starfive/camss/Makefile | 4 +- + .../media/platform/starfive/camss/stf_camss.c | 42 +- + .../media/platform/starfive/camss/stf_camss.h | 2 + + .../media/platform/starfive/camss/stf_vin.c | 1069 +++++++++++++++++ + .../media/platform/starfive/camss/stf_vin.h | 173 +++ + .../platform/starfive/camss/stf_vin_hw_ops.c | 192 +++ + 6 files changed, 1478 insertions(+), 4 deletions(-) + create mode 100644 drivers/media/platform/starfive/camss/stf_vin.c + create mode 100644 drivers/media/platform/starfive/camss/stf_vin.h + create mode 100644 drivers/media/platform/starfive/camss/stf_vin_hw_ops.c + +diff --git a/drivers/media/platform/starfive/camss/Makefile b/drivers/media/platform/starfive/camss/Makefile +index cdf57e8c9546..ef574e01ca47 100644 +--- a/drivers/media/platform/starfive/camss/Makefile ++++ b/drivers/media/platform/starfive/camss/Makefile +@@ -7,6 +7,8 @@ starfive-camss-objs += \ + stf_camss.o \ + stf_isp.o \ + stf_isp_hw_ops.o \ +- stf_video.o ++ stf_video.o \ ++ stf_vin.o \ ++ stf_vin_hw_ops.o + + obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive-camss.o +diff --git a/drivers/media/platform/starfive/camss/stf_camss.c b/drivers/media/platform/starfive/camss/stf_camss.c +index 6f56b45f57db..834ea63eb833 100644 +--- a/drivers/media/platform/starfive/camss/stf_camss.c ++++ b/drivers/media/platform/starfive/camss/stf_camss.c +@@ -131,27 +131,61 @@ static int stfcamss_init_subdevices(struct stfcamss *stfcamss) + return ret; + } + ++ ret = stf_vin_subdev_init(stfcamss); ++ if (ret < 0) { ++ dev_err(stfcamss->dev, "Failed to init vin subdev: %d\n", ret); ++ return ret; ++ } + return ret; + } + + static int stfcamss_register_subdevices(struct stfcamss *stfcamss) + { + int ret; ++ struct stf_vin_dev *vin_dev = &stfcamss->vin_dev; + struct stf_isp_dev *isp_dev = &stfcamss->isp_dev; + + ret = stf_isp_register(isp_dev, &stfcamss->v4l2_dev); + if (ret < 0) { + dev_err(stfcamss->dev, + "Failed to register stf isp%d entity: %d\n", 0, ret); +- return ret; ++ goto err_reg_isp; ++ } ++ ++ ret = stf_vin_register(vin_dev, &stfcamss->v4l2_dev); ++ if (ret < 0) { ++ dev_err(stfcamss->dev, ++ "Failed to register vin entity: %d\n", ret); ++ goto err_reg_vin; + } + ++ ret = media_create_pad_link(&isp_dev->subdev.entity, ++ STF_ISP_PAD_SRC, ++ &vin_dev->line[VIN_LINE_ISP].subdev.entity, ++ STF_VIN_PAD_SINK, ++ 0); ++ if (ret < 0) { ++ dev_err(stfcamss->dev, ++ "Failed to link %s->%s entities: %d\n", ++ isp_dev->subdev.entity.name, ++ vin_dev->line[VIN_LINE_ISP].subdev.entity.name, ret); ++ goto err_link; ++ } ++ ++ return ret; ++ ++err_link: ++ stf_vin_unregister(&stfcamss->vin_dev); ++err_reg_vin: ++ stf_isp_unregister(&stfcamss->isp_dev); ++err_reg_isp: + return ret; + } + + static void stfcamss_unregister_subdevices(struct stfcamss *stfcamss) + { + stf_isp_unregister(&stfcamss->isp_dev); ++ stf_vin_unregister(&stfcamss->vin_dev); + } + + static int stfcamss_subdev_notifier_bound(struct v4l2_async_notifier *async, +@@ -164,12 +198,14 @@ static int stfcamss_subdev_notifier_bound(struct v4l2_async_notifier *async, + container_of(asd, struct stfcamss_async_subdev, asd); + enum stf_port_num port = csd->port; + struct stf_isp_dev *isp_dev = &stfcamss->isp_dev; ++ struct stf_vin_dev *vin_dev = &stfcamss->vin_dev; + struct media_pad *pad[STF_PADS_NUM]; + unsigned int i, pad_num; + + if (port == STF_PORT_CSI2RX) { +- pad[0] = &isp_dev->pads[STF_PAD_SINK]; +- pad_num = 1; ++ pad[0] = &vin_dev->line[VIN_LINE_WR].pads[STF_PAD_SINK]; ++ pad[1] = &isp_dev->pads[STF_PAD_SINK]; ++ pad_num = 2; + } else if (port == STF_PORT_DVP) { + dev_err(stfcamss->dev, "Not support DVP sensor\n"); + return -EPERM; +diff --git a/drivers/media/platform/starfive/camss/stf_camss.h b/drivers/media/platform/starfive/camss/stf_camss.h +index 9482081288fa..a14f22bc0742 100644 +--- a/drivers/media/platform/starfive/camss/stf_camss.h ++++ b/drivers/media/platform/starfive/camss/stf_camss.h +@@ -19,6 +19,7 @@ + #include + + #include "stf_isp.h" ++#include "stf_vin.h" + + #define STF_DVP_NAME "stf_dvp" + #define STF_CSI_NAME "cdns_csi2rx" +@@ -67,6 +68,7 @@ struct stfcamss { + struct media_device media_dev; + struct media_pipeline pipe; + struct device *dev; ++ struct stf_vin_dev vin_dev; + struct stf_isp_dev isp_dev; + struct v4l2_async_notifier notifier; + void __iomem *syscon_base; +diff --git a/drivers/media/platform/starfive/camss/stf_vin.c b/drivers/media/platform/starfive/camss/stf_vin.c +new file mode 100644 +index 000000000000..0efa4bbb079c +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_vin.c +@@ -0,0 +1,1069 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_vin.c ++ * ++ * StarFive Camera Subsystem - VIN Module ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++ ++#include "stf_camss.h" ++ ++#define vin_line_array(ptr_line) \ ++ ((const struct vin_line (*)[]) &(ptr_line)[-((ptr_line)->id)]) ++ ++#define line_to_vin_dev(ptr_line) \ ++ container_of(vin_line_array(ptr_line), struct stf_vin_dev, line) ++ ++#define VIN_FRAME_DROP_MIN_VAL 4 ++ ++/* ISP ctrl need 1 sec to let frames become stable. */ ++#define VIN_FRAME_DROP_SEC_FOR_ISP_CTRL 1 ++ ++static const struct vin_format vin_formats_wr[] = { ++ { MEDIA_BUS_FMT_SRGGB10_1X10, 10}, ++ { MEDIA_BUS_FMT_SGRBG10_1X10, 10}, ++ { MEDIA_BUS_FMT_SGBRG10_1X10, 10}, ++ { MEDIA_BUS_FMT_SBGGR10_1X10, 10}, ++}; ++ ++static const struct vin_format vin_formats_uo[] = { ++ { MEDIA_BUS_FMT_Y12_1X12, 8}, ++}; ++ ++static const struct vin_format_table vin_formats_table[] = { ++ /* VIN_LINE_WR */ ++ { vin_formats_wr, ARRAY_SIZE(vin_formats_wr) }, ++ /* VIN_LINE_ISP */ ++ { vin_formats_uo, ARRAY_SIZE(vin_formats_uo) }, ++}; ++ ++static void vin_buffer_done(struct vin_line *line); ++static void vin_change_buffer(struct vin_line *line); ++static struct stfcamss_buffer *vin_buf_get_pending(struct vin_output *output); ++static void vin_output_init_addrs(struct vin_line *line); ++static struct v4l2_mbus_framefmt * ++__vin_get_format(struct vin_line *line, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ enum v4l2_subdev_format_whence which); ++ ++static char *vin_get_line_subdevname(int line_id) ++{ ++ char *name = NULL; ++ ++ switch (line_id) { ++ case VIN_LINE_WR: ++ name = "wr"; ++ break; ++ case VIN_LINE_ISP: ++ name = "isp0"; ++ break; ++ default: ++ name = "unknown"; ++ break; ++ } ++ return name; ++} ++ ++static enum isp_line_id vin_map_isp_line(enum vin_line_id line) ++{ ++ enum isp_line_id line_id; ++ ++ if (line > VIN_LINE_WR && line < VIN_LINE_MAX) ++ line_id = STF_ISP_LINE_SRC; ++ else ++ line_id = STF_ISP_LINE_INVALID; ++ ++ return line_id; ++} ++ ++enum isp_pad_id stf_vin_map_isp_pad(enum vin_line_id line, enum isp_pad_id def) ++{ ++ enum isp_pad_id pad_id; ++ ++ if (line == VIN_LINE_WR) ++ pad_id = STF_ISP_PAD_SINK; ++ else if ((line > VIN_LINE_WR) && (line < VIN_LINE_MAX)) ++ pad_id = (enum isp_pad_id)vin_map_isp_line(line); ++ else ++ pad_id = def; ++ ++ return pad_id; ++} ++ ++int stf_vin_subdev_init(struct stfcamss *stfcamss) ++{ ++ struct device *dev = stfcamss->dev; ++ struct stf_vin_dev *vin_dev = &stfcamss->vin_dev; ++ int i, ret = 0; ++ ++ vin_dev->stfcamss = stfcamss; ++ ++ vin_dev->isr_ops = devm_kzalloc(dev, sizeof(*vin_dev->isr_ops), ++ GFP_KERNEL); ++ if (!vin_dev->isr_ops) ++ return -ENOMEM; ++ vin_dev->isr_ops->isr_buffer_done = vin_buffer_done; ++ vin_dev->isr_ops->isr_change_buffer = vin_change_buffer; ++ ++ atomic_set(&vin_dev->ref_count, 0); ++ ++ ret = devm_request_irq(dev, ++ stfcamss->irq[STF_IRQ_VINWR], ++ stf_vin_wr_irq_handler, ++ 0, "vin_axiwr_irq", vin_dev); ++ if (ret) { ++ dev_err(dev, "Failed to request irq\n"); ++ goto out; ++ } ++ ++ ret = devm_request_irq(dev, ++ stfcamss->irq[STF_IRQ_ISP], ++ stf_vin_isp_irq_handler, ++ 0, "vin_isp_irq", vin_dev); ++ if (ret) { ++ dev_err(dev, "Failed to request isp irq\n"); ++ goto out; ++ } ++ ++ ret = devm_request_irq(dev, ++ stfcamss->irq[STF_IRQ_ISPCSIL], ++ stf_vin_isp_irq_csiline_handler, ++ 0, "vin_isp_irq_csiline", vin_dev); ++ if (ret) { ++ dev_err(dev, "failed to request isp irq csiline\n"); ++ goto out; ++ } ++ ++ for (i = 0; i < STF_DUMMY_MODULE_NUMS; i++) { ++ struct dummy_buffer *dummy_buffer = &vin_dev->dummy_buffer[i]; ++ ++ mutex_init(&dummy_buffer->stream_lock); ++ dummy_buffer->nums = ++ i == 0 ? VIN_DUMMY_BUFFER_NUMS : ISP_DUMMY_BUFFER_NUMS; ++ dummy_buffer->stream_count = 0; ++ dummy_buffer->buffer = ++ devm_kzalloc(dev, ++ dummy_buffer->nums * sizeof(struct vin_dummy_buffer), ++ GFP_KERNEL); ++ atomic_set(&dummy_buffer->frame_skip, 0); ++ } ++ ++ for (i = VIN_LINE_WR; i < STF_ISP_LINE_MAX + 1; i++) { ++ struct vin_line *l = &vin_dev->line[i]; ++ ++ l->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ l->video_out.stfcamss = stfcamss; ++ l->id = i; ++ l->formats = vin_formats_table[i].fmts; ++ l->nformats = vin_formats_table[i].nfmts; ++ spin_lock_init(&l->output_lock); ++ ++ mutex_init(&l->stream_lock); ++ l->stream_count = 0; ++ } ++ ++ return 0; ++out: ++ return ret; ++} ++ ++static enum link vin_get_link(struct media_entity *entity) ++{ ++ struct v4l2_subdev *subdev; ++ struct media_pad *pad; ++ bool isp = false; ++ ++ while (1) { ++ pad = &entity->pads[0]; ++ if (!(pad->flags & MEDIA_PAD_FL_SINK)) ++ return LINK_ERROR; ++ ++ pad = media_pad_remote_pad_first(pad); ++ if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) ++ return LINK_ERROR; ++ ++ entity = pad->entity; ++ subdev = media_entity_to_v4l2_subdev(entity); ++ ++ if (!strncmp(subdev->name, STF_CSI_NAME, ++ strlen(STF_CSI_NAME))) { ++ if (isp) ++ return LINK_CSI_TO_ISP; ++ else ++ return LINK_CSI_TO_WR; ++ } else if (!strncmp(subdev->name, STF_DVP_NAME, ++ strlen(STF_DVP_NAME))) { ++ if (isp) ++ return LINK_DVP_TO_ISP; ++ else ++ return LINK_DVP_TO_WR; ++ } else if (!strncmp(subdev->name, STF_ISP_NAME, ++ strlen(STF_ISP_NAME))) { ++ isp = true; ++ } else { ++ return LINK_ERROR; ++ } ++ } ++} ++ ++static int vin_enable_output(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ output->state = VIN_OUTPUT_IDLE; ++ ++ output->buf[0] = vin_buf_get_pending(output); ++ ++ if (!output->buf[0] && output->buf[1]) { ++ output->buf[0] = output->buf[1]; ++ output->buf[1] = NULL; ++ } ++ ++ if (output->buf[0]) ++ output->state = VIN_OUTPUT_SINGLE; ++ ++ output->sequence = 0; ++ ++ vin_output_init_addrs(line); ++ spin_unlock_irqrestore(&line->output_lock, flags); ++ return 0; ++} ++ ++static int vin_disable_output(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ output->state = VIN_OUTPUT_OFF; ++ ++ spin_unlock_irqrestore(&line->output_lock, flags); ++ return 0; ++} ++ ++static u32 vin_line_to_dummy_module(struct vin_line *line) ++{ ++ u32 dummy_module = 0; ++ ++ switch (line->id) { ++ case VIN_LINE_WR: ++ dummy_module = STF_DUMMY_VIN; ++ break; ++ case VIN_LINE_ISP: ++ dummy_module = STF_DUMMY_ISP; ++ break; ++ default: ++ dummy_module = STF_DUMMY_VIN; ++ break; ++ } ++ ++ return dummy_module; ++} ++ ++static int vin_alloc_dummy_buffer(struct stf_vin_dev *vin_dev, ++ struct v4l2_mbus_framefmt *fmt, ++ int dummy_module) ++{ ++ struct device *dev = vin_dev->stfcamss->dev; ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[dummy_module]; ++ struct vin_dummy_buffer *buffer = NULL; ++ int ret = 0, i; ++ u32 aligns; ++ ++ for (i = 0; i < dummy_buffer->nums; i++) { ++ buffer = &vin_dev->dummy_buffer[dummy_module].buffer[i]; ++ buffer->width = fmt->width; ++ buffer->height = fmt->height; ++ buffer->mcode = fmt->code; ++ if (i == STF_VIN_PAD_SINK) { ++ aligns = ALIGN(fmt->width * 4, ++ STFCAMSS_FRAME_WIDTH_ALIGN_8); ++ buffer->buffer_size = PAGE_ALIGN(aligns * fmt->height); ++ } else if (i == STF_ISP_PAD_SRC) { ++ aligns = ALIGN(fmt->width, ++ STFCAMSS_FRAME_WIDTH_ALIGN_8); ++ buffer->buffer_size = ++ PAGE_ALIGN(aligns * fmt->height * 3 / 2); ++ } else { ++ continue; ++ } ++ ++ buffer->vaddr = dma_alloc_coherent(dev, ++ buffer->buffer_size, ++ &buffer->paddr[0], ++ GFP_KERNEL | __GFP_NOWARN); ++ ++ if (buffer->vaddr) { ++ if (i == STF_ISP_PAD_SRC) ++ buffer->paddr[1] = ++ (dma_addr_t)(buffer->paddr[0] + aligns * fmt->height); ++ else ++ dev_dbg(dev, "signal plane\n"); ++ } ++ } ++ ++ return ret; ++} ++ ++static void vin_free_dummy_buffer(struct stf_vin_dev *vin_dev, int dummy_module) ++{ ++ struct device *dev = vin_dev->stfcamss->dev; ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[dummy_module]; ++ struct vin_dummy_buffer *buffer = NULL; ++ int i; ++ ++ for (i = 0; i < dummy_buffer->nums; i++) { ++ buffer = &dummy_buffer->buffer[i]; ++ if (buffer->vaddr) ++ dma_free_coherent(dev, buffer->buffer_size, ++ buffer->vaddr, buffer->paddr[0]); ++ memset(buffer, 0, sizeof(struct vin_dummy_buffer)); ++ } ++} ++ ++static void vin_set_dummy_buffer(struct vin_line *line, u32 pad) ++{ ++ struct stf_vin_dev *vin_dev = line_to_vin_dev(line); ++ int dummy_module = vin_line_to_dummy_module(line); ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[dummy_module]; ++ struct vin_dummy_buffer *buffer = NULL; ++ ++ switch (pad) { ++ case STF_VIN_PAD_SINK: ++ if (line->id == VIN_LINE_WR) { ++ buffer = &dummy_buffer->buffer[STF_VIN_PAD_SINK]; ++ stf_vin_wr_set_ping_addr(vin_dev, buffer->paddr[0]); ++ stf_vin_wr_set_pong_addr(vin_dev, buffer->paddr[0]); ++ } else { ++ buffer = &dummy_buffer->buffer[STF_ISP_PAD_SRC]; ++ stf_vin_isp_set_yuv_addr(vin_dev, ++ buffer->paddr[0], ++ buffer->paddr[1]); ++ } ++ break; ++ case STF_ISP_PAD_SRC: ++ buffer = &dummy_buffer->buffer[STF_ISP_PAD_SRC]; ++ stf_vin_isp_set_yuv_addr(vin_dev, ++ buffer->paddr[0], ++ buffer->paddr[1]); ++ break; ++ default: ++ break; ++ } ++} ++ ++static int vin_set_stream(struct v4l2_subdev *sd, int enable) ++{ ++ struct vin_line *line = v4l2_get_subdevdata(sd); ++ struct stf_vin_dev *vin_dev = line_to_vin_dev(line); ++ int dummy_module = vin_line_to_dummy_module(line); ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[dummy_module]; ++ struct v4l2_mbus_framefmt *fmt; ++ enum link link; ++ ++ fmt = __vin_get_format(line, NULL, ++ STF_VIN_PAD_SINK, V4L2_SUBDEV_FORMAT_ACTIVE); ++ mutex_lock(&dummy_buffer->stream_lock); ++ if (enable) { ++ if (dummy_buffer->stream_count == 0) { ++ vin_alloc_dummy_buffer(vin_dev, fmt, dummy_module); ++ vin_set_dummy_buffer(line, STF_VIN_PAD_SINK); ++ atomic_set(&dummy_buffer->frame_skip, ++ VIN_FRAME_DROP_MIN_VAL); ++ } ++ dummy_buffer->stream_count++; ++ } else { ++ if (dummy_buffer->stream_count == 1) { ++ vin_free_dummy_buffer(vin_dev, dummy_module); ++ /* set buffer addr to zero */ ++ vin_set_dummy_buffer(line, STF_VIN_PAD_SINK); ++ } else { ++ vin_set_dummy_buffer(line, ++ stf_vin_map_isp_pad(line->id, STF_ISP_PAD_SINK)); ++ } ++ ++ dummy_buffer->stream_count--; ++ } ++ mutex_unlock(&dummy_buffer->stream_lock); ++ ++ mutex_lock(&line->stream_lock); ++ link = vin_get_link(&sd->entity); ++ if (link == LINK_ERROR) ++ goto exit; ++ ++ if (enable) { ++ if (line->stream_count == 0) { ++ stf_vin_stream_set(vin_dev, link); ++ if (line->id == VIN_LINE_WR) { ++ stf_vin_wr_irq_enable(vin_dev, 1); ++ stf_vin_wr_stream_set(vin_dev); ++ } ++ } ++ line->stream_count++; ++ } else { ++ if (line->stream_count == 1 && line->id == VIN_LINE_WR) ++ stf_vin_wr_irq_enable(vin_dev, 0); ++ line->stream_count--; ++ } ++exit: ++ mutex_unlock(&line->stream_lock); ++ ++ if (enable) ++ vin_enable_output(line); ++ else ++ vin_disable_output(line); ++ ++ return 0; ++} ++ ++static struct v4l2_mbus_framefmt * ++__vin_get_format(struct vin_line *line, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ enum v4l2_subdev_format_whence which) ++{ ++ if (which == V4L2_SUBDEV_FORMAT_TRY) ++ return v4l2_subdev_get_try_format(&line->subdev, state, pad); ++ return &line->fmt[pad]; ++} ++ ++static void vin_try_format(struct vin_line *line, ++ struct v4l2_subdev_state *state, ++ unsigned int pad, ++ struct v4l2_mbus_framefmt *fmt, ++ enum v4l2_subdev_format_whence which) ++{ ++ unsigned int i; ++ ++ switch (pad) { ++ case STF_VIN_PAD_SINK: ++ /* Set format on sink pad */ ++ for (i = 0; i < line->nformats; i++) ++ if (fmt->code == line->formats[i].code) ++ break; ++ ++ /* If not found, use UYVY as default */ ++ if (i >= line->nformats) ++ fmt->code = line->formats[0].code; ++ ++ fmt->width = clamp_t(u32, fmt->width, ++ STFCAMSS_FRAME_MIN_WIDTH, ++ STFCAMSS_FRAME_MAX_WIDTH); ++ fmt->height = clamp_t(u32, fmt->height, ++ STFCAMSS_FRAME_MIN_HEIGHT, ++ STFCAMSS_FRAME_MAX_HEIGHT); ++ ++ fmt->field = V4L2_FIELD_NONE; ++ fmt->colorspace = V4L2_COLORSPACE_SRGB; ++ fmt->flags = 0; ++ break; ++ ++ case STF_VIN_PAD_SRC: ++ /* Set and return a format same as sink pad */ ++ *fmt = *__vin_get_format(line, state, STF_VIN_PAD_SINK, which); ++ break; ++ } ++ ++ fmt->colorspace = V4L2_COLORSPACE_SRGB; ++} ++ ++static int vin_enum_mbus_code(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_mbus_code_enum *code) ++{ ++ struct vin_line *line = v4l2_get_subdevdata(sd); ++ ++ if (code->index >= line->nformats) ++ return -EINVAL; ++ if (code->pad == STF_VIN_PAD_SINK) { ++ code->code = line->formats[code->index].code; ++ } else { ++ struct v4l2_mbus_framefmt *sink_fmt; ++ ++ sink_fmt = __vin_get_format(line, state, STF_VIN_PAD_SINK, ++ code->which); ++ ++ code->code = sink_fmt->code; ++ if (!code->code) ++ return -EINVAL; ++ } ++ code->flags = 0; ++ ++ return 0; ++} ++ ++static int vin_enum_frame_size(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_frame_size_enum *fse) ++{ ++ struct vin_line *line = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt format; ++ ++ if (fse->index != 0) ++ return -EINVAL; ++ ++ format.code = fse->code; ++ format.width = 1; ++ format.height = 1; ++ vin_try_format(line, state, fse->pad, &format, fse->which); ++ fse->min_width = format.width; ++ fse->min_height = format.height; ++ ++ if (format.code != fse->code) ++ return -EINVAL; ++ ++ format.code = fse->code; ++ format.width = -1; ++ format.height = -1; ++ vin_try_format(line, state, fse->pad, &format, fse->which); ++ fse->max_width = format.width; ++ fse->max_height = format.height; ++ ++ return 0; ++} ++ ++static int vin_get_format(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_format *fmt) ++{ ++ struct vin_line *line = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt *format; ++ ++ format = __vin_get_format(line, state, fmt->pad, fmt->which); ++ if (!format) ++ return -EINVAL; ++ ++ fmt->format = *format; ++ ++ return 0; ++} ++ ++static int vin_set_format(struct v4l2_subdev *sd, ++ struct v4l2_subdev_state *state, ++ struct v4l2_subdev_format *fmt) ++{ ++ struct vin_line *line = v4l2_get_subdevdata(sd); ++ struct v4l2_mbus_framefmt *format; ++ ++ format = __vin_get_format(line, state, fmt->pad, fmt->which); ++ if (!format) ++ return -EINVAL; ++ ++ mutex_lock(&line->stream_lock); ++ if (line->stream_count) { ++ fmt->format = *format; ++ mutex_unlock(&line->stream_lock); ++ goto out; ++ } else { ++ vin_try_format(line, state, fmt->pad, &fmt->format, fmt->which); ++ *format = fmt->format; ++ } ++ mutex_unlock(&line->stream_lock); ++ ++ if (fmt->pad == STF_VIN_PAD_SINK) { ++ /* Propagate the format from sink to source */ ++ format = __vin_get_format(line, state, STF_VIN_PAD_SRC, ++ fmt->which); ++ ++ *format = fmt->format; ++ vin_try_format(line, state, STF_VIN_PAD_SRC, format, ++ fmt->which); ++ } ++ ++out: ++ return 0; ++} ++ ++static int vin_init_formats(struct v4l2_subdev *sd, ++ struct v4l2_subdev_fh *fh) ++{ ++ struct v4l2_subdev_format format = { ++ .pad = STF_VIN_PAD_SINK, ++ .which = fh ? ++ V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE, ++ .format = { ++ .code = MEDIA_BUS_FMT_RGB565_2X8_LE, ++ .width = 1920, ++ .height = 1080 ++ } ++ }; ++ ++ return vin_set_format(sd, fh ? fh->state : NULL, &format); ++} ++ ++static void vin_output_init_addrs(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ struct stf_vin_dev *vin_dev = line_to_vin_dev(line); ++ dma_addr_t ping_addr; ++ dma_addr_t y_addr, uv_addr; ++ ++ output->active_buf = 0; ++ ++ if (output->buf[0]) { ++ ping_addr = output->buf[0]->addr[0]; ++ y_addr = output->buf[0]->addr[0]; ++ uv_addr = output->buf[0]->addr[1]; ++ } else { ++ return; ++ } ++ ++ switch (vin_map_isp_line(line->id)) { ++ case STF_ISP_LINE_SRC: ++ stf_vin_isp_set_yuv_addr(vin_dev, y_addr, uv_addr); ++ break; ++ default: ++ if (line->id == VIN_LINE_WR) { ++ stf_vin_wr_set_ping_addr(vin_dev, ping_addr); ++ stf_vin_wr_set_pong_addr(vin_dev, ping_addr); ++ } ++ break; ++ } ++} ++ ++static void vin_init_outputs(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ ++ output->state = VIN_OUTPUT_OFF; ++ output->buf[0] = NULL; ++ output->buf[1] = NULL; ++ output->active_buf = 0; ++ INIT_LIST_HEAD(&output->pending_bufs); ++ INIT_LIST_HEAD(&output->ready_bufs); ++} ++ ++static void vin_buf_add_ready(struct vin_output *output, ++ struct stfcamss_buffer *buffer) ++{ ++ INIT_LIST_HEAD(&buffer->queue); ++ list_add_tail(&buffer->queue, &output->ready_bufs); ++} ++ ++static struct stfcamss_buffer *vin_buf_get_ready(struct vin_output *output) ++{ ++ struct stfcamss_buffer *buffer = NULL; ++ ++ if (!list_empty(&output->ready_bufs)) { ++ buffer = list_first_entry(&output->ready_bufs, ++ struct stfcamss_buffer, ++ queue); ++ list_del(&buffer->queue); ++ } ++ ++ return buffer; ++} ++ ++static void vin_buf_add_pending(struct vin_output *output, ++ struct stfcamss_buffer *buffer) ++{ ++ INIT_LIST_HEAD(&buffer->queue); ++ list_add_tail(&buffer->queue, &output->pending_bufs); ++} ++ ++static struct stfcamss_buffer *vin_buf_get_pending(struct vin_output *output) ++{ ++ struct stfcamss_buffer *buffer = NULL; ++ ++ if (!list_empty(&output->pending_bufs)) { ++ buffer = list_first_entry(&output->pending_bufs, ++ struct stfcamss_buffer, ++ queue); ++ list_del(&buffer->queue); ++ } ++ ++ return buffer; ++} ++ ++static void vin_buf_update_on_last(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ ++ switch (output->state) { ++ case VIN_OUTPUT_CONTINUOUS: ++ output->state = VIN_OUTPUT_SINGLE; ++ output->active_buf = !output->active_buf; ++ break; ++ case VIN_OUTPUT_SINGLE: ++ output->state = VIN_OUTPUT_STOPPING; ++ break; ++ default: ++ break; ++ } ++} ++ ++static void vin_buf_update_on_next(struct vin_line *line) ++{ ++ struct vin_output *output = &line->output; ++ ++ switch (output->state) { ++ case VIN_OUTPUT_CONTINUOUS: ++ output->active_buf = !output->active_buf; ++ break; ++ case VIN_OUTPUT_SINGLE: ++ default: ++ break; ++ } ++} ++ ++static void vin_buf_update_on_new(struct vin_line *line, ++ struct vin_output *output, ++ struct stfcamss_buffer *new_buf) ++{ ++ switch (output->state) { ++ case VIN_OUTPUT_SINGLE: ++ vin_buf_add_pending(output, new_buf); ++ break; ++ case VIN_OUTPUT_IDLE: ++ if (!output->buf[0]) { ++ output->buf[0] = new_buf; ++ vin_output_init_addrs(line); ++ output->state = VIN_OUTPUT_SINGLE; ++ } else { ++ vin_buf_add_pending(output, new_buf); ++ } ++ break; ++ case VIN_OUTPUT_STOPPING: ++ if (output->last_buffer) { ++ output->buf[output->active_buf] = output->last_buffer; ++ output->last_buffer = NULL; ++ } ++ ++ output->state = VIN_OUTPUT_SINGLE; ++ vin_buf_add_pending(output, new_buf); ++ break; ++ case VIN_OUTPUT_CONTINUOUS: ++ default: ++ vin_buf_add_pending(output, new_buf); ++ break; ++ } ++} ++ ++static void vin_buf_flush(struct vin_output *output, ++ enum vb2_buffer_state state) ++{ ++ struct stfcamss_buffer *buf; ++ struct stfcamss_buffer *t; ++ ++ list_for_each_entry_safe(buf, t, &output->pending_bufs, queue) { ++ vb2_buffer_done(&buf->vb.vb2_buf, state); ++ list_del(&buf->queue); ++ } ++ list_for_each_entry_safe(buf, t, &output->ready_bufs, queue) { ++ vb2_buffer_done(&buf->vb.vb2_buf, state); ++ list_del(&buf->queue); ++ } ++} ++ ++static void vin_buffer_done(struct vin_line *line) ++{ ++ struct stfcamss_buffer *ready_buf; ++ struct vin_output *output = &line->output; ++ unsigned long flags; ++ u64 ts = ktime_get_ns(); ++ ++ if (output->state == VIN_OUTPUT_OFF || ++ output->state == VIN_OUTPUT_RESERVED) ++ return; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ while ((ready_buf = vin_buf_get_ready(output))) { ++ ready_buf->vb.vb2_buf.timestamp = ts; ++ ready_buf->vb.sequence = output->sequence++; ++ ++ vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); ++ } ++ ++ spin_unlock_irqrestore(&line->output_lock, flags); ++} ++ ++static void vin_change_buffer(struct vin_line *line) ++{ ++ struct stfcamss_buffer *ready_buf; ++ struct vin_output *output = &line->output; ++ struct stf_vin_dev *vin_dev = line_to_vin_dev(line); ++ dma_addr_t *new_addr; ++ unsigned long flags; ++ u32 active_index; ++ ++ if (output->state == VIN_OUTPUT_OFF || ++ output->state == VIN_OUTPUT_STOPPING || ++ output->state == VIN_OUTPUT_RESERVED || ++ output->state == VIN_OUTPUT_IDLE) ++ return; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ active_index = output->active_buf; ++ ++ ready_buf = output->buf[active_index]; ++ if (!ready_buf) { ++ dev_warn(vin_dev->stfcamss->dev, "Missing ready buf %d %d!\n", ++ active_index, output->state); ++ active_index = !active_index; ++ ready_buf = output->buf[active_index]; ++ if (!ready_buf) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Missing ready buf2 %d %d!\n", ++ active_index, output->state); ++ goto out_unlock; ++ } ++ } ++ ++ /* Get next buffer */ ++ output->buf[active_index] = vin_buf_get_pending(output); ++ if (!output->buf[active_index]) { ++ /* No next buffer - set same address */ ++ new_addr = ready_buf->addr; ++ vin_buf_update_on_last(line); ++ } else { ++ new_addr = output->buf[active_index]->addr; ++ vin_buf_update_on_next(line); ++ } ++ ++ if (output->state == VIN_OUTPUT_STOPPING) { ++ output->last_buffer = ready_buf; ++ } else { ++ switch (vin_map_isp_line(line->id)) { ++ case STF_ISP_LINE_SRC: ++ stf_vin_isp_set_yuv_addr(vin_dev, ++ new_addr[0], ++ new_addr[1]); ++ break; ++ default: ++ if (line->id == VIN_LINE_WR) { ++ stf_vin_wr_set_ping_addr(vin_dev, new_addr[0]); ++ stf_vin_wr_set_pong_addr(vin_dev, new_addr[0]); ++ } ++ break; ++ } ++ ++ vin_buf_add_ready(output, ready_buf); ++ } ++ ++ spin_unlock_irqrestore(&line->output_lock, flags); ++ return; ++ ++out_unlock: ++ spin_unlock_irqrestore(&line->output_lock, flags); ++} ++ ++static int vin_queue_buffer(struct stfcamss_video *vid, ++ struct stfcamss_buffer *buf) ++{ ++ struct vin_line *line = container_of(vid, struct vin_line, video_out); ++ struct vin_output *output; ++ unsigned long flags; ++ ++ output = &line->output; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ vin_buf_update_on_new(line, output, buf); ++ ++ spin_unlock_irqrestore(&line->output_lock, flags); ++ ++ return 0; ++} ++ ++static int vin_flush_buffers(struct stfcamss_video *vid, ++ enum vb2_buffer_state state) ++{ ++ struct vin_line *line = container_of(vid, struct vin_line, video_out); ++ struct vin_output *output = &line->output; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&line->output_lock, flags); ++ ++ vin_buf_flush(output, state); ++ if (output->buf[0]) ++ vb2_buffer_done(&output->buf[0]->vb.vb2_buf, state); ++ ++ if (output->buf[1]) ++ vb2_buffer_done(&output->buf[1]->vb.vb2_buf, state); ++ ++ if (output->last_buffer) { ++ vb2_buffer_done(&output->last_buffer->vb.vb2_buf, state); ++ output->last_buffer = NULL; ++ } ++ output->buf[0] = NULL; ++ output->buf[1] = NULL; ++ ++ spin_unlock_irqrestore(&line->output_lock, flags); ++ return 0; ++} ++ ++static int vin_link_setup(struct media_entity *entity, ++ const struct media_pad *local, ++ const struct media_pad *remote, u32 flags) ++{ ++ if (flags & MEDIA_LNK_FL_ENABLED) ++ if (media_pad_remote_pad_first(local)) ++ return -EBUSY; ++ return 0; ++} ++ ++static const struct v4l2_subdev_video_ops vin_video_ops = { ++ .s_stream = vin_set_stream, ++}; ++ ++static const struct v4l2_subdev_pad_ops vin_pad_ops = { ++ .enum_mbus_code = vin_enum_mbus_code, ++ .enum_frame_size = vin_enum_frame_size, ++ .get_fmt = vin_get_format, ++ .set_fmt = vin_set_format, ++}; ++ ++static const struct v4l2_subdev_ops vin_v4l2_ops = { ++ .video = &vin_video_ops, ++ .pad = &vin_pad_ops, ++}; ++ ++static const struct v4l2_subdev_internal_ops vin_v4l2_internal_ops = { ++ .open = vin_init_formats, ++}; ++ ++static const struct stfcamss_video_ops stfcamss_vin_video_ops = { ++ .queue_buffer = vin_queue_buffer, ++ .flush_buffers = vin_flush_buffers, ++}; ++ ++static const struct media_entity_operations vin_media_ops = { ++ .link_setup = vin_link_setup, ++ .link_validate = v4l2_subdev_link_validate, ++}; ++ ++int stf_vin_register(struct stf_vin_dev *vin_dev, struct v4l2_device *v4l2_dev) ++{ ++ struct v4l2_subdev *sd; ++ struct stfcamss_video *video_out; ++ struct media_pad *pads; ++ int ret; ++ int i; ++ ++ for (i = 0; i < STF_ISP_LINE_MAX + 1; i++) { ++ char name[32]; ++ char *sub_name = vin_get_line_subdevname(i); ++ ++ sd = &vin_dev->line[i].subdev; ++ pads = vin_dev->line[i].pads; ++ video_out = &vin_dev->line[i].video_out; ++ video_out->id = i; ++ ++ vin_init_outputs(&vin_dev->line[i]); ++ ++ v4l2_subdev_init(sd, &vin_v4l2_ops); ++ sd->internal_ops = &vin_v4l2_internal_ops; ++ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; ++ snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d_%s", ++ STF_VIN_NAME, 0, sub_name); ++ v4l2_set_subdevdata(sd, &vin_dev->line[i]); ++ ++ ret = vin_init_formats(sd, NULL); ++ if (ret < 0) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Failed to init format: %d\n", ret); ++ goto err_init; ++ } ++ ++ pads[STF_VIN_PAD_SINK].flags = MEDIA_PAD_FL_SINK; ++ pads[STF_VIN_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; ++ ++ sd->entity.function = ++ MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; ++ sd->entity.ops = &vin_media_ops; ++ ret = media_entity_pads_init(&sd->entity, ++ STF_VIN_PADS_NUM, pads); ++ if (ret < 0) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Failed to init media entity: %d\n", ++ ret); ++ goto err_init; ++ } ++ ++ ret = v4l2_device_register_subdev(v4l2_dev, sd); ++ if (ret < 0) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Failed to register subdev: %d\n", ret); ++ goto err_reg_subdev; ++ } ++ ++ video_out->ops = &stfcamss_vin_video_ops; ++ video_out->bpl_alignment = 16 * 8; ++ ++ snprintf(name, ARRAY_SIZE(name), "%s_%s%d", ++ sd->name, "video", i); ++ ret = stf_video_register(video_out, v4l2_dev, name); ++ if (ret < 0) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Failed to register video node: %d\n", ret); ++ goto err_vid_reg; ++ } ++ ++ ret = media_create_pad_link( ++ &sd->entity, STF_VIN_PAD_SRC, ++ &video_out->vdev.entity, 0, ++ MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); ++ if (ret < 0) { ++ dev_err(vin_dev->stfcamss->dev, ++ "Failed to link %s->%s entities: %d\n", ++ sd->entity.name, video_out->vdev.entity.name, ++ ret); ++ goto err_create_link; ++ } ++ } ++ ++ return 0; ++ ++err_create_link: ++ stf_video_unregister(video_out); ++err_vid_reg: ++ v4l2_device_unregister_subdev(sd); ++err_reg_subdev: ++ media_entity_cleanup(&sd->entity); ++err_init: ++ for (i--; i >= 0; i--) { ++ sd = &vin_dev->line[i].subdev; ++ video_out = &vin_dev->line[i].video_out; ++ ++ stf_video_unregister(video_out); ++ v4l2_device_unregister_subdev(sd); ++ media_entity_cleanup(&sd->entity); ++ } ++ return ret; ++} ++ ++int stf_vin_unregister(struct stf_vin_dev *vin_dev) ++{ ++ struct v4l2_subdev *sd; ++ struct stfcamss_video *video_out; ++ int i; ++ ++ for (i = 0; i < STF_DUMMY_MODULE_NUMS; i++) ++ mutex_destroy(&vin_dev->dummy_buffer[i].stream_lock); ++ ++ for (i = 0; i < STF_ISP_LINE_MAX + 1; i++) { ++ sd = &vin_dev->line[i].subdev; ++ video_out = &vin_dev->line[i].video_out; ++ ++ stf_video_unregister(video_out); ++ v4l2_device_unregister_subdev(sd); ++ media_entity_cleanup(&sd->entity); ++ mutex_destroy(&vin_dev->line[i].stream_lock); ++ } ++ return 0; ++} +diff --git a/drivers/media/platform/starfive/camss/stf_vin.h b/drivers/media/platform/starfive/camss/stf_vin.h +new file mode 100644 +index 000000000000..28572eb6abe4 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_vin.h +@@ -0,0 +1,173 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * stf_vin.h ++ * ++ * StarFive Camera Subsystem - VIN Module ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef STF_VIN_H ++#define STF_VIN_H ++ ++#include ++#include ++#include ++ ++#include "stf_video.h" ++ ++#define SYSCONSAIF_SYSCFG(x) (x) ++ ++/* syscon offset 0 */ ++#define U0_VIN_CNFG_AXI_DVP_EN BIT(2) ++ ++/* syscon offset 20 */ ++#define U0_VIN_CHANNEL_SEL_MASK GENMASK(3, 0) ++#define U0_VIN_AXIWR0_EN BIT(4) ++#define CHANNEL(x) ((x) << 0) ++ ++/* syscon offset 32 */ ++#define U0_VIN_INTR_CLEAN BIT(0) ++#define U0_VIN_INTR_M BIT(1) ++#define U0_VIN_PIX_CNT_END_MASK GENMASK(12, 2) ++#define U0_VIN_PIX_CT_MASK GENMASK(14, 13) ++#define U0_VIN_PIXEL_HEIGH_BIT_SEL_MAKS GENMASK(16, 15) ++ ++#define PIX_CNT_END(x) ((x) << 2) ++#define PIX_CT(x) ((x) << 13) ++#define PIXEL_HEIGH_BIT_SEL(x) ((x) << 15) ++ ++/* syscon offset 36 */ ++#define U0_VIN_CNFG_DVP_HS_POS BIT(1) ++#define U0_VIN_CNFG_DVP_SWAP_EN BIT(2) ++#define U0_VIN_CNFG_DVP_VS_POS BIT(3) ++#define U0_VIN_CNFG_GEN_EN_AXIRD BIT(4) ++#define U0_VIN_CNFG_ISP_DVP_EN0 BIT(5) ++#define U0_VIN_MIPI_BYTE_EN_ISP0(n) ((n) << 6) ++#define U0_VIN_MIPI_CHANNEL_SEL0(n) ((n) << 8) ++#define U0_VIN_P_I_MIPI_HAEDER_EN0(n) ((n) << 12) ++#define U0_VIN_PIX_NUM(n) ((n) << 13) ++#define U0_VIN_MIPI_BYTE_EN_ISP0_MASK GENMASK(7, 6) ++#define U0_VIN_MIPI_CHANNEL_SEL0_MASK GENMASK(11, 8) ++#define U0_VIN_P_I_MIPI_HAEDER_EN0_MASK BIT(12) ++#define U0_VIN_PIX_NUM_MASK GENMASK(16, 13) ++ ++#define STF_VIN_PAD_SINK 0 ++#define STF_VIN_PAD_SRC 1 ++#define STF_VIN_PADS_NUM 2 ++ ++#define ISP_DUMMY_BUFFER_NUMS STF_ISP_PAD_MAX ++#define VIN_DUMMY_BUFFER_NUMS 1 ++ ++enum { ++ STF_DUMMY_VIN, ++ STF_DUMMY_ISP, ++ STF_DUMMY_MODULE_NUMS, ++}; ++ ++enum link { ++ LINK_ERROR = -1, ++ LINK_DVP_TO_WR, ++ LINK_DVP_TO_ISP, ++ LINK_CSI_TO_WR, ++ LINK_CSI_TO_ISP, ++}; ++ ++struct vin_format { ++ u32 code; ++ u8 bpp; ++}; ++ ++struct vin_format_table { ++ const struct vin_format *fmts; ++ int nfmts; ++}; ++ ++enum vin_output_state { ++ VIN_OUTPUT_OFF, ++ VIN_OUTPUT_RESERVED, ++ VIN_OUTPUT_SINGLE, ++ VIN_OUTPUT_CONTINUOUS, ++ VIN_OUTPUT_IDLE, ++ VIN_OUTPUT_STOPPING ++}; ++ ++struct vin_output { ++ int active_buf; ++ struct stfcamss_buffer *buf[2]; ++ struct stfcamss_buffer *last_buffer; ++ struct list_head pending_bufs; ++ struct list_head ready_bufs; ++ enum vin_output_state state; ++ unsigned int sequence; ++ unsigned int frame_skip; ++}; ++ ++/* The vin output lines */ ++enum vin_line_id { ++ VIN_LINE_NONE = -1, ++ VIN_LINE_WR = 0, ++ VIN_LINE_ISP, ++ VIN_LINE_MAX, ++}; ++ ++struct vin_line { ++ enum vin_line_id id; ++ struct v4l2_subdev subdev; ++ struct media_pad pads[STF_VIN_PADS_NUM]; ++ struct v4l2_mbus_framefmt fmt[STF_VIN_PADS_NUM]; ++ struct stfcamss_video video_out; ++ struct mutex stream_lock; /* serialize stream control */ ++ int stream_count; ++ struct vin_output output; /* pipeline and stream states */ ++ spinlock_t output_lock; ++ const struct vin_format *formats; ++ unsigned int nformats; ++}; ++ ++struct vin_dummy_buffer { ++ dma_addr_t paddr[3]; ++ void *vaddr; ++ u32 buffer_size; ++ u32 width; ++ u32 height; ++ u32 mcode; ++}; ++ ++struct dummy_buffer { ++ struct vin_dummy_buffer *buffer; ++ u32 nums; ++ struct mutex stream_lock; /* protects buffer data */ ++ int stream_count; ++ atomic_t frame_skip; ++}; ++ ++struct vin_isr_ops { ++ void (*isr_buffer_done)(struct vin_line *line); ++ void (*isr_change_buffer)(struct vin_line *line); ++}; ++ ++struct stf_vin_dev { ++ struct stfcamss *stfcamss; ++ struct vin_line line[VIN_LINE_MAX]; ++ struct dummy_buffer dummy_buffer[STF_DUMMY_MODULE_NUMS]; ++ struct vin_isr_ops *isr_ops; ++ atomic_t ref_count; ++}; ++ ++int stf_vin_wr_stream_set(struct stf_vin_dev *vin_dev); ++int stf_vin_stream_set(struct stf_vin_dev *vin_dev, enum link link); ++void stf_vin_wr_irq_enable(struct stf_vin_dev *vin_dev, int enable); ++void stf_vin_wr_set_ping_addr(struct stf_vin_dev *vin_dev, dma_addr_t addr); ++void stf_vin_wr_set_pong_addr(struct stf_vin_dev *vin_dev, dma_addr_t addr); ++void stf_vin_isp_set_yuv_addr(struct stf_vin_dev *vin_dev, ++ dma_addr_t y_addr, dma_addr_t uv_addr); ++irqreturn_t stf_vin_wr_irq_handler(int irq, void *priv); ++irqreturn_t stf_vin_isp_irq_handler(int irq, void *priv); ++irqreturn_t stf_vin_isp_irq_csiline_handler(int irq, void *priv); ++int stf_vin_subdev_init(struct stfcamss *stfcamss); ++int stf_vin_register(struct stf_vin_dev *vin_dev, struct v4l2_device *v4l2_dev); ++int stf_vin_unregister(struct stf_vin_dev *vin_dev); ++enum isp_pad_id stf_vin_map_isp_pad(enum vin_line_id line, enum isp_pad_id def); ++ ++#endif /* STF_VIN_H */ +diff --git a/drivers/media/platform/starfive/camss/stf_vin_hw_ops.c b/drivers/media/platform/starfive/camss/stf_vin_hw_ops.c +new file mode 100644 +index 000000000000..7bd3265128d0 +--- /dev/null ++++ b/drivers/media/platform/starfive/camss/stf_vin_hw_ops.c +@@ -0,0 +1,192 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * stf_vin_hw_ops.c ++ * ++ * Register interface file for StarFive VIN module driver ++ * ++ * Copyright (C) 2021-2023 StarFive Technology Co., Ltd. ++ */ ++#include "stf_camss.h" ++ ++static void vin_intr_clear(struct stfcamss *stfcamss) ++{ ++ stf_syscon_reg_set_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_CLEAN); ++ stf_syscon_reg_clear_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_CLEAN); ++} ++ ++irqreturn_t stf_vin_wr_irq_handler(int irq, void *priv) ++{ ++ struct stf_vin_dev *vin_dev = priv; ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[STF_DUMMY_VIN]; ++ ++ if (atomic_dec_if_positive(&dummy_buffer->frame_skip) < 0) { ++ vin_dev->isr_ops->isr_change_buffer(&vin_dev->line[VIN_LINE_WR]); ++ vin_dev->isr_ops->isr_buffer_done(&vin_dev->line[VIN_LINE_WR]); ++ } ++ ++ vin_intr_clear(stfcamss); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t stf_vin_isp_irq_handler(int irq, void *priv) ++{ ++ struct stf_vin_dev *vin_dev = priv; ++ u32 int_status; ++ ++ int_status = stf_isp_reg_read(vin_dev->stfcamss, ISP_REG_ISP_CTRL_0); ++ ++ if (int_status & ISPC_INTS) { ++ if ((int_status & ISPC_ENUO)) ++ vin_dev->isr_ops->isr_buffer_done( ++ &vin_dev->line[VIN_LINE_ISP]); ++ ++ /* clear interrupt */ ++ stf_isp_reg_write(vin_dev->stfcamss, ++ ISP_REG_ISP_CTRL_0, ++ (int_status & ~EN_INT_ALL) | ++ EN_INT_ISP_DONE | ++ EN_INT_CSI_DONE | ++ EN_INT_SC_DONE); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t stf_vin_isp_irq_csiline_handler(int irq, void *priv) ++{ ++ struct stf_vin_dev *vin_dev = priv; ++ struct stf_isp_dev *isp_dev; ++ u32 int_status; ++ ++ isp_dev = &vin_dev->stfcamss->isp_dev; ++ ++ int_status = stf_isp_reg_read(vin_dev->stfcamss, ISP_REG_ISP_CTRL_0); ++ if (int_status & ISPC_SCFEINT) { ++ struct dummy_buffer *dummy_buffer = ++ &vin_dev->dummy_buffer[STF_DUMMY_ISP]; ++ ++ if (atomic_dec_if_positive(&dummy_buffer->frame_skip) < 0) { ++ if ((int_status & ISPC_ENUO)) ++ vin_dev->isr_ops->isr_change_buffer( ++ &vin_dev->line[VIN_LINE_ISP]); ++ } ++ ++ stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_CSIINTS, ++ CSI_INTS_MASK, CSI_INTS(0x3)); ++ stf_isp_reg_set_bit(isp_dev->stfcamss, ISP_REG_IESHD, ++ SHAD_UP_M | SHAD_UP_EN, 0x3); ++ ++ /* clear interrupt */ ++ stf_isp_reg_write(vin_dev->stfcamss, ISP_REG_ISP_CTRL_0, ++ (int_status & ~EN_INT_ALL) | EN_INT_LINE_INT); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++int stf_vin_wr_stream_set(struct stf_vin_dev *vin_dev) ++{ ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ ++ stf_syscon_reg_set_bit(stfcamss, SYSCONSAIF_SYSCFG(20), ++ U0_VIN_AXIWR0_EN); ++ ++ return 0; ++} ++ ++int stf_vin_stream_set(struct stf_vin_dev *vin_dev, enum link link) ++{ ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ u32 val; ++ ++ switch (link) { ++ case LINK_CSI_TO_WR: ++ val = stf_syscon_reg_read(stfcamss, SYSCONSAIF_SYSCFG(20)); ++ val &= ~U0_VIN_CHANNEL_SEL_MASK; ++ val |= CHANNEL(0); ++ stf_syscon_reg_write(stfcamss, SYSCONSAIF_SYSCFG(20), val); ++ ++ val = stf_syscon_reg_read(stfcamss, SYSCONSAIF_SYSCFG(28)); ++ val &= ~U0_VIN_PIX_CT_MASK; ++ val |= PIX_CT(1); ++ ++ val &= ~U0_VIN_PIXEL_HEIGH_BIT_SEL_MAKS; ++ val |= PIXEL_HEIGH_BIT_SEL(0); ++ ++ val &= ~U0_VIN_PIX_CNT_END_MASK; ++ val |= PIX_CNT_END(IMAGE_MAX_WIDTH / 4 - 1); ++ ++ stf_syscon_reg_write(stfcamss, SYSCONSAIF_SYSCFG(28), val); ++ break; ++ case LINK_CSI_TO_ISP: ++ val = stf_syscon_reg_read(stfcamss, SYSCONSAIF_SYSCFG(36)); ++ val &= ~U0_VIN_MIPI_BYTE_EN_ISP0_MASK; ++ val |= U0_VIN_MIPI_BYTE_EN_ISP0(0); ++ ++ val &= ~U0_VIN_MIPI_CHANNEL_SEL0_MASK; ++ val |= U0_VIN_MIPI_CHANNEL_SEL0(0); ++ ++ val &= ~U0_VIN_PIX_NUM_MASK; ++ val |= U0_VIN_PIX_NUM(0); ++ ++ val &= ~U0_VIN_P_I_MIPI_HAEDER_EN0_MASK; ++ val |= U0_VIN_P_I_MIPI_HAEDER_EN0(1); ++ ++ stf_syscon_reg_write(stfcamss, SYSCONSAIF_SYSCFG(36), val); ++ break; ++ case LINK_DVP_TO_WR: ++ case LINK_DVP_TO_ISP: ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++void stf_vin_wr_irq_enable(struct stf_vin_dev *vin_dev, int enable) ++{ ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ ++ if (enable) { ++ stf_syscon_reg_clear_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_M); ++ } else { ++ /* clear vin interrupt */ ++ stf_syscon_reg_set_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_CLEAN); ++ stf_syscon_reg_clear_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_CLEAN); ++ stf_syscon_reg_set_bit(stfcamss, SYSCONSAIF_SYSCFG(28), ++ U0_VIN_INTR_M); ++ } ++} ++ ++void stf_vin_wr_set_ping_addr(struct stf_vin_dev *vin_dev, dma_addr_t addr) ++{ ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ ++ /* set the start address */ ++ stf_syscon_reg_write(stfcamss, SYSCONSAIF_SYSCFG(32), (long)addr); ++} ++ ++void stf_vin_wr_set_pong_addr(struct stf_vin_dev *vin_dev, dma_addr_t addr) ++{ ++ struct stfcamss *stfcamss = vin_dev->stfcamss; ++ ++ /* set the start address */ ++ stf_syscon_reg_write(stfcamss, SYSCONSAIF_SYSCFG(24), (long)addr); ++} ++ ++void stf_vin_isp_set_yuv_addr(struct stf_vin_dev *vin_dev, ++ dma_addr_t y_addr, dma_addr_t uv_addr) ++{ ++ stf_isp_reg_write(vin_dev->stfcamss, ++ ISP_REG_Y_PLANE_START_ADDR, y_addr); ++ stf_isp_reg_write(vin_dev->stfcamss, ++ ISP_REG_UV_PLANE_START_ADDR, uv_addr); ++} +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0050-dt-bindings-display-Add-yamls-for-JH7110-display-sub.patch b/srcpkgs/linux6.4/patches/0050-dt-bindings-display-Add-yamls-for-JH7110-display-sub.patch new file mode 100644 index 0000000000000..8c65355f8fa34 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0050-dt-bindings-display-Add-yamls-for-JH7110-display-sub.patch @@ -0,0 +1,300 @@ +From 1f2f29085cc9adff2635b0a391afc3f70133b854 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:35 +0800 +Subject: [PATCH 50/72] dt-bindings: display: Add yamls for JH7110 display + subsystem + +Add bindings for JH7110 display subsystem which +has a display controller verisilicon dc8200 +and an HDMI interface. + +Signed-off-by: Keith Zhao +--- + .../display/verisilicon/starfive-hdmi.yaml | 93 +++++++++++++++ + .../display/verisilicon/verisilicon-dc.yaml | 110 ++++++++++++++++++ + .../display/verisilicon/verisilicon-drm.yaml | 42 +++++++ + .../devicetree/bindings/vendor-prefixes.yaml | 2 + + 4 files changed, 247 insertions(+) + create mode 100644 Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml + create mode 100644 Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml + create mode 100644 Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml + +diff --git a/Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml b/Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml +new file mode 100644 +index 000000000000..c30b7954a355 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/verisilicon/starfive-hdmi.yaml +@@ -0,0 +1,93 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/verisilicon/starfive-hdmi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive HDMI transmiter ++ ++description: ++ The StarFive SoC uses the HDMI signal transmiter based on innosilicon IP ++ to generate HDMI signal from its input and transmit the signal to the screen. ++ ++maintainers: ++ - Keith Zhao ++ - ShengYang Chen ++ ++properties: ++ compatible: ++ const: starfive,hdmi ++ ++ reg: ++ minItems: 1 ++ ++ interrupts: ++ items: ++ - description: The HDMI hot plug detection interrupt. ++ ++ clocks: ++ items: ++ - description: System clock of HDMI module. ++ - description: Mclk clock of HDMI audio. ++ - description: Bclk clock of HDMI audio. ++ - description: Pixel clock generated by HDMI module. ++ ++ clock-names: ++ items: ++ - const: sysclk ++ - const: mclk ++ - const: bclk ++ - const: pclk ++ ++ resets: ++ items: ++ - description: Reset for HDMI module. ++ ++ reset-names: ++ items: ++ - const: hdmi_tx ++ ++ '#sound-dai-cells': ++ const: 0 ++ ++ port: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Port node with one endpoint connected to a display connector node. ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - '#sound-dai-cells' ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ hdmi: hdmi@29590000 { ++ compatible = "starfive,hdmi"; ++ reg = <0x29590000 0x4000>; ++ interrupts = <99>; ++ clocks = <&voutcrg 17>, ++ <&voutcrg 15>, ++ <&voutcrg 16>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "sysclk", "mclk","bclk","pclk"; ++ resets = <&voutcrg 9>; ++ reset-names = "hdmi_tx"; ++ #sound-dai-cells = <0>; ++ hdmi_in: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ hdmi_input: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dc_out_dpi0>; ++ }; ++ }; ++ }; +diff --git a/Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml +new file mode 100644 +index 000000000000..1322502c4cde +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml +@@ -0,0 +1,110 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/verisilicon/verisilicon-dc.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive display controller ++ ++description: ++ The StarFive SoC uses the display controller based on Verisilicon IP ++ to transfer the image data from a video memory ++ buffer to an external LCD interface. ++ ++maintainers: ++ - Keith Zhao ++ - ShengYang Chen ++ ++properties: ++ compatible: ++ const: verisilicon,dc8200 ++ ++ reg: ++ maxItems: 3 ++ ++ interrupts: ++ items: ++ - description: The interrupt will be generated when DC finish one frame ++ ++ clocks: ++ items: ++ - description: Clock for display system noc bus. ++ - description: Pixel clock for display channel 0. ++ - description: Pixel clock for display channel 1. ++ - description: Clock for axi interface of display controller. ++ - description: Core clock for display controller. ++ - description: Clock for ahb interface of display controller. ++ - description: External HDMI pixel clock. ++ - description: Parent clock for pixel clock ++ ++ clock-names: ++ items: ++ - const: clk_vout_noc_disp ++ - const: clk_vout_pix0 ++ - const: clk_vout_pix1 ++ - const: clk_vout_axi ++ - const: clk_vout_core ++ - const: clk_vout_vout_ahb ++ - const: hdmitx0_pixel ++ - const: clk_vout_dc8200 ++ ++ resets: ++ items: ++ - description: Reset for axi interface of display controller. ++ - description: Reset for ahb interface of display controller. ++ - description: Core reset of display controller. ++ ++ reset-names: ++ items: ++ - const: rst_vout_axi ++ - const: rst_vout_ahb ++ - const: rst_vout_core ++ ++ port: ++ $ref: /schemas/graph.yaml#/properties/port ++ description: ++ Port node with one endpoint connected to a hdmi node. ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - clocks ++ - clock-names ++ - resets ++ - reset-names ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ dc8200: dc8200@29400000 { ++ compatible = "verisilicon,dc8200"; ++ reg = <0x29400000 0x100>, ++ <0x29400800 0x2000>, ++ <0x295B0000 0x90>; ++ interrupts = <95>; ++ clocks = <&syscrg 60>, ++ <&voutcrg 7>, ++ <&voutcrg 8>, ++ <&voutcrg 4>, ++ <&voutcrg 5>, ++ <&voutcrg 6>, ++ <&hdmitx0_pixelclk>, ++ <&voutcrg 1>; ++ clock-names = "clk_vout_noc_disp", "clk_vout_pix0", "clk_vout_pix1", "clk_vout_axi", ++ "clk_vout_core", "clk_vout_vout_ahb", "hdmitx0_pixel","clk_vout_dc8200"; ++ resets = <&voutcrg 0>, ++ <&voutcrg 1>, ++ <&voutcrg 2>; ++ reset-names = "rst_vout_axi","rst_vout_ahb","rst_vout_core"; ++ dc_out: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dc_out_dpi0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&hdmi_input>; ++ }; ++ }; ++ }; +diff --git a/Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml +new file mode 100644 +index 000000000000..aed8d4af2c55 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/verisilicon/verisilicon-drm.yaml +@@ -0,0 +1,42 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/verisilicon/verisilicon-drm.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Verisilicon DRM master device ++ ++maintainers: ++ - Keith Zhao ++ - ShengYang Chen ++ ++description: | ++ The Verisilicon DRM master device is a virtual device needed to list all ++ display controller or other display interface nodes that comprise the ++ graphics subsystem. ++ ++properties: ++ compatible: ++ const: verisilicon,display-subsystem ++ ++ ports: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ maxItems: 1 ++ description: | ++ Should contain a list of phandles pointing to display interface ports ++ of display controller devices. Display controller definitions as defined in ++ Documentation/devicetree/bindings/display/verisilicon/verisilicon-dc.yaml ++ ++required: ++ - compatible ++ - ports ++ ++additionalProperties: false ++ ++examples: ++ - | ++ display-subsystem { ++ compatible = "verisilicon,display-subsystem"; ++ ports = <&dc_out>; ++ }; +diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml +index 82d39ab0231b..52c04fd098be 100644 +--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml ++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml +@@ -1436,6 +1436,8 @@ patternProperties: + description: Variscite Ltd. + "^vdl,.*": + description: Van der Laan b.v. ++ "^verisilicon,.*": ++ description: Verisilicon Technologies, Inc. + "^vertexcom,.*": + description: Vertexcom Technologies, Inc. + "^via,.*": +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0051-drm-verisilicon-Add-basic-drm-driver.patch b/srcpkgs/linux6.4/patches/0051-drm-verisilicon-Add-basic-drm-driver.patch new file mode 100644 index 0000000000000..e2b3994e67e09 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0051-drm-verisilicon-Add-basic-drm-driver.patch @@ -0,0 +1,581 @@ +From 15a62ad54809694779212d4bcdfe8f065b5cd9e5 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:37 +0800 +Subject: [PATCH 51/72] drm/verisilicon: Add basic drm driver + +Add a basic platform driver of the DRM driver for JH7110 SoC. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/Kconfig | 2 + + drivers/gpu/drm/Makefile | 1 + + drivers/gpu/drm/verisilicon/Kconfig | 13 ++ + drivers/gpu/drm/verisilicon/Makefile | 6 + + drivers/gpu/drm/verisilicon/vs_drv.c | 284 +++++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_drv.h | 48 +++++ + include/uapi/drm/drm_fourcc.h | 83 ++++++++ + include/uapi/drm/vs_drm.h | 50 +++++ + 8 files changed, 487 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/Kconfig + create mode 100644 drivers/gpu/drm/verisilicon/Makefile + create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.h + create mode 100644 include/uapi/drm/vs_drm.h + +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index ba3fb04bb691..f7e461fa4656 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -371,6 +371,8 @@ source "drivers/gpu/drm/solomon/Kconfig" + + source "drivers/gpu/drm/sprd/Kconfig" + ++source "drivers/gpu/drm/verisilicon/Kconfig" ++ + config DRM_HYPERV + tristate "DRM Support for Hyper-V synthetic video device" + depends on DRM && PCI && MMU && HYPERV +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index a33257d2bc7f..e50622ee4e46 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -194,3 +194,4 @@ obj-y += gud/ + obj-$(CONFIG_DRM_HYPERV) += hyperv/ + obj-y += solomon/ + obj-$(CONFIG_DRM_SPRD) += sprd/ ++obj-$(CONFIG_DRM_VERISILICON) += verisilicon/ +diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig +new file mode 100644 +index 000000000000..89d12185f73b +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Kconfig +@@ -0,0 +1,13 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++config DRM_VERISILICON ++ tristate "DRM Support for VeriSilicon" ++ depends on DRM ++ select DRM_KMS_HELPER ++ select CMA ++ select DMA_CMA ++ help ++ Choose this option if you have a VeriSilicon soc chipset. ++ This driver provides VeriSilicon kernel mode ++ setting and buffer management. It does not ++ provide 2D or 3D acceleration. +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +new file mode 100644 +index 000000000000..64ce1b26546c +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0 ++ ++vs_drm-objs := vs_drv.o ++ ++obj-$(CONFIG_DRM_VERISILICON) += vs_drm.o ++ +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +new file mode 100644 +index 000000000000..24d333598477 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -0,0 +1,284 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_drv.h" ++ ++#define DRV_NAME "starfive" ++#define DRV_DESC "Starfive DRM driver" ++#define DRV_DATE "202305161" ++#define DRV_MAJOR 1 ++#define DRV_MINOR 0 ++ ++static struct platform_driver vs_drm_platform_driver; ++ ++static const struct file_operations fops = { ++ .owner = THIS_MODULE, ++ .open = drm_open, ++ .release = drm_release, ++ .unlocked_ioctl = drm_ioctl, ++ .compat_ioctl = drm_compat_ioctl, ++ .poll = drm_poll, ++ .read = drm_read, ++}; ++ ++static struct drm_driver vs_drm_driver = { ++ .driver_features = DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM, ++ .lastclose = drm_fb_helper_lastclose, ++ .prime_handle_to_fd = drm_gem_prime_handle_to_fd, ++ .prime_fd_to_handle = drm_gem_prime_fd_to_handle, ++ .fops = &fops, ++ .name = DRV_NAME, ++ .desc = DRV_DESC, ++ .date = DRV_DATE, ++ .major = DRV_MAJOR, ++ .minor = DRV_MINOR, ++}; ++ ++void vs_drm_update_pitch_alignment(struct drm_device *drm_dev, ++ unsigned int alignment) ++{ ++ struct vs_drm_private *priv = drm_dev->dev_private; ++ ++ if (alignment > priv->pitch_alignment) ++ priv->pitch_alignment = alignment; ++} ++ ++static int vs_drm_bind(struct device *dev) ++{ ++ struct drm_device *drm_dev; ++ struct vs_drm_private *priv; ++ int ret; ++ static u64 dma_mask = DMA_BIT_MASK(40); ++ ++ /* Remove existing drivers that may own the framebuffer memory. */ ++ ret = drm_aperture_remove_framebuffers(false, &vs_drm_driver); ++ if (ret) { ++ DRM_DEV_ERROR(dev, ++ "Failed to remove existing framebuffers - %d.\n", ++ ret); ++ return ret; ++ } ++ ++ drm_dev = drm_dev_alloc(&vs_drm_driver, dev); ++ if (IS_ERR(drm_dev)) ++ return PTR_ERR(drm_dev); ++ ++ dev_set_drvdata(dev, drm_dev); ++ ++ priv = devm_kzalloc(drm_dev->dev, sizeof(struct vs_drm_private), ++ GFP_KERNEL); ++ if (!priv) { ++ ret = -ENOMEM; ++ goto err_put_dev; ++ } ++ ++ priv->pitch_alignment = 64; ++ priv->dma_dev = drm_dev->dev; ++ priv->dma_dev->coherent_dma_mask = dma_mask; ++ drm_dev->dev_private = priv; ++ ++ drm_mode_config_init(drm_dev); ++ ++ /* Now try and bind all our sub-components */ ++ ret = component_bind_all(dev, drm_dev); ++ if (ret) ++ goto err_mode; ++ ++ ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc); ++ if (ret) ++ goto err_bind; ++ ++ drm_mode_config_reset(drm_dev); ++ ++ drm_kms_helper_poll_init(drm_dev); ++ ++ ret = drm_dev_register(drm_dev, 0); ++ if (ret) ++ goto err_helper; ++ ++ drm_fbdev_generic_setup(drm_dev, 32); ++ ++ return 0; ++ ++err_helper: ++ drm_kms_helper_poll_fini(drm_dev); ++err_bind: ++ component_unbind_all(drm_dev->dev, drm_dev); ++err_mode: ++ drm_mode_config_cleanup(drm_dev); ++ if (priv->domain) ++ iommu_domain_free(priv->domain); ++err_put_dev: ++ drm_dev->dev_private = NULL; ++ dev_set_drvdata(dev, NULL); ++ drm_dev_put(drm_dev); ++ return ret; ++} ++ ++static void vs_drm_unbind(struct device *dev) ++{ ++ struct drm_device *drm_dev = dev_get_drvdata(dev); ++ struct vs_drm_private *priv = drm_dev->dev_private; ++ ++ drm_dev_unregister(drm_dev); ++ ++ drm_kms_helper_poll_fini(drm_dev); ++ ++ component_unbind_all(drm_dev->dev, drm_dev); ++ ++ drm_mode_config_cleanup(drm_dev); ++ ++ if (priv->domain) { ++ iommu_domain_free(priv->domain); ++ priv->domain = NULL; ++ } ++ ++ drm_dev->dev_private = NULL; ++ dev_set_drvdata(dev, NULL); ++ drm_dev_put(drm_dev); ++} ++ ++static const struct component_master_ops vs_drm_ops = { ++ .bind = vs_drm_bind, ++ .unbind = vs_drm_unbind, ++}; ++ ++static struct platform_driver *drm_sub_drivers[] = { ++}; ++ ++#define NUM_DRM_DRIVERS \ ++ (sizeof(drm_sub_drivers) / sizeof(struct platform_driver *)) ++ ++static int compare_dev(struct device *dev, void *data) ++{ ++ return dev == (struct device *)data; ++} ++ ++static struct component_match *vs_drm_match_add(struct device *dev) ++{ ++ struct component_match *match = NULL; ++ int i; ++ ++ for (i = 0; i < NUM_DRM_DRIVERS; ++i) { ++ struct platform_driver *drv = drm_sub_drivers[i]; ++ struct device *p = NULL, *d; ++ ++ while ((d = platform_find_device_by_driver(p, &drv->driver))) { ++ put_device(p); ++ ++ component_match_add(dev, &match, compare_dev, d); ++ p = d; ++ } ++ put_device(p); ++ } ++ ++ return match ?: ERR_PTR(-ENODEV); ++} ++ ++static int vs_drm_platform_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct component_match *match; ++ ++ match = vs_drm_match_add(dev); ++ if (IS_ERR(match)) ++ return PTR_ERR(match); ++ ++ return component_master_add_with_match(dev, &vs_drm_ops, match); ++} ++ ++static int vs_drm_platform_remove(struct platform_device *pdev) ++{ ++ component_master_del(&pdev->dev, &vs_drm_ops); ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int vs_drm_suspend(struct device *dev) ++{ ++ struct drm_device *drm = dev_get_drvdata(dev); ++ ++ return drm_mode_config_helper_suspend(drm); ++} ++ ++static int vs_drm_resume(struct device *dev) ++{ ++ struct drm_device *drm = dev_get_drvdata(dev); ++ ++ return drm_mode_config_helper_resume(drm); ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(vs_drm_pm_ops, vs_drm_suspend, vs_drm_resume); ++ ++static const struct of_device_id vs_drm_dt_ids[] = { ++ { .compatible = "verisilicon,display-subsystem", }, ++}; ++ ++MODULE_DEVICE_TABLE(of, vs_drm_dt_ids); ++ ++static struct platform_driver vs_drm_platform_driver = { ++ .probe = vs_drm_platform_probe, ++ .remove = vs_drm_platform_remove, ++ ++ .driver = { ++ .name = DRV_NAME, ++ .of_match_table = vs_drm_dt_ids, ++ .pm = &vs_drm_pm_ops, ++ }, ++}; ++ ++static int __init vs_drm_init(void) ++{ ++ int ret; ++ ++ ret = platform_register_drivers(drm_sub_drivers, NUM_DRM_DRIVERS); ++ if (ret) ++ return ret; ++ ++ ret = platform_driver_register(&vs_drm_platform_driver); ++ if (ret) ++ platform_unregister_drivers(drm_sub_drivers, NUM_DRM_DRIVERS); ++ ++ return ret; ++} ++ ++static void __exit vs_drm_fini(void) ++{ ++ platform_driver_unregister(&vs_drm_platform_driver); ++ platform_unregister_drivers(drm_sub_drivers, NUM_DRM_DRIVERS); ++} ++ ++module_init(vs_drm_init); ++module_exit(vs_drm_fini); ++ ++MODULE_DESCRIPTION("VeriSilicon DRM Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.h b/drivers/gpu/drm/verisilicon/vs_drv.h +new file mode 100644 +index 000000000000..0382b44e3bf0 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_drv.h +@@ -0,0 +1,48 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_DRV_H__ ++#define __VS_DRV_H__ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* ++ * ++ * @dma_dev: device for DMA API. ++ * - use the first attached device if support iommu ++ else use drm device (only contiguous buffer support) ++ * @domain: iommu domain for DRM. ++ * - all DC IOMMU share same domain to reduce mapping ++ * @pitch_alignment: buffer pitch alignment required by sub-devices. ++ * ++ */ ++struct vs_drm_private { ++ struct device *dma_dev; ++ struct iommu_domain *domain; ++ unsigned int pitch_alignment; ++}; ++ ++void vs_drm_update_pitch_alignment(struct drm_device *drm_dev, ++ unsigned int alignment); ++ ++static inline struct device *to_dma_dev(struct drm_device *dev) ++{ ++ struct vs_drm_private *priv = dev->dev_private; ++ ++ return priv->dma_dev; ++} ++ ++static inline bool is_iommu_enabled(struct drm_device *dev) ++{ ++ struct vs_drm_private *priv = dev->dev_private; ++ ++ return priv->domain ? true : false; ++} ++ ++#endif /* __VS_DRV_H__ */ +diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h +index de703c6be969..af4fb50f9207 100644 +--- a/include/uapi/drm/drm_fourcc.h ++++ b/include/uapi/drm/drm_fourcc.h +@@ -419,6 +419,7 @@ extern "C" { + #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 + #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 + #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a ++#define DRM_FORMAT_MOD_VENDOR_VS 0x0b + + /* add more to the end as needed */ + +@@ -1519,6 +1520,88 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) + #define AMD_FMT_MOD_CLEAR(field) \ + (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) + ++#define DRM_FORMAT_MOD_VS_TYPE_NORMAL 0x00 ++#define DRM_FORMAT_MOD_VS_TYPE_COMPRESSED 0x01 ++#define DRM_FORMAT_MOD_VS_TYPE_CUSTOM_10BIT 0x02 ++#define DRM_FORMAT_MOD_VS_TYPE_MASK ((__u64)0x3 << 54) ++ ++#define fourcc_mod_vs_code(type, val) \ ++ fourcc_mod_code(VS, ((((__u64)type) << 54) | (val))) ++ ++#define DRM_FORMAT_MOD_VS_DEC_TILE_MODE_MASK 0x3F ++#define DRM_FORMAT_MOD_VS_DEC_TILE_8X8_XMAJOR 0x00 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_8X8_YMAJOR 0x01 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_16X4 0x02 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_8X4 0x03 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_4X8 0x04 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_16X4 0x06 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_64X4 0x07 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_32X4 0x08 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_256X1 0x09 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_128X1 0x0A ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_64X4 0x0B ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_256X2 0x0C ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_128X2 0x0D ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_128X4 0x0E ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_64X1 0x0F ++#define DRM_FORMAT_MOD_VS_DEC_TILE_16X8 0x10 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_8X16 0x11 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_512X1 0x12 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_32X4 0x13 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_64X2 0x14 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_32X2 0x15 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_32X1 0x16 ++#define DRM_FORMAT_MOD_VS_DEC_RASTER_16X1 0x17 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_128X4 0x18 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_256X4 0x19 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_512X4 0x1A ++#define DRM_FORMAT_MOD_VS_DEC_TILE_16X16 0x1B ++#define DRM_FORMAT_MOD_VS_DEC_TILE_32X16 0x1C ++#define DRM_FORMAT_MOD_VS_DEC_TILE_64X16 0x1D ++#define DRM_FORMAT_MOD_VS_DEC_TILE_128X8 0x1E ++#define DRM_FORMAT_MOD_VS_DEC_TILE_8X4_S 0x1F ++#define DRM_FORMAT_MOD_VS_DEC_TILE_16X4_S 0x20 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_32X4_S 0x21 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_16X4_LSB 0x22 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_32X4_LSB 0x23 ++#define DRM_FORMAT_MOD_VS_DEC_TILE_32X8 0x24 ++ ++#define DRM_FORMAT_MOD_VS_DEC_ALIGN_32 (0x01 << 6) ++#define DRM_FORMAT_MOD_VS_DEC_ALIGN_64 (0x01 << 7) ++ ++#define fourcc_mod_vs_dec_code(tile, align) \ ++ fourcc_mod_vs_code(DRM_FORMAT_MOD_VS_TYPE_COMPRESSED, \ ++ ((tile) | (align))) ++ ++#define DRM_FORMAT_MOD_VS_NORM_MODE_MASK 0x1F ++#define DRM_FORMAT_MOD_VS_LINEAR 0x00 ++#define DRM_FORMAT_MOD_VS_TILED4x4 0x01 ++#define DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR 0x02 ++#define DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR 0x03 ++#define DRM_FORMAT_MOD_VS_TILE_8X8 0x04 ++#define DRM_FORMAT_MOD_VS_TILE_MODE1 0x05 ++#define DRM_FORMAT_MOD_VS_TILE_MODE2 0x06 ++#define DRM_FORMAT_MOD_VS_TILE_8X4 0x07 ++#define DRM_FORMAT_MOD_VS_TILE_MODE4 0x08 ++#define DRM_FORMAT_MOD_VS_TILE_MODE5 0x09 ++#define DRM_FORMAT_MOD_VS_TILE_MODE6 0x0A ++#define DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR_8X4 0x0B ++#define DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR_4X8 0x0C ++#define DRM_FORMAT_MOD_VS_TILE_Y 0x0D ++#define DRM_FORMAT_MOD_VS_TILE_128X1 0x0F ++#define DRM_FORMAT_MOD_VS_TILE_256X1 0x10 ++#define DRM_FORMAT_MOD_VS_TILE_32X1 0x11 ++#define DRM_FORMAT_MOD_VS_TILE_64X1 0x12 ++#define DRM_FORMAT_MOD_VS_TILE_MODE4X4 0x15 ++ ++#define fourcc_mod_vs_norm_code(tile) \ ++ fourcc_mod_vs_code(DRM_FORMAT_MOD_VS_TYPE_NORMAL, \ ++ (tile)) ++ ++#define fourcc_mod_vs_custom_code(tile) \ ++ fourcc_mod_vs_code(DRM_FORMAT_MOD_VS_TYPE_CUSTOM_10BIT, \ ++ (tile)) ++ + #if defined(__cplusplus) + } + #endif +diff --git a/include/uapi/drm/vs_drm.h b/include/uapi/drm/vs_drm.h +new file mode 100644 +index 000000000000..96b7fc95d658 +--- /dev/null ++++ b/include/uapi/drm/vs_drm.h +@@ -0,0 +1,50 @@ ++/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ ++/* ++ * Copyright (C) 2020 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_DRM_H__ ++#define __VS_DRM_H__ ++ ++#include "drm.h" ++ ++enum drm_vs_degamma_mode { ++ VS_DEGAMMA_DISABLE = 0, ++ VS_DEGAMMA_BT709 = 1, ++ VS_DEGAMMA_BT2020 = 2, ++}; ++ ++enum drm_vs_sync_dc_mode { ++ VS_SINGLE_DC = 0, ++ VS_MULTI_DC_PRIMARY = 1, ++ VS_MULTI_DC_SECONDARY = 2, ++}; ++ ++enum drm_vs_mmu_prefetch_mode { ++ VS_MMU_PREFETCH_DISABLE = 0, ++ VS_MMU_PREFETCH_ENABLE = 1, ++}; ++ ++struct drm_vs_watermark { ++ __u32 watermark; ++ __u8 qos_low; ++ __u8 qos_high; ++}; ++ ++struct drm_vs_color_mgmt { ++ __u32 colorkey; ++ __u32 colorkey_high; ++ __u32 clear_value; ++ bool clear_enable; ++ bool transparency; ++}; ++ ++struct drm_vs_roi { ++ bool enable; ++ __u16 roi_x; ++ __u16 roi_y; ++ __u16 roi_w; ++ __u16 roi_h; ++}; ++ ++#endif /* __VS_DRM_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0052-drm-verisilicon-Add-gem-driver-for-JH7110-SoC.patch b/srcpkgs/linux6.4/patches/0052-drm-verisilicon-Add-gem-driver-for-JH7110-SoC.patch new file mode 100644 index 0000000000000..b6fc7794ee6b9 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0052-drm-verisilicon-Add-gem-driver-for-JH7110-SoC.patch @@ -0,0 +1,520 @@ +From 447dad4b026d2ee4c943b39021ffa5290c44a623 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:38 +0800 +Subject: [PATCH 52/72] drm/verisilicon: Add gem driver for JH7110 SoC + +This patch implements gem related APIs for JH7100 SoC. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Makefile | 3 +- + drivers/gpu/drm/verisilicon/vs_drv.c | 6 + + drivers/gpu/drm/verisilicon/vs_gem.c | 372 +++++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_gem.h | 72 ++++++ + 4 files changed, 452 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_gem.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_gem.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index 64ce1b26546c..30360e370e47 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + +-vs_drm-objs := vs_drv.o ++vs_drm-objs := vs_drv.o \ ++ vs_gem.o + + obj-$(CONFIG_DRM_VERISILICON) += vs_drm.o + +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index 24d333598477..e0a2fc43b55f 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -30,6 +30,7 @@ + #include + + #include "vs_drv.h" ++#include "vs_gem.h" + + #define DRV_NAME "starfive" + #define DRV_DESC "Starfive DRM driver" +@@ -47,6 +48,7 @@ static const struct file_operations fops = { + .compat_ioctl = drm_compat_ioctl, + .poll = drm_poll, + .read = drm_read, ++ .mmap = vs_gem_mmap, + }; + + static struct drm_driver vs_drm_driver = { +@@ -54,6 +56,10 @@ static struct drm_driver vs_drm_driver = { + .lastclose = drm_fb_helper_lastclose, + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, ++ .gem_prime_import = vs_gem_prime_import, ++ .gem_prime_import_sg_table = vs_gem_prime_import_sg_table, ++ .gem_prime_mmap = vs_gem_prime_mmap, ++ .dumb_create = vs_gem_dumb_create, + .fops = &fops, + .name = DRV_NAME, + .desc = DRV_DESC, +diff --git a/drivers/gpu/drm/verisilicon/vs_gem.c b/drivers/gpu/drm/verisilicon/vs_gem.c +new file mode 100644 +index 000000000000..3f963471c1ab +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_gem.c +@@ -0,0 +1,372 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++ ++#include "vs_drv.h" ++#include "vs_gem.h" ++ ++static const struct drm_gem_object_funcs vs_gem_default_funcs; ++ ++static int vs_gem_alloc_buf(struct vs_gem_object *vs_obj) ++{ ++ struct drm_device *dev = vs_obj->base.dev; ++ unsigned int nr_pages; ++ struct sg_table sgt; ++ int ret = -ENOMEM; ++ ++ if (vs_obj->dma_addr) { ++ DRM_DEV_DEBUG_KMS(dev->dev, "already allocated.\n"); ++ return 0; ++ } ++ ++ vs_obj->dma_attrs = DMA_ATTR_WRITE_COMBINE | DMA_ATTR_FORCE_CONTIGUOUS ++ | DMA_ATTR_NO_KERNEL_MAPPING; ++ ++ nr_pages = vs_obj->size >> PAGE_SHIFT; ++ ++ vs_obj->pages = kvmalloc_array(nr_pages, sizeof(struct page *), ++ GFP_KERNEL | __GFP_ZERO); ++ if (!vs_obj->pages) { ++ DRM_DEV_ERROR(dev->dev, "failed to allocate pages.\n"); ++ return -ENOMEM; ++ } ++ ++ vs_obj->cookie = dma_alloc_attrs(to_dma_dev(dev), vs_obj->size, ++ &vs_obj->dma_addr, GFP_KERNEL, ++ vs_obj->dma_attrs); ++ ++ if (!vs_obj->cookie) { ++ DRM_DEV_ERROR(dev->dev, "failed to allocate buffer.\n"); ++ goto err_free; ++ } ++ ++ vs_obj->iova = vs_obj->dma_addr; ++ ++ ret = dma_get_sgtable_attrs(to_dma_dev(dev), &sgt, ++ vs_obj->cookie, vs_obj->dma_addr, ++ vs_obj->size, vs_obj->dma_attrs); ++ if (ret < 0) { ++ DRM_DEV_ERROR(dev->dev, "failed to get sgtable.\n"); ++ goto err_mem_free; ++ } ++ ++ if (drm_prime_sg_to_page_array(&sgt, vs_obj->pages, nr_pages)) { ++ DRM_DEV_ERROR(dev->dev, "invalid sgtable.\n"); ++ ret = -EINVAL; ++ goto err_sgt_free; ++ } ++ ++ sg_free_table(&sgt); ++ ++ return 0; ++ ++err_sgt_free: ++ sg_free_table(&sgt); ++err_mem_free: ++ dma_free_attrs(to_dma_dev(dev), vs_obj->size, vs_obj->cookie, ++ vs_obj->dma_addr, vs_obj->dma_attrs); ++err_free: ++ kvfree(vs_obj->pages); ++ ++ return ret; ++} ++ ++static void vs_gem_free_buf(struct vs_gem_object *vs_obj) ++{ ++ struct drm_device *dev = vs_obj->base.dev; ++ ++ if (!vs_obj->dma_addr) { ++ DRM_DEV_DEBUG_KMS(dev->dev, "dma_addr is invalid.\n"); ++ return; ++ } ++ ++ dma_free_attrs(to_dma_dev(dev), vs_obj->size, vs_obj->cookie, ++ (dma_addr_t)vs_obj->dma_addr, ++ vs_obj->dma_attrs); ++ ++ kvfree(vs_obj->pages); ++} ++ ++static void vs_gem_free_object(struct drm_gem_object *obj) ++{ ++ struct vs_gem_object *vs_obj = to_vs_gem_object(obj); ++ ++ if (obj->import_attach) ++ drm_prime_gem_destroy(obj, vs_obj->sgt); ++ else ++ vs_gem_free_buf(vs_obj); ++ ++ drm_gem_object_release(obj); ++ ++ kfree(vs_obj); ++} ++ ++static struct vs_gem_object *vs_gem_alloc_object(struct drm_device *dev, ++ size_t size) ++{ ++ struct vs_gem_object *vs_obj; ++ struct drm_gem_object *obj; ++ int ret; ++ ++ vs_obj = kzalloc(sizeof(*vs_obj), GFP_KERNEL); ++ if (!vs_obj) ++ return ERR_PTR(-ENOMEM); ++ ++ vs_obj->size = size; ++ obj = &vs_obj->base; ++ ++ ret = drm_gem_object_init(dev, obj, size); ++ if (ret) ++ goto err_free; ++ ++ vs_obj->base.funcs = &vs_gem_default_funcs; ++ ++ ret = drm_gem_create_mmap_offset(obj); ++ if (ret) { ++ drm_gem_object_release(obj); ++ goto err_free; ++ } ++ ++ return vs_obj; ++ ++err_free: ++ kfree(vs_obj); ++ return ERR_PTR(ret); ++} ++ ++struct vs_gem_object *vs_gem_create_object(struct drm_device *dev, ++ size_t size) ++{ ++ struct vs_gem_object *vs_obj; ++ int ret; ++ ++ size = PAGE_ALIGN(size); ++ ++ vs_obj = vs_gem_alloc_object(dev, size); ++ if (IS_ERR(vs_obj)) ++ return vs_obj; ++ ++ ret = vs_gem_alloc_buf(vs_obj); ++ if (ret) { ++ drm_gem_object_release(&vs_obj->base); ++ kfree(vs_obj); ++ return ERR_PTR(ret); ++ } ++ ++ return vs_obj; ++} ++ ++static struct vs_gem_object *vs_gem_create_with_handle(struct drm_device *dev, ++ struct drm_file *file, ++ size_t size, ++ unsigned int *handle) ++{ ++ struct vs_gem_object *vs_obj; ++ struct drm_gem_object *obj; ++ int ret; ++ ++ vs_obj = vs_gem_create_object(dev, size); ++ if (IS_ERR(vs_obj)) ++ return vs_obj; ++ ++ obj = &vs_obj->base; ++ ++ ret = drm_gem_handle_create(file, obj, handle); ++ ++ drm_gem_object_put(obj); ++ ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return vs_obj; ++} ++ ++static int vs_gem_mmap_obj(struct drm_gem_object *obj, ++ struct vm_area_struct *vma) ++{ ++ struct vs_gem_object *vs_obj = to_vs_gem_object(obj); ++ struct drm_device *drm_dev = vs_obj->base.dev; ++ unsigned long vm_size; ++ int ret = 0; ++ ++ vm_size = vma->vm_end - vma->vm_start; ++ if (vm_size > vs_obj->size) ++ return -EINVAL; ++ ++ vma->vm_pgoff = 0; ++ ++ /* ++ * We allocated a struct page table for starfive_obj, so clear ++ * VM_PFNMAP flag that was set by drm_gem_mmap_obj()/drm_gem_mmap(). ++ */ ++ vm_flags_mod(vma, VM_IO | VM_DONTEXPAND | VM_DONTDUMP, VM_PFNMAP); ++ ++ vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); ++ vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); ++ ++ ret = dma_mmap_attrs(to_dma_dev(drm_dev), vma, vs_obj->cookie, ++ vs_obj->dma_addr, vs_obj->size, ++ vs_obj->dma_attrs); ++ ++ if (ret) ++ drm_gem_vm_close(vma); ++ ++ return ret; ++} ++ ++struct sg_table *vs_gem_prime_get_sg_table(struct drm_gem_object *obj) ++{ ++ struct vs_gem_object *vs_obj = to_vs_gem_object(obj); ++ ++ return drm_prime_pages_to_sg(obj->dev, vs_obj->pages, ++ vs_obj->size >> PAGE_SHIFT); ++} ++ ++int vs_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map) ++{ ++ struct vs_gem_object *vs_obj = to_vs_gem_object(obj); ++ ++ void *vaddr = vs_obj->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING ? ++ page_address(vs_obj->cookie) : vs_obj->cookie; ++ ++ iosys_map_set_vaddr(map, vaddr); ++ ++ return 0; ++} ++ ++void vs_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map) ++{ ++ /* Nothing to do */ ++} ++ ++static const struct vm_operations_struct vs_vm_ops = { ++ .open = drm_gem_vm_open, ++ .close = drm_gem_vm_close, ++}; ++ ++static const struct drm_gem_object_funcs vs_gem_default_funcs = { ++ .free = vs_gem_free_object, ++ .get_sg_table = vs_gem_prime_get_sg_table, ++ .vmap = vs_gem_prime_vmap, ++ .vunmap = vs_gem_prime_vunmap, ++ .vm_ops = &vs_vm_ops, ++}; ++ ++int vs_gem_dumb_create(struct drm_file *file, ++ struct drm_device *dev, ++ struct drm_mode_create_dumb *args) ++{ ++ struct vs_drm_private *priv = dev->dev_private; ++ struct vs_gem_object *vs_obj; ++ unsigned int pitch = DIV_ROUND_UP(args->width * args->bpp, 8); ++ ++ if (args->bpp % 10) ++ args->pitch = ALIGN(pitch, priv->pitch_alignment); ++ else ++ /* for costum 10bit format with no bit gaps */ ++ args->pitch = pitch; ++ args->size = PAGE_ALIGN(args->pitch * args->height); ++ vs_obj = vs_gem_create_with_handle(dev, file, args->size, ++ &args->handle); ++ return PTR_ERR_OR_ZERO(vs_obj); ++} ++ ++struct drm_gem_object *vs_gem_prime_import(struct drm_device *dev, ++ struct dma_buf *dma_buf) ++{ ++ return drm_gem_prime_import_dev(dev, dma_buf, to_dma_dev(dev)); ++} ++ ++struct drm_gem_object * ++vs_gem_prime_import_sg_table(struct drm_device *dev, ++ struct dma_buf_attachment *attach, ++ struct sg_table *sgt) ++{ ++ struct vs_gem_object *vs_obj; ++ int npages; ++ int ret; ++ struct scatterlist *s; ++ u32 i; ++ dma_addr_t expected; ++ size_t size = attach->dmabuf->size; ++ ++ size = PAGE_ALIGN(size); ++ ++ vs_obj = vs_gem_alloc_object(dev, size); ++ if (IS_ERR(vs_obj)) ++ return ERR_CAST(vs_obj); ++ ++ expected = sg_dma_address(sgt->sgl); ++ for_each_sg(sgt->sgl, s, sgt->nents, i) { ++ if (sg_dma_address(s) != expected) { ++ DRM_ERROR("sg_table is not contiguous"); ++ ret = -EINVAL; ++ goto err; ++ } ++ if (sg_dma_len(s) & (PAGE_SIZE - 1)) { ++ ret = -EINVAL; ++ goto err; ++ } ++ if (i == 0) ++ vs_obj->iova = sg_dma_address(s); ++ expected = sg_dma_address(s) + sg_dma_len(s); ++ } ++ ++ vs_obj->dma_addr = sg_dma_address(sgt->sgl); ++ ++ npages = vs_obj->size >> PAGE_SHIFT; ++ vs_obj->pages = kvmalloc_array(npages, sizeof(struct page *), ++ GFP_KERNEL); ++ if (!vs_obj->pages) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ ret = drm_prime_sg_to_page_array(sgt, vs_obj->pages, npages); ++ if (ret) ++ goto err_free_page; ++ ++ vs_obj->sgt = sgt; ++ ++ return &vs_obj->base; ++ ++err_free_page: ++ kvfree(vs_obj->pages); ++err: ++ vs_gem_free_object(&vs_obj->base); ++ ++ return ERR_PTR(ret); ++} ++ ++int vs_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) ++{ ++ int ret = 0; ++ ++ ret = drm_gem_mmap_obj(obj, obj->size, vma); ++ if (ret < 0) ++ return ret; ++ ++ return vs_gem_mmap_obj(obj, vma); ++} ++ ++int vs_gem_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ struct drm_gem_object *obj; ++ int ret; ++ ++ ret = drm_gem_mmap(filp, vma); ++ if (ret) ++ return ret; ++ ++ obj = vma->vm_private_data; ++ ++ if (obj->import_attach) ++ return dma_buf_mmap(obj->dma_buf, vma, 0); ++ ++ return vs_gem_mmap_obj(obj, vma); ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_gem.h b/drivers/gpu/drm/verisilicon/vs_gem.h +new file mode 100644 +index 000000000000..3a6d7452cb06 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_gem.h +@@ -0,0 +1,72 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_GEM_H__ ++#define __VS_GEM_H__ ++ ++#include ++ ++#include ++#include ++ ++#include "vs_drv.h" ++/* ++ * ++ * @base: drm gem object. ++ * @size: size requested from user ++ * @cookie: cookie returned by dma_alloc_attrs ++ * - not kernel virtual address with DMA_ATTR_NO_KERNEL_MAPPING ++ * @dma_addr: bus address(accessed by dma) to allocated memory region. ++ * - this address could be physical address without IOMMU and ++ * device address with IOMMU. ++ * @dma_attrs: attribute for DMA API ++ * @get_pages: flag for manually applying for non-contiguous memory. ++ * @pages: Array of backing pages. ++ * @sgt: Imported sg_table. ++ * ++ */ ++struct vs_gem_object { ++ struct drm_gem_object base; ++ size_t size; ++ void *cookie; ++ dma_addr_t dma_addr; ++ u32 iova; ++ unsigned long dma_attrs; ++ bool get_pages; ++ struct page **pages; ++ struct sg_table *sgt; ++}; ++ ++static inline ++struct vs_gem_object *to_vs_gem_object(struct drm_gem_object *obj) ++{ ++ return container_of(obj, struct vs_gem_object, base); ++} ++ ++struct vs_gem_object *vs_gem_create_object(struct drm_device *dev, ++ size_t size); ++ ++int vs_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); ++void vs_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); ++ ++int vs_gem_prime_mmap(struct drm_gem_object *obj, ++ struct vm_area_struct *vma); ++ ++int vs_gem_dumb_create(struct drm_file *file_priv, ++ struct drm_device *drm, ++ struct drm_mode_create_dumb *args); ++ ++int vs_gem_mmap(struct file *filp, struct vm_area_struct *vma); ++ ++struct sg_table *vs_gem_prime_get_sg_table(struct drm_gem_object *obj); ++ ++struct drm_gem_object *vs_gem_prime_import(struct drm_device *dev, ++ struct dma_buf *dma_buf); ++struct drm_gem_object * ++vs_gem_prime_import_sg_table(struct drm_device *dev, ++ struct dma_buf_attachment *attach, ++ struct sg_table *sgt); ++ ++#endif /* __VS_GEM_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0053-drm-verisilicon-Add-mode-config-funcs.patch b/srcpkgs/linux6.4/patches/0053-drm-verisilicon-Add-mode-config-funcs.patch new file mode 100644 index 0000000000000..c9f336ddb38ae --- /dev/null +++ b/srcpkgs/linux6.4/patches/0053-drm-verisilicon-Add-mode-config-funcs.patch @@ -0,0 +1,261 @@ +From 14dad8f744599d67842860fb914e8662ba7dd669 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:39 +0800 +Subject: [PATCH 53/72] drm/verisilicon: Add mode config funcs + +Add mode setting functions for JH7110 SoC. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Makefile | 1 + + drivers/gpu/drm/verisilicon/vs_drv.c | 3 + + drivers/gpu/drm/verisilicon/vs_fb.c | 181 +++++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_fb.h | 15 +++ + 4 files changed, 200 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/vs_fb.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_fb.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index 30360e370e47..38254dc5d98d 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + + vs_drm-objs := vs_drv.o \ ++ vs_fb.o \ + vs_gem.o + + obj-$(CONFIG_DRM_VERISILICON) += vs_drm.o +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index e0a2fc43b55f..d84aacd751bc 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -30,6 +30,7 @@ + #include + + #include "vs_drv.h" ++#include "vs_fb.h" + #include "vs_gem.h" + + #define DRV_NAME "starfive" +@@ -118,6 +119,8 @@ static int vs_drm_bind(struct device *dev) + if (ret) + goto err_mode; + ++ vs_mode_config_init(drm_dev); ++ + ret = drm_vblank_init(drm_dev, drm_dev->mode_config.num_crtc); + if (ret) + goto err_bind; +diff --git a/drivers/gpu/drm/verisilicon/vs_fb.c b/drivers/gpu/drm/verisilicon/vs_fb.c +new file mode 100644 +index 000000000000..3e85f7365084 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_fb.c +@@ -0,0 +1,181 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_fb.h" ++#include "vs_gem.h" ++ ++#define fourcc_mod_vs_get_type(val) \ ++ (((val) & DRM_FORMAT_MOD_VS_TYPE_MASK) >> 54) ++ ++static struct drm_framebuffer_funcs vs_fb_funcs = { ++ .create_handle = drm_gem_fb_create_handle, ++ .destroy = drm_gem_fb_destroy, ++ .dirty = drm_atomic_helper_dirtyfb, ++}; ++ ++static struct drm_framebuffer * ++vs_fb_alloc(struct drm_device *dev, const struct drm_mode_fb_cmd2 *mode_cmd, ++ struct vs_gem_object **obj, unsigned int num_planes) ++{ ++ struct drm_framebuffer *fb; ++ int ret, i; ++ ++ fb = kzalloc(sizeof(*fb), GFP_KERNEL); ++ if (!fb) ++ return ERR_PTR(-ENOMEM); ++ ++ drm_helper_mode_fill_fb_struct(dev, fb, mode_cmd); ++ ++ for (i = 0; i < num_planes; i++) ++ fb->obj[i] = &obj[i]->base; ++ ++ ret = drm_framebuffer_init(dev, fb, &vs_fb_funcs); ++ if (ret) { ++ dev_err(dev->dev, "Failed to initialize framebuffer: %d\n", ++ ret); ++ kfree(fb); ++ return ERR_PTR(ret); ++ } ++ ++ return fb; ++} ++ ++static struct drm_framebuffer *vs_fb_create(struct drm_device *dev, ++ struct drm_file *file_priv, ++ const struct drm_mode_fb_cmd2 *mode_cmd) ++{ ++ struct drm_framebuffer *fb; ++ const struct drm_format_info *info; ++ struct vs_gem_object *objs[MAX_NUM_PLANES]; ++ struct drm_gem_object *obj; ++ unsigned int height, size; ++ unsigned char i, num_planes; ++ int ret = 0; ++ ++ info = drm_get_format_info(dev, mode_cmd); ++ if (!info) ++ return ERR_PTR(-EINVAL); ++ ++ num_planes = info->num_planes; ++ if (num_planes > MAX_NUM_PLANES) ++ return ERR_PTR(-EINVAL); ++ ++ for (i = 0; i < num_planes; i++) { ++ obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[i]); ++ if (!obj) { ++ dev_err(dev->dev, "Failed to lookup GEM object.\n"); ++ ret = -ENXIO; ++ goto err; ++ } ++ ++ height = drm_format_info_plane_height(info, ++ mode_cmd->height, i); ++ ++ size = height * mode_cmd->pitches[i] + mode_cmd->offsets[i]; ++ ++ if (obj->size < size) { ++ drm_gem_object_put(obj); ++ ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ objs[i] = to_vs_gem_object(obj); ++ } ++ ++ fb = vs_fb_alloc(dev, mode_cmd, objs, i); ++ if (IS_ERR(fb)) { ++ ret = PTR_ERR(fb); ++ goto err; ++ } ++ ++ return fb; ++ ++err: ++ for (; i > 0; i--) ++ drm_gem_object_put(&objs[i - 1]->base); ++ ++ return ERR_PTR(ret); ++} ++ ++struct vs_gem_object *vs_fb_get_gem_obj(struct drm_framebuffer *fb, ++ unsigned char plane) ++{ ++ if (plane > MAX_NUM_PLANES) ++ return NULL; ++ ++ return to_vs_gem_object(fb->obj[plane]); ++} ++ ++static const struct drm_format_info vs_formats[] = { ++ {.format = DRM_FORMAT_NV12, .depth = 0, .num_planes = 2, .char_per_block = { 20, 40, 0 }, ++ .block_w = { 4, 4, 0 }, .block_h = { 4, 4, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true}, ++ {.format = DRM_FORMAT_YUV444, .depth = 0, .num_planes = 3, .char_per_block = { 20, 20, 20 }, ++ .block_w = { 4, 4, 4 }, .block_h = { 4, 4, 4 }, .hsub = 1, .vsub = 1, .is_yuv = true}, ++}; ++ ++static const struct drm_format_info * ++vs_lookup_format_info(const struct drm_format_info formats[], ++ int num_formats, u32 format) ++{ ++ int i; ++ ++ for (i = 0; i < num_formats; i++) { ++ if (formats[i].format == format) ++ return &formats[i]; ++ } ++ ++ return NULL; ++} ++ ++static const struct drm_format_info * ++vs_get_format_info(const struct drm_mode_fb_cmd2 *cmd) ++{ ++ if (fourcc_mod_vs_get_type(cmd->modifier[0]) == ++ DRM_FORMAT_MOD_VS_TYPE_CUSTOM_10BIT) ++ return vs_lookup_format_info(vs_formats, ARRAY_SIZE(vs_formats), ++ cmd->pixel_format); ++ else ++ return NULL; ++} ++ ++static const struct drm_mode_config_funcs vs_mode_config_funcs = { ++ .fb_create = vs_fb_create, ++ .get_format_info = vs_get_format_info, ++ .output_poll_changed = drm_fb_helper_output_poll_changed, ++ .atomic_check = drm_atomic_helper_check, ++ .atomic_commit = drm_atomic_helper_commit, ++}; ++ ++static struct drm_mode_config_helper_funcs vs_mode_config_helpers = { ++ .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, ++}; ++ ++void vs_mode_config_init(struct drm_device *dev) ++{ ++ dev->mode_config.fb_modifiers_not_supported = false; ++ ++ if (dev->mode_config.max_width == 0 || ++ dev->mode_config.max_height == 0) { ++ dev->mode_config.min_width = 0; ++ dev->mode_config.min_height = 0; ++ dev->mode_config.max_width = 4096; ++ dev->mode_config.max_height = 4096; ++ } ++ dev->mode_config.funcs = &vs_mode_config_funcs; ++ dev->mode_config.helper_private = &vs_mode_config_helpers; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_fb.h b/drivers/gpu/drm/verisilicon/vs_fb.h +new file mode 100644 +index 000000000000..78dda8e42894 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_fb.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_FB_H__ ++#define __VS_FB_H__ ++ ++#define MAX_NUM_PLANES 3 /* colour format plane */ ++ ++struct vs_gem_object *vs_fb_get_gem_obj(struct drm_framebuffer *fb, ++ unsigned char plane); ++ ++void vs_mode_config_init(struct drm_device *dev); ++#endif /* __VS_FB_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0054-drm-verisilicon-Add-drm-crtc-funcs.patch b/srcpkgs/linux6.4/patches/0054-drm-verisilicon-Add-drm-crtc-funcs.patch new file mode 100644 index 0000000000000..a25696886e09e --- /dev/null +++ b/srcpkgs/linux6.4/patches/0054-drm-verisilicon-Add-drm-crtc-funcs.patch @@ -0,0 +1,585 @@ +From f591814ee2a85a371eadf9c5ce16f54eeaddc403 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:40 +0800 +Subject: [PATCH 54/72] drm/verisilicon: Add drm crtc funcs + +Add crtc driver which implements crtc related operation functions. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Makefile | 1 + + drivers/gpu/drm/verisilicon/vs_crtc.c | 388 ++++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_crtc.h | 74 +++++ + drivers/gpu/drm/verisilicon/vs_type.h | 72 +++++ + 4 files changed, 535 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index 38254dc5d98d..bae5fbab9bbb 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0 + + vs_drm-objs := vs_drv.o \ ++ vs_crtc.o \ + vs_fb.o \ + vs_gem.o + +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.c b/drivers/gpu/drm/verisilicon/vs_crtc.c +new file mode 100644 +index 000000000000..a9e742d7bd1a +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.c +@@ -0,0 +1,388 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++ ++void vs_crtc_destroy(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ drm_crtc_cleanup(crtc); ++ kfree(vs_crtc); ++} ++ ++static void vs_crtc_reset(struct drm_crtc *crtc) ++{ ++ struct vs_crtc_state *state; ++ ++ if (crtc->state) { ++ __drm_atomic_helper_crtc_destroy_state(crtc->state); ++ ++ state = to_vs_crtc_state(crtc->state); ++ kfree(state); ++ crtc->state = NULL; ++ } ++ ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return; ++ ++ __drm_atomic_helper_crtc_reset(crtc, &state->base); ++ ++ state->sync_mode = VS_SINGLE_DC; ++ state->output_fmt = MEDIA_BUS_FMT_RBG888_1X24; ++ state->encoder_type = DRM_MODE_ENCODER_NONE; ++} ++ ++static struct drm_crtc_state * ++vs_crtc_atomic_duplicate_state(struct drm_crtc *crtc) ++{ ++ struct vs_crtc_state *ori_state; ++ struct vs_crtc_state *state; ++ ++ if (WARN_ON(!crtc->state)) ++ return NULL; ++ ++ ori_state = to_vs_crtc_state(crtc->state); ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); ++ ++ state->sync_mode = ori_state->sync_mode; ++ state->output_fmt = ori_state->output_fmt; ++ state->encoder_type = ori_state->encoder_type; ++ state->bg_color = ori_state->bg_color; ++ state->bpp = ori_state->bpp; ++ state->sync_enable = ori_state->sync_enable; ++ state->dither_enable = ori_state->dither_enable; ++ state->underflow = ori_state->underflow; ++ ++ return &state->base; ++} ++ ++static void vs_crtc_atomic_destroy_state(struct drm_crtc *crtc, ++ struct drm_crtc_state *state) ++{ ++ __drm_atomic_helper_crtc_destroy_state(state); ++ kfree(to_vs_crtc_state(state)); ++} ++ ++static int vs_crtc_atomic_set_property(struct drm_crtc *crtc, ++ struct drm_crtc_state *state, ++ struct drm_property *property, ++ uint64_t val) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ struct vs_crtc_state *vs_crtc_state = to_vs_crtc_state(state); ++ ++ if (property == vs_crtc->sync_mode) ++ vs_crtc_state->sync_mode = val; ++ else if (property == vs_crtc->mmu_prefetch) ++ vs_crtc_state->mmu_prefetch = val; ++ else if (property == vs_crtc->bg_color) ++ vs_crtc_state->bg_color = val; ++ else if (property == vs_crtc->panel_sync) ++ vs_crtc_state->sync_enable = val; ++ else if (property == vs_crtc->dither) ++ vs_crtc_state->dither_enable = val; ++ else ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int vs_crtc_atomic_get_property(struct drm_crtc *crtc, ++ const struct drm_crtc_state *state, ++ struct drm_property *property, ++ uint64_t *val) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ const struct vs_crtc_state *vs_crtc_state = ++ container_of(state, const struct vs_crtc_state, base); ++ ++ if (property == vs_crtc->sync_mode) ++ *val = vs_crtc_state->sync_mode; ++ else if (property == vs_crtc->mmu_prefetch) ++ *val = vs_crtc_state->mmu_prefetch; ++ else if (property == vs_crtc->bg_color) ++ *val = vs_crtc_state->bg_color; ++ else if (property == vs_crtc->panel_sync) ++ *val = vs_crtc_state->sync_enable; ++ else if (property == vs_crtc->dither) ++ *val = vs_crtc_state->dither_enable; ++ else ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int vs_crtc_late_register(struct drm_crtc *crtc) ++{ ++ return 0; ++} ++ ++static int vs_crtc_enable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ vs_crtc->funcs->enable_vblank(vs_crtc->dev, true); ++ ++ return 0; ++} ++ ++static void vs_crtc_disable_vblank(struct drm_crtc *crtc) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ vs_crtc->funcs->enable_vblank(vs_crtc->dev, false); ++} ++ ++static const struct drm_crtc_funcs vs_crtc_funcs = { ++ .set_config = drm_atomic_helper_set_config, ++ .destroy = vs_crtc_destroy, ++ .page_flip = drm_atomic_helper_page_flip, ++ .reset = vs_crtc_reset, ++ .atomic_duplicate_state = vs_crtc_atomic_duplicate_state, ++ .atomic_destroy_state = vs_crtc_atomic_destroy_state, ++ .atomic_set_property = vs_crtc_atomic_set_property, ++ .atomic_get_property = vs_crtc_atomic_get_property, ++ .late_register = vs_crtc_late_register, ++ .enable_vblank = vs_crtc_enable_vblank, ++ .disable_vblank = vs_crtc_disable_vblank, ++}; ++ ++static u8 cal_pixel_bits(u32 bus_format) ++{ ++ u8 bpp; ++ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB565_1X16: ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ bpp = 16; ++ break; ++ case MEDIA_BUS_FMT_RGB666_1X18: ++ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: ++ bpp = 18; ++ break; ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ bpp = 20; ++ break; ++ case MEDIA_BUS_FMT_BGR888_1X24: ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ bpp = 24; ++ break; ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ bpp = 30; ++ break; ++ default: ++ bpp = 24; ++ break; ++ } ++ ++ return bpp; ++} ++ ++static bool vs_crtc_mode_fixup(struct drm_crtc *crtc, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ return vs_crtc->funcs->mode_fixup(vs_crtc->dev, mode, adjusted_mode); ++} ++ ++static void vs_crtc_atomic_enable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ struct vs_crtc_state *vs_crtc_state = to_vs_crtc_state(crtc->state); ++ ++ vs_crtc_state->bpp = cal_pixel_bits(vs_crtc_state->output_fmt); ++ ++ vs_crtc->funcs->enable(vs_crtc->dev, crtc); ++ drm_crtc_vblank_on(crtc); ++} ++ ++static void vs_crtc_atomic_disable(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ drm_crtc_vblank_off(crtc); ++ ++ vs_crtc->funcs->disable(vs_crtc->dev, crtc); ++ ++ if (crtc->state->event && !crtc->state->active) { ++ spin_lock_irq(&crtc->dev->event_lock); ++ drm_crtc_send_vblank_event(crtc, crtc->state->event); ++ spin_unlock_irq(&crtc->dev->event_lock); ++ ++ crtc->state->event = NULL; ++ } ++} ++ ++static void vs_crtc_atomic_begin(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, ++ crtc); ++ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ struct device *dev = vs_crtc->dev; ++ struct drm_property_blob *blob = crtc->state->gamma_lut; ++ struct drm_color_lut *lut; ++ ++ if (crtc_state->color_mgmt_changed) { ++ if (blob && blob->length) { ++ lut = blob->data; ++ vs_crtc->funcs->set_gamma(dev, crtc, lut, ++ blob->length / sizeof(*lut)); ++ vs_crtc->funcs->enable_gamma(dev, crtc, true); ++ } else { ++ vs_crtc->funcs->enable_gamma(dev, crtc, false); ++ } ++ } ++} ++ ++static void vs_crtc_atomic_flush(struct drm_crtc *crtc, ++ struct drm_atomic_state *state) ++{ ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ struct drm_pending_vblank_event *event = crtc->state->event; ++ ++ vs_crtc->funcs->commit(vs_crtc->dev); ++ ++ if (event) { ++ WARN_ON(drm_crtc_vblank_get(crtc) != 0); ++ ++ spin_lock_irq(&crtc->dev->event_lock); ++ drm_crtc_arm_vblank_event(crtc, event); ++ spin_unlock_irq(&crtc->dev->event_lock); ++ crtc->state->event = NULL; ++ } ++} ++ ++static const struct drm_crtc_helper_funcs vs_crtc_helper_funcs = { ++ .mode_fixup = vs_crtc_mode_fixup, ++ .atomic_enable = vs_crtc_atomic_enable, ++ .atomic_disable = vs_crtc_atomic_disable, ++ .atomic_begin = vs_crtc_atomic_begin, ++ .atomic_flush = vs_crtc_atomic_flush, ++}; ++ ++static const struct drm_prop_enum_list vs_sync_mode_enum_list[] = { ++ { VS_SINGLE_DC, "single dc mode" }, ++ { VS_MULTI_DC_PRIMARY, "primary dc for multi dc mode" }, ++ { VS_MULTI_DC_SECONDARY, "secondary dc for multi dc mode" }, ++}; ++ ++struct vs_crtc *vs_crtc_create(struct drm_device *drm_dev, ++ struct vs_dc_info *info) ++{ ++ struct vs_crtc *crtc; ++ int ret; ++ ++ if (!info) ++ return NULL; ++ ++ crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); ++ if (!crtc) ++ return NULL; ++ ++ ret = drm_crtc_init_with_planes(drm_dev, &crtc->base, ++ NULL, NULL, &vs_crtc_funcs, ++ info->name ? info->name : NULL); ++ if (ret) ++ goto err_free_crtc; ++ ++ drm_crtc_helper_add(&crtc->base, &vs_crtc_helper_funcs); ++ ++ /* Set up the crtc properties */ ++ if (info->pipe_sync) { ++ crtc->sync_mode = drm_property_create_enum(drm_dev, 0, ++ "SYNC_MODE", ++ vs_sync_mode_enum_list, ++ ARRAY_SIZE(vs_sync_mode_enum_list)); ++ ++ if (!crtc->sync_mode) ++ goto err_cleanup_crts; ++ ++ drm_object_attach_property(&crtc->base.base, ++ crtc->sync_mode, ++ VS_SINGLE_DC); ++ } ++ ++ if (info->gamma_size) { ++ ret = drm_mode_crtc_set_gamma_size(&crtc->base, ++ info->gamma_size); ++ if (ret) ++ goto err_cleanup_crts; ++ ++ drm_crtc_enable_color_mgmt(&crtc->base, 0, false, ++ info->gamma_size); ++ } ++ ++ if (info->background) { ++ crtc->bg_color = drm_property_create_range(drm_dev, 0, ++ "BG_COLOR", 0, 0xffffffff); ++ ++ if (!crtc->bg_color) ++ goto err_cleanup_crts; ++ ++ drm_object_attach_property(&crtc->base.base, crtc->bg_color, 0); ++ } ++ ++ if (info->panel_sync) { ++ crtc->panel_sync = drm_property_create_bool(drm_dev, 0, "SYNC_ENABLED"); ++ ++ if (!crtc->panel_sync) ++ goto err_cleanup_crts; ++ ++ drm_object_attach_property(&crtc->base.base, crtc->panel_sync, 0); ++ } ++ ++ crtc->dither = drm_property_create_bool(drm_dev, 0, "DITHER_ENABLED"); ++ if (!crtc->dither) ++ goto err_cleanup_crts; ++ ++ drm_object_attach_property(&crtc->base.base, crtc->dither, 0); ++ ++ crtc->max_bpc = info->max_bpc; ++ crtc->color_formats = info->color_formats; ++ return crtc; ++ ++err_cleanup_crts: ++ drm_crtc_cleanup(&crtc->base); ++ ++err_free_crtc: ++ kfree(crtc); ++ return NULL; ++} ++ ++void vs_crtc_handle_vblank(struct drm_crtc *crtc, bool underflow) ++{ ++ struct vs_crtc_state *vs_crtc_state = to_vs_crtc_state(crtc->state); ++ ++ drm_crtc_handle_vblank(crtc); ++ ++ vs_crtc_state->underflow = underflow; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_crtc.h b/drivers/gpu/drm/verisilicon/vs_crtc.h +new file mode 100644 +index 000000000000..33b3b14249ce +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_crtc.h +@@ -0,0 +1,74 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_CRTC_H__ ++#define __VS_CRTC_H__ ++ ++#include ++#include ++ ++#include "vs_type.h" ++ ++struct vs_crtc_funcs { ++ void (*enable)(struct device *dev, struct drm_crtc *crtc); ++ void (*disable)(struct device *dev, struct drm_crtc *crtc); ++ bool (*mode_fixup)(struct device *dev, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode); ++ void (*set_gamma)(struct device *dev, struct drm_crtc *crtc, ++ struct drm_color_lut *lut, unsigned int size); ++ void (*enable_gamma)(struct device *dev, struct drm_crtc *crtc, ++ bool enable); ++ void (*enable_vblank)(struct device *dev, bool enable); ++ void (*commit)(struct device *dev); ++}; ++ ++struct vs_crtc_state { ++ struct drm_crtc_state base; ++ ++ u32 sync_mode; ++ u32 output_fmt; ++ u32 bg_color; ++ u8 encoder_type; ++ u8 mmu_prefetch; ++ u8 bpp; ++ bool sync_enable; ++ bool dither_enable; ++ bool underflow; ++}; ++ ++struct vs_crtc { ++ struct drm_crtc base; ++ struct device *dev; ++ struct drm_pending_vblank_event *event; ++ unsigned int max_bpc; ++ unsigned int color_formats; /* supported color format */ ++ ++ struct drm_property *sync_mode; ++ struct drm_property *mmu_prefetch; ++ struct drm_property *bg_color; ++ struct drm_property *panel_sync; ++ struct drm_property *dither; ++ ++ const struct vs_crtc_funcs *funcs; ++}; ++ ++void vs_crtc_destroy(struct drm_crtc *crtc); ++ ++struct vs_crtc *vs_crtc_create(struct drm_device *drm_dev, ++ struct vs_dc_info *info); ++void vs_crtc_handle_vblank(struct drm_crtc *crtc, bool underflow); ++ ++static inline struct vs_crtc *to_vs_crtc(struct drm_crtc *crtc) ++{ ++ return container_of(crtc, struct vs_crtc, base); ++} ++ ++static inline struct vs_crtc_state * ++to_vs_crtc_state(struct drm_crtc_state *state) ++{ ++ return container_of(state, struct vs_crtc_state, base); ++} ++#endif /* __VS_CRTC_H__ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_type.h b/drivers/gpu/drm/verisilicon/vs_type.h +new file mode 100644 +index 000000000000..6f8db65a703d +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_type.h +@@ -0,0 +1,72 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_TYPE_H__ ++#define __VS_TYPE_H__ ++ ++#include ++ ++#include ++#include ++ ++struct vs_plane_info { ++ const char *name; ++ u8 id; ++ enum drm_plane_type type; ++ unsigned int num_formats; ++ const u32 *formats; ++ u8 num_modifiers; ++ const u64 *modifiers; ++ unsigned int min_width; ++ unsigned int min_height; ++ unsigned int max_width; ++ unsigned int max_height; ++ unsigned int rotation; ++ unsigned int blend_mode; ++ unsigned int color_encoding; ++ ++ /* 0 means no de-gamma LUT */ ++ unsigned int degamma_size; ++ ++ int min_scale; /* 16.16 fixed point */ ++ int max_scale; /* 16.16 fixed point */ ++ ++ /* default zorder value, ++ * and 255 means unsupported zorder capability ++ */ ++ u8 zpos; ++ ++ bool watermark; ++ bool color_mgmt; ++ bool roi; ++}; ++ ++struct vs_dc_info { ++ const char *name; ++ ++ u8 panel_num; ++ ++ /* planes */ ++ u8 plane_num; ++ const struct vs_plane_info *planes; ++ ++ u8 layer_num; ++ unsigned int max_bpc; ++ unsigned int color_formats; ++ ++ /* 0 means no gamma LUT */ ++ u16 gamma_size; ++ u8 gamma_bits; ++ ++ u16 pitch_alignment; ++ ++ bool pipe_sync; ++ bool mmu_prefetch; ++ bool background; ++ bool panel_sync; ++ bool cap_dec; ++}; ++ ++#endif /* __VS_TYPE_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0055-drm-verisilicon-Add-drm-plane-funcs.patch b/srcpkgs/linux6.4/patches/0055-drm-verisilicon-Add-drm-plane-funcs.patch new file mode 100644 index 0000000000000..c919d287ab1ee --- /dev/null +++ b/srcpkgs/linux6.4/patches/0055-drm-verisilicon-Add-drm-plane-funcs.patch @@ -0,0 +1,559 @@ +From c83b7f09bb0ca73d595f16410b357d90b6cedd23 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:41 +0800 +Subject: [PATCH 55/72] drm/verisilicon: Add drm plane funcs + +Implement plane functions for the DRM driver. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Makefile | 3 +- + drivers/gpu/drm/verisilicon/vs_plane.c | 440 +++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_plane.h | 74 +++++ + 3 files changed, 516 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index bae5fbab9bbb..d96ad9399fc7 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -3,7 +3,8 @@ + vs_drm-objs := vs_drv.o \ + vs_crtc.o \ + vs_fb.o \ +- vs_gem.o ++ vs_gem.o \ ++ vs_plane.o + + obj-$(CONFIG_DRM_VERISILICON) += vs_drm.o + +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.c b/drivers/gpu/drm/verisilicon/vs_plane.c +new file mode 100644 +index 000000000000..7b0dcef232ae +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.c +@@ -0,0 +1,440 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "vs_crtc.h" ++#include "vs_fb.h" ++#include "vs_gem.h" ++#include "vs_plane.h" ++#include "vs_type.h" ++ ++void vs_plane_destory(struct drm_plane *plane) ++{ ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ ++ drm_plane_cleanup(plane); ++ kfree(vs_plane); ++} ++ ++static void vs_plane_reset(struct drm_plane *plane) ++{ ++ struct vs_plane_state *state; ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ ++ if (plane->state) { ++ __drm_atomic_helper_plane_destroy_state(plane->state); ++ ++ state = to_vs_plane_state(plane->state); ++ kfree(state); ++ plane->state = NULL; ++ } ++ ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return; ++ ++ __drm_atomic_helper_plane_reset(plane, &state->base); ++ ++ state->degamma = VS_DEGAMMA_DISABLE; ++ state->degamma_changed = false; ++ state->base.zpos = vs_plane->id; ++ ++ memset(&state->status, 0, sizeof(state->status)); ++} ++ ++static void _vs_plane_duplicate_blob(struct vs_plane_state *state, ++ struct vs_plane_state *ori_state) ++{ ++ state->watermark = ori_state->watermark; ++ state->color_mgmt = ori_state->color_mgmt; ++ state->roi = ori_state->roi; ++ ++ if (state->watermark) ++ drm_property_blob_get(state->watermark); ++ if (state->color_mgmt) ++ drm_property_blob_get(state->color_mgmt); ++ if (state->roi) ++ drm_property_blob_get(state->roi); ++} ++ ++static int ++_vs_plane_set_property_blob_from_id(struct drm_device *dev, ++ struct drm_property_blob **blob, ++ u64 blob_id, ++ size_t expected_size) ++{ ++ struct drm_property_blob *new_blob = NULL; ++ ++ if (blob_id) { ++ new_blob = drm_property_lookup_blob(dev, blob_id); ++ if (!new_blob) ++ return -EINVAL; ++ ++ if (new_blob->length != expected_size) { ++ drm_property_blob_put(new_blob); ++ return -EINVAL; ++ } ++ } ++ ++ drm_property_replace_blob(blob, new_blob); ++ drm_property_blob_put(new_blob); ++ ++ return 0; ++} ++ ++static struct drm_plane_state * ++vs_plane_atomic_duplicate_state(struct drm_plane *plane) ++{ ++ struct vs_plane_state *ori_state; ++ struct vs_plane_state *state; ++ ++ if (WARN_ON(!plane->state)) ++ return NULL; ++ ++ ori_state = to_vs_plane_state(plane->state); ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return NULL; ++ ++ __drm_atomic_helper_plane_duplicate_state(plane, &state->base); ++ ++ state->degamma = ori_state->degamma; ++ state->degamma_changed = ori_state->degamma_changed; ++ ++ _vs_plane_duplicate_blob(state, ori_state); ++ memcpy(&state->status, &ori_state->status, sizeof(ori_state->status)); ++ ++ return &state->base; ++} ++ ++static void vs_plane_atomic_destroy_state(struct drm_plane *plane, ++ struct drm_plane_state *state) ++{ ++ struct vs_plane_state *vs_plane_state = to_vs_plane_state(state); ++ ++ __drm_atomic_helper_plane_destroy_state(state); ++ ++ drm_property_blob_put(vs_plane_state->watermark); ++ drm_property_blob_put(vs_plane_state->color_mgmt); ++ drm_property_blob_put(vs_plane_state->roi); ++ kfree(vs_plane_state); ++} ++ ++static int vs_plane_atomic_set_property(struct drm_plane *plane, ++ struct drm_plane_state *state, ++ struct drm_property *property, ++ uint64_t val) ++{ ++ struct drm_device *dev = plane->dev; ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ struct vs_plane_state *vs_plane_state = to_vs_plane_state(state); ++ int ret = 0; ++ ++ if (property == vs_plane->degamma_mode) { ++ if (vs_plane_state->degamma != val) { ++ vs_plane_state->degamma = val; ++ vs_plane_state->degamma_changed = true; ++ } else { ++ vs_plane_state->degamma_changed = false; ++ } ++ } else if (property == vs_plane->watermark_prop) { ++ ret = _vs_plane_set_property_blob_from_id(dev, ++ &vs_plane_state->watermark, ++ val, ++ sizeof(struct drm_vs_watermark)); ++ return ret; ++ } else if (property == vs_plane->color_mgmt_prop) { ++ ret = _vs_plane_set_property_blob_from_id(dev, ++ &vs_plane_state->color_mgmt, ++ val, ++ sizeof(struct drm_vs_color_mgmt)); ++ return ret; ++ } else if (property == vs_plane->roi_prop) { ++ ret = _vs_plane_set_property_blob_from_id(dev, ++ &vs_plane_state->roi, ++ val, ++ sizeof(struct drm_vs_roi)); ++ return ret; ++ } else { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int vs_plane_atomic_get_property(struct drm_plane *plane, ++ const struct drm_plane_state *state, ++ struct drm_property *property, ++ uint64_t *val) ++{ ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ const struct vs_plane_state *vs_plane_state = ++ container_of(state, const struct vs_plane_state, base); ++ ++ if (property == vs_plane->degamma_mode) ++ *val = vs_plane_state->degamma; ++ else if (property == vs_plane->watermark_prop) ++ *val = (vs_plane_state->watermark) ? ++ vs_plane_state->watermark->base.id : 0; ++ else if (property == vs_plane->color_mgmt_prop) ++ *val = (vs_plane_state->color_mgmt) ? ++ vs_plane_state->color_mgmt->base.id : 0; ++ else if (property == vs_plane->roi_prop) ++ *val = (vs_plane_state->roi) ? ++ vs_plane_state->roi->base.id : 0; ++ else ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static bool vs_format_mod_supported(struct drm_plane *plane, ++ u32 format, ++ u64 modifier) ++{ ++ int i; ++ ++ /* We always have to allow these modifiers: ++ * 1. Core DRM checks for LINEAR support if userspace does not provide modifiers. ++ * 2. Not passing any modifiers is the same as explicitly passing INVALID. ++ */ ++ if (modifier == DRM_FORMAT_MOD_LINEAR) ++ return true; ++ ++ /* Check that the modifier is on the list of the plane's supported modifiers. */ ++ for (i = 0; i < plane->modifier_count; i++) { ++ if (modifier == plane->modifiers[i]) ++ break; ++ } ++ ++ if (i == plane->modifier_count) ++ return false; ++ ++ return true; ++} ++ ++const struct drm_plane_funcs vs_plane_funcs = { ++ .update_plane = drm_atomic_helper_update_plane, ++ .disable_plane = drm_atomic_helper_disable_plane, ++ .destroy = vs_plane_destory, ++ .reset = vs_plane_reset, ++ .atomic_duplicate_state = vs_plane_atomic_duplicate_state, ++ .atomic_destroy_state = vs_plane_atomic_destroy_state, ++ .atomic_set_property = vs_plane_atomic_set_property, ++ .atomic_get_property = vs_plane_atomic_get_property, ++ .format_mod_supported = vs_format_mod_supported, ++}; ++ ++static unsigned char vs_get_plane_number(struct drm_framebuffer *fb) ++{ ++ const struct drm_format_info *info; ++ ++ if (!fb) ++ return 0; ++ ++ info = drm_format_info(fb->format->format); ++ if (!info || info->num_planes > MAX_NUM_PLANES) ++ return 0; ++ ++ return info->num_planes; ++} ++ ++static int vs_plane_atomic_check(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ struct drm_framebuffer *fb = new_plane_state->fb; ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct vs_crtc *vs_crtc = to_vs_crtc(crtc); ++ ++ if (!crtc || !fb) ++ return 0; ++ ++ //return vs_plane->funcs->check(vs_crtc->dev, vs_plane, new_plane_state); ++ return vs_plane->funcs->check(vs_crtc->dev, plane, state); ++} ++ ++static void vs_plane_atomic_update(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ unsigned char i, num_planes; ++ struct drm_framebuffer *fb; ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ //struct drm_plane_state *state = plane->state; ++ struct vs_crtc *vs_crtc = to_vs_crtc(new_state->crtc); ++ struct vs_plane_state *plane_state = to_vs_plane_state(new_state); ++ //struct drm_format_name_buf *name = &plane_state->status.format_name; ++ ++ if (!new_state->fb || !new_state->crtc) ++ return; ++ ++ fb = new_state->fb; ++ ++ num_planes = vs_get_plane_number(fb); ++ ++ for (i = 0; i < num_planes; i++) { ++ struct vs_gem_object *vs_obj; ++ ++ vs_obj = vs_fb_get_gem_obj(fb, i); ++ vs_plane->dma_addr[i] = vs_obj->iova + fb->offsets[i]; ++ } ++ ++ plane_state->status.src = drm_plane_state_src(new_state); ++ plane_state->status.dest = drm_plane_state_dest(new_state); ++ ++ vs_plane->funcs->update(vs_crtc->dev, vs_plane, plane, state); ++} ++ ++static void vs_plane_atomic_disable(struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, ++ plane); ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ struct vs_crtc *vs_crtc = to_vs_crtc(old_state->crtc); ++ ++ vs_plane->funcs->disable(vs_crtc->dev, vs_plane, old_state); ++} ++ ++const struct drm_plane_helper_funcs vs_plane_helper_funcs = { ++ .atomic_check = vs_plane_atomic_check, ++ .atomic_update = vs_plane_atomic_update, ++ .atomic_disable = vs_plane_atomic_disable, ++}; ++ ++static const struct drm_prop_enum_list vs_degamma_mode_enum_list[] = { ++ { VS_DEGAMMA_DISABLE, "disabled" }, ++ { VS_DEGAMMA_BT709, "preset degamma for BT709" }, ++ { VS_DEGAMMA_BT2020, "preset degamma for BT2020" }, ++}; ++ ++struct vs_plane *vs_plane_create(struct drm_device *drm_dev, ++ struct vs_plane_info *info, ++ unsigned int layer_num, ++ unsigned int possible_crtcs) ++{ ++ struct vs_plane *plane; ++ int ret; ++ ++ if (!info) ++ return NULL; ++ ++ plane = kzalloc(sizeof(*plane), GFP_KERNEL); ++ if (!plane) ++ return NULL; ++ ++ ret = drm_universal_plane_init(drm_dev, &plane->base, possible_crtcs, ++ &vs_plane_funcs, info->formats, ++ info->num_formats, info->modifiers, info->type, ++ info->name ? info->name : NULL); ++ if (ret) ++ goto err_free_plane; ++ ++ drm_plane_helper_add(&plane->base, &vs_plane_helper_funcs); ++ ++ /* Set up the plane properties */ ++ if (info->degamma_size) { ++ plane->degamma_mode = ++ drm_property_create_enum(drm_dev, 0, ++ "DEGAMMA_MODE", ++ vs_degamma_mode_enum_list, ++ ARRAY_SIZE(vs_degamma_mode_enum_list)); ++ ++ if (!plane->degamma_mode) ++ goto error_cleanup_plane; ++ ++ drm_object_attach_property(&plane->base.base, ++ plane->degamma_mode, ++ VS_DEGAMMA_DISABLE); ++ } ++ ++ if (info->rotation) { ++ ret = drm_plane_create_rotation_property(&plane->base, ++ DRM_MODE_ROTATE_0, ++ info->rotation); ++ if (ret) ++ goto error_cleanup_plane; ++ } ++ ++ if (info->blend_mode) { ++ ret = drm_plane_create_blend_mode_property(&plane->base, ++ info->blend_mode); ++ if (ret) ++ goto error_cleanup_plane; ++ ret = drm_plane_create_alpha_property(&plane->base); ++ if (ret) ++ goto error_cleanup_plane; ++ } ++ ++ if (info->color_encoding) { ++ ret = drm_plane_create_color_properties(&plane->base, ++ info->color_encoding, ++ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE), ++ DRM_COLOR_YCBCR_BT709, ++ DRM_COLOR_YCBCR_LIMITED_RANGE); ++ if (ret) ++ goto error_cleanup_plane; ++ } ++ ++ if (info->zpos != 255) { ++ ret = drm_plane_create_zpos_property(&plane->base, info->zpos, 0, ++ layer_num - 1); ++ if (ret) ++ goto error_cleanup_plane; ++ } else { ++ ret = drm_plane_create_zpos_immutable_property(&plane->base, ++ info->zpos); ++ if (ret) ++ goto error_cleanup_plane; ++ } ++ ++ if (info->watermark) { ++ plane->watermark_prop = drm_property_create(drm_dev, DRM_MODE_PROP_BLOB, ++ "WATERMARK", 0); ++ if (!plane->watermark_prop) ++ goto error_cleanup_plane; ++ ++ drm_object_attach_property(&plane->base.base, plane->watermark_prop, 0); ++ } ++ ++ if (info->color_mgmt) { ++ plane->color_mgmt_prop = drm_property_create(drm_dev, DRM_MODE_PROP_BLOB, ++ "COLOR_CONFIG", 0); ++ if (!plane->color_mgmt_prop) ++ goto error_cleanup_plane; ++ ++ drm_object_attach_property(&plane->base.base, plane->color_mgmt_prop, 0); ++ } ++ ++ if (info->roi) { ++ plane->roi_prop = drm_property_create(drm_dev, DRM_MODE_PROP_BLOB, ++ "ROI", 0); ++ if (!plane->roi_prop) ++ goto error_cleanup_plane; ++ ++ drm_object_attach_property(&plane->base.base, plane->roi_prop, 0); ++ } ++ ++ return plane; ++ ++error_cleanup_plane: ++ drm_plane_cleanup(&plane->base); ++err_free_plane: ++ kfree(plane); ++ return NULL; ++} +diff --git a/drivers/gpu/drm/verisilicon/vs_plane.h b/drivers/gpu/drm/verisilicon/vs_plane.h +new file mode 100644 +index 000000000000..76ef3c3de045 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_plane.h +@@ -0,0 +1,74 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_PLANE_H__ ++#define __VS_PLANE_H__ ++ ++#include ++#include ++ ++#include "vs_fb.h" ++#include "vs_type.h" ++ ++struct vs_plane; ++ ++struct vs_plane_funcs { ++ void (*update)(struct device *dev, struct vs_plane *plane, struct drm_plane *drm_plane, ++ struct drm_atomic_state *state); ++ void (*disable)(struct device *dev, struct vs_plane *plane, ++ struct drm_plane_state *old_state); ++ int (*check)(struct device *dev, struct drm_plane *plane, ++ struct drm_atomic_state *state); ++}; ++ ++struct vs_plane_status { ++ u32 tile_mode; ++ struct drm_rect src; ++ struct drm_rect dest; ++}; ++ ++struct vs_plane_state { ++ struct drm_plane_state base; ++ struct vs_plane_status status; /* for debugfs */ ++ ++ struct drm_property_blob *watermark; ++ struct drm_property_blob *color_mgmt; ++ struct drm_property_blob *roi; ++ ++ u32 degamma; ++ bool degamma_changed; ++}; ++ ++struct vs_plane { ++ struct drm_plane base; ++ u8 id; ++ dma_addr_t dma_addr[MAX_NUM_PLANES]; ++ ++ struct drm_property *degamma_mode; ++ struct drm_property *watermark_prop; ++ struct drm_property *color_mgmt_prop; ++ struct drm_property *roi_prop; ++ ++ const struct vs_plane_funcs *funcs; ++}; ++ ++void vs_plane_destory(struct drm_plane *plane); ++ ++struct vs_plane *vs_plane_create(struct drm_device *drm_dev, ++ struct vs_plane_info *info, ++ unsigned int layer_num, ++ unsigned int possible_crtcs); ++ ++static inline struct vs_plane *to_vs_plane(struct drm_plane *plane) ++{ ++ return container_of(plane, struct vs_plane, base); ++} ++ ++static inline struct vs_plane_state * ++to_vs_plane_state(struct drm_plane_state *state) ++{ ++ return container_of(state, struct vs_plane_state, base); ++} ++#endif /* __VS_PLANE_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0056-drm-verisilicon-Add-verisilicon-dc-controller-driver.patch b/srcpkgs/linux6.4/patches/0056-drm-verisilicon-Add-verisilicon-dc-controller-driver.patch new file mode 100644 index 0000000000000..c42a4f046252a --- /dev/null +++ b/srcpkgs/linux6.4/patches/0056-drm-verisilicon-Add-verisilicon-dc-controller-driver.patch @@ -0,0 +1,3689 @@ +From b801749f58d611b7bf844cff60e867990864911f Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:42 +0800 +Subject: [PATCH 56/72] drm/verisilicon: Add verisilicon dc controller driver + +Add DC8200 display controller driver for StarFive JH7110 SoC. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Makefile | 4 +- + drivers/gpu/drm/verisilicon/vs_dc.c | 1040 ++++++++++++ + drivers/gpu/drm/verisilicon/vs_dc.h | 62 + + drivers/gpu/drm/verisilicon/vs_dc_hw.c | 2008 ++++++++++++++++++++++++ + drivers/gpu/drm/verisilicon/vs_dc_hw.h | 496 ++++++ + drivers/gpu/drm/verisilicon/vs_drv.c | 2 + + 6 files changed, 3611 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc.h + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c + create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h + +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index d96ad9399fc7..0ed25b5e3062 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -1,7 +1,9 @@ + # SPDX-License-Identifier: GPL-2.0 + +-vs_drm-objs := vs_drv.o \ ++vs_drm-objs := vs_dc_hw.o \ ++ vs_dc.o \ + vs_crtc.o \ ++ vs_drv.o \ + vs_fb.o \ + vs_gem.o \ + vs_plane.o +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.c b/drivers/gpu/drm/verisilicon/vs_dc.c +new file mode 100644 +index 000000000000..a512aaa57f2f +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.c +@@ -0,0 +1,1040 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_dc_hw.h" ++#include "vs_dc.h" ++#include "vs_drv.h" ++#include "vs_type.h" ++ ++static const char * const vout_clocks[] = { ++ "clk_vout_noc_disp", ++ "clk_vout_pix0", ++ "clk_vout_pix1", ++ "clk_vout_axi", ++ "clk_vout_core", ++ "clk_vout_vout_ahb", ++ "hdmitx0_pixel", ++ "clk_vout_dc8200", ++ ++}; ++ ++static const char * const vout_resets[] = { ++ "rst_vout_axi", ++ "rst_vout_ahb", ++ "rst_vout_core", ++}; ++ ++static inline void update_format(u32 format, u64 mod, struct dc_hw_fb *fb) ++{ ++ u8 f = FORMAT_A8R8G8B8; ++ ++ switch (format) { ++ case DRM_FORMAT_XRGB4444: ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_BGRX4444: ++ f = FORMAT_X4R4G4B4; ++ break; ++ case DRM_FORMAT_ARGB4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_BGRA4444: ++ f = FORMAT_A4R4G4B4; ++ break; ++ case DRM_FORMAT_XRGB1555: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_BGRX5551: ++ f = FORMAT_X1R5G5B5; ++ break; ++ case DRM_FORMAT_ARGB1555: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGRA5551: ++ f = FORMAT_A1R5G5B5; ++ break; ++ case DRM_FORMAT_RGB565: ++ case DRM_FORMAT_BGR565: ++ f = FORMAT_R5G6B5; ++ break; ++ case DRM_FORMAT_XRGB8888: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_BGRX8888: ++ f = FORMAT_X8R8G8B8; ++ break; ++ case DRM_FORMAT_ARGB8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_BGRA8888: ++ f = FORMAT_A8R8G8B8; ++ break; ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ f = FORMAT_YUY2; ++ break; ++ case DRM_FORMAT_UYVY: ++ case DRM_FORMAT_VYUY: ++ f = FORMAT_UYVY; ++ break; ++ case DRM_FORMAT_YUV420: ++ case DRM_FORMAT_YVU420: ++ f = FORMAT_YV12; ++ break; ++ case DRM_FORMAT_NV21: ++ f = FORMAT_NV12; ++ break; ++ case DRM_FORMAT_NV16: ++ case DRM_FORMAT_NV61: ++ f = FORMAT_NV16; ++ break; ++ case DRM_FORMAT_P010: ++ f = FORMAT_P010; ++ break; ++ case DRM_FORMAT_ARGB2101010: ++ case DRM_FORMAT_RGBA1010102: ++ case DRM_FORMAT_ABGR2101010: ++ case DRM_FORMAT_BGRA1010102: ++ f = FORMAT_A2R10G10B10; ++ break; ++ case DRM_FORMAT_NV12: ++ if (fourcc_mod_vs_get_type(mod) == ++ DRM_FORMAT_MOD_VS_TYPE_CUSTOM_10BIT) ++ f = FORMAT_NV12_10BIT; ++ else ++ f = FORMAT_NV12; ++ break; ++ case DRM_FORMAT_YUV444: ++ if (fourcc_mod_vs_get_type(mod) == ++ DRM_FORMAT_MOD_VS_TYPE_CUSTOM_10BIT) ++ f = FORMAT_YUV444_10BIT; ++ else ++ f = FORMAT_YUV444; ++ break; ++ default: ++ break; ++ } ++ ++ fb->format = f; ++} ++ ++static inline void update_swizzle(u32 format, struct dc_hw_fb *fb) ++{ ++ fb->swizzle = SWIZZLE_ARGB; ++ fb->uv_swizzle = 0; ++ ++ switch (format) { ++ case DRM_FORMAT_RGBX4444: ++ case DRM_FORMAT_RGBA4444: ++ case DRM_FORMAT_RGBX5551: ++ case DRM_FORMAT_RGBA5551: ++ case DRM_FORMAT_RGBX8888: ++ case DRM_FORMAT_RGBA8888: ++ case DRM_FORMAT_RGBA1010102: ++ fb->swizzle = SWIZZLE_RGBA; ++ break; ++ case DRM_FORMAT_XBGR4444: ++ case DRM_FORMAT_ABGR4444: ++ case DRM_FORMAT_XBGR1555: ++ case DRM_FORMAT_ABGR1555: ++ case DRM_FORMAT_BGR565: ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ case DRM_FORMAT_ABGR2101010: ++ fb->swizzle = SWIZZLE_ABGR; ++ break; ++ case DRM_FORMAT_BGRX4444: ++ case DRM_FORMAT_BGRA4444: ++ case DRM_FORMAT_BGRX5551: ++ case DRM_FORMAT_BGRA5551: ++ case DRM_FORMAT_BGRX8888: ++ case DRM_FORMAT_BGRA8888: ++ case DRM_FORMAT_BGRA1010102: ++ fb->swizzle = SWIZZLE_BGRA; ++ break; ++ case DRM_FORMAT_YVYU: ++ case DRM_FORMAT_VYUY: ++ case DRM_FORMAT_NV21: ++ case DRM_FORMAT_NV61: ++ fb->uv_swizzle = 1; ++ break; ++ default: ++ break; ++ } ++} ++ ++static inline void update_watermark(struct drm_property_blob *watermark, ++ struct dc_hw_fb *fb) ++{ ++ struct drm_vs_watermark *data; ++ ++ fb->water_mark = 0; ++ ++ if (watermark) { ++ data = watermark->data; ++ fb->water_mark = data->watermark & 0xFFFFF; ++ } ++} ++ ++static inline u8 to_vs_rotation(unsigned int rotation) ++{ ++ u8 rot; ++ ++ switch (rotation & DRM_MODE_REFLECT_MASK) { ++ case DRM_MODE_REFLECT_X: ++ rot = FLIP_X; ++ return rot; ++ case DRM_MODE_REFLECT_Y: ++ rot = FLIP_Y; ++ return rot; ++ case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y: ++ rot = FLIP_XY; ++ return rot; ++ default: ++ break; ++ } ++ ++ switch (rotation & DRM_MODE_ROTATE_MASK) { ++ case DRM_MODE_ROTATE_0: ++ rot = ROT_0; ++ break; ++ case DRM_MODE_ROTATE_90: ++ rot = ROT_90; ++ break; ++ case DRM_MODE_ROTATE_180: ++ rot = ROT_180; ++ break; ++ case DRM_MODE_ROTATE_270: ++ rot = ROT_270; ++ break; ++ default: ++ rot = ROT_0; ++ break; ++ } ++ ++ return rot; ++} ++ ++static inline u8 to_vs_yuv_color_space(u32 color_space) ++{ ++ u8 cs; ++ ++ switch (color_space) { ++ case DRM_COLOR_YCBCR_BT601: ++ cs = COLOR_SPACE_601; ++ break; ++ case DRM_COLOR_YCBCR_BT709: ++ cs = COLOR_SPACE_709; ++ break; ++ case DRM_COLOR_YCBCR_BT2020: ++ cs = COLOR_SPACE_2020; ++ break; ++ default: ++ cs = COLOR_SPACE_601; ++ break; ++ } ++ ++ return cs; ++} ++ ++static inline u8 to_vs_tile_mode(u64 modifier) ++{ ++ return (u8)(modifier & DRM_FORMAT_MOD_VS_NORM_MODE_MASK); ++} ++ ++static inline u8 to_vs_display_id(struct vs_dc *dc, struct drm_crtc *crtc) ++{ ++ u8 panel_num = dc->hw.info->panel_num; ++ u32 index = drm_crtc_index(crtc); ++ int i; ++ ++ for (i = 0; i < panel_num; i++) { ++ if (index == dc->crtc[i]->base.index) ++ return i; ++ } ++ ++ return 0; ++} ++ ++static int plda_clk_rst_init(struct device *dev) ++{ ++ int ret = 0; ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ ++ ret = clk_bulk_prepare_enable(dc->nclks, dc->clk_vout); ++ if (ret) { ++ dev_err(dev, "failed to enable clocks\n"); ++ return ret; ++ } ++ ++ ret = reset_control_bulk_deassert(dc->nrsts, dc->rst_vout); ++ return ret; ++} ++ ++static void plda_clk_rst_deinit(struct device *dev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ ++ reset_control_bulk_assert(dc->nrsts, dc->rst_vout); ++ clk_bulk_disable_unprepare(dc->nclks, dc->clk_vout); ++} ++ ++static void dc_deinit(struct device *dev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ ++ dc_hw_enable_interrupt(&dc->hw, 0); ++ dc_hw_deinit(&dc->hw); ++ plda_clk_rst_deinit(dev); ++} ++ ++static int dc_init(struct device *dev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ int ret; ++ ++ dc->first_frame = true; ++ ++ ret = plda_clk_rst_init(dev); ++ if (ret < 0) { ++ dev_err(dev, "failed to init dc clk reset: %d\n", ret); ++ return ret; ++ } ++ ++ ret = dc_hw_init(&dc->hw); ++ if (ret) { ++ dev_err(dev, "failed to init DC HW\n"); ++ return ret; ++ } ++ return 0; ++} ++ ++static void vs_dc_enable(struct device *dev, struct drm_crtc *crtc) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ struct vs_crtc_state *crtc_state = to_vs_crtc_state(crtc->state); ++ struct drm_display_mode *mode = &crtc->state->adjusted_mode; ++ struct dc_hw_display display; ++ ++ display.bus_format = crtc_state->output_fmt; ++ display.h_active = mode->hdisplay; ++ display.h_total = mode->htotal; ++ display.h_sync_start = mode->hsync_start; ++ display.h_sync_end = mode->hsync_end; ++ if (mode->flags & DRM_MODE_FLAG_PHSYNC) ++ display.h_sync_polarity = true; ++ else ++ display.h_sync_polarity = false; ++ ++ display.v_active = mode->vdisplay; ++ display.v_total = mode->vtotal; ++ display.v_sync_start = mode->vsync_start; ++ display.v_sync_end = mode->vsync_end; ++ ++ if (mode->flags & DRM_MODE_FLAG_PVSYNC) ++ display.v_sync_polarity = true; ++ else ++ display.v_sync_polarity = false; ++ ++ display.sync_mode = crtc_state->sync_mode; ++ display.bg_color = crtc_state->bg_color; ++ ++ display.id = to_vs_display_id(dc, crtc); ++ display.sync_enable = crtc_state->sync_enable; ++ display.dither_enable = crtc_state->dither_enable; ++ ++ display.enable = true; ++ ++ if (crtc_state->encoder_type == DRM_MODE_ENCODER_DSI) { ++ dc_hw_set_out(&dc->hw, OUT_DPI, display.id); ++ clk_set_rate(dc->clk_vout[CLK_VOUT_SOC_PIX].clk, mode->clock * 1000); ++ clk_set_parent(dc->clk_vout[CLK_VOUT_PIX1].clk, ++ dc->clk_vout[CLK_VOUT_SOC_PIX].clk); ++ } else { ++ dc_hw_set_out(&dc->hw, OUT_DP, display.id); ++ clk_set_parent(dc->clk_vout[CLK_VOUT_PIX0].clk, ++ dc->clk_vout[CLK_VOUT_HDMI_PIX].clk); ++ } ++ ++ dc_hw_setup_display(&dc->hw, &display); ++} ++ ++static void vs_dc_disable(struct device *dev, struct drm_crtc *crtc) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ struct dc_hw_display display; ++ ++ display.id = to_vs_display_id(dc, crtc); ++ display.enable = false; ++ ++ dc_hw_setup_display(&dc->hw, &display); ++} ++ ++static bool vs_dc_mode_fixup(struct device *dev, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adjusted_mode) ++{ ++ return true; ++} ++ ++static void vs_dc_set_gamma(struct device *dev, struct drm_crtc *crtc, ++ struct drm_color_lut *lut, unsigned int size) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ u16 i, r, g, b; ++ u8 bits, id; ++ ++ if (size != dc->hw.info->gamma_size) { ++ dev_err(dev, "gamma size does not match!\n"); ++ return; ++ } ++ ++ id = to_vs_display_id(dc, crtc); ++ ++ bits = dc->hw.info->gamma_bits; ++ for (i = 0; i < size; i++) { ++ r = drm_color_lut_extract(lut[i].red, bits); ++ g = drm_color_lut_extract(lut[i].green, bits); ++ b = drm_color_lut_extract(lut[i].blue, bits); ++ dc_hw_update_gamma(&dc->hw, id, i, r, g, b); ++ } ++} ++ ++static void vs_dc_enable_gamma(struct device *dev, struct drm_crtc *crtc, ++ bool enable) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ u8 id; ++ ++ id = to_vs_display_id(dc, crtc); ++ dc_hw_enable_gamma(&dc->hw, id, enable); ++} ++ ++static void vs_dc_enable_vblank(struct device *dev, bool enable) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ ++ dc_hw_enable_interrupt(&dc->hw, enable); ++} ++ ++static u32 calc_factor(u32 src, u32 dest) ++{ ++ u32 factor = 1 << 16; ++ ++ if (src > 1 && dest > 1) ++ factor = ((src - 1) << 16) / (dest - 1); ++ ++ return factor; ++} ++ ++static void update_scale(struct drm_plane_state *state, struct dc_hw_roi *roi, ++ struct dc_hw_scale *scale) ++{ ++ int dst_w = drm_rect_width(&state->dst); ++ int dst_h = drm_rect_height(&state->dst); ++ int src_w, src_h, temp; ++ ++ scale->enable = false; ++ ++ if (roi->enable) { ++ src_w = roi->width; ++ src_h = roi->height; ++ } else { ++ src_w = drm_rect_width(&state->src) >> 16; ++ src_h = drm_rect_height(&state->src) >> 16; ++ } ++ ++ if (drm_rotation_90_or_270(state->rotation)) { ++ temp = src_w; ++ src_w = src_h; ++ src_h = temp; ++ } ++ ++ if (src_w != dst_w) { ++ scale->scale_factor_x = calc_factor(src_w, dst_w); ++ scale->enable = true; ++ } else { ++ scale->scale_factor_x = 1 << 16; ++ } ++ if (src_h != dst_h) { ++ scale->scale_factor_y = calc_factor(src_h, dst_h); ++ scale->enable = true; ++ } else { ++ scale->scale_factor_y = 1 << 16; ++ } ++} ++ ++static void update_fb(struct vs_plane *plane, u8 display_id, ++ struct dc_hw_fb *fb, struct drm_plane_state *state) ++{ ++ struct vs_plane_state *plane_state = to_vs_plane_state(state); ++ struct drm_framebuffer *drm_fb = state->fb; ++ struct drm_rect *src = &state->src; ++ ++ fb->display_id = display_id; ++ fb->y_address = plane->dma_addr[0]; ++ fb->y_stride = drm_fb->pitches[0]; ++ if (drm_fb->format->format == DRM_FORMAT_YVU420) { ++ fb->u_address = plane->dma_addr[2]; ++ fb->v_address = plane->dma_addr[1]; ++ fb->u_stride = drm_fb->pitches[2]; ++ fb->v_stride = drm_fb->pitches[1]; ++ } else { ++ fb->u_address = plane->dma_addr[1]; ++ fb->v_address = plane->dma_addr[2]; ++ fb->u_stride = drm_fb->pitches[1]; ++ fb->v_stride = drm_fb->pitches[2]; ++ } ++ fb->width = drm_rect_width(src) >> 16; ++ fb->height = drm_rect_height(src) >> 16; ++ fb->tile_mode = to_vs_tile_mode(drm_fb->modifier); ++ fb->rotation = to_vs_rotation(state->rotation); ++ fb->yuv_color_space = to_vs_yuv_color_space(state->color_encoding); ++ fb->zpos = state->zpos; ++ fb->enable = state->visible; ++ update_format(drm_fb->format->format, drm_fb->modifier, fb); ++ update_swizzle(drm_fb->format->format, fb); ++ update_watermark(plane_state->watermark, fb); ++ plane_state->status.tile_mode = fb->tile_mode; ++} ++ ++static void update_degamma(struct vs_dc *dc, struct vs_plane *plane, ++ struct vs_plane_state *plane_state) ++{ ++ dc_hw_update_degamma(&dc->hw, plane->id, plane_state->degamma); ++ plane_state->degamma_changed = false; ++} ++ ++static void update_roi(struct vs_dc *dc, u8 id, ++ struct vs_plane_state *plane_state, ++ struct dc_hw_roi *roi, ++ struct drm_plane_state *state) ++{ ++ struct drm_vs_roi *data; ++ struct drm_rect *src = &state->src; ++ u16 src_w = drm_rect_width(src) >> 16; ++ u16 src_h = drm_rect_height(src) >> 16; ++ ++ if (plane_state->roi) { ++ data = plane_state->roi->data; ++ ++ if (data->enable) { ++ roi->x = data->roi_x; ++ roi->y = data->roi_y; ++ roi->width = (data->roi_x + data->roi_w > src_w) ? ++ (src_w - data->roi_x) : data->roi_w; ++ roi->height = (data->roi_y + data->roi_h > src_h) ? ++ (src_h - data->roi_y) : data->roi_h; ++ roi->enable = true; ++ } else { ++ roi->enable = false; ++ } ++ ++ dc_hw_update_roi(&dc->hw, id, roi); ++ } else { ++ roi->enable = false; ++ } ++} ++ ++static void update_color_mgmt(struct vs_dc *dc, u8 id, ++ struct dc_hw_fb *fb, ++ struct vs_plane_state *plane_state) ++{ ++ struct drm_vs_color_mgmt *data; ++ struct dc_hw_colorkey colorkey; ++ ++ if (plane_state->color_mgmt) { ++ data = plane_state->color_mgmt->data; ++ ++ fb->clear_enable = data->clear_enable; ++ fb->clear_value = data->clear_value; ++ ++ if (data->colorkey > data->colorkey_high) ++ data->colorkey = data->colorkey_high; ++ ++ colorkey.colorkey = data->colorkey; ++ colorkey.colorkey_high = data->colorkey_high; ++ colorkey.transparency = (data->transparency) ? ++ DC_TRANSPARENCY_KEY : DC_TRANSPARENCY_OPAQUE; ++ dc_hw_update_colorkey(&dc->hw, id, &colorkey); ++ } ++} ++ ++static void update_plane(struct vs_dc *dc, struct vs_plane *plane, ++ struct drm_plane *drm_plane, ++ struct drm_atomic_state *drm_state) ++{ ++ struct dc_hw_fb fb = {0}; ++ struct dc_hw_scale scale; ++ struct dc_hw_position pos; ++ struct dc_hw_blend blend; ++ struct dc_hw_roi roi; ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(drm_state, ++ drm_plane); ++ struct vs_plane_state *plane_state = to_vs_plane_state(state); ++ struct drm_rect *dest = &state->dst; ++ bool dec_enable = false; ++ u8 display_id = 0; ++ ++ display_id = to_vs_display_id(dc, state->crtc); ++ update_fb(plane, display_id, &fb, state); ++ fb.dec_enable = dec_enable; ++ ++ update_roi(dc, plane->id, plane_state, &roi, state); ++ ++ update_scale(state, &roi, &scale); ++ ++ if (plane_state->degamma_changed) ++ update_degamma(dc, plane, plane_state); ++ ++ pos.start_x = dest->x1; ++ pos.start_y = dest->y1; ++ pos.end_x = dest->x2; ++ pos.end_y = dest->y2; ++ ++ blend.alpha = (u8)(state->alpha >> 8); ++ blend.blend_mode = (u8)(state->pixel_blend_mode); ++ ++ update_color_mgmt(dc, plane->id, &fb, plane_state); ++ ++ dc_hw_update_plane(&dc->hw, plane->id, &fb, &scale, &pos, &blend); ++} ++ ++static void update_qos(struct vs_dc *dc, struct vs_plane *plane, ++ struct drm_plane *drm_plane, ++ struct drm_atomic_state *drm_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(drm_state, ++ drm_plane); ++ struct vs_plane_state *plane_state = to_vs_plane_state(state); ++ struct drm_vs_watermark *data; ++ struct dc_hw_qos qos; ++ ++ if (plane_state->watermark) { ++ data = plane_state->watermark->data; ++ ++ if (data->qos_high) { ++ if (data->qos_low > data->qos_high) ++ data->qos_low = data->qos_high; ++ ++ qos.low_value = data->qos_low & 0x0F; ++ qos.high_value = data->qos_high & 0x0F; ++ dc_hw_update_qos(&dc->hw, &qos); ++ } ++ } ++} ++ ++static void update_cursor_size(struct drm_plane_state *state, struct dc_hw_cursor *cursor) ++{ ++ u8 size_type; ++ ++ switch (state->crtc_w) { ++ case 32: ++ size_type = CURSOR_SIZE_32X32; ++ break; ++ case 64: ++ size_type = CURSOR_SIZE_64X64; ++ break; ++ default: ++ size_type = CURSOR_SIZE_32X32; ++ break; ++ } ++ ++ cursor->size = size_type; ++} ++ ++static void update_cursor_plane(struct vs_dc *dc, struct vs_plane *plane, ++ struct drm_plane *drm_plane, ++ struct drm_atomic_state *drm_state) ++{ ++ struct drm_plane_state *state = drm_atomic_get_new_plane_state(drm_state, ++ drm_plane); ++ struct drm_framebuffer *drm_fb = state->fb; ++ struct dc_hw_cursor cursor; ++ ++ cursor.address = plane->dma_addr[0]; ++ cursor.x = state->crtc_x; ++ cursor.y = state->crtc_y; ++ cursor.hot_x = drm_fb->hot_x; ++ cursor.hot_y = drm_fb->hot_y; ++ cursor.display_id = to_vs_display_id(dc, state->crtc); ++ update_cursor_size(state, &cursor); ++ cursor.enable = true; ++ ++ dc_hw_update_cursor(&dc->hw, cursor.display_id, &cursor); ++} ++ ++static void vs_dc_update_plane(struct device *dev, struct vs_plane *plane, ++ struct drm_plane *drm_plane, ++ struct drm_atomic_state *drm_state) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ enum drm_plane_type type = plane->base.type; ++ ++ switch (type) { ++ case DRM_PLANE_TYPE_PRIMARY: ++ case DRM_PLANE_TYPE_OVERLAY: ++ update_plane(dc, plane, drm_plane, drm_state); ++ update_qos(dc, plane, drm_plane, drm_state); ++ break; ++ case DRM_PLANE_TYPE_CURSOR: ++ update_cursor_plane(dc, plane, drm_plane, drm_state); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void vs_dc_disable_plane(struct device *dev, struct vs_plane *plane, ++ struct drm_plane_state *old_state) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ enum drm_plane_type type = plane->base.type; ++ struct dc_hw_fb fb = {0}; ++ struct dc_hw_cursor cursor = {0}; ++ ++ switch (type) { ++ case DRM_PLANE_TYPE_PRIMARY: ++ case DRM_PLANE_TYPE_OVERLAY: ++ fb.enable = false; ++ dc_hw_update_plane(&dc->hw, plane->id, &fb, NULL, NULL, NULL); ++ break; ++ ++ case DRM_PLANE_TYPE_CURSOR: ++ cursor.enable = false; ++ cursor.display_id = to_vs_display_id(dc, old_state->crtc); ++ dc_hw_update_cursor(&dc->hw, cursor.display_id, &cursor); ++ break; ++ default: ++ break; ++ } ++} ++ ++static bool vs_dc_mod_supported(const struct vs_plane_info *plane_info, ++ u64 modifier) ++{ ++ const u64 *mods; ++ ++ if (!plane_info->modifiers) ++ return false; ++ ++ for (mods = plane_info->modifiers; *mods != DRM_FORMAT_MOD_INVALID; mods++) { ++ if (*mods == modifier) ++ return true; ++ } ++ ++ return false; ++} ++ ++static int vs_dc_check_plane(struct device *dev, struct drm_plane *plane, ++ struct drm_atomic_state *state) ++{ ++ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, ++ plane); ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ struct drm_framebuffer *fb = new_plane_state->fb; ++ const struct vs_plane_info *plane_info; ++ struct drm_crtc *crtc = new_plane_state->crtc; ++ struct drm_crtc_state *crtc_state; ++ struct vs_plane *vs_plane = to_vs_plane(plane); ++ ++ plane_info = &dc->hw.info->planes[vs_plane->id]; ++ if (!plane_info) ++ return -EINVAL; ++ ++ if (fb->width < plane_info->min_width || ++ fb->width > plane_info->max_width || ++ fb->height < plane_info->min_height || ++ fb->height > plane_info->max_height) ++ dev_err_once(dev, "buffer size may not support on plane%d.\n", ++ vs_plane->id); ++ ++ if (vs_plane->base.type != DRM_PLANE_TYPE_CURSOR && ++ (!vs_dc_mod_supported(plane_info, fb->modifier))) { ++ dev_err(dev, "unsupported modifier on plane%d.\n", vs_plane->id); ++ return -EINVAL; ++ } ++ ++ crtc_state = drm_atomic_get_existing_crtc_state(state, crtc); ++ if (IS_ERR(crtc_state)) ++ return -EINVAL; ++ ++ return drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, ++ plane_info->min_scale, ++ plane_info->max_scale, ++ true, true); ++} ++ ++static irqreturn_t dc_isr(int irq, void *data) ++{ ++ struct vs_dc *dc = data; ++ struct vs_dc_info *dc_info = dc->hw.info; ++ u32 i, ret; ++ ++ ret = dc_hw_get_interrupt(&dc->hw); ++ ++ for (i = 0; i < dc_info->panel_num; i++) ++ vs_crtc_handle_vblank(&dc->crtc[i]->base, dc_hw_check_underflow(&dc->hw)); ++ ++ return IRQ_HANDLED; ++} ++ ++static void vs_dc_commit(struct device *dev) ++{ ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ ++ dc_hw_enable_shadow_register(&dc->hw, false); ++ ++ dc_hw_commit(&dc->hw); ++ ++ if (dc->first_frame) ++ dc->first_frame = false; ++ ++ dc_hw_enable_shadow_register(&dc->hw, true); ++} ++ ++static const struct vs_crtc_funcs dc_crtc_funcs = { ++ .enable = vs_dc_enable, ++ .disable = vs_dc_disable, ++ .mode_fixup = vs_dc_mode_fixup, ++ .set_gamma = vs_dc_set_gamma, ++ .enable_gamma = vs_dc_enable_gamma, ++ .enable_vblank = vs_dc_enable_vblank, ++ .commit = vs_dc_commit, ++}; ++ ++static const struct vs_plane_funcs dc_plane_funcs = { ++ .update = vs_dc_update_plane, ++ .disable = vs_dc_disable_plane, ++ .check = vs_dc_check_plane, ++}; ++ ++static int dc_bind(struct device *dev, struct device *master, void *data) ++{ ++ struct drm_device *drm_dev = data; ++ struct vs_dc *dc = dev_get_drvdata(dev); ++ struct device_node *port; ++ struct vs_crtc *crtc; ++ struct drm_crtc *drm_crtc; ++ struct vs_dc_info *dc_info; ++ struct vs_plane *plane; ++ struct drm_plane *drm_plane, *tmp; ++ struct vs_plane_info *plane_info; ++ int i, ret; ++ u32 ctrc_mask = 0; ++ ++ if (!drm_dev || !dc) { ++ dev_err(dev, "devices are not created.\n"); ++ return -ENODEV; ++ } ++ ++ ret = dc_init(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to initialize DC hardware.\n"); ++ return ret; ++ } ++ ++ port = of_get_child_by_name(dev->of_node, "port"); ++ if (!port) { ++ dev_err(dev, "no port node found\n"); ++ return -ENODEV; ++ } ++ of_node_put(port); ++ ++ dc_info = dc->hw.info; ++ ++ for (i = 0; i < dc_info->panel_num; i++) { ++ crtc = vs_crtc_create(drm_dev, dc_info); ++ if (!crtc) { ++ dev_err(dev, "Failed to create CRTC.\n"); ++ ret = -ENOMEM; ++ return ret; ++ } ++ ++ crtc->base.port = port; ++ crtc->dev = dev; ++ crtc->funcs = &dc_crtc_funcs; ++ dc->crtc[i] = crtc; ++ ctrc_mask |= drm_crtc_mask(&crtc->base); ++ } ++ ++ for (i = 0; i < dc_info->plane_num; i++) { ++ plane_info = (struct vs_plane_info *)&dc_info->planes[i]; ++ ++ if (!strcmp(plane_info->name, "Primary") || !strcmp(plane_info->name, "Cursor")) { ++ plane = vs_plane_create(drm_dev, plane_info, dc_info->layer_num, ++ drm_crtc_mask(&dc->crtc[0]->base)); ++ } else if (!strcmp(plane_info->name, "Primary_1") || ++ !strcmp(plane_info->name, "Cursor_1")) { ++ plane = vs_plane_create(drm_dev, plane_info, dc_info->layer_num, ++ drm_crtc_mask(&dc->crtc[1]->base)); ++ } else { ++ plane = vs_plane_create(drm_dev, plane_info, ++ dc_info->layer_num, ctrc_mask); ++ } ++ ++ if (!plane) ++ goto err_cleanup_planes; ++ ++ plane->id = i; ++ dc->planes[i].id = plane_info->id; ++ ++ plane->funcs = &dc_plane_funcs; ++ ++ if (plane_info->type == DRM_PLANE_TYPE_PRIMARY) { ++ if (!strcmp(plane_info->name, "Primary")) ++ dc->crtc[0]->base.primary = &plane->base; ++ else ++ dc->crtc[1]->base.primary = &plane->base; ++ drm_dev->mode_config.min_width = plane_info->min_width; ++ drm_dev->mode_config.min_height = ++ plane_info->min_height; ++ drm_dev->mode_config.max_width = plane_info->max_width; ++ drm_dev->mode_config.max_height = ++ plane_info->max_height; ++ } ++ ++ if (plane_info->type == DRM_PLANE_TYPE_CURSOR) { ++ if (!strcmp(plane_info->name, "Cursor")) ++ dc->crtc[0]->base.cursor = &plane->base; ++ else ++ dc->crtc[1]->base.cursor = &plane->base; ++ drm_dev->mode_config.cursor_width = ++ plane_info->max_width; ++ drm_dev->mode_config.cursor_height = ++ plane_info->max_height; ++ } ++ } ++ ++ vs_drm_update_pitch_alignment(drm_dev, dc_info->pitch_alignment); ++ ++ return 0; ++ ++err_cleanup_planes: ++ list_for_each_entry_safe(drm_plane, tmp, ++ &drm_dev->mode_config.plane_list, head) ++ if (drm_plane->possible_crtcs & ctrc_mask) ++ vs_plane_destory(drm_plane); ++ ++ drm_for_each_crtc(drm_crtc, drm_dev) ++ vs_crtc_destroy(drm_crtc); ++ ++ return ret; ++} ++ ++static void dc_unbind(struct device *dev, struct device *master, void *data) ++{ ++ dc_deinit(dev); ++} ++ ++const struct component_ops dc_component_ops = { ++ .bind = dc_bind, ++ .unbind = dc_unbind, ++}; ++ ++static const struct of_device_id dc_driver_dt_match[] = { ++ { .compatible = "verisilicon,dc8200", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, dc_driver_dt_match); ++ ++static int dc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vs_dc *dc; ++ int irq, ret, i; ++ ++ dc = devm_kzalloc(dev, sizeof(*dc), GFP_KERNEL); ++ if (!dc) ++ return -ENOMEM; ++ ++ dc->hw.hi_base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(dc->hw.hi_base)) ++ return PTR_ERR(dc->hw.hi_base); ++ ++ dc->hw.reg_base = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(dc->hw.reg_base)) ++ return PTR_ERR(dc->hw.reg_base); ++ ++ dc->dss_reg = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(dc->dss_reg)) ++ return PTR_ERR(dc->dss_reg); ++ ++ dc->nclks = ARRAY_SIZE(dc->clk_vout); ++ for (i = 0; i < dc->nclks; ++i) ++ dc->clk_vout[i].id = vout_clocks[i]; ++ ret = devm_clk_bulk_get(dev, dc->nclks, dc->clk_vout); ++ if (ret) { ++ dev_err(dev, "Failed to get clk controls\n"); ++ return ret; ++ } ++ ++ dc->nrsts = ARRAY_SIZE(dc->rst_vout); ++ for (i = 0; i < dc->nrsts; ++i) ++ dc->rst_vout[i].id = vout_resets[i]; ++ ret = devm_reset_control_bulk_get_shared(dev, dc->nrsts, ++ dc->rst_vout); ++ if (ret) { ++ dev_err(dev, "Failed to get reset controls\n"); ++ return ret; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ ++ ret = devm_request_irq(dev, irq, dc_isr, 0, dev_name(dev), dc); ++ if (ret < 0) { ++ dev_err(dev, "Failed to install irq:%u.\n", irq); ++ return ret; ++ } ++ ++ dev_set_drvdata(dev, dc); ++ ++ return component_add(dev, &dc_component_ops); ++} ++ ++static int dc_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ ++ component_del(dev, &dc_component_ops); ++ ++ dev_set_drvdata(dev, NULL); ++ ++ return 0; ++} ++ ++struct platform_driver dc_platform_driver = { ++ .probe = dc_probe, ++ .remove = dc_remove, ++ .driver = { ++ .name = "vs-dc", ++ .of_match_table = of_match_ptr(dc_driver_dt_match), ++ }, ++}; ++ ++MODULE_AUTHOR("StarFive Corporation"); ++MODULE_AUTHOR("Verisilicon Corporation"); ++MODULE_DESCRIPTION("VeriSilicon DC Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/verisilicon/vs_dc.h b/drivers/gpu/drm/verisilicon/vs_dc.h +new file mode 100644 +index 000000000000..ab76ac1e9943 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc.h +@@ -0,0 +1,62 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_DC_H__ ++#define __VS_DC_H__ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "vs_crtc.h" ++#include "vs_dc_hw.h" ++#include "vs_plane.h" ++ ++#define fourcc_mod_vs_get_type(val) \ ++ (((val) & DRM_FORMAT_MOD_VS_TYPE_MASK) >> 54) ++ ++struct vs_dc_plane { ++ enum dc_hw_plane_id id; ++}; ++ ++enum vout_clk { ++ CLK_VOUT_NOC_DISP = 0, ++ CLK_VOUT_PIX0, ++ CLK_VOUT_PIX1, ++ CLK_VOUT_AXI, ++ CLK_VOUT_CORE, ++ CLK_VOUT_AHB, ++ CLK_VOUT_HDMI_PIX, ++ CLK_VOUT_SOC_PIX, ++ CLK_VOUT_NUM ++}; ++ ++enum rst_vout { ++ RST_VOUT_AXI = 0, ++ RST_VOUT_AHB, ++ RST_VOUT_CORE, ++ RST_VOUT_NUM ++}; ++ ++struct vs_dc { ++ struct vs_crtc *crtc[DC_DISPLAY_NUM]; ++ struct dc_hw hw; ++ void __iomem *dss_reg; ++ bool first_frame; ++ ++ struct vs_dc_plane planes[PLANE_NUM]; ++ struct clk_bulk_data clk_vout[CLK_VOUT_NUM]; ++ int nclks; ++ struct reset_control_bulk_data rst_vout[RST_VOUT_NUM]; ++ int nrsts; ++}; ++ ++extern struct platform_driver dc_platform_driver; ++ ++#endif /* __VS_DC_H__ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.c b/drivers/gpu/drm/verisilicon/vs_dc_hw.c +new file mode 100644 +index 000000000000..d370dd401084 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.c +@@ -0,0 +1,2008 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vs_dc_hw.h" ++#include "vs_type.h" ++ ++static const u32 horkernel[] = { ++ 0x00000000, 0x20000000, 0x00002000, 0x00000000, ++ 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000, ++ 0x00000000, 0x00000000, 0x181f0000, 0x000027e1, ++ 0x00000000, 0x00000000, 0x00000000, 0x2b981468, ++ 0x00000000, 0x00000000, 0x00000000, 0x10f00000, ++ 0x00002f10, 0x00000000, 0x00000000, 0x00000000, ++ 0x32390dc7, 0x00000000, 0x00000000, 0x00000000, ++ 0x0af50000, 0x0000350b, 0x00000000, 0x00000000, ++ 0x00000000, 0x3781087f, 0x00000000, 0x00000000, ++ 0x00000000, 0x06660000, 0x0000399a, 0x00000000, ++ 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000, ++ 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4, ++ 0x00000000, 0x00000000, 0x00000000, 0x3de1021f, ++ 0x00000000, 0x00000000, 0x00000000, 0x01470000, ++ 0x00003eb9, 0x00000000, 0x00000000, 0x00000000, ++ 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000, ++ 0x00480000, 0x00003fb8, 0x00000000, 0x00000000, ++ 0x00000000, 0x3fef0011, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00004000, 0x00000000, ++ 0x00000000, 0x00000000, 0x20002000, 0x00000000, ++ 0x00000000, 0x00000000, 0x1c030000, 0x000023fd, ++ 0x00000000, 0x00000000, 0x00000000, 0x27e1181f, ++ 0x00000000, 0x00000000, 0x00000000, 0x14680000, ++ 0x00002b98, 0x00000000, 0x00000000, 0x00000000, ++ 0x2f1010f0, 0x00000000, 0x00000000, 0x00000000, ++ 0x0dc70000, 0x00003239, 0x00000000, 0x00000000, ++ 0x00000000, 0x350b0af5, 0x00000000, 0x00000000, ++ 0x00000000, 0x087f0000, 0x00003781, 0x00000000, ++ 0x00000000, 0x00000000, 0x399a0666, 0x00000000, ++ 0x00000000, 0x00000000, 0x04a70000, 0x00003b59, ++ 0x00000000, 0x00000000, 0x00000000, 0x3cc4033c, ++ 0x00000000, 0x00000000, 0x00000000, 0x021f0000, ++}; ++ ++#define H_COEF_SIZE (sizeof(horkernel) / sizeof(u32)) ++ ++static const u32 verkernel[] = { ++ 0x00000000, 0x20000000, 0x00002000, 0x00000000, ++ 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000, ++ 0x00000000, 0x00000000, 0x181f0000, 0x000027e1, ++ 0x00000000, 0x00000000, 0x00000000, 0x2b981468, ++ 0x00000000, 0x00000000, 0x00000000, 0x10f00000, ++ 0x00002f10, 0x00000000, 0x00000000, 0x00000000, ++ 0x32390dc7, 0x00000000, 0x00000000, 0x00000000, ++ 0x0af50000, 0x0000350b, 0x00000000, 0x00000000, ++ 0x00000000, 0x3781087f, 0x00000000, 0x00000000, ++ 0x00000000, 0x06660000, 0x0000399a, 0x00000000, ++ 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000, ++ 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4, ++ 0x00000000, 0x00000000, 0x00000000, 0x3de1021f, ++ 0x00000000, 0x00000000, 0x00000000, 0x01470000, ++ 0x00003eb9, 0x00000000, 0x00000000, 0x00000000, ++ 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000, ++ 0x00480000, 0x00003fb8, 0x00000000, 0x00000000, ++ 0x00000000, 0x3fef0011, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00004000, 0x00000000, ++ 0xcdcd0000, 0xfdfdfdfd, 0xabababab, 0xabababab, ++ 0x00000000, 0x00000000, 0x5ff5f456, 0x000f5f58, ++ 0x02cc6c78, 0x02cc0c28, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, ++}; ++ ++#define V_COEF_SIZE (sizeof(verkernel) / sizeof(u32)) ++ ++/* ++ * RGB 709->2020 conversion parameters ++ */ ++static u16 RGB2RGB[RGB_TO_RGB_TABLE_SIZE] = { ++ 10279, 5395, 709, ++ 1132, 15065, 187, ++ 269, 1442, 14674 ++}; ++ ++/* ++ * YUV601 to RGB conversion parameters ++ * YUV2RGB[0] - [8] : C0 - C8; ++ * YUV2RGB[9] - [11]: D0 - D2; ++ * YUV2RGB[12] - [13]: Y clamp min & max calue; ++ * YUV2RGB[14] - [15]: UV clamp min & max calue; ++ */ ++static s32 YUV601_2RGB[YUV_TO_RGB_TABLE_SIZE] = { ++ 1196, 0, 1640, 1196, ++ -404, -836, 1196, 2076, ++ 0, -916224, 558336, -1202944, ++ 64, 940, 64, 960 ++}; ++ ++/* ++ * YUV709 to RGB conversion parameters ++ * YUV2RGB[0] - [8] : C0 - C8; ++ * YUV2RGB[9] - [11]: D0 - D2; ++ * YUV2RGB[12] - [13]: Y clamp min & max calue; ++ * YUV2RGB[14] - [15]: UV clamp min & max calue; ++ */ ++static s32 YUV709_2RGB[YUV_TO_RGB_TABLE_SIZE] = { ++ 1196, 0, 1844, 1196, ++ -220, -548, 1196, 2172, ++ 0, -1020672, 316672, -1188608, ++ 64, 940, 64, 960 ++}; ++ ++/* ++ * YUV2020 to RGB conversion parameters ++ * YUV2RGB[0] - [8] : C0 - C8; ++ * YUV2RGB[9] - [11]: D0 - D2; ++ * YUV2RGB[12] - [13]: Y clamp min & max calue; ++ * YUV2RGB[14] - [15]: UV clamp min & max calue; ++ */ ++static s32 YUV2020_2RGB[YUV_TO_RGB_TABLE_SIZE] = { ++ 1196, 0, 1724, 1196, ++ -192, -668, 1196, 2200, ++ 0, -959232, 363776, -1202944, ++ 64, 940, 64, 960 ++}; ++ ++/* ++ * RGB to YUV2020 conversion parameters ++ * RGB2YUV[0] - [8] : C0 - C8; ++ * RGB2YUV[9] - [11]: D0 - D2; ++ */ ++static s16 RGB2YUV[RGB_TO_YUV_TABLE_SIZE] = { ++ 230, 594, 52, ++ -125, -323, 448, ++ 448, -412, -36, ++ 64, 512, 512 ++}; ++ ++/* ++ * Degamma table for 709 color space data. ++ */ ++static u16 DEGAMMA_709[DEGAMMA_SIZE] = { ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0005, ++ 0x0007, 0x000a, 0x000d, 0x0011, 0x0015, 0x0019, 0x001e, 0x0024, ++ 0x002a, 0x0030, 0x0038, 0x003f, 0x0048, 0x0051, 0x005a, 0x0064, ++ 0x006f, 0x007b, 0x0087, 0x0094, 0x00a1, 0x00af, 0x00be, 0x00ce, ++ 0x00de, 0x00ef, 0x0101, 0x0114, 0x0127, 0x013b, 0x0150, 0x0166, ++ 0x017c, 0x0193, 0x01ac, 0x01c4, 0x01de, 0x01f9, 0x0214, 0x0230, ++ 0x024d, 0x026b, 0x028a, 0x02aa, 0x02ca, 0x02ec, 0x030e, 0x0331, ++ 0x0355, 0x037a, 0x03a0, 0x03c7, 0x03ef, 0x0418, 0x0441, 0x046c, ++ 0x0498, 0x04c4, 0x04f2, 0x0520, 0x0550, 0x0581, 0x05b2, 0x05e5, ++ 0x0618, 0x064d, 0x0682, 0x06b9, 0x06f0, 0x0729, 0x0763, 0x079d, ++ 0x07d9, 0x0816, 0x0854, 0x0893, 0x08d3, 0x0914, 0x0956, 0x0999, ++ 0x09dd, 0x0a23, 0x0a69, 0x0ab1, 0x0afa, 0x0b44, 0x0b8f, 0x0bdb, ++ 0x0c28, 0x0c76, 0x0cc6, 0x0d17, 0x0d69, 0x0dbb, 0x0e10, 0x0e65, ++ 0x0ebb, 0x0f13, 0x0f6c, 0x0fc6, 0x1021, 0x107d, 0x10db, 0x113a, ++ 0x119a, 0x11fb, 0x125d, 0x12c1, 0x1325, 0x138c, 0x13f3, 0x145b, ++ 0x14c5, 0x1530, 0x159c, 0x160a, 0x1678, 0x16e8, 0x175a, 0x17cc, ++ 0x1840, 0x18b5, 0x192b, 0x19a3, 0x1a1c, 0x1a96, 0x1b11, 0x1b8e, ++ 0x1c0c, 0x1c8c, 0x1d0c, 0x1d8e, 0x1e12, 0x1e96, 0x1f1c, 0x1fa3, ++ 0x202c, 0x20b6, 0x2141, 0x21ce, 0x225c, 0x22eb, 0x237c, 0x240e, ++ 0x24a1, 0x2536, 0x25cc, 0x2664, 0x26fc, 0x2797, 0x2832, 0x28cf, ++ 0x296e, 0x2a0e, 0x2aaf, 0x2b51, 0x2bf5, 0x2c9b, 0x2d41, 0x2dea, ++ 0x2e93, 0x2f3e, 0x2feb, 0x3099, 0x3148, 0x31f9, 0x32ab, 0x335f, ++ 0x3414, 0x34ca, 0x3582, 0x363c, 0x36f7, 0x37b3, 0x3871, 0x3930, ++ 0x39f1, 0x3ab3, 0x3b77, 0x3c3c, 0x3d02, 0x3dcb, 0x3e94, 0x3f5f, ++ 0x402c, 0x40fa, 0x41ca, 0x429b, 0x436d, 0x4442, 0x4517, 0x45ee, ++ 0x46c7, 0x47a1, 0x487d, 0x495a, 0x4a39, 0x4b19, 0x4bfb, 0x4cde, ++ 0x4dc3, 0x4eaa, 0x4f92, 0x507c, 0x5167, 0x5253, 0x5342, 0x5431, ++ 0x5523, 0x5616, 0x570a, 0x5800, 0x58f8, 0x59f1, 0x5aec, 0x5be9, ++ 0x5ce7, 0x5de6, 0x5ee7, 0x5fea, 0x60ef, 0x61f5, 0x62fc, 0x6406, ++ 0x6510, 0x661d, 0x672b, 0x683b, 0x694c, 0x6a5f, 0x6b73, 0x6c8a, ++ 0x6da2, 0x6ebb, 0x6fd6, 0x70f3, 0x7211, 0x7331, 0x7453, 0x7576, ++ 0x769b, 0x77c2, 0x78ea, 0x7a14, 0x7b40, 0x7c6d, 0x7d9c, 0x7ecd, ++ 0x3f65, 0x3f8c, 0x3fb2, 0x3fd8 ++}; ++ ++/* ++ * Degamma table for 2020 color space data. ++ */ ++static u16 DEGAMMA_2020[DEGAMMA_SIZE] = { ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, ++ 0x0000, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, ++ 0x0001, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0003, 0x0003, ++ 0x0003, 0x0003, 0x0004, 0x0004, 0x0004, 0x0005, 0x0005, 0x0006, ++ 0x0006, 0x0006, 0x0007, 0x0007, 0x0008, 0x0008, 0x0009, 0x000a, ++ 0x000a, 0x000b, 0x000c, 0x000c, 0x000d, 0x000e, 0x000f, 0x000f, ++ 0x0010, 0x0011, 0x0012, 0x0013, 0x0014, 0x0016, 0x0017, 0x0018, ++ 0x0019, 0x001b, 0x001c, 0x001e, 0x001f, 0x0021, 0x0022, 0x0024, ++ 0x0026, 0x0028, 0x002a, 0x002c, 0x002e, 0x0030, 0x0033, 0x0035, ++ 0x0038, 0x003a, 0x003d, 0x0040, 0x0043, 0x0046, 0x0049, 0x004d, ++ 0x0050, 0x0054, 0x0057, 0x005b, 0x005f, 0x0064, 0x0068, 0x006d, ++ 0x0071, 0x0076, 0x007c, 0x0081, 0x0086, 0x008c, 0x0092, 0x0098, ++ 0x009f, 0x00a5, 0x00ac, 0x00b4, 0x00bb, 0x00c3, 0x00cb, 0x00d3, ++ 0x00dc, 0x00e5, 0x00ee, 0x00f8, 0x0102, 0x010c, 0x0117, 0x0123, ++ 0x012e, 0x013a, 0x0147, 0x0154, 0x0161, 0x016f, 0x017e, 0x018d, ++ 0x019c, 0x01ac, 0x01bd, 0x01ce, 0x01e0, 0x01f3, 0x0206, 0x021a, ++ 0x022f, 0x0244, 0x025a, 0x0272, 0x0289, 0x02a2, 0x02bc, 0x02d6, ++ 0x02f2, 0x030f, 0x032c, 0x034b, 0x036b, 0x038b, 0x03ae, 0x03d1, ++ 0x03f5, 0x041b, 0x0443, 0x046b, 0x0495, 0x04c1, 0x04ee, 0x051d, ++ 0x054e, 0x0580, 0x05b4, 0x05ea, 0x0622, 0x065c, 0x0698, 0x06d6, ++ 0x0717, 0x075a, 0x079f, 0x07e7, 0x0831, 0x087e, 0x08cd, 0x0920, ++ 0x0976, 0x09ce, 0x0a2a, 0x0a89, 0x0aec, 0x0b52, 0x0bbc, 0x0c2a, ++ 0x0c9b, 0x0d11, 0x0d8b, 0x0e0a, 0x0e8d, 0x0f15, 0x0fa1, 0x1033, ++ 0x10ca, 0x1167, 0x120a, 0x12b2, 0x1360, 0x1415, 0x14d1, 0x1593, ++ 0x165d, 0x172e, 0x1806, 0x18e7, 0x19d0, 0x1ac1, 0x1bbb, 0x1cbf, ++ 0x1dcc, 0x1ee3, 0x2005, 0x2131, 0x2268, 0x23ab, 0x24fa, 0x2656, ++ 0x27be, 0x2934, 0x2ab8, 0x2c4a, 0x2dec, 0x2f9d, 0x315f, 0x3332, ++ 0x3516, 0x370d, 0x3916, 0x3b34, 0x3d66, 0x3fad, 0x420b, 0x4480, ++ 0x470d, 0x49b3, 0x4c73, 0x4f4e, 0x5246, 0x555a, 0x588e, 0x5be1, ++ 0x5f55, 0x62eb, 0x66a6, 0x6a86, 0x6e8c, 0x72bb, 0x7714, 0x7b99, ++ 0x3dcb, 0x3e60, 0x3ef5, 0x3f8c ++}; ++ ++/* one is for primary plane and the other is for all overlay planes */ ++static const struct dc_hw_plane_reg dc_plane_reg[] = { ++ { ++ .y_address = DC_FRAMEBUFFER_ADDRESS, ++ .u_address = DC_FRAMEBUFFER_U_ADDRESS, ++ .v_address = DC_FRAMEBUFFER_V_ADDRESS, ++ .y_stride = DC_FRAMEBUFFER_STRIDE, ++ .u_stride = DC_FRAMEBUFFER_U_STRIDE, ++ .v_stride = DC_FRAMEBUFFER_V_STRIDE, ++ .size = DC_FRAMEBUFFER_SIZE, ++ .top_left = DC_FRAMEBUFFER_TOP_LEFT, ++ .bottom_right = DC_FRAMEBUFFER_BOTTOM_RIGHT, ++ .scale_factor_x = DC_FRAMEBUFFER_SCALE_FACTOR_X, ++ .scale_factor_y = DC_FRAMEBUFFER_SCALE_FACTOR_Y, ++ .h_filter_coef_index = DC_FRAMEBUFFER_H_FILTER_COEF_INDEX, ++ .h_filter_coef_data = DC_FRAMEBUFFER_H_FILTER_COEF_DATA, ++ .v_filter_coef_index = DC_FRAMEBUFFER_V_FILTER_COEF_INDEX, ++ .v_filter_coef_data = DC_FRAMEBUFFER_V_FILTER_COEF_DATA, ++ .init_offset = DC_FRAMEBUFFER_INIT_OFFSET, ++ .color_key = DC_FRAMEBUFFER_COLOR_KEY, ++ .color_key_high = DC_FRAMEBUFFER_COLOR_KEY_HIGH, ++ .clear_value = DC_FRAMEBUFFER_CLEAR_VALUE, ++ .color_table_index = DC_FRAMEBUFFER_COLOR_TABLE_INDEX, ++ .color_table_data = DC_FRAMEBUFFER_COLOR_TABLE_DATA, ++ .scale_config = DC_FRAMEBUFFER_SCALE_CONFIG, ++ .water_mark = DC_FRAMEBUFFER_WATER_MARK, ++ .degamma_index = DC_FRAMEBUFFER_DEGAMMA_INDEX, ++ .degamma_data = DC_FRAMEBUFFER_DEGAMMA_DATA, ++ .degamma_ex_data = DC_FRAMEBUFFER_DEGAMMA_EX_DATA, ++ .src_global_color = DC_FRAMEBUFFER_SRC_GLOBAL_COLOR, ++ .dst_global_color = DC_FRAMEBUFFER_DST_GLOBAL_COLOR, ++ .blend_config = DC_FRAMEBUFFER_BLEND_CONFIG, ++ .roi_origin = DC_FRAMEBUFFER_ROI_ORIGIN, ++ .roi_size = DC_FRAMEBUFFER_ROI_SIZE, ++ .yuv_to_rgb_coef0 = DC_FRAMEBUFFER_YUVTORGB_COEF0, ++ .yuv_to_rgb_coef1 = DC_FRAMEBUFFER_YUVTORGB_COEF1, ++ .yuv_to_rgb_coef2 = DC_FRAMEBUFFER_YUVTORGB_COEF2, ++ .yuv_to_rgb_coef3 = DC_FRAMEBUFFER_YUVTORGB_COEF3, ++ .yuv_to_rgb_coef4 = DC_FRAMEBUFFER_YUVTORGB_COEF4, ++ .yuv_to_rgb_coefd0 = DC_FRAMEBUFFER_YUVTORGB_COEFD0, ++ .yuv_to_rgb_coefd1 = DC_FRAMEBUFFER_YUVTORGB_COEFD1, ++ .yuv_to_rgb_coefd2 = DC_FRAMEBUFFER_YUVTORGB_COEFD2, ++ .y_clamp_bound = DC_FRAMEBUFFER_Y_CLAMP_BOUND, ++ .uv_clamp_bound = DC_FRAMEBUFFER_UV_CLAMP_BOUND, ++ .rgb_to_rgb_coef0 = DC_FRAMEBUFFER_RGBTORGB_COEF0, ++ .rgb_to_rgb_coef1 = DC_FRAMEBUFFER_RGBTORGB_COEF1, ++ .rgb_to_rgb_coef2 = DC_FRAMEBUFFER_RGBTORGB_COEF2, ++ .rgb_to_rgb_coef3 = DC_FRAMEBUFFER_RGBTORGB_COEF3, ++ .rgb_to_rgb_coef4 = DC_FRAMEBUFFER_RGBTORGB_COEF4, ++ }, ++ { ++ .y_address = DC_OVERLAY_ADDRESS, ++ .u_address = DC_OVERLAY_U_ADDRESS, ++ .v_address = DC_OVERLAY_V_ADDRESS, ++ .y_stride = DC_OVERLAY_STRIDE, ++ .u_stride = DC_OVERLAY_U_STRIDE, ++ .v_stride = DC_OVERLAY_V_STRIDE, ++ .size = DC_OVERLAY_SIZE, ++ .top_left = DC_OVERLAY_TOP_LEFT, ++ .bottom_right = DC_OVERLAY_BOTTOM_RIGHT, ++ .scale_factor_x = DC_OVERLAY_SCALE_FACTOR_X, ++ .scale_factor_y = DC_OVERLAY_SCALE_FACTOR_Y, ++ .h_filter_coef_index = DC_OVERLAY_H_FILTER_COEF_INDEX, ++ .h_filter_coef_data = DC_OVERLAY_H_FILTER_COEF_DATA, ++ .v_filter_coef_index = DC_OVERLAY_V_FILTER_COEF_INDEX, ++ .v_filter_coef_data = DC_OVERLAY_V_FILTER_COEF_DATA, ++ .init_offset = DC_OVERLAY_INIT_OFFSET, ++ .color_key = DC_OVERLAY_COLOR_KEY, ++ .color_key_high = DC_OVERLAY_COLOR_KEY_HIGH, ++ .clear_value = DC_OVERLAY_CLEAR_VALUE, ++ .color_table_index = DC_OVERLAY_COLOR_TABLE_INDEX, ++ .color_table_data = DC_OVERLAY_COLOR_TABLE_DATA, ++ .scale_config = DC_OVERLAY_SCALE_CONFIG, ++ .water_mark = DC_OVERLAY_WATER_MARK, ++ .degamma_index = DC_OVERLAY_DEGAMMA_INDEX, ++ .degamma_data = DC_OVERLAY_DEGAMMA_DATA, ++ .degamma_ex_data = DC_OVERLAY_DEGAMMA_EX_DATA, ++ .src_global_color = DC_OVERLAY_SRC_GLOBAL_COLOR, ++ .dst_global_color = DC_OVERLAY_DST_GLOBAL_COLOR, ++ .blend_config = DC_OVERLAY_BLEND_CONFIG, ++ .roi_origin = DC_OVERLAY_ROI_ORIGIN, ++ .roi_size = DC_OVERLAY_ROI_SIZE, ++ .yuv_to_rgb_coef0 = DC_OVERLAY_YUVTORGB_COEF0, ++ .yuv_to_rgb_coef1 = DC_OVERLAY_YUVTORGB_COEF1, ++ .yuv_to_rgb_coef2 = DC_OVERLAY_YUVTORGB_COEF2, ++ .yuv_to_rgb_coef3 = DC_OVERLAY_YUVTORGB_COEF3, ++ .yuv_to_rgb_coef4 = DC_OVERLAY_YUVTORGB_COEF4, ++ .yuv_to_rgb_coefd0 = DC_OVERLAY_YUVTORGB_COEFD0, ++ .yuv_to_rgb_coefd1 = DC_OVERLAY_YUVTORGB_COEFD1, ++ .yuv_to_rgb_coefd2 = DC_OVERLAY_YUVTORGB_COEFD2, ++ .y_clamp_bound = DC_OVERLAY_Y_CLAMP_BOUND, ++ .uv_clamp_bound = DC_OVERLAY_UV_CLAMP_BOUND, ++ .rgb_to_rgb_coef0 = DC_OVERLAY_RGBTORGB_COEF0, ++ .rgb_to_rgb_coef1 = DC_OVERLAY_RGBTORGB_COEF1, ++ .rgb_to_rgb_coef2 = DC_OVERLAY_RGBTORGB_COEF2, ++ .rgb_to_rgb_coef3 = DC_OVERLAY_RGBTORGB_COEF3, ++ .rgb_to_rgb_coef4 = DC_OVERLAY_RGBTORGB_COEF4, ++ }, ++}; ++ ++static const u32 primary_overlay_format0[] = { ++ DRM_FORMAT_XRGB4444, ++ DRM_FORMAT_XBGR4444, ++ DRM_FORMAT_RGBX4444, ++ DRM_FORMAT_BGRX4444, ++ DRM_FORMAT_ARGB4444, ++ DRM_FORMAT_ABGR4444, ++ DRM_FORMAT_RGBA4444, ++ DRM_FORMAT_BGRA4444, ++ DRM_FORMAT_XRGB1555, ++ DRM_FORMAT_XBGR1555, ++ DRM_FORMAT_RGBX5551, ++ DRM_FORMAT_BGRX5551, ++ DRM_FORMAT_ARGB1555, ++ DRM_FORMAT_ABGR1555, ++ DRM_FORMAT_RGBA5551, ++ DRM_FORMAT_BGRA5551, ++ DRM_FORMAT_RGB565, ++ DRM_FORMAT_BGR565, ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ DRM_FORMAT_YUYV, ++ DRM_FORMAT_YVYU, ++ DRM_FORMAT_UYVY, ++ DRM_FORMAT_VYUY, ++ DRM_FORMAT_YVU420, ++ DRM_FORMAT_YUV420, ++ DRM_FORMAT_NV12, ++ DRM_FORMAT_NV21, ++ DRM_FORMAT_NV16, ++ DRM_FORMAT_NV61, ++ DRM_FORMAT_P010, ++}; ++ ++static const u32 primary_overlay_format1[] = { ++ DRM_FORMAT_XRGB8888, ++ DRM_FORMAT_XBGR8888, ++ DRM_FORMAT_RGBX8888, ++ DRM_FORMAT_BGRX8888, ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGBA8888, ++ DRM_FORMAT_BGRA8888, ++ DRM_FORMAT_ARGB2101010, ++ DRM_FORMAT_ABGR2101010, ++ DRM_FORMAT_RGBA1010102, ++ DRM_FORMAT_BGRA1010102, ++ DRM_FORMAT_NV12, ++ DRM_FORMAT_NV21, ++ DRM_FORMAT_YUV444, ++}; ++ ++static const u32 cursor_formats[] = { ++ DRM_FORMAT_ARGB8888 ++}; ++ ++static const u64 format_modifier0[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_LINEAR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X8), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X4), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR_8X4), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR_4X8), ++ DRM_FORMAT_MOD_INVALID ++}; ++ ++static const u64 format_modifier1[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_LINEAR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X8), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_8X4), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_XMAJOR_8X4), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_SUPER_TILED_YMAJOR_4X8), ++ fourcc_mod_vs_norm_code(DRM_FORMAT_MOD_VS_TILE_MODE4X4), ++ fourcc_mod_vs_custom_code(DRM_FORMAT_MOD_VS_TILE_MODE4X4), ++ DRM_FORMAT_MOD_INVALID ++}; ++ ++static const u64 secondary_format_modifiers[] = { ++ DRM_FORMAT_MOD_LINEAR, ++ DRM_FORMAT_MOD_INVALID ++}; ++ ++#define FRAC_16_16(mult, div) (((mult) << 16) / (div)) ++ ++static const struct vs_plane_info dc_hw_planes[][PLANE_NUM] = { ++ { ++ /* DC_REV_0 */ ++ { ++ .name = "Primary", ++ .id = PRIMARY_PLANE_0, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 0, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay", ++ .id = OVERLAY_PLANE_0, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 1, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_1", ++ .id = OVERLAY_PLANE_1, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(secondary_format_modifiers), ++ .modifiers = secondary_format_modifiers, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = 0, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 2, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Primary_1", ++ .id = PRIMARY_PLANE_1, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 3, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_2", ++ .id = OVERLAY_PLANE_2, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 4, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_3", ++ .id = OVERLAY_PLANE_3, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(secondary_format_modifiers), ++ .modifiers = secondary_format_modifiers, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = 0, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 5, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Cursor", ++ .id = CURSOR_PLANE_0, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ { ++ .name = "Cursor_1", ++ .id = CURSOR_PLANE_1, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ }, ++ { ++ /* DC_REV_1 */ ++ { ++ .name = "Primary", ++ .id = PRIMARY_PLANE_0, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 0, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay", ++ .id = OVERLAY_PLANE_0, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 1, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Primary_1", ++ .id = PRIMARY_PLANE_1, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 2, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_2", ++ .id = OVERLAY_PLANE_2, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format0), ++ .formats = primary_overlay_format0, ++ .num_modifiers = ARRAY_SIZE(format_modifier0), ++ .modifiers = format_modifier0, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 3, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Cursor", ++ .id = CURSOR_PLANE_0, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ { ++ .name = "Cursor_1", ++ .id = CURSOR_PLANE_1, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ }, ++ { ++ /* DC_REV_2 */ ++ { ++ .name = "Primary", ++ .id = PRIMARY_PLANE_0, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(format_modifier1), ++ .modifiers = format_modifier1, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 0, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay", ++ .id = OVERLAY_PLANE_0, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(format_modifier1), ++ .modifiers = format_modifier1, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 1, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_1", ++ .id = OVERLAY_PLANE_1, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(secondary_format_modifiers), ++ .modifiers = secondary_format_modifiers, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = 0, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 2, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Primary_1", ++ .id = PRIMARY_PLANE_1, ++ .type = DRM_PLANE_TYPE_PRIMARY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(format_modifier1), ++ .modifiers = format_modifier1, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 3, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_2", ++ .id = OVERLAY_PLANE_2, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(format_modifier1), ++ .modifiers = format_modifier1, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = DRM_MODE_ROTATE_0 | ++ DRM_MODE_ROTATE_90 | ++ DRM_MODE_ROTATE_180 | ++ DRM_MODE_ROTATE_270 | ++ DRM_MODE_REFLECT_X | ++ DRM_MODE_REFLECT_Y, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = FRAC_16_16(1, 3), ++ .max_scale = FRAC_16_16(10, 1), ++ .zpos = 4, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Overlay_3", ++ .id = OVERLAY_PLANE_3, ++ .type = DRM_PLANE_TYPE_OVERLAY, ++ .num_formats = ARRAY_SIZE(primary_overlay_format1), ++ .formats = primary_overlay_format1, ++ .num_modifiers = ARRAY_SIZE(secondary_format_modifiers), ++ .modifiers = secondary_format_modifiers, ++ .min_width = 0, ++ .min_height = 0, ++ .max_width = 4096, ++ .max_height = 4096, ++ .rotation = 0, ++ .blend_mode = BIT(DRM_MODE_BLEND_PIXEL_NONE) | ++ BIT(DRM_MODE_BLEND_PREMULTI) | ++ BIT(DRM_MODE_BLEND_COVERAGE), ++ .color_encoding = BIT(DRM_COLOR_YCBCR_BT709) | ++ BIT(DRM_COLOR_YCBCR_BT2020), ++ .degamma_size = DEGAMMA_SIZE, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 5, ++ .watermark = true, ++ .color_mgmt = true, ++ .roi = true, ++ }, ++ { ++ .name = "Cursor", ++ .id = CURSOR_PLANE_0, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ { ++ .name = "Cursor_1", ++ .id = CURSOR_PLANE_1, ++ .type = DRM_PLANE_TYPE_CURSOR, ++ .num_formats = ARRAY_SIZE(cursor_formats), ++ .formats = cursor_formats, ++ .num_modifiers = 0, ++ .modifiers = NULL, ++ .min_width = 32, ++ .min_height = 32, ++ .max_width = 64, ++ .max_height = 64, ++ .rotation = 0, ++ .degamma_size = 0, ++ .min_scale = DRM_PLANE_NO_SCALING, ++ .max_scale = DRM_PLANE_NO_SCALING, ++ .zpos = 255, ++ .watermark = false, ++ .color_mgmt = false, ++ .roi = false, ++ }, ++ }, ++}; ++ ++static const struct vs_dc_info dc_info[] = { ++ { ++ /* DC_REV_0 */ ++ .name = "DC8200", ++ .panel_num = 2, ++ .plane_num = 8, ++ .planes = dc_hw_planes[DC_REV_0], ++ .layer_num = 6, ++ .max_bpc = 10, ++ .color_formats = DRM_COLOR_FORMAT_RGB444 | ++ DRM_COLOR_FORMAT_YCBCR444 | ++ DRM_COLOR_FORMAT_YCBCR422 | ++ DRM_COLOR_FORMAT_YCBCR420, ++ .gamma_size = GAMMA_EX_SIZE, ++ .gamma_bits = 12, ++ .pitch_alignment = 128, ++ .pipe_sync = false, ++ .mmu_prefetch = false, ++ .background = true, ++ .panel_sync = true, ++ .cap_dec = true, ++ }, ++ { ++ /* DC_REV_1 */ ++ .name = "DC8200", ++ .panel_num = 2, ++ .plane_num = 6, ++ .planes = dc_hw_planes[DC_REV_1], ++ .layer_num = 4, ++ .max_bpc = 10, ++ .color_formats = DRM_COLOR_FORMAT_RGB444 | ++ DRM_COLOR_FORMAT_YCBCR444 | ++ DRM_COLOR_FORMAT_YCBCR422 | ++ DRM_COLOR_FORMAT_YCBCR420, ++ .gamma_size = GAMMA_EX_SIZE, ++ .gamma_bits = 12, ++ .pitch_alignment = 128, ++ .pipe_sync = false, ++ .mmu_prefetch = false, ++ .background = true, ++ .panel_sync = true, ++ .cap_dec = true, ++ }, ++ { ++ /* DC_REV_2 */ ++ .name = "DC8200", ++ .panel_num = 2, ++ .plane_num = 8, ++ .planes = dc_hw_planes[DC_REV_2], ++ .layer_num = 6, ++ .max_bpc = 10, ++ .color_formats = DRM_COLOR_FORMAT_RGB444 | ++ DRM_COLOR_FORMAT_YCBCR444 | ++ DRM_COLOR_FORMAT_YCBCR422 | ++ DRM_COLOR_FORMAT_YCBCR420, ++ .gamma_size = GAMMA_EX_SIZE, ++ .gamma_bits = 12, ++ .pitch_alignment = 128, ++ .pipe_sync = false, ++ .mmu_prefetch = false, ++ .background = true, ++ .panel_sync = true, ++ .cap_dec = false, ++ }, ++}; ++ ++static const struct dc_hw_funcs hw_func; ++ ++static inline u32 hi_read(struct dc_hw *hw, u32 reg) ++{ ++ return readl(hw->hi_base + reg); ++} ++ ++static inline void hi_write(struct dc_hw *hw, u32 reg, u32 value) ++{ ++ writel(value, hw->hi_base + reg); ++} ++ ++static inline void dc_write(struct dc_hw *hw, u32 reg, u32 value) ++{ ++ writel(value, hw->reg_base + reg - DC_REG_BASE); ++} ++ ++static inline u32 dc_read(struct dc_hw *hw, u32 reg) ++{ ++ u32 value = readl(hw->reg_base + reg - DC_REG_BASE); ++ ++ return value; ++} ++ ++static inline void dc_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32 clear) ++{ ++ u32 value = dc_read(hw, reg); ++ ++ value &= ~clear; ++ value |= set; ++ dc_write(hw, reg, value); ++} ++ ++static void load_default_filter(struct dc_hw *hw, ++ const struct dc_hw_plane_reg *reg, u32 offset) ++{ ++ u8 i; ++ ++ dc_write(hw, reg->scale_config + offset, 0x33); ++ dc_write(hw, reg->init_offset + offset, 0x80008000); ++ dc_write(hw, reg->h_filter_coef_index + offset, 0x00); ++ for (i = 0; i < H_COEF_SIZE; i++) ++ dc_write(hw, reg->h_filter_coef_data + offset, horkernel[i]); ++ ++ dc_write(hw, reg->v_filter_coef_index + offset, 0x00); ++ for (i = 0; i < V_COEF_SIZE; i++) ++ dc_write(hw, reg->v_filter_coef_data + offset, verkernel[i]); ++} ++ ++static void load_rgb_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg, ++ u32 offset, u16 *table) ++{ ++ dc_write(hw, reg->rgb_to_rgb_coef0 + offset, table[0] | (table[1] << 16)); ++ dc_write(hw, reg->rgb_to_rgb_coef1 + offset, table[2] | (table[3] << 16)); ++ dc_write(hw, reg->rgb_to_rgb_coef2 + offset, table[4] | (table[5] << 16)); ++ dc_write(hw, reg->rgb_to_rgb_coef3 + offset, table[6] | (table[7] << 16)); ++ dc_write(hw, reg->rgb_to_rgb_coef4 + offset, table[8]); ++} ++ ++static void load_yuv_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg, ++ u32 offset, s32 *table) ++{ ++ dc_write(hw, reg->yuv_to_rgb_coef0 + offset, ++ (0xFFFF & table[0]) | (table[1] << 16)); ++ dc_write(hw, reg->yuv_to_rgb_coef1 + offset, ++ (0xFFFF & table[2]) | (table[3] << 16)); ++ dc_write(hw, reg->yuv_to_rgb_coef2 + offset, ++ (0xFFFF & table[4]) | (table[5] << 16)); ++ dc_write(hw, reg->yuv_to_rgb_coef3 + offset, ++ (0xFFFF & table[6]) | (table[7] << 16)); ++ dc_write(hw, reg->yuv_to_rgb_coef4 + offset, table[8]); ++ dc_write(hw, reg->yuv_to_rgb_coefd0 + offset, table[9]); ++ dc_write(hw, reg->yuv_to_rgb_coefd1 + offset, table[10]); ++ dc_write(hw, reg->yuv_to_rgb_coefd2 + offset, table[11]); ++ dc_write(hw, reg->y_clamp_bound + offset, table[12] | (table[13] << 16)); ++ dc_write(hw, reg->uv_clamp_bound + offset, table[14] | (table[15] << 16)); ++} ++ ++static void load_rgb_to_yuv(struct dc_hw *hw, u32 offset, s16 *table) ++{ ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF0 + offset, ++ table[0] | (table[1] << 16)); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF1 + offset, ++ table[2] | (table[3] << 16)); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF2 + offset, ++ table[4] | (table[5] << 16)); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF3 + offset, ++ table[6] | (table[7] << 16)); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF4 + offset, table[8]); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD0 + offset, table[9]); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD1 + offset, table[10]); ++ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD2 + offset, table[11]); ++} ++ ++static bool is_rgb(enum dc_hw_color_format format) ++{ ++ switch (format) { ++ case FORMAT_X4R4G4B4: ++ case FORMAT_A4R4G4B4: ++ case FORMAT_X1R5G5B5: ++ case FORMAT_A1R5G5B5: ++ case FORMAT_R5G6B5: ++ case FORMAT_X8R8G8B8: ++ case FORMAT_A8R8G8B8: ++ case FORMAT_A2R10G10B10: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static void load_degamma_table(struct dc_hw *hw, ++ const struct dc_hw_plane_reg *reg, ++ u32 offset, u16 *table) ++{ ++ u16 i; ++ u32 value; ++ ++ dc_write(hw, reg->degamma_index + offset, 0); ++ ++ for (i = 0; i < DEGAMMA_SIZE; i++) { ++ value = table[i] | (table[i] << 16); ++ dc_write(hw, reg->degamma_data + offset, value); ++ dc_write(hw, reg->degamma_ex_data + offset, table[i]); ++ } ++} ++ ++static u32 get_addr_offset(u32 id) ++{ ++ u32 offset = 0; ++ ++ switch (id) { ++ case PRIMARY_PLANE_1: ++ case OVERLAY_PLANE_1: ++ offset = 0x04; ++ break; ++ case OVERLAY_PLANE_2: ++ offset = 0x08; ++ break; ++ case OVERLAY_PLANE_3: ++ offset = 0x0C; ++ break; ++ default: ++ break; ++ } ++ ++ return offset; ++} ++ ++int dc_hw_init(struct dc_hw *hw) ++{ ++ u8 i, id, panel_num, layer_num; ++ u32 offset; ++ u32 revision = hi_read(hw, DC_HW_REVISION); ++ u32 cid = hi_read(hw, DC_HW_CHIP_CID); ++ const struct dc_hw_plane_reg *reg; ++ ++ switch (revision) { ++ case 0x5720: ++ hw->rev = DC_REV_0; ++ break; ++ case 0x5721: ++ switch (cid) { ++ case 0x30B: ++ hw->rev = DC_REV_1; ++ break; ++ case 0x310: ++ hw->rev = DC_REV_2; ++ break; ++ default: ++ hw->rev = DC_REV_0; ++ break; ++ } ++ break; ++ default: ++ return -ENXIO; ++ } ++ ++ hw->info = (struct vs_dc_info *)&dc_info[hw->rev]; ++ hw->func = (struct dc_hw_funcs *)&hw_func; ++ ++ layer_num = hw->info->layer_num; ++ for (i = 0; i < layer_num; i++) { ++ id = hw->info->planes[i].id; ++ offset = get_addr_offset(id); ++ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) ++ reg = &dc_plane_reg[0]; ++ else ++ reg = &dc_plane_reg[1]; ++ ++ load_default_filter(hw, reg, offset); ++ load_rgb_to_rgb(hw, reg, offset, RGB2RGB); ++ } ++ ++ panel_num = hw->info->panel_num; ++ for (i = 0; i < panel_num; i++) { ++ offset = i << 2; ++ ++ load_rgb_to_yuv(hw, offset, RGB2YUV); ++ dc_write(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0x111); ++ ++ offset = i ? DC_CURSOR_OFFSET : 0; ++ dc_write(hw, DC_CURSOR_BACKGROUND + offset, 0x00FFFFFF); ++ dc_write(hw, DC_CURSOR_FOREGROUND + offset, 0x00AAAAAA); ++ } ++ ++ return 0; ++} ++ ++void dc_hw_deinit(struct dc_hw *hw) ++{ ++ /* Nothing to do */ ++} ++ ++void dc_hw_update_plane(struct dc_hw *hw, u8 id, ++ struct dc_hw_fb *fb, struct dc_hw_scale *scale, ++ struct dc_hw_position *pos, struct dc_hw_blend *blend) ++{ ++ struct dc_hw_plane *plane = &hw->plane[id]; ++ ++ if (plane) { ++ if (fb) { ++ if (!fb->enable) ++ plane->fb.enable = false; ++ else ++ memcpy(&plane->fb, fb, ++ sizeof(*fb) - sizeof(fb->dirty)); ++ plane->fb.dirty = true; ++ } ++ if (scale) { ++ memcpy(&plane->scale, scale, ++ sizeof(*scale) - sizeof(scale->dirty)); ++ plane->scale.dirty = true; ++ } ++ if (pos) { ++ memcpy(&plane->pos, pos, ++ sizeof(*pos) - sizeof(pos->dirty)); ++ plane->pos.dirty = true; ++ } ++ if (blend) { ++ memcpy(&plane->blend, blend, ++ sizeof(*blend) - sizeof(blend->dirty)); ++ plane->blend.dirty = true; ++ } ++ } ++} ++ ++void dc_hw_update_degamma(struct dc_hw *hw, u8 id, u32 mode) ++{ ++ struct dc_hw_plane *plane = &hw->plane[id]; ++ ++ if (plane) { ++ if (hw->info->planes[id].degamma_size) { ++ plane->degamma.mode = mode; ++ plane->degamma.dirty = true; ++ } else { ++ plane->degamma.dirty = false; ++ } ++ } ++} ++ ++void dc_hw_update_roi(struct dc_hw *hw, u8 id, struct dc_hw_roi *roi) ++{ ++ struct dc_hw_plane *plane = &hw->plane[id]; ++ ++ if (plane) { ++ memcpy(&plane->roi, roi, sizeof(*roi) - sizeof(roi->dirty)); ++ plane->roi.dirty = true; ++ } ++} ++ ++void dc_hw_update_colorkey(struct dc_hw *hw, u8 id, ++ struct dc_hw_colorkey *colorkey) ++{ ++ struct dc_hw_plane *plane = &hw->plane[id]; ++ ++ if (plane) { ++ memcpy(&plane->colorkey, colorkey, ++ sizeof(*colorkey) - sizeof(colorkey->dirty)); ++ plane->colorkey.dirty = true; ++ } ++} ++ ++void dc_hw_update_qos(struct dc_hw *hw, struct dc_hw_qos *qos) ++{ ++ memcpy(&hw->qos, qos, sizeof(*qos) - sizeof(qos->dirty)); ++ hw->qos.dirty = true; ++} ++ ++void dc_hw_update_cursor(struct dc_hw *hw, u8 id, struct dc_hw_cursor *cursor) ++{ ++ memcpy(&hw->cursor[id], cursor, sizeof(*cursor) - sizeof(cursor->dirty)); ++ hw->cursor[id].dirty = true; ++} ++ ++void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index, ++ u16 r, u16 g, u16 b) ++{ ++ if (index >= hw->info->gamma_size) ++ return; ++ ++ hw->gamma[id].gamma[index][0] = r; ++ hw->gamma[id].gamma[index][1] = g; ++ hw->gamma[id].gamma[index][2] = b; ++ hw->gamma[id].dirty = true; ++} ++ ++void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable) ++{ ++ hw->gamma[id].enable = enable; ++ hw->gamma[id].dirty = true; ++} ++ ++void dc_hw_setup_display(struct dc_hw *hw, struct dc_hw_display *display) ++{ ++ u8 id = display->id; ++ ++ memcpy(&hw->display[id], display, sizeof(*display)); ++ ++ hw->func->display(hw, display); ++} ++ ++void dc_hw_enable_interrupt(struct dc_hw *hw, bool enable) ++{ ++ if (enable) ++ hi_write(hw, AQ_INTR_ENBL, 0xFFFFFFFF); ++ else ++ hi_write(hw, AQ_INTR_ENBL, 0); ++} ++ ++u32 dc_hw_get_interrupt(struct dc_hw *hw) ++{ ++ return hi_read(hw, AQ_INTR_ACKNOWLEDGE); ++} ++ ++bool dc_hw_check_underflow(struct dc_hw *hw) ++{ ++ return dc_read(hw, DC_FRAMEBUFFER_CONFIG) & BIT(5); ++} ++ ++void dc_hw_enable_shadow_register(struct dc_hw *hw, bool enable) ++{ ++ u32 i, offset; ++ u8 id, layer_num = hw->info->layer_num; ++ u8 panel_num = hw->info->panel_num; ++ ++ for (i = 0; i < layer_num; i++) { ++ id = hw->info->planes[i].id; ++ offset = get_addr_offset(id); ++ if (enable) { ++ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, BIT(12), 0); ++ else ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, BIT(31), 0); ++ } else { ++ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, 0, BIT(12)); ++ else ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, 0, BIT(31)); ++ } ++ } ++ ++ for (i = 0; i < panel_num; i++) { ++ offset = i << 2; ++ if (enable) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, 0, BIT(0)); ++ else ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, BIT(0), 0); ++ } ++} ++ ++void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id) ++{ ++ if (out <= OUT_DP) ++ hw->out[id] = out; ++} ++ ++static void gamma_ex_commit(struct dc_hw *hw) ++{ ++ u8 panel_num = hw->info->panel_num; ++ u16 i, j; ++ u32 value; ++ ++ for (j = 0; j < panel_num; j++) { ++ if (hw->gamma[j].dirty) { ++ if (hw->gamma[j].enable) { ++ dc_write(hw, DC_DISPLAY_GAMMA_EX_INDEX + (j << 2), 0x00); ++ for (i = 0; i < GAMMA_EX_SIZE; i++) { ++ value = hw->gamma[j].gamma[i][2] | ++ (hw->gamma[j].gamma[i][1] << 12); ++ dc_write(hw, DC_DISPLAY_GAMMA_EX_DATA + (j << 2), value); ++ dc_write(hw, DC_DISPLAY_GAMMA_EX_ONE_DATA + (j << 2), ++ hw->gamma[j].gamma[i][0]); ++ } ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (j << 2), ++ BIT(13), 0); ++ } else { ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (j << 2), ++ 0, BIT(13)); ++ } ++ hw->gamma[j].dirty = false; ++ } ++ } ++} ++ ++static void plane_commit(struct dc_hw *hw) ++{ ++ struct dc_hw_plane *plane; ++ const struct dc_hw_plane_reg *reg; ++ bool primary = false; ++ u8 id, layer_num = hw->info->layer_num; ++ u32 i, offset; ++ ++ for (i = 0; i < layer_num; i++) { ++ plane = &hw->plane[i]; ++ id = hw->info->planes[i].id; ++ offset = get_addr_offset(id); ++ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) { ++ reg = &dc_plane_reg[0]; ++ primary = true; ++ } else { ++ reg = &dc_plane_reg[1]; ++ primary = false; ++ } ++ ++ if (plane->fb.dirty) { ++ if (plane->fb.enable) { ++ dc_write(hw, reg->y_address + offset, ++ plane->fb.y_address); ++ dc_write(hw, reg->u_address + offset, ++ plane->fb.u_address); ++ dc_write(hw, reg->v_address + offset, ++ plane->fb.v_address); ++ dc_write(hw, reg->y_stride + offset, ++ plane->fb.y_stride); ++ dc_write(hw, reg->u_stride + offset, ++ plane->fb.u_stride); ++ dc_write(hw, reg->v_stride + offset, ++ plane->fb.v_stride); ++ dc_write(hw, reg->size + offset, ++ plane->fb.width | ++ (plane->fb.height << 15)); ++ dc_write(hw, reg->water_mark + offset, ++ plane->fb.water_mark); ++ ++ if (plane->fb.clear_enable) ++ dc_write(hw, reg->clear_value + offset, ++ plane->fb.clear_value); ++ } ++ ++ if (primary) { ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, ++ (plane->fb.format << 26) | ++ (plane->fb.uv_swizzle << 25) | ++ (plane->fb.swizzle << 23) | ++ (plane->fb.tile_mode << 17) | ++ (plane->fb.yuv_color_space << 14) | ++ (plane->fb.rotation << 11) | ++ (plane->fb.clear_enable << 8), ++ (0x1F << 26) | ++ BIT(25) | ++ (0x03 << 23) | ++ (0x1F << 17) | ++ (0x07 << 14) | ++ (0x07 << 11) | ++ BIT(8)); ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, ++ (plane->fb.dec_enable << 1) | ++ (plane->fb.enable << 13) | ++ (plane->fb.zpos << 16) | ++ (plane->fb.display_id << 19), ++ BIT(1) | BIT(13) | (0x07 << 16) | BIT(19)); ++ } else { ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, ++ (plane->fb.dec_enable << 27) | ++ (plane->fb.clear_enable << 25) | ++ (plane->fb.enable << 24) | ++ (plane->fb.format << 16) | ++ (plane->fb.uv_swizzle << 15) | ++ (plane->fb.swizzle << 13) | ++ (plane->fb.tile_mode << 8) | ++ (plane->fb.yuv_color_space << 5) | ++ (plane->fb.rotation << 2), ++ BIT(27) | ++ BIT(25) | ++ BIT(24) | ++ (0x1F << 16) | ++ BIT(15) | ++ (0x03 << 13) | ++ (0x1F << 8) | ++ (0x07 << 5) | ++ (0x07 << 2)); ++ dc_set_clear(hw, DC_OVERLAY_CONFIG_EX + offset, ++ plane->fb.zpos | (plane->fb.display_id << 3), ++ 0x07 | BIT(3)); ++ } ++ plane->fb.dirty = false; ++ } ++ ++ if (plane->scale.dirty) { ++ if (plane->scale.enable) { ++ dc_write(hw, reg->scale_factor_x + offset, ++ plane->scale.scale_factor_x); ++ dc_write(hw, reg->scale_factor_y + offset, ++ plane->scale.scale_factor_y); ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG + offset, ++ BIT(22), 0); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_SCALE_CONFIG + offset, ++ BIT(8), 0); ++ } else { ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG + offset, ++ 0, BIT(22)); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_SCALE_CONFIG + offset, ++ 0, BIT(8)); ++ } ++ plane->scale.dirty = false; ++ } ++ ++ if (plane->pos.dirty) { ++ dc_write(hw, reg->top_left + offset, ++ plane->pos.start_x | ++ (plane->pos.start_y << 15)); ++ dc_write(hw, reg->bottom_right + offset, ++ plane->pos.end_x | ++ (plane->pos.end_y << 15)); ++ plane->pos.dirty = false; ++ } ++ ++ if (plane->blend.dirty) { ++ dc_write(hw, reg->src_global_color + offset, ++ plane->blend.alpha << 24); ++ dc_write(hw, reg->dst_global_color + offset, ++ plane->blend.alpha << 24); ++ switch (plane->blend.blend_mode) { ++ case BLEND_PREMULTI: ++ dc_write(hw, reg->blend_config + offset, 0x3450); ++ break; ++ case BLEND_COVERAGE: ++ dc_write(hw, reg->blend_config + offset, 0x3950); ++ break; ++ case BLEND_PIXEL_NONE: ++ dc_write(hw, reg->blend_config + offset, 0x3548); ++ break; ++ default: ++ break; ++ } ++ plane->blend.dirty = false; ++ } ++ ++ if (plane->colorkey.dirty) { ++ dc_write(hw, reg->color_key + offset, plane->colorkey.colorkey); ++ dc_write(hw, reg->color_key_high + offset, ++ plane->colorkey.colorkey_high); ++ ++ if (primary) ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, ++ plane->colorkey.transparency << 9, 0x03 << 9); ++ else ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, ++ plane->colorkey.transparency, 0x03); ++ ++ plane->colorkey.dirty = false; ++ } ++ ++ if (plane->roi.dirty) { ++ if (plane->roi.enable) { ++ dc_write(hw, reg->roi_origin + offset, ++ plane->roi.x | (plane->roi.y << 16)); ++ dc_write(hw, reg->roi_size + offset, ++ plane->roi.width | (plane->roi.height << 16)); ++ if (primary) ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, ++ BIT(0), 0); ++ else ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, ++ BIT(22), 0); ++ } else { ++ if (primary) ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset, ++ 0, BIT(0)); ++ else ++ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset, ++ 0, BIT(22)); ++ } ++ plane->roi.dirty = false; ++ } ++ } ++} ++ ++static void plane_ex_commit(struct dc_hw *hw) ++{ ++ struct dc_hw_plane *plane; ++ const struct dc_hw_plane_reg *reg; ++ bool primary = false; ++ u8 id, layer_num = hw->info->layer_num; ++ u32 i, offset; ++ ++ for (i = 0; i < layer_num; i++) { ++ plane = &hw->plane[i]; ++ id = hw->info->planes[i].id; ++ offset = get_addr_offset(id); ++ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) { ++ reg = &dc_plane_reg[0]; ++ primary = true; ++ } else { ++ reg = &dc_plane_reg[1]; ++ primary = false; ++ } ++ ++ if (plane->fb.dirty) { ++ if (is_rgb(plane->fb.format)) { ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG_EX + offset, ++ BIT(6), BIT(8)); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_CONFIG + offset, ++ BIT(29), BIT(30)); ++ } else { ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG_EX + offset, ++ BIT(8), BIT(6)); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_CONFIG + offset, ++ BIT(30), BIT(29)); ++ switch (plane->fb.yuv_color_space) { ++ case COLOR_SPACE_601: ++ load_yuv_to_rgb(hw, reg, offset, YUV601_2RGB); ++ break; ++ case COLOR_SPACE_709: ++ load_yuv_to_rgb(hw, reg, offset, YUV709_2RGB); ++ break; ++ case COLOR_SPACE_2020: ++ load_yuv_to_rgb(hw, reg, offset, YUV2020_2RGB); ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ if (plane->degamma.dirty) { ++ switch (plane->degamma.mode) { ++ case VS_DEGAMMA_DISABLE: ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG_EX + offset, ++ 0, BIT(5)); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_CONFIG + offset, ++ 0, BIT(28)); ++ break; ++ case VS_DEGAMMA_BT709: ++ load_degamma_table(hw, reg, offset, DEGAMMA_709); ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG_EX + offset, ++ BIT(5), 0); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_CONFIG + offset, ++ BIT(28), 0); ++ break; ++ case VS_DEGAMMA_BT2020: ++ load_degamma_table(hw, reg, offset, DEGAMMA_2020); ++ if (primary) ++ dc_set_clear(hw, ++ DC_FRAMEBUFFER_CONFIG_EX + offset, ++ BIT(5), 0); ++ else ++ dc_set_clear(hw, ++ DC_OVERLAY_CONFIG + offset, ++ BIT(28), 0); ++ break; ++ default: ++ break; ++ } ++ plane->degamma.dirty = false; ++ } ++ } ++ plane_commit(hw); ++} ++ ++static void setup_display(struct dc_hw *hw, struct dc_hw_display *display) ++{ ++ u8 id = display->id; ++ u32 dpi_cfg, offset = id << 2; ++ ++ if (hw->display[id].enable) { ++ switch (display->bus_format) { ++ case MEDIA_BUS_FMT_RGB565_1X16: ++ dpi_cfg = 0; ++ break; ++ case MEDIA_BUS_FMT_RGB666_1X18: ++ dpi_cfg = 3; ++ break; ++ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: ++ dpi_cfg = 4; ++ break; ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ dpi_cfg = 5; ++ break; ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ dpi_cfg = 6; ++ break; ++ default: ++ dpi_cfg = 5; ++ break; ++ } ++ dc_write(hw, DC_DISPLAY_DPI_CONFIG + offset, dpi_cfg); ++ ++ if (id == 0) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(0) | BIT(2)); ++ else ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(1) | BIT(2)); ++ ++ dc_write(hw, DC_DISPLAY_H + offset, hw->display[id].h_active | ++ (hw->display[id].h_total << 16)); ++ dc_write(hw, DC_DISPLAY_H_SYNC + offset, ++ hw->display[id].h_sync_start | ++ (hw->display[id].h_sync_end << 15) | ++ (hw->display[id].h_sync_polarity ? 0 : BIT(31)) | ++ BIT(30)); ++ dc_write(hw, DC_DISPLAY_V + offset, hw->display[id].v_active | ++ (hw->display[id].v_total << 16)); ++ dc_write(hw, DC_DISPLAY_V_SYNC + offset, ++ hw->display[id].v_sync_start | ++ (hw->display[id].v_sync_end << 15) | ++ (hw->display[id].v_sync_polarity ? 0 : BIT(31)) | ++ BIT(30)); ++ ++ if (hw->info->pipe_sync) { ++ switch (display->sync_mode) { ++ case VS_SINGLE_DC: ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX, ++ 0, BIT(3) | BIT(4)); ++ break; ++ case VS_MULTI_DC_PRIMARY: ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX, ++ BIT(3) | BIT(4), 0); ++ break; ++ case VS_MULTI_DC_SECONDARY: ++ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX, ++ BIT(3), BIT(4)); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ if (hw->info->background) ++ dc_write(hw, DC_FRAMEBUFFER_BG_COLOR + offset, ++ hw->display[id].bg_color); ++ ++ if (hw->display[id].dither_enable) { ++ dc_write(hw, DC_DISPLAY_DITHER_TABLE_LOW + offset, ++ DC_DISPLAY_DITHERTABLE_LOW); ++ dc_write(hw, DC_DISPLAY_DITHER_TABLE_HIGH + offset, ++ DC_DISPLAY_DITHERTABLE_HIGH); ++ dc_write(hw, DC_DISPLAY_DITHER_CONFIG + offset, BIT(31)); ++ } else { ++ dc_write(hw, DC_DISPLAY_DITHER_CONFIG + offset, 0); ++ } ++ ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, BIT(12), 0); ++ if (hw->display[id].sync_enable) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(2) | BIT(3), 0); ++ else if (id == 0) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(0), BIT(3)); ++ else ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(1), BIT(3)); ++ } else { ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, BIT(12)); ++ if (id == 0) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(0) | BIT(2)); ++ else ++ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(1) | BIT(2)); ++ } ++} ++ ++static void setup_display_ex(struct dc_hw *hw, struct dc_hw_display *display) ++{ ++ u8 id = display->id; ++ u32 dp_cfg, offset = id << 2; ++ bool is_yuv = false; ++ ++ if (hw->display[id].enable && hw->out[id] == OUT_DP) { ++ switch (display->bus_format) { ++ case MEDIA_BUS_FMT_RGB565_1X16: ++ dp_cfg = 0; ++ break; ++ case MEDIA_BUS_FMT_RGB666_1X18: ++ dp_cfg = 1; ++ break; ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ dp_cfg = 2; ++ break; ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ dp_cfg = 3; ++ break; ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ dp_cfg = 2 << 4; ++ is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ dp_cfg = 4 << 4; ++ is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ dp_cfg = 8 << 4; ++ is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ dp_cfg = 10 << 4; ++ is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_UYYVYY8_0_5X24: ++ dp_cfg = 12 << 4; ++ is_yuv = true; ++ break; ++ case MEDIA_BUS_FMT_UYYVYY10_0_5X30: ++ dp_cfg = 13 << 4; ++ is_yuv = true; ++ break; ++ default: ++ dp_cfg = 2; ++ break; ++ } ++ if (is_yuv) ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, BIT(16), 0); ++ else ++ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, BIT(16)); ++ dc_write(hw, DC_DISPLAY_DP_CONFIG + offset, dp_cfg | BIT(3)); ++ } ++ ++ if (hw->out[id] == OUT_DPI) ++ dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, BIT(3)); ++ ++ setup_display(hw, display); ++} ++ ++static const struct dc_hw_funcs hw_func = { ++ .gamma = &gamma_ex_commit, ++ .plane = &plane_ex_commit, ++ .display = setup_display_ex, ++}; ++ ++void dc_hw_commit(struct dc_hw *hw) ++{ ++ u32 i, offset = 0; ++ u8 plane_num = hw->info->plane_num; ++ u8 layer_num = hw->info->layer_num; ++ u8 cursor_num = plane_num - layer_num; ++ ++ hw->func->gamma(hw); ++ hw->func->plane(hw); ++ ++ for (i = 0; i < cursor_num; i++) { ++ if (hw->cursor[i].dirty) { ++ offset = hw->cursor[i].display_id ? DC_CURSOR_OFFSET : 0; ++ if (hw->cursor[i].enable) { ++ dc_write(hw, DC_CURSOR_ADDRESS + offset, ++ hw->cursor[i].address); ++ dc_write(hw, DC_CURSOR_LOCATION + offset, hw->cursor[i].x | ++ (hw->cursor[i].y << 16)); ++ dc_set_clear(hw, DC_CURSOR_CONFIG + offset, ++ (hw->cursor[i].hot_x << 16) | ++ (hw->cursor[i].hot_y << 8) | ++ (hw->cursor[i].size << 5) | ++ BIT(3) | BIT(2) | 0x02, ++ (0xFF << 16) | ++ (0xFF << 8) | ++ (0x07 << 5) | 0x1F); ++ } else { ++ dc_set_clear(hw, DC_CURSOR_CONFIG + offset, BIT(3), 0x03); ++ } ++ hw->cursor[i].dirty = false; ++ } ++ } ++ ++ if (hw->qos.dirty) { ++ dc_set_clear(hw, DC_QOS_CONFIG, (hw->qos.high_value << 4) | ++ hw->qos.low_value, 0xFF); ++ hw->qos.dirty = false; ++ } ++} ++ +diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.h b/drivers/gpu/drm/verisilicon/vs_dc_hw.h +new file mode 100644 +index 000000000000..cd037718ecd5 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.h +@@ -0,0 +1,496 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. ++ */ ++ ++#ifndef __VS_DC_HW_H__ ++#define __VS_DC_HW_H__ ++ ++#include ++ ++#define AQ_INTR_ACKNOWLEDGE 0x0010 ++#define AQ_INTR_ENBL 0x0014 ++#define DC_HW_REVISION 0x0024 ++#define DC_HW_CHIP_CID 0x0030 ++ ++#define DC_REG_BASE 0x0800 ++#define DC_REG_RANGE 0x2000 ++#define DC_SEC_REG_OFFSET 0x100000 ++ ++#define DC_FRAMEBUFFER_CONFIG 0x1518 ++#define DC_FRAMEBUFFER_CONFIG_EX 0x1cc0 ++#define DC_FRAMEBUFFER_SCALE_CONFIG 0x1520 ++#define DC_FRAMEBUFFER_TOP_LEFT 0x24d8 ++#define DC_FRAMEBUFFER_BOTTOM_RIGHT 0x24e0 ++#define DC_FRAMEBUFFER_ADDRESS 0x1400 ++#define DC_FRAMEBUFFER_U_ADDRESS 0x1530 ++#define DC_FRAMEBUFFER_V_ADDRESS 0x1538 ++#define DC_FRAMEBUFFER_STRIDE 0x1408 ++#define DC_FRAMEBUFFER_U_STRIDE 0x1800 ++#define DC_FRAMEBUFFER_V_STRIDE 0x1808 ++#define DC_FRAMEBUFFER_SIZE 0x1810 ++#define DC_FRAMEBUFFER_SCALE_FACTOR_X 0x1828 ++#define DC_FRAMEBUFFER_SCALE_FACTOR_Y 0x1830 ++#define DC_FRAMEBUFFER_H_FILTER_COEF_INDEX 0x1838 ++#define DC_FRAMEBUFFER_H_FILTER_COEF_DATA 0x1a00 ++#define DC_FRAMEBUFFER_V_FILTER_COEF_INDEX 0x1a08 ++#define DC_FRAMEBUFFER_V_FILTER_COEF_DATA 0x1a10 ++#define DC_FRAMEBUFFER_INIT_OFFSET 0x1a20 ++#define DC_FRAMEBUFFER_COLOR_KEY 0x1508 ++#define DC_FRAMEBUFFER_COLOR_KEY_HIGH 0x1510 ++#define DC_FRAMEBUFFER_CLEAR_VALUE 0x1a18 ++#define DC_FRAMEBUFFER_COLOR_TABLE_INDEX 0x1818 ++#define DC_FRAMEBUFFER_COLOR_TABLE_DATA 0x1820 ++#define DC_FRAMEBUFFER_BG_COLOR 0x1528 ++#define DC_FRAMEBUFFER_ROI_ORIGIN 0x1cb0 ++#define DC_FRAMEBUFFER_ROI_SIZE 0x1cb8 ++#define DC_FRAMEBUFFER_WATER_MARK 0x1ce8 ++#define DC_FRAMEBUFFER_DEGAMMA_INDEX 0x1d88 ++#define DC_FRAMEBUFFER_DEGAMMA_DATA 0x1d90 ++#define DC_FRAMEBUFFER_DEGAMMA_EX_DATA 0x1d98 ++#define DC_FRAMEBUFFER_YUVTORGB_COEF0 0x1da0 ++#define DC_FRAMEBUFFER_YUVTORGB_COEF1 0x1da8 ++#define DC_FRAMEBUFFER_YUVTORGB_COEF2 0x1db0 ++#define DC_FRAMEBUFFER_YUVTORGB_COEF3 0x1db8 ++#define DC_FRAMEBUFFER_YUVTORGB_COEF4 0x1e00 ++#define DC_FRAMEBUFFER_YUVTORGB_COEFD0 0x1e08 ++#define DC_FRAMEBUFFER_YUVTORGB_COEFD1 0x1e10 ++#define DC_FRAMEBUFFER_YUVTORGB_COEFD2 0x1e18 ++#define DC_FRAMEBUFFER_Y_CLAMP_BOUND 0x1e88 ++#define DC_FRAMEBUFFER_UV_CLAMP_BOUND 0x1e90 ++#define DC_FRAMEBUFFER_RGBTORGB_COEF0 0x1e20 ++#define DC_FRAMEBUFFER_RGBTORGB_COEF1 0x1e28 ++#define DC_FRAMEBUFFER_RGBTORGB_COEF2 0x1e30 ++#define DC_FRAMEBUFFER_RGBTORGB_COEF3 0x1e38 ++#define DC_FRAMEBUFFER_RGBTORGB_COEF4 0x1e40 ++#define DC_FRAMEBUFFER_BLEND_CONFIG 0x2510 ++#define DC_FRAMEBUFFER_SRC_GLOBAL_COLOR 0x2500 ++#define DC_FRAMEBUFFER_DST_GLOBAL_COLOR 0x2508 ++ ++#define DC_OVERLAY_CONFIG 0x1540 ++#define DC_OVERLAY_CONFIG_EX 0x2540 ++#define DC_OVERLAY_SCALE_CONFIG 0x1c00 ++#define DC_OVERLAY_BLEND_CONFIG 0x1580 ++#define DC_OVERLAY_TOP_LEFT 0x1640 ++#define DC_OVERLAY_BOTTOM_RIGHT 0x1680 ++#define DC_OVERLAY_ADDRESS 0x15c0 ++#define DC_OVERLAY_U_ADDRESS 0x1840 ++#define DC_OVERLAY_V_ADDRESS 0x1880 ++#define DC_OVERLAY_STRIDE 0x1600 ++#define DC_OVERLAY_U_STRIDE 0x18c0 ++#define DC_OVERLAY_V_STRIDE 0x1900 ++#define DC_OVERLAY_SIZE 0x17c0 ++#define DC_OVERLAY_SCALE_FACTOR_X 0x1a40 ++#define DC_OVERLAY_SCALE_FACTOR_Y 0x1a80 ++#define DC_OVERLAY_H_FILTER_COEF_INDEX 0x1aC0 ++#define DC_OVERLAY_H_FILTER_COEF_DATA 0x1b00 ++#define DC_OVERLAY_V_FILTER_COEF_INDEX 0x1b40 ++#define DC_OVERLAY_V_FILTER_COEF_DATA 0x1b80 ++#define DC_OVERLAY_INIT_OFFSET 0x1bC0 ++#define DC_OVERLAY_COLOR_KEY 0x1740 ++#define DC_OVERLAY_COLOR_KEY_HIGH 0x1780 ++#define DC_OVERLAY_CLEAR_VALUE 0x1940 ++#define DC_OVERLAY_COLOR_TABLE_INDEX 0x1980 ++#define DC_OVERLAY_COLOR_TABLE_DATA 0x19c0 ++#define DC_OVERLAY_SRC_GLOBAL_COLOR 0x16c0 ++#define DC_OVERLAY_DST_GLOBAL_COLOR 0x1700 ++#define DC_OVERLAY_ROI_ORIGIN 0x1d00 ++#define DC_OVERLAY_ROI_SIZE 0x1d40 ++#define DC_OVERLAY_WATER_MARK 0x1dc0 ++#define DC_OVERLAY_DEGAMMA_INDEX 0x2200 ++#define DC_OVERLAY_DEGAMMA_DATA 0x2240 ++#define DC_OVERLAY_DEGAMMA_EX_DATA 0x2280 ++#define DC_OVERLAY_YUVTORGB_COEF0 0x1ec0 ++#define DC_OVERLAY_YUVTORGB_COEF1 0x1f00 ++#define DC_OVERLAY_YUVTORGB_COEF2 0x1f40 ++#define DC_OVERLAY_YUVTORGB_COEF3 0x1f80 ++#define DC_OVERLAY_YUVTORGB_COEF4 0x1fc0 ++#define DC_OVERLAY_YUVTORGB_COEFD0 0x2000 ++#define DC_OVERLAY_YUVTORGB_COEFD1 0x2040 ++#define DC_OVERLAY_YUVTORGB_COEFD2 0x2080 ++#define DC_OVERLAY_Y_CLAMP_BOUND 0x22c0 ++#define DC_OVERLAY_UV_CLAMP_BOUND 0x2300 ++#define DC_OVERLAY_RGBTORGB_COEF0 0x20c0 ++#define DC_OVERLAY_RGBTORGB_COEF1 0x2100 ++#define DC_OVERLAY_RGBTORGB_COEF2 0x2140 ++#define DC_OVERLAY_RGBTORGB_COEF3 0x2180 ++#define DC_OVERLAY_RGBTORGB_COEF4 0x21c0 ++ ++#define DC_CURSOR_CONFIG 0x1468 ++#define DC_CURSOR_ADDRESS 0x146c ++#define DC_CURSOR_LOCATION 0x1470 ++#define DC_CURSOR_BACKGROUND 0x1474 ++#define DC_CURSOR_FOREGROUND 0x1478 ++#define DC_CURSOR_CLK_GATING 0x1484 ++#define DC_CURSOR_CONFIG_EX 0x24e8 ++#define DC_CURSOR_OFFSET 0x1080 ++ ++#define DC_DISPLAY_DITHER_CONFIG 0x1410 ++#define DC_DISPLAY_PANEL_CONFIG 0x1418 ++#define DC_DISPLAY_PANEL_CONFIG_EX 0x2518 ++#define DC_DISPLAY_DITHER_TABLE_LOW 0x1420 ++#define DC_DISPLAY_DITHER_TABLE_HIGH 0x1428 ++#define DC_DISPLAY_H 0x1430 ++#define DC_DISPLAY_H_SYNC 0x1438 ++#define DC_DISPLAY_V 0x1440 ++#define DC_DISPLAY_V_SYNC 0x1448 ++#define DC_DISPLAY_CURRENT_LOCATION 0x1450 ++#define DC_DISPLAY_GAMMA_INDEX 0x1458 ++#define DC_DISPLAY_GAMMA_DATA 0x1460 ++#define DC_DISPLAY_INT 0x147c ++#define DC_DISPLAY_INT_ENABLE 0x1480 ++#define DC_DISPLAY_DBI_CONFIG 0x1488 ++#define DC_DISPLAY_GENERAL_CONFIG 0x14b0 ++#define DC_DISPLAY_DPI_CONFIG 0x14b8 ++#define DC_DISPLAY_PANEL_START 0x1ccc ++#define DC_DISPLAY_DEBUG_COUNTER_SELECT 0x14d0 ++#define DC_DISPLAY_DEBUG_COUNTER_VALUE 0x14d8 ++#define DC_DISPLAY_DP_CONFIG 0x1cd0 ++#define DC_DISPLAY_GAMMA_EX_INDEX 0x1cf0 ++#define DC_DISPLAY_GAMMA_EX_DATA 0x1cf8 ++#define DC_DISPLAY_GAMMA_EX_ONE_DATA 0x1d80 ++#define DC_DISPLAY_RGBTOYUV_COEF0 0x1e48 ++#define DC_DISPLAY_RGBTOYUV_COEF1 0x1e50 ++#define DC_DISPLAY_RGBTOYUV_COEF2 0x1e58 ++#define DC_DISPLAY_RGBTOYUV_COEF3 0x1e60 ++#define DC_DISPLAY_RGBTOYUV_COEF4 0x1e68 ++#define DC_DISPLAY_RGBTOYUV_COEFD0 0x1e70 ++#define DC_DISPLAY_RGBTOYUV_COEFD1 0x1e78 ++#define DC_DISPLAY_RGBTOYUV_COEFD2 0x1e80 ++ ++#define DC_CLK_GATTING 0x1a28 ++#define DC_QOS_CONFIG 0x1a38 ++ ++#define DC_TRANSPARENCY_OPAQUE 0x00 ++#define DC_TRANSPARENCY_KEY 0x02 ++#define DC_DISPLAY_DITHERTABLE_LOW 0x7b48f3c0 ++#define DC_DISPLAY_DITHERTABLE_HIGH 0x596ad1e2 ++ ++#define GAMMA_SIZE 256 ++#define GAMMA_EX_SIZE 300 ++#define DEGAMMA_SIZE 260 ++ ++#define RGB_TO_RGB_TABLE_SIZE 9 ++#define YUV_TO_RGB_TABLE_SIZE 16 ++#define RGB_TO_YUV_TABLE_SIZE 12 ++ ++#define DC_LAYER_NUM 6 ++#define DC_DISPLAY_NUM 2 ++#define DC_CURSOR_NUM 2 ++ ++enum dc_chip_rev { ++ DC_REV_0,/* For HW_REV_5720,HW_REV_5721_311 */ ++ DC_REV_1,/* For HW_REV_5721_30B */ ++ DC_REV_2,/* For HW_REV_5721_310 */ ++}; ++ ++enum dc_hw_plane_id { ++ PRIMARY_PLANE_0, ++ OVERLAY_PLANE_0, ++ OVERLAY_PLANE_1, ++ PRIMARY_PLANE_1, ++ OVERLAY_PLANE_2, ++ OVERLAY_PLANE_3, ++ CURSOR_PLANE_0, ++ CURSOR_PLANE_1, ++ PLANE_NUM ++}; ++ ++enum dc_hw_color_format { ++ FORMAT_X4R4G4B4,//0 ++ FORMAT_A4R4G4B4,//1 ++ FORMAT_X1R5G5B5,//2 ++ FORMAT_A1R5G5B5,//3 ++ FORMAT_R5G6B5,//4 ++ FORMAT_X8R8G8B8,//5 ++ FORMAT_A8R8G8B8,//6 ++ FORMAT_YUY2,//7 ++ FORMAT_UYVY,//8 ++ FORMAT_INDEX8,//9 ++ FORMAT_MONOCHROME,//10 ++ FORMAT_YV12 = 0xf, ++ FORMAT_A8,//16 ++ FORMAT_NV12,//17 ++ FORMAT_NV16,//18 ++ FORMAT_RG16,//19 ++ FORMAT_R8,//20 ++ FORMAT_NV12_10BIT,//21 ++ FORMAT_A2R10G10B10,//22 ++ FORMAT_NV16_10BIT,//23 ++ FORMAT_INDEX1,//24 ++ FORMAT_INDEX2,//25 ++ FORMAT_INDEX4,//26 ++ FORMAT_P010,//27 ++ FORMAT_YUV444,//28 ++ FORMAT_YUV444_10BIT,//29 ++}; ++ ++enum dc_hw_yuv_color_space { ++ COLOR_SPACE_601 = 0, ++ COLOR_SPACE_709 = 1, ++ COLOR_SPACE_2020 = 3, ++}; ++ ++enum dc_hw_rotation { ++ ROT_0 = 0, ++ ROT_90 = 4, ++ ROT_180 = 5, ++ ROT_270 = 6, ++ FLIP_X = 1, ++ FLIP_Y = 2, ++ FLIP_XY = 3, ++}; ++ ++enum dc_hw_swizzle { ++ SWIZZLE_ARGB = 0, ++ SWIZZLE_RGBA, ++ SWIZZLE_ABGR, ++ SWIZZLE_BGRA, ++}; ++ ++enum dc_hw_out { ++ OUT_DPI, ++ OUT_DP, ++}; ++ ++enum dc_hw_cursor_size { ++ CURSOR_SIZE_32X32 = 0, ++ CURSOR_SIZE_64X64, ++}; ++ ++enum dc_hw_blend_mode { ++ /* out.rgb = plane_alpha * fg.rgb + ++ * (1 - (plane_alpha * fg.alpha)) * bg.rgb ++ */ ++ BLEND_PREMULTI, ++ /* out.rgb = plane_alpha * fg.alpha * fg.rgb + ++ * (1 - (plane_alpha * fg.alpha)) * bg.rgb ++ */ ++ BLEND_COVERAGE, ++ /* out.rgb = plane_alpha * fg.rgb + ++ * (1 - plane_alpha) * bg.rgb ++ */ ++ BLEND_PIXEL_NONE, ++}; ++ ++struct dc_hw_plane_reg { ++ u32 y_address; ++ u32 u_address; ++ u32 v_address; ++ u32 y_stride; ++ u32 u_stride; ++ u32 v_stride; ++ u32 size; ++ u32 top_left; ++ u32 bottom_right; ++ u32 scale_factor_x; ++ u32 scale_factor_y; ++ u32 h_filter_coef_index; ++ u32 h_filter_coef_data; ++ u32 v_filter_coef_index; ++ u32 v_filter_coef_data; ++ u32 init_offset; ++ u32 color_key; ++ u32 color_key_high; ++ u32 clear_value; ++ u32 color_table_index; ++ u32 color_table_data; ++ u32 scale_config; ++ u32 water_mark; ++ u32 degamma_index; ++ u32 degamma_data; ++ u32 degamma_ex_data; ++ u32 src_global_color; ++ u32 dst_global_color; ++ u32 blend_config; ++ u32 roi_origin; ++ u32 roi_size; ++ u32 yuv_to_rgb_coef0; ++ u32 yuv_to_rgb_coef1; ++ u32 yuv_to_rgb_coef2; ++ u32 yuv_to_rgb_coef3; ++ u32 yuv_to_rgb_coef4; ++ u32 yuv_to_rgb_coefd0; ++ u32 yuv_to_rgb_coefd1; ++ u32 yuv_to_rgb_coefd2; ++ u32 y_clamp_bound; ++ u32 uv_clamp_bound; ++ u32 rgb_to_rgb_coef0; ++ u32 rgb_to_rgb_coef1; ++ u32 rgb_to_rgb_coef2; ++ u32 rgb_to_rgb_coef3; ++ u32 rgb_to_rgb_coef4; ++}; ++ ++struct dc_hw_fb { ++ u32 y_address; ++ u32 u_address; ++ u32 v_address; ++ u32 clear_value; ++ u32 water_mark; ++ u16 y_stride; ++ u16 u_stride; ++ u16 v_stride; ++ u16 width; ++ u16 height; ++ u8 format; ++ u8 tile_mode; ++ u8 rotation; ++ u8 yuv_color_space; ++ u8 swizzle; ++ u8 uv_swizzle; ++ u8 zpos; ++ u8 display_id; ++ bool clear_enable; ++ bool dec_enable; ++ bool enable; ++ bool dirty; ++}; ++ ++struct dc_hw_scale { ++ u32 scale_factor_x; ++ u32 scale_factor_y; ++ bool enable; ++ bool dirty; ++}; ++ ++struct dc_hw_position { ++ u16 start_x; ++ u16 start_y; ++ u16 end_x; ++ u16 end_y; ++ bool dirty; ++}; ++ ++struct dc_hw_blend { ++ u8 alpha; ++ u8 blend_mode; ++ bool dirty; ++}; ++ ++struct dc_hw_colorkey { ++ u32 colorkey; ++ u32 colorkey_high; ++ u8 transparency; ++ bool dirty; ++}; ++ ++struct dc_hw_roi { ++ u16 x; ++ u16 y; ++ u16 width; ++ u16 height; ++ bool enable; ++ bool dirty; ++}; ++ ++struct dc_hw_cursor { ++ u32 address; ++ u16 x; ++ u16 y; ++ u16 hot_x; ++ u16 hot_y; ++ u8 size; ++ u8 display_id; ++ bool enable; ++ bool dirty; ++}; ++ ++struct dc_hw_display { ++ u32 bus_format; ++ u16 h_active; ++ u16 h_total; ++ u16 h_sync_start; ++ u16 h_sync_end; ++ u16 v_active; ++ u16 v_total; ++ u16 v_sync_start; ++ u16 v_sync_end; ++ u16 sync_mode; ++ u32 bg_color; ++ u8 id; ++ bool h_sync_polarity; ++ bool v_sync_polarity; ++ bool enable; ++ bool sync_enable; ++ bool dither_enable; ++}; ++ ++struct dc_hw_gamma { ++ u16 gamma[GAMMA_EX_SIZE][3]; ++ bool enable; ++ bool dirty; ++}; ++ ++struct dc_hw_degamma { ++ u16 degamma[DEGAMMA_SIZE][3]; ++ u32 mode; ++ bool dirty; ++}; ++ ++struct dc_hw_plane { ++ struct dc_hw_fb fb; ++ struct dc_hw_position pos; ++ struct dc_hw_scale scale; ++ struct dc_hw_blend blend; ++ struct dc_hw_roi roi; ++ struct dc_hw_colorkey colorkey; ++ struct dc_hw_degamma degamma; ++}; ++ ++struct dc_hw_qos { ++ u8 low_value; ++ u8 high_value; ++ bool dirty; ++}; ++ ++struct dc_hw_read { ++ u32 reg; ++ u32 value; ++}; ++ ++struct dc_hw; ++struct dc_hw_funcs { ++ void (*gamma)(struct dc_hw *hw); ++ void (*plane)(struct dc_hw *hw); ++ void (*display)(struct dc_hw *hw, struct dc_hw_display *display); ++}; ++ ++struct dc_hw { ++ enum dc_chip_rev rev; ++ enum dc_hw_out out[DC_DISPLAY_NUM]; ++ void *hi_base; ++ void *reg_base; ++ ++ struct dc_hw_display display[DC_DISPLAY_NUM]; ++ struct dc_hw_gamma gamma[DC_DISPLAY_NUM]; ++ struct dc_hw_plane plane[DC_LAYER_NUM]; ++ struct dc_hw_cursor cursor[DC_CURSOR_NUM]; ++ struct dc_hw_qos qos; ++ struct dc_hw_funcs *func; ++ struct vs_dc_info *info; ++}; ++ ++int dc_hw_init(struct dc_hw *hw); ++void dc_hw_deinit(struct dc_hw *hw); ++void dc_hw_update_plane(struct dc_hw *hw, u8 id, ++ struct dc_hw_fb *fb, struct dc_hw_scale *scale, ++ struct dc_hw_position *pos, struct dc_hw_blend *blend); ++void dc_hw_update_degamma(struct dc_hw *hw, u8 id, u32 mode); ++void dc_hw_update_roi(struct dc_hw *hw, u8 id, struct dc_hw_roi *roi); ++void dc_hw_update_colorkey(struct dc_hw *hw, u8 id, ++ struct dc_hw_colorkey *colorkey); ++void dc_hw_update_qos(struct dc_hw *hw, struct dc_hw_qos *qos); ++void dc_hw_update_cursor(struct dc_hw *hw, u8 id, struct dc_hw_cursor *cursor); ++void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index, ++ u16 r, u16 g, u16 b); ++void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable); ++void dc_hw_setup_display(struct dc_hw *hw, struct dc_hw_display *display); ++void dc_hw_enable_interrupt(struct dc_hw *hw, bool enable); ++u32 dc_hw_get_interrupt(struct dc_hw *hw); ++bool dc_hw_check_underflow(struct dc_hw *hw); ++void dc_hw_enable_shadow_register(struct dc_hw *hw, bool enable); ++void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id); ++void dc_hw_commit(struct dc_hw *hw); ++ ++#endif /* __VS_DC_HW_H__ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index d84aacd751bc..c28bfd74ffc9 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -32,6 +32,7 @@ + #include "vs_drv.h" + #include "vs_fb.h" + #include "vs_gem.h" ++#include "vs_dc.h" + + #define DRV_NAME "starfive" + #define DRV_DESC "Starfive DRM driver" +@@ -181,6 +182,7 @@ static const struct component_master_ops vs_drm_ops = { + }; + + static struct platform_driver *drm_sub_drivers[] = { ++ &dc_platform_driver, + }; + + #define NUM_DRM_DRIVERS \ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0057-drm-verisilicon-Add-starfive-hdmi-driver.patch b/srcpkgs/linux6.4/patches/0057-drm-verisilicon-Add-starfive-hdmi-driver.patch new file mode 100644 index 0000000000000..4fe4fc8116c0a --- /dev/null +++ b/srcpkgs/linux6.4/patches/0057-drm-verisilicon-Add-starfive-hdmi-driver.patch @@ -0,0 +1,1318 @@ +From 7cd2ad113b82f8592dfc9023b2ec6f6482ea8236 Mon Sep 17 00:00:00 2001 +From: Keith Zhao +Date: Fri, 2 Jun 2023 15:40:43 +0800 +Subject: [PATCH 57/72] drm/verisilicon: Add starfive hdmi driver + +Add HDMI dirver for StarFive SoC JH7110. + +Signed-off-by: Keith Zhao +--- + drivers/gpu/drm/verisilicon/Kconfig | 11 + + drivers/gpu/drm/verisilicon/Makefile | 1 + + drivers/gpu/drm/verisilicon/starfive_hdmi.c | 928 ++++++++++++++++++++ + drivers/gpu/drm/verisilicon/starfive_hdmi.h | 296 +++++++ + drivers/gpu/drm/verisilicon/vs_drv.c | 6 + + drivers/gpu/drm/verisilicon/vs_drv.h | 4 + + 6 files changed, 1246 insertions(+) + create mode 100644 drivers/gpu/drm/verisilicon/starfive_hdmi.c + create mode 100644 drivers/gpu/drm/verisilicon/starfive_hdmi.h + +diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig +index 89d12185f73b..35e85ac41b10 100644 +--- a/drivers/gpu/drm/verisilicon/Kconfig ++++ b/drivers/gpu/drm/verisilicon/Kconfig +@@ -11,3 +11,14 @@ config DRM_VERISILICON + This driver provides VeriSilicon kernel mode + setting and buffer management. It does not + provide 2D or 3D acceleration. ++ ++config STARFIVE_HDMI ++ bool "Starfive specific extensions HDMI" ++ help ++ This selects support for StarFive SoC specific extensions ++ for the Innosilicon HDMI driver. If you want to enable ++ HDMI on JH7110 based SoC, you should select this option. ++ ++ To compile this driver as a module, choose M here. ++ ++ +diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile +index 0ed25b5e3062..ebe2c94f529a 100644 +--- a/drivers/gpu/drm/verisilicon/Makefile ++++ b/drivers/gpu/drm/verisilicon/Makefile +@@ -8,5 +8,6 @@ vs_drm-objs := vs_dc_hw.o \ + vs_gem.o \ + vs_plane.o + ++vs_drm-$(CONFIG_STARFIVE_HDMI) += starfive_hdmi.o + obj-$(CONFIG_DRM_VERISILICON) += vs_drm.o + +diff --git a/drivers/gpu/drm/verisilicon/starfive_hdmi.c b/drivers/gpu/drm/verisilicon/starfive_hdmi.c +new file mode 100644 +index 000000000000..128ecca03309 +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/starfive_hdmi.c +@@ -0,0 +1,928 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "starfive_hdmi.h" ++#include "vs_drv.h" ++ ++static struct starfive_hdmi *encoder_to_hdmi(struct drm_encoder *encoder) ++{ ++ return container_of(encoder, struct starfive_hdmi, encoder); ++} ++ ++static struct starfive_hdmi *connector_to_hdmi(struct drm_connector *connector) ++{ ++ return container_of(connector, struct starfive_hdmi, connector); ++} ++ ++struct starfive_hdmi_i2c { ++ struct i2c_adapter adap; ++ ++ u8 ddc_addr; ++ u8 segment_addr; ++ /* protects the edid data when use i2c cmd to read edid */ ++ struct mutex lock; ++ struct completion cmp; ++}; ++ ++static const struct pre_pll_config pre_pll_cfg_table[] = { ++ { 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xf55555}, ++ { 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0}, ++ { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0}, ++ { 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170a3d}, ++ { 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51eb85}, ++ { 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3d70a3}, ++ { 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ { 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ { 36000000, 36000000, 1, 36, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0}, ++ { 46970000, 46970000, 1, 46, 2, 1, 1, 3, 0, 3, 4, 0, 0xf851eb}, ++ { 49500000, 49500000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ { 49000000, 49000000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 50000000, 50000000, 1, 50, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 54000000, 54000000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 54054000, 54054000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0x0dd2f1}, ++ { 57284000, 57284000, 1, 57, 2, 1, 1, 3, 0, 3, 4, 0, 0x48b439}, ++ { 58230000, 58230000, 1, 58, 2, 1, 1, 3, 0, 3, 4, 0, 0x3ae147}, ++ { 59341000, 59341000, 1, 59, 2, 1, 1, 3, 0, 3, 4, 0, 0x574bc6}, ++ { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0}, ++ { 65000000, 65000000, 1, 130, 2, 2, 2, 12, 0, 2, 2, 0, 0}, ++ { 68250000, 68250000, 1, 68, 2, 1, 1, 3, 0, 3, 4, 0, 0x3fffff}, ++ { 71000000, 71000000, 1, 71, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xe6ae6b}, ++ { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0}, ++ { 75000000, 75000000, 1, 75, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ { 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ { 79500000, 79500000, 1, 79, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0}, ++ { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000}, ++ { 84858000, 84858000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xdba5e2}, ++ { 85500000, 85500000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ { 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ { 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xcccccc}, ++ { 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ { 89910000, 89910000, 1, 89, 2, 1, 1, 3, 0, 3, 4, 0, 0xe8f5c1}, ++ { 90000000, 90000000, 1, 90, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {101000000, 101000000, 1, 101, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {102250000, 102250000, 1, 102, 2, 1, 1, 3, 0, 3, 4, 0, 0x3fffff}, ++ {106500000, 106500000, 1, 106, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ {108000000, 108000000, 1, 90, 3, 0, 0, 5, 0, 2, 2, 0, 0}, ++ {119000000, 119000000, 1, 119, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {131481000, 131481000, 1, 131, 2, 1, 1, 3, 0, 3, 4, 0, 0x7b22d1}, ++ {135000000, 135000000, 1, 135, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ {147180000, 147180000, 1, 147, 2, 1, 1, 3, 0, 3, 4, 0, 0x2e147a}, ++ {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xe6ae6b}, ++ {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0}, ++ {154000000, 154000000, 1, 154, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {156000000, 156000000, 1, 156, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {157000000, 157000000, 1, 157, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {162000000, 162000000, 1, 162, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {174250000, 174250000, 1, 145, 3, 0, 0, 5, 0, 2, 2, 0, 0x355555}, ++ {174500000, 174500000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ {174570000, 174570000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x91eb84}, ++ {175500000, 175500000, 1, 175, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ {185590000, 185590000, 1, 185, 2, 1, 1, 3, 0, 3, 4, 0, 0x970a3c}, ++ {187000000, 187000000, 1, 187, 2, 1, 1, 3, 0, 3, 4, 0, 0}, ++ {241500000, 241500000, 1, 161, 1, 1, 1, 4, 0, 2, 2, 0, 0}, ++ {241700000, 241700000, 1, 241, 2, 1, 1, 3, 0, 3, 4, 0, 0xb33332}, ++ {262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xcfffff}, ++ {296500000, 296500000, 1, 296, 2, 1, 1, 3, 0, 3, 4, 0, 0x7fffff}, ++ {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xe6ae6b}, ++ {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0}, ++ {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0}, ++ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, ++}; ++ ++static const struct post_pll_config post_pll_cfg_table[] = { ++ {25200000, 1, 80, 13, 3, 1}, ++ {27000000, 1, 40, 11, 3, 1}, ++ {33750000, 1, 40, 11, 3, 1}, ++ {49000000, 1, 20, 1, 3, 3}, ++ {241700000, 1, 20, 1, 3, 3}, ++ {297000000, 4, 20, 0, 0, 3}, ++ {594000000, 4, 20, 0, 0, 0}, ++ { /* sentinel */ } ++}; ++ ++inline u8 hdmi_readb(struct starfive_hdmi *hdmi, u16 offset) ++{ ++ return readl_relaxed(hdmi->regs + (offset) * 0x04); ++} ++ ++inline void hdmi_writeb(struct starfive_hdmi *hdmi, u16 offset, u32 val) ++{ ++ writel_relaxed(val, hdmi->regs + (offset) * 0x04); ++} ++ ++inline void hdmi_modb(struct starfive_hdmi *hdmi, u16 offset, ++ u32 msk, u32 val) ++{ ++ u8 temp = hdmi_readb(hdmi, offset) & ~msk; ++ ++ temp |= val & msk; ++ hdmi_writeb(hdmi, offset, temp); ++} ++ ++static int starfive_hdmi_enable_clk_deassert_rst(struct device *dev, struct starfive_hdmi *hdmi) ++{ ++ int ret; ++ ++ ret = clk_prepare_enable(hdmi->sys_clk); ++ if (ret) { ++ DRM_DEV_ERROR(dev, "Cannot enable HDMI sys clock: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(hdmi->mclk); ++ if (ret) { ++ DRM_DEV_ERROR(dev, "Cannot enable HDMI mclk clock: %d\n", ret); ++ return ret; ++ } ++ ret = clk_prepare_enable(hdmi->bclk); ++ if (ret) { ++ DRM_DEV_ERROR(dev, "Cannot enable HDMI bclk clock: %d\n", ret); ++ return ret; ++ } ++ ret = reset_control_deassert(hdmi->tx_rst); ++ if (ret < 0) { ++ dev_err(dev, "failed to deassert tx_rst\n"); ++ return ret; ++ } ++ return 0; ++} ++ ++static void starfive_hdmi_disable_clk_assert_rst(struct device *dev, struct starfive_hdmi *hdmi) ++{ ++ int ret; ++ ++ ret = reset_control_assert(hdmi->tx_rst); ++ if (ret < 0) ++ dev_err(dev, "failed to assert tx_rst\n"); ++ ++ clk_disable_unprepare(hdmi->sys_clk); ++ clk_disable_unprepare(hdmi->mclk); ++ clk_disable_unprepare(hdmi->bclk); ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int hdmi_system_pm_suspend(struct device *dev) ++{ ++ return pm_runtime_force_suspend(dev); ++} ++ ++static int hdmi_system_pm_resume(struct device *dev) ++{ ++ return pm_runtime_force_resume(dev); ++} ++#endif ++ ++#ifdef CONFIG_PM ++static int hdmi_runtime_suspend(struct device *dev) ++{ ++ struct starfive_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ starfive_hdmi_disable_clk_assert_rst(dev, hdmi); ++ ++ return 0; ++} ++ ++static int hdmi_runtime_resume(struct device *dev) ++{ ++ struct starfive_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ return starfive_hdmi_enable_clk_deassert_rst(dev, hdmi); ++} ++#endif ++ ++static void starfive_hdmi_tx_phy_power_down(struct starfive_hdmi *hdmi) ++{ ++ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); ++} ++ ++static void starfive_hdmi_tx_phy_power_on(struct starfive_hdmi *hdmi) ++{ ++ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); ++} ++ ++static void starfive_hdmi_config_pll(struct starfive_hdmi *hdmi) ++{ ++ u32 val; ++ u8 reg_1ad_value = hdmi->post_cfg->post_div_en ? ++ hdmi->post_cfg->postdiv : 0x00; ++ u8 reg_1aa_value = hdmi->post_cfg->post_div_en ? ++ 0x0e : 0x02; ++ ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_CONTROL, STARFIVE_PRE_PLL_POWER_DOWN); ++ hdmi_writeb(hdmi, STARFIVE_POST_PLL_DIV_1, ++ STARFIVE_POST_PLL_POST_DIV_ENABLE | ++ STARFIVE_POST_PLL_REFCLK_SEL_TMDS | ++ STARFIVE_POST_PLL_POWER_DOWN); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_1, STARFIVE_PRE_PLL_PRE_DIV(hdmi->pre_cfg->prediv)); ++ ++ val = STARFIVE_SPREAD_SPECTRUM_MOD_DISABLE | STARFIVE_SPREAD_SPECTRUM_MOD_DOWN; ++ if (!hdmi->pre_cfg->fracdiv) ++ val |= STARFIVE_PRE_PLL_FRAC_DIV_DISABLE; ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_2, ++ STARFIVE_PRE_PLL_FB_DIV_11_8(hdmi->pre_cfg->fbdiv) | val); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_3, ++ STARFIVE_PRE_PLL_FB_DIV_7_0(hdmi->pre_cfg->fbdiv)); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_4, ++ STARFIVE_PRE_PLL_TMDSCLK_DIV_C(hdmi->pre_cfg->tmds_div_c) | ++ STARFIVE_PRE_PLL_TMDSCLK_DIV_A(hdmi->pre_cfg->tmds_div_a) | ++ STARFIVE_PRE_PLL_TMDSCLK_DIV_B(hdmi->pre_cfg->tmds_div_b)); ++ ++ if (hdmi->pre_cfg->fracdiv) { ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_FRAC_DIV_L, ++ STARFIVE_PRE_PLL_FRAC_DIV_7_0(hdmi->pre_cfg->fracdiv)); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_FRAC_DIV_M, ++ STARFIVE_PRE_PLL_FRAC_DIV_15_8(hdmi->pre_cfg->fracdiv)); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_FRAC_DIV_H, ++ STARFIVE_PRE_PLL_FRAC_DIV_23_16(hdmi->pre_cfg->fracdiv)); ++ } ++ ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_5, ++ STARFIVE_PRE_PLL_PCLK_DIV_A(hdmi->pre_cfg->pclk_div_a) | ++ STARFIVE_PRE_PLL_PCLK_DIV_B(hdmi->pre_cfg->pclk_div_b)); ++ hdmi_writeb(hdmi, STARFIVE_PRE_PLL_DIV_6, ++ STARFIVE_PRE_PLL_PCLK_DIV_C(hdmi->pre_cfg->pclk_div_c) | ++ STARFIVE_PRE_PLL_PCLK_DIV_D(hdmi->pre_cfg->pclk_div_d)); ++ ++ /*pre-pll power down*/ ++ hdmi_modb(hdmi, STARFIVE_PRE_PLL_CONTROL, STARFIVE_PRE_PLL_POWER_DOWN, 0); ++ ++ hdmi_modb(hdmi, STARFIVE_POST_PLL_DIV_2, STARFIVE_POST_PLL_Pre_DIV_MASK, ++ STARFIVE_POST_PLL_PRE_DIV(hdmi->post_cfg->prediv)); ++ hdmi_writeb(hdmi, STARFIVE_POST_PLL_DIV_3, hdmi->post_cfg->fbdiv & 0xff); ++ hdmi_writeb(hdmi, STARFIVE_POST_PLL_DIV_4, reg_1ad_value); ++ hdmi_writeb(hdmi, STARFIVE_POST_PLL_DIV_1, reg_1aa_value); ++} ++ ++static void starfive_hdmi_tmds_driver_on(struct starfive_hdmi *hdmi) ++{ ++ hdmi_modb(hdmi, STARFIVE_TMDS_CONTROL, ++ STARFIVE_TMDS_DRIVER_ENABLE, STARFIVE_TMDS_DRIVER_ENABLE); ++} ++ ++static void starfive_hdmi_sync_tmds(struct starfive_hdmi *hdmi) ++{ ++ /*first send 0 to this bit, then send 1 and keep 1 into this bit*/ ++ hdmi_writeb(hdmi, HDMI_SYNC, 0x0); ++ hdmi_writeb(hdmi, HDMI_SYNC, 0x1); ++} ++ ++static void starfive_hdmi_i2c_init(struct starfive_hdmi *hdmi) ++{ ++ int ddc_bus_freq; ++ ++ ddc_bus_freq = (hdmi->tmds_rate >> 2) / HDMI_SCL_RATE; ++ ++ hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); ++ hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); ++ ++ /* Clear the EDID interrupt flag and mute the interrupt */ ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); ++} ++ ++static const ++struct pre_pll_config *starfive_hdmi_phy_get_pre_pll_cfg(struct starfive_hdmi *hdmi, ++ unsigned long rate) ++{ ++ const struct pre_pll_config *cfg = pre_pll_cfg_table; ++ ++ rate = (rate / 1000) * 1000; ++ for (; cfg->pixclock != 0; cfg++) ++ if (cfg->tmdsclock == rate && cfg->pixclock == rate) ++ break; ++ ++ if (cfg->pixclock == 0) ++ return ERR_PTR(-EINVAL); ++ ++ return cfg; ++} ++ ++static int starfive_hdmi_phy_clk_set_rate(struct starfive_hdmi *hdmi) ++{ ++ hdmi->post_cfg = post_pll_cfg_table; ++ ++ hdmi->pre_cfg = starfive_hdmi_phy_get_pre_pll_cfg(hdmi, hdmi->tmds_rate); ++ if (IS_ERR(hdmi->pre_cfg)) ++ return PTR_ERR(hdmi->pre_cfg); ++ ++ for (; hdmi->post_cfg->tmdsclock != 0; hdmi->post_cfg++) ++ if (hdmi->tmds_rate <= hdmi->post_cfg->tmdsclock) ++ break; ++ ++ starfive_hdmi_config_pll(hdmi); ++ ++ return 0; ++} ++ ++static int starfive_hdmi_config_video_timing(struct starfive_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ int value; ++ /* Set detail external video timing */ ++ value = mode->htotal; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); ++ ++ value = mode->htotal - mode->hdisplay; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); ++ ++ value = mode->htotal - mode->hsync_start; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); ++ ++ value = mode->hsync_end - mode->hsync_start; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); ++ ++ value = mode->vtotal; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); ++ ++ value = mode->vtotal - mode->vdisplay; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); ++ ++ value = mode->vtotal - mode->vsync_start; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); ++ ++ value = mode->vsync_end - mode->vsync_start; ++ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); ++ ++ /* Set detail external video timing polarity and interlace mode */ ++ value = v_EXTERANL_VIDEO(1); ++ value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? ++ v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); ++ value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? ++ v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); ++ value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? ++ v_INETLACE(1) : v_INETLACE(0); ++ ++ hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); ++ return 0; ++} ++ ++static int starfive_hdmi_setup(struct starfive_hdmi *hdmi, ++ struct drm_display_mode *mode) ++{ ++ hdmi_modb(hdmi, STARFIVE_BIAS_CONTROL, STARFIVE_BIAS_ENABLE, STARFIVE_BIAS_ENABLE); ++ hdmi_writeb(hdmi, STARFIVE_RX_CONTROL, STARFIVE_RX_ENABLE); ++ hdmi->hdmi_data.vic = drm_match_cea_mode(mode); ++ ++ hdmi->tmds_rate = mode->clock * 1000; ++ starfive_hdmi_phy_clk_set_rate(hdmi); ++ ++ while (!(hdmi_readb(hdmi, STARFIVE_PRE_PLL_LOCK_STATUS) & 0x1)) ++ continue; ++ while (!(hdmi_readb(hdmi, STARFIVE_POST_PLL_LOCK_STATUS) & 0x1)) ++ continue; ++ ++ /*turn on LDO*/ ++ hdmi_writeb(hdmi, STARFIVE_LDO_CONTROL, STARFIVE_LDO_ENABLE); ++ /*turn on serializer*/ ++ hdmi_writeb(hdmi, STARFIVE_SERIALIER_CONTROL, STARFIVE_SERIALIER_ENABLE); ++ ++ starfive_hdmi_tx_phy_power_down(hdmi); ++ starfive_hdmi_config_video_timing(hdmi, mode); ++ starfive_hdmi_tx_phy_power_on(hdmi); ++ ++ starfive_hdmi_tmds_driver_on(hdmi); ++ starfive_hdmi_sync_tmds(hdmi); ++ ++ return 0; ++} ++ ++static void starfive_hdmi_encoder_mode_set(struct drm_encoder *encoder, ++ struct drm_display_mode *mode, ++ struct drm_display_mode *adj_mode) ++{ ++ struct starfive_hdmi *hdmi = encoder_to_hdmi(encoder); ++ ++ starfive_hdmi_setup(hdmi, adj_mode); ++ ++ memcpy(&hdmi->previous_mode, adj_mode, sizeof(hdmi->previous_mode)); ++} ++ ++static void starfive_hdmi_encoder_enable(struct drm_encoder *encoder) ++{ ++ struct starfive_hdmi *hdmi = encoder_to_hdmi(encoder); ++ ++ pm_runtime_get_sync(hdmi->dev); ++} ++ ++static void starfive_hdmi_encoder_disable(struct drm_encoder *encoder) ++{ ++ struct starfive_hdmi *hdmi = encoder_to_hdmi(encoder); ++ ++ pm_runtime_put(hdmi->dev); ++} ++ ++static bool starfive_hdmi_encoder_mode_fixup(struct drm_encoder *encoder, ++ const struct drm_display_mode *mode, ++ struct drm_display_mode *adj_mode) ++{ ++ return true; ++} ++ ++static int ++starfive_hdmi_encoder_atomic_check(struct drm_encoder *encoder, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state) ++{ ++ return 0; ++} ++ ++static const struct drm_encoder_helper_funcs starfive_hdmi_encoder_helper_funcs = { ++ .enable = starfive_hdmi_encoder_enable, ++ .disable = starfive_hdmi_encoder_disable, ++ .mode_fixup = starfive_hdmi_encoder_mode_fixup, ++ .mode_set = starfive_hdmi_encoder_mode_set, ++ .atomic_check = starfive_hdmi_encoder_atomic_check, ++}; ++ ++static enum drm_connector_status ++starfive_hdmi_connector_detect(struct drm_connector *connector, bool force) ++{ ++ struct starfive_hdmi *hdmi = connector_to_hdmi(connector); ++ int ret; ++ ++ ret = pm_runtime_get_sync(hdmi->dev); ++ if (ret < 0) ++ return ret; ++ ++ ret = (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? ++ connector_status_connected : connector_status_disconnected; ++ ++ pm_runtime_put(hdmi->dev); ++ ++ return ret; ++} ++ ++static int starfive_hdmi_connector_get_modes(struct drm_connector *connector) ++{ ++ struct starfive_hdmi *hdmi = connector_to_hdmi(connector); ++ struct edid *edid; ++ int ret = 0; ++ ++ if (!hdmi->ddc) ++ return 0; ++ ++ edid = drm_get_edid(connector, hdmi->ddc); ++ if (edid) { ++ hdmi->hdmi_data.sink_is_hdmi = drm_detect_hdmi_monitor(edid); ++ hdmi->hdmi_data.sink_has_audio = drm_detect_monitor_audio(edid); ++ drm_connector_update_edid_property(connector, edid); ++ ret = drm_add_edid_modes(connector, edid); ++ kfree(edid); ++ } ++ ++ return ret; ++} ++ ++static enum drm_mode_status ++starfive_hdmi_connector_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) ++{ ++ const struct pre_pll_config *cfg = pre_pll_cfg_table; ++ int pclk = mode->clock * 1000; ++ bool valid = false; ++ int i; ++ ++ for (i = 0; cfg[i].pixclock != (~0UL); i++) { ++ if (pclk == cfg[i].pixclock) { ++ if (pclk > 297000000) ++ continue; ++ ++ valid = true; ++ break; ++ } ++ } ++ ++ return (valid) ? MODE_OK : MODE_BAD; ++} ++ ++static int ++starfive_hdmi_probe_single_connector_modes(struct drm_connector *connector, ++ u32 maxX, u32 maxY) ++{ ++ struct starfive_hdmi *hdmi = connector_to_hdmi(connector); ++ int ret; ++ ++ pm_runtime_get_sync(hdmi->dev); ++ ++ ret = drm_helper_probe_single_connector_modes(connector, 3840, 2160); ++ ++ pm_runtime_put(hdmi->dev); ++ ++ return ret; ++} ++ ++static void starfive_hdmi_connector_destroy(struct drm_connector *connector) ++{ ++ drm_connector_unregister(connector); ++ drm_connector_cleanup(connector); ++} ++ ++static const struct drm_connector_funcs starfive_hdmi_connector_funcs = { ++ .fill_modes = starfive_hdmi_probe_single_connector_modes, ++ .detect = starfive_hdmi_connector_detect, ++ .destroy = starfive_hdmi_connector_destroy, ++ .reset = drm_atomic_helper_connector_reset, ++ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, ++}; ++ ++static struct drm_connector_helper_funcs starfive_hdmi_connector_helper_funcs = { ++ .get_modes = starfive_hdmi_connector_get_modes, ++ .mode_valid = starfive_hdmi_connector_mode_valid, ++}; ++ ++static int starfive_hdmi_register(struct drm_device *drm, struct starfive_hdmi *hdmi) ++{ ++ struct drm_encoder *encoder = &hdmi->encoder; ++ struct device *dev = hdmi->dev; ++ ++ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); ++ ++ /* ++ * If we failed to find the CRTC(s) which this encoder is ++ * supposed to be connected to, it's because the CRTC has ++ * not been registered yet. Defer probing, and hope that ++ * the required CRTC is added later. ++ */ ++ if (encoder->possible_crtcs == 0) ++ return -EPROBE_DEFER; ++ ++ drm_encoder_helper_add(encoder, &starfive_hdmi_encoder_helper_funcs); ++ drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); ++ ++ hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD; ++ ++ drm_connector_helper_add(&hdmi->connector, ++ &starfive_hdmi_connector_helper_funcs); ++ drm_connector_init_with_ddc(drm, &hdmi->connector, ++ &starfive_hdmi_connector_funcs, ++ DRM_MODE_CONNECTOR_HDMIA, ++ hdmi->ddc); ++ ++ drm_connector_attach_encoder(&hdmi->connector, encoder); ++ ++ return 0; ++} ++ ++static irqreturn_t starfive_hdmi_i2c_irq(struct starfive_hdmi *hdmi) ++{ ++ struct starfive_hdmi_i2c *i2c = hdmi->i2c; ++ u8 stat; ++ ++ stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); ++ if (!(stat & m_INT_EDID_READY)) ++ return IRQ_NONE; ++ ++ /* Clear HDMI EDID interrupt flag */ ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); ++ ++ complete(&i2c->cmp); ++ ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t starfive_hdmi_hardirq(int irq, void *dev_id) ++{ ++ struct starfive_hdmi *hdmi = dev_id; ++ irqreturn_t ret = IRQ_NONE; ++ u8 interrupt; ++ ++ if (hdmi->i2c) ++ ret = starfive_hdmi_i2c_irq(hdmi); ++ ++ interrupt = hdmi_readb(hdmi, HDMI_STATUS); ++ if (interrupt & m_INT_HOTPLUG) { ++ hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); ++ ret = IRQ_WAKE_THREAD; ++ } ++ ++ return ret; ++} ++ ++static irqreturn_t starfive_hdmi_irq(int irq, void *dev_id) ++{ ++ struct starfive_hdmi *hdmi = dev_id; ++ ++ drm_helper_hpd_irq_event(hdmi->connector.dev); ++ ++ return IRQ_HANDLED; ++} ++ ++static int starfive_hdmi_i2c_read(struct starfive_hdmi *hdmi, struct i2c_msg *msgs) ++{ ++ int length = msgs->len; ++ u8 *buf = msgs->buf; ++ int ret; ++ ++ ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); ++ if (!ret) ++ return -EAGAIN; ++ ++ while (length--) ++ *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); ++ ++ return 0; ++} ++ ++static int starfive_hdmi_i2c_write(struct starfive_hdmi *hdmi, struct i2c_msg *msgs) ++{ ++ /* ++ * The DDC module only support read EDID message, so ++ * we assume that each word write to this i2c adapter ++ * should be the offset of EDID word address. ++ */ ++ if (msgs->len != 1 || ++ (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) ++ return -EINVAL; ++ ++ reinit_completion(&hdmi->i2c->cmp); ++ ++ if (msgs->addr == DDC_SEGMENT_ADDR) ++ hdmi->i2c->segment_addr = msgs->buf[0]; ++ if (msgs->addr == DDC_ADDR) ++ hdmi->i2c->ddc_addr = msgs->buf[0]; ++ ++ /* Set edid fifo first addr */ ++ hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); ++ ++ /* Set edid word address 0x00/0x80 */ ++ hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); ++ ++ /* Set edid segment pointer */ ++ hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); ++ ++ return 0; ++} ++ ++static int starfive_hdmi_i2c_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct starfive_hdmi *hdmi = i2c_get_adapdata(adap); ++ struct starfive_hdmi_i2c *i2c = hdmi->i2c; ++ int i, ret = 0; ++ ++ mutex_lock(&i2c->lock); ++ ++ /* Clear the EDID interrupt flag and unmute the interrupt */ ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); ++ ++ for (i = 0; i < num; i++) { ++ DRM_DEV_DEBUG(hdmi->dev, ++ "xfer: num: %d/%d, len: %d, flags: %#x\n", ++ i + 1, num, msgs[i].len, msgs[i].flags); ++ ++ if (msgs[i].flags & I2C_M_RD) ++ ret = starfive_hdmi_i2c_read(hdmi, &msgs[i]); ++ else ++ ret = starfive_hdmi_i2c_write(hdmi, &msgs[i]); ++ ++ if (ret < 0) ++ break; ++ } ++ ++ if (!ret) ++ ret = num; ++ ++ /* Mute HDMI EDID interrupt */ ++ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); ++ ++ mutex_unlock(&i2c->lock); ++ ++ return ret; ++} ++ ++static u32 starfive_hdmi_i2c_func(struct i2c_adapter *adapter) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; ++} ++ ++static const struct i2c_algorithm starfive_hdmi_algorithm = { ++ .master_xfer = starfive_hdmi_i2c_xfer, ++ .functionality = starfive_hdmi_i2c_func, ++}; ++ ++static struct i2c_adapter *starfive_hdmi_i2c_adapter(struct starfive_hdmi *hdmi) ++{ ++ struct i2c_adapter *adap; ++ struct starfive_hdmi_i2c *i2c; ++ int ret; ++ ++ i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); ++ if (!i2c) ++ return ERR_PTR(-ENOMEM); ++ ++ mutex_init(&i2c->lock); ++ init_completion(&i2c->cmp); ++ ++ adap = &i2c->adap; ++ adap->class = I2C_CLASS_DDC; ++ adap->owner = THIS_MODULE; ++ adap->dev.parent = hdmi->dev; ++ adap->algo = &starfive_hdmi_algorithm; ++ strscpy(adap->name, "Starfive HDMI", sizeof(adap->name)); ++ i2c_set_adapdata(adap, hdmi); ++ ++ ret = i2c_add_adapter(adap); ++ if (ret) { ++ dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); ++ devm_kfree(hdmi->dev, i2c); ++ return ERR_PTR(ret); ++ } ++ ++ hdmi->i2c = i2c; ++ ++ DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver success\n", adap->name); ++ ++ return adap; ++} ++ ++static int starfive_hdmi_get_clk_rst(struct device *dev, struct starfive_hdmi *hdmi) ++{ ++ hdmi->sys_clk = devm_clk_get(dev, "sysclk"); ++ if (IS_ERR(hdmi->sys_clk)) { ++ DRM_DEV_ERROR(dev, "Unable to get HDMI sysclk clk\n"); ++ return PTR_ERR(hdmi->sys_clk); ++ } ++ hdmi->mclk = devm_clk_get(dev, "mclk"); ++ if (IS_ERR(hdmi->mclk)) { ++ DRM_DEV_ERROR(dev, "Unable to get HDMI mclk clk\n"); ++ return PTR_ERR(hdmi->mclk); ++ } ++ hdmi->bclk = devm_clk_get(dev, "bclk"); ++ if (IS_ERR(hdmi->bclk)) { ++ DRM_DEV_ERROR(dev, "Unable to get HDMI bclk clk\n"); ++ return PTR_ERR(hdmi->bclk); ++ } ++ hdmi->tx_rst = reset_control_get_shared(dev, "hdmi_tx"); ++ if (IS_ERR(hdmi->tx_rst)) { ++ DRM_DEV_ERROR(dev, "Unable to get HDMI tx rst\n"); ++ return PTR_ERR(hdmi->tx_rst); ++ } ++ return 0; ++} ++ ++static int starfive_hdmi_bind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ struct drm_device *drm = data; ++ struct starfive_hdmi *hdmi; ++ struct resource *iores; ++ int irq; ++ int ret; ++ ++ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); ++ if (!hdmi) ++ return -ENOMEM; ++ ++ hdmi->dev = dev; ++ hdmi->drm_dev = drm; ++ ++ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ hdmi->regs = devm_ioremap_resource(dev, iores); ++ if (IS_ERR(hdmi->regs)) ++ return PTR_ERR(hdmi->regs); ++ ++ ret = starfive_hdmi_get_clk_rst(dev, hdmi); ++ ret = starfive_hdmi_enable_clk_deassert_rst(dev, hdmi); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ ret = irq; ++ goto err_disable_clk; ++ } ++ ++ hdmi->ddc = starfive_hdmi_i2c_adapter(hdmi); ++ if (IS_ERR(hdmi->ddc)) { ++ ret = PTR_ERR(hdmi->ddc); ++ hdmi->ddc = NULL; ++ goto err_disable_clk; ++ } ++ ++ hdmi->tmds_rate = clk_get_rate(hdmi->sys_clk); ++ ++ starfive_hdmi_i2c_init(hdmi); ++ ++ ret = starfive_hdmi_register(drm, hdmi); ++ if (ret) ++ goto err_put_adapter; ++ ++ dev_set_drvdata(dev, hdmi); ++ ++ /* Unmute hotplug interrupt */ ++ hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); ++ ++ ret = devm_request_threaded_irq(dev, irq, starfive_hdmi_hardirq, ++ starfive_hdmi_irq, IRQF_SHARED, ++ dev_name(dev), hdmi); ++ if (ret < 0) ++ goto err_cleanup_hdmi; ++ ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_set_autosuspend_delay(&pdev->dev, 500); ++ pm_runtime_enable(&pdev->dev); ++ ++ starfive_hdmi_disable_clk_assert_rst(dev, hdmi); ++ ++ return 0; ++err_cleanup_hdmi: ++ hdmi->connector.funcs->destroy(&hdmi->connector); ++ hdmi->encoder.funcs->destroy(&hdmi->encoder); ++err_put_adapter: ++ i2c_put_adapter(hdmi->ddc); ++err_disable_clk: ++ clk_disable_unprepare(hdmi->sys_clk); ++ clk_disable_unprepare(hdmi->mclk); ++ clk_disable_unprepare(hdmi->bclk); ++ ++ return ret; ++} ++ ++static void starfive_hdmi_unbind(struct device *dev, struct device *master, ++ void *data) ++{ ++ struct starfive_hdmi *hdmi = dev_get_drvdata(dev); ++ ++ hdmi->connector.funcs->destroy(&hdmi->connector); ++ hdmi->encoder.funcs->destroy(&hdmi->encoder); ++ ++ i2c_put_adapter(hdmi->ddc); ++ ++ starfive_hdmi_disable_clk_assert_rst(dev, hdmi); ++} ++ ++static const struct component_ops starfive_hdmi_ops = { ++ .bind = starfive_hdmi_bind, ++ .unbind = starfive_hdmi_unbind, ++}; ++ ++static int starfive_hdmi_probe(struct platform_device *pdev) ++{ ++ return component_add(&pdev->dev, &starfive_hdmi_ops); ++} ++ ++static int starfive_hdmi_remove(struct platform_device *pdev) ++{ ++ component_del(&pdev->dev, &starfive_hdmi_ops); ++ ++ return 0; ++} ++ ++static const struct dev_pm_ops hdmi_pm_ops = { ++ SET_RUNTIME_PM_OPS(hdmi_runtime_suspend, hdmi_runtime_resume, NULL) ++ SET_LATE_SYSTEM_SLEEP_PM_OPS(hdmi_system_pm_suspend, hdmi_system_pm_resume) ++}; ++ ++static const struct of_device_id starfive_hdmi_dt_ids[] = { ++ { .compatible = "starfive,hdmi", ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, starfive_hdmi_dt_ids); ++ ++struct platform_driver starfive_hdmi_driver = { ++ .probe = starfive_hdmi_probe, ++ .remove = starfive_hdmi_remove, ++ .driver = { ++ .name = "starfive-hdmi", ++ .of_match_table = starfive_hdmi_dt_ids, ++ .pm = &hdmi_pm_ops, ++ }, ++}; ++ ++MODULE_AUTHOR("StarFive Corporation"); ++MODULE_DESCRIPTION("Starfive HDMI Driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/gpu/drm/verisilicon/starfive_hdmi.h b/drivers/gpu/drm/verisilicon/starfive_hdmi.h +new file mode 100644 +index 000000000000..d151c61f9a3e +--- /dev/null ++++ b/drivers/gpu/drm/verisilicon/starfive_hdmi.h +@@ -0,0 +1,296 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ */ ++ ++#ifndef __STARFIVE_HDMI_H__ ++#define __STARFIVE_HDMI_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DDC_SEGMENT_ADDR 0x30 ++ ++#define HDMI_SCL_RATE (100 * 1000) ++#define DDC_BUS_FREQ_L 0x4b ++#define DDC_BUS_FREQ_H 0x4c ++ ++#define HDMI_SYS_CTRL 0x00 ++#define m_RST_ANALOG BIT(6) ++#define v_RST_ANALOG 0 ++#define v_NOT_RST_ANALOG BIT(6) ++#define m_RST_DIGITAL BIT(5) ++#define v_RST_DIGITAL 0 ++#define v_NOT_RST_DIGITAL BIT(5) ++#define m_REG_CLK_INV BIT(4) ++#define v_REG_CLK_NOT_INV 0 ++#define v_REG_CLK_INV BIT(4) ++#define m_VCLK_INV BIT(3) ++#define v_VCLK_NOT_INV 0 ++#define v_VCLK_INV BIT(3) ++#define m_REG_CLK_SOURCE BIT(2) ++#define v_REG_CLK_SOURCE_TMDS 0 ++#define v_REG_CLK_SOURCE_SYS BIT(2) ++#define m_POWER BIT(1) ++#define v_PWR_ON 0 ++#define v_PWR_OFF BIT(1) ++#define m_INT_POL BIT(0) ++#define v_INT_POL_HIGH 1 ++#define v_INT_POL_LOW 0 ++ ++#define HDMI_AV_MUTE 0x05 ++#define m_AVMUTE_CLEAR BIT(7) ++#define m_AVMUTE_ENABLE BIT(6) ++#define m_AUDIO_MUTE BIT(1) ++#define m_VIDEO_BLACK BIT(0) ++#define v_AVMUTE_CLEAR(n) ((n) << 7) ++#define v_AVMUTE_ENABLE(n) ((n) << 6) ++#define v_AUDIO_MUTE(n) ((n) << 1) ++#define v_VIDEO_MUTE(n) ((n) << 0) ++ ++#define HDMI_VIDEO_TIMING_CTL 0x08 ++#define v_VSYNC_POLARITY(n) ((n) << 3) ++#define v_HSYNC_POLARITY(n) ((n) << 2) ++#define v_INETLACE(n) ((n) << 1) ++#define v_EXTERANL_VIDEO(n) ((n) << 0) ++ ++#define HDMI_VIDEO_EXT_HTOTAL_L 0x09 ++#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a ++#define HDMI_VIDEO_EXT_HBLANK_L 0x0b ++#define HDMI_VIDEO_EXT_HBLANK_H 0x0c ++#define HDMI_VIDEO_EXT_HDELAY_L 0x0d ++#define HDMI_VIDEO_EXT_HDELAY_H 0x0e ++#define HDMI_VIDEO_EXT_HDURATION_L 0x0f ++#define HDMI_VIDEO_EXT_HDURATION_H 0x10 ++#define HDMI_VIDEO_EXT_VTOTAL_L 0x11 ++#define HDMI_VIDEO_EXT_VTOTAL_H 0x12 ++#define HDMI_VIDEO_EXT_VBLANK 0x13 ++#define HDMI_VIDEO_EXT_VDELAY 0x14 ++#define HDMI_VIDEO_EXT_VDURATION 0x15 ++ ++#define HDMI_EDID_SEGMENT_POINTER 0x4d ++#define HDMI_EDID_WORD_ADDR 0x4e ++#define HDMI_EDID_FIFO_OFFSET 0x4f ++#define HDMI_EDID_FIFO_ADDR 0x50 ++ ++#define HDMI_INTERRUPT_MASK1 0xc0 ++#define HDMI_INTERRUPT_STATUS1 0xc1 ++#define m_INT_ACTIVE_VSYNC BIT(5) ++#define m_INT_EDID_READY BIT(2) ++ ++#define HDMI_STATUS 0xc8 ++#define m_HOTPLUG BIT(7) ++#define m_MASK_INT_HOTPLUG BIT(5) ++#define m_INT_HOTPLUG BIT(1) ++#define v_MASK_INT_HOTPLUG(n) (((n) & 0x1) << 5) ++ ++#define HDMI_SYNC 0xce ++ ++#define UPDATE(x, h, l)\ ++({\ ++ typeof(x) x_ = (x);\ ++ typeof(h) h_ = (h);\ ++ typeof(l) l_ = (l);\ ++ (((x_) << (l_)) & GENMASK((h_), (l_)));\ ++}) ++ ++/* REG: 0x1a0 */ ++#define STARFIVE_PRE_PLL_CONTROL 0x1a0 ++#define STARFIVE_PCLK_VCO_DIV_5_MASK BIT(1) ++#define STARFIVE_PCLK_VCO_DIV_5(x) UPDATE(x, 1, 1) ++#define STARFIVE_PRE_PLL_POWER_DOWN BIT(0) ++ ++/* REG: 0x1a1 */ ++#define STARFIVE_PRE_PLL_DIV_1 0x1a1 ++#define STARFIVE_PRE_PLL_PRE_DIV_MASK GENMASK(5, 0) ++#define STARFIVE_PRE_PLL_PRE_DIV(x) UPDATE(x, 5, 0) ++ ++/* REG: 0x1a2 */ ++#define STARFIVE_PRE_PLL_DIV_2 0x1a2 ++#define STARFIVE_SPREAD_SPECTRUM_MOD_DOWN BIT(7) ++#define STARFIVE_SPREAD_SPECTRUM_MOD_DISABLE BIT(6) ++#define STARFIVE_PRE_PLL_FRAC_DIV_DISABLE UPDATE(3, 5, 4) ++#define STARFIVE_PRE_PLL_FB_DIV_11_8_MASK GENMASK(3, 0) ++#define STARFIVE_PRE_PLL_FB_DIV_11_8(x) UPDATE((x) >> 8, 3, 0) ++ ++/* REG: 0x1a3 */ ++#define STARFIVE_PRE_PLL_DIV_3 0x1a3 ++#define STARFIVE_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) ++ ++/* REG: 0x1a4*/ ++#define STARFIVE_PRE_PLL_DIV_4 0x1a4 ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(1, 0) ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 1, 0) ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(3, 2) ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 3, 2) ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(5, 4) ++#define STARFIVE_PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 5, 4) ++ ++/* REG: 0x1a5 */ ++#define STARFIVE_PRE_PLL_DIV_5 0x1a5 ++#define STARFIVE_PRE_PLL_PCLK_DIV_B_SHIFT 5 ++#define STARFIVE_PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5) ++#define STARFIVE_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5) ++#define STARFIVE_PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0) ++#define STARFIVE_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0) ++ ++/* REG: 0x1a6 */ ++#define STARFIVE_PRE_PLL_DIV_6 0x1a6 ++#define STARFIVE_PRE_PLL_PCLK_DIV_C_SHIFT 5 ++#define STARFIVE_PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5) ++#define STARFIVE_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5) ++#define STARFIVE_PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0) ++#define STARFIVE_PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0) ++ ++/* REG: 0x1a9 */ ++#define STARFIVE_PRE_PLL_LOCK_STATUS 0x1a9 ++ ++/* REG: 0x1aa */ ++#define STARFIVE_POST_PLL_DIV_1 0x1aa ++#define STARFIVE_POST_PLL_POST_DIV_ENABLE GENMASK(3, 2) ++#define STARFIVE_POST_PLL_REFCLK_SEL_TMDS BIT(1) ++#define STARFIVE_POST_PLL_POWER_DOWN BIT(0) ++#define STARFIVE_POST_PLL_FB_DIV_8(x) UPDATE(((x) >> 8) << 4, 4, 4) ++ ++/* REG:0x1ab */ ++#define STARFIVE_POST_PLL_DIV_2 0x1ab ++#define STARFIVE_POST_PLL_Pre_DIV_MASK GENMASK(5, 0) ++#define STARFIVE_POST_PLL_PRE_DIV(x) UPDATE(x, 5, 0) ++ ++/* REG: 0x1ac */ ++#define STARFIVE_POST_PLL_DIV_3 0x1ac ++#define STARFIVE_POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0) ++ ++/* REG: 0x1ad */ ++#define STARFIVE_POST_PLL_DIV_4 0x1ad ++#define STARFIVE_POST_PLL_POST_DIV_MASK GENMASK(2, 0) ++#define STARFIVE_POST_PLL_POST_DIV_2 0x0 ++#define STARFIVE_POST_PLL_POST_DIV_4 0x1 ++#define STARFIVE_POST_PLL_POST_DIV_8 0x3 ++ ++/* REG: 0x1af */ ++#define STARFIVE_POST_PLL_LOCK_STATUS 0x1af ++ ++/* REG: 0x1b0 */ ++#define STARFIVE_BIAS_CONTROL 0x1b0 ++#define STARFIVE_BIAS_ENABLE BIT(2) ++ ++/* REG: 0x1b2 */ ++#define STARFIVE_TMDS_CONTROL 0x1b2 ++#define STARFIVE_TMDS_CLK_DRIVER_EN BIT(3) ++#define STARFIVE_TMDS_D2_DRIVER_EN BIT(2) ++#define STARFIVE_TMDS_D1_DRIVER_EN BIT(1) ++#define STARFIVE_TMDS_D0_DRIVER_EN BIT(0) ++#define STARFIVE_TMDS_DRIVER_ENABLE (STARFIVE_TMDS_CLK_DRIVER_EN | \ ++ STARFIVE_TMDS_D2_DRIVER_EN | \ ++ STARFIVE_TMDS_D1_DRIVER_EN | \ ++ STARFIVE_TMDS_D0_DRIVER_EN) ++ ++/* REG: 0x1b4 */ ++#define STARFIVE_LDO_CONTROL 0x1b4 ++#define STARFIVE_LDO_D2_EN BIT(2) ++#define STARFIVE_LDO_D1_EN BIT(1) ++#define STARFIVE_LDO_D0_EN BIT(0) ++#define STARFIVE_LDO_ENABLE (STARFIVE_LDO_D2_EN | \ ++ STARFIVE_LDO_D1_EN | \ ++ STARFIVE_LDO_D0_EN) ++ ++/* REG: 0x1be */ ++#define STARFIVE_SERIALIER_CONTROL 0x1be ++#define STARFIVE_SERIALIER_D2_EN BIT(6) ++#define STARFIVE_SERIALIER_D1_EN BIT(5) ++#define STARFIVE_SERIALIER_D0_EN BIT(4) ++#define STARFIVE_SERIALIER_ENABLE (STARFIVE_SERIALIER_D2_EN | \ ++ STARFIVE_SERIALIER_D1_EN | \ ++ STARFIVE_SERIALIER_D0_EN) ++ ++/* REG: 0x1cc */ ++#define STARFIVE_RX_CONTROL 0x1cc ++#define STARFIVE_RX_EN BIT(3) ++#define STARFIVE_RX_CHANNEL_2_EN BIT(2) ++#define STARFIVE_RX_CHANNEL_1_EN BIT(1) ++#define STARFIVE_RX_CHANNEL_0_EN BIT(0) ++#define STARFIVE_RX_ENABLE (STARFIVE_RX_EN | \ ++ STARFIVE_RX_CHANNEL_2_EN | \ ++ STARFIVE_RX_CHANNEL_1_EN | \ ++ STARFIVE_RX_CHANNEL_0_EN) ++ ++/* REG: 0x1d1 */ ++#define STARFIVE_PRE_PLL_FRAC_DIV_H 0x1d1 ++#define STARFIVE_PRE_PLL_FRAC_DIV_23_16(x) UPDATE((x) >> 16, 7, 0) ++/* REG: 0x1d2 */ ++#define STARFIVE_PRE_PLL_FRAC_DIV_M 0x1d2 ++#define STARFIVE_PRE_PLL_FRAC_DIV_15_8(x) UPDATE((x) >> 8, 7, 0) ++/* REG: 0x1d3 */ ++#define STARFIVE_PRE_PLL_FRAC_DIV_L 0x1d3 ++#define STARFIVE_PRE_PLL_FRAC_DIV_7_0(x) UPDATE(x, 7, 0) ++ ++struct pre_pll_config { ++ unsigned long pixclock; ++ unsigned long tmdsclock; ++ u8 prediv; ++ u16 fbdiv; ++ u8 tmds_div_a; ++ u8 tmds_div_b; ++ u8 tmds_div_c; ++ u8 pclk_div_a; ++ u8 pclk_div_b; ++ u8 pclk_div_c; ++ u8 pclk_div_d; ++ u8 vco_div_5_en; ++ u32 fracdiv; ++}; ++ ++struct post_pll_config { ++ unsigned long tmdsclock; ++ u8 prediv; ++ u16 fbdiv; ++ u8 postdiv; ++ u8 post_div_en; ++ u8 version; ++}; ++ ++struct phy_config { ++ unsigned long tmdsclock; ++ u8 regs[14]; ++}; ++ ++struct hdmi_data_info { ++ int vic; ++ bool sink_is_hdmi; ++ bool sink_has_audio; ++ unsigned int enc_in_format; ++ unsigned int enc_out_format; ++ unsigned int colorimetry; ++}; ++ ++struct starfive_hdmi { ++ struct device *dev; ++ struct drm_device *drm_dev; ++ ++ int irq; ++ struct clk *sys_clk; ++ struct clk *mclk; ++ struct clk *bclk; ++ struct reset_control *tx_rst; ++ void __iomem *regs; ++ ++ struct drm_connector connector; ++ struct drm_encoder encoder; ++ ++ struct starfive_hdmi_i2c *i2c; ++ struct i2c_adapter *ddc; ++ ++ unsigned long tmds_rate; ++ ++ struct hdmi_data_info hdmi_data; ++ struct drm_display_mode previous_mode; ++ const struct pre_pll_config *pre_cfg; ++ const struct post_pll_config *post_cfg; ++}; ++ ++#endif /* __STARFIVE_HDMI_H__ */ +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index c28bfd74ffc9..b740fe934035 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -183,6 +183,12 @@ static const struct component_master_ops vs_drm_ops = { + + static struct platform_driver *drm_sub_drivers[] = { + &dc_platform_driver, ++ ++ /* connector + encoder*/ ++#ifdef CONFIG_STARFIVE_HDMI ++ &starfive_hdmi_driver, ++#endif ++ + }; + + #define NUM_DRM_DRIVERS \ +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.h b/drivers/gpu/drm/verisilicon/vs_drv.h +index 0382b44e3bf0..3668e1d65b3f 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.h ++++ b/drivers/gpu/drm/verisilicon/vs_drv.h +@@ -45,4 +45,8 @@ static inline bool is_iommu_enabled(struct drm_device *dev) + return priv->domain ? true : false; + } + ++#ifdef CONFIG_STARFIVE_HDMI ++extern struct platform_driver starfive_hdmi_driver; ++#endif ++ + #endif /* __VS_DRV_H__ */ +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0058-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch b/srcpkgs/linux6.4/patches/0058-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch new file mode 100644 index 0000000000000..1ea1a89e094ed --- /dev/null +++ b/srcpkgs/linux6.4/patches/0058-dt-bindings-usb-Add-StarFive-JH7110-USB-controller.patch @@ -0,0 +1,141 @@ +From 97de0003979a97f67584f5b5845ffb30cac97ca3 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 18 May 2023 19:27:48 +0800 +Subject: [PATCH 58/72] dt-bindings: usb: Add StarFive JH7110 USB controller + +StarFive JH7110 platforms USB have a wrapper module around +the Cadence USBSS-DRD controller. Add binding information doc +for that. + +Signed-off-by: Minda Chen +Reviewed-by: Peter Chen +Reviewed-by: Hal Feng +--- + .../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++ + 1 file changed, 115 insertions(+) + create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml + +diff --git a/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml +new file mode 100644 +index 000000000000..24aa9c10d6ab +--- /dev/null ++++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml +@@ -0,0 +1,115 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-usb ++ ++ ranges: true ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for USB. ++ ++ dr_mode: ++ enum: [host, otg, peripheral] ++ ++ "#address-cells": ++ enum: [1, 2] ++ ++ "#size-cells": ++ enum: [1, 2] ++ ++ clocks: ++ items: ++ - description: link power management clock ++ - description: standby clock ++ - description: APB clock ++ - description: AXI clock ++ - description: UTMI APB clock ++ ++ clock-names: ++ items: ++ - const: lpm ++ - const: stb ++ - const: apb ++ - const: axi ++ - const: utmi_apb ++ ++ resets: ++ items: ++ - description: Power up reset ++ - description: APB clock reset ++ - description: AXI clock reset ++ - description: UTMI APB clock reset ++ ++ reset-names: ++ items: ++ - const: pwrup ++ - const: apb ++ - const: axi ++ - const: utmi_apb ++ ++patternProperties: ++ "^usb@[0-9a-f]+$": ++ $ref: cdns,usb3.yaml# ++ description: Required child node ++ ++required: ++ - compatible ++ - ranges ++ - starfive,stg-syscon ++ - '#address-cells' ++ - '#size-cells' ++ - dr_mode ++ - clocks ++ - resets ++ ++additionalProperties: false ++ ++examples: ++ - | ++ usb@10100000 { ++ compatible = "starfive,jh7110-usb"; ++ ranges = <0x0 0x10100000 0x100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ starfive,stg-syscon = <&stg_syscon 0x4>; ++ clocks = <&syscrg 4>, ++ <&stgcrg 5>, ++ <&stgcrg 1>, ++ <&stgcrg 3>, ++ <&stgcrg 2>; ++ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; ++ resets = <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 7>, ++ <&stgcrg 9>; ++ reset-names = "pwrup", "apb", "axi", "utmi_apb"; ++ dr_mode = "host"; ++ ++ usb@0 { ++ compatible = "cdns,usb3"; ++ reg = <0x0 0x10000>, ++ <0x10000 0x10000>, ++ <0x20000 0x10000>; ++ reg-names = "otg", "xhci", "dev"; ++ interrupts = <100>, <108>, <110>; ++ interrupt-names = "host", "peripheral", "otg"; ++ maximum-speed = "super-speed"; ++ }; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0059-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch b/srcpkgs/linux6.4/patches/0059-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch new file mode 100644 index 0000000000000..123bab1c458f1 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0059-usb-cdns3-Add-StarFive-JH7110-USB-driver.patch @@ -0,0 +1,308 @@ +From 1ae1f90b42a3bc8724d2979690413e226a2b0540 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 18 May 2023 19:27:49 +0800 +Subject: [PATCH 59/72] usb: cdns3: Add StarFive JH7110 USB driver + +Adds Specific Glue layer to support USB peripherals on +StarFive JH7110 SoC. +There is a Cadence USB3 core for JH7110 SoCs, the cdns +core is the child of this USB wrapper module device. + +Signed-off-by: Minda Chen +Acked-by: Peter Chen +--- + drivers/usb/cdns3/Kconfig | 11 ++ + drivers/usb/cdns3/Makefile | 1 + + drivers/usb/cdns3/cdns3-starfive.c | 246 +++++++++++++++++++++++++++++ + 3 files changed, 258 insertions(+) + create mode 100644 drivers/usb/cdns3/cdns3-starfive.c + +diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig +index b98ca0a1352a..0a514b591527 100644 +--- a/drivers/usb/cdns3/Kconfig ++++ b/drivers/usb/cdns3/Kconfig +@@ -78,6 +78,17 @@ config USB_CDNS3_IMX + + For example, imx8qm and imx8qxp. + ++config USB_CDNS3_STARFIVE ++ tristate "Cadence USB3 support on StarFive SoC platforms" ++ depends on ARCH_STARFIVE || COMPILE_TEST ++ help ++ Say 'Y' or 'M' here if you are building for StarFive SoCs ++ platforms that contain Cadence USB3 controller core. ++ ++ e.g. JH7110. ++ ++ If you choose to build this driver as module it will ++ be dynamically linked and module will be called cdns3-starfive.ko + endif + + if USB_CDNS_SUPPORT +diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile +index 61edb2f89276..48dfae75b5aa 100644 +--- a/drivers/usb/cdns3/Makefile ++++ b/drivers/usb/cdns3/Makefile +@@ -24,6 +24,7 @@ endif + obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o + obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o + obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o ++obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o + + cdnsp-udc-pci-y := cdnsp-pci.o + +diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c +new file mode 100644 +index 000000000000..fc1f003b145d +--- /dev/null ++++ b/drivers/usb/cdns3/cdns3-starfive.c +@@ -0,0 +1,246 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/** ++ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "core.h" ++ ++#define USB_STRAP_HOST BIT(17) ++#define USB_STRAP_DEVICE BIT(18) ++#define USB_STRAP_MASK GENMASK(18, 16) ++ ++#define USB_SUSPENDM_HOST BIT(19) ++#define USB_SUSPENDM_MASK BIT(19) ++ ++#define USB_MISC_CFG_MASK GENMASK(23, 20) ++#define USB_SUSPENDM_BYPS BIT(20) ++#define USB_PLL_EN BIT(22) ++#define USB_REFCLK_MODE BIT(23) ++ ++struct cdns_starfive { ++ struct device *dev; ++ struct regmap *stg_syscon; ++ struct reset_control *resets; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ u32 stg_usb_mode; ++}; ++ ++static void cdns_mode_init(struct platform_device *pdev, ++ struct cdns_starfive *data) ++{ ++ enum usb_dr_mode mode; ++ ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_MISC_CFG_MASK, ++ USB_SUSPENDM_BYPS | USB_PLL_EN | USB_REFCLK_MODE); ++ ++ /* dr mode setting */ ++ mode = usb_get_dr_mode(&pdev->dev); ++ ++ switch (mode) { ++ case USB_DR_MODE_HOST: ++ regmap_update_bits(data->stg_syscon, ++ data->stg_usb_mode, ++ USB_STRAP_MASK, ++ USB_STRAP_HOST); ++ regmap_update_bits(data->stg_syscon, ++ data->stg_usb_mode, ++ USB_SUSPENDM_MASK, ++ USB_SUSPENDM_HOST); ++ break; ++ ++ case USB_DR_MODE_PERIPHERAL: ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_STRAP_MASK, USB_STRAP_DEVICE); ++ regmap_update_bits(data->stg_syscon, data->stg_usb_mode, ++ USB_SUSPENDM_MASK, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++static int cdns_clk_rst_init(struct cdns_starfive *data) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare_enable(data->num_clks, data->clks); ++ if (ret) ++ return dev_err_probe(data->dev, ret, ++ "failed to enable clocks\n"); ++ ++ ret = reset_control_deassert(data->resets); ++ if (ret) { ++ dev_err(data->dev, "failed to reset clocks\n"); ++ goto err_clk_init; ++ } ++ ++ return ret; ++ ++err_clk_init: ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++ return ret; ++} ++ ++static void cdns_clk_rst_deinit(struct cdns_starfive *data) ++{ ++ reset_control_assert(data->resets); ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++} ++ ++static int cdns_starfive_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct cdns_starfive *data; ++ unsigned int args; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ data->dev = dev; ++ ++ data->stg_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", 1, &args); ++ ++ if (IS_ERR(data->stg_syscon)) ++ return dev_err_probe(dev, PTR_ERR(data->stg_syscon), ++ "Failed to parse starfive,stg-syscon\n"); ++ ++ data->stg_usb_mode = args; ++ ++ data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks); ++ if (data->num_clks < 0) ++ return dev_err_probe(data->dev, -ENODEV, ++ "Failed to get clocks\n"); ++ ++ data->resets = devm_reset_control_array_get_exclusive(data->dev); ++ if (IS_ERR(data->resets)) ++ return dev_err_probe(data->dev, PTR_ERR(data->resets), ++ "Failed to get resets"); ++ ++ cdns_mode_init(pdev, data); ++ ret = cdns_clk_rst_init(data); ++ if (ret) ++ return ret; ++ ++ ret = of_platform_populate(dev->of_node, NULL, NULL, dev); ++ if (ret) { ++ dev_err(dev, "Failed to create children\n"); ++ cdns_clk_rst_deinit(data); ++ return ret; ++ } ++ ++ device_set_wakeup_capable(dev, true); ++ pm_runtime_set_active(dev); ++ pm_runtime_enable(dev); ++ platform_set_drvdata(pdev, data); ++ ++ return 0; ++} ++ ++static int cdns_starfive_remove_core(struct device *dev, void *c) ++{ ++ struct platform_device *pdev = to_platform_device(dev); ++ ++ platform_device_unregister(pdev); ++ ++ return 0; ++} ++ ++static int cdns_starfive_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ pm_runtime_get_sync(dev); ++ device_for_each_child(dev, NULL, cdns_starfive_remove_core); ++ ++ pm_runtime_disable(dev); ++ pm_runtime_put_noidle(dev); ++ cdns_clk_rst_deinit(data); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int cdns_starfive_runtime_resume(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ return clk_bulk_prepare_enable(data->num_clks, data->clks); ++} ++ ++static int cdns_starfive_runtime_suspend(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ clk_bulk_disable_unprepare(data->num_clks, data->clks); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int cdns_starfive_resume(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ return cdns_clk_rst_init(data); ++} ++ ++static int cdns_starfive_suspend(struct device *dev) ++{ ++ struct cdns_starfive *data = dev_get_drvdata(dev); ++ ++ cdns_clk_rst_deinit(data); ++ ++ return 0; ++} ++#endif ++#endif ++ ++static const struct dev_pm_ops cdns_starfive_pm_ops = { ++ SET_RUNTIME_PM_OPS(cdns_starfive_runtime_suspend, ++ cdns_starfive_runtime_resume, NULL) ++ SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume) ++}; ++ ++static const struct of_device_id cdns_starfive_of_match[] = { ++ { .compatible = "starfive,jh7110-usb", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, cdns_starfive_of_match); ++ ++static struct platform_driver cdns_starfive_driver = { ++ .probe = cdns_starfive_probe, ++ .remove = cdns_starfive_remove, ++ .driver = { ++ .name = "cdns3-starfive", ++ .of_match_table = cdns_starfive_of_match, ++ .pm = &cdns_starfive_pm_ops, ++ }, ++}; ++module_platform_driver(cdns_starfive_driver); ++ ++MODULE_ALIAS("platform:cdns3-starfive"); ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0060-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch b/srcpkgs/linux6.4/patches/0060-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch new file mode 100644 index 0000000000000..20073aa53a20d --- /dev/null +++ b/srcpkgs/linux6.4/patches/0060-dt-bindings-phy-Add-StarFive-JH7110-USB-PHY.patch @@ -0,0 +1,75 @@ +From cf8ea126d15e92734daeaaa51feaf86daaf20ed8 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 29 Jun 2023 15:51:11 +0800 +Subject: [PATCH 60/72] dt-bindings: phy: Add StarFive JH7110 USB PHY + +Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Rob Herring +Reviewed-by: Roger Quadros +--- + .../bindings/phy/starfive,jh7110-usb-phy.yaml | 50 +++++++++++++++++++ + 1 file changed, 50 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +new file mode 100644 +index 000000000000..269e9f9f12b6 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml +@@ -0,0 +1,50 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 USB 2.0 PHY ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-usb-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ clocks: ++ items: ++ - description: PHY 125m ++ - description: app 125m ++ ++ clock-names: ++ items: ++ - const: 125m ++ - const: app_125m ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@10200000 { ++ compatible = "starfive,jh7110-usb-phy"; ++ reg = <0x10200000 0x10000>; ++ clocks = <&syscrg 95>, ++ <&stgcrg 6>; ++ clock-names = "125m", "app_125m"; ++ #phy-cells = <0>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0061-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch b/srcpkgs/linux6.4/patches/0061-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch new file mode 100644 index 0000000000000..07a4bf0e8f848 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0061-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch @@ -0,0 +1,84 @@ +From f1838320165c05509a1e0408f3521c72442f24ed Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 29 Jun 2023 15:51:12 +0800 +Subject: [PATCH 61/72] dt-bindings: phy: Add StarFive JH7110 PCIe PHY + +Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding. +PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY. + +Signed-off-by: Minda Chen +Reviewed-by: Hal Feng +Reviewed-by: Rob Herring +Reviewed-by: Roger Quadros +--- + .../phy/starfive,jh7110-pcie-phy.yaml | 58 +++++++++++++++++++ + 1 file changed, 58 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml +new file mode 100644 +index 000000000000..2e83a6164cd1 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml +@@ -0,0 +1,58 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe 2.0 PHY ++ ++maintainers: ++ - Minda Chen ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie-phy ++ ++ reg: ++ maxItems: 1 ++ ++ "#phy-cells": ++ const: 0 ++ ++ starfive,sys-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller sys_syscon node. ++ - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY. ++ description: ++ The phandle to System Register Controller syscon node and the PHY connect offset ++ of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller. ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ - items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register. ++ - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset. ++ ++required: ++ - compatible ++ - reg ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ phy@10210000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x10210000 0x10000>; ++ #phy-cells = <0>; ++ starfive,sys-syscon = <&sys_syscon 0x18>; ++ starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0062-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch b/srcpkgs/linux6.4/patches/0062-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch new file mode 100644 index 0000000000000..30d740e3153e8 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0062-phy-starfive-Add-JH7110-USB-2.0-PHY-driver.patch @@ -0,0 +1,204 @@ +From 807a213dd532964d8fec0ba8540ce4149a378dab Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 29 Jun 2023 15:51:13 +0800 +Subject: [PATCH 62/72] phy: starfive: Add JH7110 USB 2.0 PHY driver + +Add Starfive JH7110 SoC USB 2.0 PHY driver support. +USB 2.0 PHY default connect to Cadence USB controller. + +Signed-off-by: Minda Chen +Reviewed-by: Roger Quadros +--- + drivers/phy/starfive/Kconfig | 10 ++ + drivers/phy/starfive/Makefile | 1 + + drivers/phy/starfive/phy-jh7110-usb.c | 152 ++++++++++++++++++++++++++ + 3 files changed, 163 insertions(+) + create mode 100644 drivers/phy/starfive/phy-jh7110-usb.c + +diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig +index f989b8ff8bcb..c7cdd0dcc1de 100644 +--- a/drivers/phy/starfive/Kconfig ++++ b/drivers/phy/starfive/Kconfig +@@ -11,3 +11,13 @@ config PHY_STARFIVE_DPHY_RX + Choose this option if you have a StarFive D-PHY in your + system. If M is selected, the module will be called + phy-starfive-dphy-rx. ++ ++config PHY_STARFIVE_JH7110_USB ++ tristate "Starfive JH7110 USB 2.0 PHY support" ++ depends on USB_SUPPORT ++ select GENERIC_PHY ++ help ++ Enable this to support the StarFive USB 2.0 PHY, ++ used with the Cadence USB controller. ++ If M is selected, the module will be called ++ phy-jh7110-usb.ko. +diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile +index 7ec576cb30ae..176443852f4d 100644 +--- a/drivers/phy/starfive/Makefile ++++ b/drivers/phy/starfive/Makefile +@@ -1,2 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o ++obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o +diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c +new file mode 100644 +index 000000000000..633912f8a05d +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-usb.c +@@ -0,0 +1,152 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 USB 2.0 PHY driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define USB_125M_CLK_RATE 125000000 ++#define USB_LS_KEEPALIVE_OFF 0x4 ++#define USB_LS_KEEPALIVE_ENABLE BIT(4) ++ ++struct jh7110_usb2_phy { ++ struct phy *phy; ++ void __iomem *regs; ++ struct clk *usb_125m_clk; ++ struct clk *app_125m; ++ enum phy_mode mode; ++}; ++ ++static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) ++{ ++ unsigned int val; ++ ++ /* Host mode enable the LS speed keep-alive signal */ ++ val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); ++ if (set) ++ val |= USB_LS_KEEPALIVE_ENABLE; ++ else ++ val &= ~USB_LS_KEEPALIVE_ENABLE; ++ ++ writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); ++} ++ ++static int usb2_phy_set_mode(struct phy *_phy, ++ enum phy_mode mode, int submode) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (mode != phy->mode) { ++ dev_dbg(&_phy->dev, "Changing phy to %d\n", mode); ++ phy->mode = mode; ++ usb2_set_ls_keepalive(phy, (mode != PHY_MODE_USB_DEVICE)); ++ } ++ ++ return 0; ++} ++ ++static int jh7110_usb2_phy_init(struct phy *_phy) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ int ret; ++ ++ ret = clk_set_rate(phy->usb_125m_clk, USB_125M_CLK_RATE); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(phy->app_125m); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int jh7110_usb2_phy_exit(struct phy *_phy) ++{ ++ struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); ++ ++ clk_disable_unprepare(phy->app_125m); ++ ++ return 0; ++} ++ ++static const struct phy_ops jh7110_usb2_phy_ops = { ++ .init = jh7110_usb2_phy_init, ++ .exit = jh7110_usb2_phy_exit, ++ .set_mode = usb2_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static int jh7110_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct jh7110_usb2_phy *phy; ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->usb_125m_clk = devm_clk_get(dev, "125m"); ++ if (IS_ERR(phy->usb_125m_clk)) ++ return dev_err_probe(dev, PTR_ERR(phy->usb_125m_clk), ++ "Failed to get 125m clock\n"); ++ ++ phy->app_125m = devm_clk_get(dev, "app_125m"); ++ if (IS_ERR(phy->app_125m)) ++ return dev_err_probe(dev, PTR_ERR(phy->app_125m), ++ "Failed to get app 125m clock\n"); ++ ++ phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->regs)) ++ return dev_err_probe(dev, PTR_ERR(phy->regs), ++ "Failed to map phy base\n"); ++ ++ phy->phy = devm_phy_create(dev, NULL, &jh7110_usb2_phy_ops); ++ if (IS_ERR(phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(phy->phy), ++ "Failed to create phy\n"); ++ ++ phy_set_drvdata(phy->phy, phy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id jh7110_usb_phy_of_match[] = { ++ { .compatible = "starfive,jh7110-usb-phy" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, jh7110_usb_phy_of_match); ++ ++static struct platform_driver jh7110_usb_phy_driver = { ++ .probe = jh7110_usb_phy_probe, ++ .driver = { ++ .of_match_table = jh7110_usb_phy_of_match, ++ .name = "jh7110-usb-phy", ++ } ++}; ++module_platform_driver(jh7110_usb_phy_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 USB 2.0 PHY driver"); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0063-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch b/srcpkgs/linux6.4/patches/0063-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch new file mode 100644 index 0000000000000..d10e3d57965ee --- /dev/null +++ b/srcpkgs/linux6.4/patches/0063-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch @@ -0,0 +1,261 @@ +From 7495a300a79658d958f707ee1fdc80f0c4cbe899 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 29 Jun 2023 15:51:14 +0800 +Subject: [PATCH 63/72] phy: starfive: Add JH7110 PCIE 2.0 PHY driver + +Add Starfive JH7110 SoC PCIe 2.0 PHY driver support. +PCIe 2.0 PHY default connect to PCIe controller. +PCIe PHY can connect to USB 3.0 controller. + +Signed-off-by: Minda Chen +Reviewed-by: Roger Quadros +--- + drivers/phy/starfive/Kconfig | 10 ++ + drivers/phy/starfive/Makefile | 1 + + drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++++++++++++ + 3 files changed, 215 insertions(+) + create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c + +diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig +index c7cdd0dcc1de..e64c1628a467 100644 +--- a/drivers/phy/starfive/Kconfig ++++ b/drivers/phy/starfive/Kconfig +@@ -12,6 +12,16 @@ config PHY_STARFIVE_DPHY_RX + system. If M is selected, the module will be called + phy-starfive-dphy-rx. + ++config PHY_STARFIVE_JH7110_PCIE ++ tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support" ++ depends on HAS_IOMEM ++ select GENERIC_PHY ++ help ++ Enable this to support the StarFive PCIe 2.0 PHY, ++ or used as USB 3.0 PHY. ++ If M is selected, the module will be called ++ phy-jh7110-pcie.ko. ++ + config PHY_STARFIVE_JH7110_USB + tristate "Starfive JH7110 USB 2.0 PHY support" + depends on USB_SUPPORT +diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile +index 176443852f4d..03a55aad53a2 100644 +--- a/drivers/phy/starfive/Makefile ++++ b/drivers/phy/starfive/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o ++obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o + obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o +diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c +new file mode 100644 +index 000000000000..cbe79c1f59d3 +--- /dev/null ++++ b/drivers/phy/starfive/phy-jh7110-pcie.c +@@ -0,0 +1,204 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * StarFive JH7110 PCIe 2.0 PHY driver ++ * ++ * Copyright (C) 2023 StarFive Technology Co., Ltd. ++ * Author: Minda Chen ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define PCIE_KVCO_LEVEL_OFF 0x28 ++#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c ++#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80 ++#define PCIE_USB3_PHY_ENABLE BIT(4) ++#define PHY_KVCO_FINE_TUNE_LEVEL 0x91 ++#define PHY_KVCO_FINE_TUNE_SIGNALS 0xc ++ ++#define USB_PDRSTN_SPLIT BIT(17) ++ ++#define PCIE_PHY_MODE BIT(20) ++#define PCIE_PHY_MODE_MASK GENMASK(21, 20) ++#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) ++#define PCIE_USB3_BUS_WIDTH BIT(3) ++#define PCIE_USB3_RATE_MASK GENMASK(6, 5) ++#define PCIE_USB3_RX_STANDBY_MASK BIT(7) ++#define PCIE_USB3_PHY_ENABLE BIT(4) ++ ++struct jh7110_pcie_phy { ++ struct phy *phy; ++ struct regmap *stg_syscon; ++ struct regmap *sys_syscon; ++ void __iomem *regs; ++ u32 sys_phy_connect; ++ u32 stg_pcie_mode; ++ u32 stg_pcie_usb; ++ enum phy_mode mode; ++}; ++ ++static int phy_usb3_mode_set(struct jh7110_pcie_phy *data) ++{ ++ if (!data->stg_syscon || !data->sys_syscon) { ++ dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, ++ PCIE_PHY_MODE_MASK, PCIE_PHY_MODE); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_BUS_WIDTH_MASK, 0); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE); ++ ++ /* Connect usb 3.0 phy mode */ ++ regmap_update_bits(data->sys_syscon, data->sys_phy_connect, ++ USB_PDRSTN_SPLIT, 0); ++ ++ /* Configuare spread-spectrum mode: down-spread-spectrum */ ++ writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); ++ ++ return 0; ++} ++ ++static void phy_pcie_mode_set(struct jh7110_pcie_phy *data) ++{ ++ u32 val; ++ ++ /* default is PCIe mode */ ++ if (!data->stg_syscon || !data->sys_syscon) ++ return; ++ ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, ++ PCIE_PHY_MODE_MASK, 0); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_BUS_WIDTH_MASK, ++ PCIE_USB3_BUS_WIDTH); ++ regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, ++ PCIE_USB3_PHY_ENABLE, 0); ++ ++ regmap_update_bits(data->sys_syscon, data->sys_phy_connect, ++ USB_PDRSTN_SPLIT, 0); ++ ++ val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); ++ val &= ~PCIE_USB3_PHY_ENABLE; ++ writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF); ++} ++ ++static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy) ++{ ++ /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */ ++ writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF); ++ writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF); ++} ++ ++static int jh7110_pcie_phy_set_mode(struct phy *_phy, ++ enum phy_mode mode, int submode) ++{ ++ struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy); ++ int ret; ++ ++ if (mode == phy->mode) ++ return 0; ++ ++ switch (mode) { ++ case PHY_MODE_USB_HOST: ++ case PHY_MODE_USB_DEVICE: ++ case PHY_MODE_USB_OTG: ++ ret = phy_usb3_mode_set(phy); ++ if (ret) ++ return ret; ++ break; ++ case PHY_MODE_PCIE: ++ phy_pcie_mode_set(phy); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ dev_dbg(&_phy->dev, "Changing phy mode to %d\n", mode); ++ phy->mode = mode; ++ ++ return 0; ++} ++ ++static const struct phy_ops jh7110_pcie_phy_ops = { ++ .set_mode = jh7110_pcie_phy_set_mode, ++ .owner = THIS_MODULE, ++}; ++ ++static int jh7110_pcie_phy_probe(struct platform_device *pdev) ++{ ++ struct jh7110_pcie_phy *phy; ++ struct device *dev = &pdev->dev; ++ struct phy_provider *phy_provider; ++ u32 args[2]; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (!phy) ++ return -ENOMEM; ++ ++ phy->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(phy->regs)) ++ return PTR_ERR(phy->regs); ++ ++ phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops); ++ if (IS_ERR(phy->phy)) ++ return dev_err_probe(dev, PTR_ERR(phy->regs), ++ "Failed to map phy base\n"); ++ ++ phy->sys_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,sys-syscon", ++ 1, args); ++ ++ if (!IS_ERR_OR_NULL(phy->sys_syscon)) ++ phy->sys_phy_connect = args[0]; ++ else ++ phy->sys_syscon = NULL; ++ ++ phy->stg_syscon = ++ syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", ++ 2, args); ++ ++ if (!IS_ERR_OR_NULL(phy->stg_syscon)) { ++ phy->stg_pcie_mode = args[0]; ++ phy->stg_pcie_usb = args[1]; ++ } else { ++ phy->stg_syscon = NULL; ++ } ++ ++ phy_kvco_gain_set(phy); ++ ++ phy_set_drvdata(phy->phy, phy); ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ ++ return PTR_ERR_OR_ZERO(phy_provider); ++} ++ ++static const struct of_device_id jh7110_pcie_phy_of_match[] = { ++ { .compatible = "starfive,jh7110-pcie-phy" }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match); ++ ++static struct platform_driver jh7110_pcie_phy_driver = { ++ .probe = jh7110_pcie_phy_probe, ++ .driver = { ++ .of_match_table = jh7110_pcie_phy_of_match, ++ .name = "jh7110-pcie-phy", ++ } ++}; ++module_platform_driver(jh7110_pcie_phy_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver"); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0064-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch b/srcpkgs/linux6.4/patches/0064-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch new file mode 100644 index 0000000000000..f70ae19031c75 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0064-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch @@ -0,0 +1,186 @@ +From 9d89115577648d9243da7994c2cf5848de7f6143 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 6 Apr 2023 19:11:40 +0800 +Subject: [PATCH 64/72] dt-binding: pci: add JH7110 PCIe dt-binding documents. + +Add PCIe controller driver dt-binding documents +for StarFive JH7110 SoC platform. + +Signed-off-by: Minda Chen +--- + .../bindings/pci/starfive,jh7110-pcie.yaml | 163 ++++++++++++++++++ + 1 file changed, 163 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml + +diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +new file mode 100644 +index 000000000000..fa4829766195 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml +@@ -0,0 +1,163 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: StarFive JH7110 PCIe 2.0 host controller ++ ++maintainers: ++ - Minda Chen ++ ++allOf: ++ - $ref: /schemas/pci/pci-bus.yaml# ++ - $ref: /schemas/interrupt-controller/msi-controller.yaml# ++ ++properties: ++ compatible: ++ const: starfive,jh7110-pcie ++ ++ reg: ++ maxItems: 2 ++ ++ reg-names: ++ items: ++ - const: reg ++ - const: config ++ ++ msi-parent: true ++ ++ interrupts: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: noc ++ - const: tl ++ - const: axi_mst0 ++ - const: apb ++ ++ resets: ++ items: ++ - description: AXI MST0 reset ++ - description: AXI SLAVE reset ++ - description: AXI SLAVE0 reset ++ - description: PCIE BRIDGE reset ++ - description: PCIE CORE reset ++ - description: PCIE APB reset ++ ++ reset-names: ++ items: ++ - const: mst0 ++ - const: slv0 ++ - const: slv ++ - const: brg ++ - const: core ++ - const: apb ++ ++ starfive,stg-syscon: ++ $ref: /schemas/types.yaml#/definitions/phandle-array ++ items: ++ items: ++ - description: phandle to System Register Controller stg_syscon node. ++ - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. ++ description: ++ The phandle to System Register Controller syscon node and the offset ++ of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset ++ for PCIe. ++ ++ pwren-gpios: ++ description: Should specify the GPIO for controlling the PCI bus device power on. ++ maxItems: 1 ++ ++ reset-gpios: ++ maxItems: 1 ++ ++ phys: ++ maxItems: 1 ++ ++ interrupt-controller: ++ type: object ++ properties: ++ '#address-cells': ++ const: 0 ++ ++ '#interrupt-cells': ++ const: 1 ++ ++ interrupt-controller: true ++ ++ required: ++ - '#address-cells' ++ - '#interrupt-cells' ++ - interrupt-controller ++ ++ additionalProperties: false ++ ++required: ++ - reg ++ - reg-names ++ - "#interrupt-cells" ++ - interrupts ++ - interrupt-map-mask ++ - interrupt-map ++ - clocks ++ - clock-names ++ - resets ++ - msi-controller ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ bus { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ pcie0: pcie@2B000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2B000000 0x0 0x1000000>, ++ <0x9 0x40000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ interrupt-parent = <&plic>; ++ interrupts = <56>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-parent = <&pcie0>; ++ msi-controller; ++ clocks = <&syscrg 86>, ++ <&stgcrg 10>, ++ <&stgcrg 8>, ++ <&stgcrg 9>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg 11>, ++ <&stgcrg 12>, ++ <&stgcrg 13>, ++ <&stgcrg 14>, ++ <&stgcrg 15>, ++ <&stgcrg 16>; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0065-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch b/srcpkgs/linux6.4/patches/0065-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch new file mode 100644 index 0000000000000..309d95dc4495b --- /dev/null +++ b/srcpkgs/linux6.4/patches/0065-pcie-starfive-add-StarFive-JH7110-PCIe-driver.patch @@ -0,0 +1,1014 @@ +From 695ccccf1f47b424abd36c00a7c51c93bad07102 Mon Sep 17 00:00:00 2001 +From: Minda Chen +Date: Thu, 6 Apr 2023 19:11:41 +0800 +Subject: [PATCH 65/72] pcie: starfive: add StarFive JH7110 PCIe driver. + +Add PCIe controller driver for StarFive JH7110 +SoC platform. The PCIe controller is PCIe 2.0, single lane. + +Signed-off-by: Minda Chen +--- + drivers/pci/controller/Kconfig | 8 + + drivers/pci/controller/Makefile | 1 + + drivers/pci/controller/pcie-starfive.c | 958 +++++++++++++++++++++++++ + 3 files changed, 967 insertions(+) + create mode 100644 drivers/pci/controller/pcie-starfive.c + +diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig +index 8d49bad7f847..bc7efe5f1f58 100644 +--- a/drivers/pci/controller/Kconfig ++++ b/drivers/pci/controller/Kconfig +@@ -343,6 +343,14 @@ config PCIE_XILINX_CPM + Say 'Y' here if you want kernel support for the + Xilinx Versal CPM host bridge. + ++config PCIE_STARFIVE ++ tristate "StarFive JH7110 PCIe controller" ++ depends on PCI_MSI && OF ++ select PCI_MSI_IRQ_DOMAIN ++ help ++ Say 'Y' here if you want kernel to support the StarFive JH7110 ++ PCIe Host driver. ++ + source "drivers/pci/controller/cadence/Kconfig" + source "drivers/pci/controller/dwc/Kconfig" + source "drivers/pci/controller/mobiveil/Kconfig" +diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile +index 37c8663de7fe..23708222db8a 100644 +--- a/drivers/pci/controller/Makefile ++++ b/drivers/pci/controller/Makefile +@@ -39,6 +39,7 @@ obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o + obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o + obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o + obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o ++obj-$(CONFIG_PCIE_STARFIVE) += pcie-starfive.o + + # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW + obj-y += dwc/ +diff --git a/drivers/pci/controller/pcie-starfive.c b/drivers/pci/controller/pcie-starfive.c +new file mode 100644 +index 000000000000..e1dc8ecc769a +--- /dev/null ++++ b/drivers/pci/controller/pcie-starfive.c +@@ -0,0 +1,958 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * PCIe host controller driver for Starfive JH7110 Soc. ++ * ++ * Based on pcie-altera.c, pcie-altera-msi.c. ++ * ++ * Copyright (C) StarFive Technology Co., Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "../pci.h" ++ ++#define IMASK_LOCAL 0x180 ++#define ISTATUS_LOCAL 0x184 ++#define IMSI_ADDR 0x190 ++#define ISTATUS_MSI 0x194 ++#define GEN_SETTINGS 0x80 ++#define PCIE_PCI_IDS 0x9C ++#define PCIE_WINROM 0xFC ++#define PMSG_SUPPORT_RX 0x3F0 ++ ++#define PCI_MISC 0xB4 ++ ++#define RP_ENABLE 1 ++ ++#define IDS_CLASS_CODE_SHIFT 16 ++ ++#define DATA_LINK_ACTIVE BIT(5) ++#define PREF_MEM_WIN_64_SUPPORT BIT(3) ++#define PMSG_LTR_SUPPORT BIT(2) ++#define LINK_SPEED_GEN2 BIT(12) ++#define PHY_FUNCTION_DIS BIT(15) ++#define PCIE_FUNC_NUM 4 ++#define PHY_FUNC_SHIFT 9 ++ ++#define XR3PCI_ATR_AXI4_SLV0 0x800 ++#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 ++#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 ++#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 ++#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc ++#define XR3PCI_ATR_TRSL_PARAM 0x10 ++#define XR3PCI_ATR_TABLE_OFFSET 0x20 ++#define XR3PCI_ATR_MAX_TABLE_NUM 8 ++ ++#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 ++#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) ++#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) ++#define XR3PCI_ECAM_SIZE BIT(28) ++#define XR3PCI_ATR_TRSL_DIR BIT(22) ++/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ ++#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0 ++#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1 ++ ++#define INT_AXI_POST_ERROR BIT(16) ++#define INT_AXI_FETCH_ERROR BIT(17) ++#define INT_AXI_DISCARD_ERROR BIT(18) ++#define INT_PCIE_POST_ERROR BIT(20) ++#define INT_PCIE_FETCH_ERROR BIT(21) ++#define INT_PCIE_DISCARD_ERROR BIT(22) ++#define INT_ERRORS (INT_AXI_POST_ERROR | INT_AXI_FETCH_ERROR | \ ++ INT_AXI_DISCARD_ERROR | INT_PCIE_POST_ERROR | \ ++ INT_PCIE_FETCH_ERROR | INT_PCIE_DISCARD_ERROR) ++ ++#define INTA_OFFSET 24 ++#define INTA BIT(24) ++#define INTB BIT(25) ++#define INTC BIT(26) ++#define INTD BIT(27) ++#define INT_MSI BIT(28) ++#define INT_INTX_MASK (INTA | INTB | INTC | INTD) ++#define INT_MASK (INT_INTX_MASK | INT_MSI | INT_ERRORS) ++ ++#define INT_PCI_MSI_NR 32 ++ ++/* system control */ ++#define STG_SYSCON_K_RP_NEP BIT(8) ++#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) ++#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 ++#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) ++#define STG_SYSCON_CLKREQ BIT(22) ++#define STG_SYSCON_CKREF_SRC_SHIFT 18 ++#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) ++ ++/* MSI information */ ++struct jh7110_pcie_msi { ++ DECLARE_BITMAP(used, INT_PCI_MSI_NR); ++ struct irq_domain *msi_domain; ++ struct irq_domain *inner_domain; ++ /* Protect bitmap variable */ ++ struct mutex lock; ++}; ++ ++struct starfive_jh7110_pcie { ++ struct platform_device *pdev; ++ void __iomem *reg_base; ++ void __iomem *config_base; ++ phys_addr_t config_phyaddr; ++ struct regmap *reg_syscon; ++ struct phy *phy; ++ u32 stg_arfun; ++ u32 stg_awfun; ++ u32 stg_rp_nep; ++ u32 stg_lnksta; ++ int irq; ++ struct irq_domain *legacy_irq_domain; ++ struct pci_host_bridge *bridge; ++ struct jh7110_pcie_msi msi; ++ struct reset_control *resets; ++ struct clk_bulk_data *clks; ++ int num_clks; ++ int atr_table_num; ++ struct gpio_desc *power_gpio; ++ struct gpio_desc *reset_gpio; ++}; ++ ++/* ++ * StarFive PCIe port uses BAR0-BAR1 of RC's configuration space as ++ * the translation from PCI bus to native BUS. Entire DDR region ++ * is mapped into PCIe space using these registers, so it can be ++ * reached by DMA from EP devices. The BAR0/1 of bridge should be ++ * hidden during enumeration to avoid the sizing and resource allocation ++ * by PCIe core. ++ */ ++static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, ++ int offset) ++{ ++ if (pci_is_root_bus(bus) && (devfn == 0) ++ && ((offset == PCI_BASE_ADDRESS_0) ++ || (offset == PCI_BASE_ADDRESS_1))) ++ return true; ++ ++ return false; ++} ++ ++void __iomem *starfive_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ struct starfive_jh7110_pcie *pcie = bus->sysdata; ++ ++ return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); ++} ++ ++int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ if (starfive_pcie_hide_rc_bar(bus, devfn, where)) ++ return PCIBIOS_BAD_REGISTER_NUMBER; ++ ++ return pci_generic_config_write(bus, devfn, where, size, value); ++} ++ ++static void starfive_pcie_handle_msi_irq(struct starfive_jh7110_pcie *pcie) ++{ ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 bit; ++ u32 virq; ++ unsigned long status = readl(pcie->reg_base + ISTATUS_MSI); ++ ++ for_each_set_bit(bit, &status, INT_PCI_MSI_NR) { ++ /* Clear interrupts */ ++ writel(1 << bit, pcie->reg_base + ISTATUS_MSI); ++ virq = irq_find_mapping(msi->inner_domain, bit); ++ if (virq) { ++ if (test_bit(bit, msi->used)) ++ generic_handle_irq(virq); ++ else ++ dev_err(&pcie->pdev->dev, ++ "Unhandled MSI, MSI%d virq %d\n", bit, ++ virq); ++ } else ++ dev_err(&pcie->pdev->dev, "Unexpected MSI, MSI%d\n", ++ bit); ++ } ++ writel(INT_MSI, pcie->reg_base + ISTATUS_LOCAL); ++} ++ ++static void starfive_pcie_handle_intx_irq(struct starfive_jh7110_pcie *pcie, ++ unsigned long status) ++{ ++ u32 bit; ++ u32 virq; ++ ++ status >>= INTA_OFFSET; ++ ++ for_each_set_bit(bit, &status, PCI_NUM_INTX) { ++ /* Clear interrupts */ ++ writel(1 << (bit + INTA_OFFSET), pcie->reg_base + ISTATUS_LOCAL); ++ ++ virq = irq_find_mapping(pcie->legacy_irq_domain, bit); ++ if (virq) ++ generic_handle_irq(virq); ++ else ++ dev_err(&pcie->pdev->dev, ++ "unexpected IRQ, INT%d\n", bit); ++ } ++} ++ ++static void starfive_pcie_handle_errors_irq(struct starfive_jh7110_pcie *pcie, u32 status) ++{ ++ if (status & INT_AXI_POST_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI post error\n"); ++ if (status & INT_AXI_FETCH_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI fetch error\n"); ++ if (status & INT_AXI_DISCARD_ERROR) ++ dev_err(&pcie->pdev->dev, "AXI discard error\n"); ++ if (status & INT_PCIE_POST_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe post error\n"); ++ if (status & INT_PCIE_FETCH_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe fetch error\n"); ++ if (status & INT_PCIE_DISCARD_ERROR) ++ dev_err(&pcie->pdev->dev, "PCIe discard error\n"); ++ ++ writel(INT_ERRORS, pcie->reg_base + ISTATUS_LOCAL); ++} ++ ++static void starfive_pcie_isr(struct irq_desc *desc) ++{ ++ struct irq_chip *chip = irq_desc_get_chip(desc); ++ struct starfive_jh7110_pcie *pcie; ++ u32 status; ++ ++ chained_irq_enter(chip, desc); ++ pcie = irq_desc_get_handler_data(desc); ++ ++ status = readl(pcie->reg_base + ISTATUS_LOCAL); ++ while ((status = (readl(pcie->reg_base + ISTATUS_LOCAL) & INT_MASK))) { ++ if (status & INT_INTX_MASK) ++ starfive_pcie_handle_intx_irq(pcie, status); ++ ++ if (status & INT_MSI) ++ starfive_pcie_handle_msi_irq(pcie); ++ ++ if (status & INT_ERRORS) ++ starfive_pcie_handle_errors_irq(pcie, status); ++ } ++ ++ chained_irq_exit(chip, desc); ++} ++ ++#ifdef CONFIG_PCI_MSI ++static struct irq_chip starfive_pcie_msi_irq_chip = { ++ .name = "StarFive PCIe MSI", ++ .irq_mask = pci_msi_mask_irq, ++ .irq_unmask = pci_msi_unmask_irq, ++}; ++ ++static struct msi_domain_info starfive_pcie_msi_domain_info = { ++ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | ++ MSI_FLAG_PCI_MSIX), ++ .chip = &starfive_pcie_msi_irq_chip, ++}; ++#endif ++ ++static void starfive_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) ++{ ++ struct starfive_jh7110_pcie *pcie = irq_data_get_irq_chip_data(data); ++ phys_addr_t msi_addr = readl(pcie->reg_base + IMSI_ADDR); ++ ++ msg->address_lo = lower_32_bits(msi_addr); ++ msg->address_hi = upper_32_bits(msi_addr); ++ msg->data = data->hwirq; ++ ++ dev_info(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", ++ (int)data->hwirq, msg->address_hi, msg->address_lo); ++} ++ ++static int starfive_pcie_msi_set_affinity(struct irq_data *irq_data, ++ const struct cpumask *mask, bool force) ++{ ++ return -EINVAL; ++} ++ ++static struct irq_chip starfive_irq_chip = { ++ .name = "StarFive MSI", ++ .irq_compose_msi_msg = starfive_pcie_compose_msi_msg, ++ .irq_set_affinity = starfive_pcie_msi_set_affinity, ++}; ++ ++static int starfive_pcie_msi_alloc(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs, void *args) ++{ ++ struct starfive_jh7110_pcie *pcie = domain->host_data; ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ int bit; ++ ++ WARN_ON(nr_irqs != 1); ++ mutex_lock(&msi->lock); ++ ++ bit = find_first_zero_bit(msi->used, INT_PCI_MSI_NR); ++ if (bit >= INT_PCI_MSI_NR) { ++ mutex_unlock(&msi->lock); ++ return -ENOSPC; ++ } ++ ++ set_bit(bit, msi->used); ++ ++ irq_domain_set_info(domain, virq, bit, &starfive_irq_chip, ++ domain->host_data, handle_simple_irq, ++ NULL, NULL); ++ mutex_unlock(&msi->lock); ++ ++ return 0; ++} ++ ++static void starfive_pcie_msi_free(struct irq_domain *domain, unsigned int virq, ++ unsigned int nr_irqs) ++{ ++ struct irq_data *data = irq_domain_get_irq_data(domain, virq); ++ struct starfive_jh7110_pcie *pcie = irq_data_get_irq_chip_data(data); ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ ++ mutex_lock(&msi->lock); ++ ++ if (!test_bit(data->hwirq, msi->used)) ++ dev_err(&pcie->pdev->dev, "Trying to free unused MSI#%lu\n", ++ data->hwirq); ++ else ++ __clear_bit(data->hwirq, msi->used); ++ ++ writel(0xffffffff, pcie->reg_base + ISTATUS_MSI); ++ mutex_unlock(&msi->lock); ++} ++ ++static const struct irq_domain_ops dev_msi_domain_ops = { ++ .alloc = starfive_pcie_msi_alloc, ++ .free = starfive_pcie_msi_free, ++}; ++ ++static void starfive_pcie_msi_free_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++#ifdef CONFIG_PCI_MSI ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 irq; ++ int i; ++ ++ for (i = 0; i < INT_PCI_MSI_NR; i++) { ++ irq = irq_find_mapping(msi->inner_domain, i); ++ if (irq > 0) ++ irq_dispose_mapping(irq); ++ } ++ ++ if (msi->msi_domain) ++ irq_domain_remove(msi->msi_domain); ++ ++ if (msi->inner_domain) ++ irq_domain_remove(msi->inner_domain); ++#endif ++} ++ ++static void starfive_pcie_free_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++ int i; ++ u32 irq; ++ ++ /* Disable all interrupts */ ++ writel(0, pcie->reg_base + IMASK_LOCAL); ++ ++ if (pcie->legacy_irq_domain) { ++ for (i = 0; i < PCI_NUM_INTX; i++) { ++ irq = irq_find_mapping(pcie->legacy_irq_domain, i); ++ if (irq > 0) ++ irq_dispose_mapping(irq); ++ } ++ irq_domain_remove(pcie->legacy_irq_domain); ++ } ++ ++ if (pci_msi_enabled()) ++ starfive_pcie_msi_free_irq_domain(pcie); ++ irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); ++} ++ ++static int starfive_pcie_init_msi_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++#ifdef CONFIG_PCI_MSI ++ struct fwnode_handle *fwn = of_node_to_fwnode(pcie->pdev->dev.of_node); ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ ++ msi->inner_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, ++ &dev_msi_domain_ops, pcie); ++ if (!msi->inner_domain) { ++ dev_err(&pcie->pdev->dev, "Failed to create dev IRQ domain\n"); ++ return -ENOMEM; ++ } ++ msi->msi_domain = pci_msi_create_irq_domain(fwn, &starfive_pcie_msi_domain_info, ++ msi->inner_domain); ++ if (!msi->msi_domain) { ++ dev_err(&pcie->pdev->dev, "Failed to create msi IRQ domain\n"); ++ irq_domain_remove(msi->inner_domain); ++ return -ENOMEM; ++ } ++#endif ++ return 0; ++} ++ ++static int starfive_pcie_enable_msi(struct starfive_jh7110_pcie *pcie, struct pci_bus *bus) ++{ ++ struct jh7110_pcie_msi *msi = &pcie->msi; ++ u32 reg; ++ ++ mutex_init(&msi->lock); ++ ++ /* Enable MSI */ ++ reg = readl(pcie->reg_base + IMASK_LOCAL); ++ reg |= INT_MSI; ++ writel(reg, pcie->reg_base + IMASK_LOCAL); ++ return 0; ++} ++ ++static int starfive_pcie_intx_map(struct irq_domain *domain, unsigned int irq, ++ irq_hw_number_t hwirq) ++{ ++ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); ++ irq_set_chip_data(irq, domain->host_data); ++ ++ return 0; ++} ++ ++static const struct irq_domain_ops intx_domain_ops = { ++ .map = starfive_pcie_intx_map, ++ .xlate = pci_irqd_intx_xlate, ++}; ++ ++static int starfive_pcie_init_irq_domain(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ struct device_node *node = dev->of_node; ++ int ret; ++ ++ if (pci_msi_enabled()) { ++ ret = starfive_pcie_init_msi_irq_domain(pcie); ++ if (ret != 0) ++ return -ENOMEM; ++ } ++ ++ /* Setup INTx */ ++ pcie->legacy_irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX, ++ &intx_domain_ops, pcie); ++ ++ if (!pcie->legacy_irq_domain) { ++ dev_err(dev, "Failed to get a INTx IRQ domain\n"); ++ return -ENOMEM; ++ } ++ ++ irq_set_chained_handler_and_data(pcie->irq, starfive_pcie_isr, pcie); ++ ++ return 0; ++} ++ ++static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie) ++{ ++ struct resource *cfg_res; ++ struct platform_device *pdev = pcie->pdev; ++ unsigned int args[4]; ++ ++ pcie->reg_base = ++ devm_platform_ioremap_resource_byname(pdev, "reg"); ++ ++ if (IS_ERR(pcie->reg_base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->reg_base), ++ "Failed to map reg memory\n"); ++ ++ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); ++ if (!cfg_res) ++ return dev_err_probe(&pdev->dev, -ENODEV, ++ "Failed to get config memory\n"); ++ ++ pcie->config_base = devm_ioremap_resource(&pdev->dev, cfg_res); ++ if (IS_ERR(pcie->config_base)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->config_base), ++ "Failed to map config memory\n"); ++ ++ pcie->config_phyaddr = cfg_res->start; ++ ++ pcie->phy = devm_phy_optional_get(&pdev->dev, NULL); ++ if (IS_ERR(pcie->phy)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->phy), ++ "Failed to get pcie phy\n"); ++ ++ pcie->irq = platform_get_irq(pdev, 0); ++ if (pcie->irq < 0) ++ return dev_err_probe(&pdev->dev, -EINVAL, ++ "Failed to get IRQ: %d\n", pcie->irq); ++ ++ pcie->reg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node, ++ "starfive,stg-syscon", 4, args); ++ ++ if (IS_ERR(pcie->reg_syscon)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(pcie->reg_syscon), ++ "Failed to parse starfive,stg-syscon\n"); ++ ++ pcie->stg_arfun = args[0]; ++ pcie->stg_awfun = args[1]; ++ pcie->stg_rp_nep = args[2]; ++ pcie->stg_lnksta = args[3]; ++ ++ /* Clear all interrupts */ ++ writel(0xffffffff, pcie->reg_base + ISTATUS_LOCAL); ++ writel(INT_INTX_MASK | INT_ERRORS, pcie->reg_base + IMASK_LOCAL); ++ ++ return 0; ++} ++ ++static struct pci_ops starfive_pcie_ops = { ++ .map_bus = starfive_pcie_map_bus, ++ .read = pci_generic_config_read, ++ .write = starfive_pcie_config_write, ++}; ++ ++static void starfive_pcie_set_atr_entry(struct starfive_jh7110_pcie *pcie, ++ phys_addr_t src_addr, phys_addr_t trsl_addr, ++ size_t window_size, int trsl_param) ++{ ++ void __iomem *base = ++ pcie->reg_base + XR3PCI_ATR_AXI4_SLV0; ++ ++ /* Support AXI4 Slave 0 Address Translation Tables 0-7. */ ++ if (pcie->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM) ++ pcie->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1; ++ base += XR3PCI_ATR_TABLE_OFFSET * pcie->atr_table_num; ++ pcie->atr_table_num++; ++ ++ /* ++ * X3PCI_ATR_SRC_ADDR_LOW: ++ * - bit 0: enable entry, ++ * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) ++ * - bits 7-11: reserved ++ * - bits 12-31: start of source address ++ */ ++ writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) | ++ (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1, ++ base + XR3PCI_ATR_SRC_ADDR_LOW); ++ writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH); ++ writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK), ++ base + XR3PCI_ATR_TRSL_ADDR_LOW); ++ writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH); ++ writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM); ++ ++ dev_info(&pcie->pdev->dev, "ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n", ++ src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->", ++ trsl_addr, (u64)window_size, trsl_param); ++} ++ ++static int starfive_pcie_setup_windows(struct starfive_jh7110_pcie *pcie) ++{ ++ struct pci_host_bridge *bridge = pcie->bridge; ++ struct resource_entry *entry; ++ u64 pci_addr; ++ ++ resource_list_for_each_entry(entry, &bridge->windows) { ++ if (resource_type(entry->res) == IORESOURCE_MEM) { ++ pci_addr = entry->res->start - entry->offset; ++ starfive_pcie_set_atr_entry(pcie, ++ entry->res->start, pci_addr, ++ resource_size(entry->res), ++ XR3PCI_ATR_TRSLID_PCIE_MEMORY); ++ } ++ } ++ ++ return 0; ++} ++ ++static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie *pcie) ++{ ++ int ret; ++ struct device *dev = &pcie->pdev->dev; ++ ++ pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); ++ if (pcie->num_clks < 0) ++ return dev_err_probe(dev, -ENODEV, ++ "Failed to get pcie clocks\n"); ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) ++ return dev_err_probe(&pcie->pdev->dev, ret, ++ "Failed to enable clocks\n"); ++ ++ pcie->resets = devm_reset_control_array_get_exclusive(dev); ++ if (IS_ERR(pcie->resets)) { ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ return dev_err_probe(dev, PTR_ERR(pcie->resets), ++ "Failed to get pcie resets"); ++ } ++ ++ return reset_control_deassert(pcie->resets); ++} ++ ++static void starfive_pcie_clk_rst_deinit(struct starfive_jh7110_pcie *pcie) ++{ ++ reset_control_assert(pcie->resets); ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++} ++ ++int starfive_pcie_gpio_init(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ ++ pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); ++ if (IS_ERR_OR_NULL(pcie->reset_gpio)) { ++ dev_warn(dev, "Failed to get reset-gpio.\n"); ++ return -EINVAL; ++ } ++ ++ pcie->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW); ++ if (IS_ERR_OR_NULL(pcie->power_gpio)) ++ pcie->power_gpio = NULL; ++ ++ return 0; ++} ++ ++static void starfive_pcie_hw_init(struct starfive_jh7110_pcie *pcie) ++{ ++ unsigned int value; ++ int i; ++ ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 1); ++ ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 1); ++ ++ /* Disable physical functions except #0 */ ++ for (i = 1; i < PCIE_FUNC_NUM; i++) { ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_arfun, ++ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, ++ (i << PHY_FUNC_SHIFT) << ++ STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, ++ i << PHY_FUNC_SHIFT); ++ ++ value = readl(pcie->reg_base + PCI_MISC); ++ value |= PHY_FUNCTION_DIS; ++ writel(value, pcie->reg_base + PCI_MISC); ++ } ++ ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_arfun, ++ STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, ++ 0); ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, ++ 0); ++ ++ /* Enable root port */ ++ value = readl(pcie->reg_base + GEN_SETTINGS); ++ value |= RP_ENABLE; ++ writel(value, pcie->reg_base + GEN_SETTINGS); ++ ++ /* PCIe PCI Standard Configuration Identification Settings. */ ++ value = (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT); ++ writel(value, pcie->reg_base + PCIE_PCI_IDS); ++ ++ /* ++ * The LTR message forwarding of PCIe Message Reception was set by core ++ * as default, but the forward id & addr are also need to be reset. ++ * If we do not disable LTR message forwarding here, or set a legal ++ * forwarding address, the kernel will get stuck after this driver probe. ++ * To workaround, disable the LTR message forwarding support on ++ * PCIe Message Reception. ++ */ ++ value = readl(pcie->reg_base + PMSG_SUPPORT_RX); ++ value &= ~PMSG_LTR_SUPPORT; ++ writel(value, pcie->reg_base + PMSG_SUPPORT_RX); ++ ++ /* Prefetchable memory window 64-bit addressing support */ ++ value = readl(pcie->reg_base + PCIE_WINROM); ++ value |= PREF_MEM_WIN_64_SUPPORT; ++ writel(value, pcie->reg_base + PCIE_WINROM); ++ ++ /* ++ * As the two host bridges in JH7110 soc have the same default ++ * address translation table, this cause the second root port can't ++ * access it's host bridge config space correctly. ++ * To workaround, config the ATR of host bridge config space by SW. ++ */ ++ starfive_pcie_set_atr_entry(pcie, ++ pcie->config_phyaddr, 0, ++ XR3PCI_ECAM_SIZE, ++ XR3PCI_ATR_TRSLID_PCIE_CONFIG); ++ ++ starfive_pcie_setup_windows(pcie); ++ ++ /* Ensure that PERST has been asserted for at least 100 ms */ ++ msleep(300); ++ if (pcie->reset_gpio) ++ gpiod_set_value_cansleep(pcie->reset_gpio, 0); ++} ++ ++static bool starfive_pcie_is_link_up(struct starfive_jh7110_pcie *pcie) ++{ ++ struct device *dev = &pcie->pdev->dev; ++ int ret; ++ u32 stg_reg_val; ++ ++ /* 100ms timeout value should be enough for Gen1/2 training */ ++ ret = regmap_read_poll_timeout(pcie->reg_syscon, ++ pcie->stg_lnksta, ++ stg_reg_val, ++ stg_reg_val & DATA_LINK_ACTIVE, ++ 10 * 1000, 100 * 1000); ++ ++ /* If the link is down (no device in slot), then exit. */ ++ if (ret == -ETIMEDOUT) { ++ dev_info(dev, "Port link down, exit.\n"); ++ return false; ++ } else if (ret == 0) { ++ dev_info(dev, "Port link up.\n"); ++ return true; ++ } ++ ++ dev_warn(dev, "Read stg_linksta failed.\n"); ++ ++ return false; ++} ++ ++static int starfive_pcie_enable_phy(struct device *dev, ++ struct starfive_jh7110_pcie *pcie) ++{ ++ int ret; ++ ++ if (!pcie->phy) ++ return 0; ++ ++ ret = phy_init(pcie->phy); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "failed to initialize pcie phy\n"); ++ ++ ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); ++ if (ret) { ++ ret = dev_err_probe(dev, ret, ++ "failed to set pcie mode\n"); ++ goto err_phy_on; ++ } ++ ++ ret = phy_power_on(pcie->phy); ++ if (ret) { ++ ret = dev_err_probe(dev, ret, "failed to power on pcie phy\n"); ++ goto err_phy_on; ++ } ++ ++ return 0; ++ ++err_phy_on: ++ phy_exit(pcie->phy); ++ return ret; ++} ++ ++static void starfive_pcie_disable_phy(struct starfive_jh7110_pcie *pcie) ++{ ++ phy_power_off(pcie->phy); ++ phy_exit(pcie->phy); ++} ++ ++static int starfive_pcie_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct starfive_jh7110_pcie *pcie; ++ struct pci_bus *bus; ++ struct pci_host_bridge *bridge; ++ int ret; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->pdev = pdev; ++ pcie->atr_table_num = 0; ++ ++ ret = starfive_pcie_parse_dt(pcie); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, pcie); ++ ++ ret = starfive_pcie_gpio_init(pcie); ++ if (ret) ++ return ret; ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_rp_nep, ++ STG_SYSCON_K_RP_NEP, ++ STG_SYSCON_K_RP_NEP); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_CKREF_SRC_MASK, ++ 2 << STG_SYSCON_CKREF_SRC_SHIFT); ++ ++ regmap_update_bits(pcie->reg_syscon, ++ pcie->stg_awfun, ++ STG_SYSCON_CLKREQ, ++ STG_SYSCON_CLKREQ); ++ ++ ret = starfive_pcie_clk_rst_init(pcie); ++ if (ret) ++ return ret; ++ ++ ret = starfive_pcie_init_irq_domain(pcie); ++ if (ret) ++ return ret; ++ ++ bridge = devm_pci_alloc_host_bridge(dev, 0); ++ if (!bridge) ++ return -ENOMEM; ++ ++ pm_runtime_enable(&pdev->dev); ++ pm_runtime_get_sync(&pdev->dev); ++ ++ /* Set default bus ops */ ++ bridge->ops = &starfive_pcie_ops; ++ bridge->sysdata = pcie; ++ pcie->bridge = bridge; ++ ++ starfive_pcie_hw_init(pcie); ++ ++ if (starfive_pcie_is_link_up(pcie) == false) ++ goto release; ++ ++ if (IS_ENABLED(CONFIG_PCI_MSI)) { ++ ret = starfive_pcie_enable_msi(pcie, bus); ++ if (ret < 0) { ++ dev_err(dev, "Failed to enable MSI support: %d\n", ret); ++ goto release; ++ } ++ } ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ goto release; ++ ++ ret = pci_host_probe(bridge); ++ if (ret < 0) { ++ dev_err_probe(dev, ret, "Failed to pci host probe: %d\n", ret); ++ goto err_phy_on; ++ } ++ ++ return ret; ++ ++err_phy_on: ++ starfive_pcie_disable_phy(pcie); ++release: ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 0); ++ ++ starfive_pcie_clk_rst_deinit(pcie); ++ ++ pm_runtime_put_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ ++ pci_free_host_bridge(pcie->bridge); ++ platform_set_drvdata(pdev, NULL); ++ ++ return ret; ++} ++ ++static int starfive_pcie_remove(struct platform_device *pdev) ++{ ++ struct starfive_jh7110_pcie *pcie = platform_get_drvdata(pdev); ++ ++ starfive_pcie_disable_phy(pcie); ++ if (pcie->power_gpio) ++ gpiod_set_value_cansleep(pcie->power_gpio, 0); ++ starfive_pcie_free_irq_domain(pcie); ++ starfive_pcie_clk_rst_deinit(pcie); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int __maybe_unused starfive_pcie_suspend_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ ++ if (!pcie) ++ return 0; ++ ++ starfive_pcie_disable_phy(pcie); ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ ++ return 0; ++} ++ ++static int __maybe_unused starfive_pcie_resume_noirq(struct device *dev) ++{ ++ struct starfive_jh7110_pcie *pcie = dev_get_drvdata(dev); ++ int ret; ++ ++ if (!pcie) ++ return 0; ++ ++ ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to enable clocks\n"); ++ ++ ret = starfive_pcie_enable_phy(dev, pcie); ++ if (ret) ++ clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); ++ ++ return ret; ++} ++ ++static const struct dev_pm_ops starfive_pcie_pm_ops = { ++ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(starfive_pcie_suspend_noirq, ++ starfive_pcie_resume_noirq) ++}; ++#endif ++ ++static const struct of_device_id starfive_pcie_of_match[] = { ++ { .compatible = "starfive,jh7110-pcie"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, starfive_pcie_of_match); ++ ++static struct platform_driver starfive_pcie_driver = { ++ .driver = { ++ .name = "pcie-starfive", ++ .of_match_table = of_match_ptr(starfive_pcie_of_match), ++#ifdef CONFIG_PM_SLEEP ++ .pm = &starfive_pcie_pm_ops, ++#endif ++ }, ++ .probe = starfive_pcie_probe, ++ .remove = starfive_pcie_remove, ++}; ++module_platform_driver(starfive_pcie_driver); ++ ++MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver"); ++MODULE_AUTHOR("Mason Huo "); ++MODULE_AUTHOR("Kevin Xie "); ++MODULE_AUTHOR("Minda Chen "); ++MODULE_LICENSE("GPL v2"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0066-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch b/srcpkgs/linux6.4/patches/0066-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch new file mode 100644 index 0000000000000..6046f325c8040 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0066-cpufreq-dt-platdev-Add-JH7110-SOC-to-the-allowlist.patch @@ -0,0 +1,29 @@ +From 3a0e8c78369da5822ce5f9f579ebbf1278a99b30 Mon Sep 17 00:00:00 2001 +From: Mason Huo +Date: Fri, 21 Apr 2023 11:14:30 +0800 +Subject: [PATCH 66/72] cpufreq: dt-platdev: Add JH7110 SOC to the allowlist + +Add the compatible strings for supporting the generic +cpufreq driver on the StarFive JH7110 SoC. + +Signed-off-by: Mason Huo +--- + drivers/cpufreq/cpufreq-dt-platdev.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c +index 338cf6cc6596..14aa8281c7f4 100644 +--- a/drivers/cpufreq/cpufreq-dt-platdev.c ++++ b/drivers/cpufreq/cpufreq-dt-platdev.c +@@ -85,6 +85,8 @@ static const struct of_device_id allowlist[] __initconst = { + { .compatible = "st-ericsson,u9500", }, + { .compatible = "st-ericsson,u9540", }, + ++ { .compatible = "starfive,jh7110", }, ++ + { .compatible = "ti,omap2", }, + { .compatible = "ti,omap4", }, + { .compatible = "ti,omap5", }, +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0067-MAINTAINERS-Update-all-StarFive-entries.patch b/srcpkgs/linux6.4/patches/0067-MAINTAINERS-Update-all-StarFive-entries.patch new file mode 100644 index 0000000000000..89aa9485db995 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0067-MAINTAINERS-Update-all-StarFive-entries.patch @@ -0,0 +1,167 @@ +From 5d9d003d31575d08251da635cab419c8492e0230 Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Tue, 11 Apr 2023 16:25:57 +0800 +Subject: [PATCH 67/72] MAINTAINERS: Update all StarFive entries + +Merge all StarFive maintainers changes together. + +Signed-off-by: Hal Feng +--- + MAINTAINERS | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 88 insertions(+) + +diff --git a/MAINTAINERS b/MAINTAINERS +index 35e19594640d..10d2c6453bfd 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -4492,6 +4492,7 @@ M: Maxime Ripard + L: linux-media@vger.kernel.org + S: Maintained + F: Documentation/devicetree/bindings/media/cdns,*.txt ++F: Documentation/devicetree/bindings/media/cdns,csi2rx.yaml + F: drivers/media/platform/cadence/cdns-csi2* + + CADENCE NAND DRIVER +@@ -20109,6 +20110,22 @@ M: Ion Badulescu + S: Odd Fixes + F: drivers/net/ethernet/adaptec/starfire* + ++STARFIVE CAMERA SUBSYSTEM DRIVER ++M: Jack Zhu ++M: Changhuang Liang ++L: linux-media@vger.kernel.org ++S: Maintained ++F: Documentation/admin-guide/media/starfive_camss.rst ++F: Documentation/devicetree/bindings/media/starfive,jh7110-camss.yaml ++F: drivers/media/platform/starfive/ ++ ++STARFIVE CRYPTO DRIVER ++M: Jia Jie Ho ++M: William Qiu ++S: Supported ++F: Documentation/devicetree/bindings/crypto/starfive* ++F: drivers/crypto/starfive/ ++ + STARFIVE DEVICETREES + M: Emil Renner Berthing + S: Maintained +@@ -20121,20 +20138,69 @@ S: Maintained + F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml + F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c + ++STARFIVE JH7110 DPHY RX DRIVER ++M: Jack Zhu ++M: Changhuang Liang ++S: Supported ++F: Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml ++F: drivers/phy/starfive/phy-starfive-dphy-rx.c ++ + STARFIVE JH7110 MMC/SD/SDIO DRIVER + M: William Qiu + S: Supported + F: Documentation/devicetree/bindings/mmc/starfive* + F: drivers/mmc/host/dw_mmc-starfive.c + ++STARFIVE JH7110 PLL CLOCK DRIVER ++M: Xingyu Wu ++S: Supported ++F: Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml ++F: drivers/clk/starfive/clk-starfive-jh7110-pll.* ++ ++STARFIVE JH7110 PWMDAC DRIVER ++M: Hal Feng ++M: Xingyu Wu ++S: Supported ++F: Documentation/devicetree/bindings/sound/starfive,jh7110-pwmdac* ++F: sound/soc/codecs/jh7110_pwmdac_transmitter.c ++F: sound/soc/starfive/jh7110_pwmdac.c ++ ++STARFIVE JH7110 SYSCON ++M: William Qiu ++M: Xingyu Wu ++S: Supported ++F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml ++ ++STARFIVE JH7110 TDM DRIVERS ++M: Walker Chen ++S: Maintained ++F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml ++F: sound/soc/starfive/jh7110-tdm.* ++ + STARFIVE JH71X0 CLOCK DRIVERS + M: Emil Renner Berthing + M: Hal Feng ++M: Xingyu Wu + S: Maintained + F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml + F: drivers/clk/starfive/clk-starfive-jh71* + F: include/dt-bindings/clock/starfive?jh71*.h + ++STARFIVE JH71X0 PCIE AND USB PHY DRIVER ++M: Emil Renner Berthing ++M: Minda Chen ++S: Supported ++F: Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml ++F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml ++F: drivers/phy/starfive/phy-jh7110-pcie.c ++F: drivers/phy/starfive/phy-jh7110-usb.c ++ ++STARFIVE JH71X0 PCIE DRIVERS ++M: Minda Chen ++S: Maintained ++F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml ++F: drivers/pci/controller/pcie-starfive.c ++ + STARFIVE JH71X0 PINCTRL DRIVERS + M: Emil Renner Berthing + M: Jianlong Huang +@@ -20145,6 +20211,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* + F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h + F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h + ++STARFIVE JH71X0 PWM DRIVERS ++M: William Qiu ++M: Hal Feng ++S: Supported ++F: Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml ++F: drivers/pwm/pwm-starfive-ptc.c ++ + STARFIVE JH71X0 RESET CONTROLLER DRIVERS + M: Emil Renner Berthing + M: Hal Feng +@@ -20153,8 +20226,15 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml + F: drivers/reset/starfive/reset-starfive-jh71* + F: include/dt-bindings/reset/starfive?jh71*.h + ++STARFIVE JH71X0 USB DRIVERS ++M: Minda Chen ++S: Maintained ++F: Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml ++F: drivers/usb/cdns3/cdns3-starfive.c ++ + STARFIVE JH71XX PMU CONTROLLER DRIVER + M: Walker Chen ++M: Changhuang Liang + S: Supported + F: Documentation/devicetree/bindings/power/starfive* + F: drivers/soc/starfive/jh71xx_pmu.c +@@ -20164,8 +20244,16 @@ STARFIVE SOC DRIVERS + M: Conor Dooley + S: Maintained + T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ ++F: Documentation/devicetree/bindings/soc/starfive/ + F: drivers/soc/starfive/ + ++STARFIVE TIMER DRIVER ++M: Samin Guo ++M: Xingyu Wu ++S: Supported ++F: Documentation/devicetree/bindings/timer/starfive* ++F: drivers/clocksource/timer-starfive* ++ + STARFIVE TRNG DRIVER + M: Jia Jie Ho + S: Supported +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0068-riscv-dts-starfive-Add-full-support-for-JH7110-and-V.patch b/srcpkgs/linux6.4/patches/0068-riscv-dts-starfive-Add-full-support-for-JH7110-and-V.patch new file mode 100644 index 0000000000000..875febcb01c4c --- /dev/null +++ b/srcpkgs/linux6.4/patches/0068-riscv-dts-starfive-Add-full-support-for-JH7110-and-V.patch @@ -0,0 +1,1413 @@ +From febb1986bcc3bb4bc5eff109068cc765f99fe16d Mon Sep 17 00:00:00 2001 +From: Hal Feng +Date: Tue, 11 Apr 2023 16:31:15 +0800 +Subject: [PATCH 68/72] riscv: dts: starfive: Add full support for JH7110 and + VisionFive 2 board + +Merge all StarFive dts patches together. + +Signed-off-by: Hal Feng +--- + .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 + + .../jh7110-starfive-visionfive-2-v1.3b.dts | 31 + + .../jh7110-starfive-visionfive-2.dtsi | 494 +++++++++++++ + arch/riscv/boot/dts/starfive/jh7110.dtsi | 661 +++++++++++++++++- + 4 files changed, 1197 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +index 4af3300f3cf3..205a13d8c8b1 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +@@ -11,3 +11,16 @@ / { + model = "StarFive VisionFive 2 v1.2A"; + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; + }; ++ ++&gmac1 { ++ phy-mode = "rmii"; ++ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, ++ <&syscrg JH7110_SYSCLK_GMAC1_RX>; ++ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, ++ <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; ++}; ++ ++&phy0 { ++ rx-internal-delay-ps = <1900>; ++ tx-internal-delay-ps = <1350>; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +index 9230cc3d8946..0229f7a154ad 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +@@ -11,3 +11,34 @@ / { + model = "StarFive VisionFive 2 v1.3B"; + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; + }; ++ ++&gmac0 { ++ starfive,tx-use-rgmii-clk; ++ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; ++ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; ++}; ++ ++&gmac1 { ++ starfive,tx-use-rgmii-clk; ++ assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; ++ assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; ++}; ++ ++&phy0 { ++ motorcomm,tx-clk-adj-enabled; ++ motorcomm,tx-clk-100-inverted; ++ motorcomm,tx-clk-1000-inverted; ++ motorcomm,rx-clk-driver-strength = <0x6>; ++ motorcomm,rx-data-driver-strength = <0x3>; ++ rx-internal-delay-ps = <1500>; ++ tx-internal-delay-ps = <1500>; ++}; ++ ++&phy1 { ++ motorcomm,tx-clk-adj-enabled; ++ motorcomm,tx-clk-100-inverted; ++ motorcomm,rx-clk-driver-strength = <0x6>; ++ motorcomm,rx-data-driver-strength = <0x3>; ++ rx-internal-delay-ps = <300>; ++ tx-internal-delay-ps = <0>; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +index 2a6d81609284..78ab796e01a8 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +@@ -11,6 +11,8 @@ + + / { + aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c5 = &i2c5; +@@ -31,11 +33,92 @@ memory@40000000 { + reg = <0x0 0x40000000 0x1 0x0>; + }; + ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x0 0x20000000>; ++ alignment = <0x0 0x1000>; ++ alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu-thermal { ++ polling-delay-passive = <250>; ++ polling-delay = <15000>; ++ ++ thermal-sensors = <&sfctemp>; ++ ++ cooling-maps { ++ }; ++ ++ trips { ++ cpu_alert0: cpu_alert0 { ++ /* milliCelsius */ ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ ++ cpu_crit: cpu_crit { ++ /* milliCelsius */ ++ temperature = <90000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ }; ++ }; ++ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; + priority = <224>; + }; ++ ++ pwmdac_dit: pwmdac-dit { ++ compatible = "starfive,jh7110-pwmdac-dit"; ++ #sound-dai-cells = <0>; ++ }; ++ ++ sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "StarFive-PWMDAC-Sound-Card"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ simple-audio-card,dai-link@0 { ++ reg = <0>; ++ format = "left_j"; ++ bitclock-master = <&sndcpu0>; ++ frame-master = <&sndcpu0>; ++ status = "okay"; ++ ++ sndcpu0: cpu { ++ sound-dai = <&pwmdac>; ++ }; ++ ++ codec { ++ sound-dai = <&pwmdac_dit>; ++ }; ++ }; ++ }; ++ ++ clk_ext_camera: clk_ext_camera { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++}; ++ ++&dvp_clk { ++ clock-frequency = <74250000>; + }; + + &gmac0_rgmii_rxin { +@@ -54,6 +137,10 @@ &gmac1_rmii_refin { + clock-frequency = <50000000>; + }; + ++&hdmitx0_pixelclk { ++ clock-frequency = <297000000>; ++}; ++ + &i2srx_bclk_ext { + clock-frequency = <12288000>; + }; +@@ -86,6 +173,104 @@ &tdm_ext { + clock-frequency = <49152000>; + }; + ++&csi2rx { ++ status = "okay"; ++ ++ assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>; ++ assigned-clock-rates = <297000000>; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ csi2rx_from_imx219: endpoint { ++ remote-endpoint = <&imx219_to_csi2rx>; ++ bus-type = <4>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ status = "okay"; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ csi2rx_to_vin: endpoint { ++ remote-endpoint = <&vin_from_csi2rx>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; ++ ++&dc8200 { ++ status = "okay"; ++ ++ dc_out: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dc_out_dpi0: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&hdmi_input>; ++ }; ++ ++ }; ++}; ++ ++&display { ++ status = "okay"; ++}; ++ ++&gmac0 { ++ phy-handle = <&phy0>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ }; ++}; ++ ++&gmac1 { ++ phy-handle = <&phy1>; ++ phy-mode = "rgmii-id"; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy1: ethernet-phy@1 { ++ reg = <0>; ++ }; ++ }; ++}; ++ ++&hdmi { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hdmi_pins>; ++ ++ hdmi_in: port { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ hdmi_input: endpoint@0 { ++ reg = <0>; ++ remote-endpoint = <&dc_out_dpi0>; ++ }; ++ }; ++}; ++ + &i2c0 { + clock-frequency = <100000>; + i2c-sda-hold-time-ns = <300>; +@@ -114,6 +299,23 @@ &i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + status = "okay"; ++ ++ axp15060: pmic@36 { ++ compatible = "x-powers,axp15060"; ++ reg = <0x36>; ++ interrupts = <0>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ ++ regulators { ++ vdd_cpu: dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1540000>; ++ regulator-name = "vdd-cpu"; ++ }; ++ }; ++ }; + }; + + &i2c6 { +@@ -124,9 +326,164 @@ &i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + status = "okay"; ++ ++ imx219: imx219@10 { ++ compatible = "sony,imx219"; ++ reg = <0x10>; ++ clocks = <&clk_ext_camera>; ++ reset-gpio = <&sysgpio 18 0>; ++ rotation = <0>; ++ orientation = <1>; ++ ++ port { ++ imx219_to_csi2rx: endpoint { ++ remote-endpoint = <&csi2rx_from_imx219>; ++ bus-type = <4>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ link-frequencies = /bits/ 64 <456000000>; ++ }; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ max-frequency = <100000000>; ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ mmc-ddr-1_8v; ++ mmc-hs200-1_8v; ++ non-removable; ++ cap-mmc-hw-reset; ++ post-power-on-delay-ms = <200>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ max-frequency = <100000000>; ++ bus-width = <4>; ++ no-sdio; ++ no-mmc; ++ broken-cd; ++ cap-sd-highspeed; ++ post-power-on-delay-ms = <200>; ++ status = "okay"; ++}; ++ ++&pcie0 { ++ pinctrl-names = "default"; ++ reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy0>; ++ status = "okay"; ++}; ++ ++&pcie1 { ++ pinctrl-names = "default"; ++ reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; ++ phys = <&pciephy1>; ++ status = "okay"; ++}; ++ ++&ptc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&pwmdac { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwmdac_pins>; ++ status = "okay"; ++}; ++ ++&qspi { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ nor_flash: flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg=<0>; ++ cdns,read-delay = <5>; ++ spi-max-frequency = <12000000>; ++ cdns,tshsl-ns = <1>; ++ cdns,tsd2d-ns = <1>; ++ cdns,tchsh-ns = <1>; ++ cdns,tslch-ns = <1>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ spl@0 { ++ reg = <0x0 0x20000>; ++ }; ++ uboot@100000 { ++ reg = <0x100000 0x300000>; ++ }; ++ data@f00000 { ++ reg = <0xf00000 0x100000>; ++ }; ++ }; ++ }; ++}; ++ ++&stfcamss { ++ status = "okay"; ++ ++ ports { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ vin_from_csi2rx: endpoint@1 { ++ reg = <1>; ++ remote-endpoint = <&csi2rx_to_vin>; ++ status = "okay"; ++ }; ++ }; ++ }; + }; + + &sysgpio { ++ hdmi_pins: hdmi-0 { ++ hdmi-scl-pins { ++ pinmux = ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ hdmi-sda-pins { ++ pinmux = ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ hdmi-cec-pins { ++ pinmux = ; ++ input-enable; ++ bias-pull-up; ++ }; ++ ++ hdmi-hpd-pins { ++ pinmux = ; ++ input-enable; ++ bias-disable; /* external pull-up */ ++ }; ++ }; ++ + i2c0_pins: i2c0-0 { + i2c-pins { + pinmux = ; ++ bias-disable; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie0_clkreq_default: pcie0_clkreq_default { ++ clkreq-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie1_wake_default: pcie1_wake_default { ++ wake-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pcie1_clkreq_default: pcie1_clkreq_default { ++ clkreq-pins { ++ bias-disable; ++ pinmux = ; ++ drive-strength = <2>; ++ input-enable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pwm_pins: pwm-0 { ++ pwm-pins { ++ pinmux = , ++ ; ++ bias-disable; ++ drive-strength = <12>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ pwmdac_pins: pwmdac-0 { ++ pwmdac-pins { ++ pinmux = , ++ ; ++ bias-disable; ++ drive-strength = <2>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ }; ++ ++ tdm0_pins: tdm0-pins { ++ tdm0-pins-tx { ++ pinmux = ; ++ bias-pull-up; ++ drive-strength = <2>; ++ input-disable; ++ input-schmitt-disable; ++ slew-rate = <0>; ++ }; ++ ++ tdm0-pins-rx { ++ pinmux = ; ++ input-enable; ++ }; ++ ++ tdm0-pins-sync { ++ pinmux = ; ++ input-enable; ++ }; ++ ++ tdm0-pins-pcmclk { ++ pinmux = ; ++ input-enable; ++ }; ++ }; ++ + uart0_pins: uart0-0 { + tx-pins { + pinmux = ; ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; ++ ++&usb0 { ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&U74_1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&U74_4 { ++ cpu-supply = <&vdd_cpu>; ++}; +diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi +index 4c5fdb905da8..4d33dd85b9af 100644 +--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi ++++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi +@@ -6,6 +6,7 @@ + + /dts-v1/; + #include ++#include + #include + + / { +@@ -53,6 +54,9 @@ U74_1: cpu@1 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -79,6 +83,9 @@ U74_2: cpu@2 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -105,6 +112,9 @@ U74_3: cpu@3 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -131,6 +141,9 @@ U74_4: cpu@4 { + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; ++ operating-points-v2 = <&cpu_opp>; ++ clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; ++ clock-names = "cpu"; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; +@@ -164,6 +177,33 @@ core4 { + }; + }; + ++ cpu_opp: opp-table-0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ opp-375000000 { ++ opp-hz = /bits/ 64 <375000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-500000000 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-750000000 { ++ opp-hz = /bits/ 64 <750000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp-1500000000 { ++ opp-hz = /bits/ 64 <1500000000>; ++ opp-microvolt = <1040000>; ++ }; ++ }; ++ ++ dvp_clk: dvp-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "dvp_clk"; ++ #clock-cells = <0>; ++ }; ++ + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; +@@ -188,6 +228,12 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock { + #clock-cells = <0>; + }; + ++ hdmitx0_pixelclk: hdmitx0-pixel-clock { ++ compatible = "fixed-clock"; ++ clock-output-names = "hdmitx0_pixelclk"; ++ #clock-cells = <0>; ++ }; ++ + i2srx_bclk_ext: i2srx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_bclk_ext"; +@@ -236,6 +282,18 @@ tdm_ext: tdm-ext-clock { + #clock-cells = <0>; + }; + ++ display: display-subsystem { ++ compatible = "verisilicon,display-subsystem"; ++ ports = <&dc_out>; ++ }; ++ ++ stmmac_axi_setup: stmmac-axi-config { ++ snps,lpi_en; ++ snps,wr_osr_lmt = <4>; ++ snps,rd_osr_lmt = <4>; ++ snps,blen = <256 128 64 32 0 0 0>; ++ }; ++ + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; +@@ -353,6 +411,117 @@ i2c2: i2c@10050000 { + status = "disabled"; + }; + ++ tdm: tdm@10090000 { ++ compatible = "starfive,jh7110-tdm"; ++ reg = <0x0 0x10090000 0x0 0x1000>; ++ clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, ++ <&syscrg JH7110_SYSCLK_TDM_APB>, ++ <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, ++ <&syscrg JH7110_SYSCLK_TDM_TDM>, ++ <&syscrg JH7110_SYSCLK_MCLK_INNER>, ++ <&tdm_ext>; ++ clock-names = "tdm_ahb", "tdm_apb", ++ "tdm_internal", "tdm", ++ "mclk_inner", "tdm_ext"; ++ resets = <&syscrg JH7110_SYSRST_TDM_AHB>, ++ <&syscrg JH7110_SYSRST_TDM_APB>, ++ <&syscrg JH7110_SYSRST_TDM_CORE>; ++ dmas = <&dma 20>, <&dma 21>; ++ dma-names = "rx","tx"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwmdac: pwmdac@100b0000 { ++ compatible = "starfive,jh7110-pwmdac"; ++ reg = <0x0 0x100b0000 0x0 0x1000>; ++ clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>, ++ <&syscrg JH7110_SYSCLK_PWMDAC_CORE>; ++ clock-names = "apb", "core"; ++ resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>; ++ dmas = <&dma 22>; ++ dma-names = "tx"; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ usb0: usb@10100000 { ++ compatible = "starfive,jh7110-usb"; ++ ranges = <0x0 0x0 0x10100000 0x100000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ starfive,stg-syscon = <&stg_syscon 0x4>; ++ clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, ++ <&stgcrg JH7110_STGCLK_USB0_STB>, ++ <&stgcrg JH7110_STGCLK_USB0_APB>, ++ <&stgcrg JH7110_STGCLK_USB0_AXI>, ++ <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; ++ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; ++ resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, ++ <&stgcrg JH7110_STGRST_USB0_APB>, ++ <&stgcrg JH7110_STGRST_USB0_AXI>, ++ <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; ++ reset-names = "pwrup", "apb", "axi", "utmi_apb"; ++ status = "disabled"; ++ ++ usb_cdns3: usb@0 { ++ compatible = "cdns,usb3"; ++ reg = <0x0 0x10000>, ++ <0x10000 0x10000>, ++ <0x20000 0x10000>; ++ reg-names = "otg", "xhci", "dev"; ++ interrupts = <100>, <108>, <110>; ++ interrupt-names = "host", "peripheral", "otg"; ++ phys = <&usbphy0>; ++ phy-names = "cdns3,usb2-phy"; ++ }; ++ }; ++ ++ usbphy0: phy@10200000 { ++ compatible = "starfive,jh7110-usb-phy"; ++ reg = <0x0 0x10200000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&stgcrg JH7110_STGCLK_USB0_APP_125>; ++ clock-names = "125m", "app_125m"; ++ #phy-cells = <0>; ++ }; ++ ++ pciephy0: phy@10210000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x0 0x10210000 0x0 0x10000>; ++ #phy-cells = <0>; ++ }; ++ ++ pciephy1: phy@10220000 { ++ compatible = "starfive,jh7110-pcie-phy"; ++ reg = <0x0 0x10220000 0x0 0x10000>; ++ #phy-cells = <0>; ++ }; ++ ++ stgcrg: clock-controller@10230000 { ++ compatible = "starfive,jh7110-stgcrg"; ++ reg = <0x0 0x10230000 0x0 0x10000>; ++ clocks = <&osc>, ++ <&syscrg JH7110_SYSCLK_HIFI4_CORE>, ++ <&syscrg JH7110_SYSCLK_STG_AXIAHB>, ++ <&syscrg JH7110_SYSCLK_USB_125M>, ++ <&syscrg JH7110_SYSCLK_CPU_BUS>, ++ <&syscrg JH7110_SYSCLK_HIFI4_AXI>, ++ <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, ++ <&syscrg JH7110_SYSCLK_APB_BUS>; ++ clock-names = "osc", "hifi4_core", ++ "stg_axiahb", "usb_125m", ++ "cpu_bus", "hifi4_axi", ++ "nocstg_bus", "apb_bus"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ stg_syscon: syscon@10240000 { ++ compatible = "starfive,jh7110-stg-syscon", "syscon"; ++ reg = <0x0 0x10240000 0x0 0x1000>; ++ }; ++ + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; +@@ -440,6 +609,45 @@ i2c6: i2c@12060000 { + status = "disabled"; + }; + ++ ptc: pwm@120d0000 { ++ compatible = "starfive,jh7110-pwm"; ++ reg = <0x0 0x120d0000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; ++ resets = <&syscrg JH7110_SYSRST_PWM_APB>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ sfctemp: temperature-sensor@120e0000 { ++ compatible = "starfive,jh7110-temp"; ++ reg = <0x0 0x120e0000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, ++ <&syscrg JH7110_SYSCLK_TEMP_APB>; ++ clock-names = "sense", "bus"; ++ resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, ++ <&syscrg JH7110_SYSRST_TEMP_APB>; ++ reset-names = "sense", "bus"; ++ #thermal-sensor-cells = <0>; ++ }; ++ ++ qspi: spi@13010000 { ++ compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; ++ reg = <0x0 0x13010000 0x0 0x10000 ++ 0x0 0x21000000 0x0 0x400000>; ++ interrupts = <25>; ++ clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, ++ <&syscrg JH7110_SYSCLK_QSPI_AHB>, ++ <&syscrg JH7110_SYSCLK_QSPI_APB>; ++ clock-names = "ref", "ahb", "apb"; ++ resets = <&syscrg JH7110_SYSRST_QSPI_APB>, ++ <&syscrg JH7110_SYSRST_QSPI_AHB>, ++ <&syscrg JH7110_SYSRST_QSPI_REF>; ++ reset-names = "qspi", "qspi-ocp", "rstc_ref"; ++ cdns,fifo-depth = <256>; ++ cdns,fifo-width = <4>; ++ cdns,trigger-address = <0x0>; ++ }; ++ + syscrg: clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x0 0x13020000 0x0 0x10000>; +@@ -447,16 +655,31 @@ syscrg: clock-controller@13020000 { + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, +- <&tdm_ext>, <&mclk_ext>; ++ <&tdm_ext>, <&mclk_ext>, ++ <&pllclk JH7110_CLK_PLL0_OUT>, ++ <&pllclk JH7110_CLK_PLL1_OUT>, ++ <&pllclk JH7110_CLK_PLL2_OUT>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", +- "tdm_ext", "mclk_ext"; ++ "tdm_ext", "mclk_ext", ++ "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + ++ sys_syscon: syscon@13030000 { ++ compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; ++ reg = <0x0 0x13030000 0x0 0x1000>; ++ ++ pllclk: clock-controller { ++ compatible = "starfive,jh7110-pll"; ++ clocks = <&osc>; ++ #clock-cells = <1>; ++ }; ++ }; ++ + sysgpio: pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; +@@ -469,6 +692,187 @@ sysgpio: pinctrl@13040000 { + #gpio-cells = <2>; + }; + ++ timer@13050000 { ++ compatible = "starfive,jh7110-timer"; ++ reg = <0x0 0x13050000 0x0 0x10000>; ++ interrupts = <69>, <70>, <71> ,<72>; ++ clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>, ++ <&syscrg JH7110_SYSCLK_TIMER0>, ++ <&syscrg JH7110_SYSCLK_TIMER1>, ++ <&syscrg JH7110_SYSCLK_TIMER2>, ++ <&syscrg JH7110_SYSCLK_TIMER3>; ++ clock-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ resets = <&syscrg JH7110_SYSRST_TIMER_APB>, ++ <&syscrg JH7110_SYSRST_TIMER0>, ++ <&syscrg JH7110_SYSRST_TIMER1>, ++ <&syscrg JH7110_SYSRST_TIMER2>, ++ <&syscrg JH7110_SYSRST_TIMER3>; ++ reset-names = "apb", "ch0", "ch1", ++ "ch2", "ch3"; ++ }; ++ ++ watchdog@13070000 { ++ compatible = "starfive,jh7110-wdt"; ++ reg = <0x0 0x13070000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, ++ <&syscrg JH7110_SYSCLK_WDT_CORE>; ++ clock-names = "apb", "core"; ++ resets = <&syscrg JH7110_SYSRST_WDT_APB>, ++ <&syscrg JH7110_SYSRST_WDT_CORE>; ++ }; ++ ++ crypto: crypto@16000000 { ++ compatible = "starfive,jh7110-crypto"; ++ reg = <0x0 0x16000000 0x0 0x4000>; ++ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, ++ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; ++ clock-names = "hclk", "ahb"; ++ interrupts = <28>; ++ resets = <&stgcrg JH7110_STGRST_SEC_AHB>; ++ dmas = <&sdma 1 2>, <&sdma 0 2>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ sdma: dma@16008000 { ++ compatible = "arm,pl080", "arm,primecell"; ++ arm,primecell-periphid = <0x00041080>; ++ reg = <0x0 0x16008000 0x0 0x4000>; ++ interrupts = <29>; ++ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, ++ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; ++ clock-names = "hclk", "apb_pclk"; ++ resets = <&stgcrg JH7110_STGRST_SEC_AHB>; ++ lli-bus-interface-ahb1; ++ mem-bus-interface-ahb1; ++ memcpy-burst-size = <256>; ++ memcpy-bus-width = <32>; ++ #dma-cells = <2>; ++ }; ++ ++ rng: rng@1600c000 { ++ compatible = "starfive,jh7110-trng"; ++ reg = <0x0 0x1600C000 0x0 0x4000>; ++ clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, ++ <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; ++ clock-names = "hclk", "ahb"; ++ resets = <&stgcrg JH7110_STGRST_SEC_AHB>; ++ interrupts = <30>; ++ }; ++ ++ mmc0: mmc@16010000 { ++ compatible = "starfive,jh7110-mmc"; ++ reg = <0x0 0x16010000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, ++ <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; ++ clock-names = "biu","ciu"; ++ resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; ++ reset-names = "reset"; ++ interrupts = <74>; ++ fifo-depth = <32>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; ++ status = "disabled"; ++ }; ++ ++ mmc1: mmc@16020000 { ++ compatible = "starfive,jh7110-mmc"; ++ reg = <0x0 0x16020000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, ++ <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; ++ clock-names = "biu","ciu"; ++ resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; ++ reset-names = "reset"; ++ interrupts = <75>; ++ fifo-depth = <32>; ++ fifo-watermark-aligned; ++ data-addr = <0>; ++ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; ++ status = "disabled"; ++ }; ++ ++ gmac0: ethernet@16030000 { ++ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; ++ reg = <0x0 0x16030000 0x0 0x10000>; ++ clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, ++ <&aoncrg JH7110_AONCLK_GMAC0_AHB>, ++ <&syscrg JH7110_SYSCLK_GMAC0_PTP>, ++ <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, ++ <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; ++ clock-names = "stmmaceth", "pclk", "ptp_ref", ++ "tx", "gtx"; ++ resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, ++ <&aoncrg JH7110_AONRST_GMAC0_AHB>; ++ reset-names = "stmmaceth", "ahb"; ++ interrupts = <7>, <6>, <5>; ++ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; ++ rx-fifo-depth = <2048>; ++ tx-fifo-depth = <2048>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <8>; ++ snps,fixed-burst; ++ snps,no-pbl-x8; ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,tso; ++ snps,en-tx-lpi-clockgating; ++ snps,txpbl = <16>; ++ snps,rxpbl = <16>; ++ starfive,syscon = <&aon_syscon 0xc 0x12>; ++ status = "disabled"; ++ }; ++ ++ gmac1: ethernet@16040000 { ++ compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; ++ reg = <0x0 0x16040000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, ++ <&syscrg JH7110_SYSCLK_GMAC1_AHB>, ++ <&syscrg JH7110_SYSCLK_GMAC1_PTP>, ++ <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, ++ <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; ++ clock-names = "stmmaceth", "pclk", "ptp_ref", ++ "tx", "gtx"; ++ resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, ++ <&syscrg JH7110_SYSRST_GMAC1_AHB>; ++ reset-names = "stmmaceth", "ahb"; ++ interrupts = <78>, <77>, <76>; ++ interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; ++ rx-fifo-depth = <2048>; ++ tx-fifo-depth = <2048>; ++ snps,multicast-filter-bins = <64>; ++ snps,perfect-filter-entries = <8>; ++ snps,fixed-burst; ++ snps,no-pbl-x8; ++ snps,force_thresh_dma_mode; ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,tso; ++ snps,en-tx-lpi-clockgating; ++ snps,txpbl = <16>; ++ snps,rxpbl = <16>; ++ starfive,syscon = <&sys_syscon 0x90 0x2>; ++ status = "disabled"; ++ }; ++ ++ dma: dma-controller@16050000 { ++ compatible = "starfive,jh7110-axi-dma"; ++ reg = <0x0 0x16050000 0x0 0x10000>; ++ clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, ++ <&stgcrg JH7110_STGCLK_DMA1P_AHB>; ++ clock-names = "core-clk", "cfgr-clk"; ++ resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, ++ <&stgcrg JH7110_STGRST_DMA1P_AHB>; ++ interrupts = <73>; ++ #dma-cells = <1>; ++ dma-channels = <4>; ++ snps,dma-masters = <1>; ++ snps,data-width = <3>; ++ snps,block-size = <65536 65536 65536 65536>; ++ snps,priority = <0 1 2 3>; ++ snps,axi-max-burst-len = <16>; ++ }; ++ + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; +@@ -486,6 +890,12 @@ aoncrg: clock-controller@17000000 { + #reset-cells = <1>; + }; + ++ aon_syscon: syscon@17010000 { ++ compatible = "starfive,jh7110-aon-syscon", "syscon"; ++ reg = <0x0 0x17010000 0x0 0x1000>; ++ #power-domain-cells = <1>; ++ }; ++ + aongpio: pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; +@@ -496,5 +906,252 @@ aongpio: pinctrl@17020000 { + gpio-controller; + #gpio-cells = <2>; + }; ++ ++ pwrc: power-controller@17030000 { ++ compatible = "starfive,jh7110-pmu"; ++ reg = <0x0 0x17030000 0x0 0x10000>; ++ interrupts = <111>; ++ #power-domain-cells = <1>; ++ }; ++ ++ csi2rx: csi-bridge@19800000 { ++ compatible = "starfive,jh7110-csi2rx"; ++ reg = <0x0 0x19800000 0x0 0x10000>; ++ clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, ++ <&ispcrg JH7110_ISPCLK_VIN_APB>, ++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, ++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, ++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, ++ <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; ++ clock-names = "sys_clk", "p_clk", ++ "pixel_if0_clk", "pixel_if1_clk", ++ "pixel_if2_clk", "pixel_if3_clk"; ++ resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, ++ <&ispcrg JH7110_ISPRST_VIN_APB>, ++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, ++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, ++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, ++ <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; ++ reset-names = "sys", "reg_bank", ++ "pixel_if0", "pixel_if1", ++ "pixel_if2", "pixel_if3"; ++ phys = <&csi_phy>; ++ phy-names = "dphy"; ++ status = "disabled"; ++ }; ++ ++ ispcrg: clock-controller@19810000 { ++ compatible = "starfive,jh7110-ispcrg"; ++ reg = <0x0 0x19810000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, ++ <&dvp_clk>; ++ clock-names = "isp_top_core", "isp_top_axi", ++ "noc_bus_isp_axi", "dvp_clk"; ++ resets = <&syscrg JH7110_SYSRST_ISP_TOP>, ++ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, ++ <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_ISP>; ++ }; ++ ++ csi_phy: phy@19820000 { ++ compatible = "starfive,jh7110-dphy-rx"; ++ reg = <0x0 0x19820000 0x0 0x10000>; ++ clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, ++ <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, ++ <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; ++ clock-names = "cfg", "ref", "tx"; ++ resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, ++ <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; ++ power-domains = <&aon_syscon JH7110_PD_DPHY_RX>; ++ #phy-cells = <0>; ++ }; ++ ++ stfcamss: camss@19840000 { ++ compatible = "starfive,jh7110-camss"; ++ reg = <0x0 0x19840000 0x0 0x10000>, ++ <0x0 0x19870000 0x0 0x30000>; ++ reg-names = "syscon", "isp"; ++ clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, ++ <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, ++ <&ispcrg JH7110_ISPCLK_DVP_INV>, ++ <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, ++ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, ++ <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; ++ clock-names = "clk_apb_func", ++ "clk_wrapper_clk_c", ++ "clk_dvp_inv", ++ "clk_axiwr", ++ "clk_mipi_rx0_pxl", ++ "clk_ispcore_2x", ++ "clk_isp_axi"; ++ resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, ++ <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, ++ <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, ++ <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, ++ <&syscrg JH7110_SYSRST_ISP_TOP>, ++ <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; ++ reset-names = "rst_wrapper_p", ++ "rst_wrapper_c", ++ "rst_axird", ++ "rst_axiwr", ++ "rst_isp_top_n", ++ "rst_isp_top_axi"; ++ power-domains = <&pwrc JH7110_PD_ISP>; ++ /* irq nr: vin, isp, isp_csi, isp_csiline */ ++ interrupts = <92>, <87>, <90>; ++ status = "disabled"; ++ }; ++ ++ dc8200: dc8200@29400000 { ++ compatible = "verisilicon,dc8200"; ++ reg = <0x0 0x29400000 0x0 0x100>, ++ <0x0 0x29400800 0x0 0x2000>, ++ <0x0 0x295B0000 0x0 0x90>; ++ interrupts = <95>; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_AHB>, ++ <&hdmitx0_pixelclk>, ++ <&voutcrg JH7110_VOUTCLK_DC8200_PIX>; ++ clock-names = "clk_vout_noc_disp", ++ "clk_vout_pix0","clk_vout_pix1", ++ "clk_vout_axi","clk_vout_core", ++ "clk_vout_vout_ahb","hdmitx0_pixel", ++ "clk_vout_dc8200"; ++ resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>, ++ <&voutcrg JH7110_VOUTRST_DC8200_AHB>, ++ <&voutcrg JH7110_VOUTRST_DC8200_CORE>; ++ reset-names = "rst_vout_axi","rst_vout_ahb", ++ "rst_vout_core"; ++ }; ++ ++ hdmi: hdmi@29590000 { ++ compatible = "starfive,hdmi"; ++ reg = <0x0 0x29590000 0x0 0x4000>; ++ interrupts = <99>; ++ ++ clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, ++ <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, ++ <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "sysclk", "mclk","bclk","pclk"; ++ resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; ++ reset-names = "hdmi_tx"; ++ #sound-dai-cells = <0>; ++ }; ++ ++ voutcrg: clock-controller@295c0000 { ++ compatible = "starfive,jh7110-voutcrg"; ++ reg = <0x0 0x295c0000 0x0 0x10000>; ++ clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, ++ <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, ++ <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, ++ <&hdmitx0_pixelclk>; ++ clock-names = "vout_src", "vout_top_ahb", ++ "vout_top_axi", "vout_top_hdmitx0_mclk", ++ "i2stx0_bclk", "hdmitx0_pixelclk"; ++ resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ power-domains = <&pwrc JH7110_PD_VOUT>; ++ }; ++ ++ pcie0: pcie@2B000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2B000000 0x0 0x1000000 ++ 0x9 0x40000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; ++ interrupts = <56>; ++ interrupt-parent = <&plic>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; ++ msi-parent = <&pcie0>; ++ msi-controller; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE0_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE0_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE0_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE0_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE0_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc0: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; ++ ++ pcie1: pcie@2C000000 { ++ compatible = "starfive,jh7110-pcie"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ reg = <0x0 0x2C000000 0x0 0x1000000 ++ 0x9 0xc0000000 0x0 0x10000000>; ++ reg-names = "reg", "config"; ++ device_type = "pci"; ++ starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, ++ <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; ++ interrupts = <57>; ++ interrupt-parent = <&plic>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, ++ <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, ++ <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, ++ <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; ++ msi-parent = <&pcie1>; ++ msi-controller; ++ clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, ++ <&stgcrg JH7110_STGCLK_PCIE1_TL>, ++ <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGCLK_PCIE1_APB>; ++ clock-names = "noc", "tl", "axi_mst0", "apb"; ++ resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, ++ <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, ++ <&stgcrg JH7110_STGRST_PCIE1_BRG>, ++ <&stgcrg JH7110_STGRST_PCIE1_CORE>, ++ <&stgcrg JH7110_STGRST_PCIE1_APB>; ++ reset-names = "mst0", "slv0", "slv", "brg", ++ "core", "apb"; ++ status = "disabled"; ++ ++ pcie_intc1: interrupt-controller { ++ #address-cells = <0>; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ }; + }; + }; +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0071-drm-verisilicon-add-missing-null-entry-in-vs_drm_dt_.patch b/srcpkgs/linux6.4/patches/0071-drm-verisilicon-add-missing-null-entry-in-vs_drm_dt_.patch new file mode 100644 index 0000000000000..ca3418ad6a5a1 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0071-drm-verisilicon-add-missing-null-entry-in-vs_drm_dt_.patch @@ -0,0 +1,25 @@ +From 7cfe30ea4d73d89d04a381c24008232f0b266789 Mon Sep 17 00:00:00 2001 +From: Nick Cao +Date: Sat, 1 Jul 2023 17:19:22 +0800 +Subject: [PATCH 71/72] drm/verisilicon: add missing null entry in + vs_drm_dt_ids + +--- + drivers/gpu/drm/verisilicon/vs_drv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index b740fe934035..1255a373f7a2 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -258,6 +258,7 @@ static SIMPLE_DEV_PM_OPS(vs_drm_pm_ops, vs_drm_suspend, vs_drm_resume); + + static const struct of_device_id vs_drm_dt_ids[] = { + { .compatible = "verisilicon,display-subsystem", }, ++ {}, + }; + + MODULE_DEVICE_TABLE(of, vs_drm_dt_ids); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/patches/0072-drm-verisilicon-import-DMA_BUF-namespace.patch b/srcpkgs/linux6.4/patches/0072-drm-verisilicon-import-DMA_BUF-namespace.patch new file mode 100644 index 0000000000000..10fe9f57acf07 --- /dev/null +++ b/srcpkgs/linux6.4/patches/0072-drm-verisilicon-import-DMA_BUF-namespace.patch @@ -0,0 +1,22 @@ +From 5d5245e14c6d38af7f5db3642426fe319e92926f Mon Sep 17 00:00:00 2001 +From: Nick Cao +Date: Sat, 1 Jul 2023 17:49:05 +0800 +Subject: [PATCH 72/72] drm/verisilicon: import DMA_BUF namespace + +--- + drivers/gpu/drm/verisilicon/vs_drv.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/verisilicon/vs_drv.c b/drivers/gpu/drm/verisilicon/vs_drv.c +index 1255a373f7a2..8627027047aa 100644 +--- a/drivers/gpu/drm/verisilicon/vs_drv.c ++++ b/drivers/gpu/drm/verisilicon/vs_drv.c +@@ -299,4 +299,5 @@ module_init(vs_drm_init); + module_exit(vs_drm_fini); + + MODULE_DESCRIPTION("VeriSilicon DRM Driver"); ++MODULE_IMPORT_NS(DMA_BUF); + MODULE_LICENSE("GPL"); +-- +2.41.0 + diff --git a/srcpkgs/linux6.4/template b/srcpkgs/linux6.4/template index 575ce63df061a..4321e87a3ea22 100644 --- a/srcpkgs/linux6.4/template +++ b/srcpkgs/linux6.4/template @@ -18,7 +18,7 @@ checksum="8fa0588f0c2ceca44cac77a0e39ba48c9f00a6b9dc69761c02a5d3efac8da7f3 python_version=3 # XXX Restrict archs until a proper -dotconfig is available in FILESDIR. -archs="x86_64* i686* aarch64*" +archs="x86_64* i686* aarch64* riscv64*" nodebug=yes # -dbg package is generated below manually nostrip=yes From 32f0c375bdf914f4ef931f221a01badcd29313a9 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Sat, 26 Aug 2023 14:52:36 +0200 Subject: [PATCH 188/189] [DO NOT MERGE] cross-riscv64-linux-musl: bump to musl 1.2.4 --- srcpkgs/cross-riscv64-linux-musl/template | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/srcpkgs/cross-riscv64-linux-musl/template b/srcpkgs/cross-riscv64-linux-musl/template index d20751fd9fdb6..20e014ff0501f 100644 --- a/srcpkgs/cross-riscv64-linux-musl/template +++ b/srcpkgs/cross-riscv64-linux-musl/template @@ -1,12 +1,12 @@ # Template file for 'cross-riscv64-linux-musl' _binutils_version=2.39 _gcc_version=12.2.0 -_musl_version=1.1.24 +_musl_version=1.2.4 _linux_version=5.10.4 _libucontext_version=1.0 pkgname=cross-riscv64-linux-musl version=0.35 -revision=2 +revision=666 build_style=void-cross configure_args="--with-arch=rv64gc --with-abi=lp64d --enable-autolink-libatomic --disable-multilib" hostmakedepends="texinfo tar gcc-objc gcc-go flex perl python3 pkg-config" @@ -25,7 +25,7 @@ distfiles=" https://github.com/kaniini/libucontext/archive/libucontext-${_libucontext_version}.tar.gz" checksum="645c25f563b8adc0a81dbd6a41cffbf4d37083a382e02d5d3df4f65c09516d00 e549cf9cf3594a00e27b6589d4322d70e0720cdd213f39beb4181e06926230ff - 1370c9a812b2cf2a7d92802510cca0058cc37e66a7bedd70051f0a34015022a3 + 7a35eae33d5372a7c0da1188de798726f68825513b7ae3ebe97aaaa52114f039 904e396c26e9992a16cd1cc989460171536bed7739bf36049f6eb020ee5d56ec 23714e99a87f6dea82e8a073c526325161dd65462459820b16a6162be91955bb" nocross=yes From f77720d87d5088108d5249e3de099ff93403c001 Mon Sep 17 00:00:00 2001 From: Leah Neukirchen Date: Sat, 26 Aug 2023 14:52:57 +0200 Subject: [PATCH 189/189] [DO NOT MERGE] musl: drop patch --- srcpkgs/musl/patches/00-reallocarray.patch | 42 ---------------------- srcpkgs/musl/patches/00empty.patch | 0 2 files changed, 42 deletions(-) delete mode 100644 srcpkgs/musl/patches/00-reallocarray.patch create mode 100644 srcpkgs/musl/patches/00empty.patch diff --git a/srcpkgs/musl/patches/00-reallocarray.patch b/srcpkgs/musl/patches/00-reallocarray.patch deleted file mode 100644 index cfaab330e89ad..0000000000000 --- a/srcpkgs/musl/patches/00-reallocarray.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 821083ac7b54eaa040d5a8ddc67c6206a175e0ca Mon Sep 17 00:00:00 2001 -From: Ariadne Conill -Date: Sat, 1 Aug 2020 08:26:35 -0600 -Subject: [PATCH] implement reallocarray - -reallocarray is an extension introduced by OpenBSD, which introduces -calloc overflow checking to realloc. - -glibc 2.28 introduced support for this function behind _GNU_SOURCE, -while glibc 2.29 allows its usage in _DEFAULT_SOURCE. - -diff --git a/include/stdlib.h b/include/stdlib.h -index 194c2033..b54a051f 100644 ---- a/include/stdlib.h -+++ b/include/stdlib.h -@@ -145,6 +145,7 @@ int getloadavg(double *, int); - int clearenv(void); - #define WCOREDUMP(s) ((s) & 0x80) - #define WIFCONTINUED(s) ((s) == 0xffff) -+void *reallocarray (void *, size_t, size_t); - #endif - - #ifdef _GNU_SOURCE -diff --git a/src/malloc/reallocarray.c b/src/malloc/reallocarray.c -new file mode 100644 -index 00000000..4a6ebe46 ---- /dev/null -+++ b/src/malloc/reallocarray.c -@@ -0,0 +1,13 @@ -+#define _BSD_SOURCE -+#include -+#include -+ -+void *reallocarray(void *ptr, size_t m, size_t n) -+{ -+ if (n && m > -1 / n) { -+ errno = ENOMEM; -+ return 0; -+ } -+ -+ return realloc(ptr, m * n); -+} diff --git a/srcpkgs/musl/patches/00empty.patch b/srcpkgs/musl/patches/00empty.patch new file mode 100644 index 0000000000000..e69de29bb2d1d