From 00dc5bd620f2ba0db6ed5489dab1c63b5e728cad Mon Sep 17 00:00:00 2001
From: q66 <daniel@octaforge.org>
Date: Sun, 1 Sep 2019 00:47:00 +0200
Subject: [PATCH] gsl: add patch to fix build on ppc-musl

[ci skip]
---
 srcpkgs/gsl/patches/ppc-musl.patch | 36 ++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 srcpkgs/gsl/patches/ppc-musl.patch

diff --git a/srcpkgs/gsl/patches/ppc-musl.patch b/srcpkgs/gsl/patches/ppc-musl.patch
new file mode 100644
index 00000000000..807ae163675
--- /dev/null
+++ b/srcpkgs/gsl/patches/ppc-musl.patch
@@ -0,0 +1,36 @@
+fpu_control.h is glibc specific, but we only need some bits from it.
+
+--- ieee-utils/fp-gnuppc.c
++++ ieee-utils/fp-gnuppc.c
+@@ -18,7 +18,31 @@
+  */
+ 
+ #include <stdio.h>
++
++#if defined(__GLIBC__)
+ #include <fpu_control.h>
++#else
++/* copied from fpu_control.h, only stuff that is needed here */
++# define _FPU_RC_NEAREST 0x00
++# define _FPU_RC_DOWN    0x03
++# define _FPU_RC_UP      0x02
++# define _FPU_RC_ZERO    0x01
++
++# define _FPU_MASK_ZM  0x10
++# define _FPU_MASK_OM  0x40
++# define _FPU_MASK_UM  0x20
++# define _FPU_MASK_IM  0x80 
++
++# define _FPU_SETCW(cw)						\
++  { union { double __d; unsigned long long __ll; } __u;		\
++    register double __fr;					\
++    __u.__ll = 0xfff80000LL << 32; /* This is a QNaN.  */	\
++    __u.__ll |= (cw) & 0xffffffffLL;				\
++    __fr = __u.__d;						\
++    __asm__ __volatile__("mtfsf 255,%0" : : "f" (__fr));	\
++  }
++#endif
++
+ #include <gsl/gsl_errno.h>
+ #include <gsl/gsl_ieee_utils.h>
+