[9fans] TAS

[9fans] TAS

[pip]

My brief perusal of the source seems to indicate that tas(), called in
sys/src/9/port/taslock.c, is implemented in the architecture specific l.s.
There it seems, we splhi then issue a TAS instruction. For the SPARC
architecture for example, it seems TAS maps onto a `swap' instruction,
going from the plan9 asm to the underlying V8 asm, or something along
those lines.

Why implement tas() as a function, rather than do what it does inline.
Does the additional overhead of doing a function call make this act less
atomic ?

[9fans] TAS

[pip]

On Sat, 19 Jun 1999, Nigel Roles wrote:

>>> Why implement as a call? Because inlining is not supported by the
>>> compiler,
I think you may have misunderstood what I meant when I said 'inline'. I
did not mean like gcc's __inline__ or C++ inline fxns. I meant doing it
maually.

>>> anyway the instruction sequence has a very strong chance of being
>>> cached as it is used a lot, so performance is not really an issue.
???


>>> Does this make it less atomic? No. The assembler instruction is just
>>> as atomic as it was before. This is all that matters.
But what about the additional stack manipulations involved in a function
call ? I agree that things have to be done the way they are, and that
advantage has to be taken of the processors equivalent of a TSL
instruction.

[9fans] TAS

[forsyth]

>>architecture for example, it seems TAS maps onto a `swap' instruction,
>> ...
>>Why implement tas() as a function, rather than do what it does inline.

it needs to use an instruction that guarantees interlock (on a multiprocessor)
and i assume `swap' does that on the sparc.  the instruction needed will be
peculiar to an architecture, hence it's found in a platform-dependent
function separate from the portable code.  the linkers are in a position to
inline things if need be (and do actually do some code shuffling as it is,
though not perhaps in this case -- i haven't looked).

[9fans] TAS

[Nigel]

Why implement as a call? Because inlining is not supported by the compiler,
and
anyway the instruction sequence has a very strong chance of being cached as
it is
used a lot, so performance is not really an issue.

Does this make it less atomic? No. The assembler instruction is just as
atomic as
it was before. This is all that matters.

-----Original Message-----
From: pip [mailto:pip@cpu.khimaira.com]
Sent: Friday, June 18, 1999 5:56 PM
To: 9fans@cse.psu.edu
Subject: [9fans] TAS



My brief perusal of the source seems to indicate that tas(), called in
sys/src/9/port/taslock.c, is implemented in the architecture specific l.s.
There it seems, we splhi then issue a TAS instruction. For the SPARC
architecture for example, it seems TAS maps onto a `swap' instruction,
going from the plan9 asm to the underlying V8 asm, or something along
those lines.

Why implement tas() as a function, rather than do what it does inline.
Does the additional overhead of doing a function call make this act less
atomic ?