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From: Steven Stallion <sstallion@gmail.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
Subject: Re: [9fans] FP register usage in Plan9 assembler
Date: Wed,  3 Feb 2016 09:51:50 -0600	[thread overview]
Message-ID: <CAGGHmKGf4t9ugTuFDTznUZg1puvMxyib76SP5sdGPOG=AiikHg@mail.gmail.com> (raw)
In-Reply-To: <fc42bda0163394857779140dd988c036@lilly.quanstro.net>

On Wed, Feb 3, 2016 at 9:24 AM, erik quanstrom <quanstro@quanstro.net> wrote:

> i think this is off the original point, but as to modifying the assmbler.
> to add a new instruction, the linker, assembler and libmach need modification.
> typically this is a matter of adding a line to each one for assembly, linking,
> and disassembly, respecively.  it's worth looking at the addition of the ymm,
> and then zmm registers and those patterns to 6[al] and libmach.  this is an
> example of adding a new instruction encoding to an existing arch.
>
>> * The diff to update support for ARMv7-A to 5a came in at over 2800
>> lines; this was to add a handful of instructions.
>
> do you perhaps mean the linker?
>
> the pi kernels, which supports v6 (original) and v7 (pi2) rely on small asm
> files for arch-specific functions.  i think you provided some explaination of
> why this approach would not work for v5, but unfortunately, i don't remember
> it.

The patch ended up in the usual place on sources. The patch itself
modernized all of the v7-A ports (this pre-dated the pi2 port by a
couple of years) to support common instructions rather than cramming
opcodes into the instruction stream. The exynos port relied on it
heavily since the Cortex-A15 required a bit more special handling than
the simpler cores in the omap, pi2, and teg2 ports. As you mentioned,
5[al], libmach, even acid were updated. You really can't touch one
thing without modifying everything else.

WRT to drawbacks in the loader for writing assembly, one of the
biggest problems is merciless optimization that cannot be disabled on
a per translation-unit basis (we're using a loader, remember?) As an
example, it's damned near impossible to perform PC-relative branching
in the vector table. Instead you end up having to the slower (and
sillier) load method that exists today.

As far as consistency between architectures go, it's a non-goal for
me. C is my portability layer - odds are very good that if I need to
dip into assembly, I need complete control over the instruction
stream.

Steve



  reply	other threads:[~2016-02-03 15:51 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-01 16:47 Giacomo Tesio
2016-02-01 22:38 ` Charles Forsyth
2016-02-01 22:44   ` Charles Forsyth
2016-02-01 22:48 ` cinap_lenrek
2016-02-01 23:34   ` Giacomo Tesio
2016-02-02  0:36     ` Charles Forsyth
2016-02-02  0:58       ` Giacomo Tesio
2016-02-02 12:39         ` Aram Hăvărneanu
2016-02-02 16:42 ` Steven Stallion
2016-02-02 17:16   ` lucio
2016-02-03 15:24   ` erik quanstrom
2016-02-03 15:51     ` Steven Stallion [this message]
2016-02-03 16:36       ` erik quanstrom
2016-02-04 10:08     ` Aram Hăvărneanu
2016-02-04 12:04       ` lucio
2016-02-04 15:58         ` Ryan Gonzalez
2016-02-04 16:09           ` lucio
2016-02-04 18:06             ` Ryan Gonzalez
2016-02-04 18:14               ` balaji
2016-02-04 18:28             ` Ryan Gonzalez
2016-02-04 19:31           ` Skip Tavakkolian
2016-02-04 12:24       ` Brantley Coile
2016-02-04 12:53         ` lucio
2016-02-04 14:57           ` erik quanstrom
2016-02-04 14:05         ` Aram Hăvărneanu
2016-02-04 14:10           ` Aram Hăvărneanu
2016-02-04 14:30             ` Aram Hăvărneanu
2016-02-04 15:07         ` Charles Forsyth
2016-02-04 15:16           ` erik quanstrom
2016-02-04 15:11         ` erik quanstrom
2016-02-04 15:22           ` erik quanstrom
2016-02-04 15:26             ` Charles Forsyth
2016-02-04 20:34               ` erik quanstrom

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