Re: [9front] 9front on Raspberry Pi 400

[cinap_lenrek@felloff.net]

ok, so it seems on the CM4 and PI400 with newer firmware, they changed
the pcie inbound window address space. which is the range of addresses
as seen from a pci device perspecive doing busmaster dma towards memory
on the host system.

this also means we need to configure the inbound windows differently
in the pcie controller and also that drivers offset physical memory
addresses by that window base when passing them to pci devices for dma.

this is done by the PCIWADDR() macro, which currently just translates
to physical address and then adds PCIWINDOW constant, which in the
previous address scheme was 0 (no translation).

so the problem is likely that the xhcireset firmware call places the
firmware image somewhere in memory, and then the xhci controller is
not able to reach it because we assume a "no translation" regime in the
pcie controller. also the window we program is currently limited to
1GB so not all dma memory can be targeted, but this was not a problem
as we only do dma to kernel memory and the kernel memory pool fits in
that range.

to top it off, all this garbage is communicated thru devicetree blobs,
which we only partially support at this point. (mainly just to get
the sdram memory sizes and boot arguments).

i can work on this and might have something for you to test in a
couple of days.

--
cinap