Re: [9front] pci: add did for the x260's southbridge chipset

Re: [9front] pci: add did for the x260's southbridge chipset

[cinap_lenrek]

look at the following code:

			irq = southbridge->get(sbpci, link);
			if(irq == pci->intl)
				continue;
			if(irq == 0 || (irq & 0x80) != 0){
				irq = pci->intl;
				if(irq == 0 || irq == 0xff)
					continue;
				if(southbridge->set == nil)
					continue;
				southbridge->set(sbpci, link, irq);
			}
			print("pcirouting: %T at pin %d link %.2uX irq %d -> %d\n", tbdf, pin, link, pci->intl, irq);
			pcicfgw8(pci, PciINTL, irq);
			pci->intl = irq;

the prints mean that your pIIxget() returns some garbage which
does not match what the bios programmed in the pci interrupt
line register of the device. as the bios set something sensible
already, we try to reprogram that interrupt ROUTER to match what
the BIOS set up.

none of this matters with any computer that is not a pentium 2
and you want to use it with the legacy PIC interrupt controller
wich has only interrupts 0-15.

you have a multiprocessor system with an apic. the legacy
interrupt line does not matter there. often bios doesnt
even bother setting these up anymore. what matters is the
interrupt *PIN* to which apic it is connected to. that
information is in the MP or ACPI tables. this is fixed.
theres nothing to reprogram there.

and most of this also doesnt matter anymore as modern pci
devices that support message signaled interrupts. which goes
thru the memory subsystem and completely bypasses all that
pci interrupt routing madness.

... back to your interrupt router thing. have you tried
running the system with *nomp=1 mode and your patch?

--
cinap