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* Fixed 6c
@ 2014-05-30 10:40 Aram Hăvărneanu
  2014-06-01  1:28 ` [9front] " sl
  0 siblings, 1 reply; 2+ messages in thread
From: Aram Hăvărneanu @ 2014-05-30 10:40 UTC (permalink / raw)
  To: 9front

I found a bug in 6c while working on arm64 stuff.  So we have this C
code:

    ulong sf, op, Rn, Rd;
    uvlong Xn, m, r;
    ulong Wn, m32;

    /* ... */
    Xn = reg.r[Rn];
    Wn = (ulong)Xn;
//  print("Xn: %llux\n", Xn);
    switch(sf) {
    case 0:    /* 32-bit */
        /* ... */
    case 1:    /* 64-bit */
        switch(op) {
        /* ... */
        case 0:    /* ADD, ADDS */
            r = Xn + m;
            break;
        }
        break;
    }
    reg.r[Rd] = r;

The problem is that reg.r[Rd] gets truncated to 32 bits (actually Xn
starts truncated).  If I add the commented print, everything is fine.
That is because the print it causing registeration to happen
differently, and the bug is not exposed.

The problem is evident in the assembly.

So this is the original assignement:

  addsubimm+0x6d 0x00000000002020bf MOVL SI,Rn+0x68(SP)
  addsubimm+0x71 0x00000000002020c3 MOVQ reg+0x10(SB)(SI*8),SI
  addsubimm+0x79 0x00000000002020cb MOVL SI,CX

So SI is Xn (64-bit) and CX is Wn (32-bit).

Next we have the big switch:

  addsubimm+0x7b 0x00000000002020cd CMPL DI,$0x0
  addsubimm+0x7e 0x00000000002020d0 JEQ addsubimm+0x18a(SB)
  addsubimm+0x84 0x00000000002020d6 CMPL DI,$0x1
  addsubimm+0x87 0x00000000002020d9 JEQ addsubimm+0x12d(SB)

This is our case, which the check for the small switch:

  addsubimm+0x12d 0x000000000020217f CMPL BP,$0x0
  addsubimm+0x130 0x0000000000202182 JEQ addsubimm+0x141(SB)
  addsubimm+0x132 0x0000000000202184 CMPL BP,$0x1
  addsubimm+0x135 0x0000000000202187 JNE addsubimm+0x8d(SB)

op is 0, so it switches to addsubimm+0x141:

  addsubimm+0x141 0x0000000000202193 MOVQ CX,AX
  addsubimm+0x144 0x0000000000202196 ADDQ DX,AX

This is the problem, it should use SI, but it uses CX.

After I fixed it, I talked to Charles and he fixed it independently in
his private 6c copy.  I digged some more and it was fixed by Go as
well.

I committed a fix for our 6c.

-- 
Aram Hăvărneanu


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [9front] Fixed 6c
  2014-05-30 10:40 Fixed 6c Aram Hăvărneanu
@ 2014-06-01  1:28 ` sl
  0 siblings, 0 replies; 2+ messages in thread
From: sl @ 2014-06-01  1:28 UTC (permalink / raw)
  To: 9front

Note:

Build in this order:

6l, 6a, 6c

sl


^ permalink raw reply	[flat|nested] 2+ messages in thread

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