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  • * [COFF] Re: Instruction Density. (Was: Clever code)
           [not found] ` <20221213185109.663zv3usi5ey5jx6@illithid>
           [not found]   ` <>
    @ 2022-12-19  9:48   ` Ralph Corderoy
      2022-12-19 12:10     ` [COFF] Re: Instruction Density Michael Kjörling
      1 sibling, 1 reply; 3+ messages in thread
    From: Ralph Corderoy @ 2022-12-19  9:48 UTC (permalink / raw)
      To: coff
    Branden wrote:
    > the amount of space in the instruction for encoding registers seems to
    > me to have played a major role in the design of the RV32I/E and C
    > (compressed) extension instruction formats of RISC-V.
    Before RISC-V, the need for code density caused ARM to move away from
    the original, highly regular instruction format of one 32-bit word per
    instruction to Thumb and then Thumb-2 encoding.  IIRC, Thumb moved to
    16-bit per instruction which was expanded by Thumb-2 to also have some
    32-bit instructions.  The mobile market was getting going and the
    storage options and their financial and power costs meant code density
    mattered more.
    The original ARM instructions had the top four bits hold the ‘condition
    code’ which decided if the instruction was executed, thus the top hex
    nibble was readable.  
         0                                               f
        eq ne cs cc  mi pl vs vc  hi ls ge lt  gt le al nv
    Data processing instructions, like
        and rd, rn, rm    ; d = n & m
    aligned each of the four-bits to identify which of the sixteen registers
    were used on nibble boundaries so again it was readable as hex.
        xxxx000a aaaSnnnn ddddcccc ctttmmmm
    The ‘a aaa’ above wasn't aligned, but still neatly picked which of the
    sixteen data-processing instructions was used.
        and eor sub rsb  add adc sbc rsc  tst teq cmp cmn  orr mov bic mvn         
    And so it went on.  A SoftWare Interrupt had an aligned 1111 to select
    it and the low twenty-four bits as the interrupt number.
        xxxx1111 yyyyyyyy yyyyyyyy yyyyyyyy
    I assume this neat arrangement helped keep the decoding circuitry small
    leading to a simpler design and lower power consumption.  The latter was
    important because Acorn, the ARM chip's designer, wanted a cheaper
    plastic case rather than ceramic so they set a design limit of 1 W.  Due
    to the poor tooling available, it came in at 0.1 W after allowing for a
    margin of error.  This was so low that Acorn were surprised when an
    early board ran without power connected to the ARM; they found it was
    clocking just from the leakage of the surrounding support chips.
    Also, Acorn's Roger Wilson who designed the ARM's instruction set was an
    expert assembly programmer, e.g. he wrote the 16 KiB BASIC ROM for 6502,
    so he approached it from the programmer's viewpoint as well as the chip
    designer he became.
    Thumb and Thumb-2 naturally had to destroy all this so instructions are
    now not orthogonal.  Having coded swtch() in assembler for various ARM
    Cortex M-..., it's a pain to have to keep checking what instructions are
    available on this model and what registers can it access.  On ARM 2,
    there were few rules to remember and writing assembler was fun.
    Cheers, Ralph.
    ^ permalink raw reply	[flat|nested] 3+ messages in thread

  • end of thread, other threads:[~2022-12-19 12:10 UTC | newest]
    Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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         [not found] ` <20221213185109.663zv3usi5ey5jx6@illithid>
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    2022-12-13 20:58     ` [COFF] Re: Clever code Warren Toomey via COFF
    2022-12-19  9:48   ` [COFF] Re: Instruction Density. (Was: Clever code) Ralph Corderoy
    2022-12-19 12:10     ` [COFF] Re: Instruction Density Michael Kjörling

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