Re: [COFF] Encoding an ISA: Random Logic vs. Control Stores

[Bakul Shah <bakul@iitbombay.org>]

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On Nov 30, 2021, at 8:49 AM, Clem Cole <clemc@ccc.com> wrote:
> 
> Also remember that Gordan and the CMU types of those days were beginning to create what we now call Hardware Description Languages (HDL).  Gordon describes in "Bell and Newell" (the definitive Computer Structures book of the 1970s) his Processor-Memory-Switch (PMS) diagrams.   The original 11 (which would become the 11/20) was first described as a set of PMS diagrams.   PMS of course, beget the Instruction Set Processor Language (ISPL) that Mario created a couple of years later.   While ISPL was after the 11 had been designed, ISPL could synthesize a system using PDP-16 RTM modules.  A later version from our old friend from UNIX land, Ted Kowalski [his PhD thesis actually], that could spit out TTL from the later ISPS simulator and compiler [the S being simulation].   ISPS would beget VHDL, which beget today Verilog/System Verilog.

Verilog has no direct connection with VHDL. Phil Moorby had been working with HILO simulators since 1976 so had considerable experience with simulators and based on that experience he designed Verilog as a fast gate & switch level simulator, as well as for synthesis.
See https://community.cadence.com/cadence_blogs_8/b/ii/posts/q-amp-a-phil-moorby-hdl-pioneer-and-cadence-fellow-from-verilog-to-parallel-programming and https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/phil-moorby

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