From: Damian McGuckin <damianm@esi.com.au>
To: musl@lists.openwall.com
Subject: [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10
Date: Sat, 21 Oct 2023 11:02:27 +1100 (AEDT) [thread overview]
Message-ID: <1de79c9a-b970-5285-3a90-a3d5a8df90e9@esi.com.au> (raw)
What modern CPUs have a penalty for double precision floating point
arithmetic on scalars compared to single precision once they are in a
register, i.e. ignoring memory fetch issues.
I have Agner Fog's excellent document for X86-64 which basically says that 32
bit and 64 bit operations for scalars take the same amount of time.
I am looking for the same type of information for ARM and RISC-V. I found the
data for 32-bit in the online documentation. But nothing bout 64 bit.
I cannot find anything on this topic on RISC-V or POWER10.
Maybe I am not searching on the right terms.
Note that I am after the raw performance, not say the relative performance
of say the MUSL sin() routine compared with the MUSL sinf().
Thanks - Damian
next reply other threads:[~2023-10-21 0:02 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-21 0:02 Damian McGuckin [this message]
2023-10-21 0:35 ` David Edelsohn
2023-10-21 1:06 ` Damian McGuckin
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