From: Damian McGuckin <damianm@esi.com.au>
To: musl@lists.openwall.com
Subject: Re: [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10
Date: Sat, 21 Oct 2023 12:06:15 +1100 (AEDT) [thread overview]
Message-ID: <4559c029-6f1f-dd1c-3fb4-ae5b5c21eb31@esi.com.au> (raw)
In-Reply-To: <CAGWvnymR+YNY+C6VLjT588qEG9UkLENu+PR9YY+EZammfr9=pQ@mail.gmail.com>
On Fri, 20 Oct 2023, David Edelsohn wrote:
> Have you looked at the scheduler description for ARM, RISC-V and POWER in
> GCC or LLVM?
No.
Thanks for the pointer - Damian
prev parent reply other threads:[~2023-10-21 1:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-21 0:02 Damian McGuckin
2023-10-21 0:35 ` David Edelsohn
2023-10-21 1:06 ` Damian McGuckin [this message]
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