* [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10
@ 2023-10-21 0:02 Damian McGuckin
2023-10-21 0:35 ` David Edelsohn
0 siblings, 1 reply; 3+ messages in thread
From: Damian McGuckin @ 2023-10-21 0:02 UTC (permalink / raw)
To: musl
What modern CPUs have a penalty for double precision floating point
arithmetic on scalars compared to single precision once they are in a
register, i.e. ignoring memory fetch issues.
I have Agner Fog's excellent document for X86-64 which basically says that 32
bit and 64 bit operations for scalars take the same amount of time.
I am looking for the same type of information for ARM and RISC-V. I found the
data for 32-bit in the online documentation. But nothing bout 64 bit.
I cannot find anything on this topic on RISC-V or POWER10.
Maybe I am not searching on the right terms.
Note that I am after the raw performance, not say the relative performance
of say the MUSL sin() routine compared with the MUSL sinf().
Thanks - Damian
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10
2023-10-21 0:02 [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10 Damian McGuckin
@ 2023-10-21 0:35 ` David Edelsohn
2023-10-21 1:06 ` Damian McGuckin
0 siblings, 1 reply; 3+ messages in thread
From: David Edelsohn @ 2023-10-21 0:35 UTC (permalink / raw)
To: musl
[-- Attachment #1: Type: text/plain, Size: 958 bytes --]
On Fri, Oct 20, 2023 at 8:02 PM Damian McGuckin <damianm@esi.com.au> wrote:
>
> What modern CPUs have a penalty for double precision floating point
> arithmetic on scalars compared to single precision once they are in a
> register, i.e. ignoring memory fetch issues.
>
> I have Agner Fog's excellent document for X86-64 which basically says that
> 32
> bit and 64 bit operations for scalars take the same amount of time.
>
> I am looking for the same type of information for ARM and RISC-V. I found
> the
> data for 32-bit in the online documentation. But nothing bout 64 bit.
>
> I cannot find anything on this topic on RISC-V or POWER10.
>
> Maybe I am not searching on the right terms.
>
> Note that I am after the raw performance, not say the relative performance
> of say the MUSL sin() routine compared with the MUSL sinf().
>
Have you looked at the scheduler description for ARM, RISC-V and POWER in
GCC or LLVM?
David
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10
2023-10-21 0:35 ` David Edelsohn
@ 2023-10-21 1:06 ` Damian McGuckin
0 siblings, 0 replies; 3+ messages in thread
From: Damian McGuckin @ 2023-10-21 1:06 UTC (permalink / raw)
To: musl
On Fri, 20 Oct 2023, David Edelsohn wrote:
> Have you looked at the scheduler description for ARM, RISC-V and POWER in
> GCC or LLVM?
No.
Thanks for the pointer - Damian
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-10-21 1:06 UTC | newest]
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2023-10-21 0:02 [musl] Floating Point Operations Cycles/Latency for ARM + RISC-V + POWER10 Damian McGuckin
2023-10-21 0:35 ` David Edelsohn
2023-10-21 1:06 ` Damian McGuckin
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