[PATCH] mips: fix setjmp/longjmp for O32 FP64 ABI

[PATCH] mips: fix setjmp/longjmp for O32 FP64 ABI

[info]

Save/restore six double-precision callee-saved registers as described in sections 9 and 12.1 at [1].

This intentionally touches only the O32 FP64 case (-mfp64 -modd-spreg) and changes nothing for FP32 (-mfp32), FPXX (-mfpxx) or FP64A (-mfp64 -mno-odd-spreg).

The s.d/l.d instruction aliases are not used because
- they are not implemented in llvm/clang before 4.0 at all;
- they do not expand to swc1/lwc1 pairs for e.g. -mips1 with llvm/clang 5.0.1 at least.

[1] https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking
---
 src/setjmp/mips/longjmp.S | 9 +++++++++
 src/setjmp/mips/setjmp.S  | 9 +++++++++
 2 files changed, 18 insertions(+)

diff --git a/src/setjmp/mips/longjmp.S b/src/setjmp/mips/longjmp.S
index fdb6c95d..21f1df99 100644
--- a/src/setjmp/mips/longjmp.S
+++ b/src/setjmp/mips/longjmp.S
@@ -12,6 +12,14 @@ longjmp:
 	addu    $2, $2, 1
 1:
 #ifndef __mips_soft_float
+#if __mips_fpr == 64
+	ldc1	$20, 56($4)
+	ldc1	$22, 64($4)
+	ldc1	$24, 72($4)
+	ldc1	$26, 80($4)
+	ldc1	$28, 88($4)
+	ldc1	$30, 96($4)
+#else
 	lwc1    $20, 56($4)
 	lwc1    $21, 60($4)
 	lwc1    $22, 64($4)
@@ -24,6 +32,7 @@ longjmp:
 	lwc1    $29, 92($4)
 	lwc1    $30, 96($4)
 	lwc1    $31, 100($4)
+#endif
 #endif
 	lw      $ra,  0($4)
 	lw      $sp,  4($4)
diff --git a/src/setjmp/mips/setjmp.S b/src/setjmp/mips/setjmp.S
index 501d5264..54a6d71c 100644
--- a/src/setjmp/mips/setjmp.S
+++ b/src/setjmp/mips/setjmp.S
@@ -22,6 +22,14 @@ setjmp:
 	sw      $30, 40($4)
 	sw      $28, 44($4)
 #ifndef __mips_soft_float
+#if __mips_fpr == 64
+	sdc1	$20, 56($4)
+	sdc1	$22, 64($4)
+	sdc1	$24, 72($4)
+	sdc1	$26, 80($4)
+	sdc1	$28, 88($4)
+	sdc1	$30, 96($4)
+#else
 	swc1    $20, 56($4)
 	swc1    $21, 60($4)
 	swc1    $22, 64($4)
@@ -34,6 +42,7 @@ setjmp:
 	swc1    $29, 92($4)
 	swc1    $30, 96($4)
 	swc1    $31, 100($4)
+#endif
 #endif
 	jr      $ra
 	li      $2, 0
-- 
2.17.2 (Apple Git-113)

Re: [PATCH] mips: fix setjmp/longjmp for O32 FP64 ABI

[Rich Felker]

On Wed, Nov 14, 2018 at 01:37:16PM +0300, info@mobile-stream.com wrote:
> Save/restore six double-precision callee-saved registers as
> described in sections 9 and 12.1 at [1].
> 
> This intentionally touches only the O32 FP64 case (-mfp64
> -modd-spreg) and changes nothing for FP32 (-mfp32), FPXX (-mfpxx) or
> FP64A (-mfp64 -mno-odd-spreg).
> 
> The s.d/l.d instruction aliases are not used because
> - they are not implemented in llvm/clang before 4.0 at all;
> - they do not expand to swc1/lwc1 pairs for e.g. -mips1 with llvm/clang 5.0.1 at least.
> 
> [1] https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking

This patch needs more explanation for consideration. I could probably
figure it out from the above link but that's a lot of reading, and a
TL;DR would be really helpful here. If the patch to solve an existing
problem with some supported ABI or is it adding a new ABI? If the
latter, is it mutually compatible for the purposes of calling/linkage?
New ABIs can't just be added without both a name and a justification.

Rich