From: 张飞 <zhangfei@nj.iscas.ac.cn>
To: musl <musl@lists.openwall.com>
Subject: [musl] memset_riscv64
Date: Tue, 11 Apr 2023 10:17:39 +0800 (GMT+08:00) [thread overview]
Message-ID: <7ab4e713.9fae.1876e1ac122.Coremail.zhangfei@nj.iscas.ac.cn> (raw)
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Hello,
Currently, there is no assembly implementation of the memset function for riscv64 in Musl.
This patch is a riscv64 assembly implementation of the memset function, which is implemented using the basic instruction set and
has better performance than the c language implementation in Musl. I hope it can be integrated into Musl.
Please review it and look forward to your reply.
Fei Zhang
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diff -uprN src/string/riscv64/memset.S src/string/riscv64/memset.S
--- src/string/riscv64/memset.S 1970-01-01 08:00:00.000000000 +0800
+++ src/string/riscv64/memset.S 2023-04-11 09:43:05.733274437 +0800
@@ -0,0 +1,95 @@
+.global memset
+.type memset,@function
+
+#define SZREG 8
+#define REG_S sd
+
+memset:
+ mv t0, a0
+
+ sltiu a3, a2, 16
+ bnez a3, 4f
+
+ addi a3, t0, SZREG-1
+ andi a3, a3, ~(SZREG-1)
+ beq a3, t0, 2f
+ sub a4, a3, t0
+
+1:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 1b
+ sub a2, a2, a4
+
+2:
+ andi a1, a1, 0xff
+ slli a3, a1, 8
+ or a1, a3, a1
+ slli a3, a1, 16
+ or a1, a3, a1
+ slli a3, a1, 32
+ or a1, a3, a1
+
+ andi a4, a2, ~(SZREG-1)
+ add a3, t0, a4
+
+ andi a4, a4, 31*SZREG
+ beqz a4, 3f
+ neg a4, a4
+ addi a4, a4, 32*SZREG
+
+ sub t0, t0, a4
+
+ la a5, 3f
+ srli a4, a4, 1
+ add a5, a5, a4
+ jr a5
+
+3:
+ REG_S a1, 0(t0)
+ REG_S a1, SZREG(t0)
+ REG_S a1, 2*SZREG(t0)
+ REG_S a1, 3*SZREG(t0)
+ REG_S a1, 4*SZREG(t0)
+ REG_S a1, 5*SZREG(t0)
+ REG_S a1, 6*SZREG(t0)
+ REG_S a1, 7*SZREG(t0)
+ REG_S a1, 8*SZREG(t0)
+ REG_S a1, 9*SZREG(t0)
+ REG_S a1, 10*SZREG(t0)
+ REG_S a1, 11*SZREG(t0)
+ REG_S a1, 12*SZREG(t0)
+ REG_S a1, 13*SZREG(t0)
+ REG_S a1, 14*SZREG(t0)
+ REG_S a1, 15*SZREG(t0)
+ REG_S a1, 16*SZREG(t0)
+ REG_S a1, 17*SZREG(t0)
+ REG_S a1, 18*SZREG(t0)
+ REG_S a1, 19*SZREG(t0)
+ REG_S a1, 20*SZREG(t0)
+ REG_S a1, 21*SZREG(t0)
+ REG_S a1, 22*SZREG(t0)
+ REG_S a1, 23*SZREG(t0)
+ REG_S a1, 24*SZREG(t0)
+ REG_S a1, 25*SZREG(t0)
+ REG_S a1, 26*SZREG(t0)
+ REG_S a1, 27*SZREG(t0)
+ REG_S a1, 28*SZREG(t0)
+ REG_S a1, 29*SZREG(t0)
+ REG_S a1, 30*SZREG(t0)
+ REG_S a1, 31*SZREG(t0)
+ addi t0, t0, 32*SZREG
+ bltu t0, a3, 3b
+ andi a2, a2, SZREG-1
+
+4:
+ beqz a2, 6f
+ add a3, t0, a2
+
+5:
+ sb a1, 0(t0)
+ addi t0, t0, 1
+ bltu t0, a3, 5b
+
+6:
+ ret
next reply other threads:[~2023-04-11 2:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-11 2:17 张飞 [this message]
2023-04-11 9:48 ` Pedro Falcato
2023-04-19 5:33 ` 张飞
2023-04-19 9:02 ` Szabolcs Nagy
2023-04-20 8:17 ` 张飞
2023-04-21 13:30 ` Szabolcs Nagy
2023-04-21 14:50 ` Pedro Falcato
2023-04-21 16:54 ` Rich Felker
2023-04-21 17:01 ` enh
2023-04-26 7:25 ` 张飞
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