From: jnc@mercury.lcs.mit.edu (Noel Chiappa)
To: tuhs@minnie.tuhs.org
Cc: jnc@mercury.lcs.mit.edu
Subject: Re: [TUHS] System III on 11/34 + rl02
Date: Wed, 24 Oct 2018 07:23:49 -0400 (EDT) [thread overview]
Message-ID: <20181024112349.E94EB18C0AB@mercury.lcs.mit.edu> (raw)
> From: Jacob Ritorto <jacob.ritorto@gmail.com>
> System III only supports rl01, not rl02
Really? That seems odd; SysII long post-dates (I think) the RL0x, if so it's
odd they only supported the RL01. Looking at:
https://minnie.tuhs.org//cgi-bin/utree.pl?file=SysIII/usr/src/uts/pdp11/io/rl.c
it seems to support RL02's:
#define RL02 0200 /* bit 7 indicates an rl02 present if set */
> Would anyone know if it's trivial to modify the source for the rl01
> driver to just add double the blocks
The only difference between the two is that the RL02 has twice as many
cylinders, so there's an extra bit in use on the high end of the 'disk
address' register.
> From: Clem cole <clemc@ccc.com>
> Also if you have a 40 class system like the 34 of 34A see if you can
> find an Able Enable board.
I'm sure there are a stack of them stored away with Jimmy Hoffa's body and the
Ark of the Covenant in King Solomon's Mine! :-)
Seriously, if anyone has one, I'd pay a very substantial sum for it.
Noel
next reply other threads:[~2018-10-24 11:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-24 11:23 Noel Chiappa [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-10-25 10:56 Noel Chiappa
2018-10-26 3:27 ` Jacob Ritorto
2018-10-24 2:59 Jacob Ritorto
2018-10-24 3:21 ` Clem cole
2018-10-25 1:22 ` Jacob Ritorto
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