* Re: [PR PATCH] [Updated] firefox-esr: update to 91.12.0
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
@ 2022-08-21 22:07 ` oreo639
2022-08-22 2:22 ` oreo639
` (12 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-08-21 22:07 UTC (permalink / raw)
To: ml
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There is an updated pull request by oreo639 against master on the void-packages repository
https://github.com/oreo639/void-packages ffesr
https://github.com/void-linux/void-packages/pull/38817
firefox-esr: update to 91.12.0
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with gcc 12 and fixes build with the current cbindgen in the repos.
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
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#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
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A patch file from https://github.com/void-linux/void-packages/pull/38817.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-ffesr-38817.patch --]
[-- Type: text/x-diff, Size: 15992 bytes --]
From bf740947ffd1d3e716bf151e9e83181fa7e10baf Mon Sep 17 00:00:00 2001
From: oreo639 <31916379+Oreo639@users.noreply.github.com>
Date: Sun, 21 Aug 2022 15:03:40 -0700
Subject: [PATCH 1/2] firefox-esr: update to 91.12.0
---
.../firefox-esr/patches/fix-cbindgen.patch | 22 +++++++++++++++++++
srcpkgs/firefox-esr/template | 4 ++--
2 files changed, 24 insertions(+), 2 deletions(-)
create mode 100644 srcpkgs/firefox-esr/patches/fix-cbindgen.patch
diff --git a/srcpkgs/firefox-esr/patches/fix-cbindgen.patch b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
new file mode 100644
index 000000000000..ba3ce7ae3e97
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
@@ -0,0 +1,22 @@
+Fix error with new cbindgen:
+
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi_generated.h:24:33: error: redefinition of 'constexpr const uint64_t mozilla::wr::ROOT_CLIP_CHAIN'
+ 24 | constexpr static const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi.h:76:16: note: 'const uint64_t mozilla::wr::ROOT_CLIP_CHAIN' previously defined here
+ 76 | const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+
+diff --git a/gfx/webrender_bindings/webrender_ffi.h b/gfx/webrender_bindings/webrender_ffi.h
+index b1d67b17a4bde..eb79974bdf434 100644
+--- a/gfx/webrender_bindings/webrender_ffi.h
++++ b/gfx/webrender_bindings/webrender_ffi.h
+@@ -73,8 +73,6 @@ struct WrPipelineInfo;
+ struct WrPipelineIdAndEpoch;
+ using WrPipelineIdEpochs = nsTArray<WrPipelineIdAndEpoch>;
+
+-const uint64_t ROOT_CLIP_CHAIN = ~0;
+-
+ } // namespace wr
+ } // namespace mozilla
+
diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template
index 58c065649bc4..373044d880c8 100644
--- a/srcpkgs/firefox-esr/template
+++ b/srcpkgs/firefox-esr/template
@@ -3,7 +3,7 @@
# THIS PKG MUST BE SYNCHRONIZED WITH "srcpkgs/firefox-esr-i18n".
#
pkgname=firefox-esr
-version=91.10.0
+version=91.12.0
revision=1
wrksrc="firefox-${version}"
build_helper="rust"
@@ -13,7 +13,7 @@ license="MPL-2.0, GPL-2.0-or-later, LGPL-2.1-or-later"
homepage="https://www.mozilla.org/firefox/"
distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz
https://github.com/chmeeedalf/gecko-dev/files/7729086/esrppcjit.tar.gz"
-checksum="825a8cb38bb5da9821ef87cc6de64af007cf0faef07c4ed0651283b56a0ee1bb
+checksum="6c0b8ff1826885eeace19ec87ae9e5a6512284d4863930713c8a288a03832b5c
5e926a8be5d6d4949c3bc3eb98e2103692eaa26a98928db432b1d44b535f7241"
lib32disabled=yes
From bb9818a5548e14bab3222bd2fbef28723183469b Mon Sep 17 00:00:00 2001
From: oreo639 <31916379+Oreo639@users.noreply.github.com>
Date: Sun, 21 Aug 2022 15:04:04 -0700
Subject: [PATCH 2/2] firefox-esr-i18n: update to 91.12.0
---
srcpkgs/firefox-esr-i18n/template | 188 +++++++++++++++---------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/srcpkgs/firefox-esr-i18n/template b/srcpkgs/firefox-esr-i18n/template
index 765303a93236..dc5870558bde 100644
--- a/srcpkgs/firefox-esr-i18n/template
+++ b/srcpkgs/firefox-esr-i18n/template
@@ -1,6 +1,6 @@
# Template file for 'firefox-esr-i18n'
pkgname=firefox-esr-i18n
-version=91.10.0
+version=91.12.0
revision=1
build_style=meta
short_desc="Firefox ESR language packs"
@@ -135,96 +135,96 @@ _pkgtmpl() {
}
}
-checksum="6b47684de4218749d90a07b858ca298b034a2cda10655941e8ba47891d0d95ed
- 54852ef937387cba360fb2bed348c9bc3f1153f7242ad5491ca0b85ee6ed7455
- de66e0263dd0a2d87554fa1d9a406dee5cb3df1a774dffb8636e1be2bd80bc14
- 1f4824ad51a662285ac3a0d8029462a3bf12b36eb0834e65b9276e0869115c09
- a16fc6e0a1bf251ab19b7bbfb620b53437e5bf71b0e7871ed40ace8c97dbf635
- d9057bc71605f2a93d924beb37497195b8ad83501aa4d211ad71106e7b9bce4a
- 36316a7c4ca844ac3e81b2a0bb9ee4952017c2d2404f529848e280d04a21589b
- 150bafd02393355567d75bb9f966900e70502fdddff2822cbbd3bbc1fb3fd785
- 5b69e761666b28e5604d4cf8abc72acf3c3d79abeb7b6230e56aaae775ec225b
- b005c63d5e0d933ef1a4193b75a291a61524a939c3465d41ed111416210eb97f
- d5a2d2fafbfc50e23f5b68d30fcd7376d127f9f697c872d0d7c8e19ee4538cb1
- 16f88ec5de39f982057abcf34f17b22c698453debb62a5a18e0475798fc1cca9
- 84d491f73bc53da4605ee45a8633f14ee5672b9a61c40689d5e3289744a7cb2d
- 7781b6c29923360fd3a95bd2b2532eba7f92bed29640e0276c161eadbe56a13f
- 7984904ede35def33ccf73fda9aa46777c673c4d27de3806873d17694f7f0b13
- 4c57b6eb1cd968ba1eb4b427bed66bab04fb42424d03ae4b892fd3648e255b2e
- a80e9e2a6062bf68106ba1d1b8b7e2ff608ce52fa55d43558e7c073ec1872516
- 2b040ff1d010508760cb4ce4b76cce9e98b4620203c1ef77f87a336ced0aefc7
- 1fa4f5e59a9352f14aefe0cff8e8c4eed4eba16f4d8dbcec6850bce035301c18
- 2da0b09b9bf80f66edc6e3e9d5c1b75fae12905b5193cc64a73bb8bd7bfcbb04
- dce96c9fccb8c857f8cc370f7f5635b1475138195b05e944782b072beebc8d44
- e90dbf86c1823c209def11052995834ed15528dc5c6d3b502ed315dd471a9d5b
- f38624c81f2f9dac4f05b9e9d4d6e7a4e0381a279e3b4c53811aeb1db13cd000
- 221b7f4031a7c120d0ca753d93c41c18ac4f9500ae424c7983e4593497ddbbf8
- 60f5ceb21287a6786a6dd2d177325dfbcc6ca7f9a5df1b9299a2c5bb01d9c172
- 308ce25a9a0a9038dd94c2c22889c54def3937d35eafbcb34b75026cf3de3b8f
- 2d332a6f5bd92017700a15da5fe506612cea03b49f903592fc105fca978cd1d3
- 5cd35666f54a5ae4e35a1ca4c627cec8a47594da4083adf4f06dbe31c20a7444
- 1c1252765cb24f6a0206b648d834566aca9229075f7413f9c7deff1949a99c37
- 002772c46d6a7162e2add4726f105e4c0e355bbb84ce91b07ab02967cc5f1eb4
- 64ce2c0735caf9b67d2be003b1d667bce5ff614653151c617e4d26e349033e3a
- 60bd5f2532700ae9139d4d59a571b72b2806e80630fddb5f4444c7d6e377d2dc
- 2753317b7580ee1a377275905e254084263d0a87bda1bb572537fa75489d92dc
- 7f1b74d2cc5a9c4c6c7864a62eadef2b3d72c5cc2010f5c03bce3a9fae2286dc
- 2232c3b9a8f313145967152bf1dbafd6233593ceb422d2c3277d1b4cfecb6f50
- c41e866f3fc3cf0e0088681b55bb8489de1c5840ca7dc52d1f4f077b53452bd5
- 5d787fd6a9aa06ce31a6823b3393ba7ad66cf3d374dd6eaab3648103e826a10b
- 8d73e01655af7117856374be3669d530af96a79cdb8238bc953688d45e94567c
- 03f2b133746746c328cb7e4055b568d8e99cea51c845136c3f4446840d68e32f
- 691b0e760ebe5269dfa4aa4ea8dd2139260fbb0ca38af4c5438548b7c7ee88f5
- c63492236e75bf984a1671de95dddc954c1b4a1e92f5201c9b333faefae93035
- df9a036c67aecb1ea65f9709a11f6ccdf253451dcbe6b267437c51f422b9df2d
- 32ec78a51439b02f087c12c6be4a9159826113e83774085e800c37b6d7c112aa
- 1e44e3ded5aa07d44f3fdea8cf68bb33fd243cda159384ea8b87e783ed5c9a65
- 1cac44cdec68b56b77aba139a8425f607bac34ae2e09e27ecff2522b16fef44d
- aefb4fbacbdfc749a8d5888f7af48999406f207850fafae8ef39c083e08fa80c
- 753dbcffdf54ce3787a939517b059f11c305edc035bc22f8a9efed6145af6391
- 6c3be5abaf3878390b074970132c4cba935f7160f365cfa98a07e6b882084bdd
- 0b7771965f34c890dea0d2290a283212a1cdc0c8c8044ec634622d52eb595df9
- 0910f98a89b712a40aeb42761f25c763818af05edb5c96e2b6cfba023c28ab73
- 758ab6ea150702ee0d6203a0f75e8baa595c4a0f3d4cb9b87076f732a0e4546f
- d4259375f321b98426885e0b903199dce1f988c74963297bbd1a2aa8f94b0544
- 1614e1288f6d6ce43a7343586141df5e121cff7f1fd703ab4ec40a7f07498843
- 3ae5219a384a872fdbdd8ca5d99ad5370e0d8d87d93f5e39e96c5a2dc26736e3
- 05807b1c17849ffd2a3a63b1e26815dc9463aa3c137f640113530d2662d64116
- e4f3cfb11dfac8ec4caf29f34e20a0c0bb799649fd5b534f22f202c237491f7f
- 80b2b6446590a9fc55ed80a9e07b657cafc5d50294988974747c0e60d41f569b
- 1b32bc1282ded7f6f0f0979cbce3496ed07b1fcad64e70bbbc2eb5d2a8f3953b
- 0f80e3b0a9e17f39560b7cad8280e25c0278935f125d8e724a2381102abff783
- f259ee2683e525051d6f314d4bae4a98c0482a2a443aaac1160b2e0c1326b931
- b9a9eab4c5ea110ccbce20cb88e6652e2cf4c28bfd0aa95907148befd198544d
- a5a6e9bdaad420f281ce5fd16dabf5338d48c7cd8518c38b1e101b79b530fdb9
- a1fe6a2c7606b0720933496cad2bc959693905db87c3a2e5313db82dbfebda7c
- d1b22a495c637d5652c84afe8650d876b4206f2ea0d96751bec684ea63327f98
- e1587dac082479821697d97b4d5cb63a8d1f9189fdc2048885d963aea95b8400
- 6e40a5d5f0cb8794edc5f6a1fae778d89f6dbd97d8a288236d72fa571ffe91c9
- 33b5df625ae13ec35b41bb350e9e66d9ccc04f4d4d8c7e45020344739881e6d8
- e2f271691bb1b9873583175ff303bbaaf05a9d1207fbe8fffc34ec4abcfc1545
- 13382dabc604e99553c98b9e41eb046d4688b15f2ee9dd12c4f9c8967afa62d1
- 77133c69968073fec909dbe9e44d2eaea002cb0d0e142125865d1c03c89ed73d
- f8998128b0c656e72124baeff45c72013953f8314aa4959b6fef8a1b3039647f
- 2f24e5db025c0302fe3b696f280dcbab83728aaccaefe1ff082e165276896296
- d658095fd2d3e4d3decb8c2cdaa64f02fd8b663ba711fb9f2130ed7ed2a97291
- 7c28a82ecdd622653b26a9dd0913ac7d7cebe7246f64874fea2d1fa4af354c2a
- f78694d438032af3ca1a265a089407eb12b431bd314177672a66338b9bf7390f
- ea2d769b90a06400eba3e1f4eec58342fe4450ecce38b1e721923a65bed34337
- 8edf5b04b6cb477f482c14efdbada7023ff7a0ef584a4c30b2350e7825a612a0
- 851db60a218c36b61ee0adfcdc478bc051c95e41a4dba54d43594b8f03c6b187
- 6af72cae7f72ce68c644d49b6a621945f5e8f79119a86bb67ee144585f734925
- 7b01771078ec475b0103fcc4222b0b40eb92ec64180aaad02f2846cfdfb3e319
- 0c4df78eafbbe7ff98d9eff03bb258d1d0f4591102147f643ec395711f35d940
- cf21434f24e221ce58184f43a582c10187eceb7a71da5d81156cc870d78c1f4c
- 839088e2f23f6c62c38c45d5f7012513d95034aa5e6ab28307f152dbc10f97d3
- 4058ae6dd7b556bae2c13bb6fa0c5f16207c6fef4e0802d3d0badae2108a0da8
- d2c473fb93f0c4dc67ae18c25fdc414056bf779038c0f5dd25aa63a9a5cfcd0a
- 6e31c79b9955fd879528b0a614295da69ab26b608275946a4a5a29178a2aed20
- 852fe9ab16d29f7cf8f443bfd65fa1d522a9f27ef8766ad72a0c22a65450dc18
- 9411873b1ea01a1b8656957aedb79137f4c189b9cd3e96626c8e503539cf2c4b
- 5f43106472ae66dc8c0ffc317faba09c2370d4f18837c3cfaf05eb9b03f33b90
- 30f3f50133532ce379b9d5dd0f7e81204905e8a43a27e9d2ac1a26059e393913
- 285f615cc8852fd74bd7693a5a45b106f293c0a2d89836e9f25336ac6376af69
- 190ac7991a8b501fab2654d23b5f6f1e7a5f0cfeb402c8f5fe382d25c2222dc6
- 2de7676c71508ffbb337bdd8ca68f9d2fa1e30f23e8be283b937c5c4e30c59d6"
+checksum="fedea0f565a107674568bb867f1126b201f94155da4f33a4ba06372d6305fdaf
+ 3d6672cb7171258cd473778c7ca8835cac92c8f3d88fcb283cf6fb00ca2238b8
+ 3484191507d55a2ca0531b5bb942d2f1e1a0cb8b6d78f56fba09d85aaad8fb40
+ c4e40e3484e47dd87610413e1d77bf5569bf071b9631021259125465fe46875c
+ 1b92a2c12d2b8f0daf65568d4a06b52ee002028b611d4da8f586f129fd7bcf3c
+ 28789864690cd697f7028f7ea4f1c5e39115452effd98cd6ce011dbada9984a3
+ 6463f156654d607357edce6705981dc9cc1367a70acc41765e968b51e1112fe5
+ c6a0a57b1aa808c31802550856447f7fb251787ba4aecf6c3fe2b6db43e2357c
+ 76742b7c64d3c45765dfdff064f939dc5f648613b5b9cbae82827b747a8a763f
+ 564387ab8d6f7c0a203f90f888966aa85e89457a7c5f0991af9dfa908639f23a
+ 204a895f822a5bb3063037f42bd66c80ad06abdbcede62a5b0893f96d0e095e9
+ e0e83a93e497d8d15f4a4b6231b02a7286c578ca052ccda5f8329891bfbfad11
+ 2227844dca574b6e4d83b0a7c4d2015a596b55df8b1129be515161ca7a01af34
+ fd3d50ac9a46e56b954a8843ac45cff24af5e7b1e3c6b3a68f73092e05a5c3c5
+ 216f994f4cb5a9ed20f91fa4a2a485d1b677e31bb22c57d398c8a31653ea8dda
+ d5a3e92d9d78029286ab7a33766aa49ea439dd10e392481e3690560cb70445b2
+ 24533b096d4e86892e10f557b097cbde3666088f4087b6a07fcc6b14175677f0
+ 3de6d5c821f560e9bf8c1500d8285ee7de1f88bf1d8a7e8ee7d5569e4124f784
+ 578305cd0de9712e67dba9431c4dba9ea3a8f0bd5aa7b75ceee5b1d2590f59c0
+ f1437c43271230b7eadad262250656a445b95adbd2ce7ab6be78b2a577bea73d
+ 704668a2a6505700f13de47db3543552068cbdfe4f1f3a1d6fb11cb412d119d1
+ 215bec4c8b1f7438b1e8a6b89a44fcb6c70bccea5e8ff3534106686bc4073c68
+ aafcc3057b04b40b6cdf63fb17c8bb61b0bcc20afd5de66bef9f59cf36b8d5f3
+ c66de6da2ee4484ad3a98079efe8a4b3b97442dbe17f40ac39e342c52d20e7c0
+ 1b330a9b974fef1a3ce6870823fbca77fbaa3d83ed1868e9ba7d99f28c1750cd
+ 1cdd1fc81f8776ae1c0e5ad9d00e18cddb9902aee4825dfeb95240af6ba5897a
+ d65a443b90cb00a06df7196306667ba4293381260e0e610f34c1a10af8d2f02b
+ 37836f01c31a5fab00b21fef8a96f88977ae25543e7ab41ac2cfc8bb0fd81b8a
+ 86a5b99f28476b027e07029a3ed60487af0ae1890d6f90b8b6e7ead56698b306
+ 6a3c26d9b256a621e4289eae3fa0ecdaf8326ab4f90e84e189426dfee3fa0458
+ 9fe29366f3f252826a3abe749a802aa2164e5273d5a35521b2dbdff4017d2ba5
+ 635e3eaea0f94f5faa11bff02590dbc4563850af14d4f18aa134dea8f29c6899
+ 8c42dac92f9cf2bf15190080921a78917cb8a3f7c7df5ecabef0dce81c6c6dd4
+ 5e91979792c5fdd00b43692c69c6954de0e15dd4e1331050388dd4acf7c3870d
+ ce77d5238666f8be72f145edabb99d9155dd3ee592a2d00aeb4b96334432884e
+ 01fe38f57d5990ff4586f2539bf7f7b7d2a6d94306639d0237c9f8f01f982730
+ c6327f44a2d340d5c8ffe6f77ccfa813821a3302acf1999c083fb222eedfcb8a
+ e4f330f7b36f58ca23eff6b2ed99aba56b5b7b789a8f16ecf7825746ba0d388b
+ 81c701ef1b0592c593a30ff563ad30f7f3fa036e04889b7ff6eee5685879af57
+ 228310913898bd013f9c015ca47d415b653c323732fb87b918f5337488415e2b
+ 65a93f13bd35acf44da9cc12dd181d3778c598c83ee1c0aed77bc483004af364
+ 3b6aef851b9c761f7f8f0088cb568df361a835ba8d2b9c3897576f42c10692cd
+ ae3f507319906232ba5b0cfa7632288dcae161ef8278e4f44376070b146c2757
+ cca38399f8eecf3248fe1532f8659ee4bdf01876a271f16fe01ad892f8be405f
+ 6b925b174472e9a47a0be8e804a2647ede63bde9dc797d11b62752936f157cc1
+ f758adf61a8ecffb7997b2a22e523dbc76198139f0fbd67e83f81332a6cce4a8
+ 240071f9f5e8a4b56e2e43a654c5be9e26ac26a6fd7cfb8d595b1521a06426d8
+ 8bb8f990c045739506da2b445821ded94911e8459596f10c30488d4ff1a9476e
+ 6305fcb0b1fa9cd3d27c902d312549f5cbb911deff8fef4b6b0772563cab158e
+ 9b1d954852a8fd94b8946b80bb4fb387c13eeee0f54d62b8dda4d0dd1d03f40c
+ 6fd3f345dff25c7a3b2e83fdaf8bb4446b46755fad7ffdedeaa0800f5ac710a6
+ 85932c366b61b3d4a53437bddef66759d478da70e0b9ddaa2a39dbbdcebf6625
+ db70798770e4b31f4b31707f04919597e0109f51ea57f9013949ad05776d7df2
+ bb4319a3c1f2956fe1c7884cb87a2161798c009449d6c83d628584b98cc44b4d
+ fbecc5ad940ab62d2ffb0445ec91c4abd45f25f77298b8cc0a38c37ddd132184
+ 5b1fdb3709b8621953386f4229860978c55841e528f266368fcfb65ad2029f12
+ 52f0d6c5d9065e0a32bc4b7680cfb1755e75774cc97e505d15933ca0f8bed34a
+ b318939a52244c06e6ce578b6e0d8cc13345b1254724e6081c314b9f6366798c
+ 2020618007a6787ff4356e048785300879a5ce90c5ccf2e4aa1e664092a14cb0
+ acda0456e689e379c16c10007566c837a1628f0e468002a120093e54eed8991d
+ 7942a05ae06ef62e5bef187e7c92cfc9b477e6c9c6f37092d3a2b442c6a1f531
+ 4b4be5ab323486eb3bcef02028bf70f546b1ea923701609c9002efeded725e88
+ b275a9dfa8cd779954746843e3cca74e6d70565ec7fb396467512ddc9a957a44
+ 5c59d5a9e8e2d2fbb0ba452f74b0e105223848192de9b96efe65a7e4486d84b7
+ c1c7e73ebdd819520fe4769a587b3122f0727493d557643caecfeb2942113309
+ 28f6898da734c1f922f71c38a7da6a81760683c8eb8e94669b2988360b920de3
+ 255e87775af18786d80dc2a3ea1bc6f2d2b3de73426a31969ced09fb296ebf4f
+ d45b82b1fdcdfa1087e7df17adfb0e27896f7c970ef4c8df982e2cd0eaf005be
+ 82963142d2d64b570a9ea841eb3ded01b93f283ff51e837a28bd9e11eb5fd259
+ 1901f52c72520ed99d9774a3a0e20ea877c12d2a3e4cbd25bee33d93f5d856a5
+ 2b6ce7fa3c8d9250b10a59b6de9a3c46a3e1a65fc83a5c2594a04254fa7ff9bd
+ 993a2ea5b1e43c32488ecb47c22efd3eb5a05eb1c17dfd84a4d2882ab9d62c55
+ a315b29db6f7a8c7fdacca9f083b8acb055efe676656ea00156737f544a791b4
+ 5edb7bdb1bececf020f159d6060f057c4c3f196782e91a34d61b2653a854da40
+ 2465f58c0456b2a3e76361838d51fad963dbc02a51efe2d01f10875662e3a32e
+ e5d5949fd380697c8a759e3fc9ca4010e0eba8a1406e8fec31fc9a8b2ce0d0e2
+ 93332e568f3775b3df06a9e94aa87d7038a538aaab4c612825de5f1777246cf1
+ fc981f076f7b1c2ba5b717c370ad35c008c9afa21c1c80d57bc64075cb007205
+ b33cc81941532e427e121726447f70880c9c2c58226465d0874683e7333a0e15
+ 251fb76a72c46f1d5c25885bf6d7313d5adc745d06ffee1413bc347562a8eec6
+ 9ecca8afaa81feab79bfafd13cc1ccf06b85b5434a41f73f82f330fb421dae31
+ bec561cbbaf5a9a8db64d41d152a09f6ea0728b31394618e02f84612f33b6a97
+ 07c838fe60a514e6f4ad129d8a6dd1b9b504a5a6af667cdf06a21c3bc098cd94
+ 3ad0441c2261d6c618536818925971a993181102257bf3fa9a2320c93d480ba6
+ 0ceb920cc612f8089b0eab0ec65f0809f77bae63e40f5b06f621b60b9908d36c
+ e54852504560cdedd31c5b0cd043e90ab816fff3895499f944cf90cf05b9f5d2
+ 2702c8a383e5f76b858fb31dfe5cd382c1f7d73ade719b1273b3fe29d5aebde9
+ bd52e2ca1fc1af5bc5a7b0f397b59442a0d840e1cb08e5d2215d408808fd124e
+ c74174733e9046928c4e75a81f13defc76810b1d5d1da277a798bdc923a60dfa
+ e236a45cd1fb8c015209b1eb7c8cab61ab217a56f6c7fd45d4675d2d5a61e02c
+ cb104b86a4c7883e4d67e7b5dde25c1fd7cd24e4536c426c6030b9b66f7b70d1
+ bc01ec1a12738cf983d3803f56e6f3298bc99bb12280828d8e3713be86adff4d
+ cfb1d91299b12bd7e400d1f187d6f7a77d869d70fa43e158aa3a34750aa6f66f"
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PR PATCH] [Updated] firefox-esr: update to 91.12.0
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
2022-08-21 22:07 ` [PR PATCH] [Updated] " oreo639
@ 2022-08-22 2:22 ` oreo639
2022-08-22 14:39 ` biopsin
` (11 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-08-22 2:22 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1350 bytes --]
There is an updated pull request by oreo639 against master on the void-packages repository
https://github.com/oreo639/void-packages ffesr
https://github.com/void-linux/void-packages/pull/38817
firefox-esr: update to 91.12.0
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with gcc 12 and fixes build with the current cbindgen in the repos.
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/38817.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-ffesr-38817.patch --]
[-- Type: text/x-diff, Size: 15993 bytes --]
From bf740947ffd1d3e716bf151e9e83181fa7e10baf Mon Sep 17 00:00:00 2001
From: oreo639 <31916379+Oreo639@users.noreply.github.com>
Date: Sun, 21 Aug 2022 15:03:40 -0700
Subject: [PATCH 1/2] firefox-esr: update to 91.12.0
---
.../firefox-esr/patches/fix-cbindgen.patch | 22 +++++++++++++++++++
srcpkgs/firefox-esr/template | 4 ++--
2 files changed, 24 insertions(+), 2 deletions(-)
create mode 100644 srcpkgs/firefox-esr/patches/fix-cbindgen.patch
diff --git a/srcpkgs/firefox-esr/patches/fix-cbindgen.patch b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
new file mode 100644
index 000000000000..ba3ce7ae3e97
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
@@ -0,0 +1,22 @@
+Fix error with new cbindgen:
+
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi_generated.h:24:33: error: redefinition of 'constexpr const uint64_t mozilla::wr::ROOT_CLIP_CHAIN'
+ 24 | constexpr static const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi.h:76:16: note: 'const uint64_t mozilla::wr::ROOT_CLIP_CHAIN' previously defined here
+ 76 | const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+
+diff --git a/gfx/webrender_bindings/webrender_ffi.h b/gfx/webrender_bindings/webrender_ffi.h
+index b1d67b17a4bde..eb79974bdf434 100644
+--- a/gfx/webrender_bindings/webrender_ffi.h
++++ b/gfx/webrender_bindings/webrender_ffi.h
+@@ -73,8 +73,6 @@ struct WrPipelineInfo;
+ struct WrPipelineIdAndEpoch;
+ using WrPipelineIdEpochs = nsTArray<WrPipelineIdAndEpoch>;
+
+-const uint64_t ROOT_CLIP_CHAIN = ~0;
+-
+ } // namespace wr
+ } // namespace mozilla
+
diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template
index 58c065649bc4..373044d880c8 100644
--- a/srcpkgs/firefox-esr/template
+++ b/srcpkgs/firefox-esr/template
@@ -3,7 +3,7 @@
# THIS PKG MUST BE SYNCHRONIZED WITH "srcpkgs/firefox-esr-i18n".
#
pkgname=firefox-esr
-version=91.10.0
+version=91.12.0
revision=1
wrksrc="firefox-${version}"
build_helper="rust"
@@ -13,7 +13,7 @@ license="MPL-2.0, GPL-2.0-or-later, LGPL-2.1-or-later"
homepage="https://www.mozilla.org/firefox/"
distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz
https://github.com/chmeeedalf/gecko-dev/files/7729086/esrppcjit.tar.gz"
-checksum="825a8cb38bb5da9821ef87cc6de64af007cf0faef07c4ed0651283b56a0ee1bb
+checksum="6c0b8ff1826885eeace19ec87ae9e5a6512284d4863930713c8a288a03832b5c
5e926a8be5d6d4949c3bc3eb98e2103692eaa26a98928db432b1d44b535f7241"
lib32disabled=yes
From e661327fc3681afe6b8aa90f1c297aab477ce053 Mon Sep 17 00:00:00 2001
From: oreo639 <31916379+Oreo639@users.noreply.github.com>
Date: Sun, 21 Aug 2022 15:04:04 -0700
Subject: [PATCH 2/2] firefox-esr-i18n: update to 91.12.0.
---
srcpkgs/firefox-esr-i18n/template | 188 +++++++++++++++---------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/srcpkgs/firefox-esr-i18n/template b/srcpkgs/firefox-esr-i18n/template
index 765303a93236..dc5870558bde 100644
--- a/srcpkgs/firefox-esr-i18n/template
+++ b/srcpkgs/firefox-esr-i18n/template
@@ -1,6 +1,6 @@
# Template file for 'firefox-esr-i18n'
pkgname=firefox-esr-i18n
-version=91.10.0
+version=91.12.0
revision=1
build_style=meta
short_desc="Firefox ESR language packs"
@@ -135,96 +135,96 @@ _pkgtmpl() {
}
}
-checksum="6b47684de4218749d90a07b858ca298b034a2cda10655941e8ba47891d0d95ed
- 54852ef937387cba360fb2bed348c9bc3f1153f7242ad5491ca0b85ee6ed7455
- de66e0263dd0a2d87554fa1d9a406dee5cb3df1a774dffb8636e1be2bd80bc14
- 1f4824ad51a662285ac3a0d8029462a3bf12b36eb0834e65b9276e0869115c09
- a16fc6e0a1bf251ab19b7bbfb620b53437e5bf71b0e7871ed40ace8c97dbf635
- d9057bc71605f2a93d924beb37497195b8ad83501aa4d211ad71106e7b9bce4a
- 36316a7c4ca844ac3e81b2a0bb9ee4952017c2d2404f529848e280d04a21589b
- 150bafd02393355567d75bb9f966900e70502fdddff2822cbbd3bbc1fb3fd785
- 5b69e761666b28e5604d4cf8abc72acf3c3d79abeb7b6230e56aaae775ec225b
- b005c63d5e0d933ef1a4193b75a291a61524a939c3465d41ed111416210eb97f
- d5a2d2fafbfc50e23f5b68d30fcd7376d127f9f697c872d0d7c8e19ee4538cb1
- 16f88ec5de39f982057abcf34f17b22c698453debb62a5a18e0475798fc1cca9
- 84d491f73bc53da4605ee45a8633f14ee5672b9a61c40689d5e3289744a7cb2d
- 7781b6c29923360fd3a95bd2b2532eba7f92bed29640e0276c161eadbe56a13f
- 7984904ede35def33ccf73fda9aa46777c673c4d27de3806873d17694f7f0b13
- 4c57b6eb1cd968ba1eb4b427bed66bab04fb42424d03ae4b892fd3648e255b2e
- a80e9e2a6062bf68106ba1d1b8b7e2ff608ce52fa55d43558e7c073ec1872516
- 2b040ff1d010508760cb4ce4b76cce9e98b4620203c1ef77f87a336ced0aefc7
- 1fa4f5e59a9352f14aefe0cff8e8c4eed4eba16f4d8dbcec6850bce035301c18
- 2da0b09b9bf80f66edc6e3e9d5c1b75fae12905b5193cc64a73bb8bd7bfcbb04
- dce96c9fccb8c857f8cc370f7f5635b1475138195b05e944782b072beebc8d44
- e90dbf86c1823c209def11052995834ed15528dc5c6d3b502ed315dd471a9d5b
- f38624c81f2f9dac4f05b9e9d4d6e7a4e0381a279e3b4c53811aeb1db13cd000
- 221b7f4031a7c120d0ca753d93c41c18ac4f9500ae424c7983e4593497ddbbf8
- 60f5ceb21287a6786a6dd2d177325dfbcc6ca7f9a5df1b9299a2c5bb01d9c172
- 308ce25a9a0a9038dd94c2c22889c54def3937d35eafbcb34b75026cf3de3b8f
- 2d332a6f5bd92017700a15da5fe506612cea03b49f903592fc105fca978cd1d3
- 5cd35666f54a5ae4e35a1ca4c627cec8a47594da4083adf4f06dbe31c20a7444
- 1c1252765cb24f6a0206b648d834566aca9229075f7413f9c7deff1949a99c37
- 002772c46d6a7162e2add4726f105e4c0e355bbb84ce91b07ab02967cc5f1eb4
- 64ce2c0735caf9b67d2be003b1d667bce5ff614653151c617e4d26e349033e3a
- 60bd5f2532700ae9139d4d59a571b72b2806e80630fddb5f4444c7d6e377d2dc
- 2753317b7580ee1a377275905e254084263d0a87bda1bb572537fa75489d92dc
- 7f1b74d2cc5a9c4c6c7864a62eadef2b3d72c5cc2010f5c03bce3a9fae2286dc
- 2232c3b9a8f313145967152bf1dbafd6233593ceb422d2c3277d1b4cfecb6f50
- c41e866f3fc3cf0e0088681b55bb8489de1c5840ca7dc52d1f4f077b53452bd5
- 5d787fd6a9aa06ce31a6823b3393ba7ad66cf3d374dd6eaab3648103e826a10b
- 8d73e01655af7117856374be3669d530af96a79cdb8238bc953688d45e94567c
- 03f2b133746746c328cb7e4055b568d8e99cea51c845136c3f4446840d68e32f
- 691b0e760ebe5269dfa4aa4ea8dd2139260fbb0ca38af4c5438548b7c7ee88f5
- c63492236e75bf984a1671de95dddc954c1b4a1e92f5201c9b333faefae93035
- df9a036c67aecb1ea65f9709a11f6ccdf253451dcbe6b267437c51f422b9df2d
- 32ec78a51439b02f087c12c6be4a9159826113e83774085e800c37b6d7c112aa
- 1e44e3ded5aa07d44f3fdea8cf68bb33fd243cda159384ea8b87e783ed5c9a65
- 1cac44cdec68b56b77aba139a8425f607bac34ae2e09e27ecff2522b16fef44d
- aefb4fbacbdfc749a8d5888f7af48999406f207850fafae8ef39c083e08fa80c
- 753dbcffdf54ce3787a939517b059f11c305edc035bc22f8a9efed6145af6391
- 6c3be5abaf3878390b074970132c4cba935f7160f365cfa98a07e6b882084bdd
- 0b7771965f34c890dea0d2290a283212a1cdc0c8c8044ec634622d52eb595df9
- 0910f98a89b712a40aeb42761f25c763818af05edb5c96e2b6cfba023c28ab73
- 758ab6ea150702ee0d6203a0f75e8baa595c4a0f3d4cb9b87076f732a0e4546f
- d4259375f321b98426885e0b903199dce1f988c74963297bbd1a2aa8f94b0544
- 1614e1288f6d6ce43a7343586141df5e121cff7f1fd703ab4ec40a7f07498843
- 3ae5219a384a872fdbdd8ca5d99ad5370e0d8d87d93f5e39e96c5a2dc26736e3
- 05807b1c17849ffd2a3a63b1e26815dc9463aa3c137f640113530d2662d64116
- e4f3cfb11dfac8ec4caf29f34e20a0c0bb799649fd5b534f22f202c237491f7f
- 80b2b6446590a9fc55ed80a9e07b657cafc5d50294988974747c0e60d41f569b
- 1b32bc1282ded7f6f0f0979cbce3496ed07b1fcad64e70bbbc2eb5d2a8f3953b
- 0f80e3b0a9e17f39560b7cad8280e25c0278935f125d8e724a2381102abff783
- f259ee2683e525051d6f314d4bae4a98c0482a2a443aaac1160b2e0c1326b931
- b9a9eab4c5ea110ccbce20cb88e6652e2cf4c28bfd0aa95907148befd198544d
- a5a6e9bdaad420f281ce5fd16dabf5338d48c7cd8518c38b1e101b79b530fdb9
- a1fe6a2c7606b0720933496cad2bc959693905db87c3a2e5313db82dbfebda7c
- d1b22a495c637d5652c84afe8650d876b4206f2ea0d96751bec684ea63327f98
- e1587dac082479821697d97b4d5cb63a8d1f9189fdc2048885d963aea95b8400
- 6e40a5d5f0cb8794edc5f6a1fae778d89f6dbd97d8a288236d72fa571ffe91c9
- 33b5df625ae13ec35b41bb350e9e66d9ccc04f4d4d8c7e45020344739881e6d8
- e2f271691bb1b9873583175ff303bbaaf05a9d1207fbe8fffc34ec4abcfc1545
- 13382dabc604e99553c98b9e41eb046d4688b15f2ee9dd12c4f9c8967afa62d1
- 77133c69968073fec909dbe9e44d2eaea002cb0d0e142125865d1c03c89ed73d
- f8998128b0c656e72124baeff45c72013953f8314aa4959b6fef8a1b3039647f
- 2f24e5db025c0302fe3b696f280dcbab83728aaccaefe1ff082e165276896296
- d658095fd2d3e4d3decb8c2cdaa64f02fd8b663ba711fb9f2130ed7ed2a97291
- 7c28a82ecdd622653b26a9dd0913ac7d7cebe7246f64874fea2d1fa4af354c2a
- f78694d438032af3ca1a265a089407eb12b431bd314177672a66338b9bf7390f
- ea2d769b90a06400eba3e1f4eec58342fe4450ecce38b1e721923a65bed34337
- 8edf5b04b6cb477f482c14efdbada7023ff7a0ef584a4c30b2350e7825a612a0
- 851db60a218c36b61ee0adfcdc478bc051c95e41a4dba54d43594b8f03c6b187
- 6af72cae7f72ce68c644d49b6a621945f5e8f79119a86bb67ee144585f734925
- 7b01771078ec475b0103fcc4222b0b40eb92ec64180aaad02f2846cfdfb3e319
- 0c4df78eafbbe7ff98d9eff03bb258d1d0f4591102147f643ec395711f35d940
- cf21434f24e221ce58184f43a582c10187eceb7a71da5d81156cc870d78c1f4c
- 839088e2f23f6c62c38c45d5f7012513d95034aa5e6ab28307f152dbc10f97d3
- 4058ae6dd7b556bae2c13bb6fa0c5f16207c6fef4e0802d3d0badae2108a0da8
- d2c473fb93f0c4dc67ae18c25fdc414056bf779038c0f5dd25aa63a9a5cfcd0a
- 6e31c79b9955fd879528b0a614295da69ab26b608275946a4a5a29178a2aed20
- 852fe9ab16d29f7cf8f443bfd65fa1d522a9f27ef8766ad72a0c22a65450dc18
- 9411873b1ea01a1b8656957aedb79137f4c189b9cd3e96626c8e503539cf2c4b
- 5f43106472ae66dc8c0ffc317faba09c2370d4f18837c3cfaf05eb9b03f33b90
- 30f3f50133532ce379b9d5dd0f7e81204905e8a43a27e9d2ac1a26059e393913
- 285f615cc8852fd74bd7693a5a45b106f293c0a2d89836e9f25336ac6376af69
- 190ac7991a8b501fab2654d23b5f6f1e7a5f0cfeb402c8f5fe382d25c2222dc6
- 2de7676c71508ffbb337bdd8ca68f9d2fa1e30f23e8be283b937c5c4e30c59d6"
+checksum="fedea0f565a107674568bb867f1126b201f94155da4f33a4ba06372d6305fdaf
+ 3d6672cb7171258cd473778c7ca8835cac92c8f3d88fcb283cf6fb00ca2238b8
+ 3484191507d55a2ca0531b5bb942d2f1e1a0cb8b6d78f56fba09d85aaad8fb40
+ c4e40e3484e47dd87610413e1d77bf5569bf071b9631021259125465fe46875c
+ 1b92a2c12d2b8f0daf65568d4a06b52ee002028b611d4da8f586f129fd7bcf3c
+ 28789864690cd697f7028f7ea4f1c5e39115452effd98cd6ce011dbada9984a3
+ 6463f156654d607357edce6705981dc9cc1367a70acc41765e968b51e1112fe5
+ c6a0a57b1aa808c31802550856447f7fb251787ba4aecf6c3fe2b6db43e2357c
+ 76742b7c64d3c45765dfdff064f939dc5f648613b5b9cbae82827b747a8a763f
+ 564387ab8d6f7c0a203f90f888966aa85e89457a7c5f0991af9dfa908639f23a
+ 204a895f822a5bb3063037f42bd66c80ad06abdbcede62a5b0893f96d0e095e9
+ e0e83a93e497d8d15f4a4b6231b02a7286c578ca052ccda5f8329891bfbfad11
+ 2227844dca574b6e4d83b0a7c4d2015a596b55df8b1129be515161ca7a01af34
+ fd3d50ac9a46e56b954a8843ac45cff24af5e7b1e3c6b3a68f73092e05a5c3c5
+ 216f994f4cb5a9ed20f91fa4a2a485d1b677e31bb22c57d398c8a31653ea8dda
+ d5a3e92d9d78029286ab7a33766aa49ea439dd10e392481e3690560cb70445b2
+ 24533b096d4e86892e10f557b097cbde3666088f4087b6a07fcc6b14175677f0
+ 3de6d5c821f560e9bf8c1500d8285ee7de1f88bf1d8a7e8ee7d5569e4124f784
+ 578305cd0de9712e67dba9431c4dba9ea3a8f0bd5aa7b75ceee5b1d2590f59c0
+ f1437c43271230b7eadad262250656a445b95adbd2ce7ab6be78b2a577bea73d
+ 704668a2a6505700f13de47db3543552068cbdfe4f1f3a1d6fb11cb412d119d1
+ 215bec4c8b1f7438b1e8a6b89a44fcb6c70bccea5e8ff3534106686bc4073c68
+ aafcc3057b04b40b6cdf63fb17c8bb61b0bcc20afd5de66bef9f59cf36b8d5f3
+ c66de6da2ee4484ad3a98079efe8a4b3b97442dbe17f40ac39e342c52d20e7c0
+ 1b330a9b974fef1a3ce6870823fbca77fbaa3d83ed1868e9ba7d99f28c1750cd
+ 1cdd1fc81f8776ae1c0e5ad9d00e18cddb9902aee4825dfeb95240af6ba5897a
+ d65a443b90cb00a06df7196306667ba4293381260e0e610f34c1a10af8d2f02b
+ 37836f01c31a5fab00b21fef8a96f88977ae25543e7ab41ac2cfc8bb0fd81b8a
+ 86a5b99f28476b027e07029a3ed60487af0ae1890d6f90b8b6e7ead56698b306
+ 6a3c26d9b256a621e4289eae3fa0ecdaf8326ab4f90e84e189426dfee3fa0458
+ 9fe29366f3f252826a3abe749a802aa2164e5273d5a35521b2dbdff4017d2ba5
+ 635e3eaea0f94f5faa11bff02590dbc4563850af14d4f18aa134dea8f29c6899
+ 8c42dac92f9cf2bf15190080921a78917cb8a3f7c7df5ecabef0dce81c6c6dd4
+ 5e91979792c5fdd00b43692c69c6954de0e15dd4e1331050388dd4acf7c3870d
+ ce77d5238666f8be72f145edabb99d9155dd3ee592a2d00aeb4b96334432884e
+ 01fe38f57d5990ff4586f2539bf7f7b7d2a6d94306639d0237c9f8f01f982730
+ c6327f44a2d340d5c8ffe6f77ccfa813821a3302acf1999c083fb222eedfcb8a
+ e4f330f7b36f58ca23eff6b2ed99aba56b5b7b789a8f16ecf7825746ba0d388b
+ 81c701ef1b0592c593a30ff563ad30f7f3fa036e04889b7ff6eee5685879af57
+ 228310913898bd013f9c015ca47d415b653c323732fb87b918f5337488415e2b
+ 65a93f13bd35acf44da9cc12dd181d3778c598c83ee1c0aed77bc483004af364
+ 3b6aef851b9c761f7f8f0088cb568df361a835ba8d2b9c3897576f42c10692cd
+ ae3f507319906232ba5b0cfa7632288dcae161ef8278e4f44376070b146c2757
+ cca38399f8eecf3248fe1532f8659ee4bdf01876a271f16fe01ad892f8be405f
+ 6b925b174472e9a47a0be8e804a2647ede63bde9dc797d11b62752936f157cc1
+ f758adf61a8ecffb7997b2a22e523dbc76198139f0fbd67e83f81332a6cce4a8
+ 240071f9f5e8a4b56e2e43a654c5be9e26ac26a6fd7cfb8d595b1521a06426d8
+ 8bb8f990c045739506da2b445821ded94911e8459596f10c30488d4ff1a9476e
+ 6305fcb0b1fa9cd3d27c902d312549f5cbb911deff8fef4b6b0772563cab158e
+ 9b1d954852a8fd94b8946b80bb4fb387c13eeee0f54d62b8dda4d0dd1d03f40c
+ 6fd3f345dff25c7a3b2e83fdaf8bb4446b46755fad7ffdedeaa0800f5ac710a6
+ 85932c366b61b3d4a53437bddef66759d478da70e0b9ddaa2a39dbbdcebf6625
+ db70798770e4b31f4b31707f04919597e0109f51ea57f9013949ad05776d7df2
+ bb4319a3c1f2956fe1c7884cb87a2161798c009449d6c83d628584b98cc44b4d
+ fbecc5ad940ab62d2ffb0445ec91c4abd45f25f77298b8cc0a38c37ddd132184
+ 5b1fdb3709b8621953386f4229860978c55841e528f266368fcfb65ad2029f12
+ 52f0d6c5d9065e0a32bc4b7680cfb1755e75774cc97e505d15933ca0f8bed34a
+ b318939a52244c06e6ce578b6e0d8cc13345b1254724e6081c314b9f6366798c
+ 2020618007a6787ff4356e048785300879a5ce90c5ccf2e4aa1e664092a14cb0
+ acda0456e689e379c16c10007566c837a1628f0e468002a120093e54eed8991d
+ 7942a05ae06ef62e5bef187e7c92cfc9b477e6c9c6f37092d3a2b442c6a1f531
+ 4b4be5ab323486eb3bcef02028bf70f546b1ea923701609c9002efeded725e88
+ b275a9dfa8cd779954746843e3cca74e6d70565ec7fb396467512ddc9a957a44
+ 5c59d5a9e8e2d2fbb0ba452f74b0e105223848192de9b96efe65a7e4486d84b7
+ c1c7e73ebdd819520fe4769a587b3122f0727493d557643caecfeb2942113309
+ 28f6898da734c1f922f71c38a7da6a81760683c8eb8e94669b2988360b920de3
+ 255e87775af18786d80dc2a3ea1bc6f2d2b3de73426a31969ced09fb296ebf4f
+ d45b82b1fdcdfa1087e7df17adfb0e27896f7c970ef4c8df982e2cd0eaf005be
+ 82963142d2d64b570a9ea841eb3ded01b93f283ff51e837a28bd9e11eb5fd259
+ 1901f52c72520ed99d9774a3a0e20ea877c12d2a3e4cbd25bee33d93f5d856a5
+ 2b6ce7fa3c8d9250b10a59b6de9a3c46a3e1a65fc83a5c2594a04254fa7ff9bd
+ 993a2ea5b1e43c32488ecb47c22efd3eb5a05eb1c17dfd84a4d2882ab9d62c55
+ a315b29db6f7a8c7fdacca9f083b8acb055efe676656ea00156737f544a791b4
+ 5edb7bdb1bececf020f159d6060f057c4c3f196782e91a34d61b2653a854da40
+ 2465f58c0456b2a3e76361838d51fad963dbc02a51efe2d01f10875662e3a32e
+ e5d5949fd380697c8a759e3fc9ca4010e0eba8a1406e8fec31fc9a8b2ce0d0e2
+ 93332e568f3775b3df06a9e94aa87d7038a538aaab4c612825de5f1777246cf1
+ fc981f076f7b1c2ba5b717c370ad35c008c9afa21c1c80d57bc64075cb007205
+ b33cc81941532e427e121726447f70880c9c2c58226465d0874683e7333a0e15
+ 251fb76a72c46f1d5c25885bf6d7313d5adc745d06ffee1413bc347562a8eec6
+ 9ecca8afaa81feab79bfafd13cc1ccf06b85b5434a41f73f82f330fb421dae31
+ bec561cbbaf5a9a8db64d41d152a09f6ea0728b31394618e02f84612f33b6a97
+ 07c838fe60a514e6f4ad129d8a6dd1b9b504a5a6af667cdf06a21c3bc098cd94
+ 3ad0441c2261d6c618536818925971a993181102257bf3fa9a2320c93d480ba6
+ 0ceb920cc612f8089b0eab0ec65f0809f77bae63e40f5b06f621b60b9908d36c
+ e54852504560cdedd31c5b0cd043e90ab816fff3895499f944cf90cf05b9f5d2
+ 2702c8a383e5f76b858fb31dfe5cd382c1f7d73ade719b1273b3fe29d5aebde9
+ bd52e2ca1fc1af5bc5a7b0f397b59442a0d840e1cb08e5d2215d408808fd124e
+ c74174733e9046928c4e75a81f13defc76810b1d5d1da277a798bdc923a60dfa
+ e236a45cd1fb8c015209b1eb7c8cab61ab217a56f6c7fd45d4675d2d5a61e02c
+ cb104b86a4c7883e4d67e7b5dde25c1fd7cd24e4536c426c6030b9b66f7b70d1
+ bc01ec1a12738cf983d3803f56e6f3298bc99bb12280828d8e3713be86adff4d
+ cfb1d91299b12bd7e400d1f187d6f7a77d869d70fa43e158aa3a34750aa6f66f"
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
2022-08-21 22:07 ` [PR PATCH] [Updated] " oreo639
2022-08-22 2:22 ` oreo639
@ 2022-08-22 14:39 ` biopsin
2022-09-08 0:41 ` classabbyamp
` (10 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: biopsin @ 2022-08-22 14:39 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 173 bytes --]
New comment by biopsin on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1222455434
Comment:
Tests ok for me on x86_64-glibc
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (2 preceding siblings ...)
2022-08-22 14:39 ` biopsin
@ 2022-09-08 0:41 ` classabbyamp
2022-09-08 1:04 ` oreo639
` (9 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: classabbyamp @ 2022-09-08 0:41 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 180 bytes --]
New comment by classabbyamp on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1240062616
Comment:
91.13.0 and 102.2.0 are available
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (3 preceding siblings ...)
2022-09-08 0:41 ` classabbyamp
@ 2022-09-08 1:04 ` oreo639
2022-09-08 1:05 ` classabbyamp
` (8 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 1:04 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 558 bytes --]
New comment by oreo639 on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1240085243
Comment:
> 91.13.0 and 102.2.0 are available
I didn't update it to 102.2.0 because the ppc64le js jit patches haven't been updated for firefox 102 (the author of the patches only got as far as just copying over some of the files from the 91 branch to the 102 branch and nothing more).
I can try updating to that if it is okay to drop those patches.
Otherwise I will update it to 91.13.0 when I am available.
Thanks.
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (4 preceding siblings ...)
2022-09-08 1:04 ` oreo639
@ 2022-09-08 1:05 ` classabbyamp
2022-09-08 1:08 ` oreo639
` (7 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: classabbyamp @ 2022-09-08 1:05 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 279 bytes --]
New comment by classabbyamp on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1240088551
Comment:
maybe [chimera's patches](https://github.com/chimera-linux/cports/tree/master/contrib/firefox-esr/patches) can provide some insight?
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (5 preceding siblings ...)
2022-09-08 1:05 ` classabbyamp
@ 2022-09-08 1:08 ` oreo639
2022-09-08 9:18 ` [PR PATCH] [Updated] " oreo639
` (6 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 1:08 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 259 bytes --]
New comment by oreo639 on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1240093166
Comment:
It doesn't have the patches:
https://github.com/chimera-linux/cports/blob/master/contrib/firefox-esr/template.py#L26
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PR PATCH] [Updated] firefox-esr: update to 91.12.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (6 preceding siblings ...)
2022-09-08 1:08 ` oreo639
@ 2022-09-08 9:18 ` oreo639
2022-09-08 11:21 ` [PR PATCH] [Updated] firefox-esr: update to 102.2.0 oreo639
` (5 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 9:18 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1351 bytes --]
There is an updated pull request by oreo639 against master on the void-packages repository
https://github.com/oreo639/void-packages ffesr
https://github.com/void-linux/void-packages/pull/38817
firefox-esr: update to 91.12.0.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with gcc 12 and fixes build with the current cbindgen in the repos.
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
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and test at least one native build and, if supported, at least one cross build.
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-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/38817.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-ffesr-38817.patch --]
[-- Type: text/x-diff, Size: 246931 bytes --]
From 34dfc955a82ad8561056dca8dce83b8e8b046b2d Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:12:06 -0700
Subject: [PATCH 1/2] firefox-esr-i18n: update to 102.2.0.
---
srcpkgs/firefox-esr-i18n/template | 188 +++++++++++++++---------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/srcpkgs/firefox-esr-i18n/template b/srcpkgs/firefox-esr-i18n/template
index 765303a93236..f518c78f2539 100644
--- a/srcpkgs/firefox-esr-i18n/template
+++ b/srcpkgs/firefox-esr-i18n/template
@@ -1,6 +1,6 @@
# Template file for 'firefox-esr-i18n'
pkgname=firefox-esr-i18n
-version=91.10.0
+version=102.2.0
revision=1
build_style=meta
short_desc="Firefox ESR language packs"
@@ -135,96 +135,96 @@ _pkgtmpl() {
}
}
-checksum="6b47684de4218749d90a07b858ca298b034a2cda10655941e8ba47891d0d95ed
- 54852ef937387cba360fb2bed348c9bc3f1153f7242ad5491ca0b85ee6ed7455
- de66e0263dd0a2d87554fa1d9a406dee5cb3df1a774dffb8636e1be2bd80bc14
- 1f4824ad51a662285ac3a0d8029462a3bf12b36eb0834e65b9276e0869115c09
- a16fc6e0a1bf251ab19b7bbfb620b53437e5bf71b0e7871ed40ace8c97dbf635
- d9057bc71605f2a93d924beb37497195b8ad83501aa4d211ad71106e7b9bce4a
- 36316a7c4ca844ac3e81b2a0bb9ee4952017c2d2404f529848e280d04a21589b
- 150bafd02393355567d75bb9f966900e70502fdddff2822cbbd3bbc1fb3fd785
- 5b69e761666b28e5604d4cf8abc72acf3c3d79abeb7b6230e56aaae775ec225b
- b005c63d5e0d933ef1a4193b75a291a61524a939c3465d41ed111416210eb97f
- d5a2d2fafbfc50e23f5b68d30fcd7376d127f9f697c872d0d7c8e19ee4538cb1
- 16f88ec5de39f982057abcf34f17b22c698453debb62a5a18e0475798fc1cca9
- 84d491f73bc53da4605ee45a8633f14ee5672b9a61c40689d5e3289744a7cb2d
- 7781b6c29923360fd3a95bd2b2532eba7f92bed29640e0276c161eadbe56a13f
- 7984904ede35def33ccf73fda9aa46777c673c4d27de3806873d17694f7f0b13
- 4c57b6eb1cd968ba1eb4b427bed66bab04fb42424d03ae4b892fd3648e255b2e
- a80e9e2a6062bf68106ba1d1b8b7e2ff608ce52fa55d43558e7c073ec1872516
- 2b040ff1d010508760cb4ce4b76cce9e98b4620203c1ef77f87a336ced0aefc7
- 1fa4f5e59a9352f14aefe0cff8e8c4eed4eba16f4d8dbcec6850bce035301c18
- 2da0b09b9bf80f66edc6e3e9d5c1b75fae12905b5193cc64a73bb8bd7bfcbb04
- dce96c9fccb8c857f8cc370f7f5635b1475138195b05e944782b072beebc8d44
- e90dbf86c1823c209def11052995834ed15528dc5c6d3b502ed315dd471a9d5b
- f38624c81f2f9dac4f05b9e9d4d6e7a4e0381a279e3b4c53811aeb1db13cd000
- 221b7f4031a7c120d0ca753d93c41c18ac4f9500ae424c7983e4593497ddbbf8
- 60f5ceb21287a6786a6dd2d177325dfbcc6ca7f9a5df1b9299a2c5bb01d9c172
- 308ce25a9a0a9038dd94c2c22889c54def3937d35eafbcb34b75026cf3de3b8f
- 2d332a6f5bd92017700a15da5fe506612cea03b49f903592fc105fca978cd1d3
- 5cd35666f54a5ae4e35a1ca4c627cec8a47594da4083adf4f06dbe31c20a7444
- 1c1252765cb24f6a0206b648d834566aca9229075f7413f9c7deff1949a99c37
- 002772c46d6a7162e2add4726f105e4c0e355bbb84ce91b07ab02967cc5f1eb4
- 64ce2c0735caf9b67d2be003b1d667bce5ff614653151c617e4d26e349033e3a
- 60bd5f2532700ae9139d4d59a571b72b2806e80630fddb5f4444c7d6e377d2dc
- 2753317b7580ee1a377275905e254084263d0a87bda1bb572537fa75489d92dc
- 7f1b74d2cc5a9c4c6c7864a62eadef2b3d72c5cc2010f5c03bce3a9fae2286dc
- 2232c3b9a8f313145967152bf1dbafd6233593ceb422d2c3277d1b4cfecb6f50
- c41e866f3fc3cf0e0088681b55bb8489de1c5840ca7dc52d1f4f077b53452bd5
- 5d787fd6a9aa06ce31a6823b3393ba7ad66cf3d374dd6eaab3648103e826a10b
- 8d73e01655af7117856374be3669d530af96a79cdb8238bc953688d45e94567c
- 03f2b133746746c328cb7e4055b568d8e99cea51c845136c3f4446840d68e32f
- 691b0e760ebe5269dfa4aa4ea8dd2139260fbb0ca38af4c5438548b7c7ee88f5
- c63492236e75bf984a1671de95dddc954c1b4a1e92f5201c9b333faefae93035
- df9a036c67aecb1ea65f9709a11f6ccdf253451dcbe6b267437c51f422b9df2d
- 32ec78a51439b02f087c12c6be4a9159826113e83774085e800c37b6d7c112aa
- 1e44e3ded5aa07d44f3fdea8cf68bb33fd243cda159384ea8b87e783ed5c9a65
- 1cac44cdec68b56b77aba139a8425f607bac34ae2e09e27ecff2522b16fef44d
- aefb4fbacbdfc749a8d5888f7af48999406f207850fafae8ef39c083e08fa80c
- 753dbcffdf54ce3787a939517b059f11c305edc035bc22f8a9efed6145af6391
- 6c3be5abaf3878390b074970132c4cba935f7160f365cfa98a07e6b882084bdd
- 0b7771965f34c890dea0d2290a283212a1cdc0c8c8044ec634622d52eb595df9
- 0910f98a89b712a40aeb42761f25c763818af05edb5c96e2b6cfba023c28ab73
- 758ab6ea150702ee0d6203a0f75e8baa595c4a0f3d4cb9b87076f732a0e4546f
- d4259375f321b98426885e0b903199dce1f988c74963297bbd1a2aa8f94b0544
- 1614e1288f6d6ce43a7343586141df5e121cff7f1fd703ab4ec40a7f07498843
- 3ae5219a384a872fdbdd8ca5d99ad5370e0d8d87d93f5e39e96c5a2dc26736e3
- 05807b1c17849ffd2a3a63b1e26815dc9463aa3c137f640113530d2662d64116
- e4f3cfb11dfac8ec4caf29f34e20a0c0bb799649fd5b534f22f202c237491f7f
- 80b2b6446590a9fc55ed80a9e07b657cafc5d50294988974747c0e60d41f569b
- 1b32bc1282ded7f6f0f0979cbce3496ed07b1fcad64e70bbbc2eb5d2a8f3953b
- 0f80e3b0a9e17f39560b7cad8280e25c0278935f125d8e724a2381102abff783
- f259ee2683e525051d6f314d4bae4a98c0482a2a443aaac1160b2e0c1326b931
- b9a9eab4c5ea110ccbce20cb88e6652e2cf4c28bfd0aa95907148befd198544d
- a5a6e9bdaad420f281ce5fd16dabf5338d48c7cd8518c38b1e101b79b530fdb9
- a1fe6a2c7606b0720933496cad2bc959693905db87c3a2e5313db82dbfebda7c
- d1b22a495c637d5652c84afe8650d876b4206f2ea0d96751bec684ea63327f98
- e1587dac082479821697d97b4d5cb63a8d1f9189fdc2048885d963aea95b8400
- 6e40a5d5f0cb8794edc5f6a1fae778d89f6dbd97d8a288236d72fa571ffe91c9
- 33b5df625ae13ec35b41bb350e9e66d9ccc04f4d4d8c7e45020344739881e6d8
- e2f271691bb1b9873583175ff303bbaaf05a9d1207fbe8fffc34ec4abcfc1545
- 13382dabc604e99553c98b9e41eb046d4688b15f2ee9dd12c4f9c8967afa62d1
- 77133c69968073fec909dbe9e44d2eaea002cb0d0e142125865d1c03c89ed73d
- f8998128b0c656e72124baeff45c72013953f8314aa4959b6fef8a1b3039647f
- 2f24e5db025c0302fe3b696f280dcbab83728aaccaefe1ff082e165276896296
- d658095fd2d3e4d3decb8c2cdaa64f02fd8b663ba711fb9f2130ed7ed2a97291
- 7c28a82ecdd622653b26a9dd0913ac7d7cebe7246f64874fea2d1fa4af354c2a
- f78694d438032af3ca1a265a089407eb12b431bd314177672a66338b9bf7390f
- ea2d769b90a06400eba3e1f4eec58342fe4450ecce38b1e721923a65bed34337
- 8edf5b04b6cb477f482c14efdbada7023ff7a0ef584a4c30b2350e7825a612a0
- 851db60a218c36b61ee0adfcdc478bc051c95e41a4dba54d43594b8f03c6b187
- 6af72cae7f72ce68c644d49b6a621945f5e8f79119a86bb67ee144585f734925
- 7b01771078ec475b0103fcc4222b0b40eb92ec64180aaad02f2846cfdfb3e319
- 0c4df78eafbbe7ff98d9eff03bb258d1d0f4591102147f643ec395711f35d940
- cf21434f24e221ce58184f43a582c10187eceb7a71da5d81156cc870d78c1f4c
- 839088e2f23f6c62c38c45d5f7012513d95034aa5e6ab28307f152dbc10f97d3
- 4058ae6dd7b556bae2c13bb6fa0c5f16207c6fef4e0802d3d0badae2108a0da8
- d2c473fb93f0c4dc67ae18c25fdc414056bf779038c0f5dd25aa63a9a5cfcd0a
- 6e31c79b9955fd879528b0a614295da69ab26b608275946a4a5a29178a2aed20
- 852fe9ab16d29f7cf8f443bfd65fa1d522a9f27ef8766ad72a0c22a65450dc18
- 9411873b1ea01a1b8656957aedb79137f4c189b9cd3e96626c8e503539cf2c4b
- 5f43106472ae66dc8c0ffc317faba09c2370d4f18837c3cfaf05eb9b03f33b90
- 30f3f50133532ce379b9d5dd0f7e81204905e8a43a27e9d2ac1a26059e393913
- 285f615cc8852fd74bd7693a5a45b106f293c0a2d89836e9f25336ac6376af69
- 190ac7991a8b501fab2654d23b5f6f1e7a5f0cfeb402c8f5fe382d25c2222dc6
- 2de7676c71508ffbb337bdd8ca68f9d2fa1e30f23e8be283b937c5c4e30c59d6"
+checksum="d5a1473ebe95cd18f90ed0d9cf305ee6559a4f224f07cc59f1c5e1de30c65a87
+ c51c457d98da7bb1145456b57826bddb130cbe2a02bd1f9609eede50c5fc47ad
+ c11c1457d9654943003ccbf5669e1b7f78a392719ef1c1179213f517702cc2fd
+ 47f2aaa9ec19525f8877d31fd3dac68347e0ca11b98faacc9fc2cf6ffc09bbd9
+ 221b8508b66ad184a61e11c6278aee0bee6492e4b7bf74cb2daade4f406797f0
+ 5e56b37fa673f72fd7f1e88871337e3faaff871e6b00e31b44aa6ebf1db607a4
+ 93a8c6971f3d313b88954260b5247e666829adc522c6e226cdd7432288728080
+ 6960c4d2f487d57a8163e083f9eba0da20515d9e12942cb3c449948fa2d1bbff
+ dee27babb195f5bf7afdd8571ee6246259555808840d0a29f9dacacc0b6ca5b6
+ 3079b3bbb9c50f6acf5bb4f91846dafdda432a7b26723f170701889dba313820
+ 216171a907c45bd26a78fe071e1eb1666a3e7694888003e507b259bf7a2229c4
+ 47cc7b638478cad28b4e5e027e8f10f309a54abc6b0f4317e878b1376d6a282b
+ a1bfd2f5ef6dfc0d7e19699ebad6af11b6d1e6ed6ce8a0c6176f0f294d136aeb
+ 399c223f82b97e5773df35613d094f0ed73d4a2b99f2fb65936eb5aa8ec3e51a
+ d164ba3d47d79e7bc171d235053c5e51ebb71b199edd389d262fe0ddd991f014
+ 48dffaf3638e4d8c0897a07b105036fcc2ac4e132b999d726d83725c58fb0381
+ 48bf4e31f4abd7a456042566ce772c335f5627618e52614cf8426efb503802c4
+ f4c620403e732346fa66d6dd38d54252d96d924a9c6c1a0da0c077440a4c70ef
+ 4db7491052e565fbe07aa8a37166920fe7b049cef4b7f2774c0b593ff805c0aa
+ ba7f6cca8d7ede6c4562adf9cc3e2896efe08fab6e11ca964c2297e5b01eb6ae
+ b93c9812733e2bf504e77519485c345791836b30958285fdf57c364f1673fcd0
+ 8079d1c5d7e23955e845bc17bc4fbfe2a3456e7ba1a7bd01ff01664d827438e2
+ a53f01d68fca8b58de937256fb962e3b978f5ffd00d2d11b6f2028a529c1f9c9
+ 417ad3babd8e62a74e65dda70d9fd47e4be900e1ea8aba1c960a9736c3ef66a5
+ 6de44c4367e370370cec480e2c3979ccdbb03f32de42bf0e15b7d5336092f2cb
+ 9d12f575e0fe8909d8792f9a4cd66d71435a79e9463a0d1f1f7142b92e0347dd
+ 08fb7caa2676ddf16e81514e660870214db39ae965ebfd9c0a24e055190c1a30
+ dc189ba71869a2052b63d08cfc2ad39fc34f3a035ff5a9910d1d07dd9ffde149
+ 1295ebf8671f823704070d4ff4f7b3eb956c419348ddb4cca1f8a33ade8caece
+ 2277c0000d1237b9159c4cdcf7f2aade52d09e4b3d04d505445dd86861359176
+ 1acc3a9c996bd331d1eefb534da41eb84cbd7a39755f277814bd7ca9609d240d
+ 5d8b9cd48a9ffd104939f4b4cd5c5c5146bcf56067280bd8e49715e95e42d53c
+ 8932a8157b092f196493f62633c3291a9575f722b810f0f9c793bc7690883866
+ fa1312afe79f2ee7f2470b3b101eac6f8689ee494e6d0a9ecc96efa455a09aeb
+ 1802755f0fc08510a0a614b5a32086b942c4ce6d8a90c6145ce6ac0c66fe07e0
+ caf2b000fd9a03732378332dc6599e628a85e44c6f4f982b483f4827fde7a5fe
+ 60c2be815d5994fcfe5133bee2ca79730f7a29fe5238f7300ef49fc941b79062
+ 7ca5bba5f47bf2da6def8d29f832333c09e7ff6c271521916c4ea42dfb6b37da
+ 7bf29d75d905fd8f0b9700de433448dbefb304c8dd181a6560d1ede433040800
+ 591d8c31cab9e3009753d2eb4bf41098a02c5b11b763a633adcb49afaf41ccd0
+ 8cec17c0174a3c9eeb512dd9c88cdf4fb2dc6b68a6e38466f4edb499af524a33
+ 36055161e5df1cde24351eb35269c0aac68c8b279116cc984cc93c9b01e196f9
+ 9533f3f7c4dec42e36fe3dcf31a7f00ac1bdda64e4ea47c0a563c4b33d6b9606
+ 80e176922404452a5f0871d493fa0e8bf7b2a2fdb317e3cd017595ffde131793
+ 4ddfc3938943c8e2d1f2b38f04566c264f1f7b6faf38456a8973937eec4f770b
+ 1c257033946f3316d1a6ad3a700b124f9f36f0ace5f9d1fec50c391ab7fd3721
+ 6d7d300c1ce9928669a3b837479e9aa8c7ef4cef113839f6e17684c58153fbc0
+ 00ea98387fc098f4fb5a7cd3e42aac5a9ce62c77805d371c489cff5ba4393d2d
+ 8f4c302dda19be2ce6704b205243c7e27e77129992bc78db330855e4aebb56a9
+ 42a0495577b5874363faf0117ef406bdee63f8274f3475f8746ec50ef601f895
+ 48c853fcb62a8fb9743fea55b3db579917130acaf0749e1e61245941e80cab62
+ 2c9cf98785c43fa49df30c7d5253c7abf90dd856ec19529a6f76bd2e19f818fc
+ e38cffcc6802078e04324846fffddbfb33c66ebcca7179a26beacfa52262681d
+ 9267b8a3a4231f45e50e9f0f3eb803e1210eae7168f57e6bb668fda47a3914b1
+ d3828f3fc4e8f198a4d05e59952f5dc2790dc0b9472a2cfc1b70d668d8af75ee
+ eb20c6ef5ed9e58d17d55f978ae9b31273ba909aee23ab88726afa0569f047c2
+ 2c8c417e039579f7a5191a9ac763cd37101b6ffa0ef34ab9e4241454304a6b99
+ eb49f9396fffabf2824b008894a1f88d5304220bba420418c48c03e50570d381
+ 6c06668712b03657604d55720a876cf63ebc0809a776578f0d2567cb284aae3f
+ 9e81cb09e69da35f9d3a2c5692f747c77963e7a79ff18bfea06abaed69c7b40f
+ f229adf1ab6a2ca65b90899bf825b50a95637b1013fd13c46baf16b2927e0ca5
+ fb29d32429f5fcfe4081f539f00132b850d8231ba8caae84ee74cccf32f8f8e6
+ 48cb704832c25635a4c02877b8dcf26216f519f68b878daa83e3580dd5fd77ee
+ e284ff3a5dab91f30cfeafd3f8aa5d1bd39aa56e8e99fdd86e34928f3414e531
+ 074969a45f46475100ae4956020ef71ad749ad3c02c9a8a6270a4a7ff915fe5c
+ 74825698f655180440e8c28eb317090555fd326eb19cca3c3369297cc2db193c
+ 3bdc7711751357f5211ade94f5c4ed1422811ad41f8d751c0e96c619d787d3c6
+ 578bb94490bef477b1c2f3fe1e47e1b57cf5bfaab937cad40859164141e1ca01
+ 5650824ee3e48839bd6429fefc744d1cda0123e0a2f1414042e5ad40f040fd71
+ fc41f0e9c8f1225666b1d6ceb7d30a21d80f39d89cbed65443afdf976840e3ce
+ 855e130f9b3b4a22d253df8b11bf20cd4528c67dc049b414667505e4eec5b3f9
+ 4cb1f99c98d078774ad389a086f1fec3957033be8ddfea80d57ccc2b2fcd912b
+ 618da6ad432aad58c2a2b8fa3fd2eabf46b9be1bf6db06b5b892adf76d616afb
+ 75f8701df6519a294d17799fe3ecb9d02177af56b0274269eddc6f4f1809bd11
+ 4f68f7af30eacf130c43a5ec14f1ca573eeb0fcb1c9242fc28e1b5ccf4274eaf
+ a6b37e3056a7845ddd49de9f0ef332bc5749477da6fee788f17e1db88c349b4f
+ 9e7418e4ba553811c54a3a04cb85c680016285291a1671abff0e81017af1d749
+ 090ea71643b074ddb6717531095e2c3cf7a2a4eaab2d729d0d3bfc28058bad8a
+ eaba5ef15835c68ec07580b8523819ba07e03ae3af25ac5c10193e3179c73bf4
+ 803e2969f15a3d738f65cbbf9d3054a039f9381327f9007e8590754f7419e70c
+ 4ab75978d8ec20846503002d3bbc959b12717695898fba5d53b1a80f5cd7a820
+ 2c15fac71576bad1e80838ee0969572bf2c15bf729356d23ae54515e16901e52
+ 145f1e77d894d1fc120bdcd6582a72f971909789506d9ae5b1997c57d27d50c6
+ 0e9b73e34ce7ca39253d1e0ded022c05654841aa61c34c284906492d4bbe27da
+ 337dab583aa1d3d524b9241ce5e94b7fe54c41dc86f0ea5c8c6b021fa3b66c66
+ 58b361eeac66c68cb3728b68afebe0648559ac6552d8cfaed3cb35a952c9fb2b
+ d8531ee94abe01ea46641f1e7eb13fffa8d81228c14ca074990e7ea4c10dcd53
+ 407ea5363696ef77fc0cffa7f5c27e78025f69248d82ac85f82452a7f5466502
+ 9e5be4dd61ec9ab0b3fad41ddf28a4cc16a97e6450ace4f112c0b843f143acbb
+ 582126ed73f312529608a44fe46935d10957cd5d46fefa7ca33b93e2a4283d84
+ 2a36bbcdc59adbf948bd5ae3176739cd5dee91f661546fffe4041a294152d4cf
+ 5e32e063c559910c5bf49bf835c47d69584a6b552a3b031433ca880618834ab9
+ 60a96f115e5cdca96e333d83955ad3e24860c61f212ada5954ef62072a9a9d85"
From 4d274b5850d94688a57f1634cc79d0ebdcbfb80c Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:13:13 -0700
Subject: [PATCH 2/2] firefox-esr: update to 102.2.0.
---
.../patches/fix-build-rust-simd2.patch | 729 ++++
.../firefox-esr/patches/fix-cbindgen.patch | 22 +
...n-path.patch => fix-firefox-desktop.patch} | 11 +-
srcpkgs/firefox-esr/patches/fix-tools.patch | 13 -
.../patches/fix-webrtc-glibcisms.patch | 24 +-
srcpkgs/firefox-esr/patches/ppc64le-jit.patch | 3441 -----------------
srcpkgs/firefox-esr/patches/skia-sucks3.patch | 24 -
srcpkgs/firefox-esr/patches/sndio.patch | 52 -
srcpkgs/firefox-esr/template | 28 +-
9 files changed, 784 insertions(+), 3560 deletions(-)
create mode 100644 srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
create mode 100644 srcpkgs/firefox-esr/patches/fix-cbindgen.patch
rename srcpkgs/firefox-esr/patches/{fix-desktop-icon-path.patch => fix-firefox-desktop.patch} (64%)
delete mode 100644 srcpkgs/firefox-esr/patches/fix-tools.patch
delete mode 100644 srcpkgs/firefox-esr/patches/ppc64le-jit.patch
delete mode 100644 srcpkgs/firefox-esr/patches/sndio.patch
diff --git a/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
new file mode 100644
index 000000000000..e20e6bf6026d
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
@@ -0,0 +1,729 @@
+From ada04eb9b82531a41553b6ffc2ba3194c70fdc45 Mon Sep 17 00:00:00 2001
+From: Mike Hommey <mh+mozilla@glandium.org>
+Date: Wed, 24 Aug 2022 06:58:59 +0000
+Subject: [PATCH] Bug 1783784 - Update packed_simd_2 to 0.3.8.
+
+Differential Revision: https://phabricator.services.mozilla.com/D154063
+---
+ .cargo/config.in | 2 +-
+ Cargo.lock | 5 +-
+ Cargo.toml | 2 +-
+ .../rust/packed_simd_2/.cargo-checksum.json | 2 +-
+ third_party/rust/packed_simd_2/Cargo.toml | 5 +-
+ third_party/rust/packed_simd_2/README.md | 2 +-
+ third_party/rust/packed_simd_2/build.rs | 5 +
+ third_party/rust/packed_simd_2/src/api.rs | 4 +-
+ third_party/rust/packed_simd_2/src/codegen.rs | 50 +++++-----
+ .../packed_simd_2/src/codegen/bit_manip.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/llvm.rs | 98 +++++++++----------
+ .../rust/packed_simd_2/src/codegen/math.rs | 2 +-
+ .../packed_simd_2/src/codegen/math/float.rs | 28 +++---
+ .../src/codegen/math/float/abs.rs | 2 +-
+ .../src/codegen/math/float/cos.rs | 2 +-
+ .../src/codegen/math/float/cos_pi.rs | 2 +-
+ .../src/codegen/math/float/exp.rs | 2 +-
+ .../src/codegen/math/float/ln.rs | 2 +-
+ .../src/codegen/math/float/mul_add.rs | 2 +-
+ .../src/codegen/math/float/mul_adde.rs | 2 +-
+ .../src/codegen/math/float/powf.rs | 2 +-
+ .../src/codegen/math/float/sin.rs | 2 +-
+ .../src/codegen/math/float/sin_cos_pi.rs | 2 +-
+ .../src/codegen/math/float/sin_pi.rs | 2 +-
+ .../src/codegen/math/float/sqrt.rs | 2 +-
+ .../src/codegen/math/float/sqrte.rs | 2 +-
+ .../src/codegen/pointer_sized_int.rs | 24 ++---
+ .../packed_simd_2/src/codegen/reductions.rs | 2 +-
+ .../src/codegen/reductions/mask.rs | 4 +-
+ .../packed_simd_2/src/codegen/swap_bytes.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/vPtr.rs | 2 +-
+ third_party/rust/packed_simd_2/src/lib.rs | 7 +-
+ third_party/rust/packed_simd_2/src/testing.rs | 2 +-
+ 33 files changed, 144 insertions(+), 136 deletions(-)
+
+diff --git a/.cargo/config.in b/.cargo/config.in
+index a6e396b29f764..2e5bad6fed2c6 100644
+--- a/.cargo/config.in
++++ b/.cargo/config.in
+@@ -70,7 +70,7 @@ rev = "746743227485a83123784df0c53227ab466612ed"
+ [source."https://github.com/hsivonen/packed_simd"]
+ git = "https://github.com/hsivonen/packed_simd"
+ replace-with = "vendored-sources"
+-rev = "c149d0a519bf878567c7630096737669ec2ff15f"
++rev = "f38664024b29d44c506431eada7c112629bb1aa9"
+
+ [source."https://github.com/hsivonen/chardetng_c"]
+ git = "https://github.com/hsivonen/chardetng_c"
+diff --git a/Cargo.lock b/Cargo.lock
+index 0560a3c86be85..ebec60085c0c0 100644
+--- a/Cargo.lock
++++ b/Cargo.lock
+@@ -3812,10 +3812,11 @@ dependencies = [
+
+ [[package]]
+ name = "packed_simd_2"
+-version = "0.3.7"
+-source = "git+https://github.com/hsivonen/packed_simd?rev=c149d0a519bf878567c7630096737669ec2ff15f#c149d0a519bf878567c7630096737669ec2ff15f"
++version = "0.3.8"
++source = "git+https://github.com/hsivonen/packed_simd?rev=f38664024b29d44c506431eada7c112629bb1aa9#f38664024b29d44c506431eada7c112629bb1aa9"
+ dependencies = [
+ "cfg-if 1.0.0",
++ "rustc_version",
+ ]
+
+ [[package]]
+diff --git a/Cargo.toml b/Cargo.toml
+index de7ee7ac7cc1f..f576534bf3f8b 100644
+--- a/Cargo.toml
++++ b/Cargo.toml
+@@ -113,7 +113,7 @@ chardetng_c = { git = "https://github.com/hsivonen/chardetng_c", rev="ed8a4c6f90
+ coremidi = { git = "https://github.com/chris-zen/coremidi.git", rev="fc68464b5445caf111e41f643a2e69ccce0b4f83" }
+ fog = { path = "toolkit/components/glean/api" }
+ libudev-sys = { path = "dom/webauthn/libudev-sys" }
+-packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="c149d0a519bf878567c7630096737669ec2ff15f" }
++packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="f38664024b29d44c506431eada7c112629bb1aa9" }
+ midir = { git = "https://github.com/mozilla/midir.git", rev = "4c11f0ffb5d6a10de4aff40a7b81218b33b94e6f" }
+ minidump_writer_linux = { git = "https://github.com/rust-minidump/minidump-writer.git", rev = "75ada456c92a429704691a85e1cb42fef8cafc0d" }
+
+diff --git a/third_party/rust/packed_simd_2/.cargo-checksum.json b/third_party/rust/packed_simd_2/.cargo-checksum.json
+index 3090b655a160c..079b4c559f5ee 100644
+--- a/third_party/rust/packed_simd_2/.cargo-checksum.json
++++ b/third_party/rust/packed_simd_2/.cargo-checksum.json
+@@ -1 +1 @@
+-{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"f85e54e13a05f6e4f27c230ab81430af27b6ff80a1c036bd70c42ea115f89487","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"882f8894b333becf490d23c9024a86fd1327c8edea33aa8dbb98dc2f2ddb3956","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"019ed29c43989782d8eec3a961654cfc172d7a7898da4eca8f654700af7e1988","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"f6e92f056565e6fd93f98829a408aee9e790251e0cbd8a8bc30c8662b4d6fabb","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"a29d38fa0a85eaf787fb49989e625bf64effd5f39c126fbb2a24be206d2a3917","src/codegen/bit_manip.rs":"9991570a21ca98134b08b5c5935e2c259cea39c82d9d1529f52c561a84fec642","src/codegen/llvm.rs":"5bc6751293f9f184cf23d5df448c7d58b58b799e41c7a91f8ca41a5ba56e64ec","src/codegen/math.rs":"35f96e37a78fcf0cdb02146b7f27a45108fe06a37fc2a54d8851ce131a326178","src/codegen/math/float.rs":"dd86c0449e576c83b719700962ac017c332987fac08d91f2b7a2b1b883598170","src/codegen/math/float/abs.rs":"f56e2b4b8055ea861c1f5cbc6b6e1d8e7e5af163b62c13574ddee4e09513bfbc","src/codegen/math/float/cos.rs":"ef3b511a24d23045b310315e80348a9b7fedb576fc2de52d74290616a0abeb2a","src/codegen/math/float/cos_pi.rs":"4e7631a5d73dac21531e09ef1802d1180f8997509c2c8fa9f67f322194263a97","src/codegen/math/float/exp.rs":"61b691598c41b5622f24e4320c1bdd08701e612a516438bdddcc728fc3405c8c","src/codegen/math/float/ln.rs":"46b718b1ba8c9d99e1ad40f53d20dfde08a3063ca7bd2a9fdd6698e060da687e","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"a37bf764345d4b1714f97e83897b7cf0855fc2811704bcbc0012db91825339e1","src/codegen/math/float/mul_adde.rs":"9aa6ed39825e61edb2522e002c59c9392d7c655c01af1cf8380ba22c8ddf69cd","src/codegen/math/float/powf.rs":"642346e982bc4c39203de0864d2149c4179cd7b21cf67a2951687932b4675872","src/codegen/math/float/sin.rs":"9d68164c90cdca6a85155040cdac42e27342ebe0b925273ef1593df721af4258","src/codegen/math/float/sin_cos_pi.rs":"e0c661d1d894fd4018723b9f3143ab6771c9405e41907cb1a7b9f9b380a97523","src/codegen/math/float/sin_pi.rs":"9890347905b4d4a3c7341c3eb06406e46e60582bcf6960688bd727e5dadc6c57","src/codegen/math/float/sqrt.rs":"e3c60dcfb0c6d2fc62adabcc931b2d4040b83cab294dea36443fb4b89eb79e34","src/codegen/math/float/sqrte.rs":"f0f4ef9eb475ae41bcc7ec6a95ad744ba6b36925faa8b2c2814004396d196b63","src/codegen/pointer_sized_int.rs":"a70697169c28218b56fd2e8d5353f2e00671d1150d0c8cef77d613bdfacd84cb","src/codegen/reductions.rs":"645e2514746d01387ddd07f0aa4ffd8430cc9ab428d4fb13773ea319fa25dd95","src/codegen/reductions/mask.rs":"dd68fd8bc5335fa2d0405e59dd1e9fff16fdf7651aa8db670ca86145fd5b5dda","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"ac659780deb0c52daa9c73afb4ba8645c9fa35350cd897b23e567860492553b7","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"711c753a08d53a2879c4fb87a0762c46ce4e34c22f0ca88d2e4c557a0f679969","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"5efc09cb3d164e4e38b71fd4999afbfd234f5080dc84ce22fda2fc15d381e8c7","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"1d3a7862ef625e235a5734ad7204e68d350f902c0695182b1f08a0552432416e","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
++{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"e76b42f3247fccb7174046c499bfaae5430d83cadeb8140259fcae34613483cf","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"fa4dd64f66972217d35b7653338c9e2011ccd8f3008ae7c0103272d4287f9b1d","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"a766fba121243a9b617432c592873801adb74c3a2f4a24d9d45859b8ce9357fc","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"bb1795e9657a8298d37d2349b45443f08e9e455399ad4b727018600728478c10","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"db4f232fb9f5728db310b87dc8c4733be48afacab1053798c06106bef9a42b05","src/codegen/bit_manip.rs":"525ea6ff7ad1e043b6f6136992166f1803ed5563b7f6fc292c1c40257d20e264","src/codegen/llvm.rs":"b4ccbc0bad90038f00fc3c158736462d01d0053df3afa00f9169e67d1a264444","src/codegen/math.rs":"dfcf02ad34e2fdfe22c3f1cc2822001cc895e65031b4d06e585e5047839febb7","src/codegen/math/float.rs":"2c1cbce155bc527ce34d472c0fef6bc3dadb79cd7a357dd7aa5b1ebeb1d77a13","src/codegen/math/float/abs.rs":"d5aaadcf540bdb9b4264dca6471a255fd7bf509e763bef0239c0144a68466fea","src/codegen/math/float/cos.rs":"17f28d2900c852dca221fa9c92a9cd5fe7fd2df8d427bbc60216c749b2be013d","src/codegen/math/float/cos_pi.rs":"dbaf9f443f9846a491d4ec52210a7b5835dd593b03366e3135b05c37d70f9d6c","src/codegen/math/float/exp.rs":"d300058a4bcc7ae7976f216f81902cd73a9e603ad63880dff3bbc866c27a9f37","src/codegen/math/float/ln.rs":"c851e211e43f8256093ba75b03ae0c307c9962ee66d94f09b4dd80068190cbdf","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"041a5b69d5991d93ef795351b17560c10faf80b78fd26ad7df42a239b32cf9de","src/codegen/math/float/mul_adde.rs":"d71d5f0f3333b62a7439b823cb7adf5340ea1555ce820fb4a3f4cb922f73f5f5","src/codegen/math/float/powf.rs":"9742c3877f1a5509ca5c9492a40884b6579ba6dd11c26b7112e63f70666b395d","src/codegen/math/float/sin.rs":"0e9868d35531566509f3a01d85d5253045eb4afa8525d8407dcc1f5f33c56036","src/codegen/math/float/sin_cos_pi.rs":"8e6b6142d7dd240cdb36669722e82ab9810a2261e86e659f7d97a942ad8b1258","src/codegen/math/float/sin_pi.rs":"bb6d39db8f921e03a301fc5206ac1a61a97def8a2cb83b87ccf189f3fc48d548","src/codegen/math/float/sqrt.rs":"e6ebb0c5f428efad1f672b9a8fe4e58534dbf1ea5a8fe092ce5ce76b52fe89cb","src/codegen/math/float/sqrte.rs":"23acfaea38d0e081a6d9021c1094e813d0cfd12c58c1eca9662aade5e625d51c","src/codegen/pointer_sized_int.rs":"6ca13c214b6cf7e0929dbe18e96a16fc0bb7d8799608df29c4c8115490f99e01","src/codegen/reductions.rs":"8eb18ebac76985d2aa30262a2edd8cb004230b511a765d657525f677a585c12c","src/codegen/reductions/mask.rs":"e67f35a1f4d156a4894a2d6ea5a935b4d898cf70eefb2715f5c1cc165e776c11","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"c67c86e91ca3fc77539e0efcea081a3c62548cccf503963ae408f2e86f4e6a21","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"f0753b405cdc865bdf8e82c6505f299ea1f96136239ebbaf7f9ce93d310764b8","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"b6f846d5d30cf6b035a2d18039aba7b2045cf89384733d643572bd68873ae064","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"896669c08d8c801448a4d2fadc9d633eda0fbe879d229997e2a182e31278e469","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
+diff --git a/third_party/rust/packed_simd_2/Cargo.toml b/third_party/rust/packed_simd_2/Cargo.toml
+index f38706d05002e..49338742dc1ff 100644
+--- a/third_party/rust/packed_simd_2/Cargo.toml
++++ b/third_party/rust/packed_simd_2/Cargo.toml
+@@ -1,6 +1,6 @@
+ [package]
+ name = "packed_simd_2"
+-version = "0.3.7"
++version = "0.3.8"
+ description = "Portable Packed SIMD vectors"
+ documentation = "https://docs.rs/crate/packed_simd/"
+ homepage = "https://github.com/rust-lang/packed_simd"
+@@ -23,6 +23,9 @@ maintenance = { status = "experimental" }
+ cfg-if = "1.0.0"
+ core_arch = { version = "0.1.5", optional = true }
+
++[build-dependencies]
++rustc_version = "0.2"
++
+ [features]
+ default = []
+ into_bits = []
+diff --git a/third_party/rust/packed_simd_2/README.md b/third_party/rust/packed_simd_2/README.md
+index 41a1512d79fbc..eb3101c33d159 100644
+--- a/third_party/rust/packed_simd_2/README.md
++++ b/third_party/rust/packed_simd_2/README.md
+@@ -8,7 +8,7 @@ If you need to continue to use the crate, we have published a "next version" und
+
+ Adjust your `[dependencies]` section of `Cargo.toml` to be the following:
+ ```toml
+-packed_simd = { version = "0.3.6", package = "packed_simd_2" }
++packed_simd = { version = "0.3.8", package = "packed_simd_2" }
+ ```
+
+ # `Simd<[T; N]>`
+diff --git a/third_party/rust/packed_simd_2/build.rs b/third_party/rust/packed_simd_2/build.rs
+index e87298a2de237..afdee9f55b62b 100644
+--- a/third_party/rust/packed_simd_2/build.rs
++++ b/third_party/rust/packed_simd_2/build.rs
+@@ -1,6 +1,11 @@
++use rustc_version::{version, Version};
++
+ fn main() {
+ let target = std::env::var("TARGET").expect("TARGET environment variable not defined");
+ if target.contains("neon") {
+ println!("cargo:rustc-cfg=libcore_neon");
+ }
++ if version().unwrap() < Version::parse("1.61.0-alpha").unwrap() {
++ println!("cargo:rustc-cfg=aarch64_target_feature");
++ }
+ }
+diff --git a/third_party/rust/packed_simd_2/src/api.rs b/third_party/rust/packed_simd_2/src/api.rs
+index 4e9c4292e06ca..aa1403e6e243d 100644
+--- a/third_party/rust/packed_simd_2/src/api.rs
++++ b/third_party/rust/packed_simd_2/src/api.rs
+@@ -2,7 +2,7 @@
+
+ #[macro_use]
+ mod bitmask;
+-crate mod cast;
++pub(crate) mod cast;
+ #[macro_use]
+ mod cmp;
+ #[macro_use]
+@@ -37,7 +37,7 @@ mod swap_bytes;
+ mod bit_manip;
+
+ #[cfg(feature = "into_bits")]
+-crate mod into_bits;
++pub(crate) mod into_bits;
+
+ macro_rules! impl_i {
+ ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+diff --git a/third_party/rust/packed_simd_2/src/codegen.rs b/third_party/rust/packed_simd_2/src/codegen.rs
+index 9d1517e203d19..8a9e971486d74 100644
+--- a/third_party/rust/packed_simd_2/src/codegen.rs
++++ b/third_party/rust/packed_simd_2/src/codegen.rs
+@@ -1,19 +1,19 @@
+ //! Code-generation utilities
+
+-crate mod bit_manip;
+-crate mod llvm;
+-crate mod math;
+-crate mod reductions;
+-crate mod shuffle;
+-crate mod shuffle1_dyn;
+-crate mod swap_bytes;
++pub(crate) mod bit_manip;
++pub(crate) mod llvm;
++pub(crate) mod math;
++pub(crate) mod reductions;
++pub(crate) mod shuffle;
++pub(crate) mod shuffle1_dyn;
++pub(crate) mod swap_bytes;
+
+ macro_rules! impl_simd_array {
+ ([$elem_ty:ident; $elem_count:expr]:
+ $tuple_id:ident | $($elem_tys:ident),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id($(crate $elem_tys),*);
++ pub struct $tuple_id($(pub(crate) $elem_tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl crate::sealed::Seal for [$elem_ty; $elem_count] {}
+@@ -35,28 +35,28 @@ macro_rules! impl_simd_array {
+ }
+ }
+
+-crate mod pointer_sized_int;
++pub(crate) mod pointer_sized_int;
+
+-crate mod v16;
+-crate use self::v16::*;
++pub(crate) mod v16;
++pub(crate) use self::v16::*;
+
+-crate mod v32;
+-crate use self::v32::*;
++pub(crate) mod v32;
++pub(crate) use self::v32::*;
+
+-crate mod v64;
+-crate use self::v64::*;
++pub(crate) mod v64;
++pub(crate) use self::v64::*;
+
+-crate mod v128;
+-crate use self::v128::*;
++pub(crate) mod v128;
++pub(crate) use self::v128::*;
+
+-crate mod v256;
+-crate use self::v256::*;
++pub(crate) mod v256;
++pub(crate) use self::v256::*;
+
+-crate mod v512;
+-crate use self::v512::*;
++pub(crate) mod v512;
++pub(crate) use self::v512::*;
+
+-crate mod vSize;
+-crate use self::vSize::*;
++pub(crate) mod vSize;
++pub(crate) use self::vSize::*;
+
+-crate mod vPtr;
+-crate use self::vPtr::*;
++pub(crate) mod vPtr;
++pub(crate) use self::vPtr::*;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+index 5986916da4387..32d8d717a0766 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+@@ -1,7 +1,7 @@
+ //! LLVM bit manipulation intrinsics.
+ #[rustfmt::skip]
+
+-use crate::*;
++pub(crate) use crate::*;
+
+ #[allow(improper_ctypes, dead_code)]
+ extern "C" {
+@@ -147,7 +147,7 @@ extern "C" {
+ fn ctpop_u128x4(x: u128x4) -> u128x4;
+ }
+
+-crate trait BitManip {
++pub(crate) trait BitManip {
+ fn ctpop(self) -> Self;
+ fn ctlz(self) -> Self;
+ fn cttz(self) -> Self;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/llvm.rs b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+index 52b11a95b9172..b4c09849bc4a3 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/llvm.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+@@ -76,53 +76,53 @@ where
+ }
+
+ extern "platform-intrinsic" {
+- crate fn simd_eq<T, U>(x: T, y: T) -> U;
+- crate fn simd_ne<T, U>(x: T, y: T) -> U;
+- crate fn simd_lt<T, U>(x: T, y: T) -> U;
+- crate fn simd_le<T, U>(x: T, y: T) -> U;
+- crate fn simd_gt<T, U>(x: T, y: T) -> U;
+- crate fn simd_ge<T, U>(x: T, y: T) -> U;
+-
+- crate fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
+- crate fn simd_extract<T, U>(x: T, idx: u32) -> U;
+-
+- crate fn simd_cast<T, U>(x: T) -> U;
+-
+- crate fn simd_add<T>(x: T, y: T) -> T;
+- crate fn simd_sub<T>(x: T, y: T) -> T;
+- crate fn simd_mul<T>(x: T, y: T) -> T;
+- crate fn simd_div<T>(x: T, y: T) -> T;
+- crate fn simd_rem<T>(x: T, y: T) -> T;
+- crate fn simd_shl<T>(x: T, y: T) -> T;
+- crate fn simd_shr<T>(x: T, y: T) -> T;
+- crate fn simd_and<T>(x: T, y: T) -> T;
+- crate fn simd_or<T>(x: T, y: T) -> T;
+- crate fn simd_xor<T>(x: T, y: T) -> T;
+-
+- crate fn simd_reduce_add_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_min<T, U>(x: T) -> U;
+- crate fn simd_reduce_max<T, U>(x: T) -> U;
+- crate fn simd_reduce_min_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_max_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_and<T, U>(x: T) -> U;
+- crate fn simd_reduce_or<T, U>(x: T) -> U;
+- crate fn simd_reduce_xor<T, U>(x: T) -> U;
+- crate fn simd_reduce_all<T>(x: T) -> bool;
+- crate fn simd_reduce_any<T>(x: T) -> bool;
+-
+- crate fn simd_select<M, T>(m: M, a: T, b: T) -> T;
+-
+- crate fn simd_fmin<T>(a: T, b: T) -> T;
+- crate fn simd_fmax<T>(a: T, b: T) -> T;
+-
+- crate fn simd_fsqrt<T>(a: T) -> T;
+- crate fn simd_fma<T>(a: T, b: T, c: T) -> T;
+-
+- crate fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
+- crate fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
+-
+- crate fn simd_bitmask<T, U>(value: T) -> U;
++ pub(crate) fn simd_eq<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ne<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_lt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_le<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_gt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ge<T, U>(x: T, y: T) -> U;
++
++ pub(crate) fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
++ pub(crate) fn simd_extract<T, U>(x: T, idx: u32) -> U;
++
++ pub(crate) fn simd_cast<T, U>(x: T) -> U;
++
++ pub(crate) fn simd_add<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_sub<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_mul<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_div<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_rem<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shl<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shr<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_and<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_or<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_xor<T>(x: T, y: T) -> T;
++
++ pub(crate) fn simd_reduce_add_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_min<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_min_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_and<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_or<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_xor<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_all<T>(x: T) -> bool;
++ pub(crate) fn simd_reduce_any<T>(x: T) -> bool;
++
++ pub(crate) fn simd_select<M, T>(m: M, a: T, b: T) -> T;
++
++ pub(crate) fn simd_fmin<T>(a: T, b: T) -> T;
++ pub(crate) fn simd_fmax<T>(a: T, b: T) -> T;
++
++ pub(crate) fn simd_fsqrt<T>(a: T) -> T;
++ pub(crate) fn simd_fma<T>(a: T, b: T, c: T) -> T;
++
++ pub(crate) fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
++ pub(crate) fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
++
++ pub(crate) fn simd_bitmask<T, U>(value: T) -> U;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math.rs b/third_party/rust/packed_simd_2/src/codegen/math.rs
+index f3997c7f11359..9a0ea7a4e2d24 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math.rs
+@@ -1,3 +1,3 @@
+ //! Vertical math operations
+
+-crate mod float;
++pub(crate) mod float;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float.rs b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+index 5e89bf6ae6b0c..ffbf18bfe989d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+@@ -2,17 +2,17 @@
+ #![allow(clippy::useless_transmute)]
+
+ #[macro_use]
+-crate mod macros;
+-crate mod abs;
+-crate mod cos;
+-crate mod cos_pi;
+-crate mod exp;
+-crate mod ln;
+-crate mod mul_add;
+-crate mod mul_adde;
+-crate mod powf;
+-crate mod sin;
+-crate mod sin_cos_pi;
+-crate mod sin_pi;
+-crate mod sqrt;
+-crate mod sqrte;
++pub(crate) mod macros;
++pub(crate) mod abs;
++pub(crate) mod cos;
++pub(crate) mod cos_pi;
++pub(crate) mod exp;
++pub(crate) mod ln;
++pub(crate) mod mul_add;
++pub(crate) mod mul_adde;
++pub(crate) mod powf;
++pub(crate) mod sin;
++pub(crate) mod sin_cos_pi;
++pub(crate) mod sin_pi;
++pub(crate) mod sqrt;
++pub(crate) mod sqrte;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+index bc4421f61de2d..34aacc25be75a 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Abs {
++pub(crate) trait Abs {
+ fn abs(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+index 50f6c16da2555..dec390cb74d46 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Cos {
++pub(crate) trait Cos {
+ fn cos(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+index ebff5fd1c7510..e283280ee44b1 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait CosPi {
++pub(crate) trait CosPi {
+ fn cos_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+index 00d10e9fa6440..a7b20580e3f1e 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Exp {
++pub(crate) trait Exp {
+ fn exp(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+index 88a5a6c6c1589..a5e38cb40d1ed 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Ln {
++pub(crate) trait Ln {
+ fn ln(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+index f48a57dc46c69..d37f30fa86140 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+@@ -4,7 +4,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_add
+
+-crate trait MulAdd {
++pub(crate) trait MulAdd {
+ fn mul_add(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+index b030c26ccf465..c0baeacec20be 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+@@ -3,7 +3,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_adde
+
+-crate trait MulAddE {
++pub(crate) trait MulAddE {
+ fn mul_adde(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+index bc15067d73a30..89ca52e96d818 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Powf {
++pub(crate) trait Powf {
+ fn powf(self, x: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+index 7b014d07da8d9..d881415909afe 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sin {
++pub(crate) trait Sin {
+ fn sin(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+index 75c2c2c5fbb03..b283d11111fd5 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinCosPi: Sized {
++pub(crate) trait SinCosPi: Sized {
+ type Output;
+ fn sin_cos_pi(self) -> Self::Output;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+index 72df98c93c91e..0c8f6bb120503 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinPi {
++pub(crate) trait SinPi {
+ fn sin_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+index 7ce31df626621..67bb0a2a9c594 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sqrt {
++pub(crate) trait Sqrt {
+ fn sqrt(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+index c1e379c34241f..58a1de1f400f9 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+@@ -6,7 +6,7 @@
+ use crate::llvm::simd_fsqrt;
+ use crate::*;
+
+-crate trait Sqrte {
++pub(crate) trait Sqrte {
+ fn sqrte(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+index 39f493d3b17f0..55cbc297aaf52 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+@@ -4,24 +4,24 @@ use cfg_if::cfg_if;
+
+ cfg_if! {
+ if #[cfg(target_pointer_width = "8")] {
+- crate type isize_ = i8;
+- crate type usize_ = u8;
++ pub(crate) type isize_ = i8;
++ pub(crate) type usize_ = u8;
+ } else if #[cfg(target_pointer_width = "16")] {
+- crate type isize_ = i16;
+- crate type usize_ = u16;
++ pub(crate) type isize_ = i16;
++ pub(crate) type usize_ = u16;
+ } else if #[cfg(target_pointer_width = "32")] {
+- crate type isize_ = i32;
+- crate type usize_ = u32;
++ pub(crate) type isize_ = i32;
++ pub(crate) type usize_ = u32;
+
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "128")] {
+- crate type isize_ = i128;
+- crate type usize_ = u128;
++ pub(crate) type isize_ = i128;
++ pub(crate) type usize_ = u128;
+ } else {
+ compile_error!("unsupported target_pointer_width");
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions.rs b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+index 7be4f5fabbea9..302ca6d88f33d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+@@ -1 +1 @@
+-crate mod mask;
++pub(crate) mod mask;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+index 0aec60969b864..a78bcc5632672 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+@@ -7,11 +7,11 @@
+
+ use crate::*;
+
+-crate trait All: crate::marker::Sized {
++pub(crate) trait All: crate::marker::Sized {
+ unsafe fn all(self) -> bool;
+ }
+
+-crate trait Any: crate::marker::Sized {
++pub(crate) trait Any: crate::marker::Sized {
+ unsafe fn any(self) -> bool;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+index a4435e3c35354..9cf34a3e0401c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SwapBytes {
++pub(crate) trait SwapBytes {
+ fn swap_bytes(self) -> Self;
+ }
+
+@@ -15,7 +15,7 @@ macro_rules! impl_swap_bytes {
+ impl SwapBytes for $id {
+ #[inline]
+ fn swap_bytes(self) -> Self {
+- unsafe { shuffle!(self, [1, 0]) }
++ shuffle!(self, [1, 0])
+ }
+ }
+ )+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+index cf4765538178d..abd3aa877920c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+@@ -5,7 +5,7 @@ macro_rules! impl_simd_ptr {
+ | $($tys:ty),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id<$ty>($(crate $tys),*);
++ pub struct $tuple_id<$ty>($(pub(crate) $tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl<$ty> crate::sealed::Seal for [$ptr_ty; $elem_count] {}
+diff --git a/third_party/rust/packed_simd_2/src/lib.rs b/third_party/rust/packed_simd_2/src/lib.rs
+index 840bae38d6a30..cd8a86805dd59 100644
+--- a/third_party/rust/packed_simd_2/src/lib.rs
++++ b/third_party/rust/packed_simd_2/src/lib.rs
+@@ -217,14 +217,13 @@
+ rustc_attrs,
+ platform_intrinsics,
+ stdsimd,
+- aarch64_target_feature,
+ arm_target_feature,
+ link_llvm_intrinsics,
+ core_intrinsics,
+ stmt_expr_attributes,
+- crate_visibility_modifier,
+ custom_inner_attributes,
+ )]
++#![cfg_attr(aarch64_target_feature, feature(aarch64_target_feature))]
+ #![allow(non_camel_case_types, non_snake_case,
+ // FIXME: these types are unsound in C FFI already
+ // See https://github.com/rust-lang/rust/issues/53346
+@@ -344,6 +343,6 @@ pub use self::codegen::llvm::{
+ __shuffle_vector8,
+ };
+
+-crate mod llvm {
+- crate use crate::codegen::llvm::*;
++pub(crate) mod llvm {
++ pub(crate) use crate::codegen::llvm::*;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/testing.rs b/third_party/rust/packed_simd_2/src/testing.rs
+index fcbcf9e2ac8eb..6320b28055569 100644
+--- a/third_party/rust/packed_simd_2/src/testing.rs
++++ b/third_party/rust/packed_simd_2/src/testing.rs
+@@ -5,4 +5,4 @@ mod macros;
+
+ #[cfg(test)]
+ #[macro_use]
+-crate mod utils;
++pub(crate) mod utils;
diff --git a/srcpkgs/firefox-esr/patches/fix-cbindgen.patch b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
new file mode 100644
index 000000000000..ba3ce7ae3e97
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
@@ -0,0 +1,22 @@
+Fix error with new cbindgen:
+
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi_generated.h:24:33: error: redefinition of 'constexpr const uint64_t mozilla::wr::ROOT_CLIP_CHAIN'
+ 24 | constexpr static const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi.h:76:16: note: 'const uint64_t mozilla::wr::ROOT_CLIP_CHAIN' previously defined here
+ 76 | const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+
+diff --git a/gfx/webrender_bindings/webrender_ffi.h b/gfx/webrender_bindings/webrender_ffi.h
+index b1d67b17a4bde..eb79974bdf434 100644
+--- a/gfx/webrender_bindings/webrender_ffi.h
++++ b/gfx/webrender_bindings/webrender_ffi.h
+@@ -73,8 +73,6 @@ struct WrPipelineInfo;
+ struct WrPipelineIdAndEpoch;
+ using WrPipelineIdEpochs = nsTArray<WrPipelineIdAndEpoch>;
+
+-const uint64_t ROOT_CLIP_CHAIN = ~0;
+-
+ } // namespace wr
+ } // namespace mozilla
+
diff --git a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
similarity index 64%
rename from srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
rename to srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
index c4664d3da7ce..3f0273cba366 100644
--- a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
+++ b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
@@ -1,6 +1,6 @@
---- a/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:31:39.428839442 +0100
-+++ b/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:32:20.689063456 +0100
-@@ -154,7 +154,7 @@
+--- a/taskcluster/docker/firefox-snap/firefox.desktop
++++ b/taskcluster/docker/firefox-snap/firefox.desktop
+@@ -154,11 +154,12 @@
Terminal=false
X-MultipleArgs=false
Type=Application
@@ -9,3 +9,8 @@
Categories=GNOME;GTK;Network;WebBrowser;
MimeType=text/html;text/xml;application/xhtml+xml;application/xml;application/rss+xml;application/rdf+xml;image/gif;image/jpeg;image/png;x-scheme-handler/http;x-scheme-handler/https;x-scheme-handler/ftp;x-scheme-handler/chrome;video/webm;application/x-xpinstall;
StartupNotify=true
+ Actions=NewWindow;NewPrivateWindow;
++StartupWMClass=Firefox
+
+ [Desktop Action NewWindow]
+ Name=Open a New Window
diff --git a/srcpkgs/firefox-esr/patches/fix-tools.patch b/srcpkgs/firefox-esr/patches/fix-tools.patch
deleted file mode 100644
index 94de423ce593..000000000000
--- a/srcpkgs/firefox-esr/patches/fix-tools.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:09:40.980448579 +0100
-+++ b/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:11:09.689590967 +0100
-@@ -497,8 +501,10 @@
- ucontext_t sSyncUContext;
-
- void Registers::SyncPopulate() {
-+#if defined(__GLIBC__)
- if (!getcontext(&sSyncUContext)) {
- PopulateRegsFromContext(*this, &sSyncUContext);
- }
-+#endif
- }
- #endif
diff --git a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
index 5d17021a99f4..4f9043b58e1e 100644
--- a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
+++ b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
@@ -1,20 +1,20 @@
---- a/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:20:52.298793223 +0100
-+++ b/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:21:48.250250850 +0100
-@@ -14,7 +14,7 @@
- #ifndef __GLIBC_PREREQ
- #define __GLIBC_PREREQ(a, b) 0
+--- a/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
++++ b/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
+@@ -18,7 +18,7 @@
+ #define WEBRTC_GLIBC_PREREQ(a, b) 0
#endif
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
#include <sys/auxv.h>
#else
- #include <fcntl.h>
-@@ -32,7 +32,7 @@
+ #include <errno.h>
+@@ -40,7 +40,7 @@
int architecture = 0;
- unsigned long hwcap = 0;
+ uint64_t hwcap = 0;
const char* platform = NULL;
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
hwcap = getauxval(AT_HWCAP);
platform = (const char*)getauxval(AT_PLATFORM);
#else
diff --git a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch b/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
deleted file mode 100644
index cced0058e8e1..000000000000
--- a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
+++ /dev/null
@@ -1,3441 +0,0 @@
-diff --git a/config/check_macroassembler_style.py b/config/check_macroassembler_style.py
-index 0d040a939b..b83e3691dd 100644
---- a/config/check_macroassembler_style.py
-+++ b/config/check_macroassembler_style.py
-@@ -24,17 +24,17 @@ from __future__ import absolute_import
- from __future__ import print_function
-
- import difflib
- import os
- import re
- import sys
-
- architecture_independent = set(["generic"])
--all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared"])
-+all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared", "ppc64"])
- all_architecture_names = set(["x86", "x64", "arm", "arm64"])
- all_shared_architecture_names = set(["x86_shared", "arm", "arm64"])
-
- reBeforeArg = "(?<=[(,\s])"
- reArgType = "(?P<type>[\w\s:*&]+)"
- reArgName = "(?P<name>\s\w+)"
- reArgDefault = "(?P<default>(?:\s=[^,)]+)?)"
- reAfterArg = "(?=[,)])"
-diff --git a/js/moz.configure b/js/moz.configure
-index 3c3d0d4359..b217d0e15c 100644
---- a/js/moz.configure
-+++ b/js/moz.configure
-@@ -214,23 +214,25 @@ def jit_codegen(jit_enabled, simulator, target):
- return namespace(**{str(target.cpu): True})
-
-
- set_config("JS_CODEGEN_NONE", jit_codegen.none)
- set_config("JS_CODEGEN_ARM", jit_codegen.arm)
- set_config("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_config("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_config("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_config("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_config("JS_CODEGEN_X86", jit_codegen.x86)
- set_config("JS_CODEGEN_X64", jit_codegen.x64)
- set_define("JS_CODEGEN_NONE", jit_codegen.none)
- set_define("JS_CODEGEN_ARM", jit_codegen.arm)
- set_define("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_define("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_define("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_define("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_define("JS_CODEGEN_X86", jit_codegen.x86)
- set_define("JS_CODEGEN_X64", jit_codegen.x64)
-
- # Profiling
- # =======================================================
- option(
- "--enable-instruments",
- env="MOZ_INSTRUMENTS",
-diff --git a/js/src/irregexp/RegExpNativeMacroAssembler.cpp b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-index e0ef7e64f5..81d8e2a198 100644
---- a/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-+++ b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-@@ -813,18 +813,33 @@ void SMRegExpMacroAssembler::JumpOrBacktrack(Label* to) {
- // If the test fails, call an OOL handler to try growing the stack.
- void SMRegExpMacroAssembler::CheckBacktrackStackLimit() {
- js::jit::Label no_stack_overflow;
- masm_.branchPtr(
- Assembler::BelowOrEqual,
- AbsoluteAddress(isolate()->regexp_stack()->limit_address_address()),
- backtrack_stack_pointer_, &no_stack_overflow);
-
-+#ifdef JS_CODEGEN_PPC64
-+ // LR on PowerPC isn't a GPR, so we have to explicitly save it here before
-+ // we call or we will end up erroneously returning after the call to the
-+ // stack overflow handler when we |blr| out and inevitably underflow the
-+ // irregexp stack on the next backtrack.
-+ masm_.xs_mflr(temp1_);
-+ masm_.as_stdu(temp1_, masm_.getStackPointer(), -8);
-+#endif
-+
- masm_.call(&stack_overflow_label_);
-
-+#ifdef JS_CODEGEN_PPC64
-+ masm_.as_ld(temp1_, masm_.getStackPointer(), 0);
-+ masm_.xs_mtlr(temp1_);
-+ masm_.as_addi(masm_.getStackPointer(), masm_.getStackPointer(), 8);
-+#endif
-+
- // Exit with an exception if the call failed
- masm_.branchTest32(Assembler::Zero, temp0_, temp0_,
- &exit_with_exception_label_);
-
- masm_.bind(&no_stack_overflow);
- }
-
- // This is used to sneak an OOM through the V8 layer.
-@@ -1127,16 +1142,20 @@ void SMRegExpMacroAssembler::stackOverflowHandler() {
- LiveGeneralRegisterSet volatileRegs(GeneralRegisterSet::Volatile());
-
- #ifdef JS_USE_LINK_REGISTER
- masm_.pushReturnAddress();
- #endif
-
- // Adjust for the return address on the stack.
- size_t frameOffset = sizeof(void*);
-+#ifdef JS_CODEGEN_PPC64
-+ // We have a double return address.
-+ frameOffset += sizeof(void*);
-+#endif
-
- volatileRegs.takeUnchecked(temp0_);
- volatileRegs.takeUnchecked(temp1_);
- masm_.PushRegsInMask(volatileRegs);
-
- using Fn = bool (*)(RegExpStack * regexp_stack);
- masm_.setupUnalignedABICall(temp0_);
- masm_.passABIArg(temp1_);
-diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h
-index f4a5727d05..138612d53b 100644
---- a/js/src/jit/AtomicOperations.h
-+++ b/js/src/jit/AtomicOperations.h
-@@ -373,19 +373,26 @@ constexpr inline bool AtomicOperations::isLockfreeJS(int32_t size) {
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- # endif
- #elif defined(__mips__)
- # if defined(__clang__) || defined(__GNUC__)
- # include "jit/mips-shared/AtomicOperations-mips-shared.h"
- # else
- # error "AtomicOperations on MIPS for an unknown compiler"
- # endif
-+#elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-+ defined(__PPC64LE__)
-+# if defined(JS_CODEGEN_PPC64)
-+/* XXX: should be # include "jit/shared/AtomicOperations-shared-jit.h" */
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# else
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# endif
- #elif defined(__ppc__) || defined(__PPC__) || defined(__sparc__) || \
-- defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-- defined(__PPC64LE__) || defined(__alpha__) || defined(__hppa__) || \
-+ defined(__alpha__) || defined(__hppa__) || \
- defined(__sh__) || defined(__s390__) || defined(__s390x__) || \
- defined(__m68k__) || defined(__riscv) || defined(__wasi__)
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- #else
- # error "No AtomicOperations support provided for this platform"
- #endif
-
- #endif // jit_AtomicOperations_h
-diff --git a/js/src/jit/BaselineBailouts.cpp b/js/src/jit/BaselineBailouts.cpp
-index bca1427f93..eb499b34cf 100644
---- a/js/src/jit/BaselineBailouts.cpp
-+++ b/js/src/jit/BaselineBailouts.cpp
-@@ -481,16 +481,21 @@ class MOZ_STACK_CLASS BaselineStackBuilder {
- // let X = STACK_START_ADDR + JitFrameLayout::Size() + PREV_FRAME_SIZE
- // X + RectifierFrameLayout::Size()
- // + ((RectifierFrameLayout*) X)->prevFrameLocalSize()
- // - BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr()
- size_t extraOffset =
- RectifierFrameLayout::Size() + priorFrame->prevFrameLocalSize() +
- BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr();
- return virtualPointerAtStackOffset(priorOffset + extraOffset);
-+#elif defined(JS_CODEGEN_PPC64)
-+ (void)priorOffset;
-+// XXX. The above code might work though
-+#warning "TODO! BaselineStackBuilder::calculatePrevFramePtr()"
-+ MOZ_CRASH();
- #elif defined(JS_CODEGEN_NONE)
- (void)priorOffset;
- MOZ_CRASH();
- #else
- # error "Bad architecture!"
- #endif
- }
- };
-diff --git a/js/src/jit/BaselineCodeGen.cpp b/js/src/jit/BaselineCodeGen.cpp
-index 7089f5e300..d67236d2c5 100644
---- a/js/src/jit/BaselineCodeGen.cpp
-+++ b/js/src/jit/BaselineCodeGen.cpp
-@@ -520,16 +520,19 @@ bool BaselineCodeGen<Handler>::emitOutOfLinePostBarrierSlot() {
- regs.take(BaselineFrameReg);
- Register scratch = regs.takeAny();
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // On ARM, save the link register before calling. It contains the return
- // address. The |masm.ret()| later will pop this into |pc| to return.
- masm.push(lr);
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- masm.push(ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.xs_mflr(ScratchRegister);
-+ masm.push(ScratchRegister);
- #endif
- masm.pushValue(R0);
-
- using Fn = void (*)(JSRuntime * rt, js::gc::Cell * cell);
- masm.setupUnalignedABICall(scratch);
- masm.movePtr(ImmPtr(cx->runtime()), scratch);
- masm.passABIArg(scratch);
- masm.passABIArg(objReg);
-diff --git a/js/src/jit/BaselineIC.cpp b/js/src/jit/BaselineIC.cpp
-index 9572394e76..dfe762e5c8 100644
---- a/js/src/jit/BaselineIC.cpp
-+++ b/js/src/jit/BaselineIC.cpp
-@@ -127,17 +127,18 @@ class MOZ_RAII FallbackICCodeCompiler final {
- };
-
- AllocatableGeneralRegisterSet BaselineICAvailableGeneralRegs(size_t numInputs) {
- AllocatableGeneralRegisterSet regs(GeneralRegisterSet::All());
- #if defined(JS_CODEGEN_ARM)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- regs.take(BaselineSecondScratchReg);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- MOZ_ASSERT(!regs.has(BaselineSecondScratchReg));
- #elif defined(JS_CODEGEN_ARM64)
- MOZ_ASSERT(!regs.has(PseudoStackPointer));
- MOZ_ASSERT(!regs.has(RealStackPointer));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- #else
-diff --git a/js/src/jit/CodeGenerator.h b/js/src/jit/CodeGenerator.h
-index 5321978fc2..b2d9a8f5a5 100644
---- a/js/src/jit/CodeGenerator.h
-+++ b/js/src/jit/CodeGenerator.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/CodeGenerator-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/CodeGenerator-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/CodeGenerator-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/CodeGenerator-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/CodeGenerator-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/CodeGenerator-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmGC.h"
-
-diff --git a/js/src/jit/FlushICache.h b/js/src/jit/FlushICache.h
-index fe66080df5..2071563c1e 100644
---- a/js/src/jit/FlushICache.h
-+++ b/js/src/jit/FlushICache.h
-@@ -19,17 +19,18 @@ namespace jit {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- // No-op. Code and data caches are coherent on x86 and x64.
- }
-
- #elif (defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)) || \
-- (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64))
-+ (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)) || \
-+ defined(JS_CODEGEN_PPC64)
-
- extern void FlushICache(void* code, size_t size, bool codeIsThreadLocal = true);
-
- #elif defined(JS_CODEGEN_NONE)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- MOZ_CRASH();
-diff --git a/js/src/jit/JitFrames.cpp b/js/src/jit/JitFrames.cpp
-index 77cfe6a9cd..507f1551e6 100644
---- a/js/src/jit/JitFrames.cpp
-+++ b/js/src/jit/JitFrames.cpp
-@@ -2220,16 +2220,24 @@ MachineState MachineState::FromBailout(RegisterDump::GPRArray& regs,
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Single),
- &fpregs[i]);
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Double),
- &fpregs[i]);
- // No SIMD support in bailouts, SIMD is internal to wasm
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
-+ machine.setRegisterLocation(FloatRegister(i), &fpregs[i]);
-+# ifdef ENABLE_WASM_SIMD
-+ // Needs additional handling if VMX or non-FPR VSX regs are in play.
-+# error "SIMD for PPC NYI"
-+# endif
-+ }
-
- #elif defined(JS_CODEGEN_NONE)
- MOZ_CRASH();
- #else
- # error "Unknown architecture!"
- #endif
- return machine;
- }
-diff --git a/js/src/jit/JitFrames.h b/js/src/jit/JitFrames.h
-index 40c661d146..7b4ea3157d 100644
---- a/js/src/jit/JitFrames.h
-+++ b/js/src/jit/JitFrames.h
-@@ -152,16 +152,26 @@ struct ResumeFromException {
- static const uint32_t RESUME_ENTRY_FRAME = 0;
- static const uint32_t RESUME_CATCH = 1;
- static const uint32_t RESUME_FINALLY = 2;
- static const uint32_t RESUME_FORCED_RETURN = 3;
- static const uint32_t RESUME_BAILOUT = 4;
- static const uint32_t RESUME_WASM = 5;
- static const uint32_t RESUME_WASM_CATCH = 6;
-
-+#if defined(JS_CODEGEN_PPC64)
-+ // This gets built on the stack as part of exception returns. Because
-+ // it goes right on top of the stack, an ABI-compliant routine can wreck
-+ // it, so we implement a minimum Power ISA linkage area (four doublewords).
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
-+
- uint8_t* framePointer;
- uint8_t* stackPointer;
- uint8_t* target;
- uint32_t kind;
-
- // Value to push when resuming into a |finally| block.
- // Also used by Wasm to send the exception object to the throw stub.
- JS::Value exception;
-diff --git a/js/src/jit/JitOptions.cpp b/js/src/jit/JitOptions.cpp
-index de13777fc3..795e41bf21 100644
---- a/js/src/jit/JitOptions.cpp
-+++ b/js/src/jit/JitOptions.cpp
-@@ -132,17 +132,22 @@ DefaultJitOptions::DefaultJitOptions() {
- // Warp compile Generator functions
- SET_DEFAULT(warpGenerator, true);
-
- // Whether the IonMonkey and Baseline JITs are enabled for Trusted Principals.
- // (Ignored if ion or baselineJit is set to true.)
- SET_DEFAULT(jitForTrustedPrincipals, false);
-
- // Whether the RegExp JIT is enabled.
-+#if defined(JS_CODEGEN_PPC64)
-+ // This may generate ISA 3 instructions. The other JIT tiers gate on it too.
-+ SET_DEFAULT(nativeRegExp, MacroAssembler::SupportsFloatingPoint());
-+#else
- SET_DEFAULT(nativeRegExp, true);
-+#endif
-
- // Whether Warp should use ICs instead of transpiling Baseline CacheIR.
- SET_DEFAULT(forceInlineCaches, false);
-
- // Whether all ICs should be initialized as megamorphic ICs.
- SET_DEFAULT(forceMegamorphicICs, false);
-
- // Toggles whether large scripts are rejected.
-diff --git a/js/src/jit/LIR.h b/js/src/jit/LIR.h
-index 024bd798ca..0cd43c12ab 100644
---- a/js/src/jit/LIR.h
-+++ b/js/src/jit/LIR.h
-@@ -1939,16 +1939,18 @@ AnyRegister LAllocation::toRegister() const {
- # include "jit/arm64/LIR-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/LIR-mips32.h"
- # elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/LIR-mips64.h"
- # endif
- # include "jit/mips-shared/LIR-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/LIR-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/LIR-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #undef LIR_HEADER
-
-diff --git a/js/src/jit/Label.h b/js/src/jit/Label.h
-index a8f93de378..480b18b251 100644
---- a/js/src/jit/Label.h
-+++ b/js/src/jit/Label.h
-@@ -21,17 +21,18 @@ struct LabelBase {
- uint32_t bound_ : 1;
-
- // offset_ < INVALID_OFFSET means that the label is either bound or has
- // incoming uses and needs to be bound.
- uint32_t offset_ : 31;
-
- void operator=(const LabelBase& label) = delete;
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- public:
- #endif
- static const uint32_t INVALID_OFFSET = 0x7fffffff; // UINT31_MAX.
-
- public:
- LabelBase() : bound_(false), offset_(INVALID_OFFSET) {}
-
- // If the label is bound, all incoming edges have been patched and any
-diff --git a/js/src/jit/Lowering.h b/js/src/jit/Lowering.h
-index 979687da85..c064e5d914 100644
---- a/js/src/jit/Lowering.h
-+++ b/js/src/jit/Lowering.h
-@@ -18,16 +18,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Lowering-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Lowering-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Lowering-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Lowering-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Lowering-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Lowering-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler-inl.h b/js/src/jit/MacroAssembler-inl.h
-index cf16cdf0a7..fa39c5f4d2 100644
---- a/js/src/jit/MacroAssembler-inl.h
-+++ b/js/src/jit/MacroAssembler-inl.h
-@@ -30,16 +30,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32-inl.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64-inl.h"
- #elif !defined(JS_CODEGEN_NONE)
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmBuiltins.h"
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler.cpp b/js/src/jit/MacroAssembler.cpp
-index 2a3aeec607..cbe9d14f46 100644
---- a/js/src/jit/MacroAssembler.cpp
-+++ b/js/src/jit/MacroAssembler.cpp
-@@ -4044,16 +4044,18 @@ void MacroAssembler::emitPreBarrierFastPath(JSRuntime* rt, MIRType type,
- #elif JS_CODEGEN_ARM
- ma_lsl(temp3, temp1, temp1);
- #elif JS_CODEGEN_ARM64
- Lsl(ARMRegister(temp1, 64), ARMRegister(temp1, 64), ARMRegister(temp3, 64));
- #elif JS_CODEGEN_MIPS32
- ma_sll(temp1, temp1, temp3);
- #elif JS_CODEGEN_MIPS64
- ma_dsll(temp1, temp1, temp3);
-+#elif JS_CODEGEN_PPC64
-+ as_sld(temp1, temp1, temp3);
- #elif JS_CODEGEN_NONE
- MOZ_CRASH();
- #else
- # error "Unknown architecture"
- #endif
-
- // No barrier is needed if the bit is set, |word & mask != 0|.
- branchTestPtr(Assembler::NonZero, temp2, temp1, noBarrier);
-diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h
-index e2d53d5cef..cb0148b94e 100644
---- a/js/src/jit/MacroAssembler.h
-+++ b/js/src/jit/MacroAssembler.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MacroAssembler-none.h"
- #else
- # error "Unknown architecture!"
- #endif
- #include "jit/ABIFunctions.h"
- #include "jit/AtomicOp.h"
- #include "jit/AutoJitContextAlloc.h"
-@@ -87,18 +89,18 @@
- // //{{{ check_macroassembler_style
- // inline uint32_t
- // MacroAssembler::framePushed() const
- // {
- // return framePushed_;
- // }
- // ////}}} check_macroassembler_style
-
--#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64
--#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared
-+#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64, ppc64
-+#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared, ppc64
-
- // * How this macro works:
- //
- // DEFINED_ON is a macro which check if, for the current architecture, the
- // method is defined on the macro assembler or not.
- //
- // For each architecture, we have a macro named DEFINED_ON_arch. This macro is
- // empty if this is not the current architecture. Otherwise it must be either
-@@ -134,16 +136,17 @@
- #define DEFINED_ON_x86
- #define DEFINED_ON_x64
- #define DEFINED_ON_x86_shared
- #define DEFINED_ON_arm
- #define DEFINED_ON_arm64
- #define DEFINED_ON_mips32
- #define DEFINED_ON_mips64
- #define DEFINED_ON_mips_shared
-+#define DEFINED_ON_ppc64
- #define DEFINED_ON_none
-
- // Specialize for each architecture.
- #if defined(JS_CODEGEN_X86)
- # undef DEFINED_ON_x86
- # define DEFINED_ON_x86 define
- # undef DEFINED_ON_x86_shared
- # define DEFINED_ON_x86_shared define
-@@ -163,16 +166,19 @@
- # define DEFINED_ON_mips32 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
- #elif defined(JS_CODEGEN_MIPS64)
- # undef DEFINED_ON_mips64
- # define DEFINED_ON_mips64 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
-+#elif defined(JS_CODEGEN_PPC64)
-+# undef DEFINED_ON_ppc64
-+# define DEFINED_ON_ppc64 define
- #elif defined(JS_CODEGEN_NONE)
- # undef DEFINED_ON_none
- # define DEFINED_ON_none crash
- #else
- # error "Unknown architecture!"
- #endif
-
- #define DEFINED_ON_RESULT_crash \
-@@ -479,36 +485,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // targets roll their own save-code instead.
- //
- // Nevertheless, because some targets *do* call PushRegsInMask from
- // JitRuntime::generateInvalidator, you should check carefully all of the
- // ::generateInvalidator methods if you change the PushRegsInMask format.
-
- // The size of the area used by PushRegsInMask.
- size_t PushRegsInMaskSizeInBytes(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PushRegsInMask(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- void PushRegsInMask(LiveGeneralRegisterSet set);
-
- // Like PushRegsInMask, but instead of pushing the registers, store them to
- // |dest|. |dest| should point to the end of the reserved space, so the
- // first register will be stored at |dest.offset - sizeof(register)|. It is
- // required that |dest.offset| is at least as large as the value computed by
- // PushRegsInMaskSizeInBytes for this |set|. In other words, |dest.base|
- // must point to either the lowest address in the save area, or some address
- // below that.
- void storeRegsInMask(LiveRegisterSet set, Address dest, Register scratch)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PopRegsInMask(LiveRegisterSet set);
- void PopRegsInMask(LiveGeneralRegisterSet set);
- void PopRegsInMaskIgnore(LiveRegisterSet set, LiveRegisterSet ignore)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // ===============================================================
- // Stack manipulation functions -- single registers/values.
-
- void Push(const Operand op) DEFINED_ON(x86_shared);
- void Push(Register reg) PER_SHARED_ARCH;
- void Push(Register reg1, Register reg2, Register reg3, Register reg4)
- DEFINED_ON(arm64);
-@@ -531,17 +537,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline CodeOffset PushWithPatch(ImmWord word);
- inline CodeOffset PushWithPatch(ImmPtr imm);
-
- void Pop(const Operand op) DEFINED_ON(x86_shared);
- void Pop(Register reg) PER_SHARED_ARCH;
- void Pop(FloatRegister t) PER_SHARED_ARCH;
- void Pop(const ValueOperand& val) PER_SHARED_ARCH;
- void PopFlags() DEFINED_ON(x86_shared);
-- void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared);
-+ void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared, ppc64);
- void popRooted(VMFunctionData::RootType rootType, Register cellReg,
- const ValueOperand& valueReg);
-
- // Move the stack pointer based on the requested amount.
- void adjustStack(int amount);
- void freeStack(uint32_t amount);
-
- // Warning: This method does not update the framePushed() counter.
-@@ -589,18 +595,18 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Push the return address and make a call. On platforms where this function
- // is not defined, push the link register (pushReturnAddress) at the entry
- // point of the callee.
- void callAndPushReturnAddress(Register reg) DEFINED_ON(x86_shared);
- void callAndPushReturnAddress(Label* label) DEFINED_ON(x86_shared);
-
- // These do not adjust framePushed().
-- void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-- void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-+ void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-+ void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-
- // Useful for dealing with two-valued returns.
- void moveRegPair(Register src0, Register src1, Register dst0, Register dst1,
- MoveOp::Type type = MoveOp::GENERAL);
-
- public:
- // ===============================================================
- // Patchable near/far jumps.
-@@ -621,20 +627,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // These methods are like movWithPatch/PatchDataWithValueCheck but allow
- // using pc-relative addressing on certain platforms (RIP-relative LEA on x64,
- // ADR instruction on arm64).
- //
- // Note: "Near" applies to ARM64 where the target must be within 1 MB (this is
- // release-asserted).
- CodeOffset moveNearAddressWithPatch(Register dest)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
- static void patchNearAddressMove(CodeLocationLabel loc,
- CodeLocationLabel target)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
-
- public:
- // ===============================================================
- // [SMDOC] JIT-to-C++ Function Calls (callWithABI)
- //
- // callWithABI is used to make a call using the standard C/C++ system ABI.
- //
- // callWithABI is a low level interface for making calls, as such every call
-@@ -983,20 +989,21 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void xor32(Imm32 imm, Register dest) PER_SHARED_ARCH;
- inline void xor32(Imm32 imm, const Address& dest) PER_SHARED_ARCH;
- inline void xor32(const Address& src, Register dest) PER_SHARED_ARCH;
-
- inline void xorPtr(Register src, Register dest) PER_ARCH;
- inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
-
- inline void and64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-- inline void or64(const Operand& src, Register64 dest) DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-+ inline void or64(const Operand& src, Register64 dest)
-+ DEFINED_ON(x64, mips64, ppc64);
- inline void xor64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- // ===============================================================
- // Swap instructions
-
- // Swap the two lower bytes and sign extend the result to 32-bit.
- inline void byteSwap16SignExtend(Register reg) PER_SHARED_ARCH;
-
- // Swap the two lower bytes and zero extend the result to 32-bit.
-@@ -1020,27 +1027,27 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addPtr(Register src, Register dest) PER_ARCH;
- inline void addPtr(Register src1, Register src2, Register dest)
- DEFINED_ON(arm64);
- inline void addPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void addPtr(Imm32 imm, Register src, Register dest) DEFINED_ON(arm64);
- inline void addPtr(ImmWord imm, Register dest) PER_ARCH;
- inline void addPtr(ImmPtr imm, Register dest);
- inline void addPtr(Imm32 imm, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void addPtr(Imm32 imm, const AbsoluteAddress& dest)
- DEFINED_ON(x86, x64);
- inline void addPtr(const Address& src, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void add64(Register64 src, Register64 dest) PER_ARCH;
- inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
- inline void add64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void add64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void addFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- // Compute dest=SP-imm where dest is a pointer registers and not SP. The
- // offset returned from sub32FromStackPtrWithPatch() must be passed to
- // patchSub32FromStackPtr().
- inline CodeOffset sub32FromStackPtrWithPatch(Register dest) PER_ARCH;
- inline void patchSub32FromStackPtr(CodeOffset offset, Imm32 imm) PER_ARCH;
-@@ -1049,58 +1056,58 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addConstantDouble(double d, FloatRegister dest) DEFINED_ON(x86);
-
- inline void sub32(const Address& src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Register src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Imm32 imm, Register dest) PER_SHARED_ARCH;
-
- inline void subPtr(Register src, Register dest) PER_ARCH;
- inline void subPtr(Register src, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void subPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
- inline void subPtr(const Address& addr, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void sub64(Register64 src, Register64 dest) PER_ARCH;
- inline void sub64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void sub64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void subFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void subDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mul32(Register rhs, Register srcDest) PER_SHARED_ARCH;
-
- inline void mul32(Register src1, Register src2, Register dest, Label* onOver)
- DEFINED_ON(arm64);
-
- inline void mulPtr(Register rhs, Register srcDest) PER_ARCH;
-
- inline void mul64(const Operand& src, const Register64& dest) DEFINED_ON(x64);
- inline void mul64(const Operand& src, const Register64& dest,
-- const Register temp) DEFINED_ON(x64, mips64);
-+ const Register temp) DEFINED_ON(x64, mips64, ppc64);
- inline void mul64(Imm64 imm, const Register64& dest) PER_ARCH;
- inline void mul64(Imm64 imm, const Register64& dest, const Register temp)
-- DEFINED_ON(x86, x64, arm, mips32, mips64);
-+ DEFINED_ON(x86, x64, arm, mips32, mips64, ppc64);
- inline void mul64(const Register64& src, const Register64& dest,
- const Register temp) PER_ARCH;
- inline void mul64(const Register64& src1, const Register64& src2,
- const Register64& dest) DEFINED_ON(arm64);
- inline void mul64(Imm64 src1, const Register64& src2, const Register64& dest)
- DEFINED_ON(arm64);
-
- inline void mulBy3(Register src, Register dest) PER_ARCH;
-
- inline void mulFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void mulDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // On x86_shared, srcDest must be eax and edx will be clobbered.
- // On ARM, the chip must have hardware division instructions.
- inline void quotient32(Register rhs, Register srcDest,
- bool isUnsigned) PER_SHARED_ARCH;
-@@ -1117,41 +1124,41 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleRemainder32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleQuotient32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow. The
- // remainder is stored into the third argument register here.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest and remOutput are clobbered.
- void flexibleDivMod32(Register rhs, Register srcDest, Register remOutput,
- bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- inline void divFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void divDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void inc64(AbsoluteAddress dest) PER_ARCH;
-
- inline void neg32(Register reg) PER_SHARED_ARCH;
- inline void neg64(Register64 reg) PER_ARCH;
-@@ -1342,17 +1349,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // temp may be invalid only if the chip has the POPCNT instruction.
- inline void popcnt64(Register64 src, Register64 dest, Register temp) PER_ARCH;
-
- // ===============================================================
- // Condition functions
-
- template <typename T1, typename T2>
- inline void cmp32Set(Condition cond, T1 lhs, T2 rhs, Register dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
-
- template <typename T1, typename T2>
- inline void cmpPtrSet(Condition cond, T1 lhs, T2 rhs, Register dest) PER_ARCH;
-
- // ===============================================================
- // Branch functions
-
- template <class L>
-@@ -1367,34 +1374,34 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branch32(Condition cond, const Address& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branch32(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branch32(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) DEFINED_ON(arm, x86_shared);
- inline void branch32(Condition cond, const BaseIndex& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const Operand& lhs, Register rhs,
- Label* label) DEFINED_ON(x86_shared);
- inline void branch32(Condition cond, const Operand& lhs, Imm32 rhs,
- Label* label) DEFINED_ON(x86_shared);
-
- inline void branch32(Condition cond, wasm::SymbolicAddress lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // The supported condition are Equal, NotEqual, LessThan(orEqual),
- // GreaterThan(orEqual), Below(orEqual) and Above(orEqual). When a fail label
- // is not defined it will fall through to next instruction, else jump to the
- // fail label.
- inline void branch64(Condition cond, Register64 lhs, Imm64 val,
- Label* success, Label* fail = nullptr) PER_ARCH;
- inline void branch64(Condition cond, Register64 lhs, Register64 rhs,
-@@ -1433,32 +1440,32 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchPtr(Condition cond, const BaseIndex& lhs, ImmWord rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchPtr(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs,
- Register rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs, ImmWord rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchPtr(Condition cond, wasm::SymbolicAddress lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Given a pointer to a GC Cell, retrieve the StoreBuffer pointer from its
- // chunk header, or nullptr if it is in the tenured heap.
- void loadStoreBuffer(Register ptr, Register buffer) PER_ARCH;
-
- void branchPtrInNurseryChunk(Condition cond, Register ptr, Register temp,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- void branchPtrInNurseryChunk(Condition cond, const Address& address,
- Register temp, Label* label) DEFINED_ON(x86);
- void branchValueIsNurseryCell(Condition cond, const Address& address,
- Register temp, Label* label) PER_ARCH;
- void branchValueIsNurseryCell(Condition cond, ValueOperand value,
- Register temp, Label* label) PER_ARCH;
-
- // This function compares a Value (lhs) which is having a private pointer
-@@ -1470,36 +1477,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- // Truncate a double/float32 to int32 and when it doesn't fit an int32 it will
- // jump to the failure label. This particular variant is allowed to return the
- // value module 2**32, which isn't implemented on all architectures. E.g. the
- // x64 variants will do this only in the int64_t range.
- inline void branchTruncateFloat32MaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleMaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Truncate a double/float32 to intptr and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
- inline void branchTruncateDoubleToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
-
- // Truncate a double/float32 to int32 and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchDouble(DoubleCondition cond, FloatRegister lhs,
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- inline void branchDoubleNotInInt64Range(Address src, Register temp,
- Label* fail);
- inline void branchDoubleNotInUInt64Range(Address src, Register temp,
- Label* fail);
-@@ -1543,17 +1550,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- L label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTest32(Condition cond, Register lhs, Imm32 rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const Address& lhs, Imm32 rhh,
- Label* label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const AbsoluteAddress& lhs,
- Imm32 rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- template <class L>
- inline void branchTestPtr(Condition cond, Register lhs, Register rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, Register lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-@@ -1689,17 +1696,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Perform a type-test on a tag of a Value (32bits boxing), or the tagged
- // value (64bits boxing).
- inline void branchTestUndefined(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, Register tag, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestNumber(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
-@@ -1721,106 +1728,106 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // BaseIndex and ValueOperand variants clobber the ScratchReg on x64.
- // All Variants clobber the ScratchReg on arm64.
- inline void branchTestUndefined(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestInt32(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestDouble(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNumber(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBoolean(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestString(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestSymbol(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBigInt(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNull(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Clobbers the ScratchReg on x64.
- inline void branchTestObject(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestGCThing(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const ValueOperand& value,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchTestPrimitive(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestMagic(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTestMagic(Condition cond, const ValueOperand& value,
- L label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& valaddr,
- JSWhyMagic why, Label* label) PER_ARCH;
-
- inline void branchTestMagicValue(Condition cond, const ValueOperand& val,
- JSWhyMagic why, Label* label);
-
- void branchTestValue(Condition cond, const ValueOperand& lhs,
-@@ -1828,42 +1835,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchTestValue(Condition cond, const BaseIndex& lhs,
- const ValueOperand& rhs, Label* label) PER_ARCH;
-
- // Checks if given Value is evaluated to true or false in a condition.
- // The type of the value should match the type of the method.
- inline void branchTestInt32Truthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestDoubleTruthy(bool truthy, FloatRegister reg,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBooleanTruthy(bool truthy, const ValueOperand& value,
- Label* label) PER_ARCH;
- inline void branchTestStringTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestBigIntTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Create an unconditional branch to the address given as argument.
- inline void branchToComputedAddress(const BaseIndex& address) PER_ARCH;
-
- private:
- template <typename T, typename S, typename L>
- inline void branchPtrImpl(Condition cond, const T& lhs, const S& rhs, L label)
- DEFINED_ON(x86_shared);
-
- void branchPtrInNurseryChunkImpl(Condition cond, Register ptr, Label* label)
- DEFINED_ON(x86);
- template <typename T>
- void branchValueIsNurseryCellImpl(Condition cond, const T& value,
- Register temp, Label* label)
-- DEFINED_ON(arm64, x64, mips64);
-+ DEFINED_ON(arm64, x64, mips64, ppc64);
-
- template <typename T>
- inline void branchTestUndefinedImpl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
- inline void branchTestInt32Impl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
-@@ -1923,116 +1930,116 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void fallibleUnboxString(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxSymbol(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxBigInt(const T& src, Register dest, Label* fail);
-
- inline void cmp32Move32(Condition cond, Register lhs, Register rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Move32(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, Register rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmp32Load32(Condition cond, Register lhs, const Address& rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Load32(Condition cond, Register lhs, Register rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32LoadPtr(Condition cond, const Address& lhs, Imm32 rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void cmp32MovePtr(Condition cond, Register lhs, Imm32 rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32LoadPtr(Condition cond, const Address& addr, Imm32 mask,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32MovePtr(Condition cond, const Address& addr, Imm32 mask,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Conditional move for Spectre mitigations.
- inline void spectreMovePtr(Condition cond, Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Zeroes dest if the condition is true.
- inline void spectreZeroRegister(Condition cond, Register scratch,
- Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- // Performs a bounds check and zeroes the index register if out-of-bounds
- // (to mitigate Spectre).
- private:
- inline void spectreBoundsCheck32(Register index, const Operand& length,
- Register maybeScratch, Label* failure)
- DEFINED_ON(x86);
-
- public:
- inline void spectreBoundsCheck32(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheck32(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void spectreBoundsCheckPtr(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheckPtr(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // ========================================================================
- // Canonicalization primitives.
- inline void canonicalizeDouble(FloatRegister reg);
- inline void canonicalizeDoubleIfDeterministic(FloatRegister reg);
-
- inline void canonicalizeFloat(FloatRegister reg);
- inline void canonicalizeFloatIfDeterministic(FloatRegister reg);
-
- public:
- // ========================================================================
- // Memory access primitives.
- inline void storeUncanonicalizedDouble(FloatRegister src, const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src, const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeDouble(FloatRegister src, const T& dest);
-
- template <class T>
- inline void boxDouble(FloatRegister src, const T& dest);
-
- using MacroAssemblerSpecific::boxDouble;
-
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeFloat32(FloatRegister src, const T& dest);
-
- template <typename T>
-@@ -3470,20 +3477,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
- DEFINED_ON(x86, x64);
-
- public:
- // ========================================================================
- // Convert floating point.
-
- // temp required on x86 and x64; must be undefined on mips64.
- void convertUInt64ToFloat32(Register64 src, FloatRegister dest, Register temp)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- void convertInt64ToFloat32(Register64 src, FloatRegister dest)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- bool convertUInt64ToDoubleNeedsTemp() PER_ARCH;
-
- // temp required when convertUInt64ToDoubleNeedsTemp() returns true.
- void convertUInt64ToDouble(Register64 src, FloatRegister dest,
- Register temp) PER_ARCH;
-
- void convertInt64ToDouble(Register64 src, FloatRegister dest) PER_ARCH;
-@@ -3514,29 +3521,29 @@ class MacroAssembler : public MacroAssemblerSpecific {
- //
- // On 32-bit systems for both wasm and asm.js, and on 64-bit systems for
- // asm.js, heap lengths are limited to 2GB. On 64-bit systems for wasm,
- // 32-bit heap lengths are limited to 4GB, and 64-bit heap lengths will be
- // limited to something much larger.
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Register boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Register64 boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- // Each wasm load/store instruction appends its own wasm::Trap::OutOfBounds.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- AnyRegister out) DEFINED_ON(x86, x64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- Register64 out) DEFINED_ON(x86, x64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Operand dstAddr) DEFINED_ON(x86, x64);
-@@ -3546,26 +3553,26 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // For all the ARM/MIPS wasmLoad and wasmStore functions below, `ptr`
- // MUST equal `ptrScratch`, and that register will be updated based on
- // conditions listed below (where it is only mentioned as `ptr`).
-
- // `ptr` will be updated if access.offset() != 0 or access.type() ==
- // Scalar::Int64.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, AnyRegister output)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, Register64 output)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
-
- // These accept general memoryBase + ptr + offset (in `access`); the offset is
- // always smaller than the guard region. They will insert an additional add
- // if the offset is nonzero, and of course that add may require a temporary
- // register for the offset if the offset is large, and instructions to set it
- // up.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, AnyRegister output) DEFINED_ON(arm64);
-@@ -3575,100 +3582,100 @@ class MacroAssembler : public MacroAssemblerSpecific {
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoad(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr, Register ptrScratch,
- Register output, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedLoadFP(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, FloatRegister output,
- Register tmp1, Register tmp2, Register tmp3)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoadI64(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register64 output,
-- Register tmp) DEFINED_ON(mips32, mips64);
-+ Register tmp) DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedStore(const wasm::MemoryAccessDesc& access, Register value,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreFP(const wasm::MemoryAccessDesc& access,
- FloatRegister floatValue, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreI64(const wasm::MemoryAccessDesc& access,
- Register64 value, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // wasm specific methods, used in both the wasm baseline compiler and ion.
-
- // The truncate-to-int32 methods do not bind the rejoin label; clients must
- // do so if oolWasmTruncateCheckF64ToI32() can jump to it.
- void wasmTruncateDoubleToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateDoubleToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF64ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateFloat32ToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF32ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // The truncate-to-int64 methods will always bind the `oolRejoin` label
- // after the last emitted instruction.
- void wasmTruncateDoubleToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateDoubleToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF64ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateFloat32ToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF32ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // This function takes care of loading the callee's TLS and pinned regs but
- // it is the caller's responsibility to save/restore TLS or pinned regs.
- CodeOffset wasmCallImport(const wasm::CallSiteDesc& desc,
- const wasm::CalleeDesc& callee);
-
- // WasmTableCallIndexReg must contain the index of the indirect call.
- CodeOffset wasmCallIndirect(const wasm::CallSiteDesc& desc,
-@@ -3735,72 +3742,72 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `expected` and `output` must be edx:eax; `replacement` is ecx:ebx.
- // x64: `output` must be rax.
- // ARM: Registers must be distinct; `replacement` and `output` must be
- // (even,odd) pairs.
-
- void compareExchange64(const Synchronization& sync, const Address& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void compareExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Exchange with memory. Return the value initially in memory.
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `value` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `value` and `output` must be distinct and (even,odd) pairs.
- // ARM64: `value` and `output` must be distinct.
-
- void atomicExchange64(const Synchronization& sync, const Address& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void atomicExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Read-modify-write with memory. Return the value in memory before the
- // operation.
- //
- // x86-shared:
- // For 8-bit operations, `value` and `output` must have a byte subregister.
- // For Add and Sub, `temp` must be invalid.
- // For And, Or, and Xor, `output` must be eax and `temp` must have a byte
-@@ -3826,44 +3833,44 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp, Register output) DEFINED_ON(x86_shared);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- // x86:
- // `temp` must be ecx:ebx; `output` must be edx:eax.
- // x64:
- // For Add and Sub, `temp` is ignored.
- // For And, Or, and Xor, `output` must be rax.
- // ARM:
- // `temp` and `output` must be (even,odd) pairs and distinct from `value`.
- // ARM64:
- // Registers `value`, `temp`, and `output` must all differ.
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- // x64:
- // `value` can be any register.
- // ARM:
-@@ -3871,24 +3878,24 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM64:
- // Registers `value` and `temp` must differ.
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- // 64-bit atomic load. On 64-bit systems, use regular load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `output` must be (even,odd) pair.
-
- void atomicLoad64(const Synchronization& sync, const Address& mem,
-@@ -3930,43 +3937,43 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp,
- Register output) DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const Address& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-@@ -3977,23 +3984,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // Read-modify-write with memory. Return no value.
- //
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp)
-@@ -4009,22 +4016,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp)
- DEFINED_ON(x86_shared);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- // 64-bit wide operations.
-
- // 64-bit atomic load. On 64-bit systems, use regular wasm load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `temp` should be invalid; `output` must be (even,odd) pair.
-@@ -4074,22 +4081,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM: Registers must be distinct; `temp` and `output` must be (even,odd)
- // pairs.
- // MIPS: Registers must be distinct.
- // MIPS32: `temp` should be invalid.
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const Address& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const BaseIndex& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-@@ -4131,42 +4138,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
-@@ -4182,23 +4189,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-@@ -4209,22 +4216,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp) DEFINED_ON(x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicIsLockFreeJS(Register value, Register output);
-
- // ========================================================================
- // Spectre Mitigations.
- //
- // Spectre attacks are side-channel attacks based on cache pollution or
- // slow-execution of some instructions. We have multiple spectre mitigations
-@@ -4803,17 +4810,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // StackPointer manipulation functions.
- // On ARM64, the StackPointer is implemented as two synchronized registers.
- // Code shared across platforms must use these functions to be valid.
- template <typename T>
- inline void addToStackPtr(T t);
- template <typename T>
- inline void addStackPtrTo(T t);
-
-- void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64);
-+ void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64, ppc64);
- void subFromStackPtr(Register reg);
-
- template <typename T>
- void subStackPtrFrom(T t) {
- subPtr(getStackPointer(), t);
- }
-
- template <typename T>
-diff --git a/js/src/jit/MoveEmitter.h b/js/src/jit/MoveEmitter.h
-index 6c62c0561a..30ee4b61a5 100644
---- a/js/src/jit/MoveEmitter.h
-+++ b/js/src/jit/MoveEmitter.h
-@@ -12,15 +12,17 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MoveEmitter-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MoveEmitter-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MoveEmitter-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MoveEmitter-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MoveEmitter-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MoveEmitter-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #endif /* jit_MoveEmitter_h */
-diff --git a/js/src/jit/Registers.h b/js/src/jit/Registers.h
-index 67c8661004..ef49df83e5 100644
---- a/js/src/jit/Registers.h
-+++ b/js/src/jit/Registers.h
-@@ -15,16 +15,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Architecture-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Architecture-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Architecture-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Architecture-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Architecture-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Architecture-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/SharedICHelpers-inl.h b/js/src/jit/SharedICHelpers-inl.h
-index 901c80cdd8..fd4a27d8bb 100644
---- a/js/src/jit/SharedICHelpers-inl.h
-+++ b/js/src/jit/SharedICHelpers-inl.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64-inl.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64-inl.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none-inl.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICHelpers.h b/js/src/jit/SharedICHelpers.h
-index 563cae3ccf..737ca1d5a5 100644
---- a/js/src/jit/SharedICHelpers.h
-+++ b/js/src/jit/SharedICHelpers.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICRegisters.h b/js/src/jit/SharedICRegisters.h
-index c87e5f8408..76239d5dde 100644
---- a/js/src/jit/SharedICRegisters.h
-+++ b/js/src/jit/SharedICRegisters.h
-@@ -14,16 +14,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICRegisters-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICRegisters-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/SharedICRegisters-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/SharedICRegisters-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICRegisters-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICRegisters-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/moz.build b/js/src/jit/moz.build
-index f50d86fc44..82cddd07af 100644
---- a/js/src/jit/moz.build
-+++ b/js/src/jit/moz.build
-@@ -227,17 +227,29 @@ elif CONFIG["JS_CODEGEN_MIPS32"] or CONFIG["JS_CODEGEN_MIPS64"]:
- "mips64/CodeGenerator-mips64.cpp",
- "mips64/Lowering-mips64.cpp",
- "mips64/MacroAssembler-mips64.cpp",
- "mips64/MoveEmitter-mips64.cpp",
- "mips64/Trampoline-mips64.cpp",
- ]
- if CONFIG["JS_SIMULATOR_MIPS64"]:
- UNIFIED_SOURCES += ["mips64/Simulator-mips64.cpp"]
--
-+elif CONFIG["JS_CODEGEN_PPC64"]:
-+ lir_inputs += ["ppc64/LIR-ppc64.h"]
-+ UNIFIED_SOURCES += [
-+ "ppc64/Architecture-ppc64.cpp",
-+ "ppc64/Assembler-ppc64.cpp",
-+ "ppc64/Bailouts-ppc64.cpp",
-+ "ppc64/CodeGenerator-ppc64.cpp",
-+ "ppc64/Lowering-ppc64.cpp",
-+ "ppc64/MacroAssembler-ppc64.cpp",
-+ "ppc64/MoveEmitter-ppc64.cpp",
-+ "ppc64/Trampoline-ppc64.cpp",
-+ "shared/AtomicOperations-shared-jit.cpp",
-+ ]
-
- # Generate jit/MIROpsGenerated.h from jit/MIROps.yaml
- GeneratedFile(
- "MIROpsGenerated.h",
- script="GenerateMIRFiles.py",
- entry_point="generate_mir_header",
- inputs=["MIROps.yaml"],
- )
-diff --git a/js/src/jit/shared/Assembler-shared.h b/js/src/jit/shared/Assembler-shared.h
-index dfb2bcb6b8..69ba759d42 100644
---- a/js/src/jit/shared/Assembler-shared.h
-+++ b/js/src/jit/shared/Assembler-shared.h
-@@ -20,23 +20,24 @@
- #include "jit/Registers.h"
- #include "jit/RegisterSets.h"
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "vm/HelperThreads.h"
- #include "vm/NativeObject.h"
- #include "wasm/WasmTypes.h"
-
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- // Push return addresses callee-side.
- # define JS_USE_LINK_REGISTER
- #endif
-
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-- defined(JS_CODEGEN_ARM64)
-+ defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_PPC64)
- // JS_CODELABEL_LINKMODE gives labels additional metadata
- // describing how Bind() should patch them.
- # define JS_CODELABEL_LINKMODE
- #endif
-
- namespace js {
- namespace jit {
-
-diff --git a/js/src/jit/shared/AtomicOperations-shared-jit.cpp b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-index 79463f118b..7c8eeaf89e 100644
---- a/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-+++ b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-@@ -133,16 +133,38 @@ static constexpr Register AtomicTemp = edx;
- // 64-bit registers for cmpxchg8b. ValReg/Val2Reg/Temp are not used in this
- // case.
-
- static constexpr Register64 AtomicValReg64(edx, eax);
- static constexpr Register64 AtomicVal2Reg64(ecx, ebx);
-
- // AtomicReturnReg64 is unused on x86.
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+// Selected registers match the argument registers, except that the Ptr is not
-+// in IntArgReg0 so as not to conflict with the result register.
-+
-+static const LiveRegisterSet AtomicNonVolatileRegs;
-+
-+static constexpr Register AtomicPtrReg = IntArgReg4;
-+static constexpr Register AtomicPtr2Reg = IntArgReg1;
-+static constexpr Register AtomicValReg = IntArgReg1;
-+static constexpr Register64 AtomicValReg64(IntArgReg1);
-+static constexpr Register AtomicVal2Reg = IntArgReg2;
-+static constexpr Register64 AtomicVal2Reg64(IntArgReg2);
-+static constexpr Register AtomicTemp = IntArgReg3;
-+static constexpr Register AtomicTemp2 = IntArgReg5;
-+static constexpr Register AtomicTemp3 = IntArgReg6;
-+static constexpr Register64 AtomicTemp64(IntArgReg3);
-+static constexpr Register64 AtomicTemp64_2(IntArgReg5);
-+static constexpr Register64 AtomicTemp64_3(IntArgReg6);
-+
-+static constexpr Register64 AtomicReturnReg64 = ReturnReg64;
-+
- #else
- # error "Unsupported platform"
- #endif
-
- // These are useful shorthands and hide the meaningless uint/int distinction.
-
- static constexpr Scalar::Type SIZE8 = Scalar::Uint8;
- static constexpr Scalar::Type SIZE16 = Scalar::Uint16;
-@@ -248,31 +270,37 @@ static uint32_t GenPrologue(MacroAssembler& masm, ArgIterator* iter) {
- uint32_t start = masm.currentOffset();
- masm.PushRegsInMask(AtomicNonVolatileRegs);
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // The return address is among the nonvolatile registers, if pushed at all.
- iter->argBase = masm.framePushed();
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // The return address is pushed separately.
- iter->argBase = sizeof(void*) + masm.framePushed();
-+#elif defined(JS_CODEGEN_PPC64)
-+// XXX
-+ // The return address is in LR (an SPR); it's not (probably) on the stack.
-+ iter->argBase = masm.framePushed();
- #else
- # error "Unsupported platform"
- #endif
- return start;
- }
-
- static void GenEpilogue(MacroAssembler& masm) {
- masm.PopRegsInMask(AtomicNonVolatileRegs);
- MOZ_ASSERT(masm.framePushed() == 0);
- #if defined(JS_CODEGEN_ARM64)
- masm.Ret();
- #elif defined(JS_CODEGEN_ARM)
- masm.mov(lr, pc);
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- masm.ret();
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.as_blr();
- #endif
- }
-
- #ifndef JS_64BIT
- static uint32_t GenNop(MacroAssembler& masm) {
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenEpilogue(masm);
-@@ -414,21 +442,31 @@ static uint32_t GenCmpxchg(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
- GenGprArg(masm, MIRType::Int32, &iter, AtomicVal2Reg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
- ReturnReg);
-+#endif
- break;
- case SIZE64:
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- GenGpr64Arg(masm, &iter, AtomicVal2Reg64);
- #if defined(JS_CODEGEN_X86)
- static_assert(AtomicValReg64 == Register64(edx, eax));
- static_assert(AtomicVal2Reg64 == Register64(ecx, ebx));
-
-@@ -453,19 +491,29 @@ static uint32_t GenExchange(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.atomicExchange(size, sync, addr, AtomicValReg, ReturnReg);
-+#endif
- break;
- case SIZE64:
- #if defined(JS_64BIT)
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- masm.atomicExchange64(sync, addr, AtomicValReg64, AtomicReturnReg64);
- break;
- #else
- MOZ_CRASH("64-bit atomic exchange not available on this platform");
-@@ -492,17 +540,22 @@ static uint32_t GenFetchOp(MacroAssembler& masm, Scalar::Type size, AtomicOp op,
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- Register tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register::Invalid()
- : AtomicTemp;
- #else
- Register tmp = AtomicTemp;
- #endif
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, AtomicTemp2,
-+ AtomicTemp3, ReturnReg);
-+#else
- masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, ReturnReg);
-+#endif
- break;
- }
- case SIZE64: {
- #if defined(JS_64BIT)
- # if defined(JS_CODEGEN_X64)
- Register64 tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register64::Invalid()
- : AtomicTemp64;
-@@ -636,16 +689,19 @@ static bool UnalignedAccessesAreOK() {
- #endif
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return true;
- #elif defined(JS_CODEGEN_ARM)
- return !HasAlignmentFault();
- #elif defined(JS_CODEGEN_ARM64)
- // This is not necessarily true but it's the best guess right now.
- return true;
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We'd sure like to avoid it, even though it works.
-+ return false;
- #else
- # error "Unsupported platform"
- #endif
- }
-
- void AtomicMemcpyDownUnsynchronized(uint8_t* dest, const uint8_t* src,
- size_t nbytes) {
- const uint8_t* lim = src + nbytes;
-diff --git a/js/src/jsapi-tests/testJitABIcalls.cpp b/js/src/jsapi-tests/testJitABIcalls.cpp
-index 02b67da3ca..bd45389b21 100644
---- a/js/src/jsapi-tests/testJitABIcalls.cpp
-+++ b/js/src/jsapi-tests/testJitABIcalls.cpp
-@@ -653,16 +653,19 @@ class JitABICall final : public JSAPITest, public DefineCheckArgs<Sig> {
- Register base = r8;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS32)
- Register base = t1;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS64)
- Register base = t1;
- regs.take(base);
-+#elif defined(JS_CODEGEN_PPC64)
-+ Register base = r0;
-+ regs.take(base);
- #else
- # error "Unknown architecture!"
- #endif
-
- Register setup = regs.takeAny();
-
- this->generateCalls(masm, base, setup);
-
-diff --git a/js/src/jsapi-tests/testsJit.cpp b/js/src/jsapi-tests/testsJit.cpp
-index 069eef43fe..705609df2c 100644
---- a/js/src/jsapi-tests/testsJit.cpp
-+++ b/js/src/jsapi-tests/testsJit.cpp
-@@ -20,16 +20,21 @@ void PrepareJit(js::jit::MacroAssembler& masm) {
- #endif
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Push the link register separately, since it's not a GPR.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PushRegsInMask(save);
- }
-
- // Generate the exit path of the JIT code, which restores every register. Then,
- // make it executable and run it.
-@@ -37,26 +42,35 @@ bool ExecuteJit(JSContext* cx, js::jit::MacroAssembler& masm) {
- using namespace js::jit;
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We pop after loading the regs.
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PopRegsInMask(save);
- #if defined(JS_CODEGEN_ARM64)
- // Return using the value popped into x30.
- masm.abiret();
-
- // Reset stack pointer.
- masm.SetStackPointer64(PseudoStackPointer64);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Pop LR and exit.
-+ masm.as_ld(ScratchRegister, StackPointer, 0);
-+ masm.xs_mtlr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, 8);
-+ masm.as_blr();
- #else
- // Exit the JIT-ed code using the ABI return style.
- masm.abiret();
- #endif
-
- if (masm.oom()) {
- return false;
- }
-diff --git a/js/src/util/Poison.h b/js/src/util/Poison.h
-index 8356ca1f00..5eeb111cf8 100644
---- a/js/src/util/Poison.h
-+++ b/js/src/util/Poison.h
-@@ -88,16 +88,18 @@ const uint8_t JS_SCOPE_DATA_TRAILING_NAMES_PATTERN = 0xCC;
- */
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) || \
- defined(JS_CODEGEN_NONE)
- # define JS_SWEPT_CODE_PATTERN 0xED // IN instruction, crashes in user mode.
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- # define JS_SWEPT_CODE_PATTERN 0xA3 // undefined instruction
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # define JS_SWEPT_CODE_PATTERN 0x01 // undefined instruction
-+#elif defined(JS_CODEGEN_PPC64) || defined(JS_CODEGEN_PPC)
-+# define JS_SWEPT_CODE_PATTERN 0x00 // architecturally defined as illegal
- #else
- # error "JS_SWEPT_CODE_PATTERN not defined for this platform"
- #endif
-
- enum class MemCheckKind : uint8_t {
- // Marks a region as poisoned. Memory sanitizers like ASan will crash when
- // accessing it (both reads and writes).
- MakeNoAccess,
-diff --git a/js/src/wasm/WasmBaselineCompile.cpp b/js/src/wasm/WasmBaselineCompile.cpp
-index 156f3cbbba..ab29f44713 100644
---- a/js/src/wasm/WasmBaselineCompile.cpp
-+++ b/js/src/wasm/WasmBaselineCompile.cpp
-@@ -138,16 +138,19 @@
- #if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips32/Assembler-mips32.h"
- #endif
- #if defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips64/Assembler-mips64.h"
- #endif
-+#if defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Assembler-ppc64.h"
-+#endif
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "util/Memory.h"
- #include "wasm/TypedObject.h"
- #include "wasm/WasmGC.h"
- #include "wasm/WasmGenerator.h"
- #include "wasm/WasmInstance.h"
- #include "wasm/WasmOpIter.h"
- #include "wasm/WasmSignalHandlers.h"
-@@ -288,16 +291,23 @@ static constexpr Register RabaldrScratchI32 = CallTempReg2;
- #endif
-
- #ifdef RABALDR_SCRATCH_F32_ALIASES_F64
- # if !defined(RABALDR_SCRATCH_F32) || !defined(RABALDR_SCRATCH_F64)
- # error "Bad configuration"
- # endif
- #endif
-
-+#ifdef JS_CODEGEN_PPC64
-+# define RABALDR_SCRATCH_I32
-+// We can use all the argregs up, and we don't want the JIT using our own
-+// private scratch registers, so this is the best option of what's left.
-+static constexpr Register RabaldrScratchI32 = r19;
-+#endif
-+
- template <MIRType t>
- struct RegTypeOf {
- #ifdef ENABLE_WASM_SIMD
- static_assert(t == MIRType::Float32 || t == MIRType::Double ||
- t == MIRType::Simd128,
- "Float mask type");
- #else
- static_assert(t == MIRType::Float32 || t == MIRType::Double,
-@@ -550,16 +560,18 @@ struct SpecificRegs {};
- #elif defined(JS_CODEGEN_MIPS32)
- struct SpecificRegs {
- RegI64 abiReturnRegI64;
-
- SpecificRegs() : abiReturnRegI64(ReturnReg64) {}
- };
- #elif defined(JS_CODEGEN_MIPS64)
- struct SpecificRegs {};
-+#elif defined(JS_CODEGEN_PPC64)
-+struct SpecificRegs {};
- #else
- struct SpecificRegs {
- # ifndef JS_64BIT
- RegI64 abiReturnRegI64;
- # endif
-
- SpecificRegs() { MOZ_CRASH("BaseCompiler porting interface: SpecificRegs"); }
- };
-@@ -6038,16 +6050,25 @@ class BaseCompiler final : public BaseCompilerInterface {
- ABIArg argLoc = call->abi.next(MIRType::Int32);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- loadI32(arg, scratch);
- masm.store32(scratch, Address(masm.getStackPointer(),
- argLoc.offsetFromArgBase()));
- } else {
- loadI32(arg, RegI32(argLoc.gpr()));
-+#if JS_CODEGEN_PPC64
-+ // If this is a call to compiled C++, we must ensure that the
-+ // upper 32 bits are clear: addi can sign-extend, which yields
-+ // difficult-to-diagnose bugs when the function expects a uint32_t
-+ // but the register it gets has a residual 64-bit value.
-+ if (call->usesSystemAbi) {
-+ masm.as_rldicl(argLoc.gpr(), argLoc.gpr(), 0, 32);
-+ }
-+#endif
- }
- break;
- }
- case ValType::I64: {
- ABIArg argLoc = call->abi.next(MIRType::Int64);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- #ifdef JS_PUNBOX64
-@@ -6324,17 +6345,18 @@ class BaseCompiler final : public BaseCompilerInterface {
-
- // Compute the absolute table base pointer into `scratch`, offset by 8
- // to account for the fact that ma_mov read PC+8.
- masm.ma_sub(Imm32(offset + 8), scratch, arm_scratch);
-
- // Jump indirect via table element.
- masm.ma_ldr(DTRAddr(scratch, DtrRegImmShift(switchValue, LSL, 2)), pc,
- Offset, Assembler::Always);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- ScratchI32 scratch(*this);
- CodeLabel tableCl;
-
- masm.ma_li(scratch, &tableCl);
-
- tableCl.target()->bind(theTable->offset());
- masm.addCodeLabel(tableCl);
-
-@@ -6493,16 +6515,22 @@ class BaseCompiler final : public BaseCompilerInterface {
- # elif defined(JS_CODEGEN_ARM64)
- ARMRegister sd(srcDest.reg, 64);
- ARMRegister r(rhs.reg, 64);
- if (isUnsigned) {
- masm.Udiv(sd, sd, r);
- } else {
- masm.Sdiv(sd, sd, r);
- }
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (isUnsigned) {
-+ masm.as_divdu(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: quotientI64");
- # endif
- masm.bind(&done);
- }
-
- void remainderI64(RegI64 rhs, RegI64 srcDest, RegI64 reserved,
- IsUnsigned isUnsigned, bool isConst, int64_t c) {
-@@ -6544,29 +6572,46 @@ class BaseCompiler final : public BaseCompilerInterface {
- ARMRegister t(temp, 64);
- if (isUnsigned) {
- masm.Udiv(t, sd, r);
- } else {
- masm.Sdiv(t, sd, r);
- }
- masm.Mul(t, t, r);
- masm.Sub(sd, sd, t);
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (js::jit::HasPPCISA3()) {
-+ if (isUnsigned) {
-+ masm.as_modud(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_modsd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
-+ } else {
-+ ScratchI32 temp(*this);
-+ if (isUnsigned) {
-+ masm.as_divdu(temp, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(temp, srcDest.reg, rhs.reg);
-+ }
-+ masm.as_mulld(temp, temp, rhs.reg);
-+ masm.as_subf(srcDest.reg, temp, srcDest.reg); // T = B - A
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: remainderI64");
- # endif
- masm.bind(&done);
- }
- #endif // RABALDR_INT_DIV_I64_CALLOUT
-
- RegI32 needRotate64Temp() {
- #if defined(JS_CODEGEN_X86)
- return needI32();
- #elif defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- return RegI32::Invalid();
- #else
- MOZ_CRASH("BaseCompiler platform hook: needRotate64Temp");
- #endif
- }
-
- class OutOfLineTruncateCheckF32OrF64ToI32 : public OutOfLineCode {
- AnyReg src;
-@@ -6869,30 +6914,35 @@ class BaseCompiler final : public BaseCompilerInterface {
- RegI64 ptr64 = fromI32(ptr);
-
- // In principle there may be non-zero bits in the upper bits of the
- // register; clear them.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended (see comment block "64-bit GPRs
- // carrying 32-bit values" in MacroAssembler.h); we already have that.
- masm.assertCanonicalInt32(ptr);
-+# elif defined(JS_CODEGEN_PPC64)
-+ // The canonical value is sign-extended.
-+ masm.as_rldicl(ptr, ptr, 0, 32); // "clrldi"
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
-
- // Any Spectre mitigation will appear to update the ptr64 register.
- masm.wasmBoundsCheck64(
- Assembler::Below, ptr64,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
-
- // Restore the value to the canonical form for a 32-bit value in a
- // 64-bit register and/or the appropriate form for further use in the
- // indexing instruction.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended; we already have that.
-+# elif defined(JS_CODEGEN_PPC64)
-+ // Leave it zero-extended.
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
- } else {
- masm.wasmBoundsCheck32(
- Assembler::Below, ptr,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
- }
-@@ -6903,17 +6953,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- #endif
- masm.wasmTrap(Trap::OutOfBounds, bytecodeOffset());
- masm.bind(&ok);
- }
- }
-
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- BaseIndex prepareAtomicMemoryAccess(MemoryAccessDesc* access,
- AccessCheck* check, RegI32 tls,
- RegI32 ptr) {
- MOZ_ASSERT(needTlsForAccess(*check) == tls.isValid());
- prepareMemoryAccess(access, check, tls, ptr);
- return BaseIndex(HeapReg, ptr, TimesOne, access->offset());
- }
- #elif defined(JS_CODEGEN_X86)
-@@ -7001,17 +7051,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- if (dest.tag == AnyReg::I64) {
- MOZ_ASSERT(dest.i64() == specific_.abiReturnRegI64);
- masm.wasmLoadI64(*access, srcAddr, dest.i64());
- } else {
- // For 8 bit loads, this will generate movsbl or movzbl, so
- // there's no constraint on what the output register may be.
- masm.wasmLoad(*access, srcAddr, dest.any());
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (dest.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedLoadI64(*access, HeapReg, ptr, ptr, dest.i64(),
- temp1);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedLoadFP(*access, HeapReg, ptr, ptr, dest.f32(),
-@@ -7102,17 +7154,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- MOZ_ASSERT(temp.isInvalid());
- if (access->type() == Scalar::Int64) {
- masm.wasmStoreI64(*access, src.i64(), HeapReg, ptr, ptr);
- } else if (src.tag == AnyReg::I64) {
- masm.wasmStore(*access, AnyRegister(src.i64().low), HeapReg, ptr, ptr);
- } else {
- masm.wasmStore(*access, src.any(), HeapReg, ptr, ptr);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (src.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedStoreI64(*access, src.i64(), HeapReg, ptr, ptr,
- temp);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedStoreFP(*access, src.f32(), HeapReg, ptr, ptr,
-@@ -7160,17 +7214,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- void maybeFree(BaseCompiler* bc) {
- for (size_t i = 0; i < Count; ++i) {
- bc->maybeFree(this->operator[](i));
- }
- }
- };
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicRMW32Temps = Atomic32Temps<3>;
- #else
- using AtomicRMW32Temps = Atomic32Temps<1>;
- #endif
-
- template <typename T>
- void atomicRMW32(const MemoryAccessDesc& access, T srcAddr, AtomicOp op,
- RegI32 rv, RegI32 rd, const AtomicRMW32Temps& temps) {
-@@ -7187,17 +7242,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temp, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], rd);
- #endif
- break;
- default: {
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7208,17 +7264,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- // On x86, V is Address. On other platforms, it is Register64.
- // T is BaseIndex or Address.
- template <typename T, typename V>
- void atomicRMW64(const MemoryAccessDesc& access, const T& srcAddr,
- AtomicOp op, V value, Register64 temp, Register64 rd) {
- masm.wasmAtomicFetchOp64(access, op, value, srcAddr, temp, rd);
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicCmpXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicCmpXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicCmpXchg32(const MemoryAccessDesc& access, T srcAddr,
- RegI32 rexpect, RegI32 rnew, RegI32 rd,
-@@ -7236,29 +7293,31 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, temps[0],
- temps[1], temps[2], rd);
- #else
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
- }
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicXchg32(const MemoryAccessDesc& access, T srcAddr, RegI32 rv,
- RegI32 rd, const AtomicXchg32Temps& temps) {
-@@ -7275,17 +7334,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- }
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicExchange(access, srcAddr, rv, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7342,16 +7402,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_MIPS32)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM64)
- pop2xI64(r0, r1);
-+#elif defined(JS_CODEGEN_PPC64)
-+ pop2xI64(r0, r1);
- #else
- MOZ_CRASH("BaseCompiler porting interface: pop2xI64ForMulI64");
- #endif
- }
-
- void pop2xI64ForDivI64(RegI64* r0, RegI64* r1, RegI64* reserved) {
- #if defined(JS_CODEGEN_X64)
- // r0 must be rax, and rdx will be clobbered.
-@@ -7529,17 +7591,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI32();
- }
- setRd(bc->needI32());
- }
- ~PopAtomicCmpXchg32Regs() {
- bc->freeI32(rnew);
- bc->freeI32(rexpect);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- if (type == ValType::I64) {
- rnew = bc->popI64ToI32();
- rexpect = bc->popI64ToI32();
- } else {
- rnew = bc->popI32();
-@@ -7606,17 +7669,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI64();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rnew = bc->popI64();
- rexpect = bc->popI64();
- setRd(bc->needI64());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
-@@ -7658,17 +7721,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- bc->needI64(bc->specific_.edx_eax);
- setRd(bc->specific_.edx_eax);
- }
- ~PopAtomicLoad64Regs() { bc->freeI32(bc->specific_.ecx); }
- # elif defined(JS_CODEGEN_ARM)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64Pair());
- }
--# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64());
- }
- # else
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: PopAtomicLoad64Regs");
- }
- # endif
-@@ -7745,17 +7809,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- temps.allocate(bc);
- setRd(bc->needI32());
- }
- ~PopAtomicRMW32Regs() {
- bc->freeI32(rv);
- temps.maybeFree(bc);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType, AtomicOp op)
- : Base(bc) {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
-
-@@ -7833,17 +7898,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- temp = bc->needI64Pair();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW64Regs(BaseCompiler* bc, AtomicOp) : Base(bc) {
- rv = bc->popI64();
- temp = bc->needI64();
- setRd(bc->needI64());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
-@@ -7888,17 +7953,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- setRd(bc->needI32());
- }
- ~PopAtomicXchg32Regs() { bc->freeI32(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
- setRd(bc->needI32());
-@@ -7954,17 +8020,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #elif defined(JS_CODEGEN_ARM)
- // Both rv and rd must be odd/even pairs.
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64Pair());
- setRd(bc->needI64Pair());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64());
- setRd(bc->needI64());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #else
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: xchg64");
-@@ -8968,16 +9035,18 @@ static void CtzI32(MacroAssembler& masm, RegI32 rsd) {
-
- // Currently common to PopcntI32 and PopcntI64
- static RegI32 PopcntTemp(BaseCompiler& bc) {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return AssemblerX86Shared::HasPOPCNT() ? RegI32::Invalid() : bc.needI32();
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- return bc.needI32();
-+#elif defined(JS_CODEGEN_PPC64)
-+ return RegI32::Invalid(); // We rock.
- #else
- MOZ_CRASH("BaseCompiler platform hook: PopcntTemp");
- #endif
- }
-
- static void PopcntI32(BaseCompiler& bc, RegI32 rsd, RegI32 temp) {
- bc.masm.popcnt32(rsd, rsd, temp);
- }
-@@ -11982,17 +12051,17 @@ RegI32 BaseCompiler::popMemory32Access(MemoryAccessDesc* access,
- bceCheckLocal(access, check, local);
- }
-
- return popI32();
- }
-
- void BaseCompiler::pushHeapBase() {
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- RegI64 heapBase = needI64();
- moveI64(RegI64(Register64(HeapReg)), heapBase);
- pushI64(heapBase);
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32)
- RegI32 heapBase = needI32();
- moveI32(RegI32(HeapReg), heapBase);
- pushI32(heapBase);
- #elif defined(JS_CODEGEN_X86)
-@@ -17244,17 +17313,19 @@ bool js::wasm::BaselinePlatformSupport() {
- // they are definitely implemented on the Cortex-A7 and Cortex-A15
- // and on all ARMv8 systems.
- if (!HasIDIV()) {
- return false;
- }
- #endif
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) || \
- defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+ // PPC64 gates on other prerequisites not specified here.
- return true;
- #else
- return false;
- #endif
- }
-
- bool js::wasm::BaselineCompileFunctions(const ModuleEnvironment& moduleEnv,
- const CompilerEnvironment& compilerEnv,
-diff --git a/js/src/wasm/WasmCompile.cpp b/js/src/wasm/WasmCompile.cpp
-index 0f456aaaa5..f0694f1b9e 100644
---- a/js/src/wasm/WasmCompile.cpp
-+++ b/js/src/wasm/WasmCompile.cpp
-@@ -45,16 +45,17 @@ using namespace js::wasm;
- uint32_t wasm::ObservedCPUFeatures() {
- enum Arch {
- X86 = 0x1,
- X64 = 0x2,
- ARM = 0x3,
- MIPS = 0x4,
- MIPS64 = 0x5,
- ARM64 = 0x6,
-+ PPC64 = 0x7,
- ARCH_BITS = 3
- };
-
- #if defined(JS_CODEGEN_X86)
- MOZ_ASSERT(uint32_t(jit::CPUInfo::GetSSEVersion()) <=
- (UINT32_MAX >> ARCH_BITS));
- return X86 | (uint32_t(jit::CPUInfo::GetSSEVersion()) << ARCH_BITS);
- #elif defined(JS_CODEGEN_X64)
-@@ -68,16 +69,19 @@ uint32_t wasm::ObservedCPUFeatures() {
- MOZ_ASSERT(jit::GetARM64Flags() <= (UINT32_MAX >> ARCH_BITS));
- return ARM64 | (jit::GetARM64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS32)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS | (jit::GetMIPSFlags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS64)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS64 | (jit::GetMIPSFlags() << ARCH_BITS);
-+#elif defined(JS_CODEGEN_PPC64)
-+ MOZ_ASSERT(jit::GetPPC64Flags() <= (UINT32_MAX >> ARCH_BITS));
-+ return PPC64 | (jit::GetPPC64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_NONE)
- return 0;
- #else
- # error "unknown architecture"
- #endif
- }
-
- FeatureArgs FeatureArgs::build(JSContext* cx, const FeatureOptions& options) {
-diff --git a/js/src/wasm/WasmFrame.h b/js/src/wasm/WasmFrame.h
-index 85f2612d14..9919205739 100644
---- a/js/src/wasm/WasmFrame.h
-+++ b/js/src/wasm/WasmFrame.h
-@@ -53,16 +53,25 @@ constexpr uintptr_t ExitOrJitEntryFPTag = 0x1;
- // before the function has made its stack reservation, the stack alignment is
- // sizeof(Frame) % WasmStackAlignment.
- //
- // During MacroAssembler code generation, the bytes pushed after the wasm::Frame
- // are counted by masm.framePushed. Thus, the stack alignment at any point in
- // time is (sizeof(wasm::Frame) + masm.framePushed) % WasmStackAlignment.
-
- class Frame {
-+#if defined(JS_CODEGEN_PPC64)
-+ // Since Wasm can call directly to ABI-compliant routines, the Frame must
-+ // have an ABI-compliant linkage area. We allocate four doublewords, the
-+ // minimum size.
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
- // See GenerateCallableEpilogue for why this must be
- // the first field of wasm::Frame (in a downward-growing stack).
- // It's either the caller's Frame*, for wasm callers, or the JIT caller frame
- // plus a tag otherwise.
- uint8_t* callerFP_;
-
- // The return address pushed by the call (in the case of ARM/MIPS the return
- // address is pushed by the first instruction of the prologue).
-@@ -115,18 +124,21 @@ class Frame {
- static uint8_t* addExitOrJitEntryFPTag(const Frame* fp) {
- MOZ_ASSERT(!isExitOrJitEntryFP(fp));
- return reinterpret_cast<uint8_t*>(reinterpret_cast<uintptr_t>(fp) |
- ExitOrJitEntryFPTag);
- }
- };
-
- static_assert(!std::is_polymorphic_v<Frame>, "Frame doesn't need a vtable.");
-+#if !defined(JS_CODEGEN_PPC64)
-+// Not on PowerPC, it's not.
- static_assert(sizeof(Frame) == 2 * sizeof(void*),
- "Frame is a two pointer structure");
-+#endif
-
- class FrameWithTls : public Frame {
- TlsData* calleeTls_;
- TlsData* callerTls_;
-
- public:
- TlsData* calleeTls() { return calleeTls_; }
- TlsData* callerTls() { return callerTls_; }
-diff --git a/js/src/wasm/WasmFrameIter.cpp b/js/src/wasm/WasmFrameIter.cpp
-index dffab53940..5da8d6c730 100644
---- a/js/src/wasm/WasmFrameIter.cpp
-+++ b/js/src/wasm/WasmFrameIter.cpp
-@@ -358,16 +358,21 @@ static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
- static_assert(BeforePushRetAddr == 0, "Required by StartUnwinding");
- static_assert(PushedFP > PushedRetAddr, "Required by StartUnwinding");
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- static const unsigned PushedRetAddr = 8;
- static const unsigned PushedFP = 12;
- static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
-+#elif defined(JS_CODEGEN_PPC64)
-+static const unsigned PushedRetAddr = 12;
-+static const unsigned PushedFP = 16;
-+static const unsigned SetFP = 20;
-+static const unsigned PoppedFP = 8;
- #elif defined(JS_CODEGEN_NONE)
- // Synthetic values to satisfy asserts and avoid compiler warnings.
- static const unsigned PushedRetAddr = 0;
- static const unsigned PushedFP = 1;
- static const unsigned SetFP = 2;
- static const unsigned PoppedFP = 3;
- #else
- # error "Unknown architecture!"
-@@ -453,16 +458,38 @@ static void GenerateCallablePrologue(MacroAssembler& masm, uint32_t* entry) {
- MemOperand(sp, Frame::callerFPOffset()));
- MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
- masm.Mov(ARMRegister(FramePointer, 64), sp);
- MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-
- // And restore the SP-reg setting, per comment above.
- masm.SetStackPointer64(stashedSPreg);
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ {
-+ *entry = masm.currentOffset();
-+
-+ // These must be in this precise order. Fortunately we can subsume the
-+ // SPR load into the initial "verse" since it is treated atomically.
-+ // The linkage area required for ABI compliance is baked into the Frame.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, -(sizeof(Frame)));
-+ masm.as_std(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedRetAddr == masm.currentOffset() - *entry);
-+ masm.as_std(FramePointer, StackPointer, Frame::callerFPOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
-+ masm.xs_mr(FramePointer, StackPointer);
-+ MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-+
-+ // Burn nops because we have to make this a multiple of 16 and the mfspr
-+ // just screwed us.
-+ masm.as_nop(); // 24
-+ masm.as_nop(); // 28
-+ masm.as_nop(); // 32 // trap point
-+ }
- #else
- {
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
-
- *entry = masm.currentOffset();
-
-@@ -527,16 +554,28 @@ static void GenerateCallableEpilogue(MacroAssembler& masm, unsigned framePushed,
- // use it. Hence we have to do it "by hand".
- masm.Mov(PseudoStackPointer64, vixl::sp);
-
- masm.Ret(ARMRegister(lr, 64));
-
- // See comment at equivalent place in |GenerateCallablePrologue| above.
- masm.SetStackPointer64(stashedSPreg);
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+ masm.as_ld(FramePointer, StackPointer, Frame::callerFPOffset());
-+ poppedFP = masm.currentOffset();
-+ // This is suboptimal since we get serialized, but has to be in this order.
-+ masm.as_ld(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ masm.xs_mtlr(ScratchRegister);
-+ *ret = masm.currentOffset();
-+
-+ masm.as_addi(StackPointer, StackPointer, sizeof(Frame));
-+ masm.as_blr();
-+
- #else
- // Forbid pools for the same reason as described in GenerateCallablePrologue.
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm, /* number of instructions in scope = */ 6);
- # endif
-
- // There is an important ordering constraint here: fp must be repointed to
- // the caller's frame before any field of the frame currently pointed to by
-@@ -773,16 +812,23 @@ void wasm::GenerateJitEntryPrologue(MacroAssembler& masm, Offsets* offsets) {
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
- offsets->begin = masm.currentOffset();
- static_assert(BeforePushRetAddr == 0);
- // Subtract from SP first as SP must be aligned before offsetting.
- masm.Sub(sp, sp, 8);
- masm.storePtr(lr, Address(masm.getStackPointer(), 0));
- masm.adjustFrame(8);
-+#elif defined(JS_CODEGEN_PPC64)
-+ offsets->begin = masm.currentOffset();
-+
-+ // We have to burn a nop here to match the other prologue length.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_nop(); // might as well explicitly wait for the mfspr to complete
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #else
- // The x86/x64 call instruction pushes the return address.
- offsets->begin = masm.currentOffset();
- #endif
- MOZ_ASSERT_IF(!masm.oom(),
- PushedRetAddr == masm.currentOffset() - offsets->begin);
-
- // Save jit frame pointer, so unwinding from wasm to jit frames is trivial.
-diff --git a/js/src/wasm/WasmGC.cpp b/js/src/wasm/WasmGC.cpp
-index 4eb77a81a2..3f00cbb632 100644
---- a/js/src/wasm/WasmGC.cpp
-+++ b/js/src/wasm/WasmGC.cpp
-@@ -284,16 +284,33 @@ bool IsValidStackMapKey(bool debugEnabled, const uint8_t* nextPC) {
- (insn[-1] & 0xfffffc1f) == 0xd63f0000 || // blr reg
- (insn[-1] & 0xfc000000) == 0x94000000 || // bl simm26
- (debugEnabled && insn[-1] == 0xd503201f)); // nop
-
- # elif defined(JS_CODEGEN_MIPS64)
- // TODO (bug 1699696): Implement this. As for the platforms above, we need to
- // enumerate all code sequences that can precede the stackmap location.
- return true;
-+# elif defined(JS_CODEGEN_PPC64)
-+// XXX: we should just be able to use inst[0]
-+ const uint32_t* insn = (const uint32_t*)nextPC;
-+ js::jit::Instruction* inst = (js::jit::Instruction*)nextPC;
-+ //fprintf(stderr, "IsValidStackMapKey: 0x%lx 0x%08x\n", (uint64_t)nextPC, insn[0]);
-+ return (((uintptr_t(insn) & 3) == 0) &&
-+ (inst[0].extractOpcode() == js::jit::PPC_addi || // stack allocate
-+ inst[0].extractOpcode() == js::jit::PPC_addis || // load immediate
-+ inst[0].extractOpcode() == js::jit::PPC_cmpwi || // test after bl
-+ inst[0].extractOpcode() == js::jit::PPC_cmpw || // (extsw, same)
-+ inst[0].extractOpcode() == js::jit::PPC_lfd || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lfs || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lwz || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_ld || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_b || // branch
-+ inst[0].encode() == js::jit::PPC_nop || // GET BACK TO WORK
-+ inst[0].encode() == js::jit::PPC_stop)); // designated throw
- # else
- MOZ_CRASH("IsValidStackMapKey: requires implementation on this platform");
- # endif
- }
- #endif
-
- } // namespace wasm
- } // namespace js
-diff --git a/js/src/wasm/WasmSignalHandlers.cpp b/js/src/wasm/WasmSignalHandlers.cpp
-index 4ab2a44192..1a51061a12 100644
---- a/js/src/wasm/WasmSignalHandlers.cpp
-+++ b/js/src/wasm/WasmSignalHandlers.cpp
-@@ -101,16 +101,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->sc_pc)
- # define RFP_sig(p) ((p)->sc_regs[30])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->sc_frame.fixreg[1])
-+# define R31_sig(p) ((p)->sc_frame.fixreg[31])
- # define R32_sig(p) ((p)->sc_frame.srr0)
- # endif
- #elif defined(__linux__) || defined(__sun)
- # if defined(__linux__)
- # define EIP_sig(p) ((p)->uc_mcontext.gregs[REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.gregs[REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.gregs[REG_ESP])
- # else
-@@ -147,16 +148,17 @@ using mozilla::DebugOnly;
- # if defined(__linux__) && (defined(__sparc__) && defined(__arch64__))
- # define PC_sig(p) ((p)->uc_mcontext.mc_gregs[MC_PC])
- # define FP_sig(p) ((p)->uc_mcontext.mc_fp)
- # define SP_sig(p) ((p)->uc_mcontext.mc_i7)
- # endif
- # if defined(__linux__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.gp_regs[1])
-+# define R31_sig(p) ((p)->uc_mcontext.gp_regs[31])
- # define R32_sig(p) ((p)->uc_mcontext.gp_regs[32])
- # endif
- #elif defined(__NetBSD__)
- # define EIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.__gregs[_REG_ESP])
- # define RIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RIP])
- # define RSP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSP])
-@@ -173,16 +175,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.__gregs[_REG_EPC])
- # define RFP_sig(p) ((p)->uc_mcontext.__gregs[_REG_S8])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->uc_mcontext.__gregs[_REG_R1])
-+# define R31_sig(p) ((p)->uc_mcontext.__gregs[_REG_R31])
- # define R32_sig(p) ((p)->uc_mcontext.__gregs[_REG_PC])
- # endif
- #elif defined(__DragonFly__) || defined(__FreeBSD__) || \
- defined(__FreeBSD_kernel__)
- # define EIP_sig(p) ((p)->uc_mcontext.mc_eip)
- # define EBP_sig(p) ((p)->uc_mcontext.mc_ebp)
- # define ESP_sig(p) ((p)->uc_mcontext.mc_esp)
- # define RIP_sig(p) ((p)->uc_mcontext.mc_rip)
-@@ -207,16 +210,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__FreeBSD__) && defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.mc_pc)
- # define RFP_sig(p) ((p)->uc_mcontext.mc_regs[30])
- # endif
- # if defined(__FreeBSD__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.mc_gpr[1])
-+# define R31_sig(p) ((p)->uc_mcontext.mc_gpr[31])
- # define R32_sig(p) ((p)->uc_mcontext.mc_srr0)
- # endif
- #elif defined(XP_DARWIN)
- # define EIP_sig(p) ((p)->thread.uts.ts32.__eip)
- # define EBP_sig(p) ((p)->thread.uts.ts32.__ebp)
- # define ESP_sig(p) ((p)->thread.uts.ts32.__esp)
- # define RIP_sig(p) ((p)->thread.__rip)
- # define RBP_sig(p) ((p)->thread.__rbp)
-@@ -367,17 +371,17 @@ struct macos_aarch64_context {
- # define PC_sig(p) EPC_sig(p)
- # define FP_sig(p) RFP_sig(p)
- # define SP_sig(p) RSP_sig(p)
- # define LR_sig(p) R31_sig(p)
- #elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define PC_sig(p) R32_sig(p)
- # define SP_sig(p) R01_sig(p)
--# define FP_sig(p) R01_sig(p)
-+# define FP_sig(p) R31_sig(p)
- #endif
-
- static void SetContextPC(CONTEXT* context, uint8_t* pc) {
- #ifdef PC_sig
- *reinterpret_cast<uint8_t**>(&PC_sig(context)) = pc;
- #else
- MOZ_CRASH();
- #endif
-diff --git a/js/src/wasm/WasmStubs.cpp b/js/src/wasm/WasmStubs.cpp
-index 59a5cf18bf..dbc10c6e2c 100644
---- a/js/src/wasm/WasmStubs.cpp
-+++ b/js/src/wasm/WasmStubs.cpp
-@@ -719,17 +719,17 @@ static bool GenerateInterpEntry(MacroAssembler& masm, const FuncExport& fe,
- AssertExpectedSP(masm);
- masm.haltingAlign(CodeAlignment);
-
- offsets->begin = masm.currentOffset();
-
- // Save the return address if it wasn't already saved by the call insn.
- #ifdef JS_USE_LINK_REGISTER
- # if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- masm.pushReturnAddress();
- # elif defined(JS_CODEGEN_ARM64)
- // WasmPush updates framePushed() unlike pushReturnAddress(), but that's
- // cancelled by the setFramePushed() below.
- WasmPush(masm, lr);
- # else
- MOZ_CRASH("Implement this");
- # endif
-@@ -2111,17 +2111,26 @@ static bool GenerateImportInterpExit(MacroAssembler& masm, const FuncImport& fi,
- masm.storePtr(scratch,
- Address(masm.getStackPointer(), i->offsetFromArgBase()));
- }
- i++;
- MOZ_ASSERT(i.done());
-
- // Make the call, test whether it succeeded, and extract the return value.
- AssertStackAlignment(masm, ABIStackAlignment);
-+#ifdef JS_CODEGEN_PPC64
-+ // Because this is calling an ABI-compliant function, we have to pull down
-+ // a dummy linkage area or the values on the stack will be stomped on. The
-+ // minimum size is sufficient.
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), -32);
-+#endif
- masm.call(SymbolicAddress::CallImport_General);
-+#ifdef JS_CODEGEN_PPC64
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), 32);
-+#endif
- masm.branchTest32(Assembler::Zero, ReturnReg, ReturnReg, throwLabel);
-
- ResultType resultType = ResultType::Vector(fi.funcType().results());
- ValType registerResultType;
- for (ABIResultIter iter(resultType); !iter.done(); iter.next()) {
- if (iter.cur().inRegister()) {
- MOZ_ASSERT(!registerResultType.isValid());
- registerResultType = iter.cur().type();
-@@ -2673,16 +2682,21 @@ static const LiveRegisterSet RegsToPreserve(
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // It's correct to use FloatRegisters::AllMask even when SIMD is not enabled;
- // PushRegsInMask strips out the high lanes of the XMM registers in this case,
- // while the singles will be stripped as they are aliased by the larger doubles.
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(Registers::AllMask &
- ~(Registers::SetType(1) << Registers::StackPointer)),
- FloatRegisterSet(FloatRegisters::AllMask));
-+#elif defined(JS_CODEGEN_PPC64)
-+// Note that this includes no SPRs, since the JIT is unaware of them.
-+static const LiveRegisterSet RegsToPreserve(
-+ GeneralRegisterSet(Registers::AllMask),
-+ FloatRegisterSet(FloatRegisters::AllMask));
- #else
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(0), FloatRegisterSet(FloatRegisters::AllDoubleMask));
- # ifdef ENABLE_WASM_SIMD
- # error "no SIMD support"
- # endif
- #endif
-
-diff --git a/modules/libpref/init/StaticPrefList.yaml b/modules/libpref/init/StaticPrefList.yaml
-index d81025b282..43b75c6ae0 100644
---- a/modules/libpref/init/StaticPrefList.yaml
-+++ b/modules/libpref/init/StaticPrefList.yaml
-@@ -5729,17 +5729,17 @@
- - name: javascript.options.baselinejit
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- - name: javascript.options.ion
- type: bool
-- value: true
-+ value: false
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- # The irregexp JIT for regex evaluation.
- - name: javascript.options.native_regexp
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
-@@ -5968,17 +5968,17 @@
- value: 6 * 1024 * 1024
- #else
- value: 2 * 1024 * 1024
- #endif
- mirror: always
-
- - name: javascript.options.wasm_optimizingjit
- type: bool
-- value: true
-+ value: false
- mirror: always
-
- #if defined(ENABLE_WASM_SIMD)
- - name: javascript.options.wasm_simd
- type: bool
- value: true
- mirror: always
- #endif // defined(ENABLE_WASM_SIMD)
diff --git a/srcpkgs/firefox-esr/patches/skia-sucks3.patch b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
index 908311cdb6db..4bf77e684405 100644
--- a/srcpkgs/firefox-esr/patches/skia-sucks3.patch
+++ b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
@@ -30,27 +30,3 @@ diff -r 46ea866ca3ac -r 6ef20eee3f8f gfx/2d/DrawTargetSkia.cpp
mCanvas->saveLayer(saveRec);
SetPermitSubpixelAA(aOpaque);
---- a/gfx/layers/composite/CompositableHost.cpp
-+++ b/gfx/layers/composite/CompositableHost.cpp
-@@ -13,6 +13,7 @@
- #include "ImageHost.h" // for ImageHostBuffered, etc
- #include "Layers.h"
- #include "TiledContentHost.h" // for TiledContentHost
-+#include "mozilla/EndianUtils.h"
- #include "mozilla/gfx/gfxVars.h"
- #include "mozilla/layers/LayersSurfaces.h" // for SurfaceDescriptor
- #include "mozilla/layers/TextureHost.h" // for TextureHost, etc
-@@ -92,9 +93,13 @@ bool CompositableHost::AddMaskEffect(EffectChain& aEffects,
- }
- MOZ_ASSERT(source);
-
-+ // Setting an alpha-mask here breaks the URL-bar on big endian (s390x)
-+ // if the typed URL is too long for the textbox (automatic scrolling needed)
-+#if MOZ_LITTLE_ENDIAN()
- RefPtr<EffectMask> effect =
- new EffectMask(source, source->GetSize(), aTransform);
- aEffects.mSecondaryEffects[EffectTypes::MASK] = effect;
-+#endif
- return true;
- }
-
diff --git a/srcpkgs/firefox-esr/patches/sndio.patch b/srcpkgs/firefox-esr/patches/sndio.patch
deleted file mode 100644
index 68628bea8d8f..000000000000
--- a/srcpkgs/firefox-esr/patches/sndio.patch
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/old-configure.in
-+++ b/old-configure.in
-@@ -2818,6 +2818,22 @@
- _NON_GLOBAL_ACDEFINES="$_NON_GLOBAL_ACDEFINES NECKO_COOKIES"
- fi
-
-+dnl ==================================
-+dnl = Check sndio availability
-+dnl ==================================
-+
-+MOZ_ARG_ENABLE_BOOL(sndio,
-+[ --enable-sndio Enable sndio support],
-+ MOZ_SNDIO=1,
-+ MOZ_SNDIO=)
-+
-+if test -n "$MOZ_SNDIO"; then
-+ MOZ_SNDIO_LIBS="-lsndio"
-+ AC_SUBST_LIST(MOZ_SNDIO_LIBS)
-+fi
-+
-+AC_SUBST(MOZ_SNDIO)
-+
- dnl ========================================================
- dnl =
- dnl = Maintainer debug option (no --enable equivalent)
---- a/media/libcubeb/src/moz.build
-+++ b/media/libcubeb/src/moz.build
-@@ -44,11 +44,13 @@
- ]
- DEFINES['USE_JACK'] = True
-
--if CONFIG['OS_ARCH'] == 'OpenBSD':
-+if CONFIG['MOZ_SNDIO']:
- SOURCES += [
- 'cubeb_sndio.c',
- ]
- DEFINES['USE_SNDIO'] = True
-+
-+if CONFIG['OS_ARCH'] == 'OpenBSD':
- DEFINES['DISABLE_LIBSNDIO_DLOPEN'] = True
-
- if CONFIG['OS_TARGET'] == 'Darwin':
---- a/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-+++ b/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-@@ -88,6 +88,7 @@
- @old_configure_options(
- "--cache-file",
- "--datadir",
-+ "--enable-sndio",
- "--enable-crashreporter",
- "--enable-dbus",
- "--enable-debug-js-modules",
diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template
index 58c065649bc4..502f1096ea8d 100644
--- a/srcpkgs/firefox-esr/template
+++ b/srcpkgs/firefox-esr/template
@@ -3,7 +3,7 @@
# THIS PKG MUST BE SYNCHRONIZED WITH "srcpkgs/firefox-esr-i18n".
#
pkgname=firefox-esr
-version=91.10.0
+version=102.2.0
revision=1
wrksrc="firefox-${version}"
build_helper="rust"
@@ -11,10 +11,8 @@ short_desc="Mozilla Firefox web browser - Extended Support Release"
maintainer="Orphaned <orphan@voidlinux.org>"
license="MPL-2.0, GPL-2.0-or-later, LGPL-2.1-or-later"
homepage="https://www.mozilla.org/firefox/"
-distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz
- https://github.com/chmeeedalf/gecko-dev/files/7729086/esrppcjit.tar.gz"
-checksum="825a8cb38bb5da9821ef87cc6de64af007cf0faef07c4ed0651283b56a0ee1bb
- 5e926a8be5d6d4949c3bc3eb98e2103692eaa26a98928db432b1d44b535f7241"
+distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz"
+checksum="014d91d14ab4f53e93728273b45ac6022813d5ade35f842e722bf87b747c97ff"
lib32disabled=yes
@@ -63,9 +61,6 @@ post_extract() {
;;
esac
- # ppc64le jit, see --enable-jit later
- mv ../js/src/jit/ppc64 js/src/jit
-
# Mozilla API keys (see https://location.services.mozilla.com/api)
# Note: This is for Void Linux use ONLY.
echo -n "cd894504-7a2a-4263-abff-ff73ee89ffca" > mozilla-api-key
@@ -81,21 +76,19 @@ do_build() {
case "$XBPS_TARGET_MACHINE" in
*-musl)
echo "ac_add_options --disable-jemalloc" >>.mozconfig
- echo "ac_add_options --disable-gold" >>.mozconfig
+ echo "ac_add_options --enable-linker=bfd" >>.mozconfig
;;
esac
case "$XBPS_TARGET_MACHINE" in
- x86_64*|i686*|arm*)
+ x86_64*|i686*|arm*|aarch64*)
echo "ac_add_options --disable-elf-hack" >>.mozconfig
;;
esac
# webrtc currently fails to build on 32-bit ppc...
- # also enable jit on ppc64le, which is patched in earlier
- # https://www.talospace.com/2021/12/91esr-with-baseline-compilerbaseline.html
+ # TODO: also enable jit on ppc64le
case "$XBPS_TARGET_MACHINE" in
- ppc64le*) echo "ac_add_options --enable-jit" >>.mozconfig ;;
ppc64*) echo "ac_add_options --disable-jit" >>.mozconfig ;;
ppc*)
echo "ac_add_options --disable-jit" >>.mozconfig
@@ -132,6 +125,10 @@ do_build() {
echo "ac_add_options --host=$XBPS_TRIPLET" >>.mozconfig
fi
+ # XXX: wasi currently not ready
+ # echo "ac_add_options --with-wasi-sysroot=/usr/share/wasi-sysroot" >>.mozconfig
+ echo "ac_add_options --without-wasm-sandboxed-libraries" >>.mozconfig
+
mkdir -p third_party/rust/libloading/.deps
case "$XBPS_TARGET_MACHINE" in
@@ -165,7 +162,7 @@ do_build() {
export MOZ_MAKE_FLAGS="${makejobs}"
export MOZ_NOSPAM=1
export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
export AS=$CC
@@ -184,7 +181,8 @@ ac_add_options --enable-default-toolkit=$(vopt_if wayland 'cairo-gtk3-wayland' '
./mach build
}
do_install() {
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
+ export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
DESTDIR="$DESTDIR" ./mach install
vinstall ${FILESDIR}/vendor.js 644 usr/lib/firefox/browser/defaults/preferences
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PR PATCH] [Updated] firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (7 preceding siblings ...)
2022-09-08 9:18 ` [PR PATCH] [Updated] " oreo639
@ 2022-09-08 11:21 ` oreo639
2022-09-08 16:09 ` classabbyamp
` (4 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 11:21 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1351 bytes --]
There is an updated pull request by oreo639 against master on the void-packages repository
https://github.com/oreo639/void-packages ffesr
https://github.com/void-linux/void-packages/pull/38817
firefox-esr: update to 102.2.0.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with gcc 12 and fixes build with the current cbindgen in the repos.
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
A patch file from https://github.com/void-linux/void-packages/pull/38817.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-ffesr-38817.patch --]
[-- Type: text/x-diff, Size: 247054 bytes --]
From 34dfc955a82ad8561056dca8dce83b8e8b046b2d Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:12:06 -0700
Subject: [PATCH 1/2] firefox-esr-i18n: update to 102.2.0.
---
srcpkgs/firefox-esr-i18n/template | 188 +++++++++++++++---------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/srcpkgs/firefox-esr-i18n/template b/srcpkgs/firefox-esr-i18n/template
index 765303a93236..f518c78f2539 100644
--- a/srcpkgs/firefox-esr-i18n/template
+++ b/srcpkgs/firefox-esr-i18n/template
@@ -1,6 +1,6 @@
# Template file for 'firefox-esr-i18n'
pkgname=firefox-esr-i18n
-version=91.10.0
+version=102.2.0
revision=1
build_style=meta
short_desc="Firefox ESR language packs"
@@ -135,96 +135,96 @@ _pkgtmpl() {
}
}
-checksum="6b47684de4218749d90a07b858ca298b034a2cda10655941e8ba47891d0d95ed
- 54852ef937387cba360fb2bed348c9bc3f1153f7242ad5491ca0b85ee6ed7455
- de66e0263dd0a2d87554fa1d9a406dee5cb3df1a774dffb8636e1be2bd80bc14
- 1f4824ad51a662285ac3a0d8029462a3bf12b36eb0834e65b9276e0869115c09
- a16fc6e0a1bf251ab19b7bbfb620b53437e5bf71b0e7871ed40ace8c97dbf635
- d9057bc71605f2a93d924beb37497195b8ad83501aa4d211ad71106e7b9bce4a
- 36316a7c4ca844ac3e81b2a0bb9ee4952017c2d2404f529848e280d04a21589b
- 150bafd02393355567d75bb9f966900e70502fdddff2822cbbd3bbc1fb3fd785
- 5b69e761666b28e5604d4cf8abc72acf3c3d79abeb7b6230e56aaae775ec225b
- b005c63d5e0d933ef1a4193b75a291a61524a939c3465d41ed111416210eb97f
- d5a2d2fafbfc50e23f5b68d30fcd7376d127f9f697c872d0d7c8e19ee4538cb1
- 16f88ec5de39f982057abcf34f17b22c698453debb62a5a18e0475798fc1cca9
- 84d491f73bc53da4605ee45a8633f14ee5672b9a61c40689d5e3289744a7cb2d
- 7781b6c29923360fd3a95bd2b2532eba7f92bed29640e0276c161eadbe56a13f
- 7984904ede35def33ccf73fda9aa46777c673c4d27de3806873d17694f7f0b13
- 4c57b6eb1cd968ba1eb4b427bed66bab04fb42424d03ae4b892fd3648e255b2e
- a80e9e2a6062bf68106ba1d1b8b7e2ff608ce52fa55d43558e7c073ec1872516
- 2b040ff1d010508760cb4ce4b76cce9e98b4620203c1ef77f87a336ced0aefc7
- 1fa4f5e59a9352f14aefe0cff8e8c4eed4eba16f4d8dbcec6850bce035301c18
- 2da0b09b9bf80f66edc6e3e9d5c1b75fae12905b5193cc64a73bb8bd7bfcbb04
- dce96c9fccb8c857f8cc370f7f5635b1475138195b05e944782b072beebc8d44
- e90dbf86c1823c209def11052995834ed15528dc5c6d3b502ed315dd471a9d5b
- f38624c81f2f9dac4f05b9e9d4d6e7a4e0381a279e3b4c53811aeb1db13cd000
- 221b7f4031a7c120d0ca753d93c41c18ac4f9500ae424c7983e4593497ddbbf8
- 60f5ceb21287a6786a6dd2d177325dfbcc6ca7f9a5df1b9299a2c5bb01d9c172
- 308ce25a9a0a9038dd94c2c22889c54def3937d35eafbcb34b75026cf3de3b8f
- 2d332a6f5bd92017700a15da5fe506612cea03b49f903592fc105fca978cd1d3
- 5cd35666f54a5ae4e35a1ca4c627cec8a47594da4083adf4f06dbe31c20a7444
- 1c1252765cb24f6a0206b648d834566aca9229075f7413f9c7deff1949a99c37
- 002772c46d6a7162e2add4726f105e4c0e355bbb84ce91b07ab02967cc5f1eb4
- 64ce2c0735caf9b67d2be003b1d667bce5ff614653151c617e4d26e349033e3a
- 60bd5f2532700ae9139d4d59a571b72b2806e80630fddb5f4444c7d6e377d2dc
- 2753317b7580ee1a377275905e254084263d0a87bda1bb572537fa75489d92dc
- 7f1b74d2cc5a9c4c6c7864a62eadef2b3d72c5cc2010f5c03bce3a9fae2286dc
- 2232c3b9a8f313145967152bf1dbafd6233593ceb422d2c3277d1b4cfecb6f50
- c41e866f3fc3cf0e0088681b55bb8489de1c5840ca7dc52d1f4f077b53452bd5
- 5d787fd6a9aa06ce31a6823b3393ba7ad66cf3d374dd6eaab3648103e826a10b
- 8d73e01655af7117856374be3669d530af96a79cdb8238bc953688d45e94567c
- 03f2b133746746c328cb7e4055b568d8e99cea51c845136c3f4446840d68e32f
- 691b0e760ebe5269dfa4aa4ea8dd2139260fbb0ca38af4c5438548b7c7ee88f5
- c63492236e75bf984a1671de95dddc954c1b4a1e92f5201c9b333faefae93035
- df9a036c67aecb1ea65f9709a11f6ccdf253451dcbe6b267437c51f422b9df2d
- 32ec78a51439b02f087c12c6be4a9159826113e83774085e800c37b6d7c112aa
- 1e44e3ded5aa07d44f3fdea8cf68bb33fd243cda159384ea8b87e783ed5c9a65
- 1cac44cdec68b56b77aba139a8425f607bac34ae2e09e27ecff2522b16fef44d
- aefb4fbacbdfc749a8d5888f7af48999406f207850fafae8ef39c083e08fa80c
- 753dbcffdf54ce3787a939517b059f11c305edc035bc22f8a9efed6145af6391
- 6c3be5abaf3878390b074970132c4cba935f7160f365cfa98a07e6b882084bdd
- 0b7771965f34c890dea0d2290a283212a1cdc0c8c8044ec634622d52eb595df9
- 0910f98a89b712a40aeb42761f25c763818af05edb5c96e2b6cfba023c28ab73
- 758ab6ea150702ee0d6203a0f75e8baa595c4a0f3d4cb9b87076f732a0e4546f
- d4259375f321b98426885e0b903199dce1f988c74963297bbd1a2aa8f94b0544
- 1614e1288f6d6ce43a7343586141df5e121cff7f1fd703ab4ec40a7f07498843
- 3ae5219a384a872fdbdd8ca5d99ad5370e0d8d87d93f5e39e96c5a2dc26736e3
- 05807b1c17849ffd2a3a63b1e26815dc9463aa3c137f640113530d2662d64116
- e4f3cfb11dfac8ec4caf29f34e20a0c0bb799649fd5b534f22f202c237491f7f
- 80b2b6446590a9fc55ed80a9e07b657cafc5d50294988974747c0e60d41f569b
- 1b32bc1282ded7f6f0f0979cbce3496ed07b1fcad64e70bbbc2eb5d2a8f3953b
- 0f80e3b0a9e17f39560b7cad8280e25c0278935f125d8e724a2381102abff783
- f259ee2683e525051d6f314d4bae4a98c0482a2a443aaac1160b2e0c1326b931
- b9a9eab4c5ea110ccbce20cb88e6652e2cf4c28bfd0aa95907148befd198544d
- a5a6e9bdaad420f281ce5fd16dabf5338d48c7cd8518c38b1e101b79b530fdb9
- a1fe6a2c7606b0720933496cad2bc959693905db87c3a2e5313db82dbfebda7c
- d1b22a495c637d5652c84afe8650d876b4206f2ea0d96751bec684ea63327f98
- e1587dac082479821697d97b4d5cb63a8d1f9189fdc2048885d963aea95b8400
- 6e40a5d5f0cb8794edc5f6a1fae778d89f6dbd97d8a288236d72fa571ffe91c9
- 33b5df625ae13ec35b41bb350e9e66d9ccc04f4d4d8c7e45020344739881e6d8
- e2f271691bb1b9873583175ff303bbaaf05a9d1207fbe8fffc34ec4abcfc1545
- 13382dabc604e99553c98b9e41eb046d4688b15f2ee9dd12c4f9c8967afa62d1
- 77133c69968073fec909dbe9e44d2eaea002cb0d0e142125865d1c03c89ed73d
- f8998128b0c656e72124baeff45c72013953f8314aa4959b6fef8a1b3039647f
- 2f24e5db025c0302fe3b696f280dcbab83728aaccaefe1ff082e165276896296
- d658095fd2d3e4d3decb8c2cdaa64f02fd8b663ba711fb9f2130ed7ed2a97291
- 7c28a82ecdd622653b26a9dd0913ac7d7cebe7246f64874fea2d1fa4af354c2a
- f78694d438032af3ca1a265a089407eb12b431bd314177672a66338b9bf7390f
- ea2d769b90a06400eba3e1f4eec58342fe4450ecce38b1e721923a65bed34337
- 8edf5b04b6cb477f482c14efdbada7023ff7a0ef584a4c30b2350e7825a612a0
- 851db60a218c36b61ee0adfcdc478bc051c95e41a4dba54d43594b8f03c6b187
- 6af72cae7f72ce68c644d49b6a621945f5e8f79119a86bb67ee144585f734925
- 7b01771078ec475b0103fcc4222b0b40eb92ec64180aaad02f2846cfdfb3e319
- 0c4df78eafbbe7ff98d9eff03bb258d1d0f4591102147f643ec395711f35d940
- cf21434f24e221ce58184f43a582c10187eceb7a71da5d81156cc870d78c1f4c
- 839088e2f23f6c62c38c45d5f7012513d95034aa5e6ab28307f152dbc10f97d3
- 4058ae6dd7b556bae2c13bb6fa0c5f16207c6fef4e0802d3d0badae2108a0da8
- d2c473fb93f0c4dc67ae18c25fdc414056bf779038c0f5dd25aa63a9a5cfcd0a
- 6e31c79b9955fd879528b0a614295da69ab26b608275946a4a5a29178a2aed20
- 852fe9ab16d29f7cf8f443bfd65fa1d522a9f27ef8766ad72a0c22a65450dc18
- 9411873b1ea01a1b8656957aedb79137f4c189b9cd3e96626c8e503539cf2c4b
- 5f43106472ae66dc8c0ffc317faba09c2370d4f18837c3cfaf05eb9b03f33b90
- 30f3f50133532ce379b9d5dd0f7e81204905e8a43a27e9d2ac1a26059e393913
- 285f615cc8852fd74bd7693a5a45b106f293c0a2d89836e9f25336ac6376af69
- 190ac7991a8b501fab2654d23b5f6f1e7a5f0cfeb402c8f5fe382d25c2222dc6
- 2de7676c71508ffbb337bdd8ca68f9d2fa1e30f23e8be283b937c5c4e30c59d6"
+checksum="d5a1473ebe95cd18f90ed0d9cf305ee6559a4f224f07cc59f1c5e1de30c65a87
+ c51c457d98da7bb1145456b57826bddb130cbe2a02bd1f9609eede50c5fc47ad
+ c11c1457d9654943003ccbf5669e1b7f78a392719ef1c1179213f517702cc2fd
+ 47f2aaa9ec19525f8877d31fd3dac68347e0ca11b98faacc9fc2cf6ffc09bbd9
+ 221b8508b66ad184a61e11c6278aee0bee6492e4b7bf74cb2daade4f406797f0
+ 5e56b37fa673f72fd7f1e88871337e3faaff871e6b00e31b44aa6ebf1db607a4
+ 93a8c6971f3d313b88954260b5247e666829adc522c6e226cdd7432288728080
+ 6960c4d2f487d57a8163e083f9eba0da20515d9e12942cb3c449948fa2d1bbff
+ dee27babb195f5bf7afdd8571ee6246259555808840d0a29f9dacacc0b6ca5b6
+ 3079b3bbb9c50f6acf5bb4f91846dafdda432a7b26723f170701889dba313820
+ 216171a907c45bd26a78fe071e1eb1666a3e7694888003e507b259bf7a2229c4
+ 47cc7b638478cad28b4e5e027e8f10f309a54abc6b0f4317e878b1376d6a282b
+ a1bfd2f5ef6dfc0d7e19699ebad6af11b6d1e6ed6ce8a0c6176f0f294d136aeb
+ 399c223f82b97e5773df35613d094f0ed73d4a2b99f2fb65936eb5aa8ec3e51a
+ d164ba3d47d79e7bc171d235053c5e51ebb71b199edd389d262fe0ddd991f014
+ 48dffaf3638e4d8c0897a07b105036fcc2ac4e132b999d726d83725c58fb0381
+ 48bf4e31f4abd7a456042566ce772c335f5627618e52614cf8426efb503802c4
+ f4c620403e732346fa66d6dd38d54252d96d924a9c6c1a0da0c077440a4c70ef
+ 4db7491052e565fbe07aa8a37166920fe7b049cef4b7f2774c0b593ff805c0aa
+ ba7f6cca8d7ede6c4562adf9cc3e2896efe08fab6e11ca964c2297e5b01eb6ae
+ b93c9812733e2bf504e77519485c345791836b30958285fdf57c364f1673fcd0
+ 8079d1c5d7e23955e845bc17bc4fbfe2a3456e7ba1a7bd01ff01664d827438e2
+ a53f01d68fca8b58de937256fb962e3b978f5ffd00d2d11b6f2028a529c1f9c9
+ 417ad3babd8e62a74e65dda70d9fd47e4be900e1ea8aba1c960a9736c3ef66a5
+ 6de44c4367e370370cec480e2c3979ccdbb03f32de42bf0e15b7d5336092f2cb
+ 9d12f575e0fe8909d8792f9a4cd66d71435a79e9463a0d1f1f7142b92e0347dd
+ 08fb7caa2676ddf16e81514e660870214db39ae965ebfd9c0a24e055190c1a30
+ dc189ba71869a2052b63d08cfc2ad39fc34f3a035ff5a9910d1d07dd9ffde149
+ 1295ebf8671f823704070d4ff4f7b3eb956c419348ddb4cca1f8a33ade8caece
+ 2277c0000d1237b9159c4cdcf7f2aade52d09e4b3d04d505445dd86861359176
+ 1acc3a9c996bd331d1eefb534da41eb84cbd7a39755f277814bd7ca9609d240d
+ 5d8b9cd48a9ffd104939f4b4cd5c5c5146bcf56067280bd8e49715e95e42d53c
+ 8932a8157b092f196493f62633c3291a9575f722b810f0f9c793bc7690883866
+ fa1312afe79f2ee7f2470b3b101eac6f8689ee494e6d0a9ecc96efa455a09aeb
+ 1802755f0fc08510a0a614b5a32086b942c4ce6d8a90c6145ce6ac0c66fe07e0
+ caf2b000fd9a03732378332dc6599e628a85e44c6f4f982b483f4827fde7a5fe
+ 60c2be815d5994fcfe5133bee2ca79730f7a29fe5238f7300ef49fc941b79062
+ 7ca5bba5f47bf2da6def8d29f832333c09e7ff6c271521916c4ea42dfb6b37da
+ 7bf29d75d905fd8f0b9700de433448dbefb304c8dd181a6560d1ede433040800
+ 591d8c31cab9e3009753d2eb4bf41098a02c5b11b763a633adcb49afaf41ccd0
+ 8cec17c0174a3c9eeb512dd9c88cdf4fb2dc6b68a6e38466f4edb499af524a33
+ 36055161e5df1cde24351eb35269c0aac68c8b279116cc984cc93c9b01e196f9
+ 9533f3f7c4dec42e36fe3dcf31a7f00ac1bdda64e4ea47c0a563c4b33d6b9606
+ 80e176922404452a5f0871d493fa0e8bf7b2a2fdb317e3cd017595ffde131793
+ 4ddfc3938943c8e2d1f2b38f04566c264f1f7b6faf38456a8973937eec4f770b
+ 1c257033946f3316d1a6ad3a700b124f9f36f0ace5f9d1fec50c391ab7fd3721
+ 6d7d300c1ce9928669a3b837479e9aa8c7ef4cef113839f6e17684c58153fbc0
+ 00ea98387fc098f4fb5a7cd3e42aac5a9ce62c77805d371c489cff5ba4393d2d
+ 8f4c302dda19be2ce6704b205243c7e27e77129992bc78db330855e4aebb56a9
+ 42a0495577b5874363faf0117ef406bdee63f8274f3475f8746ec50ef601f895
+ 48c853fcb62a8fb9743fea55b3db579917130acaf0749e1e61245941e80cab62
+ 2c9cf98785c43fa49df30c7d5253c7abf90dd856ec19529a6f76bd2e19f818fc
+ e38cffcc6802078e04324846fffddbfb33c66ebcca7179a26beacfa52262681d
+ 9267b8a3a4231f45e50e9f0f3eb803e1210eae7168f57e6bb668fda47a3914b1
+ d3828f3fc4e8f198a4d05e59952f5dc2790dc0b9472a2cfc1b70d668d8af75ee
+ eb20c6ef5ed9e58d17d55f978ae9b31273ba909aee23ab88726afa0569f047c2
+ 2c8c417e039579f7a5191a9ac763cd37101b6ffa0ef34ab9e4241454304a6b99
+ eb49f9396fffabf2824b008894a1f88d5304220bba420418c48c03e50570d381
+ 6c06668712b03657604d55720a876cf63ebc0809a776578f0d2567cb284aae3f
+ 9e81cb09e69da35f9d3a2c5692f747c77963e7a79ff18bfea06abaed69c7b40f
+ f229adf1ab6a2ca65b90899bf825b50a95637b1013fd13c46baf16b2927e0ca5
+ fb29d32429f5fcfe4081f539f00132b850d8231ba8caae84ee74cccf32f8f8e6
+ 48cb704832c25635a4c02877b8dcf26216f519f68b878daa83e3580dd5fd77ee
+ e284ff3a5dab91f30cfeafd3f8aa5d1bd39aa56e8e99fdd86e34928f3414e531
+ 074969a45f46475100ae4956020ef71ad749ad3c02c9a8a6270a4a7ff915fe5c
+ 74825698f655180440e8c28eb317090555fd326eb19cca3c3369297cc2db193c
+ 3bdc7711751357f5211ade94f5c4ed1422811ad41f8d751c0e96c619d787d3c6
+ 578bb94490bef477b1c2f3fe1e47e1b57cf5bfaab937cad40859164141e1ca01
+ 5650824ee3e48839bd6429fefc744d1cda0123e0a2f1414042e5ad40f040fd71
+ fc41f0e9c8f1225666b1d6ceb7d30a21d80f39d89cbed65443afdf976840e3ce
+ 855e130f9b3b4a22d253df8b11bf20cd4528c67dc049b414667505e4eec5b3f9
+ 4cb1f99c98d078774ad389a086f1fec3957033be8ddfea80d57ccc2b2fcd912b
+ 618da6ad432aad58c2a2b8fa3fd2eabf46b9be1bf6db06b5b892adf76d616afb
+ 75f8701df6519a294d17799fe3ecb9d02177af56b0274269eddc6f4f1809bd11
+ 4f68f7af30eacf130c43a5ec14f1ca573eeb0fcb1c9242fc28e1b5ccf4274eaf
+ a6b37e3056a7845ddd49de9f0ef332bc5749477da6fee788f17e1db88c349b4f
+ 9e7418e4ba553811c54a3a04cb85c680016285291a1671abff0e81017af1d749
+ 090ea71643b074ddb6717531095e2c3cf7a2a4eaab2d729d0d3bfc28058bad8a
+ eaba5ef15835c68ec07580b8523819ba07e03ae3af25ac5c10193e3179c73bf4
+ 803e2969f15a3d738f65cbbf9d3054a039f9381327f9007e8590754f7419e70c
+ 4ab75978d8ec20846503002d3bbc959b12717695898fba5d53b1a80f5cd7a820
+ 2c15fac71576bad1e80838ee0969572bf2c15bf729356d23ae54515e16901e52
+ 145f1e77d894d1fc120bdcd6582a72f971909789506d9ae5b1997c57d27d50c6
+ 0e9b73e34ce7ca39253d1e0ded022c05654841aa61c34c284906492d4bbe27da
+ 337dab583aa1d3d524b9241ce5e94b7fe54c41dc86f0ea5c8c6b021fa3b66c66
+ 58b361eeac66c68cb3728b68afebe0648559ac6552d8cfaed3cb35a952c9fb2b
+ d8531ee94abe01ea46641f1e7eb13fffa8d81228c14ca074990e7ea4c10dcd53
+ 407ea5363696ef77fc0cffa7f5c27e78025f69248d82ac85f82452a7f5466502
+ 9e5be4dd61ec9ab0b3fad41ddf28a4cc16a97e6450ace4f112c0b843f143acbb
+ 582126ed73f312529608a44fe46935d10957cd5d46fefa7ca33b93e2a4283d84
+ 2a36bbcdc59adbf948bd5ae3176739cd5dee91f661546fffe4041a294152d4cf
+ 5e32e063c559910c5bf49bf835c47d69584a6b552a3b031433ca880618834ab9
+ 60a96f115e5cdca96e333d83955ad3e24860c61f212ada5954ef62072a9a9d85"
From eab9dfd60f0988c97381cc91cf68e6779b74cd64 Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:13:13 -0700
Subject: [PATCH 2/2] firefox-esr: update to 102.2.0.
---
.../patches/fix-build-rust-simd2.patch | 729 ++++
.../firefox-esr/patches/fix-cbindgen.patch | 22 +
...n-path.patch => fix-firefox-desktop.patch} | 11 +-
srcpkgs/firefox-esr/patches/fix-tools.patch | 13 -
.../patches/fix-webrtc-glibcisms.patch | 24 +-
srcpkgs/firefox-esr/patches/ppc64le-jit.patch | 3441 -----------------
srcpkgs/firefox-esr/patches/skia-sucks3.patch | 24 -
srcpkgs/firefox-esr/patches/sndio.patch | 52 -
srcpkgs/firefox-esr/template | 30 +-
9 files changed, 786 insertions(+), 3560 deletions(-)
create mode 100644 srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
create mode 100644 srcpkgs/firefox-esr/patches/fix-cbindgen.patch
rename srcpkgs/firefox-esr/patches/{fix-desktop-icon-path.patch => fix-firefox-desktop.patch} (64%)
delete mode 100644 srcpkgs/firefox-esr/patches/fix-tools.patch
delete mode 100644 srcpkgs/firefox-esr/patches/ppc64le-jit.patch
delete mode 100644 srcpkgs/firefox-esr/patches/sndio.patch
diff --git a/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
new file mode 100644
index 000000000000..e20e6bf6026d
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
@@ -0,0 +1,729 @@
+From ada04eb9b82531a41553b6ffc2ba3194c70fdc45 Mon Sep 17 00:00:00 2001
+From: Mike Hommey <mh+mozilla@glandium.org>
+Date: Wed, 24 Aug 2022 06:58:59 +0000
+Subject: [PATCH] Bug 1783784 - Update packed_simd_2 to 0.3.8.
+
+Differential Revision: https://phabricator.services.mozilla.com/D154063
+---
+ .cargo/config.in | 2 +-
+ Cargo.lock | 5 +-
+ Cargo.toml | 2 +-
+ .../rust/packed_simd_2/.cargo-checksum.json | 2 +-
+ third_party/rust/packed_simd_2/Cargo.toml | 5 +-
+ third_party/rust/packed_simd_2/README.md | 2 +-
+ third_party/rust/packed_simd_2/build.rs | 5 +
+ third_party/rust/packed_simd_2/src/api.rs | 4 +-
+ third_party/rust/packed_simd_2/src/codegen.rs | 50 +++++-----
+ .../packed_simd_2/src/codegen/bit_manip.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/llvm.rs | 98 +++++++++----------
+ .../rust/packed_simd_2/src/codegen/math.rs | 2 +-
+ .../packed_simd_2/src/codegen/math/float.rs | 28 +++---
+ .../src/codegen/math/float/abs.rs | 2 +-
+ .../src/codegen/math/float/cos.rs | 2 +-
+ .../src/codegen/math/float/cos_pi.rs | 2 +-
+ .../src/codegen/math/float/exp.rs | 2 +-
+ .../src/codegen/math/float/ln.rs | 2 +-
+ .../src/codegen/math/float/mul_add.rs | 2 +-
+ .../src/codegen/math/float/mul_adde.rs | 2 +-
+ .../src/codegen/math/float/powf.rs | 2 +-
+ .../src/codegen/math/float/sin.rs | 2 +-
+ .../src/codegen/math/float/sin_cos_pi.rs | 2 +-
+ .../src/codegen/math/float/sin_pi.rs | 2 +-
+ .../src/codegen/math/float/sqrt.rs | 2 +-
+ .../src/codegen/math/float/sqrte.rs | 2 +-
+ .../src/codegen/pointer_sized_int.rs | 24 ++---
+ .../packed_simd_2/src/codegen/reductions.rs | 2 +-
+ .../src/codegen/reductions/mask.rs | 4 +-
+ .../packed_simd_2/src/codegen/swap_bytes.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/vPtr.rs | 2 +-
+ third_party/rust/packed_simd_2/src/lib.rs | 7 +-
+ third_party/rust/packed_simd_2/src/testing.rs | 2 +-
+ 33 files changed, 144 insertions(+), 136 deletions(-)
+
+diff --git a/.cargo/config.in b/.cargo/config.in
+index a6e396b29f764..2e5bad6fed2c6 100644
+--- a/.cargo/config.in
++++ b/.cargo/config.in
+@@ -70,7 +70,7 @@ rev = "746743227485a83123784df0c53227ab466612ed"
+ [source."https://github.com/hsivonen/packed_simd"]
+ git = "https://github.com/hsivonen/packed_simd"
+ replace-with = "vendored-sources"
+-rev = "c149d0a519bf878567c7630096737669ec2ff15f"
++rev = "f38664024b29d44c506431eada7c112629bb1aa9"
+
+ [source."https://github.com/hsivonen/chardetng_c"]
+ git = "https://github.com/hsivonen/chardetng_c"
+diff --git a/Cargo.lock b/Cargo.lock
+index 0560a3c86be85..ebec60085c0c0 100644
+--- a/Cargo.lock
++++ b/Cargo.lock
+@@ -3812,10 +3812,11 @@ dependencies = [
+
+ [[package]]
+ name = "packed_simd_2"
+-version = "0.3.7"
+-source = "git+https://github.com/hsivonen/packed_simd?rev=c149d0a519bf878567c7630096737669ec2ff15f#c149d0a519bf878567c7630096737669ec2ff15f"
++version = "0.3.8"
++source = "git+https://github.com/hsivonen/packed_simd?rev=f38664024b29d44c506431eada7c112629bb1aa9#f38664024b29d44c506431eada7c112629bb1aa9"
+ dependencies = [
+ "cfg-if 1.0.0",
++ "rustc_version",
+ ]
+
+ [[package]]
+diff --git a/Cargo.toml b/Cargo.toml
+index de7ee7ac7cc1f..f576534bf3f8b 100644
+--- a/Cargo.toml
++++ b/Cargo.toml
+@@ -113,7 +113,7 @@ chardetng_c = { git = "https://github.com/hsivonen/chardetng_c", rev="ed8a4c6f90
+ coremidi = { git = "https://github.com/chris-zen/coremidi.git", rev="fc68464b5445caf111e41f643a2e69ccce0b4f83" }
+ fog = { path = "toolkit/components/glean/api" }
+ libudev-sys = { path = "dom/webauthn/libudev-sys" }
+-packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="c149d0a519bf878567c7630096737669ec2ff15f" }
++packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="f38664024b29d44c506431eada7c112629bb1aa9" }
+ midir = { git = "https://github.com/mozilla/midir.git", rev = "4c11f0ffb5d6a10de4aff40a7b81218b33b94e6f" }
+ minidump_writer_linux = { git = "https://github.com/rust-minidump/minidump-writer.git", rev = "75ada456c92a429704691a85e1cb42fef8cafc0d" }
+
+diff --git a/third_party/rust/packed_simd_2/.cargo-checksum.json b/third_party/rust/packed_simd_2/.cargo-checksum.json
+index 3090b655a160c..079b4c559f5ee 100644
+--- a/third_party/rust/packed_simd_2/.cargo-checksum.json
++++ b/third_party/rust/packed_simd_2/.cargo-checksum.json
+@@ -1 +1 @@
+-{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"f85e54e13a05f6e4f27c230ab81430af27b6ff80a1c036bd70c42ea115f89487","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"882f8894b333becf490d23c9024a86fd1327c8edea33aa8dbb98dc2f2ddb3956","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"019ed29c43989782d8eec3a961654cfc172d7a7898da4eca8f654700af7e1988","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"f6e92f056565e6fd93f98829a408aee9e790251e0cbd8a8bc30c8662b4d6fabb","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"a29d38fa0a85eaf787fb49989e625bf64effd5f39c126fbb2a24be206d2a3917","src/codegen/bit_manip.rs":"9991570a21ca98134b08b5c5935e2c259cea39c82d9d1529f52c561a84fec642","src/codegen/llvm.rs":"5bc6751293f9f184cf23d5df448c7d58b58b799e41c7a91f8ca41a5ba56e64ec","src/codegen/math.rs":"35f96e37a78fcf0cdb02146b7f27a45108fe06a37fc2a54d8851ce131a326178","src/codegen/math/float.rs":"dd86c0449e576c83b719700962ac017c332987fac08d91f2b7a2b1b883598170","src/codegen/math/float/abs.rs":"f56e2b4b8055ea861c1f5cbc6b6e1d8e7e5af163b62c13574ddee4e09513bfbc","src/codegen/math/float/cos.rs":"ef3b511a24d23045b310315e80348a9b7fedb576fc2de52d74290616a0abeb2a","src/codegen/math/float/cos_pi.rs":"4e7631a5d73dac21531e09ef1802d1180f8997509c2c8fa9f67f322194263a97","src/codegen/math/float/exp.rs":"61b691598c41b5622f24e4320c1bdd08701e612a516438bdddcc728fc3405c8c","src/codegen/math/float/ln.rs":"46b718b1ba8c9d99e1ad40f53d20dfde08a3063ca7bd2a9fdd6698e060da687e","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"a37bf764345d4b1714f97e83897b7cf0855fc2811704bcbc0012db91825339e1","src/codegen/math/float/mul_adde.rs":"9aa6ed39825e61edb2522e002c59c9392d7c655c01af1cf8380ba22c8ddf69cd","src/codegen/math/float/powf.rs":"642346e982bc4c39203de0864d2149c4179cd7b21cf67a2951687932b4675872","src/codegen/math/float/sin.rs":"9d68164c90cdca6a85155040cdac42e27342ebe0b925273ef1593df721af4258","src/codegen/math/float/sin_cos_pi.rs":"e0c661d1d894fd4018723b9f3143ab6771c9405e41907cb1a7b9f9b380a97523","src/codegen/math/float/sin_pi.rs":"9890347905b4d4a3c7341c3eb06406e46e60582bcf6960688bd727e5dadc6c57","src/codegen/math/float/sqrt.rs":"e3c60dcfb0c6d2fc62adabcc931b2d4040b83cab294dea36443fb4b89eb79e34","src/codegen/math/float/sqrte.rs":"f0f4ef9eb475ae41bcc7ec6a95ad744ba6b36925faa8b2c2814004396d196b63","src/codegen/pointer_sized_int.rs":"a70697169c28218b56fd2e8d5353f2e00671d1150d0c8cef77d613bdfacd84cb","src/codegen/reductions.rs":"645e2514746d01387ddd07f0aa4ffd8430cc9ab428d4fb13773ea319fa25dd95","src/codegen/reductions/mask.rs":"dd68fd8bc5335fa2d0405e59dd1e9fff16fdf7651aa8db670ca86145fd5b5dda","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"ac659780deb0c52daa9c73afb4ba8645c9fa35350cd897b23e567860492553b7","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"711c753a08d53a2879c4fb87a0762c46ce4e34c22f0ca88d2e4c557a0f679969","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"5efc09cb3d164e4e38b71fd4999afbfd234f5080dc84ce22fda2fc15d381e8c7","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"1d3a7862ef625e235a5734ad7204e68d350f902c0695182b1f08a0552432416e","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
++{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"e76b42f3247fccb7174046c499bfaae5430d83cadeb8140259fcae34613483cf","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"fa4dd64f66972217d35b7653338c9e2011ccd8f3008ae7c0103272d4287f9b1d","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"a766fba121243a9b617432c592873801adb74c3a2f4a24d9d45859b8ce9357fc","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"bb1795e9657a8298d37d2349b45443f08e9e455399ad4b727018600728478c10","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"db4f232fb9f5728db310b87dc8c4733be48afacab1053798c06106bef9a42b05","src/codegen/bit_manip.rs":"525ea6ff7ad1e043b6f6136992166f1803ed5563b7f6fc292c1c40257d20e264","src/codegen/llvm.rs":"b4ccbc0bad90038f00fc3c158736462d01d0053df3afa00f9169e67d1a264444","src/codegen/math.rs":"dfcf02ad34e2fdfe22c3f1cc2822001cc895e65031b4d06e585e5047839febb7","src/codegen/math/float.rs":"2c1cbce155bc527ce34d472c0fef6bc3dadb79cd7a357dd7aa5b1ebeb1d77a13","src/codegen/math/float/abs.rs":"d5aaadcf540bdb9b4264dca6471a255fd7bf509e763bef0239c0144a68466fea","src/codegen/math/float/cos.rs":"17f28d2900c852dca221fa9c92a9cd5fe7fd2df8d427bbc60216c749b2be013d","src/codegen/math/float/cos_pi.rs":"dbaf9f443f9846a491d4ec52210a7b5835dd593b03366e3135b05c37d70f9d6c","src/codegen/math/float/exp.rs":"d300058a4bcc7ae7976f216f81902cd73a9e603ad63880dff3bbc866c27a9f37","src/codegen/math/float/ln.rs":"c851e211e43f8256093ba75b03ae0c307c9962ee66d94f09b4dd80068190cbdf","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"041a5b69d5991d93ef795351b17560c10faf80b78fd26ad7df42a239b32cf9de","src/codegen/math/float/mul_adde.rs":"d71d5f0f3333b62a7439b823cb7adf5340ea1555ce820fb4a3f4cb922f73f5f5","src/codegen/math/float/powf.rs":"9742c3877f1a5509ca5c9492a40884b6579ba6dd11c26b7112e63f70666b395d","src/codegen/math/float/sin.rs":"0e9868d35531566509f3a01d85d5253045eb4afa8525d8407dcc1f5f33c56036","src/codegen/math/float/sin_cos_pi.rs":"8e6b6142d7dd240cdb36669722e82ab9810a2261e86e659f7d97a942ad8b1258","src/codegen/math/float/sin_pi.rs":"bb6d39db8f921e03a301fc5206ac1a61a97def8a2cb83b87ccf189f3fc48d548","src/codegen/math/float/sqrt.rs":"e6ebb0c5f428efad1f672b9a8fe4e58534dbf1ea5a8fe092ce5ce76b52fe89cb","src/codegen/math/float/sqrte.rs":"23acfaea38d0e081a6d9021c1094e813d0cfd12c58c1eca9662aade5e625d51c","src/codegen/pointer_sized_int.rs":"6ca13c214b6cf7e0929dbe18e96a16fc0bb7d8799608df29c4c8115490f99e01","src/codegen/reductions.rs":"8eb18ebac76985d2aa30262a2edd8cb004230b511a765d657525f677a585c12c","src/codegen/reductions/mask.rs":"e67f35a1f4d156a4894a2d6ea5a935b4d898cf70eefb2715f5c1cc165e776c11","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"c67c86e91ca3fc77539e0efcea081a3c62548cccf503963ae408f2e86f4e6a21","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"f0753b405cdc865bdf8e82c6505f299ea1f96136239ebbaf7f9ce93d310764b8","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"b6f846d5d30cf6b035a2d18039aba7b2045cf89384733d643572bd68873ae064","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"896669c08d8c801448a4d2fadc9d633eda0fbe879d229997e2a182e31278e469","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
+diff --git a/third_party/rust/packed_simd_2/Cargo.toml b/third_party/rust/packed_simd_2/Cargo.toml
+index f38706d05002e..49338742dc1ff 100644
+--- a/third_party/rust/packed_simd_2/Cargo.toml
++++ b/third_party/rust/packed_simd_2/Cargo.toml
+@@ -1,6 +1,6 @@
+ [package]
+ name = "packed_simd_2"
+-version = "0.3.7"
++version = "0.3.8"
+ description = "Portable Packed SIMD vectors"
+ documentation = "https://docs.rs/crate/packed_simd/"
+ homepage = "https://github.com/rust-lang/packed_simd"
+@@ -23,6 +23,9 @@ maintenance = { status = "experimental" }
+ cfg-if = "1.0.0"
+ core_arch = { version = "0.1.5", optional = true }
+
++[build-dependencies]
++rustc_version = "0.2"
++
+ [features]
+ default = []
+ into_bits = []
+diff --git a/third_party/rust/packed_simd_2/README.md b/third_party/rust/packed_simd_2/README.md
+index 41a1512d79fbc..eb3101c33d159 100644
+--- a/third_party/rust/packed_simd_2/README.md
++++ b/third_party/rust/packed_simd_2/README.md
+@@ -8,7 +8,7 @@ If you need to continue to use the crate, we have published a "next version" und
+
+ Adjust your `[dependencies]` section of `Cargo.toml` to be the following:
+ ```toml
+-packed_simd = { version = "0.3.6", package = "packed_simd_2" }
++packed_simd = { version = "0.3.8", package = "packed_simd_2" }
+ ```
+
+ # `Simd<[T; N]>`
+diff --git a/third_party/rust/packed_simd_2/build.rs b/third_party/rust/packed_simd_2/build.rs
+index e87298a2de237..afdee9f55b62b 100644
+--- a/third_party/rust/packed_simd_2/build.rs
++++ b/third_party/rust/packed_simd_2/build.rs
+@@ -1,6 +1,11 @@
++use rustc_version::{version, Version};
++
+ fn main() {
+ let target = std::env::var("TARGET").expect("TARGET environment variable not defined");
+ if target.contains("neon") {
+ println!("cargo:rustc-cfg=libcore_neon");
+ }
++ if version().unwrap() < Version::parse("1.61.0-alpha").unwrap() {
++ println!("cargo:rustc-cfg=aarch64_target_feature");
++ }
+ }
+diff --git a/third_party/rust/packed_simd_2/src/api.rs b/third_party/rust/packed_simd_2/src/api.rs
+index 4e9c4292e06ca..aa1403e6e243d 100644
+--- a/third_party/rust/packed_simd_2/src/api.rs
++++ b/third_party/rust/packed_simd_2/src/api.rs
+@@ -2,7 +2,7 @@
+
+ #[macro_use]
+ mod bitmask;
+-crate mod cast;
++pub(crate) mod cast;
+ #[macro_use]
+ mod cmp;
+ #[macro_use]
+@@ -37,7 +37,7 @@ mod swap_bytes;
+ mod bit_manip;
+
+ #[cfg(feature = "into_bits")]
+-crate mod into_bits;
++pub(crate) mod into_bits;
+
+ macro_rules! impl_i {
+ ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+diff --git a/third_party/rust/packed_simd_2/src/codegen.rs b/third_party/rust/packed_simd_2/src/codegen.rs
+index 9d1517e203d19..8a9e971486d74 100644
+--- a/third_party/rust/packed_simd_2/src/codegen.rs
++++ b/third_party/rust/packed_simd_2/src/codegen.rs
+@@ -1,19 +1,19 @@
+ //! Code-generation utilities
+
+-crate mod bit_manip;
+-crate mod llvm;
+-crate mod math;
+-crate mod reductions;
+-crate mod shuffle;
+-crate mod shuffle1_dyn;
+-crate mod swap_bytes;
++pub(crate) mod bit_manip;
++pub(crate) mod llvm;
++pub(crate) mod math;
++pub(crate) mod reductions;
++pub(crate) mod shuffle;
++pub(crate) mod shuffle1_dyn;
++pub(crate) mod swap_bytes;
+
+ macro_rules! impl_simd_array {
+ ([$elem_ty:ident; $elem_count:expr]:
+ $tuple_id:ident | $($elem_tys:ident),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id($(crate $elem_tys),*);
++ pub struct $tuple_id($(pub(crate) $elem_tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl crate::sealed::Seal for [$elem_ty; $elem_count] {}
+@@ -35,28 +35,28 @@ macro_rules! impl_simd_array {
+ }
+ }
+
+-crate mod pointer_sized_int;
++pub(crate) mod pointer_sized_int;
+
+-crate mod v16;
+-crate use self::v16::*;
++pub(crate) mod v16;
++pub(crate) use self::v16::*;
+
+-crate mod v32;
+-crate use self::v32::*;
++pub(crate) mod v32;
++pub(crate) use self::v32::*;
+
+-crate mod v64;
+-crate use self::v64::*;
++pub(crate) mod v64;
++pub(crate) use self::v64::*;
+
+-crate mod v128;
+-crate use self::v128::*;
++pub(crate) mod v128;
++pub(crate) use self::v128::*;
+
+-crate mod v256;
+-crate use self::v256::*;
++pub(crate) mod v256;
++pub(crate) use self::v256::*;
+
+-crate mod v512;
+-crate use self::v512::*;
++pub(crate) mod v512;
++pub(crate) use self::v512::*;
+
+-crate mod vSize;
+-crate use self::vSize::*;
++pub(crate) mod vSize;
++pub(crate) use self::vSize::*;
+
+-crate mod vPtr;
+-crate use self::vPtr::*;
++pub(crate) mod vPtr;
++pub(crate) use self::vPtr::*;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+index 5986916da4387..32d8d717a0766 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+@@ -1,7 +1,7 @@
+ //! LLVM bit manipulation intrinsics.
+ #[rustfmt::skip]
+
+-use crate::*;
++pub(crate) use crate::*;
+
+ #[allow(improper_ctypes, dead_code)]
+ extern "C" {
+@@ -147,7 +147,7 @@ extern "C" {
+ fn ctpop_u128x4(x: u128x4) -> u128x4;
+ }
+
+-crate trait BitManip {
++pub(crate) trait BitManip {
+ fn ctpop(self) -> Self;
+ fn ctlz(self) -> Self;
+ fn cttz(self) -> Self;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/llvm.rs b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+index 52b11a95b9172..b4c09849bc4a3 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/llvm.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+@@ -76,53 +76,53 @@ where
+ }
+
+ extern "platform-intrinsic" {
+- crate fn simd_eq<T, U>(x: T, y: T) -> U;
+- crate fn simd_ne<T, U>(x: T, y: T) -> U;
+- crate fn simd_lt<T, U>(x: T, y: T) -> U;
+- crate fn simd_le<T, U>(x: T, y: T) -> U;
+- crate fn simd_gt<T, U>(x: T, y: T) -> U;
+- crate fn simd_ge<T, U>(x: T, y: T) -> U;
+-
+- crate fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
+- crate fn simd_extract<T, U>(x: T, idx: u32) -> U;
+-
+- crate fn simd_cast<T, U>(x: T) -> U;
+-
+- crate fn simd_add<T>(x: T, y: T) -> T;
+- crate fn simd_sub<T>(x: T, y: T) -> T;
+- crate fn simd_mul<T>(x: T, y: T) -> T;
+- crate fn simd_div<T>(x: T, y: T) -> T;
+- crate fn simd_rem<T>(x: T, y: T) -> T;
+- crate fn simd_shl<T>(x: T, y: T) -> T;
+- crate fn simd_shr<T>(x: T, y: T) -> T;
+- crate fn simd_and<T>(x: T, y: T) -> T;
+- crate fn simd_or<T>(x: T, y: T) -> T;
+- crate fn simd_xor<T>(x: T, y: T) -> T;
+-
+- crate fn simd_reduce_add_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_min<T, U>(x: T) -> U;
+- crate fn simd_reduce_max<T, U>(x: T) -> U;
+- crate fn simd_reduce_min_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_max_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_and<T, U>(x: T) -> U;
+- crate fn simd_reduce_or<T, U>(x: T) -> U;
+- crate fn simd_reduce_xor<T, U>(x: T) -> U;
+- crate fn simd_reduce_all<T>(x: T) -> bool;
+- crate fn simd_reduce_any<T>(x: T) -> bool;
+-
+- crate fn simd_select<M, T>(m: M, a: T, b: T) -> T;
+-
+- crate fn simd_fmin<T>(a: T, b: T) -> T;
+- crate fn simd_fmax<T>(a: T, b: T) -> T;
+-
+- crate fn simd_fsqrt<T>(a: T) -> T;
+- crate fn simd_fma<T>(a: T, b: T, c: T) -> T;
+-
+- crate fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
+- crate fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
+-
+- crate fn simd_bitmask<T, U>(value: T) -> U;
++ pub(crate) fn simd_eq<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ne<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_lt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_le<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_gt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ge<T, U>(x: T, y: T) -> U;
++
++ pub(crate) fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
++ pub(crate) fn simd_extract<T, U>(x: T, idx: u32) -> U;
++
++ pub(crate) fn simd_cast<T, U>(x: T) -> U;
++
++ pub(crate) fn simd_add<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_sub<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_mul<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_div<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_rem<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shl<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shr<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_and<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_or<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_xor<T>(x: T, y: T) -> T;
++
++ pub(crate) fn simd_reduce_add_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_min<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_min_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_and<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_or<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_xor<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_all<T>(x: T) -> bool;
++ pub(crate) fn simd_reduce_any<T>(x: T) -> bool;
++
++ pub(crate) fn simd_select<M, T>(m: M, a: T, b: T) -> T;
++
++ pub(crate) fn simd_fmin<T>(a: T, b: T) -> T;
++ pub(crate) fn simd_fmax<T>(a: T, b: T) -> T;
++
++ pub(crate) fn simd_fsqrt<T>(a: T) -> T;
++ pub(crate) fn simd_fma<T>(a: T, b: T, c: T) -> T;
++
++ pub(crate) fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
++ pub(crate) fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
++
++ pub(crate) fn simd_bitmask<T, U>(value: T) -> U;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math.rs b/third_party/rust/packed_simd_2/src/codegen/math.rs
+index f3997c7f11359..9a0ea7a4e2d24 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math.rs
+@@ -1,3 +1,3 @@
+ //! Vertical math operations
+
+-crate mod float;
++pub(crate) mod float;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float.rs b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+index 5e89bf6ae6b0c..ffbf18bfe989d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+@@ -2,17 +2,17 @@
+ #![allow(clippy::useless_transmute)]
+
+ #[macro_use]
+-crate mod macros;
+-crate mod abs;
+-crate mod cos;
+-crate mod cos_pi;
+-crate mod exp;
+-crate mod ln;
+-crate mod mul_add;
+-crate mod mul_adde;
+-crate mod powf;
+-crate mod sin;
+-crate mod sin_cos_pi;
+-crate mod sin_pi;
+-crate mod sqrt;
+-crate mod sqrte;
++pub(crate) mod macros;
++pub(crate) mod abs;
++pub(crate) mod cos;
++pub(crate) mod cos_pi;
++pub(crate) mod exp;
++pub(crate) mod ln;
++pub(crate) mod mul_add;
++pub(crate) mod mul_adde;
++pub(crate) mod powf;
++pub(crate) mod sin;
++pub(crate) mod sin_cos_pi;
++pub(crate) mod sin_pi;
++pub(crate) mod sqrt;
++pub(crate) mod sqrte;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+index bc4421f61de2d..34aacc25be75a 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Abs {
++pub(crate) trait Abs {
+ fn abs(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+index 50f6c16da2555..dec390cb74d46 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Cos {
++pub(crate) trait Cos {
+ fn cos(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+index ebff5fd1c7510..e283280ee44b1 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait CosPi {
++pub(crate) trait CosPi {
+ fn cos_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+index 00d10e9fa6440..a7b20580e3f1e 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Exp {
++pub(crate) trait Exp {
+ fn exp(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+index 88a5a6c6c1589..a5e38cb40d1ed 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Ln {
++pub(crate) trait Ln {
+ fn ln(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+index f48a57dc46c69..d37f30fa86140 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+@@ -4,7 +4,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_add
+
+-crate trait MulAdd {
++pub(crate) trait MulAdd {
+ fn mul_add(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+index b030c26ccf465..c0baeacec20be 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+@@ -3,7 +3,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_adde
+
+-crate trait MulAddE {
++pub(crate) trait MulAddE {
+ fn mul_adde(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+index bc15067d73a30..89ca52e96d818 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Powf {
++pub(crate) trait Powf {
+ fn powf(self, x: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+index 7b014d07da8d9..d881415909afe 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sin {
++pub(crate) trait Sin {
+ fn sin(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+index 75c2c2c5fbb03..b283d11111fd5 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinCosPi: Sized {
++pub(crate) trait SinCosPi: Sized {
+ type Output;
+ fn sin_cos_pi(self) -> Self::Output;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+index 72df98c93c91e..0c8f6bb120503 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinPi {
++pub(crate) trait SinPi {
+ fn sin_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+index 7ce31df626621..67bb0a2a9c594 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sqrt {
++pub(crate) trait Sqrt {
+ fn sqrt(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+index c1e379c34241f..58a1de1f400f9 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+@@ -6,7 +6,7 @@
+ use crate::llvm::simd_fsqrt;
+ use crate::*;
+
+-crate trait Sqrte {
++pub(crate) trait Sqrte {
+ fn sqrte(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+index 39f493d3b17f0..55cbc297aaf52 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+@@ -4,24 +4,24 @@ use cfg_if::cfg_if;
+
+ cfg_if! {
+ if #[cfg(target_pointer_width = "8")] {
+- crate type isize_ = i8;
+- crate type usize_ = u8;
++ pub(crate) type isize_ = i8;
++ pub(crate) type usize_ = u8;
+ } else if #[cfg(target_pointer_width = "16")] {
+- crate type isize_ = i16;
+- crate type usize_ = u16;
++ pub(crate) type isize_ = i16;
++ pub(crate) type usize_ = u16;
+ } else if #[cfg(target_pointer_width = "32")] {
+- crate type isize_ = i32;
+- crate type usize_ = u32;
++ pub(crate) type isize_ = i32;
++ pub(crate) type usize_ = u32;
+
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "128")] {
+- crate type isize_ = i128;
+- crate type usize_ = u128;
++ pub(crate) type isize_ = i128;
++ pub(crate) type usize_ = u128;
+ } else {
+ compile_error!("unsupported target_pointer_width");
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions.rs b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+index 7be4f5fabbea9..302ca6d88f33d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+@@ -1 +1 @@
+-crate mod mask;
++pub(crate) mod mask;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+index 0aec60969b864..a78bcc5632672 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+@@ -7,11 +7,11 @@
+
+ use crate::*;
+
+-crate trait All: crate::marker::Sized {
++pub(crate) trait All: crate::marker::Sized {
+ unsafe fn all(self) -> bool;
+ }
+
+-crate trait Any: crate::marker::Sized {
++pub(crate) trait Any: crate::marker::Sized {
+ unsafe fn any(self) -> bool;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+index a4435e3c35354..9cf34a3e0401c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SwapBytes {
++pub(crate) trait SwapBytes {
+ fn swap_bytes(self) -> Self;
+ }
+
+@@ -15,7 +15,7 @@ macro_rules! impl_swap_bytes {
+ impl SwapBytes for $id {
+ #[inline]
+ fn swap_bytes(self) -> Self {
+- unsafe { shuffle!(self, [1, 0]) }
++ shuffle!(self, [1, 0])
+ }
+ }
+ )+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+index cf4765538178d..abd3aa877920c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+@@ -5,7 +5,7 @@ macro_rules! impl_simd_ptr {
+ | $($tys:ty),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id<$ty>($(crate $tys),*);
++ pub struct $tuple_id<$ty>($(pub(crate) $tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl<$ty> crate::sealed::Seal for [$ptr_ty; $elem_count] {}
+diff --git a/third_party/rust/packed_simd_2/src/lib.rs b/third_party/rust/packed_simd_2/src/lib.rs
+index 840bae38d6a30..cd8a86805dd59 100644
+--- a/third_party/rust/packed_simd_2/src/lib.rs
++++ b/third_party/rust/packed_simd_2/src/lib.rs
+@@ -217,14 +217,13 @@
+ rustc_attrs,
+ platform_intrinsics,
+ stdsimd,
+- aarch64_target_feature,
+ arm_target_feature,
+ link_llvm_intrinsics,
+ core_intrinsics,
+ stmt_expr_attributes,
+- crate_visibility_modifier,
+ custom_inner_attributes,
+ )]
++#![cfg_attr(aarch64_target_feature, feature(aarch64_target_feature))]
+ #![allow(non_camel_case_types, non_snake_case,
+ // FIXME: these types are unsound in C FFI already
+ // See https://github.com/rust-lang/rust/issues/53346
+@@ -344,6 +343,6 @@ pub use self::codegen::llvm::{
+ __shuffle_vector8,
+ };
+
+-crate mod llvm {
+- crate use crate::codegen::llvm::*;
++pub(crate) mod llvm {
++ pub(crate) use crate::codegen::llvm::*;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/testing.rs b/third_party/rust/packed_simd_2/src/testing.rs
+index fcbcf9e2ac8eb..6320b28055569 100644
+--- a/third_party/rust/packed_simd_2/src/testing.rs
++++ b/third_party/rust/packed_simd_2/src/testing.rs
+@@ -5,4 +5,4 @@ mod macros;
+
+ #[cfg(test)]
+ #[macro_use]
+-crate mod utils;
++pub(crate) mod utils;
diff --git a/srcpkgs/firefox-esr/patches/fix-cbindgen.patch b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
new file mode 100644
index 000000000000..ba3ce7ae3e97
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
@@ -0,0 +1,22 @@
+Fix error with new cbindgen:
+
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi_generated.h:24:33: error: redefinition of 'constexpr const uint64_t mozilla::wr::ROOT_CLIP_CHAIN'
+ 24 | constexpr static const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi.h:76:16: note: 'const uint64_t mozilla::wr::ROOT_CLIP_CHAIN' previously defined here
+ 76 | const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+
+diff --git a/gfx/webrender_bindings/webrender_ffi.h b/gfx/webrender_bindings/webrender_ffi.h
+index b1d67b17a4bde..eb79974bdf434 100644
+--- a/gfx/webrender_bindings/webrender_ffi.h
++++ b/gfx/webrender_bindings/webrender_ffi.h
+@@ -73,8 +73,6 @@ struct WrPipelineInfo;
+ struct WrPipelineIdAndEpoch;
+ using WrPipelineIdEpochs = nsTArray<WrPipelineIdAndEpoch>;
+
+-const uint64_t ROOT_CLIP_CHAIN = ~0;
+-
+ } // namespace wr
+ } // namespace mozilla
+
diff --git a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
similarity index 64%
rename from srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
rename to srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
index c4664d3da7ce..3f0273cba366 100644
--- a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
+++ b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
@@ -1,6 +1,6 @@
---- a/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:31:39.428839442 +0100
-+++ b/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:32:20.689063456 +0100
-@@ -154,7 +154,7 @@
+--- a/taskcluster/docker/firefox-snap/firefox.desktop
++++ b/taskcluster/docker/firefox-snap/firefox.desktop
+@@ -154,11 +154,12 @@
Terminal=false
X-MultipleArgs=false
Type=Application
@@ -9,3 +9,8 @@
Categories=GNOME;GTK;Network;WebBrowser;
MimeType=text/html;text/xml;application/xhtml+xml;application/xml;application/rss+xml;application/rdf+xml;image/gif;image/jpeg;image/png;x-scheme-handler/http;x-scheme-handler/https;x-scheme-handler/ftp;x-scheme-handler/chrome;video/webm;application/x-xpinstall;
StartupNotify=true
+ Actions=NewWindow;NewPrivateWindow;
++StartupWMClass=Firefox
+
+ [Desktop Action NewWindow]
+ Name=Open a New Window
diff --git a/srcpkgs/firefox-esr/patches/fix-tools.patch b/srcpkgs/firefox-esr/patches/fix-tools.patch
deleted file mode 100644
index 94de423ce593..000000000000
--- a/srcpkgs/firefox-esr/patches/fix-tools.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:09:40.980448579 +0100
-+++ b/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:11:09.689590967 +0100
-@@ -497,8 +501,10 @@
- ucontext_t sSyncUContext;
-
- void Registers::SyncPopulate() {
-+#if defined(__GLIBC__)
- if (!getcontext(&sSyncUContext)) {
- PopulateRegsFromContext(*this, &sSyncUContext);
- }
-+#endif
- }
- #endif
diff --git a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
index 5d17021a99f4..4f9043b58e1e 100644
--- a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
+++ b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
@@ -1,20 +1,20 @@
---- a/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:20:52.298793223 +0100
-+++ b/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:21:48.250250850 +0100
-@@ -14,7 +14,7 @@
- #ifndef __GLIBC_PREREQ
- #define __GLIBC_PREREQ(a, b) 0
+--- a/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
++++ b/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
+@@ -18,7 +18,7 @@
+ #define WEBRTC_GLIBC_PREREQ(a, b) 0
#endif
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
#include <sys/auxv.h>
#else
- #include <fcntl.h>
-@@ -32,7 +32,7 @@
+ #include <errno.h>
+@@ -40,7 +40,7 @@
int architecture = 0;
- unsigned long hwcap = 0;
+ uint64_t hwcap = 0;
const char* platform = NULL;
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
hwcap = getauxval(AT_HWCAP);
platform = (const char*)getauxval(AT_PLATFORM);
#else
diff --git a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch b/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
deleted file mode 100644
index cced0058e8e1..000000000000
--- a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
+++ /dev/null
@@ -1,3441 +0,0 @@
-diff --git a/config/check_macroassembler_style.py b/config/check_macroassembler_style.py
-index 0d040a939b..b83e3691dd 100644
---- a/config/check_macroassembler_style.py
-+++ b/config/check_macroassembler_style.py
-@@ -24,17 +24,17 @@ from __future__ import absolute_import
- from __future__ import print_function
-
- import difflib
- import os
- import re
- import sys
-
- architecture_independent = set(["generic"])
--all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared"])
-+all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared", "ppc64"])
- all_architecture_names = set(["x86", "x64", "arm", "arm64"])
- all_shared_architecture_names = set(["x86_shared", "arm", "arm64"])
-
- reBeforeArg = "(?<=[(,\s])"
- reArgType = "(?P<type>[\w\s:*&]+)"
- reArgName = "(?P<name>\s\w+)"
- reArgDefault = "(?P<default>(?:\s=[^,)]+)?)"
- reAfterArg = "(?=[,)])"
-diff --git a/js/moz.configure b/js/moz.configure
-index 3c3d0d4359..b217d0e15c 100644
---- a/js/moz.configure
-+++ b/js/moz.configure
-@@ -214,23 +214,25 @@ def jit_codegen(jit_enabled, simulator, target):
- return namespace(**{str(target.cpu): True})
-
-
- set_config("JS_CODEGEN_NONE", jit_codegen.none)
- set_config("JS_CODEGEN_ARM", jit_codegen.arm)
- set_config("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_config("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_config("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_config("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_config("JS_CODEGEN_X86", jit_codegen.x86)
- set_config("JS_CODEGEN_X64", jit_codegen.x64)
- set_define("JS_CODEGEN_NONE", jit_codegen.none)
- set_define("JS_CODEGEN_ARM", jit_codegen.arm)
- set_define("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_define("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_define("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_define("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_define("JS_CODEGEN_X86", jit_codegen.x86)
- set_define("JS_CODEGEN_X64", jit_codegen.x64)
-
- # Profiling
- # =======================================================
- option(
- "--enable-instruments",
- env="MOZ_INSTRUMENTS",
-diff --git a/js/src/irregexp/RegExpNativeMacroAssembler.cpp b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-index e0ef7e64f5..81d8e2a198 100644
---- a/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-+++ b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-@@ -813,18 +813,33 @@ void SMRegExpMacroAssembler::JumpOrBacktrack(Label* to) {
- // If the test fails, call an OOL handler to try growing the stack.
- void SMRegExpMacroAssembler::CheckBacktrackStackLimit() {
- js::jit::Label no_stack_overflow;
- masm_.branchPtr(
- Assembler::BelowOrEqual,
- AbsoluteAddress(isolate()->regexp_stack()->limit_address_address()),
- backtrack_stack_pointer_, &no_stack_overflow);
-
-+#ifdef JS_CODEGEN_PPC64
-+ // LR on PowerPC isn't a GPR, so we have to explicitly save it here before
-+ // we call or we will end up erroneously returning after the call to the
-+ // stack overflow handler when we |blr| out and inevitably underflow the
-+ // irregexp stack on the next backtrack.
-+ masm_.xs_mflr(temp1_);
-+ masm_.as_stdu(temp1_, masm_.getStackPointer(), -8);
-+#endif
-+
- masm_.call(&stack_overflow_label_);
-
-+#ifdef JS_CODEGEN_PPC64
-+ masm_.as_ld(temp1_, masm_.getStackPointer(), 0);
-+ masm_.xs_mtlr(temp1_);
-+ masm_.as_addi(masm_.getStackPointer(), masm_.getStackPointer(), 8);
-+#endif
-+
- // Exit with an exception if the call failed
- masm_.branchTest32(Assembler::Zero, temp0_, temp0_,
- &exit_with_exception_label_);
-
- masm_.bind(&no_stack_overflow);
- }
-
- // This is used to sneak an OOM through the V8 layer.
-@@ -1127,16 +1142,20 @@ void SMRegExpMacroAssembler::stackOverflowHandler() {
- LiveGeneralRegisterSet volatileRegs(GeneralRegisterSet::Volatile());
-
- #ifdef JS_USE_LINK_REGISTER
- masm_.pushReturnAddress();
- #endif
-
- // Adjust for the return address on the stack.
- size_t frameOffset = sizeof(void*);
-+#ifdef JS_CODEGEN_PPC64
-+ // We have a double return address.
-+ frameOffset += sizeof(void*);
-+#endif
-
- volatileRegs.takeUnchecked(temp0_);
- volatileRegs.takeUnchecked(temp1_);
- masm_.PushRegsInMask(volatileRegs);
-
- using Fn = bool (*)(RegExpStack * regexp_stack);
- masm_.setupUnalignedABICall(temp0_);
- masm_.passABIArg(temp1_);
-diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h
-index f4a5727d05..138612d53b 100644
---- a/js/src/jit/AtomicOperations.h
-+++ b/js/src/jit/AtomicOperations.h
-@@ -373,19 +373,26 @@ constexpr inline bool AtomicOperations::isLockfreeJS(int32_t size) {
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- # endif
- #elif defined(__mips__)
- # if defined(__clang__) || defined(__GNUC__)
- # include "jit/mips-shared/AtomicOperations-mips-shared.h"
- # else
- # error "AtomicOperations on MIPS for an unknown compiler"
- # endif
-+#elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-+ defined(__PPC64LE__)
-+# if defined(JS_CODEGEN_PPC64)
-+/* XXX: should be # include "jit/shared/AtomicOperations-shared-jit.h" */
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# else
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# endif
- #elif defined(__ppc__) || defined(__PPC__) || defined(__sparc__) || \
-- defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-- defined(__PPC64LE__) || defined(__alpha__) || defined(__hppa__) || \
-+ defined(__alpha__) || defined(__hppa__) || \
- defined(__sh__) || defined(__s390__) || defined(__s390x__) || \
- defined(__m68k__) || defined(__riscv) || defined(__wasi__)
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- #else
- # error "No AtomicOperations support provided for this platform"
- #endif
-
- #endif // jit_AtomicOperations_h
-diff --git a/js/src/jit/BaselineBailouts.cpp b/js/src/jit/BaselineBailouts.cpp
-index bca1427f93..eb499b34cf 100644
---- a/js/src/jit/BaselineBailouts.cpp
-+++ b/js/src/jit/BaselineBailouts.cpp
-@@ -481,16 +481,21 @@ class MOZ_STACK_CLASS BaselineStackBuilder {
- // let X = STACK_START_ADDR + JitFrameLayout::Size() + PREV_FRAME_SIZE
- // X + RectifierFrameLayout::Size()
- // + ((RectifierFrameLayout*) X)->prevFrameLocalSize()
- // - BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr()
- size_t extraOffset =
- RectifierFrameLayout::Size() + priorFrame->prevFrameLocalSize() +
- BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr();
- return virtualPointerAtStackOffset(priorOffset + extraOffset);
-+#elif defined(JS_CODEGEN_PPC64)
-+ (void)priorOffset;
-+// XXX. The above code might work though
-+#warning "TODO! BaselineStackBuilder::calculatePrevFramePtr()"
-+ MOZ_CRASH();
- #elif defined(JS_CODEGEN_NONE)
- (void)priorOffset;
- MOZ_CRASH();
- #else
- # error "Bad architecture!"
- #endif
- }
- };
-diff --git a/js/src/jit/BaselineCodeGen.cpp b/js/src/jit/BaselineCodeGen.cpp
-index 7089f5e300..d67236d2c5 100644
---- a/js/src/jit/BaselineCodeGen.cpp
-+++ b/js/src/jit/BaselineCodeGen.cpp
-@@ -520,16 +520,19 @@ bool BaselineCodeGen<Handler>::emitOutOfLinePostBarrierSlot() {
- regs.take(BaselineFrameReg);
- Register scratch = regs.takeAny();
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // On ARM, save the link register before calling. It contains the return
- // address. The |masm.ret()| later will pop this into |pc| to return.
- masm.push(lr);
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- masm.push(ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.xs_mflr(ScratchRegister);
-+ masm.push(ScratchRegister);
- #endif
- masm.pushValue(R0);
-
- using Fn = void (*)(JSRuntime * rt, js::gc::Cell * cell);
- masm.setupUnalignedABICall(scratch);
- masm.movePtr(ImmPtr(cx->runtime()), scratch);
- masm.passABIArg(scratch);
- masm.passABIArg(objReg);
-diff --git a/js/src/jit/BaselineIC.cpp b/js/src/jit/BaselineIC.cpp
-index 9572394e76..dfe762e5c8 100644
---- a/js/src/jit/BaselineIC.cpp
-+++ b/js/src/jit/BaselineIC.cpp
-@@ -127,17 +127,18 @@ class MOZ_RAII FallbackICCodeCompiler final {
- };
-
- AllocatableGeneralRegisterSet BaselineICAvailableGeneralRegs(size_t numInputs) {
- AllocatableGeneralRegisterSet regs(GeneralRegisterSet::All());
- #if defined(JS_CODEGEN_ARM)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- regs.take(BaselineSecondScratchReg);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- MOZ_ASSERT(!regs.has(BaselineSecondScratchReg));
- #elif defined(JS_CODEGEN_ARM64)
- MOZ_ASSERT(!regs.has(PseudoStackPointer));
- MOZ_ASSERT(!regs.has(RealStackPointer));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- #else
-diff --git a/js/src/jit/CodeGenerator.h b/js/src/jit/CodeGenerator.h
-index 5321978fc2..b2d9a8f5a5 100644
---- a/js/src/jit/CodeGenerator.h
-+++ b/js/src/jit/CodeGenerator.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/CodeGenerator-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/CodeGenerator-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/CodeGenerator-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/CodeGenerator-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/CodeGenerator-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/CodeGenerator-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmGC.h"
-
-diff --git a/js/src/jit/FlushICache.h b/js/src/jit/FlushICache.h
-index fe66080df5..2071563c1e 100644
---- a/js/src/jit/FlushICache.h
-+++ b/js/src/jit/FlushICache.h
-@@ -19,17 +19,18 @@ namespace jit {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- // No-op. Code and data caches are coherent on x86 and x64.
- }
-
- #elif (defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)) || \
-- (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64))
-+ (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)) || \
-+ defined(JS_CODEGEN_PPC64)
-
- extern void FlushICache(void* code, size_t size, bool codeIsThreadLocal = true);
-
- #elif defined(JS_CODEGEN_NONE)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- MOZ_CRASH();
-diff --git a/js/src/jit/JitFrames.cpp b/js/src/jit/JitFrames.cpp
-index 77cfe6a9cd..507f1551e6 100644
---- a/js/src/jit/JitFrames.cpp
-+++ b/js/src/jit/JitFrames.cpp
-@@ -2220,16 +2220,24 @@ MachineState MachineState::FromBailout(RegisterDump::GPRArray& regs,
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Single),
- &fpregs[i]);
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Double),
- &fpregs[i]);
- // No SIMD support in bailouts, SIMD is internal to wasm
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
-+ machine.setRegisterLocation(FloatRegister(i), &fpregs[i]);
-+# ifdef ENABLE_WASM_SIMD
-+ // Needs additional handling if VMX or non-FPR VSX regs are in play.
-+# error "SIMD for PPC NYI"
-+# endif
-+ }
-
- #elif defined(JS_CODEGEN_NONE)
- MOZ_CRASH();
- #else
- # error "Unknown architecture!"
- #endif
- return machine;
- }
-diff --git a/js/src/jit/JitFrames.h b/js/src/jit/JitFrames.h
-index 40c661d146..7b4ea3157d 100644
---- a/js/src/jit/JitFrames.h
-+++ b/js/src/jit/JitFrames.h
-@@ -152,16 +152,26 @@ struct ResumeFromException {
- static const uint32_t RESUME_ENTRY_FRAME = 0;
- static const uint32_t RESUME_CATCH = 1;
- static const uint32_t RESUME_FINALLY = 2;
- static const uint32_t RESUME_FORCED_RETURN = 3;
- static const uint32_t RESUME_BAILOUT = 4;
- static const uint32_t RESUME_WASM = 5;
- static const uint32_t RESUME_WASM_CATCH = 6;
-
-+#if defined(JS_CODEGEN_PPC64)
-+ // This gets built on the stack as part of exception returns. Because
-+ // it goes right on top of the stack, an ABI-compliant routine can wreck
-+ // it, so we implement a minimum Power ISA linkage area (four doublewords).
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
-+
- uint8_t* framePointer;
- uint8_t* stackPointer;
- uint8_t* target;
- uint32_t kind;
-
- // Value to push when resuming into a |finally| block.
- // Also used by Wasm to send the exception object to the throw stub.
- JS::Value exception;
-diff --git a/js/src/jit/JitOptions.cpp b/js/src/jit/JitOptions.cpp
-index de13777fc3..795e41bf21 100644
---- a/js/src/jit/JitOptions.cpp
-+++ b/js/src/jit/JitOptions.cpp
-@@ -132,17 +132,22 @@ DefaultJitOptions::DefaultJitOptions() {
- // Warp compile Generator functions
- SET_DEFAULT(warpGenerator, true);
-
- // Whether the IonMonkey and Baseline JITs are enabled for Trusted Principals.
- // (Ignored if ion or baselineJit is set to true.)
- SET_DEFAULT(jitForTrustedPrincipals, false);
-
- // Whether the RegExp JIT is enabled.
-+#if defined(JS_CODEGEN_PPC64)
-+ // This may generate ISA 3 instructions. The other JIT tiers gate on it too.
-+ SET_DEFAULT(nativeRegExp, MacroAssembler::SupportsFloatingPoint());
-+#else
- SET_DEFAULT(nativeRegExp, true);
-+#endif
-
- // Whether Warp should use ICs instead of transpiling Baseline CacheIR.
- SET_DEFAULT(forceInlineCaches, false);
-
- // Whether all ICs should be initialized as megamorphic ICs.
- SET_DEFAULT(forceMegamorphicICs, false);
-
- // Toggles whether large scripts are rejected.
-diff --git a/js/src/jit/LIR.h b/js/src/jit/LIR.h
-index 024bd798ca..0cd43c12ab 100644
---- a/js/src/jit/LIR.h
-+++ b/js/src/jit/LIR.h
-@@ -1939,16 +1939,18 @@ AnyRegister LAllocation::toRegister() const {
- # include "jit/arm64/LIR-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/LIR-mips32.h"
- # elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/LIR-mips64.h"
- # endif
- # include "jit/mips-shared/LIR-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/LIR-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/LIR-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #undef LIR_HEADER
-
-diff --git a/js/src/jit/Label.h b/js/src/jit/Label.h
-index a8f93de378..480b18b251 100644
---- a/js/src/jit/Label.h
-+++ b/js/src/jit/Label.h
-@@ -21,17 +21,18 @@ struct LabelBase {
- uint32_t bound_ : 1;
-
- // offset_ < INVALID_OFFSET means that the label is either bound or has
- // incoming uses and needs to be bound.
- uint32_t offset_ : 31;
-
- void operator=(const LabelBase& label) = delete;
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- public:
- #endif
- static const uint32_t INVALID_OFFSET = 0x7fffffff; // UINT31_MAX.
-
- public:
- LabelBase() : bound_(false), offset_(INVALID_OFFSET) {}
-
- // If the label is bound, all incoming edges have been patched and any
-diff --git a/js/src/jit/Lowering.h b/js/src/jit/Lowering.h
-index 979687da85..c064e5d914 100644
---- a/js/src/jit/Lowering.h
-+++ b/js/src/jit/Lowering.h
-@@ -18,16 +18,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Lowering-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Lowering-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Lowering-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Lowering-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Lowering-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Lowering-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler-inl.h b/js/src/jit/MacroAssembler-inl.h
-index cf16cdf0a7..fa39c5f4d2 100644
---- a/js/src/jit/MacroAssembler-inl.h
-+++ b/js/src/jit/MacroAssembler-inl.h
-@@ -30,16 +30,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32-inl.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64-inl.h"
- #elif !defined(JS_CODEGEN_NONE)
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmBuiltins.h"
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler.cpp b/js/src/jit/MacroAssembler.cpp
-index 2a3aeec607..cbe9d14f46 100644
---- a/js/src/jit/MacroAssembler.cpp
-+++ b/js/src/jit/MacroAssembler.cpp
-@@ -4044,16 +4044,18 @@ void MacroAssembler::emitPreBarrierFastPath(JSRuntime* rt, MIRType type,
- #elif JS_CODEGEN_ARM
- ma_lsl(temp3, temp1, temp1);
- #elif JS_CODEGEN_ARM64
- Lsl(ARMRegister(temp1, 64), ARMRegister(temp1, 64), ARMRegister(temp3, 64));
- #elif JS_CODEGEN_MIPS32
- ma_sll(temp1, temp1, temp3);
- #elif JS_CODEGEN_MIPS64
- ma_dsll(temp1, temp1, temp3);
-+#elif JS_CODEGEN_PPC64
-+ as_sld(temp1, temp1, temp3);
- #elif JS_CODEGEN_NONE
- MOZ_CRASH();
- #else
- # error "Unknown architecture"
- #endif
-
- // No barrier is needed if the bit is set, |word & mask != 0|.
- branchTestPtr(Assembler::NonZero, temp2, temp1, noBarrier);
-diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h
-index e2d53d5cef..cb0148b94e 100644
---- a/js/src/jit/MacroAssembler.h
-+++ b/js/src/jit/MacroAssembler.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MacroAssembler-none.h"
- #else
- # error "Unknown architecture!"
- #endif
- #include "jit/ABIFunctions.h"
- #include "jit/AtomicOp.h"
- #include "jit/AutoJitContextAlloc.h"
-@@ -87,18 +89,18 @@
- // //{{{ check_macroassembler_style
- // inline uint32_t
- // MacroAssembler::framePushed() const
- // {
- // return framePushed_;
- // }
- // ////}}} check_macroassembler_style
-
--#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64
--#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared
-+#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64, ppc64
-+#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared, ppc64
-
- // * How this macro works:
- //
- // DEFINED_ON is a macro which check if, for the current architecture, the
- // method is defined on the macro assembler or not.
- //
- // For each architecture, we have a macro named DEFINED_ON_arch. This macro is
- // empty if this is not the current architecture. Otherwise it must be either
-@@ -134,16 +136,17 @@
- #define DEFINED_ON_x86
- #define DEFINED_ON_x64
- #define DEFINED_ON_x86_shared
- #define DEFINED_ON_arm
- #define DEFINED_ON_arm64
- #define DEFINED_ON_mips32
- #define DEFINED_ON_mips64
- #define DEFINED_ON_mips_shared
-+#define DEFINED_ON_ppc64
- #define DEFINED_ON_none
-
- // Specialize for each architecture.
- #if defined(JS_CODEGEN_X86)
- # undef DEFINED_ON_x86
- # define DEFINED_ON_x86 define
- # undef DEFINED_ON_x86_shared
- # define DEFINED_ON_x86_shared define
-@@ -163,16 +166,19 @@
- # define DEFINED_ON_mips32 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
- #elif defined(JS_CODEGEN_MIPS64)
- # undef DEFINED_ON_mips64
- # define DEFINED_ON_mips64 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
-+#elif defined(JS_CODEGEN_PPC64)
-+# undef DEFINED_ON_ppc64
-+# define DEFINED_ON_ppc64 define
- #elif defined(JS_CODEGEN_NONE)
- # undef DEFINED_ON_none
- # define DEFINED_ON_none crash
- #else
- # error "Unknown architecture!"
- #endif
-
- #define DEFINED_ON_RESULT_crash \
-@@ -479,36 +485,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // targets roll their own save-code instead.
- //
- // Nevertheless, because some targets *do* call PushRegsInMask from
- // JitRuntime::generateInvalidator, you should check carefully all of the
- // ::generateInvalidator methods if you change the PushRegsInMask format.
-
- // The size of the area used by PushRegsInMask.
- size_t PushRegsInMaskSizeInBytes(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PushRegsInMask(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- void PushRegsInMask(LiveGeneralRegisterSet set);
-
- // Like PushRegsInMask, but instead of pushing the registers, store them to
- // |dest|. |dest| should point to the end of the reserved space, so the
- // first register will be stored at |dest.offset - sizeof(register)|. It is
- // required that |dest.offset| is at least as large as the value computed by
- // PushRegsInMaskSizeInBytes for this |set|. In other words, |dest.base|
- // must point to either the lowest address in the save area, or some address
- // below that.
- void storeRegsInMask(LiveRegisterSet set, Address dest, Register scratch)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PopRegsInMask(LiveRegisterSet set);
- void PopRegsInMask(LiveGeneralRegisterSet set);
- void PopRegsInMaskIgnore(LiveRegisterSet set, LiveRegisterSet ignore)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // ===============================================================
- // Stack manipulation functions -- single registers/values.
-
- void Push(const Operand op) DEFINED_ON(x86_shared);
- void Push(Register reg) PER_SHARED_ARCH;
- void Push(Register reg1, Register reg2, Register reg3, Register reg4)
- DEFINED_ON(arm64);
-@@ -531,17 +537,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline CodeOffset PushWithPatch(ImmWord word);
- inline CodeOffset PushWithPatch(ImmPtr imm);
-
- void Pop(const Operand op) DEFINED_ON(x86_shared);
- void Pop(Register reg) PER_SHARED_ARCH;
- void Pop(FloatRegister t) PER_SHARED_ARCH;
- void Pop(const ValueOperand& val) PER_SHARED_ARCH;
- void PopFlags() DEFINED_ON(x86_shared);
-- void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared);
-+ void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared, ppc64);
- void popRooted(VMFunctionData::RootType rootType, Register cellReg,
- const ValueOperand& valueReg);
-
- // Move the stack pointer based on the requested amount.
- void adjustStack(int amount);
- void freeStack(uint32_t amount);
-
- // Warning: This method does not update the framePushed() counter.
-@@ -589,18 +595,18 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Push the return address and make a call. On platforms where this function
- // is not defined, push the link register (pushReturnAddress) at the entry
- // point of the callee.
- void callAndPushReturnAddress(Register reg) DEFINED_ON(x86_shared);
- void callAndPushReturnAddress(Label* label) DEFINED_ON(x86_shared);
-
- // These do not adjust framePushed().
-- void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-- void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-+ void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-+ void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-
- // Useful for dealing with two-valued returns.
- void moveRegPair(Register src0, Register src1, Register dst0, Register dst1,
- MoveOp::Type type = MoveOp::GENERAL);
-
- public:
- // ===============================================================
- // Patchable near/far jumps.
-@@ -621,20 +627,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // These methods are like movWithPatch/PatchDataWithValueCheck but allow
- // using pc-relative addressing on certain platforms (RIP-relative LEA on x64,
- // ADR instruction on arm64).
- //
- // Note: "Near" applies to ARM64 where the target must be within 1 MB (this is
- // release-asserted).
- CodeOffset moveNearAddressWithPatch(Register dest)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
- static void patchNearAddressMove(CodeLocationLabel loc,
- CodeLocationLabel target)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
-
- public:
- // ===============================================================
- // [SMDOC] JIT-to-C++ Function Calls (callWithABI)
- //
- // callWithABI is used to make a call using the standard C/C++ system ABI.
- //
- // callWithABI is a low level interface for making calls, as such every call
-@@ -983,20 +989,21 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void xor32(Imm32 imm, Register dest) PER_SHARED_ARCH;
- inline void xor32(Imm32 imm, const Address& dest) PER_SHARED_ARCH;
- inline void xor32(const Address& src, Register dest) PER_SHARED_ARCH;
-
- inline void xorPtr(Register src, Register dest) PER_ARCH;
- inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
-
- inline void and64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-- inline void or64(const Operand& src, Register64 dest) DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-+ inline void or64(const Operand& src, Register64 dest)
-+ DEFINED_ON(x64, mips64, ppc64);
- inline void xor64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- // ===============================================================
- // Swap instructions
-
- // Swap the two lower bytes and sign extend the result to 32-bit.
- inline void byteSwap16SignExtend(Register reg) PER_SHARED_ARCH;
-
- // Swap the two lower bytes and zero extend the result to 32-bit.
-@@ -1020,27 +1027,27 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addPtr(Register src, Register dest) PER_ARCH;
- inline void addPtr(Register src1, Register src2, Register dest)
- DEFINED_ON(arm64);
- inline void addPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void addPtr(Imm32 imm, Register src, Register dest) DEFINED_ON(arm64);
- inline void addPtr(ImmWord imm, Register dest) PER_ARCH;
- inline void addPtr(ImmPtr imm, Register dest);
- inline void addPtr(Imm32 imm, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void addPtr(Imm32 imm, const AbsoluteAddress& dest)
- DEFINED_ON(x86, x64);
- inline void addPtr(const Address& src, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void add64(Register64 src, Register64 dest) PER_ARCH;
- inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
- inline void add64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void add64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void addFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- // Compute dest=SP-imm where dest is a pointer registers and not SP. The
- // offset returned from sub32FromStackPtrWithPatch() must be passed to
- // patchSub32FromStackPtr().
- inline CodeOffset sub32FromStackPtrWithPatch(Register dest) PER_ARCH;
- inline void patchSub32FromStackPtr(CodeOffset offset, Imm32 imm) PER_ARCH;
-@@ -1049,58 +1056,58 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addConstantDouble(double d, FloatRegister dest) DEFINED_ON(x86);
-
- inline void sub32(const Address& src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Register src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Imm32 imm, Register dest) PER_SHARED_ARCH;
-
- inline void subPtr(Register src, Register dest) PER_ARCH;
- inline void subPtr(Register src, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void subPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
- inline void subPtr(const Address& addr, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void sub64(Register64 src, Register64 dest) PER_ARCH;
- inline void sub64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void sub64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void subFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void subDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mul32(Register rhs, Register srcDest) PER_SHARED_ARCH;
-
- inline void mul32(Register src1, Register src2, Register dest, Label* onOver)
- DEFINED_ON(arm64);
-
- inline void mulPtr(Register rhs, Register srcDest) PER_ARCH;
-
- inline void mul64(const Operand& src, const Register64& dest) DEFINED_ON(x64);
- inline void mul64(const Operand& src, const Register64& dest,
-- const Register temp) DEFINED_ON(x64, mips64);
-+ const Register temp) DEFINED_ON(x64, mips64, ppc64);
- inline void mul64(Imm64 imm, const Register64& dest) PER_ARCH;
- inline void mul64(Imm64 imm, const Register64& dest, const Register temp)
-- DEFINED_ON(x86, x64, arm, mips32, mips64);
-+ DEFINED_ON(x86, x64, arm, mips32, mips64, ppc64);
- inline void mul64(const Register64& src, const Register64& dest,
- const Register temp) PER_ARCH;
- inline void mul64(const Register64& src1, const Register64& src2,
- const Register64& dest) DEFINED_ON(arm64);
- inline void mul64(Imm64 src1, const Register64& src2, const Register64& dest)
- DEFINED_ON(arm64);
-
- inline void mulBy3(Register src, Register dest) PER_ARCH;
-
- inline void mulFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void mulDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // On x86_shared, srcDest must be eax and edx will be clobbered.
- // On ARM, the chip must have hardware division instructions.
- inline void quotient32(Register rhs, Register srcDest,
- bool isUnsigned) PER_SHARED_ARCH;
-@@ -1117,41 +1124,41 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleRemainder32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleQuotient32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow. The
- // remainder is stored into the third argument register here.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest and remOutput are clobbered.
- void flexibleDivMod32(Register rhs, Register srcDest, Register remOutput,
- bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- inline void divFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void divDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void inc64(AbsoluteAddress dest) PER_ARCH;
-
- inline void neg32(Register reg) PER_SHARED_ARCH;
- inline void neg64(Register64 reg) PER_ARCH;
-@@ -1342,17 +1349,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // temp may be invalid only if the chip has the POPCNT instruction.
- inline void popcnt64(Register64 src, Register64 dest, Register temp) PER_ARCH;
-
- // ===============================================================
- // Condition functions
-
- template <typename T1, typename T2>
- inline void cmp32Set(Condition cond, T1 lhs, T2 rhs, Register dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
-
- template <typename T1, typename T2>
- inline void cmpPtrSet(Condition cond, T1 lhs, T2 rhs, Register dest) PER_ARCH;
-
- // ===============================================================
- // Branch functions
-
- template <class L>
-@@ -1367,34 +1374,34 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branch32(Condition cond, const Address& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branch32(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branch32(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) DEFINED_ON(arm, x86_shared);
- inline void branch32(Condition cond, const BaseIndex& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const Operand& lhs, Register rhs,
- Label* label) DEFINED_ON(x86_shared);
- inline void branch32(Condition cond, const Operand& lhs, Imm32 rhs,
- Label* label) DEFINED_ON(x86_shared);
-
- inline void branch32(Condition cond, wasm::SymbolicAddress lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // The supported condition are Equal, NotEqual, LessThan(orEqual),
- // GreaterThan(orEqual), Below(orEqual) and Above(orEqual). When a fail label
- // is not defined it will fall through to next instruction, else jump to the
- // fail label.
- inline void branch64(Condition cond, Register64 lhs, Imm64 val,
- Label* success, Label* fail = nullptr) PER_ARCH;
- inline void branch64(Condition cond, Register64 lhs, Register64 rhs,
-@@ -1433,32 +1440,32 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchPtr(Condition cond, const BaseIndex& lhs, ImmWord rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchPtr(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs,
- Register rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs, ImmWord rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchPtr(Condition cond, wasm::SymbolicAddress lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Given a pointer to a GC Cell, retrieve the StoreBuffer pointer from its
- // chunk header, or nullptr if it is in the tenured heap.
- void loadStoreBuffer(Register ptr, Register buffer) PER_ARCH;
-
- void branchPtrInNurseryChunk(Condition cond, Register ptr, Register temp,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- void branchPtrInNurseryChunk(Condition cond, const Address& address,
- Register temp, Label* label) DEFINED_ON(x86);
- void branchValueIsNurseryCell(Condition cond, const Address& address,
- Register temp, Label* label) PER_ARCH;
- void branchValueIsNurseryCell(Condition cond, ValueOperand value,
- Register temp, Label* label) PER_ARCH;
-
- // This function compares a Value (lhs) which is having a private pointer
-@@ -1470,36 +1477,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- // Truncate a double/float32 to int32 and when it doesn't fit an int32 it will
- // jump to the failure label. This particular variant is allowed to return the
- // value module 2**32, which isn't implemented on all architectures. E.g. the
- // x64 variants will do this only in the int64_t range.
- inline void branchTruncateFloat32MaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleMaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Truncate a double/float32 to intptr and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
- inline void branchTruncateDoubleToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
-
- // Truncate a double/float32 to int32 and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchDouble(DoubleCondition cond, FloatRegister lhs,
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- inline void branchDoubleNotInInt64Range(Address src, Register temp,
- Label* fail);
- inline void branchDoubleNotInUInt64Range(Address src, Register temp,
- Label* fail);
-@@ -1543,17 +1550,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- L label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTest32(Condition cond, Register lhs, Imm32 rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const Address& lhs, Imm32 rhh,
- Label* label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const AbsoluteAddress& lhs,
- Imm32 rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- template <class L>
- inline void branchTestPtr(Condition cond, Register lhs, Register rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, Register lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-@@ -1689,17 +1696,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Perform a type-test on a tag of a Value (32bits boxing), or the tagged
- // value (64bits boxing).
- inline void branchTestUndefined(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, Register tag, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestNumber(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
-@@ -1721,106 +1728,106 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // BaseIndex and ValueOperand variants clobber the ScratchReg on x64.
- // All Variants clobber the ScratchReg on arm64.
- inline void branchTestUndefined(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestInt32(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestDouble(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNumber(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBoolean(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestString(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestSymbol(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBigInt(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNull(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Clobbers the ScratchReg on x64.
- inline void branchTestObject(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestGCThing(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const ValueOperand& value,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchTestPrimitive(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestMagic(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTestMagic(Condition cond, const ValueOperand& value,
- L label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& valaddr,
- JSWhyMagic why, Label* label) PER_ARCH;
-
- inline void branchTestMagicValue(Condition cond, const ValueOperand& val,
- JSWhyMagic why, Label* label);
-
- void branchTestValue(Condition cond, const ValueOperand& lhs,
-@@ -1828,42 +1835,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchTestValue(Condition cond, const BaseIndex& lhs,
- const ValueOperand& rhs, Label* label) PER_ARCH;
-
- // Checks if given Value is evaluated to true or false in a condition.
- // The type of the value should match the type of the method.
- inline void branchTestInt32Truthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestDoubleTruthy(bool truthy, FloatRegister reg,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBooleanTruthy(bool truthy, const ValueOperand& value,
- Label* label) PER_ARCH;
- inline void branchTestStringTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestBigIntTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Create an unconditional branch to the address given as argument.
- inline void branchToComputedAddress(const BaseIndex& address) PER_ARCH;
-
- private:
- template <typename T, typename S, typename L>
- inline void branchPtrImpl(Condition cond, const T& lhs, const S& rhs, L label)
- DEFINED_ON(x86_shared);
-
- void branchPtrInNurseryChunkImpl(Condition cond, Register ptr, Label* label)
- DEFINED_ON(x86);
- template <typename T>
- void branchValueIsNurseryCellImpl(Condition cond, const T& value,
- Register temp, Label* label)
-- DEFINED_ON(arm64, x64, mips64);
-+ DEFINED_ON(arm64, x64, mips64, ppc64);
-
- template <typename T>
- inline void branchTestUndefinedImpl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
- inline void branchTestInt32Impl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
-@@ -1923,116 +1930,116 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void fallibleUnboxString(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxSymbol(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxBigInt(const T& src, Register dest, Label* fail);
-
- inline void cmp32Move32(Condition cond, Register lhs, Register rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Move32(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, Register rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmp32Load32(Condition cond, Register lhs, const Address& rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Load32(Condition cond, Register lhs, Register rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32LoadPtr(Condition cond, const Address& lhs, Imm32 rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void cmp32MovePtr(Condition cond, Register lhs, Imm32 rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32LoadPtr(Condition cond, const Address& addr, Imm32 mask,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32MovePtr(Condition cond, const Address& addr, Imm32 mask,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Conditional move for Spectre mitigations.
- inline void spectreMovePtr(Condition cond, Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Zeroes dest if the condition is true.
- inline void spectreZeroRegister(Condition cond, Register scratch,
- Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- // Performs a bounds check and zeroes the index register if out-of-bounds
- // (to mitigate Spectre).
- private:
- inline void spectreBoundsCheck32(Register index, const Operand& length,
- Register maybeScratch, Label* failure)
- DEFINED_ON(x86);
-
- public:
- inline void spectreBoundsCheck32(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheck32(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void spectreBoundsCheckPtr(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheckPtr(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // ========================================================================
- // Canonicalization primitives.
- inline void canonicalizeDouble(FloatRegister reg);
- inline void canonicalizeDoubleIfDeterministic(FloatRegister reg);
-
- inline void canonicalizeFloat(FloatRegister reg);
- inline void canonicalizeFloatIfDeterministic(FloatRegister reg);
-
- public:
- // ========================================================================
- // Memory access primitives.
- inline void storeUncanonicalizedDouble(FloatRegister src, const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src, const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeDouble(FloatRegister src, const T& dest);
-
- template <class T>
- inline void boxDouble(FloatRegister src, const T& dest);
-
- using MacroAssemblerSpecific::boxDouble;
-
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeFloat32(FloatRegister src, const T& dest);
-
- template <typename T>
-@@ -3470,20 +3477,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
- DEFINED_ON(x86, x64);
-
- public:
- // ========================================================================
- // Convert floating point.
-
- // temp required on x86 and x64; must be undefined on mips64.
- void convertUInt64ToFloat32(Register64 src, FloatRegister dest, Register temp)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- void convertInt64ToFloat32(Register64 src, FloatRegister dest)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- bool convertUInt64ToDoubleNeedsTemp() PER_ARCH;
-
- // temp required when convertUInt64ToDoubleNeedsTemp() returns true.
- void convertUInt64ToDouble(Register64 src, FloatRegister dest,
- Register temp) PER_ARCH;
-
- void convertInt64ToDouble(Register64 src, FloatRegister dest) PER_ARCH;
-@@ -3514,29 +3521,29 @@ class MacroAssembler : public MacroAssemblerSpecific {
- //
- // On 32-bit systems for both wasm and asm.js, and on 64-bit systems for
- // asm.js, heap lengths are limited to 2GB. On 64-bit systems for wasm,
- // 32-bit heap lengths are limited to 4GB, and 64-bit heap lengths will be
- // limited to something much larger.
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Register boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Register64 boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- // Each wasm load/store instruction appends its own wasm::Trap::OutOfBounds.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- AnyRegister out) DEFINED_ON(x86, x64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- Register64 out) DEFINED_ON(x86, x64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Operand dstAddr) DEFINED_ON(x86, x64);
-@@ -3546,26 +3553,26 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // For all the ARM/MIPS wasmLoad and wasmStore functions below, `ptr`
- // MUST equal `ptrScratch`, and that register will be updated based on
- // conditions listed below (where it is only mentioned as `ptr`).
-
- // `ptr` will be updated if access.offset() != 0 or access.type() ==
- // Scalar::Int64.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, AnyRegister output)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, Register64 output)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
-
- // These accept general memoryBase + ptr + offset (in `access`); the offset is
- // always smaller than the guard region. They will insert an additional add
- // if the offset is nonzero, and of course that add may require a temporary
- // register for the offset if the offset is large, and instructions to set it
- // up.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, AnyRegister output) DEFINED_ON(arm64);
-@@ -3575,100 +3582,100 @@ class MacroAssembler : public MacroAssemblerSpecific {
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoad(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr, Register ptrScratch,
- Register output, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedLoadFP(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, FloatRegister output,
- Register tmp1, Register tmp2, Register tmp3)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoadI64(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register64 output,
-- Register tmp) DEFINED_ON(mips32, mips64);
-+ Register tmp) DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedStore(const wasm::MemoryAccessDesc& access, Register value,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreFP(const wasm::MemoryAccessDesc& access,
- FloatRegister floatValue, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreI64(const wasm::MemoryAccessDesc& access,
- Register64 value, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // wasm specific methods, used in both the wasm baseline compiler and ion.
-
- // The truncate-to-int32 methods do not bind the rejoin label; clients must
- // do so if oolWasmTruncateCheckF64ToI32() can jump to it.
- void wasmTruncateDoubleToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateDoubleToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF64ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateFloat32ToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF32ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // The truncate-to-int64 methods will always bind the `oolRejoin` label
- // after the last emitted instruction.
- void wasmTruncateDoubleToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateDoubleToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF64ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateFloat32ToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF32ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // This function takes care of loading the callee's TLS and pinned regs but
- // it is the caller's responsibility to save/restore TLS or pinned regs.
- CodeOffset wasmCallImport(const wasm::CallSiteDesc& desc,
- const wasm::CalleeDesc& callee);
-
- // WasmTableCallIndexReg must contain the index of the indirect call.
- CodeOffset wasmCallIndirect(const wasm::CallSiteDesc& desc,
-@@ -3735,72 +3742,72 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `expected` and `output` must be edx:eax; `replacement` is ecx:ebx.
- // x64: `output` must be rax.
- // ARM: Registers must be distinct; `replacement` and `output` must be
- // (even,odd) pairs.
-
- void compareExchange64(const Synchronization& sync, const Address& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void compareExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Exchange with memory. Return the value initially in memory.
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `value` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `value` and `output` must be distinct and (even,odd) pairs.
- // ARM64: `value` and `output` must be distinct.
-
- void atomicExchange64(const Synchronization& sync, const Address& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void atomicExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Read-modify-write with memory. Return the value in memory before the
- // operation.
- //
- // x86-shared:
- // For 8-bit operations, `value` and `output` must have a byte subregister.
- // For Add and Sub, `temp` must be invalid.
- // For And, Or, and Xor, `output` must be eax and `temp` must have a byte
-@@ -3826,44 +3833,44 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp, Register output) DEFINED_ON(x86_shared);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- // x86:
- // `temp` must be ecx:ebx; `output` must be edx:eax.
- // x64:
- // For Add and Sub, `temp` is ignored.
- // For And, Or, and Xor, `output` must be rax.
- // ARM:
- // `temp` and `output` must be (even,odd) pairs and distinct from `value`.
- // ARM64:
- // Registers `value`, `temp`, and `output` must all differ.
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- // x64:
- // `value` can be any register.
- // ARM:
-@@ -3871,24 +3878,24 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM64:
- // Registers `value` and `temp` must differ.
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- // 64-bit atomic load. On 64-bit systems, use regular load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `output` must be (even,odd) pair.
-
- void atomicLoad64(const Synchronization& sync, const Address& mem,
-@@ -3930,43 +3937,43 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp,
- Register output) DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const Address& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-@@ -3977,23 +3984,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // Read-modify-write with memory. Return no value.
- //
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp)
-@@ -4009,22 +4016,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp)
- DEFINED_ON(x86_shared);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- // 64-bit wide operations.
-
- // 64-bit atomic load. On 64-bit systems, use regular wasm load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `temp` should be invalid; `output` must be (even,odd) pair.
-@@ -4074,22 +4081,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM: Registers must be distinct; `temp` and `output` must be (even,odd)
- // pairs.
- // MIPS: Registers must be distinct.
- // MIPS32: `temp` should be invalid.
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const Address& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const BaseIndex& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-@@ -4131,42 +4138,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
-@@ -4182,23 +4189,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-@@ -4209,22 +4216,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp) DEFINED_ON(x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicIsLockFreeJS(Register value, Register output);
-
- // ========================================================================
- // Spectre Mitigations.
- //
- // Spectre attacks are side-channel attacks based on cache pollution or
- // slow-execution of some instructions. We have multiple spectre mitigations
-@@ -4803,17 +4810,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // StackPointer manipulation functions.
- // On ARM64, the StackPointer is implemented as two synchronized registers.
- // Code shared across platforms must use these functions to be valid.
- template <typename T>
- inline void addToStackPtr(T t);
- template <typename T>
- inline void addStackPtrTo(T t);
-
-- void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64);
-+ void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64, ppc64);
- void subFromStackPtr(Register reg);
-
- template <typename T>
- void subStackPtrFrom(T t) {
- subPtr(getStackPointer(), t);
- }
-
- template <typename T>
-diff --git a/js/src/jit/MoveEmitter.h b/js/src/jit/MoveEmitter.h
-index 6c62c0561a..30ee4b61a5 100644
---- a/js/src/jit/MoveEmitter.h
-+++ b/js/src/jit/MoveEmitter.h
-@@ -12,15 +12,17 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MoveEmitter-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MoveEmitter-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MoveEmitter-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MoveEmitter-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MoveEmitter-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MoveEmitter-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #endif /* jit_MoveEmitter_h */
-diff --git a/js/src/jit/Registers.h b/js/src/jit/Registers.h
-index 67c8661004..ef49df83e5 100644
---- a/js/src/jit/Registers.h
-+++ b/js/src/jit/Registers.h
-@@ -15,16 +15,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Architecture-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Architecture-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Architecture-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Architecture-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Architecture-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Architecture-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/SharedICHelpers-inl.h b/js/src/jit/SharedICHelpers-inl.h
-index 901c80cdd8..fd4a27d8bb 100644
---- a/js/src/jit/SharedICHelpers-inl.h
-+++ b/js/src/jit/SharedICHelpers-inl.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64-inl.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64-inl.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none-inl.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICHelpers.h b/js/src/jit/SharedICHelpers.h
-index 563cae3ccf..737ca1d5a5 100644
---- a/js/src/jit/SharedICHelpers.h
-+++ b/js/src/jit/SharedICHelpers.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICRegisters.h b/js/src/jit/SharedICRegisters.h
-index c87e5f8408..76239d5dde 100644
---- a/js/src/jit/SharedICRegisters.h
-+++ b/js/src/jit/SharedICRegisters.h
-@@ -14,16 +14,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICRegisters-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICRegisters-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/SharedICRegisters-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/SharedICRegisters-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICRegisters-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICRegisters-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/moz.build b/js/src/jit/moz.build
-index f50d86fc44..82cddd07af 100644
---- a/js/src/jit/moz.build
-+++ b/js/src/jit/moz.build
-@@ -227,17 +227,29 @@ elif CONFIG["JS_CODEGEN_MIPS32"] or CONFIG["JS_CODEGEN_MIPS64"]:
- "mips64/CodeGenerator-mips64.cpp",
- "mips64/Lowering-mips64.cpp",
- "mips64/MacroAssembler-mips64.cpp",
- "mips64/MoveEmitter-mips64.cpp",
- "mips64/Trampoline-mips64.cpp",
- ]
- if CONFIG["JS_SIMULATOR_MIPS64"]:
- UNIFIED_SOURCES += ["mips64/Simulator-mips64.cpp"]
--
-+elif CONFIG["JS_CODEGEN_PPC64"]:
-+ lir_inputs += ["ppc64/LIR-ppc64.h"]
-+ UNIFIED_SOURCES += [
-+ "ppc64/Architecture-ppc64.cpp",
-+ "ppc64/Assembler-ppc64.cpp",
-+ "ppc64/Bailouts-ppc64.cpp",
-+ "ppc64/CodeGenerator-ppc64.cpp",
-+ "ppc64/Lowering-ppc64.cpp",
-+ "ppc64/MacroAssembler-ppc64.cpp",
-+ "ppc64/MoveEmitter-ppc64.cpp",
-+ "ppc64/Trampoline-ppc64.cpp",
-+ "shared/AtomicOperations-shared-jit.cpp",
-+ ]
-
- # Generate jit/MIROpsGenerated.h from jit/MIROps.yaml
- GeneratedFile(
- "MIROpsGenerated.h",
- script="GenerateMIRFiles.py",
- entry_point="generate_mir_header",
- inputs=["MIROps.yaml"],
- )
-diff --git a/js/src/jit/shared/Assembler-shared.h b/js/src/jit/shared/Assembler-shared.h
-index dfb2bcb6b8..69ba759d42 100644
---- a/js/src/jit/shared/Assembler-shared.h
-+++ b/js/src/jit/shared/Assembler-shared.h
-@@ -20,23 +20,24 @@
- #include "jit/Registers.h"
- #include "jit/RegisterSets.h"
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "vm/HelperThreads.h"
- #include "vm/NativeObject.h"
- #include "wasm/WasmTypes.h"
-
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- // Push return addresses callee-side.
- # define JS_USE_LINK_REGISTER
- #endif
-
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-- defined(JS_CODEGEN_ARM64)
-+ defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_PPC64)
- // JS_CODELABEL_LINKMODE gives labels additional metadata
- // describing how Bind() should patch them.
- # define JS_CODELABEL_LINKMODE
- #endif
-
- namespace js {
- namespace jit {
-
-diff --git a/js/src/jit/shared/AtomicOperations-shared-jit.cpp b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-index 79463f118b..7c8eeaf89e 100644
---- a/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-+++ b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-@@ -133,16 +133,38 @@ static constexpr Register AtomicTemp = edx;
- // 64-bit registers for cmpxchg8b. ValReg/Val2Reg/Temp are not used in this
- // case.
-
- static constexpr Register64 AtomicValReg64(edx, eax);
- static constexpr Register64 AtomicVal2Reg64(ecx, ebx);
-
- // AtomicReturnReg64 is unused on x86.
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+// Selected registers match the argument registers, except that the Ptr is not
-+// in IntArgReg0 so as not to conflict with the result register.
-+
-+static const LiveRegisterSet AtomicNonVolatileRegs;
-+
-+static constexpr Register AtomicPtrReg = IntArgReg4;
-+static constexpr Register AtomicPtr2Reg = IntArgReg1;
-+static constexpr Register AtomicValReg = IntArgReg1;
-+static constexpr Register64 AtomicValReg64(IntArgReg1);
-+static constexpr Register AtomicVal2Reg = IntArgReg2;
-+static constexpr Register64 AtomicVal2Reg64(IntArgReg2);
-+static constexpr Register AtomicTemp = IntArgReg3;
-+static constexpr Register AtomicTemp2 = IntArgReg5;
-+static constexpr Register AtomicTemp3 = IntArgReg6;
-+static constexpr Register64 AtomicTemp64(IntArgReg3);
-+static constexpr Register64 AtomicTemp64_2(IntArgReg5);
-+static constexpr Register64 AtomicTemp64_3(IntArgReg6);
-+
-+static constexpr Register64 AtomicReturnReg64 = ReturnReg64;
-+
- #else
- # error "Unsupported platform"
- #endif
-
- // These are useful shorthands and hide the meaningless uint/int distinction.
-
- static constexpr Scalar::Type SIZE8 = Scalar::Uint8;
- static constexpr Scalar::Type SIZE16 = Scalar::Uint16;
-@@ -248,31 +270,37 @@ static uint32_t GenPrologue(MacroAssembler& masm, ArgIterator* iter) {
- uint32_t start = masm.currentOffset();
- masm.PushRegsInMask(AtomicNonVolatileRegs);
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // The return address is among the nonvolatile registers, if pushed at all.
- iter->argBase = masm.framePushed();
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // The return address is pushed separately.
- iter->argBase = sizeof(void*) + masm.framePushed();
-+#elif defined(JS_CODEGEN_PPC64)
-+// XXX
-+ // The return address is in LR (an SPR); it's not (probably) on the stack.
-+ iter->argBase = masm.framePushed();
- #else
- # error "Unsupported platform"
- #endif
- return start;
- }
-
- static void GenEpilogue(MacroAssembler& masm) {
- masm.PopRegsInMask(AtomicNonVolatileRegs);
- MOZ_ASSERT(masm.framePushed() == 0);
- #if defined(JS_CODEGEN_ARM64)
- masm.Ret();
- #elif defined(JS_CODEGEN_ARM)
- masm.mov(lr, pc);
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- masm.ret();
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.as_blr();
- #endif
- }
-
- #ifndef JS_64BIT
- static uint32_t GenNop(MacroAssembler& masm) {
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenEpilogue(masm);
-@@ -414,21 +442,31 @@ static uint32_t GenCmpxchg(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
- GenGprArg(masm, MIRType::Int32, &iter, AtomicVal2Reg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
- ReturnReg);
-+#endif
- break;
- case SIZE64:
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- GenGpr64Arg(masm, &iter, AtomicVal2Reg64);
- #if defined(JS_CODEGEN_X86)
- static_assert(AtomicValReg64 == Register64(edx, eax));
- static_assert(AtomicVal2Reg64 == Register64(ecx, ebx));
-
-@@ -453,19 +491,29 @@ static uint32_t GenExchange(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.atomicExchange(size, sync, addr, AtomicValReg, ReturnReg);
-+#endif
- break;
- case SIZE64:
- #if defined(JS_64BIT)
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- masm.atomicExchange64(sync, addr, AtomicValReg64, AtomicReturnReg64);
- break;
- #else
- MOZ_CRASH("64-bit atomic exchange not available on this platform");
-@@ -492,17 +540,22 @@ static uint32_t GenFetchOp(MacroAssembler& masm, Scalar::Type size, AtomicOp op,
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- Register tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register::Invalid()
- : AtomicTemp;
- #else
- Register tmp = AtomicTemp;
- #endif
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, AtomicTemp2,
-+ AtomicTemp3, ReturnReg);
-+#else
- masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, ReturnReg);
-+#endif
- break;
- }
- case SIZE64: {
- #if defined(JS_64BIT)
- # if defined(JS_CODEGEN_X64)
- Register64 tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register64::Invalid()
- : AtomicTemp64;
-@@ -636,16 +689,19 @@ static bool UnalignedAccessesAreOK() {
- #endif
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return true;
- #elif defined(JS_CODEGEN_ARM)
- return !HasAlignmentFault();
- #elif defined(JS_CODEGEN_ARM64)
- // This is not necessarily true but it's the best guess right now.
- return true;
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We'd sure like to avoid it, even though it works.
-+ return false;
- #else
- # error "Unsupported platform"
- #endif
- }
-
- void AtomicMemcpyDownUnsynchronized(uint8_t* dest, const uint8_t* src,
- size_t nbytes) {
- const uint8_t* lim = src + nbytes;
-diff --git a/js/src/jsapi-tests/testJitABIcalls.cpp b/js/src/jsapi-tests/testJitABIcalls.cpp
-index 02b67da3ca..bd45389b21 100644
---- a/js/src/jsapi-tests/testJitABIcalls.cpp
-+++ b/js/src/jsapi-tests/testJitABIcalls.cpp
-@@ -653,16 +653,19 @@ class JitABICall final : public JSAPITest, public DefineCheckArgs<Sig> {
- Register base = r8;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS32)
- Register base = t1;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS64)
- Register base = t1;
- regs.take(base);
-+#elif defined(JS_CODEGEN_PPC64)
-+ Register base = r0;
-+ regs.take(base);
- #else
- # error "Unknown architecture!"
- #endif
-
- Register setup = regs.takeAny();
-
- this->generateCalls(masm, base, setup);
-
-diff --git a/js/src/jsapi-tests/testsJit.cpp b/js/src/jsapi-tests/testsJit.cpp
-index 069eef43fe..705609df2c 100644
---- a/js/src/jsapi-tests/testsJit.cpp
-+++ b/js/src/jsapi-tests/testsJit.cpp
-@@ -20,16 +20,21 @@ void PrepareJit(js::jit::MacroAssembler& masm) {
- #endif
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Push the link register separately, since it's not a GPR.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PushRegsInMask(save);
- }
-
- // Generate the exit path of the JIT code, which restores every register. Then,
- // make it executable and run it.
-@@ -37,26 +42,35 @@ bool ExecuteJit(JSContext* cx, js::jit::MacroAssembler& masm) {
- using namespace js::jit;
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We pop after loading the regs.
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PopRegsInMask(save);
- #if defined(JS_CODEGEN_ARM64)
- // Return using the value popped into x30.
- masm.abiret();
-
- // Reset stack pointer.
- masm.SetStackPointer64(PseudoStackPointer64);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Pop LR and exit.
-+ masm.as_ld(ScratchRegister, StackPointer, 0);
-+ masm.xs_mtlr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, 8);
-+ masm.as_blr();
- #else
- // Exit the JIT-ed code using the ABI return style.
- masm.abiret();
- #endif
-
- if (masm.oom()) {
- return false;
- }
-diff --git a/js/src/util/Poison.h b/js/src/util/Poison.h
-index 8356ca1f00..5eeb111cf8 100644
---- a/js/src/util/Poison.h
-+++ b/js/src/util/Poison.h
-@@ -88,16 +88,18 @@ const uint8_t JS_SCOPE_DATA_TRAILING_NAMES_PATTERN = 0xCC;
- */
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) || \
- defined(JS_CODEGEN_NONE)
- # define JS_SWEPT_CODE_PATTERN 0xED // IN instruction, crashes in user mode.
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- # define JS_SWEPT_CODE_PATTERN 0xA3 // undefined instruction
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # define JS_SWEPT_CODE_PATTERN 0x01 // undefined instruction
-+#elif defined(JS_CODEGEN_PPC64) || defined(JS_CODEGEN_PPC)
-+# define JS_SWEPT_CODE_PATTERN 0x00 // architecturally defined as illegal
- #else
- # error "JS_SWEPT_CODE_PATTERN not defined for this platform"
- #endif
-
- enum class MemCheckKind : uint8_t {
- // Marks a region as poisoned. Memory sanitizers like ASan will crash when
- // accessing it (both reads and writes).
- MakeNoAccess,
-diff --git a/js/src/wasm/WasmBaselineCompile.cpp b/js/src/wasm/WasmBaselineCompile.cpp
-index 156f3cbbba..ab29f44713 100644
---- a/js/src/wasm/WasmBaselineCompile.cpp
-+++ b/js/src/wasm/WasmBaselineCompile.cpp
-@@ -138,16 +138,19 @@
- #if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips32/Assembler-mips32.h"
- #endif
- #if defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips64/Assembler-mips64.h"
- #endif
-+#if defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Assembler-ppc64.h"
-+#endif
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "util/Memory.h"
- #include "wasm/TypedObject.h"
- #include "wasm/WasmGC.h"
- #include "wasm/WasmGenerator.h"
- #include "wasm/WasmInstance.h"
- #include "wasm/WasmOpIter.h"
- #include "wasm/WasmSignalHandlers.h"
-@@ -288,16 +291,23 @@ static constexpr Register RabaldrScratchI32 = CallTempReg2;
- #endif
-
- #ifdef RABALDR_SCRATCH_F32_ALIASES_F64
- # if !defined(RABALDR_SCRATCH_F32) || !defined(RABALDR_SCRATCH_F64)
- # error "Bad configuration"
- # endif
- #endif
-
-+#ifdef JS_CODEGEN_PPC64
-+# define RABALDR_SCRATCH_I32
-+// We can use all the argregs up, and we don't want the JIT using our own
-+// private scratch registers, so this is the best option of what's left.
-+static constexpr Register RabaldrScratchI32 = r19;
-+#endif
-+
- template <MIRType t>
- struct RegTypeOf {
- #ifdef ENABLE_WASM_SIMD
- static_assert(t == MIRType::Float32 || t == MIRType::Double ||
- t == MIRType::Simd128,
- "Float mask type");
- #else
- static_assert(t == MIRType::Float32 || t == MIRType::Double,
-@@ -550,16 +560,18 @@ struct SpecificRegs {};
- #elif defined(JS_CODEGEN_MIPS32)
- struct SpecificRegs {
- RegI64 abiReturnRegI64;
-
- SpecificRegs() : abiReturnRegI64(ReturnReg64) {}
- };
- #elif defined(JS_CODEGEN_MIPS64)
- struct SpecificRegs {};
-+#elif defined(JS_CODEGEN_PPC64)
-+struct SpecificRegs {};
- #else
- struct SpecificRegs {
- # ifndef JS_64BIT
- RegI64 abiReturnRegI64;
- # endif
-
- SpecificRegs() { MOZ_CRASH("BaseCompiler porting interface: SpecificRegs"); }
- };
-@@ -6038,16 +6050,25 @@ class BaseCompiler final : public BaseCompilerInterface {
- ABIArg argLoc = call->abi.next(MIRType::Int32);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- loadI32(arg, scratch);
- masm.store32(scratch, Address(masm.getStackPointer(),
- argLoc.offsetFromArgBase()));
- } else {
- loadI32(arg, RegI32(argLoc.gpr()));
-+#if JS_CODEGEN_PPC64
-+ // If this is a call to compiled C++, we must ensure that the
-+ // upper 32 bits are clear: addi can sign-extend, which yields
-+ // difficult-to-diagnose bugs when the function expects a uint32_t
-+ // but the register it gets has a residual 64-bit value.
-+ if (call->usesSystemAbi) {
-+ masm.as_rldicl(argLoc.gpr(), argLoc.gpr(), 0, 32);
-+ }
-+#endif
- }
- break;
- }
- case ValType::I64: {
- ABIArg argLoc = call->abi.next(MIRType::Int64);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- #ifdef JS_PUNBOX64
-@@ -6324,17 +6345,18 @@ class BaseCompiler final : public BaseCompilerInterface {
-
- // Compute the absolute table base pointer into `scratch`, offset by 8
- // to account for the fact that ma_mov read PC+8.
- masm.ma_sub(Imm32(offset + 8), scratch, arm_scratch);
-
- // Jump indirect via table element.
- masm.ma_ldr(DTRAddr(scratch, DtrRegImmShift(switchValue, LSL, 2)), pc,
- Offset, Assembler::Always);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- ScratchI32 scratch(*this);
- CodeLabel tableCl;
-
- masm.ma_li(scratch, &tableCl);
-
- tableCl.target()->bind(theTable->offset());
- masm.addCodeLabel(tableCl);
-
-@@ -6493,16 +6515,22 @@ class BaseCompiler final : public BaseCompilerInterface {
- # elif defined(JS_CODEGEN_ARM64)
- ARMRegister sd(srcDest.reg, 64);
- ARMRegister r(rhs.reg, 64);
- if (isUnsigned) {
- masm.Udiv(sd, sd, r);
- } else {
- masm.Sdiv(sd, sd, r);
- }
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (isUnsigned) {
-+ masm.as_divdu(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: quotientI64");
- # endif
- masm.bind(&done);
- }
-
- void remainderI64(RegI64 rhs, RegI64 srcDest, RegI64 reserved,
- IsUnsigned isUnsigned, bool isConst, int64_t c) {
-@@ -6544,29 +6572,46 @@ class BaseCompiler final : public BaseCompilerInterface {
- ARMRegister t(temp, 64);
- if (isUnsigned) {
- masm.Udiv(t, sd, r);
- } else {
- masm.Sdiv(t, sd, r);
- }
- masm.Mul(t, t, r);
- masm.Sub(sd, sd, t);
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (js::jit::HasPPCISA3()) {
-+ if (isUnsigned) {
-+ masm.as_modud(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_modsd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
-+ } else {
-+ ScratchI32 temp(*this);
-+ if (isUnsigned) {
-+ masm.as_divdu(temp, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(temp, srcDest.reg, rhs.reg);
-+ }
-+ masm.as_mulld(temp, temp, rhs.reg);
-+ masm.as_subf(srcDest.reg, temp, srcDest.reg); // T = B - A
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: remainderI64");
- # endif
- masm.bind(&done);
- }
- #endif // RABALDR_INT_DIV_I64_CALLOUT
-
- RegI32 needRotate64Temp() {
- #if defined(JS_CODEGEN_X86)
- return needI32();
- #elif defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- return RegI32::Invalid();
- #else
- MOZ_CRASH("BaseCompiler platform hook: needRotate64Temp");
- #endif
- }
-
- class OutOfLineTruncateCheckF32OrF64ToI32 : public OutOfLineCode {
- AnyReg src;
-@@ -6869,30 +6914,35 @@ class BaseCompiler final : public BaseCompilerInterface {
- RegI64 ptr64 = fromI32(ptr);
-
- // In principle there may be non-zero bits in the upper bits of the
- // register; clear them.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended (see comment block "64-bit GPRs
- // carrying 32-bit values" in MacroAssembler.h); we already have that.
- masm.assertCanonicalInt32(ptr);
-+# elif defined(JS_CODEGEN_PPC64)
-+ // The canonical value is sign-extended.
-+ masm.as_rldicl(ptr, ptr, 0, 32); // "clrldi"
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
-
- // Any Spectre mitigation will appear to update the ptr64 register.
- masm.wasmBoundsCheck64(
- Assembler::Below, ptr64,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
-
- // Restore the value to the canonical form for a 32-bit value in a
- // 64-bit register and/or the appropriate form for further use in the
- // indexing instruction.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended; we already have that.
-+# elif defined(JS_CODEGEN_PPC64)
-+ // Leave it zero-extended.
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
- } else {
- masm.wasmBoundsCheck32(
- Assembler::Below, ptr,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
- }
-@@ -6903,17 +6953,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- #endif
- masm.wasmTrap(Trap::OutOfBounds, bytecodeOffset());
- masm.bind(&ok);
- }
- }
-
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- BaseIndex prepareAtomicMemoryAccess(MemoryAccessDesc* access,
- AccessCheck* check, RegI32 tls,
- RegI32 ptr) {
- MOZ_ASSERT(needTlsForAccess(*check) == tls.isValid());
- prepareMemoryAccess(access, check, tls, ptr);
- return BaseIndex(HeapReg, ptr, TimesOne, access->offset());
- }
- #elif defined(JS_CODEGEN_X86)
-@@ -7001,17 +7051,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- if (dest.tag == AnyReg::I64) {
- MOZ_ASSERT(dest.i64() == specific_.abiReturnRegI64);
- masm.wasmLoadI64(*access, srcAddr, dest.i64());
- } else {
- // For 8 bit loads, this will generate movsbl or movzbl, so
- // there's no constraint on what the output register may be.
- masm.wasmLoad(*access, srcAddr, dest.any());
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (dest.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedLoadI64(*access, HeapReg, ptr, ptr, dest.i64(),
- temp1);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedLoadFP(*access, HeapReg, ptr, ptr, dest.f32(),
-@@ -7102,17 +7154,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- MOZ_ASSERT(temp.isInvalid());
- if (access->type() == Scalar::Int64) {
- masm.wasmStoreI64(*access, src.i64(), HeapReg, ptr, ptr);
- } else if (src.tag == AnyReg::I64) {
- masm.wasmStore(*access, AnyRegister(src.i64().low), HeapReg, ptr, ptr);
- } else {
- masm.wasmStore(*access, src.any(), HeapReg, ptr, ptr);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (src.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedStoreI64(*access, src.i64(), HeapReg, ptr, ptr,
- temp);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedStoreFP(*access, src.f32(), HeapReg, ptr, ptr,
-@@ -7160,17 +7214,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- void maybeFree(BaseCompiler* bc) {
- for (size_t i = 0; i < Count; ++i) {
- bc->maybeFree(this->operator[](i));
- }
- }
- };
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicRMW32Temps = Atomic32Temps<3>;
- #else
- using AtomicRMW32Temps = Atomic32Temps<1>;
- #endif
-
- template <typename T>
- void atomicRMW32(const MemoryAccessDesc& access, T srcAddr, AtomicOp op,
- RegI32 rv, RegI32 rd, const AtomicRMW32Temps& temps) {
-@@ -7187,17 +7242,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temp, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], rd);
- #endif
- break;
- default: {
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7208,17 +7264,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- // On x86, V is Address. On other platforms, it is Register64.
- // T is BaseIndex or Address.
- template <typename T, typename V>
- void atomicRMW64(const MemoryAccessDesc& access, const T& srcAddr,
- AtomicOp op, V value, Register64 temp, Register64 rd) {
- masm.wasmAtomicFetchOp64(access, op, value, srcAddr, temp, rd);
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicCmpXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicCmpXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicCmpXchg32(const MemoryAccessDesc& access, T srcAddr,
- RegI32 rexpect, RegI32 rnew, RegI32 rd,
-@@ -7236,29 +7293,31 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, temps[0],
- temps[1], temps[2], rd);
- #else
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
- }
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicXchg32(const MemoryAccessDesc& access, T srcAddr, RegI32 rv,
- RegI32 rd, const AtomicXchg32Temps& temps) {
-@@ -7275,17 +7334,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- }
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicExchange(access, srcAddr, rv, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7342,16 +7402,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_MIPS32)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM64)
- pop2xI64(r0, r1);
-+#elif defined(JS_CODEGEN_PPC64)
-+ pop2xI64(r0, r1);
- #else
- MOZ_CRASH("BaseCompiler porting interface: pop2xI64ForMulI64");
- #endif
- }
-
- void pop2xI64ForDivI64(RegI64* r0, RegI64* r1, RegI64* reserved) {
- #if defined(JS_CODEGEN_X64)
- // r0 must be rax, and rdx will be clobbered.
-@@ -7529,17 +7591,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI32();
- }
- setRd(bc->needI32());
- }
- ~PopAtomicCmpXchg32Regs() {
- bc->freeI32(rnew);
- bc->freeI32(rexpect);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- if (type == ValType::I64) {
- rnew = bc->popI64ToI32();
- rexpect = bc->popI64ToI32();
- } else {
- rnew = bc->popI32();
-@@ -7606,17 +7669,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI64();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rnew = bc->popI64();
- rexpect = bc->popI64();
- setRd(bc->needI64());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
-@@ -7658,17 +7721,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- bc->needI64(bc->specific_.edx_eax);
- setRd(bc->specific_.edx_eax);
- }
- ~PopAtomicLoad64Regs() { bc->freeI32(bc->specific_.ecx); }
- # elif defined(JS_CODEGEN_ARM)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64Pair());
- }
--# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64());
- }
- # else
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: PopAtomicLoad64Regs");
- }
- # endif
-@@ -7745,17 +7809,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- temps.allocate(bc);
- setRd(bc->needI32());
- }
- ~PopAtomicRMW32Regs() {
- bc->freeI32(rv);
- temps.maybeFree(bc);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType, AtomicOp op)
- : Base(bc) {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
-
-@@ -7833,17 +7898,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- temp = bc->needI64Pair();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW64Regs(BaseCompiler* bc, AtomicOp) : Base(bc) {
- rv = bc->popI64();
- temp = bc->needI64();
- setRd(bc->needI64());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
-@@ -7888,17 +7953,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- setRd(bc->needI32());
- }
- ~PopAtomicXchg32Regs() { bc->freeI32(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
- setRd(bc->needI32());
-@@ -7954,17 +8020,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #elif defined(JS_CODEGEN_ARM)
- // Both rv and rd must be odd/even pairs.
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64Pair());
- setRd(bc->needI64Pair());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64());
- setRd(bc->needI64());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #else
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: xchg64");
-@@ -8968,16 +9035,18 @@ static void CtzI32(MacroAssembler& masm, RegI32 rsd) {
-
- // Currently common to PopcntI32 and PopcntI64
- static RegI32 PopcntTemp(BaseCompiler& bc) {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return AssemblerX86Shared::HasPOPCNT() ? RegI32::Invalid() : bc.needI32();
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- return bc.needI32();
-+#elif defined(JS_CODEGEN_PPC64)
-+ return RegI32::Invalid(); // We rock.
- #else
- MOZ_CRASH("BaseCompiler platform hook: PopcntTemp");
- #endif
- }
-
- static void PopcntI32(BaseCompiler& bc, RegI32 rsd, RegI32 temp) {
- bc.masm.popcnt32(rsd, rsd, temp);
- }
-@@ -11982,17 +12051,17 @@ RegI32 BaseCompiler::popMemory32Access(MemoryAccessDesc* access,
- bceCheckLocal(access, check, local);
- }
-
- return popI32();
- }
-
- void BaseCompiler::pushHeapBase() {
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- RegI64 heapBase = needI64();
- moveI64(RegI64(Register64(HeapReg)), heapBase);
- pushI64(heapBase);
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32)
- RegI32 heapBase = needI32();
- moveI32(RegI32(HeapReg), heapBase);
- pushI32(heapBase);
- #elif defined(JS_CODEGEN_X86)
-@@ -17244,17 +17313,19 @@ bool js::wasm::BaselinePlatformSupport() {
- // they are definitely implemented on the Cortex-A7 and Cortex-A15
- // and on all ARMv8 systems.
- if (!HasIDIV()) {
- return false;
- }
- #endif
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) || \
- defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+ // PPC64 gates on other prerequisites not specified here.
- return true;
- #else
- return false;
- #endif
- }
-
- bool js::wasm::BaselineCompileFunctions(const ModuleEnvironment& moduleEnv,
- const CompilerEnvironment& compilerEnv,
-diff --git a/js/src/wasm/WasmCompile.cpp b/js/src/wasm/WasmCompile.cpp
-index 0f456aaaa5..f0694f1b9e 100644
---- a/js/src/wasm/WasmCompile.cpp
-+++ b/js/src/wasm/WasmCompile.cpp
-@@ -45,16 +45,17 @@ using namespace js::wasm;
- uint32_t wasm::ObservedCPUFeatures() {
- enum Arch {
- X86 = 0x1,
- X64 = 0x2,
- ARM = 0x3,
- MIPS = 0x4,
- MIPS64 = 0x5,
- ARM64 = 0x6,
-+ PPC64 = 0x7,
- ARCH_BITS = 3
- };
-
- #if defined(JS_CODEGEN_X86)
- MOZ_ASSERT(uint32_t(jit::CPUInfo::GetSSEVersion()) <=
- (UINT32_MAX >> ARCH_BITS));
- return X86 | (uint32_t(jit::CPUInfo::GetSSEVersion()) << ARCH_BITS);
- #elif defined(JS_CODEGEN_X64)
-@@ -68,16 +69,19 @@ uint32_t wasm::ObservedCPUFeatures() {
- MOZ_ASSERT(jit::GetARM64Flags() <= (UINT32_MAX >> ARCH_BITS));
- return ARM64 | (jit::GetARM64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS32)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS | (jit::GetMIPSFlags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS64)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS64 | (jit::GetMIPSFlags() << ARCH_BITS);
-+#elif defined(JS_CODEGEN_PPC64)
-+ MOZ_ASSERT(jit::GetPPC64Flags() <= (UINT32_MAX >> ARCH_BITS));
-+ return PPC64 | (jit::GetPPC64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_NONE)
- return 0;
- #else
- # error "unknown architecture"
- #endif
- }
-
- FeatureArgs FeatureArgs::build(JSContext* cx, const FeatureOptions& options) {
-diff --git a/js/src/wasm/WasmFrame.h b/js/src/wasm/WasmFrame.h
-index 85f2612d14..9919205739 100644
---- a/js/src/wasm/WasmFrame.h
-+++ b/js/src/wasm/WasmFrame.h
-@@ -53,16 +53,25 @@ constexpr uintptr_t ExitOrJitEntryFPTag = 0x1;
- // before the function has made its stack reservation, the stack alignment is
- // sizeof(Frame) % WasmStackAlignment.
- //
- // During MacroAssembler code generation, the bytes pushed after the wasm::Frame
- // are counted by masm.framePushed. Thus, the stack alignment at any point in
- // time is (sizeof(wasm::Frame) + masm.framePushed) % WasmStackAlignment.
-
- class Frame {
-+#if defined(JS_CODEGEN_PPC64)
-+ // Since Wasm can call directly to ABI-compliant routines, the Frame must
-+ // have an ABI-compliant linkage area. We allocate four doublewords, the
-+ // minimum size.
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
- // See GenerateCallableEpilogue for why this must be
- // the first field of wasm::Frame (in a downward-growing stack).
- // It's either the caller's Frame*, for wasm callers, or the JIT caller frame
- // plus a tag otherwise.
- uint8_t* callerFP_;
-
- // The return address pushed by the call (in the case of ARM/MIPS the return
- // address is pushed by the first instruction of the prologue).
-@@ -115,18 +124,21 @@ class Frame {
- static uint8_t* addExitOrJitEntryFPTag(const Frame* fp) {
- MOZ_ASSERT(!isExitOrJitEntryFP(fp));
- return reinterpret_cast<uint8_t*>(reinterpret_cast<uintptr_t>(fp) |
- ExitOrJitEntryFPTag);
- }
- };
-
- static_assert(!std::is_polymorphic_v<Frame>, "Frame doesn't need a vtable.");
-+#if !defined(JS_CODEGEN_PPC64)
-+// Not on PowerPC, it's not.
- static_assert(sizeof(Frame) == 2 * sizeof(void*),
- "Frame is a two pointer structure");
-+#endif
-
- class FrameWithTls : public Frame {
- TlsData* calleeTls_;
- TlsData* callerTls_;
-
- public:
- TlsData* calleeTls() { return calleeTls_; }
- TlsData* callerTls() { return callerTls_; }
-diff --git a/js/src/wasm/WasmFrameIter.cpp b/js/src/wasm/WasmFrameIter.cpp
-index dffab53940..5da8d6c730 100644
---- a/js/src/wasm/WasmFrameIter.cpp
-+++ b/js/src/wasm/WasmFrameIter.cpp
-@@ -358,16 +358,21 @@ static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
- static_assert(BeforePushRetAddr == 0, "Required by StartUnwinding");
- static_assert(PushedFP > PushedRetAddr, "Required by StartUnwinding");
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- static const unsigned PushedRetAddr = 8;
- static const unsigned PushedFP = 12;
- static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
-+#elif defined(JS_CODEGEN_PPC64)
-+static const unsigned PushedRetAddr = 12;
-+static const unsigned PushedFP = 16;
-+static const unsigned SetFP = 20;
-+static const unsigned PoppedFP = 8;
- #elif defined(JS_CODEGEN_NONE)
- // Synthetic values to satisfy asserts and avoid compiler warnings.
- static const unsigned PushedRetAddr = 0;
- static const unsigned PushedFP = 1;
- static const unsigned SetFP = 2;
- static const unsigned PoppedFP = 3;
- #else
- # error "Unknown architecture!"
-@@ -453,16 +458,38 @@ static void GenerateCallablePrologue(MacroAssembler& masm, uint32_t* entry) {
- MemOperand(sp, Frame::callerFPOffset()));
- MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
- masm.Mov(ARMRegister(FramePointer, 64), sp);
- MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-
- // And restore the SP-reg setting, per comment above.
- masm.SetStackPointer64(stashedSPreg);
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ {
-+ *entry = masm.currentOffset();
-+
-+ // These must be in this precise order. Fortunately we can subsume the
-+ // SPR load into the initial "verse" since it is treated atomically.
-+ // The linkage area required for ABI compliance is baked into the Frame.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, -(sizeof(Frame)));
-+ masm.as_std(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedRetAddr == masm.currentOffset() - *entry);
-+ masm.as_std(FramePointer, StackPointer, Frame::callerFPOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
-+ masm.xs_mr(FramePointer, StackPointer);
-+ MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-+
-+ // Burn nops because we have to make this a multiple of 16 and the mfspr
-+ // just screwed us.
-+ masm.as_nop(); // 24
-+ masm.as_nop(); // 28
-+ masm.as_nop(); // 32 // trap point
-+ }
- #else
- {
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
-
- *entry = masm.currentOffset();
-
-@@ -527,16 +554,28 @@ static void GenerateCallableEpilogue(MacroAssembler& masm, unsigned framePushed,
- // use it. Hence we have to do it "by hand".
- masm.Mov(PseudoStackPointer64, vixl::sp);
-
- masm.Ret(ARMRegister(lr, 64));
-
- // See comment at equivalent place in |GenerateCallablePrologue| above.
- masm.SetStackPointer64(stashedSPreg);
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+ masm.as_ld(FramePointer, StackPointer, Frame::callerFPOffset());
-+ poppedFP = masm.currentOffset();
-+ // This is suboptimal since we get serialized, but has to be in this order.
-+ masm.as_ld(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ masm.xs_mtlr(ScratchRegister);
-+ *ret = masm.currentOffset();
-+
-+ masm.as_addi(StackPointer, StackPointer, sizeof(Frame));
-+ masm.as_blr();
-+
- #else
- // Forbid pools for the same reason as described in GenerateCallablePrologue.
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm, /* number of instructions in scope = */ 6);
- # endif
-
- // There is an important ordering constraint here: fp must be repointed to
- // the caller's frame before any field of the frame currently pointed to by
-@@ -773,16 +812,23 @@ void wasm::GenerateJitEntryPrologue(MacroAssembler& masm, Offsets* offsets) {
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
- offsets->begin = masm.currentOffset();
- static_assert(BeforePushRetAddr == 0);
- // Subtract from SP first as SP must be aligned before offsetting.
- masm.Sub(sp, sp, 8);
- masm.storePtr(lr, Address(masm.getStackPointer(), 0));
- masm.adjustFrame(8);
-+#elif defined(JS_CODEGEN_PPC64)
-+ offsets->begin = masm.currentOffset();
-+
-+ // We have to burn a nop here to match the other prologue length.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_nop(); // might as well explicitly wait for the mfspr to complete
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #else
- // The x86/x64 call instruction pushes the return address.
- offsets->begin = masm.currentOffset();
- #endif
- MOZ_ASSERT_IF(!masm.oom(),
- PushedRetAddr == masm.currentOffset() - offsets->begin);
-
- // Save jit frame pointer, so unwinding from wasm to jit frames is trivial.
-diff --git a/js/src/wasm/WasmGC.cpp b/js/src/wasm/WasmGC.cpp
-index 4eb77a81a2..3f00cbb632 100644
---- a/js/src/wasm/WasmGC.cpp
-+++ b/js/src/wasm/WasmGC.cpp
-@@ -284,16 +284,33 @@ bool IsValidStackMapKey(bool debugEnabled, const uint8_t* nextPC) {
- (insn[-1] & 0xfffffc1f) == 0xd63f0000 || // blr reg
- (insn[-1] & 0xfc000000) == 0x94000000 || // bl simm26
- (debugEnabled && insn[-1] == 0xd503201f)); // nop
-
- # elif defined(JS_CODEGEN_MIPS64)
- // TODO (bug 1699696): Implement this. As for the platforms above, we need to
- // enumerate all code sequences that can precede the stackmap location.
- return true;
-+# elif defined(JS_CODEGEN_PPC64)
-+// XXX: we should just be able to use inst[0]
-+ const uint32_t* insn = (const uint32_t*)nextPC;
-+ js::jit::Instruction* inst = (js::jit::Instruction*)nextPC;
-+ //fprintf(stderr, "IsValidStackMapKey: 0x%lx 0x%08x\n", (uint64_t)nextPC, insn[0]);
-+ return (((uintptr_t(insn) & 3) == 0) &&
-+ (inst[0].extractOpcode() == js::jit::PPC_addi || // stack allocate
-+ inst[0].extractOpcode() == js::jit::PPC_addis || // load immediate
-+ inst[0].extractOpcode() == js::jit::PPC_cmpwi || // test after bl
-+ inst[0].extractOpcode() == js::jit::PPC_cmpw || // (extsw, same)
-+ inst[0].extractOpcode() == js::jit::PPC_lfd || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lfs || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lwz || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_ld || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_b || // branch
-+ inst[0].encode() == js::jit::PPC_nop || // GET BACK TO WORK
-+ inst[0].encode() == js::jit::PPC_stop)); // designated throw
- # else
- MOZ_CRASH("IsValidStackMapKey: requires implementation on this platform");
- # endif
- }
- #endif
-
- } // namespace wasm
- } // namespace js
-diff --git a/js/src/wasm/WasmSignalHandlers.cpp b/js/src/wasm/WasmSignalHandlers.cpp
-index 4ab2a44192..1a51061a12 100644
---- a/js/src/wasm/WasmSignalHandlers.cpp
-+++ b/js/src/wasm/WasmSignalHandlers.cpp
-@@ -101,16 +101,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->sc_pc)
- # define RFP_sig(p) ((p)->sc_regs[30])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->sc_frame.fixreg[1])
-+# define R31_sig(p) ((p)->sc_frame.fixreg[31])
- # define R32_sig(p) ((p)->sc_frame.srr0)
- # endif
- #elif defined(__linux__) || defined(__sun)
- # if defined(__linux__)
- # define EIP_sig(p) ((p)->uc_mcontext.gregs[REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.gregs[REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.gregs[REG_ESP])
- # else
-@@ -147,16 +148,17 @@ using mozilla::DebugOnly;
- # if defined(__linux__) && (defined(__sparc__) && defined(__arch64__))
- # define PC_sig(p) ((p)->uc_mcontext.mc_gregs[MC_PC])
- # define FP_sig(p) ((p)->uc_mcontext.mc_fp)
- # define SP_sig(p) ((p)->uc_mcontext.mc_i7)
- # endif
- # if defined(__linux__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.gp_regs[1])
-+# define R31_sig(p) ((p)->uc_mcontext.gp_regs[31])
- # define R32_sig(p) ((p)->uc_mcontext.gp_regs[32])
- # endif
- #elif defined(__NetBSD__)
- # define EIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.__gregs[_REG_ESP])
- # define RIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RIP])
- # define RSP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSP])
-@@ -173,16 +175,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.__gregs[_REG_EPC])
- # define RFP_sig(p) ((p)->uc_mcontext.__gregs[_REG_S8])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->uc_mcontext.__gregs[_REG_R1])
-+# define R31_sig(p) ((p)->uc_mcontext.__gregs[_REG_R31])
- # define R32_sig(p) ((p)->uc_mcontext.__gregs[_REG_PC])
- # endif
- #elif defined(__DragonFly__) || defined(__FreeBSD__) || \
- defined(__FreeBSD_kernel__)
- # define EIP_sig(p) ((p)->uc_mcontext.mc_eip)
- # define EBP_sig(p) ((p)->uc_mcontext.mc_ebp)
- # define ESP_sig(p) ((p)->uc_mcontext.mc_esp)
- # define RIP_sig(p) ((p)->uc_mcontext.mc_rip)
-@@ -207,16 +210,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__FreeBSD__) && defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.mc_pc)
- # define RFP_sig(p) ((p)->uc_mcontext.mc_regs[30])
- # endif
- # if defined(__FreeBSD__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.mc_gpr[1])
-+# define R31_sig(p) ((p)->uc_mcontext.mc_gpr[31])
- # define R32_sig(p) ((p)->uc_mcontext.mc_srr0)
- # endif
- #elif defined(XP_DARWIN)
- # define EIP_sig(p) ((p)->thread.uts.ts32.__eip)
- # define EBP_sig(p) ((p)->thread.uts.ts32.__ebp)
- # define ESP_sig(p) ((p)->thread.uts.ts32.__esp)
- # define RIP_sig(p) ((p)->thread.__rip)
- # define RBP_sig(p) ((p)->thread.__rbp)
-@@ -367,17 +371,17 @@ struct macos_aarch64_context {
- # define PC_sig(p) EPC_sig(p)
- # define FP_sig(p) RFP_sig(p)
- # define SP_sig(p) RSP_sig(p)
- # define LR_sig(p) R31_sig(p)
- #elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define PC_sig(p) R32_sig(p)
- # define SP_sig(p) R01_sig(p)
--# define FP_sig(p) R01_sig(p)
-+# define FP_sig(p) R31_sig(p)
- #endif
-
- static void SetContextPC(CONTEXT* context, uint8_t* pc) {
- #ifdef PC_sig
- *reinterpret_cast<uint8_t**>(&PC_sig(context)) = pc;
- #else
- MOZ_CRASH();
- #endif
-diff --git a/js/src/wasm/WasmStubs.cpp b/js/src/wasm/WasmStubs.cpp
-index 59a5cf18bf..dbc10c6e2c 100644
---- a/js/src/wasm/WasmStubs.cpp
-+++ b/js/src/wasm/WasmStubs.cpp
-@@ -719,17 +719,17 @@ static bool GenerateInterpEntry(MacroAssembler& masm, const FuncExport& fe,
- AssertExpectedSP(masm);
- masm.haltingAlign(CodeAlignment);
-
- offsets->begin = masm.currentOffset();
-
- // Save the return address if it wasn't already saved by the call insn.
- #ifdef JS_USE_LINK_REGISTER
- # if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- masm.pushReturnAddress();
- # elif defined(JS_CODEGEN_ARM64)
- // WasmPush updates framePushed() unlike pushReturnAddress(), but that's
- // cancelled by the setFramePushed() below.
- WasmPush(masm, lr);
- # else
- MOZ_CRASH("Implement this");
- # endif
-@@ -2111,17 +2111,26 @@ static bool GenerateImportInterpExit(MacroAssembler& masm, const FuncImport& fi,
- masm.storePtr(scratch,
- Address(masm.getStackPointer(), i->offsetFromArgBase()));
- }
- i++;
- MOZ_ASSERT(i.done());
-
- // Make the call, test whether it succeeded, and extract the return value.
- AssertStackAlignment(masm, ABIStackAlignment);
-+#ifdef JS_CODEGEN_PPC64
-+ // Because this is calling an ABI-compliant function, we have to pull down
-+ // a dummy linkage area or the values on the stack will be stomped on. The
-+ // minimum size is sufficient.
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), -32);
-+#endif
- masm.call(SymbolicAddress::CallImport_General);
-+#ifdef JS_CODEGEN_PPC64
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), 32);
-+#endif
- masm.branchTest32(Assembler::Zero, ReturnReg, ReturnReg, throwLabel);
-
- ResultType resultType = ResultType::Vector(fi.funcType().results());
- ValType registerResultType;
- for (ABIResultIter iter(resultType); !iter.done(); iter.next()) {
- if (iter.cur().inRegister()) {
- MOZ_ASSERT(!registerResultType.isValid());
- registerResultType = iter.cur().type();
-@@ -2673,16 +2682,21 @@ static const LiveRegisterSet RegsToPreserve(
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // It's correct to use FloatRegisters::AllMask even when SIMD is not enabled;
- // PushRegsInMask strips out the high lanes of the XMM registers in this case,
- // while the singles will be stripped as they are aliased by the larger doubles.
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(Registers::AllMask &
- ~(Registers::SetType(1) << Registers::StackPointer)),
- FloatRegisterSet(FloatRegisters::AllMask));
-+#elif defined(JS_CODEGEN_PPC64)
-+// Note that this includes no SPRs, since the JIT is unaware of them.
-+static const LiveRegisterSet RegsToPreserve(
-+ GeneralRegisterSet(Registers::AllMask),
-+ FloatRegisterSet(FloatRegisters::AllMask));
- #else
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(0), FloatRegisterSet(FloatRegisters::AllDoubleMask));
- # ifdef ENABLE_WASM_SIMD
- # error "no SIMD support"
- # endif
- #endif
-
-diff --git a/modules/libpref/init/StaticPrefList.yaml b/modules/libpref/init/StaticPrefList.yaml
-index d81025b282..43b75c6ae0 100644
---- a/modules/libpref/init/StaticPrefList.yaml
-+++ b/modules/libpref/init/StaticPrefList.yaml
-@@ -5729,17 +5729,17 @@
- - name: javascript.options.baselinejit
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- - name: javascript.options.ion
- type: bool
-- value: true
-+ value: false
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- # The irregexp JIT for regex evaluation.
- - name: javascript.options.native_regexp
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
-@@ -5968,17 +5968,17 @@
- value: 6 * 1024 * 1024
- #else
- value: 2 * 1024 * 1024
- #endif
- mirror: always
-
- - name: javascript.options.wasm_optimizingjit
- type: bool
-- value: true
-+ value: false
- mirror: always
-
- #if defined(ENABLE_WASM_SIMD)
- - name: javascript.options.wasm_simd
- type: bool
- value: true
- mirror: always
- #endif // defined(ENABLE_WASM_SIMD)
diff --git a/srcpkgs/firefox-esr/patches/skia-sucks3.patch b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
index 908311cdb6db..4bf77e684405 100644
--- a/srcpkgs/firefox-esr/patches/skia-sucks3.patch
+++ b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
@@ -30,27 +30,3 @@ diff -r 46ea866ca3ac -r 6ef20eee3f8f gfx/2d/DrawTargetSkia.cpp
mCanvas->saveLayer(saveRec);
SetPermitSubpixelAA(aOpaque);
---- a/gfx/layers/composite/CompositableHost.cpp
-+++ b/gfx/layers/composite/CompositableHost.cpp
-@@ -13,6 +13,7 @@
- #include "ImageHost.h" // for ImageHostBuffered, etc
- #include "Layers.h"
- #include "TiledContentHost.h" // for TiledContentHost
-+#include "mozilla/EndianUtils.h"
- #include "mozilla/gfx/gfxVars.h"
- #include "mozilla/layers/LayersSurfaces.h" // for SurfaceDescriptor
- #include "mozilla/layers/TextureHost.h" // for TextureHost, etc
-@@ -92,9 +93,13 @@ bool CompositableHost::AddMaskEffect(EffectChain& aEffects,
- }
- MOZ_ASSERT(source);
-
-+ // Setting an alpha-mask here breaks the URL-bar on big endian (s390x)
-+ // if the typed URL is too long for the textbox (automatic scrolling needed)
-+#if MOZ_LITTLE_ENDIAN()
- RefPtr<EffectMask> effect =
- new EffectMask(source, source->GetSize(), aTransform);
- aEffects.mSecondaryEffects[EffectTypes::MASK] = effect;
-+#endif
- return true;
- }
-
diff --git a/srcpkgs/firefox-esr/patches/sndio.patch b/srcpkgs/firefox-esr/patches/sndio.patch
deleted file mode 100644
index 68628bea8d8f..000000000000
--- a/srcpkgs/firefox-esr/patches/sndio.patch
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/old-configure.in
-+++ b/old-configure.in
-@@ -2818,6 +2818,22 @@
- _NON_GLOBAL_ACDEFINES="$_NON_GLOBAL_ACDEFINES NECKO_COOKIES"
- fi
-
-+dnl ==================================
-+dnl = Check sndio availability
-+dnl ==================================
-+
-+MOZ_ARG_ENABLE_BOOL(sndio,
-+[ --enable-sndio Enable sndio support],
-+ MOZ_SNDIO=1,
-+ MOZ_SNDIO=)
-+
-+if test -n "$MOZ_SNDIO"; then
-+ MOZ_SNDIO_LIBS="-lsndio"
-+ AC_SUBST_LIST(MOZ_SNDIO_LIBS)
-+fi
-+
-+AC_SUBST(MOZ_SNDIO)
-+
- dnl ========================================================
- dnl =
- dnl = Maintainer debug option (no --enable equivalent)
---- a/media/libcubeb/src/moz.build
-+++ b/media/libcubeb/src/moz.build
-@@ -44,11 +44,13 @@
- ]
- DEFINES['USE_JACK'] = True
-
--if CONFIG['OS_ARCH'] == 'OpenBSD':
-+if CONFIG['MOZ_SNDIO']:
- SOURCES += [
- 'cubeb_sndio.c',
- ]
- DEFINES['USE_SNDIO'] = True
-+
-+if CONFIG['OS_ARCH'] == 'OpenBSD':
- DEFINES['DISABLE_LIBSNDIO_DLOPEN'] = True
-
- if CONFIG['OS_TARGET'] == 'Darwin':
---- a/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-+++ b/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-@@ -88,6 +88,7 @@
- @old_configure_options(
- "--cache-file",
- "--datadir",
-+ "--enable-sndio",
- "--enable-crashreporter",
- "--enable-dbus",
- "--enable-debug-js-modules",
diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template
index 58c065649bc4..7911f1e9e2bd 100644
--- a/srcpkgs/firefox-esr/template
+++ b/srcpkgs/firefox-esr/template
@@ -3,7 +3,7 @@
# THIS PKG MUST BE SYNCHRONIZED WITH "srcpkgs/firefox-esr-i18n".
#
pkgname=firefox-esr
-version=91.10.0
+version=102.2.0
revision=1
wrksrc="firefox-${version}"
build_helper="rust"
@@ -11,10 +11,8 @@ short_desc="Mozilla Firefox web browser - Extended Support Release"
maintainer="Orphaned <orphan@voidlinux.org>"
license="MPL-2.0, GPL-2.0-or-later, LGPL-2.1-or-later"
homepage="https://www.mozilla.org/firefox/"
-distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz
- https://github.com/chmeeedalf/gecko-dev/files/7729086/esrppcjit.tar.gz"
-checksum="825a8cb38bb5da9821ef87cc6de64af007cf0faef07c4ed0651283b56a0ee1bb
- 5e926a8be5d6d4949c3bc3eb98e2103692eaa26a98928db432b1d44b535f7241"
+distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz"
+checksum="014d91d14ab4f53e93728273b45ac6022813d5ade35f842e722bf87b747c97ff"
lib32disabled=yes
@@ -63,9 +61,6 @@ post_extract() {
;;
esac
- # ppc64le jit, see --enable-jit later
- mv ../js/src/jit/ppc64 js/src/jit
-
# Mozilla API keys (see https://location.services.mozilla.com/api)
# Note: This is for Void Linux use ONLY.
echo -n "cd894504-7a2a-4263-abff-ff73ee89ffca" > mozilla-api-key
@@ -78,24 +73,24 @@ post_patch() {
do_build() {
cp "${FILESDIR}/mozconfig" "${wrksrc}/.mozconfig"
+ echo "MOZ_APP_REMOTINGNAME=Firefox" >>.mozconfig
+
case "$XBPS_TARGET_MACHINE" in
*-musl)
echo "ac_add_options --disable-jemalloc" >>.mozconfig
- echo "ac_add_options --disable-gold" >>.mozconfig
+ echo "ac_add_options --enable-linker=bfd" >>.mozconfig
;;
esac
case "$XBPS_TARGET_MACHINE" in
- x86_64*|i686*|arm*)
+ x86_64*|i686*|arm*|aarch64*)
echo "ac_add_options --disable-elf-hack" >>.mozconfig
;;
esac
# webrtc currently fails to build on 32-bit ppc...
- # also enable jit on ppc64le, which is patched in earlier
- # https://www.talospace.com/2021/12/91esr-with-baseline-compilerbaseline.html
+ # TODO: also enable jit on ppc64le
case "$XBPS_TARGET_MACHINE" in
- ppc64le*) echo "ac_add_options --enable-jit" >>.mozconfig ;;
ppc64*) echo "ac_add_options --disable-jit" >>.mozconfig ;;
ppc*)
echo "ac_add_options --disable-jit" >>.mozconfig
@@ -132,6 +127,10 @@ do_build() {
echo "ac_add_options --host=$XBPS_TRIPLET" >>.mozconfig
fi
+ # XXX: wasi currently not ready
+ # echo "ac_add_options --with-wasi-sysroot=/usr/share/wasi-sysroot" >>.mozconfig
+ echo "ac_add_options --without-wasm-sandboxed-libraries" >>.mozconfig
+
mkdir -p third_party/rust/libloading/.deps
case "$XBPS_TARGET_MACHINE" in
@@ -165,7 +164,7 @@ do_build() {
export MOZ_MAKE_FLAGS="${makejobs}"
export MOZ_NOSPAM=1
export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
export AS=$CC
@@ -184,7 +183,8 @@ ac_add_options --enable-default-toolkit=$(vopt_if wayland 'cairo-gtk3-wayland' '
./mach build
}
do_install() {
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
+ export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
DESTDIR="$DESTDIR" ./mach install
vinstall ${FILESDIR}/vendor.js 644 usr/lib/firefox/browser/defaults/preferences
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (8 preceding siblings ...)
2022-09-08 11:21 ` [PR PATCH] [Updated] firefox-esr: update to 102.2.0 oreo639
@ 2022-09-08 16:09 ` classabbyamp
2022-09-08 21:36 ` oreo639
` (3 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: classabbyamp @ 2022-09-08 16:09 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 261 bytes --]
New comment by classabbyamp on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1240926012
Comment:
btw, can we try removing `python` from hostmakedepends? It was removable for thunderbird so probably fine here too
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (9 preceding siblings ...)
2022-09-08 16:09 ` classabbyamp
@ 2022-09-08 21:36 ` oreo639
2022-09-08 21:36 ` [PR PATCH] [Updated] " oreo639
` (2 subsequent siblings)
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 21:36 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 455 bytes --]
New comment by oreo639 on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1241258621
Comment:
> btw, can we try removing `python` from hostmakedepends? It was removable for thunderbird so probably fine here too
Builds fine. Afaict from the fedora template, python2 is only needed for the tests unless I am misunderstanding.
cc: @Duncaen (the main ff package also still has python2 in its hostmakedeps)
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PR PATCH] [Updated] firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (10 preceding siblings ...)
2022-09-08 21:36 ` oreo639
@ 2022-09-08 21:36 ` oreo639
2022-10-05 17:25 ` [PR PATCH] [Closed]: " oreo639
2022-10-05 17:25 ` oreo639
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-09-08 21:36 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1351 bytes --]
There is an updated pull request by oreo639 against master on the void-packages repository
https://github.com/oreo639/void-packages ffesr
https://github.com/void-linux/void-packages/pull/38817
firefox-esr: update to 102.2.0.
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with gcc 12 and fixes build with the current cbindgen in the repos.
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#### New package
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#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
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-->
A patch file from https://github.com/void-linux/void-packages/pull/38817.patch is attached
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: github-pr-ffesr-38817.patch --]
[-- Type: text/x-diff, Size: 247437 bytes --]
From 34dfc955a82ad8561056dca8dce83b8e8b046b2d Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:12:06 -0700
Subject: [PATCH 1/2] firefox-esr-i18n: update to 102.2.0.
---
srcpkgs/firefox-esr-i18n/template | 188 +++++++++++++++---------------
1 file changed, 94 insertions(+), 94 deletions(-)
diff --git a/srcpkgs/firefox-esr-i18n/template b/srcpkgs/firefox-esr-i18n/template
index 765303a93236..f518c78f2539 100644
--- a/srcpkgs/firefox-esr-i18n/template
+++ b/srcpkgs/firefox-esr-i18n/template
@@ -1,6 +1,6 @@
# Template file for 'firefox-esr-i18n'
pkgname=firefox-esr-i18n
-version=91.10.0
+version=102.2.0
revision=1
build_style=meta
short_desc="Firefox ESR language packs"
@@ -135,96 +135,96 @@ _pkgtmpl() {
}
}
-checksum="6b47684de4218749d90a07b858ca298b034a2cda10655941e8ba47891d0d95ed
- 54852ef937387cba360fb2bed348c9bc3f1153f7242ad5491ca0b85ee6ed7455
- de66e0263dd0a2d87554fa1d9a406dee5cb3df1a774dffb8636e1be2bd80bc14
- 1f4824ad51a662285ac3a0d8029462a3bf12b36eb0834e65b9276e0869115c09
- a16fc6e0a1bf251ab19b7bbfb620b53437e5bf71b0e7871ed40ace8c97dbf635
- d9057bc71605f2a93d924beb37497195b8ad83501aa4d211ad71106e7b9bce4a
- 36316a7c4ca844ac3e81b2a0bb9ee4952017c2d2404f529848e280d04a21589b
- 150bafd02393355567d75bb9f966900e70502fdddff2822cbbd3bbc1fb3fd785
- 5b69e761666b28e5604d4cf8abc72acf3c3d79abeb7b6230e56aaae775ec225b
- b005c63d5e0d933ef1a4193b75a291a61524a939c3465d41ed111416210eb97f
- d5a2d2fafbfc50e23f5b68d30fcd7376d127f9f697c872d0d7c8e19ee4538cb1
- 16f88ec5de39f982057abcf34f17b22c698453debb62a5a18e0475798fc1cca9
- 84d491f73bc53da4605ee45a8633f14ee5672b9a61c40689d5e3289744a7cb2d
- 7781b6c29923360fd3a95bd2b2532eba7f92bed29640e0276c161eadbe56a13f
- 7984904ede35def33ccf73fda9aa46777c673c4d27de3806873d17694f7f0b13
- 4c57b6eb1cd968ba1eb4b427bed66bab04fb42424d03ae4b892fd3648e255b2e
- a80e9e2a6062bf68106ba1d1b8b7e2ff608ce52fa55d43558e7c073ec1872516
- 2b040ff1d010508760cb4ce4b76cce9e98b4620203c1ef77f87a336ced0aefc7
- 1fa4f5e59a9352f14aefe0cff8e8c4eed4eba16f4d8dbcec6850bce035301c18
- 2da0b09b9bf80f66edc6e3e9d5c1b75fae12905b5193cc64a73bb8bd7bfcbb04
- dce96c9fccb8c857f8cc370f7f5635b1475138195b05e944782b072beebc8d44
- e90dbf86c1823c209def11052995834ed15528dc5c6d3b502ed315dd471a9d5b
- f38624c81f2f9dac4f05b9e9d4d6e7a4e0381a279e3b4c53811aeb1db13cd000
- 221b7f4031a7c120d0ca753d93c41c18ac4f9500ae424c7983e4593497ddbbf8
- 60f5ceb21287a6786a6dd2d177325dfbcc6ca7f9a5df1b9299a2c5bb01d9c172
- 308ce25a9a0a9038dd94c2c22889c54def3937d35eafbcb34b75026cf3de3b8f
- 2d332a6f5bd92017700a15da5fe506612cea03b49f903592fc105fca978cd1d3
- 5cd35666f54a5ae4e35a1ca4c627cec8a47594da4083adf4f06dbe31c20a7444
- 1c1252765cb24f6a0206b648d834566aca9229075f7413f9c7deff1949a99c37
- 002772c46d6a7162e2add4726f105e4c0e355bbb84ce91b07ab02967cc5f1eb4
- 64ce2c0735caf9b67d2be003b1d667bce5ff614653151c617e4d26e349033e3a
- 60bd5f2532700ae9139d4d59a571b72b2806e80630fddb5f4444c7d6e377d2dc
- 2753317b7580ee1a377275905e254084263d0a87bda1bb572537fa75489d92dc
- 7f1b74d2cc5a9c4c6c7864a62eadef2b3d72c5cc2010f5c03bce3a9fae2286dc
- 2232c3b9a8f313145967152bf1dbafd6233593ceb422d2c3277d1b4cfecb6f50
- c41e866f3fc3cf0e0088681b55bb8489de1c5840ca7dc52d1f4f077b53452bd5
- 5d787fd6a9aa06ce31a6823b3393ba7ad66cf3d374dd6eaab3648103e826a10b
- 8d73e01655af7117856374be3669d530af96a79cdb8238bc953688d45e94567c
- 03f2b133746746c328cb7e4055b568d8e99cea51c845136c3f4446840d68e32f
- 691b0e760ebe5269dfa4aa4ea8dd2139260fbb0ca38af4c5438548b7c7ee88f5
- c63492236e75bf984a1671de95dddc954c1b4a1e92f5201c9b333faefae93035
- df9a036c67aecb1ea65f9709a11f6ccdf253451dcbe6b267437c51f422b9df2d
- 32ec78a51439b02f087c12c6be4a9159826113e83774085e800c37b6d7c112aa
- 1e44e3ded5aa07d44f3fdea8cf68bb33fd243cda159384ea8b87e783ed5c9a65
- 1cac44cdec68b56b77aba139a8425f607bac34ae2e09e27ecff2522b16fef44d
- aefb4fbacbdfc749a8d5888f7af48999406f207850fafae8ef39c083e08fa80c
- 753dbcffdf54ce3787a939517b059f11c305edc035bc22f8a9efed6145af6391
- 6c3be5abaf3878390b074970132c4cba935f7160f365cfa98a07e6b882084bdd
- 0b7771965f34c890dea0d2290a283212a1cdc0c8c8044ec634622d52eb595df9
- 0910f98a89b712a40aeb42761f25c763818af05edb5c96e2b6cfba023c28ab73
- 758ab6ea150702ee0d6203a0f75e8baa595c4a0f3d4cb9b87076f732a0e4546f
- d4259375f321b98426885e0b903199dce1f988c74963297bbd1a2aa8f94b0544
- 1614e1288f6d6ce43a7343586141df5e121cff7f1fd703ab4ec40a7f07498843
- 3ae5219a384a872fdbdd8ca5d99ad5370e0d8d87d93f5e39e96c5a2dc26736e3
- 05807b1c17849ffd2a3a63b1e26815dc9463aa3c137f640113530d2662d64116
- e4f3cfb11dfac8ec4caf29f34e20a0c0bb799649fd5b534f22f202c237491f7f
- 80b2b6446590a9fc55ed80a9e07b657cafc5d50294988974747c0e60d41f569b
- 1b32bc1282ded7f6f0f0979cbce3496ed07b1fcad64e70bbbc2eb5d2a8f3953b
- 0f80e3b0a9e17f39560b7cad8280e25c0278935f125d8e724a2381102abff783
- f259ee2683e525051d6f314d4bae4a98c0482a2a443aaac1160b2e0c1326b931
- b9a9eab4c5ea110ccbce20cb88e6652e2cf4c28bfd0aa95907148befd198544d
- a5a6e9bdaad420f281ce5fd16dabf5338d48c7cd8518c38b1e101b79b530fdb9
- a1fe6a2c7606b0720933496cad2bc959693905db87c3a2e5313db82dbfebda7c
- d1b22a495c637d5652c84afe8650d876b4206f2ea0d96751bec684ea63327f98
- e1587dac082479821697d97b4d5cb63a8d1f9189fdc2048885d963aea95b8400
- 6e40a5d5f0cb8794edc5f6a1fae778d89f6dbd97d8a288236d72fa571ffe91c9
- 33b5df625ae13ec35b41bb350e9e66d9ccc04f4d4d8c7e45020344739881e6d8
- e2f271691bb1b9873583175ff303bbaaf05a9d1207fbe8fffc34ec4abcfc1545
- 13382dabc604e99553c98b9e41eb046d4688b15f2ee9dd12c4f9c8967afa62d1
- 77133c69968073fec909dbe9e44d2eaea002cb0d0e142125865d1c03c89ed73d
- f8998128b0c656e72124baeff45c72013953f8314aa4959b6fef8a1b3039647f
- 2f24e5db025c0302fe3b696f280dcbab83728aaccaefe1ff082e165276896296
- d658095fd2d3e4d3decb8c2cdaa64f02fd8b663ba711fb9f2130ed7ed2a97291
- 7c28a82ecdd622653b26a9dd0913ac7d7cebe7246f64874fea2d1fa4af354c2a
- f78694d438032af3ca1a265a089407eb12b431bd314177672a66338b9bf7390f
- ea2d769b90a06400eba3e1f4eec58342fe4450ecce38b1e721923a65bed34337
- 8edf5b04b6cb477f482c14efdbada7023ff7a0ef584a4c30b2350e7825a612a0
- 851db60a218c36b61ee0adfcdc478bc051c95e41a4dba54d43594b8f03c6b187
- 6af72cae7f72ce68c644d49b6a621945f5e8f79119a86bb67ee144585f734925
- 7b01771078ec475b0103fcc4222b0b40eb92ec64180aaad02f2846cfdfb3e319
- 0c4df78eafbbe7ff98d9eff03bb258d1d0f4591102147f643ec395711f35d940
- cf21434f24e221ce58184f43a582c10187eceb7a71da5d81156cc870d78c1f4c
- 839088e2f23f6c62c38c45d5f7012513d95034aa5e6ab28307f152dbc10f97d3
- 4058ae6dd7b556bae2c13bb6fa0c5f16207c6fef4e0802d3d0badae2108a0da8
- d2c473fb93f0c4dc67ae18c25fdc414056bf779038c0f5dd25aa63a9a5cfcd0a
- 6e31c79b9955fd879528b0a614295da69ab26b608275946a4a5a29178a2aed20
- 852fe9ab16d29f7cf8f443bfd65fa1d522a9f27ef8766ad72a0c22a65450dc18
- 9411873b1ea01a1b8656957aedb79137f4c189b9cd3e96626c8e503539cf2c4b
- 5f43106472ae66dc8c0ffc317faba09c2370d4f18837c3cfaf05eb9b03f33b90
- 30f3f50133532ce379b9d5dd0f7e81204905e8a43a27e9d2ac1a26059e393913
- 285f615cc8852fd74bd7693a5a45b106f293c0a2d89836e9f25336ac6376af69
- 190ac7991a8b501fab2654d23b5f6f1e7a5f0cfeb402c8f5fe382d25c2222dc6
- 2de7676c71508ffbb337bdd8ca68f9d2fa1e30f23e8be283b937c5c4e30c59d6"
+checksum="d5a1473ebe95cd18f90ed0d9cf305ee6559a4f224f07cc59f1c5e1de30c65a87
+ c51c457d98da7bb1145456b57826bddb130cbe2a02bd1f9609eede50c5fc47ad
+ c11c1457d9654943003ccbf5669e1b7f78a392719ef1c1179213f517702cc2fd
+ 47f2aaa9ec19525f8877d31fd3dac68347e0ca11b98faacc9fc2cf6ffc09bbd9
+ 221b8508b66ad184a61e11c6278aee0bee6492e4b7bf74cb2daade4f406797f0
+ 5e56b37fa673f72fd7f1e88871337e3faaff871e6b00e31b44aa6ebf1db607a4
+ 93a8c6971f3d313b88954260b5247e666829adc522c6e226cdd7432288728080
+ 6960c4d2f487d57a8163e083f9eba0da20515d9e12942cb3c449948fa2d1bbff
+ dee27babb195f5bf7afdd8571ee6246259555808840d0a29f9dacacc0b6ca5b6
+ 3079b3bbb9c50f6acf5bb4f91846dafdda432a7b26723f170701889dba313820
+ 216171a907c45bd26a78fe071e1eb1666a3e7694888003e507b259bf7a2229c4
+ 47cc7b638478cad28b4e5e027e8f10f309a54abc6b0f4317e878b1376d6a282b
+ a1bfd2f5ef6dfc0d7e19699ebad6af11b6d1e6ed6ce8a0c6176f0f294d136aeb
+ 399c223f82b97e5773df35613d094f0ed73d4a2b99f2fb65936eb5aa8ec3e51a
+ d164ba3d47d79e7bc171d235053c5e51ebb71b199edd389d262fe0ddd991f014
+ 48dffaf3638e4d8c0897a07b105036fcc2ac4e132b999d726d83725c58fb0381
+ 48bf4e31f4abd7a456042566ce772c335f5627618e52614cf8426efb503802c4
+ f4c620403e732346fa66d6dd38d54252d96d924a9c6c1a0da0c077440a4c70ef
+ 4db7491052e565fbe07aa8a37166920fe7b049cef4b7f2774c0b593ff805c0aa
+ ba7f6cca8d7ede6c4562adf9cc3e2896efe08fab6e11ca964c2297e5b01eb6ae
+ b93c9812733e2bf504e77519485c345791836b30958285fdf57c364f1673fcd0
+ 8079d1c5d7e23955e845bc17bc4fbfe2a3456e7ba1a7bd01ff01664d827438e2
+ a53f01d68fca8b58de937256fb962e3b978f5ffd00d2d11b6f2028a529c1f9c9
+ 417ad3babd8e62a74e65dda70d9fd47e4be900e1ea8aba1c960a9736c3ef66a5
+ 6de44c4367e370370cec480e2c3979ccdbb03f32de42bf0e15b7d5336092f2cb
+ 9d12f575e0fe8909d8792f9a4cd66d71435a79e9463a0d1f1f7142b92e0347dd
+ 08fb7caa2676ddf16e81514e660870214db39ae965ebfd9c0a24e055190c1a30
+ dc189ba71869a2052b63d08cfc2ad39fc34f3a035ff5a9910d1d07dd9ffde149
+ 1295ebf8671f823704070d4ff4f7b3eb956c419348ddb4cca1f8a33ade8caece
+ 2277c0000d1237b9159c4cdcf7f2aade52d09e4b3d04d505445dd86861359176
+ 1acc3a9c996bd331d1eefb534da41eb84cbd7a39755f277814bd7ca9609d240d
+ 5d8b9cd48a9ffd104939f4b4cd5c5c5146bcf56067280bd8e49715e95e42d53c
+ 8932a8157b092f196493f62633c3291a9575f722b810f0f9c793bc7690883866
+ fa1312afe79f2ee7f2470b3b101eac6f8689ee494e6d0a9ecc96efa455a09aeb
+ 1802755f0fc08510a0a614b5a32086b942c4ce6d8a90c6145ce6ac0c66fe07e0
+ caf2b000fd9a03732378332dc6599e628a85e44c6f4f982b483f4827fde7a5fe
+ 60c2be815d5994fcfe5133bee2ca79730f7a29fe5238f7300ef49fc941b79062
+ 7ca5bba5f47bf2da6def8d29f832333c09e7ff6c271521916c4ea42dfb6b37da
+ 7bf29d75d905fd8f0b9700de433448dbefb304c8dd181a6560d1ede433040800
+ 591d8c31cab9e3009753d2eb4bf41098a02c5b11b763a633adcb49afaf41ccd0
+ 8cec17c0174a3c9eeb512dd9c88cdf4fb2dc6b68a6e38466f4edb499af524a33
+ 36055161e5df1cde24351eb35269c0aac68c8b279116cc984cc93c9b01e196f9
+ 9533f3f7c4dec42e36fe3dcf31a7f00ac1bdda64e4ea47c0a563c4b33d6b9606
+ 80e176922404452a5f0871d493fa0e8bf7b2a2fdb317e3cd017595ffde131793
+ 4ddfc3938943c8e2d1f2b38f04566c264f1f7b6faf38456a8973937eec4f770b
+ 1c257033946f3316d1a6ad3a700b124f9f36f0ace5f9d1fec50c391ab7fd3721
+ 6d7d300c1ce9928669a3b837479e9aa8c7ef4cef113839f6e17684c58153fbc0
+ 00ea98387fc098f4fb5a7cd3e42aac5a9ce62c77805d371c489cff5ba4393d2d
+ 8f4c302dda19be2ce6704b205243c7e27e77129992bc78db330855e4aebb56a9
+ 42a0495577b5874363faf0117ef406bdee63f8274f3475f8746ec50ef601f895
+ 48c853fcb62a8fb9743fea55b3db579917130acaf0749e1e61245941e80cab62
+ 2c9cf98785c43fa49df30c7d5253c7abf90dd856ec19529a6f76bd2e19f818fc
+ e38cffcc6802078e04324846fffddbfb33c66ebcca7179a26beacfa52262681d
+ 9267b8a3a4231f45e50e9f0f3eb803e1210eae7168f57e6bb668fda47a3914b1
+ d3828f3fc4e8f198a4d05e59952f5dc2790dc0b9472a2cfc1b70d668d8af75ee
+ eb20c6ef5ed9e58d17d55f978ae9b31273ba909aee23ab88726afa0569f047c2
+ 2c8c417e039579f7a5191a9ac763cd37101b6ffa0ef34ab9e4241454304a6b99
+ eb49f9396fffabf2824b008894a1f88d5304220bba420418c48c03e50570d381
+ 6c06668712b03657604d55720a876cf63ebc0809a776578f0d2567cb284aae3f
+ 9e81cb09e69da35f9d3a2c5692f747c77963e7a79ff18bfea06abaed69c7b40f
+ f229adf1ab6a2ca65b90899bf825b50a95637b1013fd13c46baf16b2927e0ca5
+ fb29d32429f5fcfe4081f539f00132b850d8231ba8caae84ee74cccf32f8f8e6
+ 48cb704832c25635a4c02877b8dcf26216f519f68b878daa83e3580dd5fd77ee
+ e284ff3a5dab91f30cfeafd3f8aa5d1bd39aa56e8e99fdd86e34928f3414e531
+ 074969a45f46475100ae4956020ef71ad749ad3c02c9a8a6270a4a7ff915fe5c
+ 74825698f655180440e8c28eb317090555fd326eb19cca3c3369297cc2db193c
+ 3bdc7711751357f5211ade94f5c4ed1422811ad41f8d751c0e96c619d787d3c6
+ 578bb94490bef477b1c2f3fe1e47e1b57cf5bfaab937cad40859164141e1ca01
+ 5650824ee3e48839bd6429fefc744d1cda0123e0a2f1414042e5ad40f040fd71
+ fc41f0e9c8f1225666b1d6ceb7d30a21d80f39d89cbed65443afdf976840e3ce
+ 855e130f9b3b4a22d253df8b11bf20cd4528c67dc049b414667505e4eec5b3f9
+ 4cb1f99c98d078774ad389a086f1fec3957033be8ddfea80d57ccc2b2fcd912b
+ 618da6ad432aad58c2a2b8fa3fd2eabf46b9be1bf6db06b5b892adf76d616afb
+ 75f8701df6519a294d17799fe3ecb9d02177af56b0274269eddc6f4f1809bd11
+ 4f68f7af30eacf130c43a5ec14f1ca573eeb0fcb1c9242fc28e1b5ccf4274eaf
+ a6b37e3056a7845ddd49de9f0ef332bc5749477da6fee788f17e1db88c349b4f
+ 9e7418e4ba553811c54a3a04cb85c680016285291a1671abff0e81017af1d749
+ 090ea71643b074ddb6717531095e2c3cf7a2a4eaab2d729d0d3bfc28058bad8a
+ eaba5ef15835c68ec07580b8523819ba07e03ae3af25ac5c10193e3179c73bf4
+ 803e2969f15a3d738f65cbbf9d3054a039f9381327f9007e8590754f7419e70c
+ 4ab75978d8ec20846503002d3bbc959b12717695898fba5d53b1a80f5cd7a820
+ 2c15fac71576bad1e80838ee0969572bf2c15bf729356d23ae54515e16901e52
+ 145f1e77d894d1fc120bdcd6582a72f971909789506d9ae5b1997c57d27d50c6
+ 0e9b73e34ce7ca39253d1e0ded022c05654841aa61c34c284906492d4bbe27da
+ 337dab583aa1d3d524b9241ce5e94b7fe54c41dc86f0ea5c8c6b021fa3b66c66
+ 58b361eeac66c68cb3728b68afebe0648559ac6552d8cfaed3cb35a952c9fb2b
+ d8531ee94abe01ea46641f1e7eb13fffa8d81228c14ca074990e7ea4c10dcd53
+ 407ea5363696ef77fc0cffa7f5c27e78025f69248d82ac85f82452a7f5466502
+ 9e5be4dd61ec9ab0b3fad41ddf28a4cc16a97e6450ace4f112c0b843f143acbb
+ 582126ed73f312529608a44fe46935d10957cd5d46fefa7ca33b93e2a4283d84
+ 2a36bbcdc59adbf948bd5ae3176739cd5dee91f661546fffe4041a294152d4cf
+ 5e32e063c559910c5bf49bf835c47d69584a6b552a3b031433ca880618834ab9
+ 60a96f115e5cdca96e333d83955ad3e24860c61f212ada5954ef62072a9a9d85"
From 32e0f3a4afd66f70f87bd49f16b7a1dedcf99a17 Mon Sep 17 00:00:00 2001
From: oreo639 <oreo6391@gmail.com>
Date: Thu, 8 Sep 2022 02:13:13 -0700
Subject: [PATCH 2/2] firefox-esr: update to 102.2.0.
---
.../patches/fix-build-rust-simd2.patch | 729 ++++
.../firefox-esr/patches/fix-cbindgen.patch | 22 +
...n-path.patch => fix-firefox-desktop.patch} | 11 +-
srcpkgs/firefox-esr/patches/fix-tools.patch | 13 -
.../patches/fix-webrtc-glibcisms.patch | 24 +-
srcpkgs/firefox-esr/patches/ppc64le-jit.patch | 3441 -----------------
srcpkgs/firefox-esr/patches/skia-sucks3.patch | 24 -
srcpkgs/firefox-esr/patches/sndio.patch | 52 -
srcpkgs/firefox-esr/template | 32 +-
9 files changed, 787 insertions(+), 3561 deletions(-)
create mode 100644 srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
create mode 100644 srcpkgs/firefox-esr/patches/fix-cbindgen.patch
rename srcpkgs/firefox-esr/patches/{fix-desktop-icon-path.patch => fix-firefox-desktop.patch} (64%)
delete mode 100644 srcpkgs/firefox-esr/patches/fix-tools.patch
delete mode 100644 srcpkgs/firefox-esr/patches/ppc64le-jit.patch
delete mode 100644 srcpkgs/firefox-esr/patches/sndio.patch
diff --git a/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
new file mode 100644
index 000000000000..e20e6bf6026d
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-build-rust-simd2.patch
@@ -0,0 +1,729 @@
+From ada04eb9b82531a41553b6ffc2ba3194c70fdc45 Mon Sep 17 00:00:00 2001
+From: Mike Hommey <mh+mozilla@glandium.org>
+Date: Wed, 24 Aug 2022 06:58:59 +0000
+Subject: [PATCH] Bug 1783784 - Update packed_simd_2 to 0.3.8.
+
+Differential Revision: https://phabricator.services.mozilla.com/D154063
+---
+ .cargo/config.in | 2 +-
+ Cargo.lock | 5 +-
+ Cargo.toml | 2 +-
+ .../rust/packed_simd_2/.cargo-checksum.json | 2 +-
+ third_party/rust/packed_simd_2/Cargo.toml | 5 +-
+ third_party/rust/packed_simd_2/README.md | 2 +-
+ third_party/rust/packed_simd_2/build.rs | 5 +
+ third_party/rust/packed_simd_2/src/api.rs | 4 +-
+ third_party/rust/packed_simd_2/src/codegen.rs | 50 +++++-----
+ .../packed_simd_2/src/codegen/bit_manip.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/llvm.rs | 98 +++++++++----------
+ .../rust/packed_simd_2/src/codegen/math.rs | 2 +-
+ .../packed_simd_2/src/codegen/math/float.rs | 28 +++---
+ .../src/codegen/math/float/abs.rs | 2 +-
+ .../src/codegen/math/float/cos.rs | 2 +-
+ .../src/codegen/math/float/cos_pi.rs | 2 +-
+ .../src/codegen/math/float/exp.rs | 2 +-
+ .../src/codegen/math/float/ln.rs | 2 +-
+ .../src/codegen/math/float/mul_add.rs | 2 +-
+ .../src/codegen/math/float/mul_adde.rs | 2 +-
+ .../src/codegen/math/float/powf.rs | 2 +-
+ .../src/codegen/math/float/sin.rs | 2 +-
+ .../src/codegen/math/float/sin_cos_pi.rs | 2 +-
+ .../src/codegen/math/float/sin_pi.rs | 2 +-
+ .../src/codegen/math/float/sqrt.rs | 2 +-
+ .../src/codegen/math/float/sqrte.rs | 2 +-
+ .../src/codegen/pointer_sized_int.rs | 24 ++---
+ .../packed_simd_2/src/codegen/reductions.rs | 2 +-
+ .../src/codegen/reductions/mask.rs | 4 +-
+ .../packed_simd_2/src/codegen/swap_bytes.rs | 4 +-
+ .../rust/packed_simd_2/src/codegen/vPtr.rs | 2 +-
+ third_party/rust/packed_simd_2/src/lib.rs | 7 +-
+ third_party/rust/packed_simd_2/src/testing.rs | 2 +-
+ 33 files changed, 144 insertions(+), 136 deletions(-)
+
+diff --git a/.cargo/config.in b/.cargo/config.in
+index a6e396b29f764..2e5bad6fed2c6 100644
+--- a/.cargo/config.in
++++ b/.cargo/config.in
+@@ -70,7 +70,7 @@ rev = "746743227485a83123784df0c53227ab466612ed"
+ [source."https://github.com/hsivonen/packed_simd"]
+ git = "https://github.com/hsivonen/packed_simd"
+ replace-with = "vendored-sources"
+-rev = "c149d0a519bf878567c7630096737669ec2ff15f"
++rev = "f38664024b29d44c506431eada7c112629bb1aa9"
+
+ [source."https://github.com/hsivonen/chardetng_c"]
+ git = "https://github.com/hsivonen/chardetng_c"
+diff --git a/Cargo.lock b/Cargo.lock
+index 0560a3c86be85..ebec60085c0c0 100644
+--- a/Cargo.lock
++++ b/Cargo.lock
+@@ -3812,10 +3812,11 @@ dependencies = [
+
+ [[package]]
+ name = "packed_simd_2"
+-version = "0.3.7"
+-source = "git+https://github.com/hsivonen/packed_simd?rev=c149d0a519bf878567c7630096737669ec2ff15f#c149d0a519bf878567c7630096737669ec2ff15f"
++version = "0.3.8"
++source = "git+https://github.com/hsivonen/packed_simd?rev=f38664024b29d44c506431eada7c112629bb1aa9#f38664024b29d44c506431eada7c112629bb1aa9"
+ dependencies = [
+ "cfg-if 1.0.0",
++ "rustc_version",
+ ]
+
+ [[package]]
+diff --git a/Cargo.toml b/Cargo.toml
+index de7ee7ac7cc1f..f576534bf3f8b 100644
+--- a/Cargo.toml
++++ b/Cargo.toml
+@@ -113,7 +113,7 @@ chardetng_c = { git = "https://github.com/hsivonen/chardetng_c", rev="ed8a4c6f90
+ coremidi = { git = "https://github.com/chris-zen/coremidi.git", rev="fc68464b5445caf111e41f643a2e69ccce0b4f83" }
+ fog = { path = "toolkit/components/glean/api" }
+ libudev-sys = { path = "dom/webauthn/libudev-sys" }
+-packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="c149d0a519bf878567c7630096737669ec2ff15f" }
++packed_simd = { package = "packed_simd_2", git = "https://github.com/hsivonen/packed_simd", rev="f38664024b29d44c506431eada7c112629bb1aa9" }
+ midir = { git = "https://github.com/mozilla/midir.git", rev = "4c11f0ffb5d6a10de4aff40a7b81218b33b94e6f" }
+ minidump_writer_linux = { git = "https://github.com/rust-minidump/minidump-writer.git", rev = "75ada456c92a429704691a85e1cb42fef8cafc0d" }
+
+diff --git a/third_party/rust/packed_simd_2/.cargo-checksum.json b/third_party/rust/packed_simd_2/.cargo-checksum.json
+index 3090b655a160c..079b4c559f5ee 100644
+--- a/third_party/rust/packed_simd_2/.cargo-checksum.json
++++ b/third_party/rust/packed_simd_2/.cargo-checksum.json
+@@ -1 +1 @@
+-{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"f85e54e13a05f6e4f27c230ab81430af27b6ff80a1c036bd70c42ea115f89487","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"882f8894b333becf490d23c9024a86fd1327c8edea33aa8dbb98dc2f2ddb3956","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"019ed29c43989782d8eec3a961654cfc172d7a7898da4eca8f654700af7e1988","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"f6e92f056565e6fd93f98829a408aee9e790251e0cbd8a8bc30c8662b4d6fabb","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"a29d38fa0a85eaf787fb49989e625bf64effd5f39c126fbb2a24be206d2a3917","src/codegen/bit_manip.rs":"9991570a21ca98134b08b5c5935e2c259cea39c82d9d1529f52c561a84fec642","src/codegen/llvm.rs":"5bc6751293f9f184cf23d5df448c7d58b58b799e41c7a91f8ca41a5ba56e64ec","src/codegen/math.rs":"35f96e37a78fcf0cdb02146b7f27a45108fe06a37fc2a54d8851ce131a326178","src/codegen/math/float.rs":"dd86c0449e576c83b719700962ac017c332987fac08d91f2b7a2b1b883598170","src/codegen/math/float/abs.rs":"f56e2b4b8055ea861c1f5cbc6b6e1d8e7e5af163b62c13574ddee4e09513bfbc","src/codegen/math/float/cos.rs":"ef3b511a24d23045b310315e80348a9b7fedb576fc2de52d74290616a0abeb2a","src/codegen/math/float/cos_pi.rs":"4e7631a5d73dac21531e09ef1802d1180f8997509c2c8fa9f67f322194263a97","src/codegen/math/float/exp.rs":"61b691598c41b5622f24e4320c1bdd08701e612a516438bdddcc728fc3405c8c","src/codegen/math/float/ln.rs":"46b718b1ba8c9d99e1ad40f53d20dfde08a3063ca7bd2a9fdd6698e060da687e","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"a37bf764345d4b1714f97e83897b7cf0855fc2811704bcbc0012db91825339e1","src/codegen/math/float/mul_adde.rs":"9aa6ed39825e61edb2522e002c59c9392d7c655c01af1cf8380ba22c8ddf69cd","src/codegen/math/float/powf.rs":"642346e982bc4c39203de0864d2149c4179cd7b21cf67a2951687932b4675872","src/codegen/math/float/sin.rs":"9d68164c90cdca6a85155040cdac42e27342ebe0b925273ef1593df721af4258","src/codegen/math/float/sin_cos_pi.rs":"e0c661d1d894fd4018723b9f3143ab6771c9405e41907cb1a7b9f9b380a97523","src/codegen/math/float/sin_pi.rs":"9890347905b4d4a3c7341c3eb06406e46e60582bcf6960688bd727e5dadc6c57","src/codegen/math/float/sqrt.rs":"e3c60dcfb0c6d2fc62adabcc931b2d4040b83cab294dea36443fb4b89eb79e34","src/codegen/math/float/sqrte.rs":"f0f4ef9eb475ae41bcc7ec6a95ad744ba6b36925faa8b2c2814004396d196b63","src/codegen/pointer_sized_int.rs":"a70697169c28218b56fd2e8d5353f2e00671d1150d0c8cef77d613bdfacd84cb","src/codegen/reductions.rs":"645e2514746d01387ddd07f0aa4ffd8430cc9ab428d4fb13773ea319fa25dd95","src/codegen/reductions/mask.rs":"dd68fd8bc5335fa2d0405e59dd1e9fff16fdf7651aa8db670ca86145fd5b5dda","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"ac659780deb0c52daa9c73afb4ba8645c9fa35350cd897b23e567860492553b7","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"711c753a08d53a2879c4fb87a0762c46ce4e34c22f0ca88d2e4c557a0f679969","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"5efc09cb3d164e4e38b71fd4999afbfd234f5080dc84ce22fda2fc15d381e8c7","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"1d3a7862ef625e235a5734ad7204e68d350f902c0695182b1f08a0552432416e","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
++{"files":{".appveyor.yml":"f1ed01850e0d725f9498f52a1a63ddf40702ad6e0bf5b2d7c4c04d76e96794a3",".travis.yml":"30a61a5ec53355fc1f3585e1690280308c2b7961701abc11e8389b235b647178","Cargo.toml":"e76b42f3247fccb7174046c499bfaae5430d83cadeb8140259fcae34613483cf","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"fa4dd64f66972217d35b7653338c9e2011ccd8f3008ae7c0103272d4287f9b1d","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"a766fba121243a9b617432c592873801adb74c3a2f4a24d9d45859b8ce9357fc","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/.gitignore":"fe82c7da551079d832cf74200b0b359b4df9828cb4a0416fa7384f07a2ae6a13","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"bb1795e9657a8298d37d2349b45443f08e9e455399ad4b727018600728478c10","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"61d2794d68262a1090ae473bd30793b5f65cf732f32a6694a3af2ce5d9225616","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"db4f232fb9f5728db310b87dc8c4733be48afacab1053798c06106bef9a42b05","src/codegen/bit_manip.rs":"525ea6ff7ad1e043b6f6136992166f1803ed5563b7f6fc292c1c40257d20e264","src/codegen/llvm.rs":"b4ccbc0bad90038f00fc3c158736462d01d0053df3afa00f9169e67d1a264444","src/codegen/math.rs":"dfcf02ad34e2fdfe22c3f1cc2822001cc895e65031b4d06e585e5047839febb7","src/codegen/math/float.rs":"2c1cbce155bc527ce34d472c0fef6bc3dadb79cd7a357dd7aa5b1ebeb1d77a13","src/codegen/math/float/abs.rs":"d5aaadcf540bdb9b4264dca6471a255fd7bf509e763bef0239c0144a68466fea","src/codegen/math/float/cos.rs":"17f28d2900c852dca221fa9c92a9cd5fe7fd2df8d427bbc60216c749b2be013d","src/codegen/math/float/cos_pi.rs":"dbaf9f443f9846a491d4ec52210a7b5835dd593b03366e3135b05c37d70f9d6c","src/codegen/math/float/exp.rs":"d300058a4bcc7ae7976f216f81902cd73a9e603ad63880dff3bbc866c27a9f37","src/codegen/math/float/ln.rs":"c851e211e43f8256093ba75b03ae0c307c9962ee66d94f09b4dd80068190cbdf","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"041a5b69d5991d93ef795351b17560c10faf80b78fd26ad7df42a239b32cf9de","src/codegen/math/float/mul_adde.rs":"d71d5f0f3333b62a7439b823cb7adf5340ea1555ce820fb4a3f4cb922f73f5f5","src/codegen/math/float/powf.rs":"9742c3877f1a5509ca5c9492a40884b6579ba6dd11c26b7112e63f70666b395d","src/codegen/math/float/sin.rs":"0e9868d35531566509f3a01d85d5253045eb4afa8525d8407dcc1f5f33c56036","src/codegen/math/float/sin_cos_pi.rs":"8e6b6142d7dd240cdb36669722e82ab9810a2261e86e659f7d97a942ad8b1258","src/codegen/math/float/sin_pi.rs":"bb6d39db8f921e03a301fc5206ac1a61a97def8a2cb83b87ccf189f3fc48d548","src/codegen/math/float/sqrt.rs":"e6ebb0c5f428efad1f672b9a8fe4e58534dbf1ea5a8fe092ce5ce76b52fe89cb","src/codegen/math/float/sqrte.rs":"23acfaea38d0e081a6d9021c1094e813d0cfd12c58c1eca9662aade5e625d51c","src/codegen/pointer_sized_int.rs":"6ca13c214b6cf7e0929dbe18e96a16fc0bb7d8799608df29c4c8115490f99e01","src/codegen/reductions.rs":"8eb18ebac76985d2aa30262a2edd8cb004230b511a765d657525f677a585c12c","src/codegen/reductions/mask.rs":"e67f35a1f4d156a4894a2d6ea5a935b4d898cf70eefb2715f5c1cc165e776c11","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"c67c86e91ca3fc77539e0efcea081a3c62548cccf503963ae408f2e86f4e6a21","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"f0753b405cdc865bdf8e82c6505f299ea1f96136239ebbaf7f9ce93d310764b8","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"b6f846d5d30cf6b035a2d18039aba7b2045cf89384733d643572bd68873ae064","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"896669c08d8c801448a4d2fadc9d633eda0fbe879d229997e2a182e31278e469","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":null}
+\ No newline at end of file
+diff --git a/third_party/rust/packed_simd_2/Cargo.toml b/third_party/rust/packed_simd_2/Cargo.toml
+index f38706d05002e..49338742dc1ff 100644
+--- a/third_party/rust/packed_simd_2/Cargo.toml
++++ b/third_party/rust/packed_simd_2/Cargo.toml
+@@ -1,6 +1,6 @@
+ [package]
+ name = "packed_simd_2"
+-version = "0.3.7"
++version = "0.3.8"
+ description = "Portable Packed SIMD vectors"
+ documentation = "https://docs.rs/crate/packed_simd/"
+ homepage = "https://github.com/rust-lang/packed_simd"
+@@ -23,6 +23,9 @@ maintenance = { status = "experimental" }
+ cfg-if = "1.0.0"
+ core_arch = { version = "0.1.5", optional = true }
+
++[build-dependencies]
++rustc_version = "0.2"
++
+ [features]
+ default = []
+ into_bits = []
+diff --git a/third_party/rust/packed_simd_2/README.md b/third_party/rust/packed_simd_2/README.md
+index 41a1512d79fbc..eb3101c33d159 100644
+--- a/third_party/rust/packed_simd_2/README.md
++++ b/third_party/rust/packed_simd_2/README.md
+@@ -8,7 +8,7 @@ If you need to continue to use the crate, we have published a "next version" und
+
+ Adjust your `[dependencies]` section of `Cargo.toml` to be the following:
+ ```toml
+-packed_simd = { version = "0.3.6", package = "packed_simd_2" }
++packed_simd = { version = "0.3.8", package = "packed_simd_2" }
+ ```
+
+ # `Simd<[T; N]>`
+diff --git a/third_party/rust/packed_simd_2/build.rs b/third_party/rust/packed_simd_2/build.rs
+index e87298a2de237..afdee9f55b62b 100644
+--- a/third_party/rust/packed_simd_2/build.rs
++++ b/third_party/rust/packed_simd_2/build.rs
+@@ -1,6 +1,11 @@
++use rustc_version::{version, Version};
++
+ fn main() {
+ let target = std::env::var("TARGET").expect("TARGET environment variable not defined");
+ if target.contains("neon") {
+ println!("cargo:rustc-cfg=libcore_neon");
+ }
++ if version().unwrap() < Version::parse("1.61.0-alpha").unwrap() {
++ println!("cargo:rustc-cfg=aarch64_target_feature");
++ }
+ }
+diff --git a/third_party/rust/packed_simd_2/src/api.rs b/third_party/rust/packed_simd_2/src/api.rs
+index 4e9c4292e06ca..aa1403e6e243d 100644
+--- a/third_party/rust/packed_simd_2/src/api.rs
++++ b/third_party/rust/packed_simd_2/src/api.rs
+@@ -2,7 +2,7 @@
+
+ #[macro_use]
+ mod bitmask;
+-crate mod cast;
++pub(crate) mod cast;
+ #[macro_use]
+ mod cmp;
+ #[macro_use]
+@@ -37,7 +37,7 @@ mod swap_bytes;
+ mod bit_manip;
+
+ #[cfg(feature = "into_bits")]
+-crate mod into_bits;
++pub(crate) mod into_bits;
+
+ macro_rules! impl_i {
+ ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident
+diff --git a/third_party/rust/packed_simd_2/src/codegen.rs b/third_party/rust/packed_simd_2/src/codegen.rs
+index 9d1517e203d19..8a9e971486d74 100644
+--- a/third_party/rust/packed_simd_2/src/codegen.rs
++++ b/third_party/rust/packed_simd_2/src/codegen.rs
+@@ -1,19 +1,19 @@
+ //! Code-generation utilities
+
+-crate mod bit_manip;
+-crate mod llvm;
+-crate mod math;
+-crate mod reductions;
+-crate mod shuffle;
+-crate mod shuffle1_dyn;
+-crate mod swap_bytes;
++pub(crate) mod bit_manip;
++pub(crate) mod llvm;
++pub(crate) mod math;
++pub(crate) mod reductions;
++pub(crate) mod shuffle;
++pub(crate) mod shuffle1_dyn;
++pub(crate) mod swap_bytes;
+
+ macro_rules! impl_simd_array {
+ ([$elem_ty:ident; $elem_count:expr]:
+ $tuple_id:ident | $($elem_tys:ident),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id($(crate $elem_tys),*);
++ pub struct $tuple_id($(pub(crate) $elem_tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl crate::sealed::Seal for [$elem_ty; $elem_count] {}
+@@ -35,28 +35,28 @@ macro_rules! impl_simd_array {
+ }
+ }
+
+-crate mod pointer_sized_int;
++pub(crate) mod pointer_sized_int;
+
+-crate mod v16;
+-crate use self::v16::*;
++pub(crate) mod v16;
++pub(crate) use self::v16::*;
+
+-crate mod v32;
+-crate use self::v32::*;
++pub(crate) mod v32;
++pub(crate) use self::v32::*;
+
+-crate mod v64;
+-crate use self::v64::*;
++pub(crate) mod v64;
++pub(crate) use self::v64::*;
+
+-crate mod v128;
+-crate use self::v128::*;
++pub(crate) mod v128;
++pub(crate) use self::v128::*;
+
+-crate mod v256;
+-crate use self::v256::*;
++pub(crate) mod v256;
++pub(crate) use self::v256::*;
+
+-crate mod v512;
+-crate use self::v512::*;
++pub(crate) mod v512;
++pub(crate) use self::v512::*;
+
+-crate mod vSize;
+-crate use self::vSize::*;
++pub(crate) mod vSize;
++pub(crate) use self::vSize::*;
+
+-crate mod vPtr;
+-crate use self::vPtr::*;
++pub(crate) mod vPtr;
++pub(crate) use self::vPtr::*;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+index 5986916da4387..32d8d717a0766 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/bit_manip.rs
+@@ -1,7 +1,7 @@
+ //! LLVM bit manipulation intrinsics.
+ #[rustfmt::skip]
+
+-use crate::*;
++pub(crate) use crate::*;
+
+ #[allow(improper_ctypes, dead_code)]
+ extern "C" {
+@@ -147,7 +147,7 @@ extern "C" {
+ fn ctpop_u128x4(x: u128x4) -> u128x4;
+ }
+
+-crate trait BitManip {
++pub(crate) trait BitManip {
+ fn ctpop(self) -> Self;
+ fn ctlz(self) -> Self;
+ fn cttz(self) -> Self;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/llvm.rs b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+index 52b11a95b9172..b4c09849bc4a3 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/llvm.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/llvm.rs
+@@ -76,53 +76,53 @@ where
+ }
+
+ extern "platform-intrinsic" {
+- crate fn simd_eq<T, U>(x: T, y: T) -> U;
+- crate fn simd_ne<T, U>(x: T, y: T) -> U;
+- crate fn simd_lt<T, U>(x: T, y: T) -> U;
+- crate fn simd_le<T, U>(x: T, y: T) -> U;
+- crate fn simd_gt<T, U>(x: T, y: T) -> U;
+- crate fn simd_ge<T, U>(x: T, y: T) -> U;
+-
+- crate fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
+- crate fn simd_extract<T, U>(x: T, idx: u32) -> U;
+-
+- crate fn simd_cast<T, U>(x: T) -> U;
+-
+- crate fn simd_add<T>(x: T, y: T) -> T;
+- crate fn simd_sub<T>(x: T, y: T) -> T;
+- crate fn simd_mul<T>(x: T, y: T) -> T;
+- crate fn simd_div<T>(x: T, y: T) -> T;
+- crate fn simd_rem<T>(x: T, y: T) -> T;
+- crate fn simd_shl<T>(x: T, y: T) -> T;
+- crate fn simd_shr<T>(x: T, y: T) -> T;
+- crate fn simd_and<T>(x: T, y: T) -> T;
+- crate fn simd_or<T>(x: T, y: T) -> T;
+- crate fn simd_xor<T>(x: T, y: T) -> T;
+-
+- crate fn simd_reduce_add_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
+- crate fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
+- crate fn simd_reduce_min<T, U>(x: T) -> U;
+- crate fn simd_reduce_max<T, U>(x: T) -> U;
+- crate fn simd_reduce_min_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_max_nanless<T, U>(x: T) -> U;
+- crate fn simd_reduce_and<T, U>(x: T) -> U;
+- crate fn simd_reduce_or<T, U>(x: T) -> U;
+- crate fn simd_reduce_xor<T, U>(x: T) -> U;
+- crate fn simd_reduce_all<T>(x: T) -> bool;
+- crate fn simd_reduce_any<T>(x: T) -> bool;
+-
+- crate fn simd_select<M, T>(m: M, a: T, b: T) -> T;
+-
+- crate fn simd_fmin<T>(a: T, b: T) -> T;
+- crate fn simd_fmax<T>(a: T, b: T) -> T;
+-
+- crate fn simd_fsqrt<T>(a: T) -> T;
+- crate fn simd_fma<T>(a: T, b: T, c: T) -> T;
+-
+- crate fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
+- crate fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
+-
+- crate fn simd_bitmask<T, U>(value: T) -> U;
++ pub(crate) fn simd_eq<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ne<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_lt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_le<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_gt<T, U>(x: T, y: T) -> U;
++ pub(crate) fn simd_ge<T, U>(x: T, y: T) -> U;
++
++ pub(crate) fn simd_insert<T, U>(x: T, idx: u32, val: U) -> T;
++ pub(crate) fn simd_extract<T, U>(x: T, idx: u32) -> U;
++
++ pub(crate) fn simd_cast<T, U>(x: T) -> U;
++
++ pub(crate) fn simd_add<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_sub<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_mul<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_div<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_rem<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shl<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_shr<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_and<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_or<T>(x: T, y: T) -> T;
++ pub(crate) fn simd_xor<T>(x: T, y: T) -> T;
++
++ pub(crate) fn simd_reduce_add_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_mul_unordered<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_add_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_mul_ordered<T, U>(x: T, acc: U) -> U;
++ pub(crate) fn simd_reduce_min<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_min_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_max_nanless<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_and<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_or<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_xor<T, U>(x: T) -> U;
++ pub(crate) fn simd_reduce_all<T>(x: T) -> bool;
++ pub(crate) fn simd_reduce_any<T>(x: T) -> bool;
++
++ pub(crate) fn simd_select<M, T>(m: M, a: T, b: T) -> T;
++
++ pub(crate) fn simd_fmin<T>(a: T, b: T) -> T;
++ pub(crate) fn simd_fmax<T>(a: T, b: T) -> T;
++
++ pub(crate) fn simd_fsqrt<T>(a: T) -> T;
++ pub(crate) fn simd_fma<T>(a: T, b: T, c: T) -> T;
++
++ pub(crate) fn simd_gather<T, P, M>(value: T, pointers: P, mask: M) -> T;
++ pub(crate) fn simd_scatter<T, P, M>(value: T, pointers: P, mask: M);
++
++ pub(crate) fn simd_bitmask<T, U>(value: T) -> U;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math.rs b/third_party/rust/packed_simd_2/src/codegen/math.rs
+index f3997c7f11359..9a0ea7a4e2d24 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math.rs
+@@ -1,3 +1,3 @@
+ //! Vertical math operations
+
+-crate mod float;
++pub(crate) mod float;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float.rs b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+index 5e89bf6ae6b0c..ffbf18bfe989d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float.rs
+@@ -2,17 +2,17 @@
+ #![allow(clippy::useless_transmute)]
+
+ #[macro_use]
+-crate mod macros;
+-crate mod abs;
+-crate mod cos;
+-crate mod cos_pi;
+-crate mod exp;
+-crate mod ln;
+-crate mod mul_add;
+-crate mod mul_adde;
+-crate mod powf;
+-crate mod sin;
+-crate mod sin_cos_pi;
+-crate mod sin_pi;
+-crate mod sqrt;
+-crate mod sqrte;
++pub(crate) mod macros;
++pub(crate) mod abs;
++pub(crate) mod cos;
++pub(crate) mod cos_pi;
++pub(crate) mod exp;
++pub(crate) mod ln;
++pub(crate) mod mul_add;
++pub(crate) mod mul_adde;
++pub(crate) mod powf;
++pub(crate) mod sin;
++pub(crate) mod sin_cos_pi;
++pub(crate) mod sin_pi;
++pub(crate) mod sqrt;
++pub(crate) mod sqrte;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+index bc4421f61de2d..34aacc25be75a 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/abs.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Abs {
++pub(crate) trait Abs {
+ fn abs(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+index 50f6c16da2555..dec390cb74d46 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Cos {
++pub(crate) trait Cos {
+ fn cos(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+index ebff5fd1c7510..e283280ee44b1 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait CosPi {
++pub(crate) trait CosPi {
+ fn cos_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+index 00d10e9fa6440..a7b20580e3f1e 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/exp.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Exp {
++pub(crate) trait Exp {
+ fn exp(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+index 88a5a6c6c1589..a5e38cb40d1ed 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/ln.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Ln {
++pub(crate) trait Ln {
+ fn ln(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+index f48a57dc46c69..d37f30fa86140 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_add.rs
+@@ -4,7 +4,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_add
+
+-crate trait MulAdd {
++pub(crate) trait MulAdd {
+ fn mul_add(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+index b030c26ccf465..c0baeacec20be 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/mul_adde.rs
+@@ -3,7 +3,7 @@ use crate::*;
+
+ // FIXME: 64-bit 1 element mul_adde
+
+-crate trait MulAddE {
++pub(crate) trait MulAddE {
+ fn mul_adde(self, y: Self, z: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+index bc15067d73a30..89ca52e96d818 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/powf.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Powf {
++pub(crate) trait Powf {
+ fn powf(self, x: Self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+index 7b014d07da8d9..d881415909afe 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sin {
++pub(crate) trait Sin {
+ fn sin(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+index 75c2c2c5fbb03..b283d11111fd5 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinCosPi: Sized {
++pub(crate) trait SinCosPi: Sized {
+ type Output;
+ fn sin_cos_pi(self) -> Self::Output;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+index 72df98c93c91e..0c8f6bb120503 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sin_pi.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SinPi {
++pub(crate) trait SinPi {
+ fn sin_pi(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+index 7ce31df626621..67bb0a2a9c594 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrt.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait Sqrt {
++pub(crate) trait Sqrt {
+ fn sqrt(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+index c1e379c34241f..58a1de1f400f9 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/math/float/sqrte.rs
+@@ -6,7 +6,7 @@
+ use crate::llvm::simd_fsqrt;
+ use crate::*;
+
+-crate trait Sqrte {
++pub(crate) trait Sqrte {
+ fn sqrte(self) -> Self;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+index 39f493d3b17f0..55cbc297aaf52 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/pointer_sized_int.rs
+@@ -4,24 +4,24 @@ use cfg_if::cfg_if;
+
+ cfg_if! {
+ if #[cfg(target_pointer_width = "8")] {
+- crate type isize_ = i8;
+- crate type usize_ = u8;
++ pub(crate) type isize_ = i8;
++ pub(crate) type usize_ = u8;
+ } else if #[cfg(target_pointer_width = "16")] {
+- crate type isize_ = i16;
+- crate type usize_ = u16;
++ pub(crate) type isize_ = i16;
++ pub(crate) type usize_ = u16;
+ } else if #[cfg(target_pointer_width = "32")] {
+- crate type isize_ = i32;
+- crate type usize_ = u32;
++ pub(crate) type isize_ = i32;
++ pub(crate) type usize_ = u32;
+
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "64")] {
+- crate type isize_ = i64;
+- crate type usize_ = u64;
++ pub(crate) type isize_ = i64;
++ pub(crate) type usize_ = u64;
+ } else if #[cfg(target_pointer_width = "128")] {
+- crate type isize_ = i128;
+- crate type usize_ = u128;
++ pub(crate) type isize_ = i128;
++ pub(crate) type usize_ = u128;
+ } else {
+ compile_error!("unsupported target_pointer_width");
+ }
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions.rs b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+index 7be4f5fabbea9..302ca6d88f33d 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions.rs
+@@ -1 +1 @@
+-crate mod mask;
++pub(crate) mod mask;
+diff --git a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+index 0aec60969b864..a78bcc5632672 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/reductions/mask.rs
+@@ -7,11 +7,11 @@
+
+ use crate::*;
+
+-crate trait All: crate::marker::Sized {
++pub(crate) trait All: crate::marker::Sized {
+ unsafe fn all(self) -> bool;
+ }
+
+-crate trait Any: crate::marker::Sized {
++pub(crate) trait Any: crate::marker::Sized {
+ unsafe fn any(self) -> bool;
+ }
+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+index a4435e3c35354..9cf34a3e0401c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/swap_bytes.rs
+@@ -5,7 +5,7 @@
+
+ use crate::*;
+
+-crate trait SwapBytes {
++pub(crate) trait SwapBytes {
+ fn swap_bytes(self) -> Self;
+ }
+
+@@ -15,7 +15,7 @@ macro_rules! impl_swap_bytes {
+ impl SwapBytes for $id {
+ #[inline]
+ fn swap_bytes(self) -> Self {
+- unsafe { shuffle!(self, [1, 0]) }
++ shuffle!(self, [1, 0])
+ }
+ }
+ )+
+diff --git a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+index cf4765538178d..abd3aa877920c 100644
+--- a/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
++++ b/third_party/rust/packed_simd_2/src/codegen/vPtr.rs
+@@ -5,7 +5,7 @@ macro_rules! impl_simd_ptr {
+ | $($tys:ty),*) => {
+ #[derive(Copy, Clone)]
+ #[repr(simd)]
+- pub struct $tuple_id<$ty>($(crate $tys),*);
++ pub struct $tuple_id<$ty>($(pub(crate) $tys),*);
+ //^^^^^^^ leaked through SimdArray
+
+ impl<$ty> crate::sealed::Seal for [$ptr_ty; $elem_count] {}
+diff --git a/third_party/rust/packed_simd_2/src/lib.rs b/third_party/rust/packed_simd_2/src/lib.rs
+index 840bae38d6a30..cd8a86805dd59 100644
+--- a/third_party/rust/packed_simd_2/src/lib.rs
++++ b/third_party/rust/packed_simd_2/src/lib.rs
+@@ -217,14 +217,13 @@
+ rustc_attrs,
+ platform_intrinsics,
+ stdsimd,
+- aarch64_target_feature,
+ arm_target_feature,
+ link_llvm_intrinsics,
+ core_intrinsics,
+ stmt_expr_attributes,
+- crate_visibility_modifier,
+ custom_inner_attributes,
+ )]
++#![cfg_attr(aarch64_target_feature, feature(aarch64_target_feature))]
+ #![allow(non_camel_case_types, non_snake_case,
+ // FIXME: these types are unsound in C FFI already
+ // See https://github.com/rust-lang/rust/issues/53346
+@@ -344,6 +343,6 @@ pub use self::codegen::llvm::{
+ __shuffle_vector8,
+ };
+
+-crate mod llvm {
+- crate use crate::codegen::llvm::*;
++pub(crate) mod llvm {
++ pub(crate) use crate::codegen::llvm::*;
+ }
+diff --git a/third_party/rust/packed_simd_2/src/testing.rs b/third_party/rust/packed_simd_2/src/testing.rs
+index fcbcf9e2ac8eb..6320b28055569 100644
+--- a/third_party/rust/packed_simd_2/src/testing.rs
++++ b/third_party/rust/packed_simd_2/src/testing.rs
+@@ -5,4 +5,4 @@ mod macros;
+
+ #[cfg(test)]
+ #[macro_use]
+-crate mod utils;
++pub(crate) mod utils;
diff --git a/srcpkgs/firefox-esr/patches/fix-cbindgen.patch b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
new file mode 100644
index 000000000000..ba3ce7ae3e97
--- /dev/null
+++ b/srcpkgs/firefox-esr/patches/fix-cbindgen.patch
@@ -0,0 +1,22 @@
+Fix error with new cbindgen:
+
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi_generated.h:24:33: error: redefinition of 'constexpr const uint64_t mozilla::wr::ROOT_CLIP_CHAIN'
+ 24 | constexpr static const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+/builddir/firefox-102.1.0/obj-x86_64-unknown-linux-gnu/dist/include/mozilla/webrender/webrender_ffi.h:76:16: note: 'const uint64_t mozilla::wr::ROOT_CLIP_CHAIN' previously defined here
+ 76 | const uint64_t ROOT_CLIP_CHAIN = ~0;
+ | ^~~~~~~~~~~~~~~
+
+diff --git a/gfx/webrender_bindings/webrender_ffi.h b/gfx/webrender_bindings/webrender_ffi.h
+index b1d67b17a4bde..eb79974bdf434 100644
+--- a/gfx/webrender_bindings/webrender_ffi.h
++++ b/gfx/webrender_bindings/webrender_ffi.h
+@@ -73,8 +73,6 @@ struct WrPipelineInfo;
+ struct WrPipelineIdAndEpoch;
+ using WrPipelineIdEpochs = nsTArray<WrPipelineIdAndEpoch>;
+
+-const uint64_t ROOT_CLIP_CHAIN = ~0;
+-
+ } // namespace wr
+ } // namespace mozilla
+
diff --git a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
similarity index 64%
rename from srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
rename to srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
index c4664d3da7ce..3f0273cba366 100644
--- a/srcpkgs/firefox-esr/patches/fix-desktop-icon-path.patch
+++ b/srcpkgs/firefox-esr/patches/fix-firefox-desktop.patch
@@ -1,6 +1,6 @@
---- a/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:31:39.428839442 +0100
-+++ b/taskcluster/docker/firefox-snap/firefox.desktop 2019-01-18 19:32:20.689063456 +0100
-@@ -154,7 +154,7 @@
+--- a/taskcluster/docker/firefox-snap/firefox.desktop
++++ b/taskcluster/docker/firefox-snap/firefox.desktop
+@@ -154,11 +154,12 @@
Terminal=false
X-MultipleArgs=false
Type=Application
@@ -9,3 +9,8 @@
Categories=GNOME;GTK;Network;WebBrowser;
MimeType=text/html;text/xml;application/xhtml+xml;application/xml;application/rss+xml;application/rdf+xml;image/gif;image/jpeg;image/png;x-scheme-handler/http;x-scheme-handler/https;x-scheme-handler/ftp;x-scheme-handler/chrome;video/webm;application/x-xpinstall;
StartupNotify=true
+ Actions=NewWindow;NewPrivateWindow;
++StartupWMClass=Firefox
+
+ [Desktop Action NewWindow]
+ Name=Open a New Window
diff --git a/srcpkgs/firefox-esr/patches/fix-tools.patch b/srcpkgs/firefox-esr/patches/fix-tools.patch
deleted file mode 100644
index 94de423ce593..000000000000
--- a/srcpkgs/firefox-esr/patches/fix-tools.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:09:40.980448579 +0100
-+++ b/tools/profiler/core/platform-linux-android.cpp 2019-01-29 12:11:09.689590967 +0100
-@@ -497,8 +501,10 @@
- ucontext_t sSyncUContext;
-
- void Registers::SyncPopulate() {
-+#if defined(__GLIBC__)
- if (!getcontext(&sSyncUContext)) {
- PopulateRegsFromContext(*this, &sSyncUContext);
- }
-+#endif
- }
- #endif
diff --git a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
index 5d17021a99f4..4f9043b58e1e 100644
--- a/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
+++ b/srcpkgs/firefox-esr/patches/fix-webrtc-glibcisms.patch
@@ -1,20 +1,20 @@
---- a/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:20:52.298793223 +0100
-+++ b/third_party/libwebrtc/webrtc/system_wrappers/source/cpu_features_linux.c 2019-01-29 11:21:48.250250850 +0100
-@@ -14,7 +14,7 @@
- #ifndef __GLIBC_PREREQ
- #define __GLIBC_PREREQ(a, b) 0
+--- a/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
++++ b/third_party/libwebrtc/system_wrappers/source/cpu_features_linux.cc
+@@ -18,7 +18,7 @@
+ #define WEBRTC_GLIBC_PREREQ(a, b) 0
#endif
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
#include <sys/auxv.h>
#else
- #include <fcntl.h>
-@@ -32,7 +32,7 @@
+ #include <errno.h>
+@@ -40,7 +40,7 @@
int architecture = 0;
- unsigned long hwcap = 0;
+ uint64_t hwcap = 0;
const char* platform = NULL;
--#if __GLIBC_PREREQ(2, 16)
-+#if !__GLIBC__ || __GLIBC_PREREQ(2, 16)
+-#if WEBRTC_GLIBC_PREREQ(2, 16)
++#if !__GLIBC__ || WEBRTC_GLIBC_PREREQ(2, 16)
hwcap = getauxval(AT_HWCAP);
platform = (const char*)getauxval(AT_PLATFORM);
#else
diff --git a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch b/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
deleted file mode 100644
index cced0058e8e1..000000000000
--- a/srcpkgs/firefox-esr/patches/ppc64le-jit.patch
+++ /dev/null
@@ -1,3441 +0,0 @@
-diff --git a/config/check_macroassembler_style.py b/config/check_macroassembler_style.py
-index 0d040a939b..b83e3691dd 100644
---- a/config/check_macroassembler_style.py
-+++ b/config/check_macroassembler_style.py
-@@ -24,17 +24,17 @@ from __future__ import absolute_import
- from __future__ import print_function
-
- import difflib
- import os
- import re
- import sys
-
- architecture_independent = set(["generic"])
--all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared"])
-+all_unsupported_architectures_names = set(["mips32", "mips64", "mips_shared", "ppc64"])
- all_architecture_names = set(["x86", "x64", "arm", "arm64"])
- all_shared_architecture_names = set(["x86_shared", "arm", "arm64"])
-
- reBeforeArg = "(?<=[(,\s])"
- reArgType = "(?P<type>[\w\s:*&]+)"
- reArgName = "(?P<name>\s\w+)"
- reArgDefault = "(?P<default>(?:\s=[^,)]+)?)"
- reAfterArg = "(?=[,)])"
-diff --git a/js/moz.configure b/js/moz.configure
-index 3c3d0d4359..b217d0e15c 100644
---- a/js/moz.configure
-+++ b/js/moz.configure
-@@ -214,23 +214,25 @@ def jit_codegen(jit_enabled, simulator, target):
- return namespace(**{str(target.cpu): True})
-
-
- set_config("JS_CODEGEN_NONE", jit_codegen.none)
- set_config("JS_CODEGEN_ARM", jit_codegen.arm)
- set_config("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_config("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_config("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_config("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_config("JS_CODEGEN_X86", jit_codegen.x86)
- set_config("JS_CODEGEN_X64", jit_codegen.x64)
- set_define("JS_CODEGEN_NONE", jit_codegen.none)
- set_define("JS_CODEGEN_ARM", jit_codegen.arm)
- set_define("JS_CODEGEN_ARM64", jit_codegen.arm64)
- set_define("JS_CODEGEN_MIPS32", jit_codegen.mips32)
- set_define("JS_CODEGEN_MIPS64", jit_codegen.mips64)
-+set_define("JS_CODEGEN_PPC64", jit_codegen.ppc64)
- set_define("JS_CODEGEN_X86", jit_codegen.x86)
- set_define("JS_CODEGEN_X64", jit_codegen.x64)
-
- # Profiling
- # =======================================================
- option(
- "--enable-instruments",
- env="MOZ_INSTRUMENTS",
-diff --git a/js/src/irregexp/RegExpNativeMacroAssembler.cpp b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-index e0ef7e64f5..81d8e2a198 100644
---- a/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-+++ b/js/src/irregexp/RegExpNativeMacroAssembler.cpp
-@@ -813,18 +813,33 @@ void SMRegExpMacroAssembler::JumpOrBacktrack(Label* to) {
- // If the test fails, call an OOL handler to try growing the stack.
- void SMRegExpMacroAssembler::CheckBacktrackStackLimit() {
- js::jit::Label no_stack_overflow;
- masm_.branchPtr(
- Assembler::BelowOrEqual,
- AbsoluteAddress(isolate()->regexp_stack()->limit_address_address()),
- backtrack_stack_pointer_, &no_stack_overflow);
-
-+#ifdef JS_CODEGEN_PPC64
-+ // LR on PowerPC isn't a GPR, so we have to explicitly save it here before
-+ // we call or we will end up erroneously returning after the call to the
-+ // stack overflow handler when we |blr| out and inevitably underflow the
-+ // irregexp stack on the next backtrack.
-+ masm_.xs_mflr(temp1_);
-+ masm_.as_stdu(temp1_, masm_.getStackPointer(), -8);
-+#endif
-+
- masm_.call(&stack_overflow_label_);
-
-+#ifdef JS_CODEGEN_PPC64
-+ masm_.as_ld(temp1_, masm_.getStackPointer(), 0);
-+ masm_.xs_mtlr(temp1_);
-+ masm_.as_addi(masm_.getStackPointer(), masm_.getStackPointer(), 8);
-+#endif
-+
- // Exit with an exception if the call failed
- masm_.branchTest32(Assembler::Zero, temp0_, temp0_,
- &exit_with_exception_label_);
-
- masm_.bind(&no_stack_overflow);
- }
-
- // This is used to sneak an OOM through the V8 layer.
-@@ -1127,16 +1142,20 @@ void SMRegExpMacroAssembler::stackOverflowHandler() {
- LiveGeneralRegisterSet volatileRegs(GeneralRegisterSet::Volatile());
-
- #ifdef JS_USE_LINK_REGISTER
- masm_.pushReturnAddress();
- #endif
-
- // Adjust for the return address on the stack.
- size_t frameOffset = sizeof(void*);
-+#ifdef JS_CODEGEN_PPC64
-+ // We have a double return address.
-+ frameOffset += sizeof(void*);
-+#endif
-
- volatileRegs.takeUnchecked(temp0_);
- volatileRegs.takeUnchecked(temp1_);
- masm_.PushRegsInMask(volatileRegs);
-
- using Fn = bool (*)(RegExpStack * regexp_stack);
- masm_.setupUnalignedABICall(temp0_);
- masm_.passABIArg(temp1_);
-diff --git a/js/src/jit/AtomicOperations.h b/js/src/jit/AtomicOperations.h
-index f4a5727d05..138612d53b 100644
---- a/js/src/jit/AtomicOperations.h
-+++ b/js/src/jit/AtomicOperations.h
-@@ -373,19 +373,26 @@ constexpr inline bool AtomicOperations::isLockfreeJS(int32_t size) {
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- # endif
- #elif defined(__mips__)
- # if defined(__clang__) || defined(__GNUC__)
- # include "jit/mips-shared/AtomicOperations-mips-shared.h"
- # else
- # error "AtomicOperations on MIPS for an unknown compiler"
- # endif
-+#elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-+ defined(__PPC64LE__)
-+# if defined(JS_CODEGEN_PPC64)
-+/* XXX: should be # include "jit/shared/AtomicOperations-shared-jit.h" */
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# else
-+# include "jit/shared/AtomicOperations-feeling-lucky.h"
-+# endif
- #elif defined(__ppc__) || defined(__PPC__) || defined(__sparc__) || \
-- defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
-- defined(__PPC64LE__) || defined(__alpha__) || defined(__hppa__) || \
-+ defined(__alpha__) || defined(__hppa__) || \
- defined(__sh__) || defined(__s390__) || defined(__s390x__) || \
- defined(__m68k__) || defined(__riscv) || defined(__wasi__)
- # include "jit/shared/AtomicOperations-feeling-lucky.h"
- #else
- # error "No AtomicOperations support provided for this platform"
- #endif
-
- #endif // jit_AtomicOperations_h
-diff --git a/js/src/jit/BaselineBailouts.cpp b/js/src/jit/BaselineBailouts.cpp
-index bca1427f93..eb499b34cf 100644
---- a/js/src/jit/BaselineBailouts.cpp
-+++ b/js/src/jit/BaselineBailouts.cpp
-@@ -481,16 +481,21 @@ class MOZ_STACK_CLASS BaselineStackBuilder {
- // let X = STACK_START_ADDR + JitFrameLayout::Size() + PREV_FRAME_SIZE
- // X + RectifierFrameLayout::Size()
- // + ((RectifierFrameLayout*) X)->prevFrameLocalSize()
- // - BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr()
- size_t extraOffset =
- RectifierFrameLayout::Size() + priorFrame->prevFrameLocalSize() +
- BaselineStubFrameLayout::reverseOffsetOfSavedFramePtr();
- return virtualPointerAtStackOffset(priorOffset + extraOffset);
-+#elif defined(JS_CODEGEN_PPC64)
-+ (void)priorOffset;
-+// XXX. The above code might work though
-+#warning "TODO! BaselineStackBuilder::calculatePrevFramePtr()"
-+ MOZ_CRASH();
- #elif defined(JS_CODEGEN_NONE)
- (void)priorOffset;
- MOZ_CRASH();
- #else
- # error "Bad architecture!"
- #endif
- }
- };
-diff --git a/js/src/jit/BaselineCodeGen.cpp b/js/src/jit/BaselineCodeGen.cpp
-index 7089f5e300..d67236d2c5 100644
---- a/js/src/jit/BaselineCodeGen.cpp
-+++ b/js/src/jit/BaselineCodeGen.cpp
-@@ -520,16 +520,19 @@ bool BaselineCodeGen<Handler>::emitOutOfLinePostBarrierSlot() {
- regs.take(BaselineFrameReg);
- Register scratch = regs.takeAny();
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // On ARM, save the link register before calling. It contains the return
- // address. The |masm.ret()| later will pop this into |pc| to return.
- masm.push(lr);
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- masm.push(ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.xs_mflr(ScratchRegister);
-+ masm.push(ScratchRegister);
- #endif
- masm.pushValue(R0);
-
- using Fn = void (*)(JSRuntime * rt, js::gc::Cell * cell);
- masm.setupUnalignedABICall(scratch);
- masm.movePtr(ImmPtr(cx->runtime()), scratch);
- masm.passABIArg(scratch);
- masm.passABIArg(objReg);
-diff --git a/js/src/jit/BaselineIC.cpp b/js/src/jit/BaselineIC.cpp
-index 9572394e76..dfe762e5c8 100644
---- a/js/src/jit/BaselineIC.cpp
-+++ b/js/src/jit/BaselineIC.cpp
-@@ -127,17 +127,18 @@ class MOZ_RAII FallbackICCodeCompiler final {
- };
-
- AllocatableGeneralRegisterSet BaselineICAvailableGeneralRegs(size_t numInputs) {
- AllocatableGeneralRegisterSet regs(GeneralRegisterSet::All());
- #if defined(JS_CODEGEN_ARM)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- regs.take(BaselineSecondScratchReg);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- MOZ_ASSERT(!regs.has(BaselineStackReg));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- MOZ_ASSERT(!regs.has(BaselineSecondScratchReg));
- #elif defined(JS_CODEGEN_ARM64)
- MOZ_ASSERT(!regs.has(PseudoStackPointer));
- MOZ_ASSERT(!regs.has(RealStackPointer));
- MOZ_ASSERT(!regs.has(ICTailCallReg));
- #else
-diff --git a/js/src/jit/CodeGenerator.h b/js/src/jit/CodeGenerator.h
-index 5321978fc2..b2d9a8f5a5 100644
---- a/js/src/jit/CodeGenerator.h
-+++ b/js/src/jit/CodeGenerator.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/CodeGenerator-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/CodeGenerator-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/CodeGenerator-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/CodeGenerator-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/CodeGenerator-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/CodeGenerator-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmGC.h"
-
-diff --git a/js/src/jit/FlushICache.h b/js/src/jit/FlushICache.h
-index fe66080df5..2071563c1e 100644
---- a/js/src/jit/FlushICache.h
-+++ b/js/src/jit/FlushICache.h
-@@ -19,17 +19,18 @@ namespace jit {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- // No-op. Code and data caches are coherent on x86 and x64.
- }
-
- #elif (defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)) || \
-- (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64))
-+ (defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)) || \
-+ defined(JS_CODEGEN_PPC64)
-
- extern void FlushICache(void* code, size_t size, bool codeIsThreadLocal = true);
-
- #elif defined(JS_CODEGEN_NONE)
-
- inline void FlushICache(void* code, size_t size,
- bool codeIsThreadLocal = true) {
- MOZ_CRASH();
-diff --git a/js/src/jit/JitFrames.cpp b/js/src/jit/JitFrames.cpp
-index 77cfe6a9cd..507f1551e6 100644
---- a/js/src/jit/JitFrames.cpp
-+++ b/js/src/jit/JitFrames.cpp
-@@ -2220,16 +2220,24 @@ MachineState MachineState::FromBailout(RegisterDump::GPRArray& regs,
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Single),
- &fpregs[i]);
- machine.setRegisterLocation(
- FloatRegister(FloatRegisters::Encoding(i), FloatRegisters::Double),
- &fpregs[i]);
- // No SIMD support in bailouts, SIMD is internal to wasm
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) {
-+ machine.setRegisterLocation(FloatRegister(i), &fpregs[i]);
-+# ifdef ENABLE_WASM_SIMD
-+ // Needs additional handling if VMX or non-FPR VSX regs are in play.
-+# error "SIMD for PPC NYI"
-+# endif
-+ }
-
- #elif defined(JS_CODEGEN_NONE)
- MOZ_CRASH();
- #else
- # error "Unknown architecture!"
- #endif
- return machine;
- }
-diff --git a/js/src/jit/JitFrames.h b/js/src/jit/JitFrames.h
-index 40c661d146..7b4ea3157d 100644
---- a/js/src/jit/JitFrames.h
-+++ b/js/src/jit/JitFrames.h
-@@ -152,16 +152,26 @@ struct ResumeFromException {
- static const uint32_t RESUME_ENTRY_FRAME = 0;
- static const uint32_t RESUME_CATCH = 1;
- static const uint32_t RESUME_FINALLY = 2;
- static const uint32_t RESUME_FORCED_RETURN = 3;
- static const uint32_t RESUME_BAILOUT = 4;
- static const uint32_t RESUME_WASM = 5;
- static const uint32_t RESUME_WASM_CATCH = 6;
-
-+#if defined(JS_CODEGEN_PPC64)
-+ // This gets built on the stack as part of exception returns. Because
-+ // it goes right on top of the stack, an ABI-compliant routine can wreck
-+ // it, so we implement a minimum Power ISA linkage area (four doublewords).
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
-+
- uint8_t* framePointer;
- uint8_t* stackPointer;
- uint8_t* target;
- uint32_t kind;
-
- // Value to push when resuming into a |finally| block.
- // Also used by Wasm to send the exception object to the throw stub.
- JS::Value exception;
-diff --git a/js/src/jit/JitOptions.cpp b/js/src/jit/JitOptions.cpp
-index de13777fc3..795e41bf21 100644
---- a/js/src/jit/JitOptions.cpp
-+++ b/js/src/jit/JitOptions.cpp
-@@ -132,17 +132,22 @@ DefaultJitOptions::DefaultJitOptions() {
- // Warp compile Generator functions
- SET_DEFAULT(warpGenerator, true);
-
- // Whether the IonMonkey and Baseline JITs are enabled for Trusted Principals.
- // (Ignored if ion or baselineJit is set to true.)
- SET_DEFAULT(jitForTrustedPrincipals, false);
-
- // Whether the RegExp JIT is enabled.
-+#if defined(JS_CODEGEN_PPC64)
-+ // This may generate ISA 3 instructions. The other JIT tiers gate on it too.
-+ SET_DEFAULT(nativeRegExp, MacroAssembler::SupportsFloatingPoint());
-+#else
- SET_DEFAULT(nativeRegExp, true);
-+#endif
-
- // Whether Warp should use ICs instead of transpiling Baseline CacheIR.
- SET_DEFAULT(forceInlineCaches, false);
-
- // Whether all ICs should be initialized as megamorphic ICs.
- SET_DEFAULT(forceMegamorphicICs, false);
-
- // Toggles whether large scripts are rejected.
-diff --git a/js/src/jit/LIR.h b/js/src/jit/LIR.h
-index 024bd798ca..0cd43c12ab 100644
---- a/js/src/jit/LIR.h
-+++ b/js/src/jit/LIR.h
-@@ -1939,16 +1939,18 @@ AnyRegister LAllocation::toRegister() const {
- # include "jit/arm64/LIR-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/LIR-mips32.h"
- # elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/LIR-mips64.h"
- # endif
- # include "jit/mips-shared/LIR-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/LIR-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/LIR-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #undef LIR_HEADER
-
-diff --git a/js/src/jit/Label.h b/js/src/jit/Label.h
-index a8f93de378..480b18b251 100644
---- a/js/src/jit/Label.h
-+++ b/js/src/jit/Label.h
-@@ -21,17 +21,18 @@ struct LabelBase {
- uint32_t bound_ : 1;
-
- // offset_ < INVALID_OFFSET means that the label is either bound or has
- // incoming uses and needs to be bound.
- uint32_t offset_ : 31;
-
- void operator=(const LabelBase& label) = delete;
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- public:
- #endif
- static const uint32_t INVALID_OFFSET = 0x7fffffff; // UINT31_MAX.
-
- public:
- LabelBase() : bound_(false), offset_(INVALID_OFFSET) {}
-
- // If the label is bound, all incoming edges have been patched and any
-diff --git a/js/src/jit/Lowering.h b/js/src/jit/Lowering.h
-index 979687da85..c064e5d914 100644
---- a/js/src/jit/Lowering.h
-+++ b/js/src/jit/Lowering.h
-@@ -18,16 +18,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Lowering-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Lowering-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Lowering-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Lowering-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Lowering-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Lowering-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler-inl.h b/js/src/jit/MacroAssembler-inl.h
-index cf16cdf0a7..fa39c5f4d2 100644
---- a/js/src/jit/MacroAssembler-inl.h
-+++ b/js/src/jit/MacroAssembler-inl.h
-@@ -30,16 +30,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32-inl.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64-inl.h"
- #elif !defined(JS_CODEGEN_NONE)
- # error "Unknown architecture!"
- #endif
-
- #include "wasm/WasmBuiltins.h"
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/MacroAssembler.cpp b/js/src/jit/MacroAssembler.cpp
-index 2a3aeec607..cbe9d14f46 100644
---- a/js/src/jit/MacroAssembler.cpp
-+++ b/js/src/jit/MacroAssembler.cpp
-@@ -4044,16 +4044,18 @@ void MacroAssembler::emitPreBarrierFastPath(JSRuntime* rt, MIRType type,
- #elif JS_CODEGEN_ARM
- ma_lsl(temp3, temp1, temp1);
- #elif JS_CODEGEN_ARM64
- Lsl(ARMRegister(temp1, 64), ARMRegister(temp1, 64), ARMRegister(temp3, 64));
- #elif JS_CODEGEN_MIPS32
- ma_sll(temp1, temp1, temp3);
- #elif JS_CODEGEN_MIPS64
- ma_dsll(temp1, temp1, temp3);
-+#elif JS_CODEGEN_PPC64
-+ as_sld(temp1, temp1, temp3);
- #elif JS_CODEGEN_NONE
- MOZ_CRASH();
- #else
- # error "Unknown architecture"
- #endif
-
- // No barrier is needed if the bit is set, |word & mask != 0|.
- branchTestPtr(Assembler::NonZero, temp2, temp1, noBarrier);
-diff --git a/js/src/jit/MacroAssembler.h b/js/src/jit/MacroAssembler.h
-index e2d53d5cef..cb0148b94e 100644
---- a/js/src/jit/MacroAssembler.h
-+++ b/js/src/jit/MacroAssembler.h
-@@ -20,16 +20,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MacroAssembler-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MacroAssembler-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MacroAssembler-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MacroAssembler-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MacroAssembler-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MacroAssembler-none.h"
- #else
- # error "Unknown architecture!"
- #endif
- #include "jit/ABIFunctions.h"
- #include "jit/AtomicOp.h"
- #include "jit/AutoJitContextAlloc.h"
-@@ -87,18 +89,18 @@
- // //{{{ check_macroassembler_style
- // inline uint32_t
- // MacroAssembler::framePushed() const
- // {
- // return framePushed_;
- // }
- // ////}}} check_macroassembler_style
-
--#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64
--#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared
-+#define ALL_ARCH mips32, mips64, arm, arm64, x86, x64, ppc64
-+#define ALL_SHARED_ARCH arm, arm64, x86_shared, mips_shared, ppc64
-
- // * How this macro works:
- //
- // DEFINED_ON is a macro which check if, for the current architecture, the
- // method is defined on the macro assembler or not.
- //
- // For each architecture, we have a macro named DEFINED_ON_arch. This macro is
- // empty if this is not the current architecture. Otherwise it must be either
-@@ -134,16 +136,17 @@
- #define DEFINED_ON_x86
- #define DEFINED_ON_x64
- #define DEFINED_ON_x86_shared
- #define DEFINED_ON_arm
- #define DEFINED_ON_arm64
- #define DEFINED_ON_mips32
- #define DEFINED_ON_mips64
- #define DEFINED_ON_mips_shared
-+#define DEFINED_ON_ppc64
- #define DEFINED_ON_none
-
- // Specialize for each architecture.
- #if defined(JS_CODEGEN_X86)
- # undef DEFINED_ON_x86
- # define DEFINED_ON_x86 define
- # undef DEFINED_ON_x86_shared
- # define DEFINED_ON_x86_shared define
-@@ -163,16 +166,19 @@
- # define DEFINED_ON_mips32 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
- #elif defined(JS_CODEGEN_MIPS64)
- # undef DEFINED_ON_mips64
- # define DEFINED_ON_mips64 define
- # undef DEFINED_ON_mips_shared
- # define DEFINED_ON_mips_shared define
-+#elif defined(JS_CODEGEN_PPC64)
-+# undef DEFINED_ON_ppc64
-+# define DEFINED_ON_ppc64 define
- #elif defined(JS_CODEGEN_NONE)
- # undef DEFINED_ON_none
- # define DEFINED_ON_none crash
- #else
- # error "Unknown architecture!"
- #endif
-
- #define DEFINED_ON_RESULT_crash \
-@@ -479,36 +485,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // targets roll their own save-code instead.
- //
- // Nevertheless, because some targets *do* call PushRegsInMask from
- // JitRuntime::generateInvalidator, you should check carefully all of the
- // ::generateInvalidator methods if you change the PushRegsInMask format.
-
- // The size of the area used by PushRegsInMask.
- size_t PushRegsInMaskSizeInBytes(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PushRegsInMask(LiveRegisterSet set)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- void PushRegsInMask(LiveGeneralRegisterSet set);
-
- // Like PushRegsInMask, but instead of pushing the registers, store them to
- // |dest|. |dest| should point to the end of the reserved space, so the
- // first register will be stored at |dest.offset - sizeof(register)|. It is
- // required that |dest.offset| is at least as large as the value computed by
- // PushRegsInMaskSizeInBytes for this |set|. In other words, |dest.base|
- // must point to either the lowest address in the save area, or some address
- // below that.
- void storeRegsInMask(LiveRegisterSet set, Address dest, Register scratch)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void PopRegsInMask(LiveRegisterSet set);
- void PopRegsInMask(LiveGeneralRegisterSet set);
- void PopRegsInMaskIgnore(LiveRegisterSet set, LiveRegisterSet ignore)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // ===============================================================
- // Stack manipulation functions -- single registers/values.
-
- void Push(const Operand op) DEFINED_ON(x86_shared);
- void Push(Register reg) PER_SHARED_ARCH;
- void Push(Register reg1, Register reg2, Register reg3, Register reg4)
- DEFINED_ON(arm64);
-@@ -531,17 +537,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline CodeOffset PushWithPatch(ImmWord word);
- inline CodeOffset PushWithPatch(ImmPtr imm);
-
- void Pop(const Operand op) DEFINED_ON(x86_shared);
- void Pop(Register reg) PER_SHARED_ARCH;
- void Pop(FloatRegister t) PER_SHARED_ARCH;
- void Pop(const ValueOperand& val) PER_SHARED_ARCH;
- void PopFlags() DEFINED_ON(x86_shared);
-- void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared);
-+ void PopStackPtr() DEFINED_ON(arm, mips_shared, x86_shared, ppc64);
- void popRooted(VMFunctionData::RootType rootType, Register cellReg,
- const ValueOperand& valueReg);
-
- // Move the stack pointer based on the requested amount.
- void adjustStack(int amount);
- void freeStack(uint32_t amount);
-
- // Warning: This method does not update the framePushed() counter.
-@@ -589,18 +595,18 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Push the return address and make a call. On platforms where this function
- // is not defined, push the link register (pushReturnAddress) at the entry
- // point of the callee.
- void callAndPushReturnAddress(Register reg) DEFINED_ON(x86_shared);
- void callAndPushReturnAddress(Label* label) DEFINED_ON(x86_shared);
-
- // These do not adjust framePushed().
-- void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-- void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64);
-+ void pushReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-+ void popReturnAddress() DEFINED_ON(mips_shared, arm, arm64, ppc64);
-
- // Useful for dealing with two-valued returns.
- void moveRegPair(Register src0, Register src1, Register dst0, Register dst1,
- MoveOp::Type type = MoveOp::GENERAL);
-
- public:
- // ===============================================================
- // Patchable near/far jumps.
-@@ -621,20 +627,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // These methods are like movWithPatch/PatchDataWithValueCheck but allow
- // using pc-relative addressing on certain platforms (RIP-relative LEA on x64,
- // ADR instruction on arm64).
- //
- // Note: "Near" applies to ARM64 where the target must be within 1 MB (this is
- // release-asserted).
- CodeOffset moveNearAddressWithPatch(Register dest)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
- static void patchNearAddressMove(CodeLocationLabel loc,
- CodeLocationLabel target)
-- DEFINED_ON(x86, x64, arm, arm64, mips_shared);
-+ DEFINED_ON(x86, x64, arm, arm64, mips_shared, ppc64);
-
- public:
- // ===============================================================
- // [SMDOC] JIT-to-C++ Function Calls (callWithABI)
- //
- // callWithABI is used to make a call using the standard C/C++ system ABI.
- //
- // callWithABI is a low level interface for making calls, as such every call
-@@ -983,20 +989,21 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void xor32(Imm32 imm, Register dest) PER_SHARED_ARCH;
- inline void xor32(Imm32 imm, const Address& dest) PER_SHARED_ARCH;
- inline void xor32(const Address& src, Register dest) PER_SHARED_ARCH;
-
- inline void xorPtr(Register src, Register dest) PER_ARCH;
- inline void xorPtr(Imm32 imm, Register dest) PER_ARCH;
-
- inline void and64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-- inline void or64(const Operand& src, Register64 dest) DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-+ inline void or64(const Operand& src, Register64 dest)
-+ DEFINED_ON(x64, mips64, ppc64);
- inline void xor64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- // ===============================================================
- // Swap instructions
-
- // Swap the two lower bytes and sign extend the result to 32-bit.
- inline void byteSwap16SignExtend(Register reg) PER_SHARED_ARCH;
-
- // Swap the two lower bytes and zero extend the result to 32-bit.
-@@ -1020,27 +1027,27 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addPtr(Register src, Register dest) PER_ARCH;
- inline void addPtr(Register src1, Register src2, Register dest)
- DEFINED_ON(arm64);
- inline void addPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void addPtr(Imm32 imm, Register src, Register dest) DEFINED_ON(arm64);
- inline void addPtr(ImmWord imm, Register dest) PER_ARCH;
- inline void addPtr(ImmPtr imm, Register dest);
- inline void addPtr(Imm32 imm, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void addPtr(Imm32 imm, const AbsoluteAddress& dest)
- DEFINED_ON(x86, x64);
- inline void addPtr(const Address& src, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void add64(Register64 src, Register64 dest) PER_ARCH;
- inline void add64(Imm32 imm, Register64 dest) PER_ARCH;
- inline void add64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void add64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void addFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- // Compute dest=SP-imm where dest is a pointer registers and not SP. The
- // offset returned from sub32FromStackPtrWithPatch() must be passed to
- // patchSub32FromStackPtr().
- inline CodeOffset sub32FromStackPtrWithPatch(Register dest) PER_ARCH;
- inline void patchSub32FromStackPtr(CodeOffset offset, Imm32 imm) PER_ARCH;
-@@ -1049,58 +1056,58 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void addConstantDouble(double d, FloatRegister dest) DEFINED_ON(x86);
-
- inline void sub32(const Address& src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Register src, Register dest) PER_SHARED_ARCH;
- inline void sub32(Imm32 imm, Register dest) PER_SHARED_ARCH;
-
- inline void subPtr(Register src, Register dest) PER_ARCH;
- inline void subPtr(Register src, const Address& dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
- inline void subPtr(Imm32 imm, Register dest) PER_ARCH;
- inline void subPtr(ImmWord imm, Register dest) DEFINED_ON(x64);
- inline void subPtr(const Address& addr, Register dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- inline void sub64(Register64 src, Register64 dest) PER_ARCH;
- inline void sub64(Imm64 imm, Register64 dest) PER_ARCH;
- inline void sub64(const Operand& src, Register64 dest)
-- DEFINED_ON(x64, mips64);
-+ DEFINED_ON(x64, mips64, ppc64);
-
- inline void subFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void subDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mul32(Register rhs, Register srcDest) PER_SHARED_ARCH;
-
- inline void mul32(Register src1, Register src2, Register dest, Label* onOver)
- DEFINED_ON(arm64);
-
- inline void mulPtr(Register rhs, Register srcDest) PER_ARCH;
-
- inline void mul64(const Operand& src, const Register64& dest) DEFINED_ON(x64);
- inline void mul64(const Operand& src, const Register64& dest,
-- const Register temp) DEFINED_ON(x64, mips64);
-+ const Register temp) DEFINED_ON(x64, mips64, ppc64);
- inline void mul64(Imm64 imm, const Register64& dest) PER_ARCH;
- inline void mul64(Imm64 imm, const Register64& dest, const Register temp)
-- DEFINED_ON(x86, x64, arm, mips32, mips64);
-+ DEFINED_ON(x86, x64, arm, mips32, mips64, ppc64);
- inline void mul64(const Register64& src, const Register64& dest,
- const Register temp) PER_ARCH;
- inline void mul64(const Register64& src1, const Register64& src2,
- const Register64& dest) DEFINED_ON(arm64);
- inline void mul64(Imm64 src1, const Register64& src2, const Register64& dest)
- DEFINED_ON(arm64);
-
- inline void mulBy3(Register src, Register dest) PER_ARCH;
-
- inline void mulFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void mulDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void mulDoublePtr(ImmPtr imm, Register temp, FloatRegister dest)
-- DEFINED_ON(mips_shared, arm, arm64, x86, x64);
-+ DEFINED_ON(mips_shared, arm, arm64, x86, x64, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // On x86_shared, srcDest must be eax and edx will be clobbered.
- // On ARM, the chip must have hardware division instructions.
- inline void quotient32(Register rhs, Register srcDest,
- bool isUnsigned) PER_SHARED_ARCH;
-@@ -1117,41 +1124,41 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleRemainder32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest is clobbered.
- void flexibleQuotient32(Register rhs, Register srcDest, bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- // Perform an integer division, returning the integer part rounded toward
- // zero. rhs must not be zero, and the division must not overflow. The
- // remainder is stored into the third argument register here.
- //
- // This variant preserves registers, and doesn't require hardware division
- // instructions on ARM (will call out to a runtime routine).
- //
- // rhs is preserved, srdDest and remOutput are clobbered.
- void flexibleDivMod32(Register rhs, Register srcDest, Register remOutput,
- bool isUnsigned,
- const LiveRegisterSet& volatileLiveRegs)
-- DEFINED_ON(mips_shared, arm, arm64, x86_shared);
-+ DEFINED_ON(mips_shared, arm, arm64, x86_shared, ppc64);
-
- inline void divFloat32(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
- inline void divDouble(FloatRegister src, FloatRegister dest) PER_SHARED_ARCH;
-
- inline void inc64(AbsoluteAddress dest) PER_ARCH;
-
- inline void neg32(Register reg) PER_SHARED_ARCH;
- inline void neg64(Register64 reg) PER_ARCH;
-@@ -1342,17 +1349,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // temp may be invalid only if the chip has the POPCNT instruction.
- inline void popcnt64(Register64 src, Register64 dest, Register temp) PER_ARCH;
-
- // ===============================================================
- // Condition functions
-
- template <typename T1, typename T2>
- inline void cmp32Set(Condition cond, T1 lhs, T2 rhs, Register dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
-
- template <typename T1, typename T2>
- inline void cmpPtrSet(Condition cond, T1 lhs, T2 rhs, Register dest) PER_ARCH;
-
- // ===============================================================
- // Branch functions
-
- template <class L>
-@@ -1367,34 +1374,34 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branch32(Condition cond, const Address& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branch32(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branch32(Condition cond, const AbsoluteAddress& lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branch32(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) DEFINED_ON(arm, x86_shared);
- inline void branch32(Condition cond, const BaseIndex& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branch32(Condition cond, const Operand& lhs, Register rhs,
- Label* label) DEFINED_ON(x86_shared);
- inline void branch32(Condition cond, const Operand& lhs, Imm32 rhs,
- Label* label) DEFINED_ON(x86_shared);
-
- inline void branch32(Condition cond, wasm::SymbolicAddress lhs, Imm32 rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // The supported condition are Equal, NotEqual, LessThan(orEqual),
- // GreaterThan(orEqual), Below(orEqual) and Above(orEqual). When a fail label
- // is not defined it will fall through to next instruction, else jump to the
- // fail label.
- inline void branch64(Condition cond, Register64 lhs, Imm64 val,
- Label* success, Label* fail = nullptr) PER_ARCH;
- inline void branch64(Condition cond, Register64 lhs, Register64 rhs,
-@@ -1433,32 +1440,32 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchPtr(Condition cond, const BaseIndex& lhs, ImmWord rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchPtr(Condition cond, const BaseIndex& lhs, Register rhs,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs,
- Register rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchPtr(Condition cond, const AbsoluteAddress& lhs, ImmWord rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchPtr(Condition cond, wasm::SymbolicAddress lhs, Register rhs,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Given a pointer to a GC Cell, retrieve the StoreBuffer pointer from its
- // chunk header, or nullptr if it is in the tenured heap.
- void loadStoreBuffer(Register ptr, Register buffer) PER_ARCH;
-
- void branchPtrInNurseryChunk(Condition cond, Register ptr, Register temp,
- Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- void branchPtrInNurseryChunk(Condition cond, const Address& address,
- Register temp, Label* label) DEFINED_ON(x86);
- void branchValueIsNurseryCell(Condition cond, const Address& address,
- Register temp, Label* label) PER_ARCH;
- void branchValueIsNurseryCell(Condition cond, ValueOperand value,
- Register temp, Label* label) PER_ARCH;
-
- // This function compares a Value (lhs) which is having a private pointer
-@@ -1470,36 +1477,36 @@ class MacroAssembler : public MacroAssemblerSpecific {
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- // Truncate a double/float32 to int32 and when it doesn't fit an int32 it will
- // jump to the failure label. This particular variant is allowed to return the
- // value module 2**32, which isn't implemented on all architectures. E.g. the
- // x64 variants will do this only in the int64_t range.
- inline void branchTruncateFloat32MaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleMaybeModUint32(FloatRegister src,
- Register dest, Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Truncate a double/float32 to intptr and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
- inline void branchTruncateDoubleToPtr(FloatRegister src, Register dest,
- Label* fail) DEFINED_ON(x86, x64);
-
- // Truncate a double/float32 to int32 and when it doesn't fit jump to the
- // failure label.
- inline void branchTruncateFloat32ToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void branchTruncateDoubleToInt32(FloatRegister src, Register dest,
- Label* fail)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void branchDouble(DoubleCondition cond, FloatRegister lhs,
- FloatRegister rhs, Label* label) PER_SHARED_ARCH;
-
- inline void branchDoubleNotInInt64Range(Address src, Register temp,
- Label* fail);
- inline void branchDoubleNotInUInt64Range(Address src, Register temp,
- Label* fail);
-@@ -1543,17 +1550,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- L label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTest32(Condition cond, Register lhs, Imm32 rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const Address& lhs, Imm32 rhh,
- Label* label) PER_SHARED_ARCH;
- inline void branchTest32(Condition cond, const AbsoluteAddress& lhs,
- Imm32 rhs, Label* label)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- template <class L>
- inline void branchTestPtr(Condition cond, Register lhs, Register rhs,
- L label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, Register lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestPtr(Condition cond, const Address& lhs, Imm32 rhs,
- Label* label) PER_SHARED_ARCH;
-@@ -1689,17 +1696,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- // Perform a type-test on a tag of a Value (32bits boxing), or the tagged
- // value (64bits boxing).
- inline void branchTestUndefined(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, Register tag, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestNumber(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, Register tag,
- Label* label) PER_SHARED_ARCH;
-@@ -1721,106 +1728,106 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // BaseIndex and ValueOperand variants clobber the ScratchReg on x64.
- // All Variants clobber the ScratchReg on arm64.
- inline void branchTestUndefined(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestUndefined(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestInt32(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestInt32(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestDouble(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestDouble(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNumber(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBoolean(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBoolean(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestString(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestString(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestSymbol(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestSymbol(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestBigInt(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBigInt(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestNull(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestNull(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Clobbers the ScratchReg on x64.
- inline void branchTestObject(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestObject(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestGCThing(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestGCThing(Condition cond, const ValueOperand& value,
- Label* label) PER_SHARED_ARCH;
-
- inline void branchTestPrimitive(Condition cond, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& address,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestMagic(Condition cond, const BaseIndex& address,
- Label* label) PER_SHARED_ARCH;
- template <class L>
- inline void branchTestMagic(Condition cond, const ValueOperand& value,
- L label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- inline void branchTestMagic(Condition cond, const Address& valaddr,
- JSWhyMagic why, Label* label) PER_ARCH;
-
- inline void branchTestMagicValue(Condition cond, const ValueOperand& val,
- JSWhyMagic why, Label* label);
-
- void branchTestValue(Condition cond, const ValueOperand& lhs,
-@@ -1828,42 +1835,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- inline void branchTestValue(Condition cond, const BaseIndex& lhs,
- const ValueOperand& rhs, Label* label) PER_ARCH;
-
- // Checks if given Value is evaluated to true or false in a condition.
- // The type of the value should match the type of the method.
- inline void branchTestInt32Truthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestDoubleTruthy(bool truthy, FloatRegister reg,
- Label* label) PER_SHARED_ARCH;
- inline void branchTestBooleanTruthy(bool truthy, const ValueOperand& value,
- Label* label) PER_ARCH;
- inline void branchTestStringTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
- inline void branchTestBigIntTruthy(bool truthy, const ValueOperand& value,
- Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- // Create an unconditional branch to the address given as argument.
- inline void branchToComputedAddress(const BaseIndex& address) PER_ARCH;
-
- private:
- template <typename T, typename S, typename L>
- inline void branchPtrImpl(Condition cond, const T& lhs, const S& rhs, L label)
- DEFINED_ON(x86_shared);
-
- void branchPtrInNurseryChunkImpl(Condition cond, Register ptr, Label* label)
- DEFINED_ON(x86);
- template <typename T>
- void branchValueIsNurseryCellImpl(Condition cond, const T& value,
- Register temp, Label* label)
-- DEFINED_ON(arm64, x64, mips64);
-+ DEFINED_ON(arm64, x64, mips64, ppc64);
-
- template <typename T>
- inline void branchTestUndefinedImpl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
- inline void branchTestInt32Impl(Condition cond, const T& t, Label* label)
- DEFINED_ON(arm, arm64, x86_shared);
- template <typename T>
-@@ -1923,116 +1930,116 @@ class MacroAssembler : public MacroAssemblerSpecific {
- inline void fallibleUnboxString(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxSymbol(const T& src, Register dest, Label* fail);
- template <typename T>
- inline void fallibleUnboxBigInt(const T& src, Register dest, Label* fail);
-
- inline void cmp32Move32(Condition cond, Register lhs, Register rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Move32(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, Register rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmpPtrMovePtr(Condition cond, Register lhs, const Address& rhs,
- Register src, Register dest) PER_ARCH;
-
- inline void cmp32Load32(Condition cond, Register lhs, const Address& rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32Load32(Condition cond, Register lhs, Register rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- inline void cmp32LoadPtr(Condition cond, const Address& lhs, Imm32 rhs,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void cmp32MovePtr(Condition cond, Register lhs, Imm32 rhs,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32LoadPtr(Condition cond, const Address& addr, Imm32 mask,
- const Address& src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void test32MovePtr(Condition cond, const Address& addr, Imm32 mask,
- Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Conditional move for Spectre mitigations.
- inline void spectreMovePtr(Condition cond, Register src, Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // Zeroes dest if the condition is true.
- inline void spectreZeroRegister(Condition cond, Register scratch,
- Register dest)
-- DEFINED_ON(arm, arm64, mips_shared, x86_shared);
-+ DEFINED_ON(arm, arm64, mips_shared, x86_shared, ppc64);
-
- // Performs a bounds check and zeroes the index register if out-of-bounds
- // (to mitigate Spectre).
- private:
- inline void spectreBoundsCheck32(Register index, const Operand& length,
- Register maybeScratch, Label* failure)
- DEFINED_ON(x86);
-
- public:
- inline void spectreBoundsCheck32(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheck32(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- inline void spectreBoundsCheckPtr(Register index, Register length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
- inline void spectreBoundsCheckPtr(Register index, const Address& length,
- Register maybeScratch, Label* failure)
-- DEFINED_ON(arm, arm64, mips_shared, x86, x64);
-+ DEFINED_ON(arm, arm64, mips_shared, x86, x64, ppc64);
-
- // ========================================================================
- // Canonicalization primitives.
- inline void canonicalizeDouble(FloatRegister reg);
- inline void canonicalizeDoubleIfDeterministic(FloatRegister reg);
-
- inline void canonicalizeFloat(FloatRegister reg);
- inline void canonicalizeFloatIfDeterministic(FloatRegister reg);
-
- public:
- // ========================================================================
- // Memory access primitives.
- inline void storeUncanonicalizedDouble(FloatRegister src, const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedDouble(FloatRegister src, const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeDouble(FloatRegister src, const T& dest);
-
- template <class T>
- inline void boxDouble(FloatRegister src, const T& dest);
-
- using MacroAssemblerSpecific::boxDouble;
-
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Address& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const BaseIndex& dest)
-- DEFINED_ON(x86_shared, arm, arm64, mips32, mips64);
-+ DEFINED_ON(x86_shared, arm, arm64, mips32, mips64, ppc64);
- inline void storeUncanonicalizedFloat32(FloatRegister src,
- const Operand& dest)
- DEFINED_ON(x86_shared);
-
- template <class T>
- inline void storeFloat32(FloatRegister src, const T& dest);
-
- template <typename T>
-@@ -3470,20 +3477,20 @@ class MacroAssembler : public MacroAssemblerSpecific {
- DEFINED_ON(x86, x64);
-
- public:
- // ========================================================================
- // Convert floating point.
-
- // temp required on x86 and x64; must be undefined on mips64.
- void convertUInt64ToFloat32(Register64 src, FloatRegister dest, Register temp)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- void convertInt64ToFloat32(Register64 src, FloatRegister dest)
-- DEFINED_ON(arm64, mips64, x64, x86);
-+ DEFINED_ON(arm64, mips64, x64, x86, ppc64);
-
- bool convertUInt64ToDoubleNeedsTemp() PER_ARCH;
-
- // temp required when convertUInt64ToDoubleNeedsTemp() returns true.
- void convertUInt64ToDouble(Register64 src, FloatRegister dest,
- Register temp) PER_ARCH;
-
- void convertInt64ToDouble(Register64 src, FloatRegister dest) PER_ARCH;
-@@ -3514,29 +3521,29 @@ class MacroAssembler : public MacroAssemblerSpecific {
- //
- // On 32-bit systems for both wasm and asm.js, and on 64-bit systems for
- // asm.js, heap lengths are limited to 2GB. On 64-bit systems for wasm,
- // 32-bit heap lengths are limited to 4GB, and 64-bit heap lengths will be
- // limited to something much larger.
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Register boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck32(Condition cond, Register index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm, arm64, mips32, mips64, x86_shared);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x86_shared, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Register64 boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- void wasmBoundsCheck64(Condition cond, Register64 index,
- Address boundsCheckLimit, Label* label)
-- DEFINED_ON(arm64, mips64, x64);
-+ DEFINED_ON(arm64, mips64, x64, ppc64);
-
- // Each wasm load/store instruction appends its own wasm::Trap::OutOfBounds.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- AnyRegister out) DEFINED_ON(x86, x64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Operand srcAddr,
- Register64 out) DEFINED_ON(x86, x64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Operand dstAddr) DEFINED_ON(x86, x64);
-@@ -3546,26 +3553,26 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // For all the ARM/MIPS wasmLoad and wasmStore functions below, `ptr`
- // MUST equal `ptrScratch`, and that register will be updated based on
- // conditions listed below (where it is only mentioned as `ptr`).
-
- // `ptr` will be updated if access.offset() != 0 or access.type() ==
- // Scalar::Int64.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, AnyRegister output)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmLoadI64(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, Register ptrScratch, Register64 output)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
- void wasmStore(const wasm::MemoryAccessDesc& access, AnyRegister value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips_shared);
-+ DEFINED_ON(arm, mips_shared, ppc64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr, Register ptrScratch)
-- DEFINED_ON(arm, mips32, mips64);
-+ DEFINED_ON(arm, mips32, mips64, ppc64);
-
- // These accept general memoryBase + ptr + offset (in `access`); the offset is
- // always smaller than the guard region. They will insert an additional add
- // if the offset is nonzero, and of course that add may require a temporary
- // register for the offset if the offset is large, and instructions to set it
- // up.
- void wasmLoad(const wasm::MemoryAccessDesc& access, Register memoryBase,
- Register ptr, AnyRegister output) DEFINED_ON(arm64);
-@@ -3575,100 +3582,100 @@ class MacroAssembler : public MacroAssemblerSpecific {
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
- void wasmStoreI64(const wasm::MemoryAccessDesc& access, Register64 value,
- Register memoryBase, Register ptr) DEFINED_ON(arm64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoad(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr, Register ptrScratch,
- Register output, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedLoadFP(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, FloatRegister output,
- Register tmp1, Register tmp2, Register tmp3)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedLoadI64(const wasm::MemoryAccessDesc& access,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register64 output,
-- Register tmp) DEFINED_ON(mips32, mips64);
-+ Register tmp) DEFINED_ON(mips32, mips64, ppc64);
-
- // MIPS: `ptr` will always be updated.
- void wasmUnalignedStore(const wasm::MemoryAccessDesc& access, Register value,
- Register memoryBase, Register ptr,
- Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreFP(const wasm::MemoryAccessDesc& access,
- FloatRegister floatValue, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // `ptr` will always be updated.
- void wasmUnalignedStoreI64(const wasm::MemoryAccessDesc& access,
- Register64 value, Register memoryBase,
- Register ptr, Register ptrScratch, Register tmp)
-- DEFINED_ON(mips32, mips64);
-+ DEFINED_ON(mips32, mips64, ppc64);
-
- // wasm specific methods, used in both the wasm baseline compiler and ion.
-
- // The truncate-to-int32 methods do not bind the rejoin label; clients must
- // do so if oolWasmTruncateCheckF64ToI32() can jump to it.
- void wasmTruncateDoubleToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateDoubleToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF64ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToUInt32(FloatRegister input, Register output,
- bool isSaturating, Label* oolEntry) PER_ARCH;
- void wasmTruncateFloat32ToInt32(FloatRegister input, Register output,
- bool isSaturating,
- Label* oolEntry) PER_SHARED_ARCH;
- void oolWasmTruncateCheckF32ToI32(FloatRegister input, Register output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // The truncate-to-int64 methods will always bind the `oolRejoin` label
- // after the last emitted instruction.
- void wasmTruncateDoubleToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateDoubleToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF64ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- void wasmTruncateFloat32ToInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void wasmTruncateFloat32ToUInt64(FloatRegister input, Register64 output,
- bool isSaturating, Label* oolEntry,
- Label* oolRejoin, FloatRegister tempDouble)
-- DEFINED_ON(arm64, x86, x64, mips64);
-+ DEFINED_ON(arm64, x86, x64, mips64, ppc64);
- void oolWasmTruncateCheckF32ToI64(FloatRegister input, Register64 output,
- TruncFlags flags, wasm::BytecodeOffset off,
- Label* rejoin)
-- DEFINED_ON(arm, arm64, x86_shared, mips_shared);
-+ DEFINED_ON(arm, arm64, x86_shared, mips_shared, ppc64);
-
- // This function takes care of loading the callee's TLS and pinned regs but
- // it is the caller's responsibility to save/restore TLS or pinned regs.
- CodeOffset wasmCallImport(const wasm::CallSiteDesc& desc,
- const wasm::CalleeDesc& callee);
-
- // WasmTableCallIndexReg must contain the index of the indirect call.
- CodeOffset wasmCallIndirect(const wasm::CallSiteDesc& desc,
-@@ -3735,72 +3742,72 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void compareExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `expected` and `output` must be edx:eax; `replacement` is ecx:ebx.
- // x64: `output` must be rax.
- // ARM: Registers must be distinct; `replacement` and `output` must be
- // (even,odd) pairs.
-
- void compareExchange64(const Synchronization& sync, const Address& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void compareExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 expected, Register64 replacement,
- Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Exchange with memory. Return the value initially in memory.
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchange(Scalar::Type type, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // x86: `value` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `value` and `output` must be distinct and (even,odd) pairs.
- // ARM64: `value` and `output` must be distinct.
-
- void atomicExchange64(const Synchronization& sync, const Address& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- void atomicExchange64(const Synchronization& sync, const BaseIndex& mem,
- Register64 value, Register64 output)
-- DEFINED_ON(arm, arm64, x64, x86, mips64);
-+ DEFINED_ON(arm, arm64, x64, x86, mips64, ppc64);
-
- // Read-modify-write with memory. Return the value in memory before the
- // operation.
- //
- // x86-shared:
- // For 8-bit operations, `value` and `output` must have a byte subregister.
- // For Add and Sub, `temp` must be invalid.
- // For And, Or, and Xor, `output` must be eax and `temp` must have a byte
-@@ -3826,44 +3833,44 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp, Register output) DEFINED_ON(x86_shared);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOp(Scalar::Type type, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- // x86:
- // `temp` must be ecx:ebx; `output` must be edx:eax.
- // x64:
- // For Add and Sub, `temp` is ignored.
- // For And, Or, and Xor, `output` must be rax.
- // ARM:
- // `temp` and `output` must be (even,odd) pairs and distinct from `value`.
- // ARM64:
- // Registers `value`, `temp`, and `output` must all differ.
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp,
-- Register64 output) DEFINED_ON(arm, arm64, x64, mips64);
-+ Register64 output) DEFINED_ON(arm, arm64, x64, mips64, ppc64);
-
- void atomicFetchOp64(const Synchronization& sync, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- // x64:
- // `value` can be any register.
- // ARM:
-@@ -3871,24 +3878,24 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM64:
- // Registers `value` and `temp` must differ.
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const Address& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem) DEFINED_ON(x64);
-
- void atomicEffectOp64(const Synchronization& sync, AtomicOp op,
- Register64 value, const BaseIndex& mem, Register64 temp)
-- DEFINED_ON(arm, arm64, mips64);
-+ DEFINED_ON(arm, arm64, mips64, ppc64);
-
- // 64-bit atomic load. On 64-bit systems, use regular load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `output` must be (even,odd) pair.
-
- void atomicLoad64(const Synchronization& sync, const Address& mem,
-@@ -3930,43 +3937,43 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmCompareExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value, Register output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const Address& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicExchange(const wasm::MemoryAccessDesc& access,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp,
- Register output) DEFINED_ON(arm, arm64, x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const Address& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-@@ -3977,23 +3984,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp,
- Register output) DEFINED_ON(x86_shared);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register valueTemp,
- Register offsetTemp, Register maskTemp,
-- Register output) DEFINED_ON(mips_shared);
-+ Register output) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicFetchOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- // Read-modify-write with memory. Return no value.
- //
- // MIPS: `valueTemp`, `offsetTemp` and `maskTemp` must be defined for 8-bit
- // and 16-bit wide operations.
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem, Register temp)
-@@ -4009,22 +4016,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Imm32 value, const BaseIndex& mem, Register temp)
- DEFINED_ON(x86_shared);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void wasmAtomicEffectOp(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- // 64-bit wide operations.
-
- // 64-bit atomic load. On 64-bit systems, use regular wasm load with
- // Synchronization::Load, not this method.
- //
- // x86: `temp` must be ecx:ebx; `output` must be edx:eax.
- // ARM: `temp` should be invalid; `output` must be (even,odd) pair.
-@@ -4074,22 +4081,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // ARM: Registers must be distinct; `temp` and `output` must be (even,odd)
- // pairs.
- // MIPS: Registers must be distinct.
- // MIPS32: `temp` should be invalid.
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const Address& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- Register64 value, const BaseIndex& mem,
- Register64 temp, Register64 output)
-- DEFINED_ON(arm, arm64, mips32, mips64, x64);
-+ DEFINED_ON(arm, arm64, mips32, mips64, x64, ppc64);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const Address& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-
- void wasmAtomicFetchOp64(const wasm::MemoryAccessDesc& access, AtomicOp op,
- const Address& value, const BaseIndex& mem,
- Register64 temp, Register64 output) DEFINED_ON(x86);
-@@ -4131,42 +4138,42 @@ class MacroAssembler : public MacroAssemblerSpecific {
- const BaseIndex& mem, Register expected,
- Register replacement, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void compareExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register expected,
- Register replacement, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value, Register temp,
- AnyRegister output) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const Address& mem, Register value, Register valueTemp,
- Register offsetTemp, Register maskTemp, Register temp,
-- AnyRegister output) DEFINED_ON(mips_shared);
-+ AnyRegister output) DEFINED_ON(mips_shared, ppc64);
-
- void atomicExchangeJS(Scalar::Type arrayType, const Synchronization& sync,
- const BaseIndex& mem, Register value,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
-@@ -4182,23 +4189,23 @@ class MacroAssembler : public MacroAssemblerSpecific {
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp1, Register temp2, AnyRegister output)
- DEFINED_ON(x86_shared);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicFetchOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
- Register maskTemp, Register temp, AnyRegister output)
-- DEFINED_ON(mips_shared);
-+ DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register temp) DEFINED_ON(arm, arm64, x86_shared);
-@@ -4209,22 +4216,22 @@ class MacroAssembler : public MacroAssemblerSpecific {
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Imm32 value, const BaseIndex& mem,
- Register temp) DEFINED_ON(x86_shared);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const Address& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicEffectOpJS(Scalar::Type arrayType, const Synchronization& sync,
- AtomicOp op, Register value, const BaseIndex& mem,
- Register valueTemp, Register offsetTemp,
-- Register maskTemp) DEFINED_ON(mips_shared);
-+ Register maskTemp) DEFINED_ON(mips_shared, ppc64);
-
- void atomicIsLockFreeJS(Register value, Register output);
-
- // ========================================================================
- // Spectre Mitigations.
- //
- // Spectre attacks are side-channel attacks based on cache pollution or
- // slow-execution of some instructions. We have multiple spectre mitigations
-@@ -4803,17 +4810,17 @@ class MacroAssembler : public MacroAssemblerSpecific {
- // StackPointer manipulation functions.
- // On ARM64, the StackPointer is implemented as two synchronized registers.
- // Code shared across platforms must use these functions to be valid.
- template <typename T>
- inline void addToStackPtr(T t);
- template <typename T>
- inline void addStackPtrTo(T t);
-
-- void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64);
-+ void subFromStackPtr(Imm32 imm32) DEFINED_ON(mips32, mips64, arm, x86, x64, ppc64);
- void subFromStackPtr(Register reg);
-
- template <typename T>
- void subStackPtrFrom(T t) {
- subPtr(getStackPointer(), t);
- }
-
- template <typename T>
-diff --git a/js/src/jit/MoveEmitter.h b/js/src/jit/MoveEmitter.h
-index 6c62c0561a..30ee4b61a5 100644
---- a/js/src/jit/MoveEmitter.h
-+++ b/js/src/jit/MoveEmitter.h
-@@ -12,15 +12,17 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/MoveEmitter-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/MoveEmitter-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/MoveEmitter-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/MoveEmitter-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/MoveEmitter-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/MoveEmitter-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- #endif /* jit_MoveEmitter_h */
-diff --git a/js/src/jit/Registers.h b/js/src/jit/Registers.h
-index 67c8661004..ef49df83e5 100644
---- a/js/src/jit/Registers.h
-+++ b/js/src/jit/Registers.h
-@@ -15,16 +15,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/Architecture-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/Architecture-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/Architecture-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/Architecture-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Architecture-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/Architecture-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {
-diff --git a/js/src/jit/SharedICHelpers-inl.h b/js/src/jit/SharedICHelpers-inl.h
-index 901c80cdd8..fd4a27d8bb 100644
---- a/js/src/jit/SharedICHelpers-inl.h
-+++ b/js/src/jit/SharedICHelpers-inl.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64-inl.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm-inl.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64-inl.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared-inl.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64-inl.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none-inl.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICHelpers.h b/js/src/jit/SharedICHelpers.h
-index 563cae3ccf..737ca1d5a5 100644
---- a/js/src/jit/SharedICHelpers.h
-+++ b/js/src/jit/SharedICHelpers.h
-@@ -12,16 +12,18 @@
- #elif defined(JS_CODEGEN_X64)
- # include "jit/x64/SharedICHelpers-x64.h"
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICHelpers-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICHelpers-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/SharedICHelpers-mips-shared.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICHelpers-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICHelpers-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/SharedICRegisters.h b/js/src/jit/SharedICRegisters.h
-index c87e5f8408..76239d5dde 100644
---- a/js/src/jit/SharedICRegisters.h
-+++ b/js/src/jit/SharedICRegisters.h
-@@ -14,16 +14,18 @@
- #elif defined(JS_CODEGEN_ARM)
- # include "jit/arm/SharedICRegisters-arm.h"
- #elif defined(JS_CODEGEN_ARM64)
- # include "jit/arm64/SharedICRegisters-arm64.h"
- #elif defined(JS_CODEGEN_MIPS32)
- # include "jit/mips32/SharedICRegisters-mips32.h"
- #elif defined(JS_CODEGEN_MIPS64)
- # include "jit/mips64/SharedICRegisters-mips64.h"
-+#elif defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/SharedICRegisters-ppc64.h"
- #elif defined(JS_CODEGEN_NONE)
- # include "jit/none/SharedICRegisters-none.h"
- #else
- # error "Unknown architecture!"
- #endif
-
- namespace js {
- namespace jit {} // namespace jit
-diff --git a/js/src/jit/moz.build b/js/src/jit/moz.build
-index f50d86fc44..82cddd07af 100644
---- a/js/src/jit/moz.build
-+++ b/js/src/jit/moz.build
-@@ -227,17 +227,29 @@ elif CONFIG["JS_CODEGEN_MIPS32"] or CONFIG["JS_CODEGEN_MIPS64"]:
- "mips64/CodeGenerator-mips64.cpp",
- "mips64/Lowering-mips64.cpp",
- "mips64/MacroAssembler-mips64.cpp",
- "mips64/MoveEmitter-mips64.cpp",
- "mips64/Trampoline-mips64.cpp",
- ]
- if CONFIG["JS_SIMULATOR_MIPS64"]:
- UNIFIED_SOURCES += ["mips64/Simulator-mips64.cpp"]
--
-+elif CONFIG["JS_CODEGEN_PPC64"]:
-+ lir_inputs += ["ppc64/LIR-ppc64.h"]
-+ UNIFIED_SOURCES += [
-+ "ppc64/Architecture-ppc64.cpp",
-+ "ppc64/Assembler-ppc64.cpp",
-+ "ppc64/Bailouts-ppc64.cpp",
-+ "ppc64/CodeGenerator-ppc64.cpp",
-+ "ppc64/Lowering-ppc64.cpp",
-+ "ppc64/MacroAssembler-ppc64.cpp",
-+ "ppc64/MoveEmitter-ppc64.cpp",
-+ "ppc64/Trampoline-ppc64.cpp",
-+ "shared/AtomicOperations-shared-jit.cpp",
-+ ]
-
- # Generate jit/MIROpsGenerated.h from jit/MIROps.yaml
- GeneratedFile(
- "MIROpsGenerated.h",
- script="GenerateMIRFiles.py",
- entry_point="generate_mir_header",
- inputs=["MIROps.yaml"],
- )
-diff --git a/js/src/jit/shared/Assembler-shared.h b/js/src/jit/shared/Assembler-shared.h
-index dfb2bcb6b8..69ba759d42 100644
---- a/js/src/jit/shared/Assembler-shared.h
-+++ b/js/src/jit/shared/Assembler-shared.h
-@@ -20,23 +20,24 @@
- #include "jit/Registers.h"
- #include "jit/RegisterSets.h"
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "vm/HelperThreads.h"
- #include "vm/NativeObject.h"
- #include "wasm/WasmTypes.h"
-
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- // Push return addresses callee-side.
- # define JS_USE_LINK_REGISTER
- #endif
-
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-- defined(JS_CODEGEN_ARM64)
-+ defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_PPC64)
- // JS_CODELABEL_LINKMODE gives labels additional metadata
- // describing how Bind() should patch them.
- # define JS_CODELABEL_LINKMODE
- #endif
-
- namespace js {
- namespace jit {
-
-diff --git a/js/src/jit/shared/AtomicOperations-shared-jit.cpp b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-index 79463f118b..7c8eeaf89e 100644
---- a/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-+++ b/js/src/jit/shared/AtomicOperations-shared-jit.cpp
-@@ -133,16 +133,38 @@ static constexpr Register AtomicTemp = edx;
- // 64-bit registers for cmpxchg8b. ValReg/Val2Reg/Temp are not used in this
- // case.
-
- static constexpr Register64 AtomicValReg64(edx, eax);
- static constexpr Register64 AtomicVal2Reg64(ecx, ebx);
-
- // AtomicReturnReg64 is unused on x86.
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+// Selected registers match the argument registers, except that the Ptr is not
-+// in IntArgReg0 so as not to conflict with the result register.
-+
-+static const LiveRegisterSet AtomicNonVolatileRegs;
-+
-+static constexpr Register AtomicPtrReg = IntArgReg4;
-+static constexpr Register AtomicPtr2Reg = IntArgReg1;
-+static constexpr Register AtomicValReg = IntArgReg1;
-+static constexpr Register64 AtomicValReg64(IntArgReg1);
-+static constexpr Register AtomicVal2Reg = IntArgReg2;
-+static constexpr Register64 AtomicVal2Reg64(IntArgReg2);
-+static constexpr Register AtomicTemp = IntArgReg3;
-+static constexpr Register AtomicTemp2 = IntArgReg5;
-+static constexpr Register AtomicTemp3 = IntArgReg6;
-+static constexpr Register64 AtomicTemp64(IntArgReg3);
-+static constexpr Register64 AtomicTemp64_2(IntArgReg5);
-+static constexpr Register64 AtomicTemp64_3(IntArgReg6);
-+
-+static constexpr Register64 AtomicReturnReg64 = ReturnReg64;
-+
- #else
- # error "Unsupported platform"
- #endif
-
- // These are useful shorthands and hide the meaningless uint/int distinction.
-
- static constexpr Scalar::Type SIZE8 = Scalar::Uint8;
- static constexpr Scalar::Type SIZE16 = Scalar::Uint16;
-@@ -248,31 +270,37 @@ static uint32_t GenPrologue(MacroAssembler& masm, ArgIterator* iter) {
- uint32_t start = masm.currentOffset();
- masm.PushRegsInMask(AtomicNonVolatileRegs);
- #if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- // The return address is among the nonvolatile registers, if pushed at all.
- iter->argBase = masm.framePushed();
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // The return address is pushed separately.
- iter->argBase = sizeof(void*) + masm.framePushed();
-+#elif defined(JS_CODEGEN_PPC64)
-+// XXX
-+ // The return address is in LR (an SPR); it's not (probably) on the stack.
-+ iter->argBase = masm.framePushed();
- #else
- # error "Unsupported platform"
- #endif
- return start;
- }
-
- static void GenEpilogue(MacroAssembler& masm) {
- masm.PopRegsInMask(AtomicNonVolatileRegs);
- MOZ_ASSERT(masm.framePushed() == 0);
- #if defined(JS_CODEGEN_ARM64)
- masm.Ret();
- #elif defined(JS_CODEGEN_ARM)
- masm.mov(lr, pc);
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- masm.ret();
-+#elif defined(JS_CODEGEN_PPC64)
-+ masm.as_blr();
- #endif
- }
-
- #ifndef JS_64BIT
- static uint32_t GenNop(MacroAssembler& masm) {
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenEpilogue(masm);
-@@ -414,21 +442,31 @@ static uint32_t GenCmpxchg(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
- GenGprArg(masm, MIRType::Int32, &iter, AtomicVal2Reg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.compareExchange(size, sync, addr, AtomicValReg, AtomicVal2Reg,
- ReturnReg);
-+#endif
- break;
- case SIZE64:
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- GenGpr64Arg(masm, &iter, AtomicVal2Reg64);
- #if defined(JS_CODEGEN_X86)
- static_assert(AtomicValReg64 == Register64(edx, eax));
- static_assert(AtomicVal2Reg64 == Register64(ecx, ebx));
-
-@@ -453,19 +491,29 @@ static uint32_t GenExchange(MacroAssembler& masm, Scalar::Type size,
- ArgIterator iter;
- uint32_t start = GenPrologue(masm, &iter);
- GenGprArg(masm, MIRType::Pointer, &iter, AtomicPtrReg);
-
- Address addr(AtomicPtrReg, 0);
- switch (size) {
- case SIZE8:
- case SIZE16:
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ AtomicTemp, AtomicTemp2, AtomicTemp3, ReturnReg);
-+ break;
-+#endif
- case SIZE32:
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicExchange(size, sync, addr, AtomicValReg,
-+ InvalidReg, InvalidReg, InvalidReg, ReturnReg);
-+#else
- masm.atomicExchange(size, sync, addr, AtomicValReg, ReturnReg);
-+#endif
- break;
- case SIZE64:
- #if defined(JS_64BIT)
- GenGpr64Arg(masm, &iter, AtomicValReg64);
- masm.atomicExchange64(sync, addr, AtomicValReg64, AtomicReturnReg64);
- break;
- #else
- MOZ_CRASH("64-bit atomic exchange not available on this platform");
-@@ -492,17 +540,22 @@ static uint32_t GenFetchOp(MacroAssembler& masm, Scalar::Type size, AtomicOp op,
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- Register tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register::Invalid()
- : AtomicTemp;
- #else
- Register tmp = AtomicTemp;
- #endif
- GenGprArg(masm, MIRType::Int32, &iter, AtomicValReg);
-+#if defined(JS_CODEGEN_PPC64)
-+ masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, AtomicTemp2,
-+ AtomicTemp3, ReturnReg);
-+#else
- masm.atomicFetchOp(size, sync, op, AtomicValReg, addr, tmp, ReturnReg);
-+#endif
- break;
- }
- case SIZE64: {
- #if defined(JS_64BIT)
- # if defined(JS_CODEGEN_X64)
- Register64 tmp = op == AtomicFetchAddOp || op == AtomicFetchSubOp
- ? Register64::Invalid()
- : AtomicTemp64;
-@@ -636,16 +689,19 @@ static bool UnalignedAccessesAreOK() {
- #endif
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return true;
- #elif defined(JS_CODEGEN_ARM)
- return !HasAlignmentFault();
- #elif defined(JS_CODEGEN_ARM64)
- // This is not necessarily true but it's the best guess right now.
- return true;
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We'd sure like to avoid it, even though it works.
-+ return false;
- #else
- # error "Unsupported platform"
- #endif
- }
-
- void AtomicMemcpyDownUnsynchronized(uint8_t* dest, const uint8_t* src,
- size_t nbytes) {
- const uint8_t* lim = src + nbytes;
-diff --git a/js/src/jsapi-tests/testJitABIcalls.cpp b/js/src/jsapi-tests/testJitABIcalls.cpp
-index 02b67da3ca..bd45389b21 100644
---- a/js/src/jsapi-tests/testJitABIcalls.cpp
-+++ b/js/src/jsapi-tests/testJitABIcalls.cpp
-@@ -653,16 +653,19 @@ class JitABICall final : public JSAPITest, public DefineCheckArgs<Sig> {
- Register base = r8;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS32)
- Register base = t1;
- regs.take(base);
- #elif defined(JS_CODEGEN_MIPS64)
- Register base = t1;
- regs.take(base);
-+#elif defined(JS_CODEGEN_PPC64)
-+ Register base = r0;
-+ regs.take(base);
- #else
- # error "Unknown architecture!"
- #endif
-
- Register setup = regs.takeAny();
-
- this->generateCalls(masm, base, setup);
-
-diff --git a/js/src/jsapi-tests/testsJit.cpp b/js/src/jsapi-tests/testsJit.cpp
-index 069eef43fe..705609df2c 100644
---- a/js/src/jsapi-tests/testsJit.cpp
-+++ b/js/src/jsapi-tests/testsJit.cpp
-@@ -20,16 +20,21 @@ void PrepareJit(js::jit::MacroAssembler& masm) {
- #endif
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Push the link register separately, since it's not a GPR.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PushRegsInMask(save);
- }
-
- // Generate the exit path of the JIT code, which restores every register. Then,
- // make it executable and run it.
-@@ -37,26 +42,35 @@ bool ExecuteJit(JSContext* cx, js::jit::MacroAssembler& masm) {
- using namespace js::jit;
- AllocatableRegisterSet regs(RegisterSet::All());
- LiveRegisterSet save(regs.asLiveSet());
- #if defined(JS_CODEGEN_ARM)
- save.add(js::jit::d15);
- #endif
- #if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- save.add(js::jit::ra);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // We pop after loading the regs.
- #elif defined(JS_USE_LINK_REGISTER)
- save.add(js::jit::lr);
- #endif
- masm.PopRegsInMask(save);
- #if defined(JS_CODEGEN_ARM64)
- // Return using the value popped into x30.
- masm.abiret();
-
- // Reset stack pointer.
- masm.SetStackPointer64(PseudoStackPointer64);
-+#elif defined(JS_CODEGEN_PPC64)
-+ // XXX
-+ // Pop LR and exit.
-+ masm.as_ld(ScratchRegister, StackPointer, 0);
-+ masm.xs_mtlr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, 8);
-+ masm.as_blr();
- #else
- // Exit the JIT-ed code using the ABI return style.
- masm.abiret();
- #endif
-
- if (masm.oom()) {
- return false;
- }
-diff --git a/js/src/util/Poison.h b/js/src/util/Poison.h
-index 8356ca1f00..5eeb111cf8 100644
---- a/js/src/util/Poison.h
-+++ b/js/src/util/Poison.h
-@@ -88,16 +88,18 @@ const uint8_t JS_SCOPE_DATA_TRAILING_NAMES_PATTERN = 0xCC;
- */
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) || \
- defined(JS_CODEGEN_NONE)
- # define JS_SWEPT_CODE_PATTERN 0xED // IN instruction, crashes in user mode.
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- # define JS_SWEPT_CODE_PATTERN 0xA3 // undefined instruction
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- # define JS_SWEPT_CODE_PATTERN 0x01 // undefined instruction
-+#elif defined(JS_CODEGEN_PPC64) || defined(JS_CODEGEN_PPC)
-+# define JS_SWEPT_CODE_PATTERN 0x00 // architecturally defined as illegal
- #else
- # error "JS_SWEPT_CODE_PATTERN not defined for this platform"
- #endif
-
- enum class MemCheckKind : uint8_t {
- // Marks a region as poisoned. Memory sanitizers like ASan will crash when
- // accessing it (both reads and writes).
- MakeNoAccess,
-diff --git a/js/src/wasm/WasmBaselineCompile.cpp b/js/src/wasm/WasmBaselineCompile.cpp
-index 156f3cbbba..ab29f44713 100644
---- a/js/src/wasm/WasmBaselineCompile.cpp
-+++ b/js/src/wasm/WasmBaselineCompile.cpp
-@@ -138,16 +138,19 @@
- #if defined(JS_CODEGEN_MIPS32)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips32/Assembler-mips32.h"
- #endif
- #if defined(JS_CODEGEN_MIPS64)
- # include "jit/mips-shared/Assembler-mips-shared.h"
- # include "jit/mips64/Assembler-mips64.h"
- #endif
-+#if defined(JS_CODEGEN_PPC64)
-+# include "jit/ppc64/Assembler-ppc64.h"
-+#endif
- #include "js/ScalarType.h" // js::Scalar::Type
- #include "util/Memory.h"
- #include "wasm/TypedObject.h"
- #include "wasm/WasmGC.h"
- #include "wasm/WasmGenerator.h"
- #include "wasm/WasmInstance.h"
- #include "wasm/WasmOpIter.h"
- #include "wasm/WasmSignalHandlers.h"
-@@ -288,16 +291,23 @@ static constexpr Register RabaldrScratchI32 = CallTempReg2;
- #endif
-
- #ifdef RABALDR_SCRATCH_F32_ALIASES_F64
- # if !defined(RABALDR_SCRATCH_F32) || !defined(RABALDR_SCRATCH_F64)
- # error "Bad configuration"
- # endif
- #endif
-
-+#ifdef JS_CODEGEN_PPC64
-+# define RABALDR_SCRATCH_I32
-+// We can use all the argregs up, and we don't want the JIT using our own
-+// private scratch registers, so this is the best option of what's left.
-+static constexpr Register RabaldrScratchI32 = r19;
-+#endif
-+
- template <MIRType t>
- struct RegTypeOf {
- #ifdef ENABLE_WASM_SIMD
- static_assert(t == MIRType::Float32 || t == MIRType::Double ||
- t == MIRType::Simd128,
- "Float mask type");
- #else
- static_assert(t == MIRType::Float32 || t == MIRType::Double,
-@@ -550,16 +560,18 @@ struct SpecificRegs {};
- #elif defined(JS_CODEGEN_MIPS32)
- struct SpecificRegs {
- RegI64 abiReturnRegI64;
-
- SpecificRegs() : abiReturnRegI64(ReturnReg64) {}
- };
- #elif defined(JS_CODEGEN_MIPS64)
- struct SpecificRegs {};
-+#elif defined(JS_CODEGEN_PPC64)
-+struct SpecificRegs {};
- #else
- struct SpecificRegs {
- # ifndef JS_64BIT
- RegI64 abiReturnRegI64;
- # endif
-
- SpecificRegs() { MOZ_CRASH("BaseCompiler porting interface: SpecificRegs"); }
- };
-@@ -6038,16 +6050,25 @@ class BaseCompiler final : public BaseCompilerInterface {
- ABIArg argLoc = call->abi.next(MIRType::Int32);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- loadI32(arg, scratch);
- masm.store32(scratch, Address(masm.getStackPointer(),
- argLoc.offsetFromArgBase()));
- } else {
- loadI32(arg, RegI32(argLoc.gpr()));
-+#if JS_CODEGEN_PPC64
-+ // If this is a call to compiled C++, we must ensure that the
-+ // upper 32 bits are clear: addi can sign-extend, which yields
-+ // difficult-to-diagnose bugs when the function expects a uint32_t
-+ // but the register it gets has a residual 64-bit value.
-+ if (call->usesSystemAbi) {
-+ masm.as_rldicl(argLoc.gpr(), argLoc.gpr(), 0, 32);
-+ }
-+#endif
- }
- break;
- }
- case ValType::I64: {
- ABIArg argLoc = call->abi.next(MIRType::Int64);
- if (argLoc.kind() == ABIArg::Stack) {
- ScratchI32 scratch(*this);
- #ifdef JS_PUNBOX64
-@@ -6324,17 +6345,18 @@ class BaseCompiler final : public BaseCompilerInterface {
-
- // Compute the absolute table base pointer into `scratch`, offset by 8
- // to account for the fact that ma_mov read PC+8.
- masm.ma_sub(Imm32(offset + 8), scratch, arm_scratch);
-
- // Jump indirect via table element.
- masm.ma_ldr(DTRAddr(scratch, DtrRegImmShift(switchValue, LSL, 2)), pc,
- Offset, Assembler::Always);
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- ScratchI32 scratch(*this);
- CodeLabel tableCl;
-
- masm.ma_li(scratch, &tableCl);
-
- tableCl.target()->bind(theTable->offset());
- masm.addCodeLabel(tableCl);
-
-@@ -6493,16 +6515,22 @@ class BaseCompiler final : public BaseCompilerInterface {
- # elif defined(JS_CODEGEN_ARM64)
- ARMRegister sd(srcDest.reg, 64);
- ARMRegister r(rhs.reg, 64);
- if (isUnsigned) {
- masm.Udiv(sd, sd, r);
- } else {
- masm.Sdiv(sd, sd, r);
- }
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (isUnsigned) {
-+ masm.as_divdu(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: quotientI64");
- # endif
- masm.bind(&done);
- }
-
- void remainderI64(RegI64 rhs, RegI64 srcDest, RegI64 reserved,
- IsUnsigned isUnsigned, bool isConst, int64_t c) {
-@@ -6544,29 +6572,46 @@ class BaseCompiler final : public BaseCompilerInterface {
- ARMRegister t(temp, 64);
- if (isUnsigned) {
- masm.Udiv(t, sd, r);
- } else {
- masm.Sdiv(t, sd, r);
- }
- masm.Mul(t, t, r);
- masm.Sub(sd, sd, t);
-+# elif defined(JS_CODEGEN_PPC64)
-+ if (js::jit::HasPPCISA3()) {
-+ if (isUnsigned) {
-+ masm.as_modud(srcDest.reg, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_modsd(srcDest.reg, srcDest.reg, rhs.reg);
-+ }
-+ } else {
-+ ScratchI32 temp(*this);
-+ if (isUnsigned) {
-+ masm.as_divdu(temp, srcDest.reg, rhs.reg);
-+ } else {
-+ masm.as_divd(temp, srcDest.reg, rhs.reg);
-+ }
-+ masm.as_mulld(temp, temp, rhs.reg);
-+ masm.as_subf(srcDest.reg, temp, srcDest.reg); // T = B - A
-+ }
- # else
- MOZ_CRASH("BaseCompiler platform hook: remainderI64");
- # endif
- masm.bind(&done);
- }
- #endif // RABALDR_INT_DIV_I64_CALLOUT
-
- RegI32 needRotate64Temp() {
- #if defined(JS_CODEGEN_X86)
- return needI32();
- #elif defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- return RegI32::Invalid();
- #else
- MOZ_CRASH("BaseCompiler platform hook: needRotate64Temp");
- #endif
- }
-
- class OutOfLineTruncateCheckF32OrF64ToI32 : public OutOfLineCode {
- AnyReg src;
-@@ -6869,30 +6914,35 @@ class BaseCompiler final : public BaseCompilerInterface {
- RegI64 ptr64 = fromI32(ptr);
-
- // In principle there may be non-zero bits in the upper bits of the
- // register; clear them.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended (see comment block "64-bit GPRs
- // carrying 32-bit values" in MacroAssembler.h); we already have that.
- masm.assertCanonicalInt32(ptr);
-+# elif defined(JS_CODEGEN_PPC64)
-+ // The canonical value is sign-extended.
-+ masm.as_rldicl(ptr, ptr, 0, 32); // "clrldi"
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
-
- // Any Spectre mitigation will appear to update the ptr64 register.
- masm.wasmBoundsCheck64(
- Assembler::Below, ptr64,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
-
- // Restore the value to the canonical form for a 32-bit value in a
- // 64-bit register and/or the appropriate form for further use in the
- // indexing instruction.
- # if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64)
- // The canonical value is zero-extended; we already have that.
-+# elif defined(JS_CODEGEN_PPC64)
-+ // Leave it zero-extended.
- # else
- MOZ_CRASH("Platform code needed here");
- # endif
- } else {
- masm.wasmBoundsCheck32(
- Assembler::Below, ptr,
- Address(tls, offsetof(TlsData, boundsCheckLimit)), &ok);
- }
-@@ -6903,17 +6953,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- #endif
- masm.wasmTrap(Trap::OutOfBounds, bytecodeOffset());
- masm.bind(&ok);
- }
- }
-
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM) || \
- defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- BaseIndex prepareAtomicMemoryAccess(MemoryAccessDesc* access,
- AccessCheck* check, RegI32 tls,
- RegI32 ptr) {
- MOZ_ASSERT(needTlsForAccess(*check) == tls.isValid());
- prepareMemoryAccess(access, check, tls, ptr);
- return BaseIndex(HeapReg, ptr, TimesOne, access->offset());
- }
- #elif defined(JS_CODEGEN_X86)
-@@ -7001,17 +7051,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- if (dest.tag == AnyReg::I64) {
- MOZ_ASSERT(dest.i64() == specific_.abiReturnRegI64);
- masm.wasmLoadI64(*access, srcAddr, dest.i64());
- } else {
- // For 8 bit loads, this will generate movsbl or movzbl, so
- // there's no constraint on what the output register may be.
- masm.wasmLoad(*access, srcAddr, dest.any());
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (dest.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedLoadI64(*access, HeapReg, ptr, ptr, dest.i64(),
- temp1);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedLoadFP(*access, HeapReg, ptr, ptr, dest.f32(),
-@@ -7102,17 +7154,19 @@ class BaseCompiler final : public BaseCompilerInterface {
- MOZ_ASSERT(temp.isInvalid());
- if (access->type() == Scalar::Int64) {
- masm.wasmStoreI64(*access, src.i64(), HeapReg, ptr, ptr);
- } else if (src.tag == AnyReg::I64) {
- masm.wasmStore(*access, AnyRegister(src.i64().low), HeapReg, ptr, ptr);
- } else {
- masm.wasmStore(*access, src.any(), HeapReg, ptr, ptr);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+// XXX: We don't really need this anymore
- if (IsUnaligned(*access)) {
- switch (src.tag) {
- case AnyReg::I64:
- masm.wasmUnalignedStoreI64(*access, src.i64(), HeapReg, ptr, ptr,
- temp);
- break;
- case AnyReg::F32:
- masm.wasmUnalignedStoreFP(*access, src.f32(), HeapReg, ptr, ptr,
-@@ -7160,17 +7214,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- void maybeFree(BaseCompiler* bc) {
- for (size_t i = 0; i < Count; ++i) {
- bc->maybeFree(this->operator[](i));
- }
- }
- };
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicRMW32Temps = Atomic32Temps<3>;
- #else
- using AtomicRMW32Temps = Atomic32Temps<1>;
- #endif
-
- template <typename T>
- void atomicRMW32(const MemoryAccessDesc& access, T srcAddr, AtomicOp op,
- RegI32 rv, RegI32 rd, const AtomicRMW32Temps& temps) {
-@@ -7187,17 +7242,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temp, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicFetchOp(access, op, rv, srcAddr, temps[0], rd);
- #endif
- break;
- default: {
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7208,17 +7264,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- // On x86, V is Address. On other platforms, it is Register64.
- // T is BaseIndex or Address.
- template <typename T, typename V>
- void atomicRMW64(const MemoryAccessDesc& access, const T& srcAddr,
- AtomicOp op, V value, Register64 temp, Register64 rd) {
- masm.wasmAtomicFetchOp64(access, op, value, srcAddr, temp, rd);
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicCmpXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicCmpXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicCmpXchg32(const MemoryAccessDesc& access, T srcAddr,
- RegI32 rexpect, RegI32 rnew, RegI32 rd,
-@@ -7236,29 +7293,31 @@ class BaseCompiler final : public BaseCompilerInterface {
- }
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, temps[0],
- temps[1], temps[2], rd);
- #else
- masm.wasmCompareExchange(access, srcAddr, rexpect, rnew, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
- }
- }
-
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- using AtomicXchg32Temps = Atomic32Temps<3>;
- #else
- using AtomicXchg32Temps = Atomic32Temps<0>;
- #endif
-
- template <typename T>
- void atomicXchg32(const MemoryAccessDesc& access, T srcAddr, RegI32 rv,
- RegI32 rd, const AtomicXchg32Temps& temps) {
-@@ -7275,17 +7334,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- }
- break;
- }
- #endif
- case Scalar::Uint16:
- case Scalar::Int32:
- case Scalar::Uint32:
--#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#if defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- masm.wasmAtomicExchange(access, srcAddr, rv, temps[0], temps[1],
- temps[2], rd);
- #else
- masm.wasmAtomicExchange(access, srcAddr, rv, rd);
- #endif
- break;
- default:
- MOZ_CRASH("Bad type for atomic operation");
-@@ -7342,16 +7402,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_MIPS32)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM)
- pop2xI64(r0, r1);
- *temp = needI32();
- #elif defined(JS_CODEGEN_ARM64)
- pop2xI64(r0, r1);
-+#elif defined(JS_CODEGEN_PPC64)
-+ pop2xI64(r0, r1);
- #else
- MOZ_CRASH("BaseCompiler porting interface: pop2xI64ForMulI64");
- #endif
- }
-
- void pop2xI64ForDivI64(RegI64* r0, RegI64* r1, RegI64* reserved) {
- #if defined(JS_CODEGEN_X64)
- // r0 must be rax, and rdx will be clobbered.
-@@ -7529,17 +7591,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI32();
- }
- setRd(bc->needI32());
- }
- ~PopAtomicCmpXchg32Regs() {
- bc->freeI32(rnew);
- bc->freeI32(rexpect);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- if (type == ValType::I64) {
- rnew = bc->popI64ToI32();
- rexpect = bc->popI64ToI32();
- } else {
- rnew = bc->popI32();
-@@ -7606,17 +7669,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- rexpect = bc->popI64();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicCmpXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rnew = bc->popI64();
- rexpect = bc->popI64();
- setRd(bc->needI64());
- }
- ~PopAtomicCmpXchg64Regs() {
- bc->freeI64(rexpect);
- bc->freeI64(rnew);
-@@ -7658,17 +7721,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- bc->needI64(bc->specific_.edx_eax);
- setRd(bc->specific_.edx_eax);
- }
- ~PopAtomicLoad64Regs() { bc->freeI32(bc->specific_.ecx); }
- # elif defined(JS_CODEGEN_ARM)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64Pair());
- }
--# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+# elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- setRd(bc->needI64());
- }
- # else
- explicit PopAtomicLoad64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: PopAtomicLoad64Regs");
- }
- # endif
-@@ -7745,17 +7809,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- temps.allocate(bc);
- setRd(bc->needI32());
- }
- ~PopAtomicRMW32Regs() {
- bc->freeI32(rv);
- temps.maybeFree(bc);
- }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType, AtomicOp op)
- : Base(bc) {
- rv = type == ValType::I64 ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
-
-@@ -7833,17 +7898,17 @@ class BaseCompiler final : public BaseCompilerInterface {
- temp = bc->needI64Pair();
- setRd(bc->needI64Pair());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
- }
- #elif defined(JS_CODEGEN_ARM64) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- explicit PopAtomicRMW64Regs(BaseCompiler* bc, AtomicOp) : Base(bc) {
- rv = bc->popI64();
- temp = bc->needI64();
- setRd(bc->needI64());
- }
- ~PopAtomicRMW64Regs() {
- bc->freeI64(rv);
- bc->freeI64(temp);
-@@ -7888,17 +7953,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- setRd(bc->needI32());
- }
- ~PopAtomicXchg32Regs() { bc->freeI32(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg32Regs(BaseCompiler* bc, ValType type,
- Scalar::Type viewType)
- : Base(bc) {
- rv = (type == ValType::I64) ? bc->popI64ToI32() : bc->popI32();
- if (Scalar::byteSize(viewType) < 4) {
- temps.allocate(bc);
- }
- setRd(bc->needI32());
-@@ -7954,17 +8020,18 @@ class BaseCompiler final : public BaseCompilerInterface {
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #elif defined(JS_CODEGEN_ARM)
- // Both rv and rd must be odd/even pairs.
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64Pair());
- setRd(bc->needI64Pair());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
--#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+#elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- rv = bc->popI64ToSpecific(bc->needI64());
- setRd(bc->needI64());
- }
- ~PopAtomicXchg64Regs() { bc->freeI64(rv); }
- #else
- explicit PopAtomicXchg64Regs(BaseCompiler* bc) : Base(bc) {
- MOZ_CRASH("BaseCompiler porting interface: xchg64");
-@@ -8968,16 +9035,18 @@ static void CtzI32(MacroAssembler& masm, RegI32 rsd) {
-
- // Currently common to PopcntI32 and PopcntI64
- static RegI32 PopcntTemp(BaseCompiler& bc) {
- #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- return AssemblerX86Shared::HasPOPCNT() ? RegI32::Invalid() : bc.needI32();
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- return bc.needI32();
-+#elif defined(JS_CODEGEN_PPC64)
-+ return RegI32::Invalid(); // We rock.
- #else
- MOZ_CRASH("BaseCompiler platform hook: PopcntTemp");
- #endif
- }
-
- static void PopcntI32(BaseCompiler& bc, RegI32 rsd, RegI32 temp) {
- bc.masm.popcnt32(rsd, rsd, temp);
- }
-@@ -11982,17 +12051,17 @@ RegI32 BaseCompiler::popMemory32Access(MemoryAccessDesc* access,
- bceCheckLocal(access, check, local);
- }
-
- return popI32();
- }
-
- void BaseCompiler::pushHeapBase() {
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- RegI64 heapBase = needI64();
- moveI64(RegI64(Register64(HeapReg)), heapBase);
- pushI64(heapBase);
- #elif defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32)
- RegI32 heapBase = needI32();
- moveI32(RegI32(HeapReg), heapBase);
- pushI32(heapBase);
- #elif defined(JS_CODEGEN_X86)
-@@ -17244,17 +17313,19 @@ bool js::wasm::BaselinePlatformSupport() {
- // they are definitely implemented on the Cortex-A7 and Cortex-A15
- // and on all ARMv8 systems.
- if (!HasIDIV()) {
- return false;
- }
- #endif
- #if defined(JS_CODEGEN_X64) || defined(JS_CODEGEN_X86) || \
- defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_ARM64) || \
-- defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64) || \
-+ defined(JS_CODEGEN_PPC64)
-+ // PPC64 gates on other prerequisites not specified here.
- return true;
- #else
- return false;
- #endif
- }
-
- bool js::wasm::BaselineCompileFunctions(const ModuleEnvironment& moduleEnv,
- const CompilerEnvironment& compilerEnv,
-diff --git a/js/src/wasm/WasmCompile.cpp b/js/src/wasm/WasmCompile.cpp
-index 0f456aaaa5..f0694f1b9e 100644
---- a/js/src/wasm/WasmCompile.cpp
-+++ b/js/src/wasm/WasmCompile.cpp
-@@ -45,16 +45,17 @@ using namespace js::wasm;
- uint32_t wasm::ObservedCPUFeatures() {
- enum Arch {
- X86 = 0x1,
- X64 = 0x2,
- ARM = 0x3,
- MIPS = 0x4,
- MIPS64 = 0x5,
- ARM64 = 0x6,
-+ PPC64 = 0x7,
- ARCH_BITS = 3
- };
-
- #if defined(JS_CODEGEN_X86)
- MOZ_ASSERT(uint32_t(jit::CPUInfo::GetSSEVersion()) <=
- (UINT32_MAX >> ARCH_BITS));
- return X86 | (uint32_t(jit::CPUInfo::GetSSEVersion()) << ARCH_BITS);
- #elif defined(JS_CODEGEN_X64)
-@@ -68,16 +69,19 @@ uint32_t wasm::ObservedCPUFeatures() {
- MOZ_ASSERT(jit::GetARM64Flags() <= (UINT32_MAX >> ARCH_BITS));
- return ARM64 | (jit::GetARM64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS32)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS | (jit::GetMIPSFlags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_MIPS64)
- MOZ_ASSERT(jit::GetMIPSFlags() <= (UINT32_MAX >> ARCH_BITS));
- return MIPS64 | (jit::GetMIPSFlags() << ARCH_BITS);
-+#elif defined(JS_CODEGEN_PPC64)
-+ MOZ_ASSERT(jit::GetPPC64Flags() <= (UINT32_MAX >> ARCH_BITS));
-+ return PPC64 | (jit::GetPPC64Flags() << ARCH_BITS);
- #elif defined(JS_CODEGEN_NONE)
- return 0;
- #else
- # error "unknown architecture"
- #endif
- }
-
- FeatureArgs FeatureArgs::build(JSContext* cx, const FeatureOptions& options) {
-diff --git a/js/src/wasm/WasmFrame.h b/js/src/wasm/WasmFrame.h
-index 85f2612d14..9919205739 100644
---- a/js/src/wasm/WasmFrame.h
-+++ b/js/src/wasm/WasmFrame.h
-@@ -53,16 +53,25 @@ constexpr uintptr_t ExitOrJitEntryFPTag = 0x1;
- // before the function has made its stack reservation, the stack alignment is
- // sizeof(Frame) % WasmStackAlignment.
- //
- // During MacroAssembler code generation, the bytes pushed after the wasm::Frame
- // are counted by masm.framePushed. Thus, the stack alignment at any point in
- // time is (sizeof(wasm::Frame) + masm.framePushed) % WasmStackAlignment.
-
- class Frame {
-+#if defined(JS_CODEGEN_PPC64)
-+ // Since Wasm can call directly to ABI-compliant routines, the Frame must
-+ // have an ABI-compliant linkage area. We allocate four doublewords, the
-+ // minimum size.
-+ void *_ppc_sp_;
-+ void *_ppc_cr_;
-+ void *_ppc_lr_;
-+ void *_ppc_toc_;
-+#endif
- // See GenerateCallableEpilogue for why this must be
- // the first field of wasm::Frame (in a downward-growing stack).
- // It's either the caller's Frame*, for wasm callers, or the JIT caller frame
- // plus a tag otherwise.
- uint8_t* callerFP_;
-
- // The return address pushed by the call (in the case of ARM/MIPS the return
- // address is pushed by the first instruction of the prologue).
-@@ -115,18 +124,21 @@ class Frame {
- static uint8_t* addExitOrJitEntryFPTag(const Frame* fp) {
- MOZ_ASSERT(!isExitOrJitEntryFP(fp));
- return reinterpret_cast<uint8_t*>(reinterpret_cast<uintptr_t>(fp) |
- ExitOrJitEntryFPTag);
- }
- };
-
- static_assert(!std::is_polymorphic_v<Frame>, "Frame doesn't need a vtable.");
-+#if !defined(JS_CODEGEN_PPC64)
-+// Not on PowerPC, it's not.
- static_assert(sizeof(Frame) == 2 * sizeof(void*),
- "Frame is a two pointer structure");
-+#endif
-
- class FrameWithTls : public Frame {
- TlsData* calleeTls_;
- TlsData* callerTls_;
-
- public:
- TlsData* calleeTls() { return calleeTls_; }
- TlsData* callerTls() { return callerTls_; }
-diff --git a/js/src/wasm/WasmFrameIter.cpp b/js/src/wasm/WasmFrameIter.cpp
-index dffab53940..5da8d6c730 100644
---- a/js/src/wasm/WasmFrameIter.cpp
-+++ b/js/src/wasm/WasmFrameIter.cpp
-@@ -358,16 +358,21 @@ static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
- static_assert(BeforePushRetAddr == 0, "Required by StartUnwinding");
- static_assert(PushedFP > PushedRetAddr, "Required by StartUnwinding");
- #elif defined(JS_CODEGEN_MIPS32) || defined(JS_CODEGEN_MIPS64)
- static const unsigned PushedRetAddr = 8;
- static const unsigned PushedFP = 12;
- static const unsigned SetFP = 16;
- static const unsigned PoppedFP = 4;
-+#elif defined(JS_CODEGEN_PPC64)
-+static const unsigned PushedRetAddr = 12;
-+static const unsigned PushedFP = 16;
-+static const unsigned SetFP = 20;
-+static const unsigned PoppedFP = 8;
- #elif defined(JS_CODEGEN_NONE)
- // Synthetic values to satisfy asserts and avoid compiler warnings.
- static const unsigned PushedRetAddr = 0;
- static const unsigned PushedFP = 1;
- static const unsigned SetFP = 2;
- static const unsigned PoppedFP = 3;
- #else
- # error "Unknown architecture!"
-@@ -453,16 +458,38 @@ static void GenerateCallablePrologue(MacroAssembler& masm, uint32_t* entry) {
- MemOperand(sp, Frame::callerFPOffset()));
- MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
- masm.Mov(ARMRegister(FramePointer, 64), sp);
- MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-
- // And restore the SP-reg setting, per comment above.
- masm.SetStackPointer64(stashedSPreg);
- }
-+#elif defined(JS_CODEGEN_PPC64)
-+ {
-+ *entry = masm.currentOffset();
-+
-+ // These must be in this precise order. Fortunately we can subsume the
-+ // SPR load into the initial "verse" since it is treated atomically.
-+ // The linkage area required for ABI compliance is baked into the Frame.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_addi(StackPointer, StackPointer, -(sizeof(Frame)));
-+ masm.as_std(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedRetAddr == masm.currentOffset() - *entry);
-+ masm.as_std(FramePointer, StackPointer, Frame::callerFPOffset());
-+ MOZ_ASSERT_IF(!masm.oom(), PushedFP == masm.currentOffset() - *entry);
-+ masm.xs_mr(FramePointer, StackPointer);
-+ MOZ_ASSERT_IF(!masm.oom(), SetFP == masm.currentOffset() - *entry);
-+
-+ // Burn nops because we have to make this a multiple of 16 and the mfspr
-+ // just screwed us.
-+ masm.as_nop(); // 24
-+ masm.as_nop(); // 28
-+ masm.as_nop(); // 32 // trap point
-+ }
- #else
- {
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
-
- *entry = masm.currentOffset();
-
-@@ -527,16 +554,28 @@ static void GenerateCallableEpilogue(MacroAssembler& masm, unsigned framePushed,
- // use it. Hence we have to do it "by hand".
- masm.Mov(PseudoStackPointer64, vixl::sp);
-
- masm.Ret(ARMRegister(lr, 64));
-
- // See comment at equivalent place in |GenerateCallablePrologue| above.
- masm.SetStackPointer64(stashedSPreg);
-
-+#elif defined(JS_CODEGEN_PPC64)
-+
-+ masm.as_ld(FramePointer, StackPointer, Frame::callerFPOffset());
-+ poppedFP = masm.currentOffset();
-+ // This is suboptimal since we get serialized, but has to be in this order.
-+ masm.as_ld(ScratchRegister, StackPointer, Frame::returnAddressOffset());
-+ masm.xs_mtlr(ScratchRegister);
-+ *ret = masm.currentOffset();
-+
-+ masm.as_addi(StackPointer, StackPointer, sizeof(Frame));
-+ masm.as_blr();
-+
- #else
- // Forbid pools for the same reason as described in GenerateCallablePrologue.
- # if defined(JS_CODEGEN_ARM)
- AutoForbidPoolsAndNops afp(&masm, /* number of instructions in scope = */ 6);
- # endif
-
- // There is an important ordering constraint here: fp must be repointed to
- // the caller's frame before any field of the frame currently pointed to by
-@@ -773,16 +812,23 @@ void wasm::GenerateJitEntryPrologue(MacroAssembler& masm, Offsets* offsets) {
- AutoForbidPoolsAndNops afp(&masm,
- /* number of instructions in scope = */ 3);
- offsets->begin = masm.currentOffset();
- static_assert(BeforePushRetAddr == 0);
- // Subtract from SP first as SP must be aligned before offsetting.
- masm.Sub(sp, sp, 8);
- masm.storePtr(lr, Address(masm.getStackPointer(), 0));
- masm.adjustFrame(8);
-+#elif defined(JS_CODEGEN_PPC64)
-+ offsets->begin = masm.currentOffset();
-+
-+ // We have to burn a nop here to match the other prologue length.
-+ masm.xs_mflr(ScratchRegister);
-+ masm.as_nop(); // might as well explicitly wait for the mfspr to complete
-+ masm.as_stdu(ScratchRegister, StackPointer, -8);
- #else
- // The x86/x64 call instruction pushes the return address.
- offsets->begin = masm.currentOffset();
- #endif
- MOZ_ASSERT_IF(!masm.oom(),
- PushedRetAddr == masm.currentOffset() - offsets->begin);
-
- // Save jit frame pointer, so unwinding from wasm to jit frames is trivial.
-diff --git a/js/src/wasm/WasmGC.cpp b/js/src/wasm/WasmGC.cpp
-index 4eb77a81a2..3f00cbb632 100644
---- a/js/src/wasm/WasmGC.cpp
-+++ b/js/src/wasm/WasmGC.cpp
-@@ -284,16 +284,33 @@ bool IsValidStackMapKey(bool debugEnabled, const uint8_t* nextPC) {
- (insn[-1] & 0xfffffc1f) == 0xd63f0000 || // blr reg
- (insn[-1] & 0xfc000000) == 0x94000000 || // bl simm26
- (debugEnabled && insn[-1] == 0xd503201f)); // nop
-
- # elif defined(JS_CODEGEN_MIPS64)
- // TODO (bug 1699696): Implement this. As for the platforms above, we need to
- // enumerate all code sequences that can precede the stackmap location.
- return true;
-+# elif defined(JS_CODEGEN_PPC64)
-+// XXX: we should just be able to use inst[0]
-+ const uint32_t* insn = (const uint32_t*)nextPC;
-+ js::jit::Instruction* inst = (js::jit::Instruction*)nextPC;
-+ //fprintf(stderr, "IsValidStackMapKey: 0x%lx 0x%08x\n", (uint64_t)nextPC, insn[0]);
-+ return (((uintptr_t(insn) & 3) == 0) &&
-+ (inst[0].extractOpcode() == js::jit::PPC_addi || // stack allocate
-+ inst[0].extractOpcode() == js::jit::PPC_addis || // load immediate
-+ inst[0].extractOpcode() == js::jit::PPC_cmpwi || // test after bl
-+ inst[0].extractOpcode() == js::jit::PPC_cmpw || // (extsw, same)
-+ inst[0].extractOpcode() == js::jit::PPC_lfd || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lfs || // load FPR
-+ inst[0].extractOpcode() == js::jit::PPC_lwz || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_ld || // load GPR
-+ inst[0].extractOpcode() == js::jit::PPC_b || // branch
-+ inst[0].encode() == js::jit::PPC_nop || // GET BACK TO WORK
-+ inst[0].encode() == js::jit::PPC_stop)); // designated throw
- # else
- MOZ_CRASH("IsValidStackMapKey: requires implementation on this platform");
- # endif
- }
- #endif
-
- } // namespace wasm
- } // namespace js
-diff --git a/js/src/wasm/WasmSignalHandlers.cpp b/js/src/wasm/WasmSignalHandlers.cpp
-index 4ab2a44192..1a51061a12 100644
---- a/js/src/wasm/WasmSignalHandlers.cpp
-+++ b/js/src/wasm/WasmSignalHandlers.cpp
-@@ -101,16 +101,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->sc_pc)
- # define RFP_sig(p) ((p)->sc_regs[30])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->sc_frame.fixreg[1])
-+# define R31_sig(p) ((p)->sc_frame.fixreg[31])
- # define R32_sig(p) ((p)->sc_frame.srr0)
- # endif
- #elif defined(__linux__) || defined(__sun)
- # if defined(__linux__)
- # define EIP_sig(p) ((p)->uc_mcontext.gregs[REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.gregs[REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.gregs[REG_ESP])
- # else
-@@ -147,16 +148,17 @@ using mozilla::DebugOnly;
- # if defined(__linux__) && (defined(__sparc__) && defined(__arch64__))
- # define PC_sig(p) ((p)->uc_mcontext.mc_gregs[MC_PC])
- # define FP_sig(p) ((p)->uc_mcontext.mc_fp)
- # define SP_sig(p) ((p)->uc_mcontext.mc_i7)
- # endif
- # if defined(__linux__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.gp_regs[1])
-+# define R31_sig(p) ((p)->uc_mcontext.gp_regs[31])
- # define R32_sig(p) ((p)->uc_mcontext.gp_regs[32])
- # endif
- #elif defined(__NetBSD__)
- # define EIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EIP])
- # define EBP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EBP])
- # define ESP_sig(p) ((p)->uc_mcontext.__gregs[_REG_ESP])
- # define RIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RIP])
- # define RSP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSP])
-@@ -173,16 +175,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.__gregs[_REG_EPC])
- # define RFP_sig(p) ((p)->uc_mcontext.__gregs[_REG_S8])
- # endif
- # if defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define R01_sig(p) ((p)->uc_mcontext.__gregs[_REG_R1])
-+# define R31_sig(p) ((p)->uc_mcontext.__gregs[_REG_R31])
- # define R32_sig(p) ((p)->uc_mcontext.__gregs[_REG_PC])
- # endif
- #elif defined(__DragonFly__) || defined(__FreeBSD__) || \
- defined(__FreeBSD_kernel__)
- # define EIP_sig(p) ((p)->uc_mcontext.mc_eip)
- # define EBP_sig(p) ((p)->uc_mcontext.mc_ebp)
- # define ESP_sig(p) ((p)->uc_mcontext.mc_esp)
- # define RIP_sig(p) ((p)->uc_mcontext.mc_rip)
-@@ -207,16 +210,17 @@ using mozilla::DebugOnly;
- # endif
- # if defined(__FreeBSD__) && defined(__mips__)
- # define EPC_sig(p) ((p)->uc_mcontext.mc_pc)
- # define RFP_sig(p) ((p)->uc_mcontext.mc_regs[30])
- # endif
- # if defined(__FreeBSD__) && (defined(__ppc64__) || defined(__PPC64__) || \
- defined(__ppc64le__) || defined(__PPC64LE__))
- # define R01_sig(p) ((p)->uc_mcontext.mc_gpr[1])
-+# define R31_sig(p) ((p)->uc_mcontext.mc_gpr[31])
- # define R32_sig(p) ((p)->uc_mcontext.mc_srr0)
- # endif
- #elif defined(XP_DARWIN)
- # define EIP_sig(p) ((p)->thread.uts.ts32.__eip)
- # define EBP_sig(p) ((p)->thread.uts.ts32.__ebp)
- # define ESP_sig(p) ((p)->thread.uts.ts32.__esp)
- # define RIP_sig(p) ((p)->thread.__rip)
- # define RBP_sig(p) ((p)->thread.__rbp)
-@@ -367,17 +371,17 @@ struct macos_aarch64_context {
- # define PC_sig(p) EPC_sig(p)
- # define FP_sig(p) RFP_sig(p)
- # define SP_sig(p) RSP_sig(p)
- # define LR_sig(p) R31_sig(p)
- #elif defined(__ppc64__) || defined(__PPC64__) || defined(__ppc64le__) || \
- defined(__PPC64LE__)
- # define PC_sig(p) R32_sig(p)
- # define SP_sig(p) R01_sig(p)
--# define FP_sig(p) R01_sig(p)
-+# define FP_sig(p) R31_sig(p)
- #endif
-
- static void SetContextPC(CONTEXT* context, uint8_t* pc) {
- #ifdef PC_sig
- *reinterpret_cast<uint8_t**>(&PC_sig(context)) = pc;
- #else
- MOZ_CRASH();
- #endif
-diff --git a/js/src/wasm/WasmStubs.cpp b/js/src/wasm/WasmStubs.cpp
-index 59a5cf18bf..dbc10c6e2c 100644
---- a/js/src/wasm/WasmStubs.cpp
-+++ b/js/src/wasm/WasmStubs.cpp
-@@ -719,17 +719,17 @@ static bool GenerateInterpEntry(MacroAssembler& masm, const FuncExport& fe,
- AssertExpectedSP(masm);
- masm.haltingAlign(CodeAlignment);
-
- offsets->begin = masm.currentOffset();
-
- // Save the return address if it wasn't already saved by the call insn.
- #ifdef JS_USE_LINK_REGISTER
- # if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS32) || \
-- defined(JS_CODEGEN_MIPS64)
-+ defined(JS_CODEGEN_MIPS64) || defined(JS_CODEGEN_PPC64)
- masm.pushReturnAddress();
- # elif defined(JS_CODEGEN_ARM64)
- // WasmPush updates framePushed() unlike pushReturnAddress(), but that's
- // cancelled by the setFramePushed() below.
- WasmPush(masm, lr);
- # else
- MOZ_CRASH("Implement this");
- # endif
-@@ -2111,17 +2111,26 @@ static bool GenerateImportInterpExit(MacroAssembler& masm, const FuncImport& fi,
- masm.storePtr(scratch,
- Address(masm.getStackPointer(), i->offsetFromArgBase()));
- }
- i++;
- MOZ_ASSERT(i.done());
-
- // Make the call, test whether it succeeded, and extract the return value.
- AssertStackAlignment(masm, ABIStackAlignment);
-+#ifdef JS_CODEGEN_PPC64
-+ // Because this is calling an ABI-compliant function, we have to pull down
-+ // a dummy linkage area or the values on the stack will be stomped on. The
-+ // minimum size is sufficient.
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), -32);
-+#endif
- masm.call(SymbolicAddress::CallImport_General);
-+#ifdef JS_CODEGEN_PPC64
-+ masm.as_addi(masm.getStackPointer(), masm.getStackPointer(), 32);
-+#endif
- masm.branchTest32(Assembler::Zero, ReturnReg, ReturnReg, throwLabel);
-
- ResultType resultType = ResultType::Vector(fi.funcType().results());
- ValType registerResultType;
- for (ABIResultIter iter(resultType); !iter.done(); iter.next()) {
- if (iter.cur().inRegister()) {
- MOZ_ASSERT(!registerResultType.isValid());
- registerResultType = iter.cur().type();
-@@ -2673,16 +2682,21 @@ static const LiveRegisterSet RegsToPreserve(
- #elif defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
- // It's correct to use FloatRegisters::AllMask even when SIMD is not enabled;
- // PushRegsInMask strips out the high lanes of the XMM registers in this case,
- // while the singles will be stripped as they are aliased by the larger doubles.
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(Registers::AllMask &
- ~(Registers::SetType(1) << Registers::StackPointer)),
- FloatRegisterSet(FloatRegisters::AllMask));
-+#elif defined(JS_CODEGEN_PPC64)
-+// Note that this includes no SPRs, since the JIT is unaware of them.
-+static const LiveRegisterSet RegsToPreserve(
-+ GeneralRegisterSet(Registers::AllMask),
-+ FloatRegisterSet(FloatRegisters::AllMask));
- #else
- static const LiveRegisterSet RegsToPreserve(
- GeneralRegisterSet(0), FloatRegisterSet(FloatRegisters::AllDoubleMask));
- # ifdef ENABLE_WASM_SIMD
- # error "no SIMD support"
- # endif
- #endif
-
-diff --git a/modules/libpref/init/StaticPrefList.yaml b/modules/libpref/init/StaticPrefList.yaml
-index d81025b282..43b75c6ae0 100644
---- a/modules/libpref/init/StaticPrefList.yaml
-+++ b/modules/libpref/init/StaticPrefList.yaml
-@@ -5729,17 +5729,17 @@
- - name: javascript.options.baselinejit
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- - name: javascript.options.ion
- type: bool
-- value: true
-+ value: false
- mirror: always # LoadStartupJSPrefs
- do_not_use_directly: true
-
- # The irregexp JIT for regex evaluation.
- - name: javascript.options.native_regexp
- type: bool
- value: true
- mirror: always # LoadStartupJSPrefs
-@@ -5968,17 +5968,17 @@
- value: 6 * 1024 * 1024
- #else
- value: 2 * 1024 * 1024
- #endif
- mirror: always
-
- - name: javascript.options.wasm_optimizingjit
- type: bool
-- value: true
-+ value: false
- mirror: always
-
- #if defined(ENABLE_WASM_SIMD)
- - name: javascript.options.wasm_simd
- type: bool
- value: true
- mirror: always
- #endif // defined(ENABLE_WASM_SIMD)
diff --git a/srcpkgs/firefox-esr/patches/skia-sucks3.patch b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
index 908311cdb6db..4bf77e684405 100644
--- a/srcpkgs/firefox-esr/patches/skia-sucks3.patch
+++ b/srcpkgs/firefox-esr/patches/skia-sucks3.patch
@@ -30,27 +30,3 @@ diff -r 46ea866ca3ac -r 6ef20eee3f8f gfx/2d/DrawTargetSkia.cpp
mCanvas->saveLayer(saveRec);
SetPermitSubpixelAA(aOpaque);
---- a/gfx/layers/composite/CompositableHost.cpp
-+++ b/gfx/layers/composite/CompositableHost.cpp
-@@ -13,6 +13,7 @@
- #include "ImageHost.h" // for ImageHostBuffered, etc
- #include "Layers.h"
- #include "TiledContentHost.h" // for TiledContentHost
-+#include "mozilla/EndianUtils.h"
- #include "mozilla/gfx/gfxVars.h"
- #include "mozilla/layers/LayersSurfaces.h" // for SurfaceDescriptor
- #include "mozilla/layers/TextureHost.h" // for TextureHost, etc
-@@ -92,9 +93,13 @@ bool CompositableHost::AddMaskEffect(EffectChain& aEffects,
- }
- MOZ_ASSERT(source);
-
-+ // Setting an alpha-mask here breaks the URL-bar on big endian (s390x)
-+ // if the typed URL is too long for the textbox (automatic scrolling needed)
-+#if MOZ_LITTLE_ENDIAN()
- RefPtr<EffectMask> effect =
- new EffectMask(source, source->GetSize(), aTransform);
- aEffects.mSecondaryEffects[EffectTypes::MASK] = effect;
-+#endif
- return true;
- }
-
diff --git a/srcpkgs/firefox-esr/patches/sndio.patch b/srcpkgs/firefox-esr/patches/sndio.patch
deleted file mode 100644
index 68628bea8d8f..000000000000
--- a/srcpkgs/firefox-esr/patches/sndio.patch
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/old-configure.in
-+++ b/old-configure.in
-@@ -2818,6 +2818,22 @@
- _NON_GLOBAL_ACDEFINES="$_NON_GLOBAL_ACDEFINES NECKO_COOKIES"
- fi
-
-+dnl ==================================
-+dnl = Check sndio availability
-+dnl ==================================
-+
-+MOZ_ARG_ENABLE_BOOL(sndio,
-+[ --enable-sndio Enable sndio support],
-+ MOZ_SNDIO=1,
-+ MOZ_SNDIO=)
-+
-+if test -n "$MOZ_SNDIO"; then
-+ MOZ_SNDIO_LIBS="-lsndio"
-+ AC_SUBST_LIST(MOZ_SNDIO_LIBS)
-+fi
-+
-+AC_SUBST(MOZ_SNDIO)
-+
- dnl ========================================================
- dnl =
- dnl = Maintainer debug option (no --enable equivalent)
---- a/media/libcubeb/src/moz.build
-+++ b/media/libcubeb/src/moz.build
-@@ -44,11 +44,13 @@
- ]
- DEFINES['USE_JACK'] = True
-
--if CONFIG['OS_ARCH'] == 'OpenBSD':
-+if CONFIG['MOZ_SNDIO']:
- SOURCES += [
- 'cubeb_sndio.c',
- ]
- DEFINES['USE_SNDIO'] = True
-+
-+if CONFIG['OS_ARCH'] == 'OpenBSD':
- DEFINES['DISABLE_LIBSNDIO_DLOPEN'] = True
-
- if CONFIG['OS_TARGET'] == 'Darwin':
---- a/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-+++ b/build/moz.configure/old.configure 2020-06-30 12:17:04.087609070 +0200
-@@ -88,6 +88,7 @@
- @old_configure_options(
- "--cache-file",
- "--datadir",
-+ "--enable-sndio",
- "--enable-crashreporter",
- "--enable-dbus",
- "--enable-debug-js-modules",
diff --git a/srcpkgs/firefox-esr/template b/srcpkgs/firefox-esr/template
index 58c065649bc4..270c406153a7 100644
--- a/srcpkgs/firefox-esr/template
+++ b/srcpkgs/firefox-esr/template
@@ -3,7 +3,7 @@
# THIS PKG MUST BE SYNCHRONIZED WITH "srcpkgs/firefox-esr-i18n".
#
pkgname=firefox-esr
-version=91.10.0
+version=102.2.0
revision=1
wrksrc="firefox-${version}"
build_helper="rust"
@@ -11,15 +11,13 @@ short_desc="Mozilla Firefox web browser - Extended Support Release"
maintainer="Orphaned <orphan@voidlinux.org>"
license="MPL-2.0, GPL-2.0-or-later, LGPL-2.1-or-later"
homepage="https://www.mozilla.org/firefox/"
-distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz
- https://github.com/chmeeedalf/gecko-dev/files/7729086/esrppcjit.tar.gz"
-checksum="825a8cb38bb5da9821ef87cc6de64af007cf0faef07c4ed0651283b56a0ee1bb
- 5e926a8be5d6d4949c3bc3eb98e2103692eaa26a98928db432b1d44b535f7241"
+distfiles="${MOZILLA_SITE}/firefox/releases/${version}esr/source/firefox-${version}esr.source.tar.xz"
+checksum="014d91d14ab4f53e93728273b45ac6022813d5ade35f842e722bf87b747c97ff"
lib32disabled=yes
hostmakedepends="autoconf213 unzip zip pkg-config perl python3 yasm rust cargo
- llvm clang nodejs-lts cbindgen python nasm which tar"
+ llvm clang nodejs-lts cbindgen nasm which tar"
makedepends="nss-devel libjpeg-turbo-devel gtk+3-devel icu-devel
pixman-devel libevent-devel libnotify-devel libvpx-devel
libXrender-devel libXcomposite-devel libSM-devel libXt-devel rust-std
@@ -63,9 +61,6 @@ post_extract() {
;;
esac
- # ppc64le jit, see --enable-jit later
- mv ../js/src/jit/ppc64 js/src/jit
-
# Mozilla API keys (see https://location.services.mozilla.com/api)
# Note: This is for Void Linux use ONLY.
echo -n "cd894504-7a2a-4263-abff-ff73ee89ffca" > mozilla-api-key
@@ -78,24 +73,24 @@ post_patch() {
do_build() {
cp "${FILESDIR}/mozconfig" "${wrksrc}/.mozconfig"
+ echo "MOZ_APP_REMOTINGNAME=Firefox" >>.mozconfig
+
case "$XBPS_TARGET_MACHINE" in
*-musl)
echo "ac_add_options --disable-jemalloc" >>.mozconfig
- echo "ac_add_options --disable-gold" >>.mozconfig
+ echo "ac_add_options --enable-linker=bfd" >>.mozconfig
;;
esac
case "$XBPS_TARGET_MACHINE" in
- x86_64*|i686*|arm*)
+ x86_64*|i686*|arm*|aarch64*)
echo "ac_add_options --disable-elf-hack" >>.mozconfig
;;
esac
# webrtc currently fails to build on 32-bit ppc...
- # also enable jit on ppc64le, which is patched in earlier
- # https://www.talospace.com/2021/12/91esr-with-baseline-compilerbaseline.html
+ # TODO: also enable jit on ppc64le
case "$XBPS_TARGET_MACHINE" in
- ppc64le*) echo "ac_add_options --enable-jit" >>.mozconfig ;;
ppc64*) echo "ac_add_options --disable-jit" >>.mozconfig ;;
ppc*)
echo "ac_add_options --disable-jit" >>.mozconfig
@@ -132,6 +127,10 @@ do_build() {
echo "ac_add_options --host=$XBPS_TRIPLET" >>.mozconfig
fi
+ # XXX: wasi currently not ready
+ # echo "ac_add_options --with-wasi-sysroot=/usr/share/wasi-sysroot" >>.mozconfig
+ echo "ac_add_options --without-wasm-sandboxed-libraries" >>.mozconfig
+
mkdir -p third_party/rust/libloading/.deps
case "$XBPS_TARGET_MACHINE" in
@@ -165,7 +164,7 @@ do_build() {
export MOZ_MAKE_FLAGS="${makejobs}"
export MOZ_NOSPAM=1
export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
export AS=$CC
@@ -184,7 +183,8 @@ ac_add_options --enable-default-toolkit=$(vopt_if wayland 'cairo-gtk3-wayland' '
./mach build
}
do_install() {
- export MACH_USE_SYSTEM_PYTHON=1
+ export MACH_BUILD_PYTHON_NATIVE_PACKAGE_SOURCE=system
+ export MOZBUILD_STATE_PATH="${wrksrc}/mozbuild"
DESTDIR="$DESTDIR" ./mach install
vinstall ${FILESDIR}/vendor.js 644 usr/lib/firefox/browser/defaults/preferences
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PR PATCH] [Closed]: firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (11 preceding siblings ...)
2022-09-08 21:36 ` [PR PATCH] [Updated] " oreo639
@ 2022-10-05 17:25 ` oreo639
2022-10-05 17:25 ` oreo639
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-10-05 17:25 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 1196 bytes --]
There's a closed pull request on the void-packages repository
firefox-esr: update to 102.2.0.
https://github.com/void-linux/void-packages/pull/38817
Description:
<!-- Uncomment relevant sections and delete options which are not applicable -->
#### Testing the changes
- I tested the changes in this PR: **briefly**
[ci skip]
This fixes build with current cbindgen in repos. This also fixes build with gcc 12.
<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
-->
<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#continuous-integration
and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
-->
<!--
#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
- aarch64-musl
- armv7l
- armv6l-musl
-->
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: firefox-esr: update to 102.2.0.
2022-08-21 22:05 [PR PATCH] firefox-esr: update to 91.12.0 oreo639
` (12 preceding siblings ...)
2022-10-05 17:25 ` [PR PATCH] [Closed]: " oreo639
@ 2022-10-05 17:25 ` oreo639
13 siblings, 0 replies; 15+ messages in thread
From: oreo639 @ 2022-10-05 17:25 UTC (permalink / raw)
To: ml
[-- Attachment #1: Type: text/plain, Size: 233 bytes --]
New comment by oreo639 on void-packages repository
https://github.com/void-linux/void-packages/pull/38817#issuecomment-1268720956
Comment:
https://github.com/void-linux/void-packages/commit/4f1daf96bee4a39ba0db2325ef30119c48fa1f18
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