[PR PATCH] pcre2: update to 10.42.

[PR PATCH] pcre2: update to 10.42.

[mhmdanas]

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There is a new pull request by mhmdanas against master on the void-packages repository

https://github.com/mhmdanas/void-packages pcre2-10.42
https://github.com/void-linux/void-packages/pull/44329

pcre2: update to 10.42.
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#### Testing the changes
- I tested the changes in this PR: **briefly**

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A patch file from https://github.com/void-linux/void-packages/pull/44329.patch is attached

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From af78efb5d05db8928e9bd7dc6d7e2724ae3158c0 Mon Sep 17 00:00:00 2001
From: triallax <triallax@tutanota.com>
Date: Fri, 9 Jun 2023 12:52:01 +0100
Subject: [PATCH] pcre2: update to 10.42.

---
 srcpkgs/pcre2/patches/ppc-icache-flush.patch | 102 -------------------
 srcpkgs/pcre2/template                       |   7 +-
 2 files changed, 4 insertions(+), 105 deletions(-)
 delete mode 100644 srcpkgs/pcre2/patches/ppc-icache-flush.patch

diff --git a/srcpkgs/pcre2/patches/ppc-icache-flush.patch b/srcpkgs/pcre2/patches/ppc-icache-flush.patch
deleted file mode 100644
index b1abb1109a9a..000000000000
--- a/srcpkgs/pcre2/patches/ppc-icache-flush.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-GCC's version of __builtin___clear_cache() is a no-op on PowerPC.
-Change to use an improved version of the existing ppc_cache_flush().
-
---- a/src/sljit/sljitConfigInternal.h	2021-08-20 09:51:28.000000000 -0700
-+++ b/src/sljit/sljitConfigInternal.h	2022-02-11 20:56:43.159092563 -0800
-@@ -320,7 +320,8 @@
- /****************************/
- 
- #if (!defined SLJIT_CACHE_FLUSH && defined __has_builtin)
--#if __has_builtin(__builtin___clear_cache)
-+#if __has_builtin(__builtin___clear_cache) && \
-+	!(defined SLJIT_CONFIG_PPC && SLJIT_CONFIG_PPC)
- 
- #define SLJIT_CACHE_FLUSH(from, to) \
- 	__builtin___clear_cache((char*)(from), (char*)(to))
---- a/src/sljit/sljitNativePPC_common.c	2022-02-12 20:46:28.383224561 -0800
-+++ b/src/sljit/sljitNativePPC_common.c	2022-02-12 20:48:22.210099029 -0800
-@@ -46,6 +46,39 @@
- #define SLJIT_PASS_ENTRY_ADDR_TO_CALL 1
- #endif
- 
-+#ifdef __linux__
-+#include <sys/auxv.h>
-+
-+/* Return the instruction cache line size, in bytes. */
-+static SLJIT_INLINE sljit_u32 get_icache_line_size()
-+{
-+	static sljit_u32 icache_line_size = 0;
-+	if (SLJIT_UNLIKELY(!icache_line_size)) {
-+		icache_line_size = (sljit_u32) getauxval(AT_ICACHEBSIZE);
-+		SLJIT_ASSERT(icache_line_size != 0);
-+	}
-+	return icache_line_size;
-+}
-+
-+/* Cache and return the first hardware capabilities word. */
-+static SLJIT_INLINE unsigned long get_hwcap()
-+{
-+	static unsigned long hwcap = 0;
-+	if (SLJIT_UNLIKELY(!hwcap)) {
-+		hwcap = getauxval(AT_HWCAP);
-+		SLJIT_ASSERT(hwcap != 0);
-+	}
-+	return hwcap;
-+}
-+
-+/* Return non-zero if this CPU has the icache snoop feature. */
-+static SLJIT_INLINE unsigned long has_feature_icache_snoop()
-+{
-+	return (get_hwcap() & PPC_FEATURE_ICACHE_SNOOP);
-+}
-+
-+#endif  /* __linux__ */
-+
- #if (defined SLJIT_CACHE_FLUSH_OWN_IMPL && SLJIT_CACHE_FLUSH_OWN_IMPL)
- 
- static void ppc_cache_flush(sljit_ins *from, sljit_ins *to)
-@@ -68,14 +101,40 @@
- #	error "Cache flush is not implemented for PowerPC/POWER common mode."
- #	else
- 	/* Cache flush for PowerPC architecture. */
--	while (from < to) {
-+	/* For POWER5 and up with icache snooping, only one icbi in the range
-+ 	 * is required. The sync flushes the store queue, and the icbi/isync
-+	 * kills the local prefetch.
-+	 */
-+	if (has_feature_icache_snoop()) {
- 		__asm__ volatile (
--			"dcbf 0, %0\n"
- 			"sync\n"
- 			"icbi 0, %0\n"
--			: : "r"(from)
-+			"isync\n"
-+			: : "r"(from) : "memory"
-+		);
-+		return;
-+	}
-+
-+	sljit_u32 cache_line_bytes = get_icache_line_size();
-+	sljit_u32 cache_line_words = cache_line_bytes / sizeof(sljit_ins);
-+	uintptr_t cache_line_mask = ~(uintptr_t)(cache_line_bytes - 1);
-+
-+	/* Round down to start of cache line to simplify the end condition. */
-+	sljit_ins* start = (sljit_ins*)((uintptr_t)(from) & cache_line_mask);
-+
-+	for (from = start; from < to; from += cache_line_words) {
-+		__asm__ volatile (
-+			"dcbf 0, %0"
-+			: : "r"(from) : "memory"
-+		);
-+	}
-+	__asm__ volatile ( "sync" );
-+
-+	for (from = start; from < to; from += cache_line_words) {
-+		__asm__ volatile (
-+			"icbi 0, %0"
-+			: : "r"(from) : "memory"
- 		);
--		from++;
- 	}
- 	__asm__ volatile ( "isync" );
- #	endif
diff --git a/srcpkgs/pcre2/template b/srcpkgs/pcre2/template
index cbb58f41e9ee..24677648eb60 100644
--- a/srcpkgs/pcre2/template
+++ b/srcpkgs/pcre2/template
@@ -1,7 +1,7 @@
 # Template file for 'pcre2'
 pkgname=pcre2
-version=10.39
-revision=2
+version=10.42
+revision=1
 build_style=gnu-configure
 configure_args="--with-pic --enable-pcre2-16 --enable-pcre2-32
 --enable-pcre2test-libreadline --enable-pcre2grep-libz --enable-pcre2grep-libbz2
@@ -11,8 +11,9 @@ short_desc="Perl Compatible Regular Expressions (2nd version)"
 maintainer="Enno Boland <gottox@voidlinux.org>"
 license="BSD-3-Clause"
 homepage="https://www.pcre.org/"
+changelog="https://raw.githubusercontent.com/PCRE2Project/pcre2/master/NEWS"
 distfiles="https://github.com/PhilipHazel/pcre2/releases/download/pcre2-${version}/pcre2-${version}.tar.bz2"
-checksum=0f03caf57f81d9ff362ac28cd389c055ec2bf0678d277349a1a4bee00ad6d440
+checksum=8d36cd8cb6ea2a4c2bb358ff6411b0c788633a2a45dabbf1aeb4b701d1b5e840
 
 post_install() {
 	vlicense LICENCE

Re: [PR PATCH] [Closed]: pcre2: update to 10.42.

[abenson]

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There's a closed pull request on the void-packages repository

pcre2: update to 10.42.
https://github.com/void-linux/void-packages/pull/44329

Description:
<!-- Uncomment relevant sections and delete options which are not applicable -->

#### Testing the changes
- I tested the changes in this PR: **briefly**

<!--
#### New package
- This new package conforms to the [package requirements](https://github.com/void-linux/void-packages/blob/master/CONTRIBUTING.md#package-requirements): **YES**|**NO**
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<!-- Note: If the build is likely to take more than 2 hours, please add ci skip tag as described in
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and test at least one native build and, if supported, at least one cross build.
Ignore this section if this PR is not skipping CI.
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#### Local build testing
- I built this PR locally for my native architecture, (ARCH-LIBC)
- I built this PR locally for these architectures (if supported. mark crossbuilds):
  - aarch64-musl
  - armv7l
  - armv6l-musl
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