Re: [9fans] how people learn things (was architectures)

[Lucio De Re <lucio@proxima.alt.za>]

On Fri, Jul 13, 2001 at 03:26:08PM +0000, Douglas A. Gwyn wrote:
>
> Lucio De Re wrote:
> > No more than from Intel (they are to be blamed for CP/M, too),
> > overlooking the fact that their address bus was wider than the
> > register size, or scrapping the i860/i960 developments.
> > They are rushed decisions that can't be reversed.  ...
>
> Even the original PDP-11 had a wider address bus than its
> register (word) size.  It wasn't a "rushed decision", although
> in the long run it caused enough trouble that a whole new
> architecture was designed to replace it.

Do you mean to tell me that DEC had a segmented architecture, with
haphazard default "base" registers, a LOCK instruction to lock the
bus for the following fetch cycle (whatever for? even the Univac
1106 had the more sane test-and-set) and a faulty MOV SS,XX that
did _not_ lock the bus for the following MOV SP,YY as was the
intention?

I bet the 20-bit address was an oversight, one that is still being
dragged along in this era of 64-bit registers.  For heaven's sake,
Intel's marketing hype was full of praise for the ability to have
2^12 (overlapping) segments, and to this day the Pentium has segment
registers.  Worse, one reads of superservers addressing up to
64Gigabytes of main memory - must be programmed in assembler 'cause
it's a long time since I've seen a compiler capable of producing
segmented architecture code.

> architecture was designed to replace it.

No, not to "replace it", but to propagate it.

++L