Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Bakul Shah <bakul@bitblocks.com>]

On Aug 9, 2019, at 2:34 PM, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> 
> Since the resources are small if not tiny, a little systems analysis and design is probably needed, but it looks like a bit of fun, until the inevitable moment of "why am I here?".
> 
> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
> The device I've got is ESP32-WROOM-32. None of the boards I've seen that use it bother with external memory,
> so memory is limited, especially the way it's partitioned.
> 
> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
> The ESP32 has got several MMUs. The characteristics are different depending on the part that a given MMU accesses (flash, ROM, SRAM, external memory).
> Some things are accessed using Memory Protection Units instead, which control access by Process ID, but don't do mapping. Others including some of the SRAMs are accessed through
> an MMU that can do virtual to physical mapping. The MMUs for internal SRAM0 and 2 choose protection for a given physical page as none, one or all of PIDs 2 to 7, with the virtual address that
> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute privileged instructions.
> A large chunk of SRAM (SRAM 1) has only Memory Protection and no translation. The external memory MMU is the most general (most conventional).

Thanks.

Not ideal for plan9 but it would be nice to have access to all its IO capabilities over 9p.