From: Lucio De Re <lucio.dere@gmail.com>
To: Fans of the OS Plan 9 from Bell Labs <9fans@9fans.net>
Subject: Re: [9fans] Plan 9 C compiler for Xtensa CPUs
Date: Wed, 7 Aug 2019 10:07:32 +0200 [thread overview]
Message-ID: <CAJQ9t7iyXQm=OKUT6HKDidPpFQ4A5F78KfJ0026cWCkHDrod4A@mail.gmail.com> (raw)
In-Reply-To: <CAOw7k5jFJgN8dYSJ7quVMv_dqMVBsQ5N6qjcAZm0KwZ6CN+wdg@mail.gmail.com>
On 8/7/19, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> I've not previously seen an architecture where so many cache and TLB
> control instructions were in the primary space and took up so much of it.
>
I guess the remainder is RISC :-).
Lucio.
next prev parent reply other threads:[~2019-08-07 8:07 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 6:37 Cyber Fonic
2019-07-26 10:02 ` Rodrigo G. López
2019-07-26 10:30 ` Charles Forsyth
2019-07-26 12:04 ` Rodrigo G. López
2019-07-26 12:12 ` Cyber Fonic
2019-07-26 15:23 ` Charles Forsyth
2019-07-27 9:16 ` Anthony Martin
2019-07-27 11:10 ` Richard Miller
2019-07-27 16:29 ` Anthony Martin
2019-08-07 0:22 ` Charles Forsyth
2019-08-07 8:07 ` Lucio De Re [this message]
2019-08-09 14:17 ` Bakul Shah
2019-08-09 14:50 ` Charles Forsyth
2019-08-09 15:50 ` Charles Forsyth
2019-08-09 21:34 ` Charles Forsyth
2019-08-09 21:48 ` Shane Morris
2019-08-09 22:51 ` Bakul Shah
2019-08-09 22:53 ` Skip Tavakkolian
2019-08-10 9:09 ` Cyber Fonic
2019-08-10 9:15 ` Shane Morris
2019-08-10 16:18 ` Charles Forsyth
2019-08-11 18:59 ` Lyndon Nerenberg
2019-08-18 14:10 ` Charles Forsyth
2019-08-18 14:28 ` Richard Miller
2019-08-19 11:51 ` Cyber Fonic
2019-08-19 14:52 ` [9fans] Plan 9 security Ethan Gardener
2019-08-20 13:13 ` Cyber Fonic
2019-08-20 13:28 ` Don A. Bailey
2019-08-23 18:45 ` Ethan Gardener
2019-08-23 19:41 ` Don Bailey
2019-07-26 13:16 [9fans] Plan 9 C compiler for Xtensa CPUs cinap_lenrek
2023-12-04 23:20 David Boddie
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