* [9fans] high precision timings
@ 2011-09-04 17:47 Steve Simon
2011-09-04 18:34 ` erik quanstrom
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Steve Simon @ 2011-09-04 17:47 UTC (permalink / raw)
To: 9fans
after the recent discussions on nsec()...
does anyone already have the snippet of code to do fine grained
timeings on the x86 platform using the hardware performance counters?
I would use nsec() but I'am timing systemcalls so I expect my results
would be swamped by nsec()'s performance.
Thanks
-Steve
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
2011-09-04 17:47 [9fans] high precision timings Steve Simon
@ 2011-09-04 18:34 ` erik quanstrom
2011-09-05 4:42 ` ron minnich
[not found] ` <CAP6exYLkin_LGZCDCGYcSLqTNHZOfPWc6f=S0LLDG0q_WEhdZA@mail.gmail.c>
2 siblings, 0 replies; 7+ messages in thread
From: erik quanstrom @ 2011-09-04 18:34 UTC (permalink / raw)
To: steve, 9fans
On Sun Sep 4 13:48:31 EDT 2011, steve@quintile.net wrote:
> after the recent discussions on nsec()...
>
> does anyone already have the snippet of code to do fine grained
> timeings on the x86 platform using the hardware performance counters?
>
> I would use nsec() but I'am timing systemcalls so I expect my results
> would be swamped by nsec()'s performance.
i wrote up a little demo using a varient of nsec and
using the x86 cycle counter, RDTSC.
the source is in /n/sources/contrib/quanstro/highprec.
i'd recommend doing timings on your particular hardware.
here are my results:
; aux/cpuid -i
AMD Phenom(tm) II X4 965 Processor
; 8.out
nsec latency 25729ns
nsec latency 24554ns
cycle hz = 3393000000
cycles latency 88 cycles; 25 ns
cycles latency 78 cycles; 22 ns
ladd; aux/cpuid -i
Intel(R) Atom(TM) CPU 330 @ 1.60GHz
ladd; 8.out
nsec latency 39501ns
nsec latency 38901ns
cycle hz = 1604000000
cycles latency 60 cycles; 37 ns
cycles latency 48 cycles; 29 ns
new; aux/cpuid -i
Intel(R) Xeon(R) CPU E31220 @ 3.10GHz
new; 8.out
nsec latency 8591ns
nsec latency 9155ns
cycle hz = 3105000000
cycles latency 28 cycles; 9 ns
cycles latency 28 cycles; 9 ns
chula; aux/cpuid -i
Intel(R) Core(TM) i7 CPU 920 @ 2.67GHz
chula; 8.out
nsec latency 14319ns
nsec latency 14451ns
cycle hz = 2660000000
cycles latency 40 cycles; 15 ns
cycles latency 32 cycles; 12 ns
it seems like you can get ±10ns at a few 10s of
ns latency with _cycles and ±10µs at a few 10s
of µs latency with /dev/bintime.
- erik
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
2011-09-04 17:47 [9fans] high precision timings Steve Simon
2011-09-04 18:34 ` erik quanstrom
@ 2011-09-05 4:42 ` ron minnich
2011-09-05 4:50 ` s s
2011-09-05 6:27 ` dexen deVries
[not found] ` <CAP6exYLkin_LGZCDCGYcSLqTNHZOfPWc6f=S0LLDG0q_WEhdZA@mail.gmail.c>
2 siblings, 2 replies; 7+ messages in thread
From: ron minnich @ 2011-09-05 4:42 UTC (permalink / raw)
To: Fans of the OS Plan 9 from Bell Labs
The TSC has been badly abused by the chip makers over the last ten
years. It went through a period of time where it had poor accuracy. Be
sure to look at your hardware and make sure it's a later chip which
will give you reasonable TSC behavior.
ron
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
[not found] ` <CAP6exYLkin_LGZCDCGYcSLqTNHZOfPWc6f=S0LLDG0q_WEhdZA@mail.gmail.c>
@ 2011-09-05 4:48 ` erik quanstrom
0 siblings, 0 replies; 7+ messages in thread
From: erik quanstrom @ 2011-09-05 4:48 UTC (permalink / raw)
To: 9fans
On Mon Sep 5 00:43:49 EDT 2011, rminnich@gmail.com wrote:
> The TSC has been badly abused by the chip makers over the last ten
> years. It went through a period of time where it had poor accuracy. Be
> sure to look at your hardware and make sure it's a later chip which
> will give you reasonable TSC behavior.
my example code wires the proc to a mach to avoid extreme TSC problems
such as on some ht p4 machines.
perhaps that's a bit extreme. it's been a long time since i've used a machine
with a broken cycle counter. (last purchase: 2006.)
- erik
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
2011-09-05 4:42 ` ron minnich
@ 2011-09-05 4:50 ` s s
2011-09-05 4:53 ` s s
2011-09-05 6:27 ` dexen deVries
1 sibling, 1 reply; 7+ messages in thread
From: s s @ 2011-09-05 4:50 UTC (permalink / raw)
To: Fans of the OS Plan 9 from Bell Labs
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On Mon, Sep 5, 2011 at 12:42 AM, ron minnich <rminnich@gmail.com> wrote:
> The TSC has been badly abused by the chip makers over the last ten
> years. It went through a period of time where it had poor accuracy. Be
> sure to look at your hardware and make sure it's a later chip which
> will give you reasonable TSC behavior.
>
> ron
>
Not concerned just yet about the accuracy of the hardware.
Just wondering why the example client outputs "invalid arguments", and the
server outputs ...
2011/09/05 00:37:14 bad client connection: [::1]:57429
Still happy to see something compile, run, and give output, though.
- Leonard
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
2011-09-05 4:50 ` s s
@ 2011-09-05 4:53 ` s s
0 siblings, 0 replies; 7+ messages in thread
From: s s @ 2011-09-05 4:53 UTC (permalink / raw)
To: Fans of the OS Plan 9 from Bell Labs
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Sorry, wrong thread.
- Leonard
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [9fans] high precision timings
2011-09-05 4:42 ` ron minnich
2011-09-05 4:50 ` s s
@ 2011-09-05 6:27 ` dexen deVries
1 sibling, 0 replies; 7+ messages in thread
From: dexen deVries @ 2011-09-05 6:27 UTC (permalink / raw)
To: Fans of the OS Plan 9 from Bell Labs
On Monday 05 of September 2011 06:42:35 ron minnich wrote:
> The TSC has been badly abused by the chip makers over the last ten
> years. It went through a period of time where it had poor accuracy. Be
> sure to look at your hardware and make sure it's a later chip which
> will give you reasonable TSC behavior.
FWIW, Pentium M had `broken' TSC behavior. during boot, linux complains, ``TSC
halts in idle'' and refuses to use it as clock source. apparently TSC counts
actual CPU clock impulses, and those are slowed down in idle.
--
dexen deVries
[[[↓][→]]]
For example, if the first thing in the file is:
<?kzy irefvba="1.0" rapbqvat="ebg13"?>
an XML parser will recognize that the document is stored in the traditional
ROT13 encoding.
(( Joe English, http://www.flightlab.com/~joe/sgml/faq-not.txt ))
^ permalink raw reply [flat|nested] 7+ messages in thread
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2011-09-04 17:47 [9fans] high precision timings Steve Simon
2011-09-04 18:34 ` erik quanstrom
2011-09-05 4:42 ` ron minnich
2011-09-05 4:50 ` s s
2011-09-05 4:53 ` s s
2011-09-05 6:27 ` dexen deVries
[not found] ` <CAP6exYLkin_LGZCDCGYcSLqTNHZOfPWc6f=S0LLDG0q_WEhdZA@mail.gmail.c>
2011-09-05 4:48 ` erik quanstrom
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