From: Szabolcs Nagy <nsz@port70.net>
To: Rich Felker <dalias@libc.org>
Cc: 张飞 <zhangfei@nj.iscas.ac.cn>,
"A. Wilcox" <awilfox@adelielinux.org>,
musl@lists.openwall.com
Subject: Re: [musl] [PATCH]Implementation of strlen function in riscv64 architecture
Date: Tue, 11 Apr 2023 14:57:24 +0200 [thread overview]
Message-ID: <20230411125724.GL3630668@port70.net> (raw)
In-Reply-To: <20230322121529.GV4163@brightrain.aerifal.cx>
* Rich Felker <dalias@libc.org> [2023-03-22 08:15:30 -0400]:
> Regarding the code submitted for review, I'm pretty sure it's buggy
> because it doesn't seem to do anything with alignment. If you pass it
> a pointer to the last byte of a page whose contents are zero, it will
> attempt to load the rest of the vector from the next page, and fault.
the aarch64 sve isa extension has 'first faulting register' mask
and there are load/store instructions that set it instead of
actually faulting when a vector goes off at the end of a page.
i suspect riscv copied this piece of architecture (as well as the
variable vector length).
next prev parent reply other threads:[~2023-04-11 12:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 6:21 张飞
2023-03-22 6:27 ` A. Wilcox
2023-03-22 12:15 ` Rich Felker
2023-04-11 12:57 ` Szabolcs Nagy [this message]
2023-04-10 5:59 ` 张飞
2023-04-11 12:48 ` Szabolcs Nagy
2023-04-19 7:22 ` 张飞
2023-04-19 22:39 ` enh
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