Re: Re: [musl] [PATCH]Implementation of strlen function in riscv64 architecture

[张飞 <zhangfei@nj.iscas.ac.cn>]

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I have made modifications to the assembly implementation of the riscv64 strlen function, mainly 
focusing on address alignment processing to avoid the problem of data crossing 
pages during vector instruction memory access.

I think the assembly implementation of strlen is necessary. In glibc, 
X86_64, aarch64, alpha, and others all have assembly implementations of this function, 
while for riscv64, it is blank.
I have also analyzed the test sets of Spec2006 and Spec2017, and the strlen function is also a hot topic.

Please review the patch again and look forward to your reply.

Fei Zhang

> -----原始邮件-----
&gt; 发件人: "A. Wilcox" <awilfox@adelielinux.org>
&gt; 发送时间: 2023-03-22 14:27:33 (星期三)
&gt; 收件人: musl@lists.openwall.com
&gt; 抄送: 
&gt; 主题: Re: [musl] [PATCH]Implementation of strlen function in riscv64 architecture
&gt; 
&gt; The content of the message was sent as an image.
&gt; 
&gt; For those who cannot view images, I've reproduced the text below:
&gt; 
&gt; On Mar 22, 2023, at 1:21 AM, 张飞 <zhangfei@nj.iscas.ac.cn> wrote:
&gt; &gt; 
&gt; &gt; Hi:
&gt; &gt; 
&gt; &gt; I implemented vectorization of the strlen function in the riscv64
&gt; &gt; architecture, which is controlled by __riscv_vector definition. Due
&gt; &gt; to lack of support for risc-v V expansion in hardware, I conducted
&gt; &gt; performance tests on a simulator, which was more than 10 times the
&gt; &gt; performance achieved in C language. In terms of functionality, I
&gt; &gt; tested the string length from 1 byte to 64 Mb, and the alignment of
&gt; &gt; different addresses at the beginning of the string.
&gt; &gt; 
&gt; &gt; 
&gt; &gt; Please review it.I'm Looking forward to your reply,thanks.
&gt; &gt; 
&gt; &gt; 
&gt; &gt; 
&gt; &gt; Fei Zhang
&gt; &gt; <strlen.s>


</strlen.s></zhangfei@nj.iscas.ac.cn></awilfox@adelielinux.org>

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diff -uprN src/string/riscv64/strlen.S src/string/riscv64/strlen.S
--- src/string/riscv64/strlen.S	1970-01-01 08:00:00.000000000 +0800
+++ src/string/riscv64/strlen.S	2023-04-10 11:28:45.301698194 +0800
@@ -0,0 +1,46 @@
+# size_t strlen(const char *str)
+# a0 holds *str
+.global strlen
+.type strlen,@function
+strlen:
+    mv t0, a0             # Save start
+#ifdef __riscv_vector
+    csrr t1, vlenb 
+    addi t1, t1, -1
+    add  a3, t0, t1
+    not  t1, t1
+    and  a3, a3, t1
+    sub  a4, a3, t0
+    beq  a3, t0, loop /* if already aligned*/
+
+unaligned:
+    lbu     t1, 0(t0)
+    beqz    t1, found
+    addi    t0, t0, 1
+    blt     t0, a3, unaligned
+
+loop:
+    vsetvli a1, x0, e8, m8, ta, ma  # Vector of bytes of maximum length
+    vle8ff.v v8, (t0)      # Load bytes
+    csrr a1, vl           # Get bytes read
+    vmseq.vi v0, v8, 0    # Set v0[i] where v8[i] = 0
+    vfirst.m a2, v0       # Find first set bit
+    add t0, t0, a1        # Bump pointer
+    bltz a2, loop         # Not found?
+
+    add a3, a3, a1        # Sum start + bump
+    add t0, t0, a2        # Add index
+    sub a3, t0, a3        # Subtract start address+bump
+    add a0, a3, a4
+    ret
+#else
+loop:
+    lbu t1, 0(t0)
+    beqz t1, found
+    addi t0, t0, 1
+    j loop
+#endif
+
+found:
+    sub a0, t0, a0
+    ret