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From: 张飞 <zhangfei@nj.iscas.ac.cn>
To: musl@lists.openwall.com
Subject: [musl] [PATCH]Implementation of strlen function in riscv64 architecture
Date: Wed, 22 Mar 2023 14:21:31 +0800 (GMT+08:00)	[thread overview]
Message-ID: <3e056826.7b26.18707fad3e2.Coremail.zhangfei@nj.iscas.ac.cn> (raw)


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Hi:
Iimplementedvectorizationofthestrlenfunctionintheriscv64architecture, whichiscontrolledby__riscv_vectordefinition.Duetolackofsupportforrisc-vVexpansioninhardware, Iconductedperformancetestsonasimulator, whichwasmorethan10timestheperformanceachievedinClanguage. Intermsoffunctionality, Itestedthestringlengthfrom1byteto64Mb, andthealignmentofdifferentaddressesatthebeginningofthestring.




Please review it.I'm Looking forward to your reply,thanks.




Fei Zhang







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    .text
    .balign 4
    .global strlen
# size_t strlen(const char *str)
# a0 holds *str

strlen:
    mv t1, a0             # Save start

#ifdef __riscv_vector
loop:
    vsetvli t0, x0, e8, m8, ta, ma  # Vector of bytes of maximum length
    vle8ff.v v8, (t1)      # Load bytes
    csrr t0, vl           # Get bytes read
    vmseq.vi v0, v8, 0    # Set v0[i] where v8[i] = 0
    vfirst.m t2, v0       # Find first set bit
    add t1, t1, t0        # Bump pointer
    bltz t2, loop         # Not found?

    add a0, a0, t0        # Sum start + bump
    add t1, t1, t2        # Add index
    sub a0, t1, a0        # Subtract start address+bump
#else
1:
    lbu t0, 0(t1)
    beqz t0, 2f
    addi t1, t1, 1
    j 1b
2:
    sub a0, t1, a0
#endif
    ret


             reply	other threads:[~2023-03-22  6:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-22  6:21 张飞 [this message]
2023-03-22  6:27 ` A. Wilcox
2023-03-22 12:15   ` Rich Felker
2023-04-11 12:57     ` Szabolcs Nagy
2023-04-10  5:59   ` 张飞
2023-04-11 12:48     ` Szabolcs Nagy
2023-04-19  7:22       ` 张飞
2023-04-19 22:39         ` enh

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