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From: Khem Raj <raj.khem@gmail.com>
To: musl@lists.openwall.com
Subject: Re: [musl] RISC-V 32bit port in MUSL upstream
Date: Wed, 27 Sep 2023 11:09:51 -0700	[thread overview]
Message-ID: <CAMKF1sqwBTZk=sboaDFjJhB-FcxUiwHKGE+HVtEZcAt3MJfNrg@mail.gmail.com> (raw)
In-Reply-To: <MN2PR02MB6397620A8A5FEB81C1C12C69F0C2A@MN2PR02MB6397.namprd02.prod.outlook.com>

On Wed, Sep 27, 2023 at 9:36 AM Venkata Ramanaiah Nalamothu (QUIC)
<quic_vnalamot@quicinc.com> wrote:
>
> Hi,
>
>
>
> It looks like the RISC-V 32bit support is not there yet in MUSL upstream and there were past discussions on adding the support (https://www.openwall.com/lists/musl/2020/09/04/2).
>
>

we maintain these patchset for yocto -
https://github.com/riscv/meta-riscv/tree/master/recipes-core/musl/musl

I also have a github tree.
https://github.com/kraj/musl/commits/kraj/master/

>
> Is there any ongoing effort to add RISC-V 32bit port in MUSL? If yes, any idea when that might get completed?
>
>
>
> Ram Nalamothu

  reply	other threads:[~2023-09-27 18:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-27 16:36 Venkata Ramanaiah Nalamothu (QUIC)
2023-09-27 18:09 ` Khem Raj [this message]
2023-09-28  4:39   ` Venkata Ramanaiah Nalamothu (QUIC)
2023-09-29 14:42     ` Markus Wichmann
2023-10-05  3:12       ` Venkata Ramanaiah Nalamothu (QUIC)
2023-10-05  3:23       ` Venkata Ramanaiah Nalamothu (QUIC)
2023-11-08 15:00         ` Venkata Ramanaiah Nalamothu (QUIC)
2024-02-26  2:16           ` Rich Felker
2024-02-26  6:17             ` Khem Raj
2024-02-27  3:29               ` Rich Felker

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