RE: [musl] RISC-V 32bit port in MUSL upstream

["Venkata Ramanaiah Nalamothu (QUIC)" <quic_vnalamot@quicinc.com>]

Thank you very much for sharing the patch set/development branch.

Looking at your github tree commit history, it seems the tree is actively maintained.
May I know what is stopping from pushing these changes into MUSL community version?
Were there any technical challenges or someone just need to find time to work with the community to get the changes reviewed/merged?

-----Original Message-----
From: Khem Raj <raj.khem@gmail.com> 
Sent: Wednesday, September 27, 2023 11:40 PM
To: musl@lists.openwall.com
Subject: Re: [musl] RISC-V 32bit port in MUSL upstream

On Wed, Sep 27, 2023 at 9:36 AM Venkata Ramanaiah Nalamothu (QUIC) <quic_vnalamot@quicinc.com> wrote:
>
> Hi,
>
>
>
> It looks like the RISC-V 32bit support is not there yet in MUSL upstream and there were past discussions on adding the support (https://www.openwall.com/lists/musl/2020/09/04/2).
>
>

we maintain these patchset for yocto -
https://github.com/riscv/meta-riscv/tree/master/recipes-core/musl/musl

I also have a github tree.
https://github.com/kraj/musl/commits/kraj/master/

>
> Is there any ongoing effort to add RISC-V 32bit port in MUSL? If yes, any idea when that might get completed?
>
>
>
> Ram Nalamothu