RE: [Caml-list] Efficient OCaml multicore -- roadmap?

[Jon Harrop <jonathandeanharrop@googlemail.com>]

Gerd wrote:
> I wrote:
> > Yes. The hardware maintains the illusion of shared memory so the
> programmer only need optimize on the basis of an accurate cost model. There is
> no need to burden the programmer with message passing and manual memory
> management.
> 
> I don't understand this last sentence. Message passing is just an abstract
> concept (i.e. an interface) which can e.g. be implemented with a shared buffer
> (or the illusion thereof) or other data structure that decouples sender and
> receiver processes.

Similarly, caches are an abstract concept that can be implemented in different ways. We could also emulate the CPU cache in software and provide an abstract interface for our emulated cache. Does this also seem like a good idea given that the context is multicore parallelism, i.e. performance?

> Are you against using the right interfaces when they are
> appropriate?

As long as the hardware provides shared memory then using shared memory directly is the right interface in the context of multicore parallelism.

> We don't want to burden the programmer with too low-level
> details, do we?

Exactly. In this context, message passing is a low-level implementation detail that can and should be confined to the hardware layer. The programmer should be oblivious to the number of cores and threads and oblivious to the low-level communication going on between them and to the sender and receiver processes you mentioned. They need only be aware of high-level concepts like cache complexity. This makes parallel programming easy and that is why it has become the defacto-standard approach for multicore programming. After all, we could easily write parallel programs using manual message passing between explicit senders and receivers but it is harder and slower and, therefore, completely pointless.

I should note that your abstraction is of value in the context of concurrent programming when throughput is irrelevant because it can be used to expose a much simpler "memory model" but that is not relevant to this discussion about multicore parallelism.

Cheers,
Jon.