Re: [9front] core-i5(TypeSNB) and vesa mode

[cinap_lenrek@felloff.net]

> I had intended to follow those lines, because I had no other guides for this.
> Maybe I made something wrong?

i dont know that. all i see is your changes without
explaination and the intel documentation. if theres
a difference between these, i have to ask why they
differ. sometimes, documentation can be wrong. but
you only know that if you *tried* it the documented
way first... which i dont know if you did that or not.

now something we can test:

this is what i got for the fdi link training code for
SNB now which is based on the documentation, but cannot
test it.

i'm not sure rximr unmasking is actually needed, but
linux driver does it. (tho they handle interrupts
and we dont).

			/* unmask bit lock and symbol lock bits */
			csr(igfx, p->fdi->rximr.a, 3<<8, 0);

			p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern1 */
			p->fdi->rxctl.v |= 1<<31;	/* enable */
			loadreg(igfx, p->fdi->rxctl);

			p->fdi->txctl.v &= ~(3<<8);	/* link train pattern1 */
			p->fdi->txctl.v |= 1<<31;	/* enable */
			loadreg(igfx, p->fdi->txctl);

			/* wait for bit lock */
			for(i=0; i<10; i++){
				sleep(1);
				if(rr(igfx, p->fdi->rxiir.a) & (1<<8))
					break;
			}
			csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
	
			/* switch to link train pattern2 */
			csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
			csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8);

			/* wait for symbol lock */
			for(i=0; i<10; i++){
				sleep(1);
				if(rr(igfx, p->fdi->rxiir.a) & (1<<9))
					break;
			}
			csr(igfx, p->fdi->rxiir.a, 0, 1<<9);

			/* switch to link train normal */
			csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
			csr(igfx, p->fdi->txctl.a, 0, 3<<8);

			/* wait idle pattern time */
			sleep(5);

full diff follows... note that i added rxiir and rximr softregs
to the Fdi structure. this is because there can be multiple fdi
links.

diff -r 7ecc3cd531be sys/src/cmd/aux/vga/igfx.c
--- a/sys/src/cmd/aux/vga/igfx.c	Sun Jul 24 15:13:14 2016 +0200
+++ b/sys/src/cmd/aux/vga/igfx.c	Thu Jul 28 14:57:05 2016 +0200
@@ -89,6 +89,8 @@
 
 	Reg	rxctl;		/* FDI_RX_CTL */
 	Reg	rxmisc;		/* FDI_RX_MISC */
+	Reg	rxiir;		/* FDI_RX_IIR */
+	Reg	rximr;		/* FDI_RX_IMR */
 	Reg	rxtu[2];	/* FDI_RX_TUSIZE */
 };
 
@@ -276,6 +278,10 @@
 
 		p->fdi->rxctl = snarfreg(igfx, o + 0x1000c);
 		p->fdi->rxmisc = snarfreg(igfx, o + 0x10010);
+
+		p->fdi->rxiir = snarfreg(igfx, o + 0x10014);
+		p->fdi->rximr = snarfreg(igfx, o + 0x10018);
+
 		p->fdi->rxtu[0] = snarfreg(igfx, o + 0x10030);
 		p->fdi->rxtu[1] = snarfreg(igfx, o + 0x10038);
 
@@ -297,7 +303,6 @@
 	/* cursor plane */
 	switch(igfx->type){
 	case TypeIVB:
-	case TypeSNB:
 		p->cur->cntr	= snarfreg(igfx, 0x70080 + x*0x1000);
 		p->cur->base	= snarfreg(igfx, 0x70084 + x*0x1000);
 		p->cur->pos	= snarfreg(igfx, 0x70088 + x*0x1000);
@@ -305,7 +310,8 @@
 	case TypeG45:
 		p->dsp->pos	= snarfreg(igfx, 0x7018C + x*0x1000);
 		p->dsp->size	= snarfreg(igfx, 0x70190 + x*0x1000);
-
+		/* wet floor */
+	case TypeSNB:
 		p->cur->cntr	= snarfreg(igfx, 0x70080 + x*0x40);
 		p->cur->base	= snarfreg(igfx, 0x70084 + x*0x40);
 		p->cur->pos	= snarfreg(igfx, 0x70088 + x*0x40);
@@ -320,10 +326,13 @@
 		return -1;
 	switch(igfx->pci->did){
 	case 0x0166:	/* 3rd Gen Core - ThinkPad X230 */
+	case 0x0152:	/* 2nd/3rd Gen Core - Core-i3 */
 		return TypeIVB;
+	case 0x0102:	/* Dell Optiplex 790 */
 	case 0x0126:	/* Thinkpad X220 */
 		return TypeSNB;
 	case 0x27a2:	/* GM945/82940GML - ThinkPad X60 Tablet */
+	case 0x29a2:	/* 82P965/G965 HECI desktop */
 	case 0x2a02:	/* GM965/GL960/X3100 - ThinkPad X61 Tablet */
 	case 0x2a42:	/* 4 Series Mobile - ThinkPad X200 */
 		return TypeG45;
@@ -858,10 +867,10 @@
 		break;
 
 	case PortVGA:
-		if(igfx->npipe > 2)
+		if(igfx->type == TypeG45)
+			x = (igfx->adpa.v >> 30) & 1;
+		else
 			x = (igfx->adpa.v >> 29) & 3;
-		else
-			x = (igfx->adpa.v >> 30) & 1;
 		igfx->adpa.v |= (1<<31);
 		if(igfx->type == TypeG45){
 			igfx->adpa.v &= ~(3<<10);	/* Monitor DPMS: on */
@@ -876,10 +885,10 @@
 		break;
 
 	case PortLCD:
-		if(igfx->npipe > 2)
+		if(igfx->type == TypeG45)
+			x = (igfx->lvds.v >> 30) & 1;
+		else
 			x = (igfx->lvds.v >> 29) & 3;
-		else
-			x = (igfx->lvds.v >> 30) & 1;
 		igfx->lvds.v |= (1<<31);
 		igfx->ppcontrol.v |= 5;
 
@@ -1053,8 +1062,8 @@
 		loadreg(igfx, p->fdi->rxctl);
 		sleep(5);
 		p->fdi->txctl.v &= ~(7<<8 | 1);	/* clear auto training bits */
-		p->fdi->txctl.v &= ~(1<<31);
-		p->fdi->rxctl.v |= (1<<14);	/* enable pll */
+		p->fdi->txctl.v &= ~(1<<31);	/* disable */
+		p->fdi->txctl.v |= (1<<14);	/* enable pll */
 		loadreg(igfx, p->fdi->txctl);
 		sleep(5);
 	}
@@ -1102,21 +1111,61 @@
 		loadreg(igfx, p->fdi->rxtu[0]);
 		loadreg(igfx, p->fdi->rxmisc);
 
-		p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern 00 */
-		p->fdi->rxctl.v |= 1<<10;	/* auto train enable */
-		p->fdi->rxctl.v |= 1<<31;	/* enable */
-		loadreg(igfx, p->fdi->rxctl);
+		if(igfx->type == TypeSNB){
+			/* unmask bit lock and symbol lock bits */
+			csr(igfx, p->fdi->rximr.a, 3<<8, 0);
 
-		p->fdi->txctl.v &= ~(3<<8);	/* link train pattern 00 */
-		p->fdi->txctl.v |= 1<<10;	/* auto train enable */
-		p->fdi->txctl.v |= 1<<31;	/* enable */
-		loadreg(igfx, p->fdi->txctl);
+			p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern1 */
+			p->fdi->rxctl.v |= 1<<31;	/* enable */
+			loadreg(igfx, p->fdi->rxctl);
 
-		/* wait for link training done */
-		for(i=0; i<200; i++){
+			p->fdi->txctl.v &= ~(3<<8);	/* link train pattern1 */
+			p->fdi->txctl.v |= 1<<31;	/* enable */
+			loadreg(igfx, p->fdi->txctl);
+
+			/* wait for bit lock */
+			for(i=0; i<10; i++){
+				sleep(1);
+				if(rr(igfx, p->fdi->rxiir.a) & (1<<8))
+					break;
+			}
+			csr(igfx, p->fdi->rxiir.a, 0, 1<<8);
+	
+			/* switch to link train pattern2 */
+			csr(igfx, p->fdi->rxctl.a, 3<<8, 1<<8);
+			csr(igfx, p->fdi->txctl.a, 3<<8, 1<<8);
+
+			/* wait for symbol lock */
+			for(i=0; i<10; i++){
+				sleep(1);
+				if(rr(igfx, p->fdi->rxiir.a) & (1<<9))
+					break;
+			}
+			csr(igfx, p->fdi->rxiir.a, 0, 1<<9);
+
+			/* switch to link train normal */
+			csr(igfx, p->fdi->rxctl.a, 0, 3<<8);
+			csr(igfx, p->fdi->txctl.a, 0, 3<<8);
+
+			/* wait idle pattern time */
 			sleep(5);
-			if(rr(igfx, p->fdi->txctl.a) & 2)
-				break;
+		} else {
+			p->fdi->rxctl.v &= ~(3<<8);	/* link train pattern 00 */
+			p->fdi->rxctl.v |= 1<<10;	/* auto train enable */
+			p->fdi->rxctl.v |= 1<<31;	/* enable */
+			loadreg(igfx, p->fdi->rxctl);
+
+			p->fdi->txctl.v &= ~(3<<8);	/* link train pattern 00 */
+			p->fdi->txctl.v |= 1<<10;	/* auto train enable */
+			p->fdi->txctl.v |= 1<<31;	/* enable */
+			loadreg(igfx, p->fdi->txctl);
+
+			/* wait for link training done */
+			for(i=0; i<200; i++){
+				sleep(5);
+				if(rr(igfx, p->fdi->txctl.a) & 2)
+					break;
+			}
 		}
 	}
 


--
cinap