Re: [9front] core-i5(TypeSNB) and vesa mode

[cinap_lenrek@felloff.net]

		if(igfx->type == TypeSNB) {
			csr(igfx, 0xC6200, 1<<11, 2);	/* pch ref souce & ssc enable */
			sleep(5);
		}

0xC6200 is drefctl - Diplsay Reference Clock Control Register

enablepipe() is the wrong place to play arround with
the reference clock as this function is called for each
pipe! the right place to set the value would be initdpll()
by setting igfx->drefctl.v.

the whole idea is that you program the *soft* registers
in init(), and have them only get loaded into *hardware*
from load() only.

snarf:	hardregs -> softregs
dump:	print softregs
init:	program softregs
load:	softregs -> hardregs

like:
		if(igfx->type == TypeSNB){	/* pch ref souce & ssc enable */
			igfx->drefctl.v &= ~(1<<11);
			igfx->drefctl.v |= 2;
		}

this effecively becomes igfx->drefctl.v |= 2; only because
bits 3<<11 are cleared before, so clearing 1<<11 is a non-op.

now bit 1 (1<<1) is 128MHz_SSC1(-0.5%) modulation_en, which is
not what the comment says. and it should not be enabled
unconditionally, but only when the SSC1 clock is actually used.

note that the SSC clocks are only used as a ref source for the dpll
for LVDS (PortLCD):

		/*
		 * PLL Reference Input Select:
		 * 000	DREFCLK		(default is 120 MHz) for DAC/HDMI/DVI/DP
		 * 001	Super SSC	120MHz super-spread clock
		 * 011	SSC		Spread spectrum input clock (120MHz default) for LVDS/DP
		 */
		dpll = igfx->pipe[x].fdi->dpll;
		dpll->ctrl.v &= ~(7<<13);
		dpll->ctrl.v |= (port == PortLCD ? 3 : 0) << 13;

the current code does the following:

- when LVDS (PortLCD) we set 120MHz_SSC_source_en to "Integrated source" (2<<11)
  and 128MHz_SSC4_modulation_en.
- for all other ports, we set 128MHz_nonspread_source_en to "Integrated source" (2<<9)
- set the reference clock input select on the dpll to the enabled reference source

the modeset sequence of SNB says just to enable the "PCH clock reference source",
which doesnt specify which clock (depends on what ports you are going to enable).

if you are interested:

https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf

has a diagram of the clocks on page 34. for SNB this should be similar as
the drefctl register shares many settings.

--
cinap