From: kokamoto@hera.eonet.ne.jp
To: 9front@9front.org
Subject: Re: [9front] core-i5(TypeSNB) and vesa mode
Date: Fri, 29 Jul 2016 20:49:11 +0900 [thread overview]
Message-ID: <72251590bdac4e057fe43197791c2928@titan.jitaku.localdomain> (raw)
In-Reply-To: <8e1f73ab85b73b6ea3288a5600e1ff77@felloff.net>
Those may relate to the fact that DP port dosen't work
by my code, as I said before. However, on Analog VGA display, it is
working now. Now, I'm cocerned with VGA display, because I want
to use this machine on that environment.
Kenji
>> It sounds like the same as I did here.
>
> no, it is not. you put your code *before* the ivy bridge
> fdi link code which works differently resulting in the
> exeuction of patterns 2 followed by auto-train mode.
> this enables the fdi with train pattern 2, not pattern 1
> which is invalid.
>
> also you poll the wrong interrupt register. you poll the
> DEIIR (0x44008) which has bit definitions:
>
> https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part2.pdf
> section 2.5.1 "Display Engine Interrupt Registers Bit Definition"
>
> bit 9: Pipe_B_CRC_error; This is an active high pulse on the Pipe B CRC error.
> bit 8: Pipe_B_FIFO_underrun; This is an active high level for the duration of the Pipe B FIFO underrun.
>
> /* TypeSNB or TypeIVB */
> /* enable fdi */
> loadreg(igfx, p->fdi->rxtu[1]);
> loadreg(igfx, p->fdi->rxtu[0]);
> loadreg(igfx, p->fdi->rxmisc);
> /* from here K.Okamoto */
> if (igfx->type == TypeSNB){
> for(i=0;i<10;i++){ /* ensure Receive IIR, K.Okamoto */
> if(rr(igfx, 0x44008) & 1<<8)
> break;
> }
> p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 1 enable */
> p->fdi->rxctl.v |= (1<<8); /* link train pattern 2 enable */
> p->fdi->rxctl.v |= 1<<31; /* enable FDI pll */
> loadreg(igfx, p->fdi->rxctl);
> p->fdi->txctl.v &= ~(3<<8); /* link train pattern 1 enable */
> p->fdi->txctl.v |= (1<<8); /* link train pattern 2 enable */
> p->fdi->txctl.v |= 1<<31; /* enable FDI pll */
> loadreg(igfx, p->fdi->txctl);
> for(i=0;i<10;i++){
> if(rr(igfx, 0x44008) & 1<<9) /* ensure Receive IIR, K.Okamoto */
> break;
> }
> /* to here K.Okamoto */
> }
> p->fdi->rxctl.v &= ~(3<<8); /* link train pattern 1 enable[default] */
> p->fdi->rxctl.v |= 1<<10; /* auto train enable */
> p->fdi->rxctl.v |= 1<<31; /* enable FDI pll */
> loadreg(igfx, p->fdi->rxctl);
>
> p->fdi->txctl.v &= ~(3<<8); /* link train pattern 1 enable[default] */
> p->fdi->txctl.v |= 1<<10; /* auto train enable */
> p->fdi->txctl.v |= 1<<31; /* enable FDI pll */
> loadreg(igfx, p->fdi->txctl);
>
> /* wait for link training done */
> for(i=0; i<200; i++){
> sleep(5);
> if(rr(igfx, p->fdi->txctl.a) & 2) /* auto train done */
> break;
> }
>
>> I'm not interested now on it, because I have now another
>> problem of stability of high resolution(up to 1680x1050x32
>
> i cannot help you then.
>
>> Kenji
>
> --
> cinap
next prev parent reply other threads:[~2016-07-29 11:49 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-02 1:13 core-i3 " kokamoto
2016-07-02 4:56 ` [9front] " kokamoto
2016-07-03 0:17 ` kokamoto
2016-07-05 12:26 ` cinap_lenrek
2016-07-06 0:18 ` kokamoto
2016-07-06 9:49 ` cinap_lenrek
2016-07-06 23:26 ` kokamoto
2016-07-07 3:05 ` kokamoto
2016-07-08 0:00 ` kokamoto
2016-07-08 6:21 ` kokamoto
2016-07-08 6:39 ` kokamoto
2016-07-08 9:26 ` cinap_lenrek
2016-07-09 1:49 ` kokamoto
2016-07-09 2:16 ` cinap_lenrek
2016-07-09 2:38 ` kokamoto
2016-07-09 6:27 ` kokamoto
2016-07-09 12:48 ` cinap_lenrek
2016-07-12 6:32 ` kokamoto
2016-07-12 12:15 ` kokamoto
2016-07-21 1:36 ` kokamoto
2016-07-23 6:19 ` kokamoto
2016-07-23 9:50 ` kokamoto
2016-07-23 12:27 ` cinap_lenrek
2016-07-23 23:50 ` kokamoto
2016-07-24 0:16 ` kokamoto
2016-07-25 4:15 ` [9front] core-i5 " kokamoto
2016-07-25 4:19 ` [9front] core-i5(TypeSNB) " kokamoto
2016-07-27 0:12 ` kokamoto
2016-07-27 9:57 ` cinap_lenrek
2016-07-27 13:24 ` kokamoto
2016-07-27 13:42 ` kokamoto
2016-07-27 19:30 ` cinap_lenrek
2016-07-28 0:37 ` kokamoto
2016-07-28 2:19 ` kokamoto
2016-07-28 9:28 ` cinap_lenrek
2016-07-27 20:01 ` cinap_lenrek
2016-07-27 22:37 ` cinap_lenrek
2016-07-28 0:39 ` kokamoto
2016-07-28 10:03 ` cinap_lenrek
2016-07-28 11:31 ` kokamoto
2016-07-28 13:26 ` cinap_lenrek
2016-08-01 6:51 ` kokamoto
2016-07-28 10:20 ` cinap_lenrek
2016-07-28 11:34 ` kokamoto
2016-07-28 13:31 ` cinap_lenrek
2016-07-28 23:48 ` kokamoto
2016-07-29 0:58 ` kokamoto
2016-07-29 9:00 ` cinap_lenrek
2016-07-29 11:42 ` kokamoto
2016-07-29 8:15 ` cinap_lenrek
2016-07-29 11:49 ` kokamoto [this message]
2016-07-29 13:01 ` cinap_lenrek
2016-07-29 23:41 ` kokamoto
2016-07-29 23:43 ` cinap_lenrek
2016-08-05 23:58 ` kokamoto
2016-08-06 5:51 ` kokamoto
2016-08-06 12:55 ` kokamoto
2016-08-06 13:05 ` cinap_lenrek
2016-08-06 13:58 ` cinap_lenrek
2016-08-07 0:08 ` kokamoto
2016-08-07 0:38 ` cinap_lenrek
2016-08-09 1:29 ` kokamoto
2016-08-09 8:47 ` cinap_lenrek
2016-08-13 4:21 ` kokamoto
2016-08-09 9:40 ` cinap_lenrek
2016-08-12 23:27 ` kokamoto
2016-08-13 1:32 ` cinap_lenrek
2016-08-13 4:14 ` kokamoto
2016-08-13 5:57 ` kokamoto
2016-08-13 23:02 ` kokamoto
2016-08-19 23:01 ` kokamoto
2016-08-20 17:11 ` cinap_lenrek
2016-07-27 21:18 ` cinap_lenrek
2016-07-27 21:41 ` cinap_lenrek
2016-07-27 21:52 ` cinap_lenrek
2016-07-28 0:44 ` kokamoto
2016-08-06 15:08 kokamoto
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