Re: [9front] core-i5(TypeSNB) and vesa mode

[kokamoto@hera.eonet.ne.jp]

Ok, I returned from vacation.

I hadn't noticed that you posted full version of the diff.

> full diff follows... note that i added rxiir and rximr softregs
> to the Fdi structure. this is because there can be multiple fdi
> links.
> 
> diff -r 7ecc3cd531be sys/src/cmd/aux/vga/igfx.c
> --- a/sys/src/cmd/aux/vga/igfx.c	Sun Jul 24 15:13:14 2016 +0200
> +++ b/sys/src/cmd/aux/vga/igfx.c	Thu Jul 28 14:57:05 2016 +0200

I test this, and it fails.
It shows unstable horizontal color bands only.

Howeveer, when I change the lines like:
	p = &igfx->pipe[x];
	if((p->conf.v & (1<<31)) == 0)
		return;	/* pipe is disabled, done */

	if(p->fdi->rxctl.a != 0){
/* from here */
		if(igfx->type == TypeSNB){	/* K.Okamoto */
			csr(igfx, 0xC6200, 1<<11, 2);	/* pch ref souce & ssc enable */
			sleep(5);
		}
/*  to here */
		p->fdi->rxctl.v &= ~(1<<31);
		p->fdi->rxctl.v &= ~(1<<4);	/* rawclk */
		p->fdi->rxctl.v |= (1<<13);	/* enable pll */
		loadreg(igfx, p->fdi->rxctl);
		sleep(5);
		p->fdi->rxctl.v |= (1<<4);	/* pcdclk */
		loadreg(igfx, p->fdi->rxctl);
		sleep(5);
/* from here */
		if(igfx->type == TypeSNB){	/* K.Okamoto */	
			p->fdi->txctl.v |= (1<<14);	/* enable FDI pll K.Okamoto */
			loadreg(igfx, p->fdi->txctl);
			sleep(5);
		}else{
			p->fdi->txctl.v &= ~(7<<8 | 1);	/* clear auto training bits */
			p->fdi->txctl.v &= ~(1<<31);	/* disable */
			p->fdi->txctl.v |= (1<<14);	/* enable pll */
			loadreg(igfx, p->fdi->txctl);
		sleep(5);
		}
/* to here */
	}

The behaviour is all the same I posted before.
This is the first one after the rest, which means my brain works week.
I'll continue working slowly as usual.

Kenji