[9fans] Plan 9 C compiler for Xtensa CPUs

[9fans] Plan 9 C compiler for Xtensa CPUs

[Cyber Fonic]

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I was reading the post Why Didn't Plan 9 Succeed
<https://news.ycombinator.com/item?id=20527650> on Hacker News.

Made me think that Plan 9 for IoT system of systems could be viable.

To that end, ESP-32 modules look capable enough to run Plan 9, but is there
a Plan 9 C compiler for Xtensa ISA CPUs?

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Rodrigo G. López]

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there is not.

contributions are welcome. :)


-rodri

On Fri, Jul 26, 2019, 8:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:

> I was reading the post Why Didn't Plan 9 Succeed
> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>
> Made me think that Plan 9 for IoT system of systems could be viable.
>
> To that end, ESP-32 modules look capable enough to run Plan 9, but is
> there a Plan 9 C compiler for Xtensa ISA CPUs?
>
>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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I was thinking of doing that since I've got an ESP-32 for some reason

On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:

> I was reading the post Why Didn't Plan 9 Succeed
> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>
> Made me think that Plan 9 for IoT system of systems could be viable.
>
> To that end, ESP-32 modules look capable enough to run Plan 9, but is
> there a Plan 9 C compiler for Xtensa ISA CPUs?
>
>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Rodrigo G. López]

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you are one of the few who could pull that off.
the alternative would be to send the board to cinap, and he'd probably
deploy a compiler+kernel in a couple of weeks.

On Fri, Jul 26, 2019, 12:31 PM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> I was thinking of doing that since I've got an ESP-32 for some reason
>
> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> I was reading the post Why Didn't Plan 9 Succeed
>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>
>> Made me think that Plan 9 for IoT system of systems could be viable.
>>
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>
>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Cyber Fonic]

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Does anybody have any suggestions as to what it would take to create a C
compiler for Xtensa (it is basically a 32 bit sorta-like RISC architecture)?

Since C compilers do exist for Xtensa (both Arduino and ESIF) , is it at
all possible to port Plan 9 C compilers using a "host" compiler as a
semi-bootstrap?

Or would it be more effectively to use an existing Plan 9 system, grab the
sources for a similar compiler, e.g. MIPS and start building a Xtensa /
ESP-32 specific one?

On Fri, 26 Jul 2019 at 20:31, Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> I was thinking of doing that since I've got an ESP-32 for some reason
>
> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> I was reading the post Why Didn't Plan 9 Succeed
>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>
>> Made me think that Plan 9 for IoT system of systems could be viable.
>>
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>
>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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I'd need a letter or number and thought about reusing x (xa/xc/xl) since
the AT&T DSP is long gone

On Fri, Jul 26, 2019 at 11:30 AM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> I was thinking of doing that since I've got an ESP-32 for some reason
>
> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> I was reading the post Why Didn't Plan 9 Succeed
>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>
>> Made me think that Plan 9 for IoT system of systems could be viable.
>>
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>
>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Anthony Martin]

Charles Forsyth <charles.forsyth@gmail.com> once said:
> I'd need a letter or number and thought about reusing x (xa/xc/xl) since
> the AT&T DSP is long gone

https://github.com/0intro/plan9-mips/tree/master/sys/src/cmd/4c
https://github.com/0intro/plan9-mips/blob/master/rc/bin/xc

I think I sent this to the list once before but here's a table that I made
a while back.

https://www.pbrane.org/comp.html

The number 3 is free.

Cheers,
  Anthony

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Richard Miller]

> https://www.pbrane.org/comp.html

I've used .x for riscv32 but it's easily changed.

I see the above list uses .e and .j for riscv and riscv64 -
are these just reserved or are there actual compilers somewhere?

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Anthony Martin]

Richard Miller <9fans@hamnavoe.com> once said:
> I see the above list uses .e and .j for riscv and riscv64 -
> are these just reserved or are there actual compilers somewhere?

No, it was just a suggestion on my part. If I remember correctly,
I thought it was mildly clever that 'e' is the fifth letter in the
English alphabet and 'j' is five letters after that.

I'm only aware of your riscv compiler.

  Anthony

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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I've not previously seen an architecture where so many cache and TLB
control instructions were in the primary space and took up so much of it.


On Fri, Jul 26, 2019 at 11:30 AM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> I was thinking of doing that since I've got an ESP-32 for some reason
>
> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> I was reading the post Why Didn't Plan 9 Succeed
>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>
>> Made me think that Plan 9 for IoT system of systems could be viable.
>>
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>
>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Lucio De Re]

On 8/7/19, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> I've not previously seen an architecture where so many cache and TLB
> control instructions were in the primary space and took up so much of it.
>
I guess the remainder is RISC :-).

Lucio.

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Bakul Shah]

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esp32 doesn’t have an mmu, right?

> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> 
> I was thinking of doing that since I've got an ESP-32 for some reason
> 
>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>> I was reading the post Why Didn't Plan 9 Succeed on Hacker News.
>> 
>> Made me think that Plan 9 for IoT system of systems could be viable.
>> 
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is there a Plan 9 C compiler for Xtensa ISA CPUs? 
>> 

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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The ESP32 has got several MMUs. The characteristics are different depending
on the part that a given MMU accesses (flash, ROM, SRAM, external memory).
Some things are accessed using Memory Protection Units instead, which
control access by Process ID, but don't do mapping. Others including some
of the SRAMs are accessed through
an MMU that can do virtual to physical mapping. The MMUs for internal SRAM0
and 2 choose protection for a given physical page as none, one or all of
PIDs 2 to 7, with the virtual address that
maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
privileged instructions.
A large chunk of SRAM (SRAM 1) has only Memory Protection and no
translation. The external memory MMU is the most general (most
conventional).

On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:

> esp32 doesn’t have an mmu, right?
>
> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
> I was thinking of doing that since I've got an ESP-32 for some reason
>
> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> I was reading the post Why Didn't Plan 9 Succeed
>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>
>> Made me think that Plan 9 for IoT system of systems could be viable.
>>
>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>
>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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The device I've got is ESP32-WROOM-32. None of the boards I've seen that
use it bother with external memory,
so memory is limited, especially the way it's partitioned.

On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> The ESP32 has got several MMUs. The characteristics are different
> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
> memory).
> Some things are accessed using Memory Protection Units instead, which
> control access by Process ID, but don't do mapping. Others including some
> of the SRAMs are accessed through
> an MMU that can do virtual to physical mapping. The MMUs for internal
> SRAM0 and 2 choose protection for a given physical page as none, one or all
> of PIDs 2 to 7, with the virtual address that
> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
> privileged instructions.
> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
> translation. The external memory MMU is the most general (most
> conventional).
>
> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>
>> esp32 doesn’t have an mmu, right?
>>
>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>> I was thinking of doing that since I've got an ESP-32 for some reason
>>
>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>>
>>> I was reading the post Why Didn't Plan 9 Succeed
>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>
>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>
>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>
>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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Since the resources are small if not tiny, a little systems analysis and
design is probably needed, but it looks like a bit of fun, until the
inevitable moment of "why am I here?".

On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> The device I've got is ESP32-WROOM-32. None of the boards I've seen that
> use it bother with external memory,
> so memory is limited, especially the way it's partitioned.
>
> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
>> The ESP32 has got several MMUs. The characteristics are different
>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>> memory).
>> Some things are accessed using Memory Protection Units instead, which
>> control access by Process ID, but don't do mapping. Others including some
>> of the SRAMs are accessed through
>> an MMU that can do virtual to physical mapping. The MMUs for internal
>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>> of PIDs 2 to 7, with the virtual address that
>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>> privileged instructions.
>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>> translation. The external memory MMU is the most general (most
>> conventional).
>>
>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>
>>> esp32 doesn’t have an mmu, right?
>>>
>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>> wrote:
>>>
>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>
>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>> wrote:
>>>
>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>
>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>
>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>>>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>
>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Shane Morris]

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Wireless NinePea perhaps?

https://github.com/echoline/NinePea

On Sat, Aug 10, 2019 at 7:36 AM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> Since the resources are small if not tiny, a little systems analysis and
> design is probably needed, but it looks like a bit of fun, until the
> inevitable moment of "why am I here?".
>
> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
>> The device I've got is ESP32-WROOM-32. None of the boards I've seen that
>> use it bother with external memory,
>> so memory is limited, especially the way it's partitioned.
>>
>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>>> The ESP32 has got several MMUs. The characteristics are different
>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>> memory).
>>> Some things are accessed using Memory Protection Units instead, which
>>> control access by Process ID, but don't do mapping. Others including some
>>> of the SRAMs are accessed through
>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>> of PIDs 2 to 7, with the virtual address that
>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>> privileged instructions.
>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>> translation. The external memory MMU is the most general (most
>>> conventional).
>>>
>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>>
>>>> esp32 doesn’t have an mmu, right?
>>>>
>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>>> wrote:
>>>>
>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>
>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>> wrote:
>>>>
>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>
>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>
>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>>>>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>
>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Bakul Shah]

On Aug 9, 2019, at 2:34 PM, Charles Forsyth <charles.forsyth@gmail.com> wrote:
> 
> Since the resources are small if not tiny, a little systems analysis and design is probably needed, but it looks like a bit of fun, until the inevitable moment of "why am I here?".
> 
> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
> The device I've got is ESP32-WROOM-32. None of the boards I've seen that use it bother with external memory,
> so memory is limited, especially the way it's partitioned.
> 
> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com> wrote:
> The ESP32 has got several MMUs. The characteristics are different depending on the part that a given MMU accesses (flash, ROM, SRAM, external memory).
> Some things are accessed using Memory Protection Units instead, which control access by Process ID, but don't do mapping. Others including some of the SRAMs are accessed through
> an MMU that can do virtual to physical mapping. The MMUs for internal SRAM0 and 2 choose protection for a given physical page as none, one or all of PIDs 2 to 7, with the virtual address that
> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute privileged instructions.
> A large chunk of SRAM (SRAM 1) has only Memory Protection and no translation. The external memory MMU is the most general (most conventional).

Thanks.

Not ideal for plan9 but it would be nice to have access to all its IO capabilities over 9p.

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Skip Tavakkolian]

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I'm not sure if the effort would be worth it; but if you add support for
esp32, I think it would be better for the os to be something like the one
you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9.
Staying with FreeRTOS would need removal of GCC specific things from OS and
dealing with lots of drivers in C++.

The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem more
appropriate for an "embedded" Plan 9.

(*) for those who have not seen it, it is here:
% ls -l /n/sources/contrib/forsyth/avr*
--rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
/n/sources/contrib/forsyth/avr.9gz

On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> Since the resources are small if not tiny, a little systems analysis and
> design is probably needed, but it looks like a bit of fun, until the
> inevitable moment of "why am I here?".
>
> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
>> The device I've got is ESP32-WROOM-32. None of the boards I've seen that
>> use it bother with external memory,
>> so memory is limited, especially the way it's partitioned.
>>
>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>>> The ESP32 has got several MMUs. The characteristics are different
>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>> memory).
>>> Some things are accessed using Memory Protection Units instead, which
>>> control access by Process ID, but don't do mapping. Others including some
>>> of the SRAMs are accessed through
>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>> of PIDs 2 to 7, with the virtual address that
>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>> privileged instructions.
>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>> translation. The external memory MMU is the most general (most
>>> conventional).
>>>
>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>>
>>>> esp32 doesn’t have an mmu, right?
>>>>
>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>>> wrote:
>>>>
>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>
>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>> wrote:
>>>>
>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>
>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>
>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>>>>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>
>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Cyber Fonic]

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The emergent problem with IoT is the lack of security.  From my
understanding of Plan9's architecture. 9p protocol and the "root-less"
security model suggests to me that a Plan9 swarm of IoT devices could be
the "killer app" where Plan9 emerges on the strength of the vision of
decades ago.  Looking at other RT OSes the security models are often bolted
on.  Plan9 worked well on IBM PC era hardware. An ESP-32 has more resources
and better networking than the early PCs.  From my tinkering and reverse
engineering of IoT devices, almost all use 8266 based WiFi and often in
conjunction with a uController. An ESP-32 is dual processor and with
sufficient I/O for most simple tasks.  With IoT, in general, you don't need
a lot of I/O, you simply throw more CPUs into the mix.

On Sat, 10 Aug 2019 at 08:55, Skip Tavakkolian <skip.tavakkolian@gmail.com>
wrote:

> I'm not sure if the effort would be worth it; but if you add support for
> esp32, I think it would be better for the os to be something like the one
> you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9.
> Staying with FreeRTOS would need removal of GCC specific things from OS and
> dealing with lots of drivers in C++.
>
> The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem more
> appropriate for an "embedded" Plan 9.
>
> (*) for those who have not seen it, it is here:
> % ls -l /n/sources/contrib/forsyth/avr*
> --rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
> /n/sources/contrib/forsyth/avr.9gz
>
> On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
>> Since the resources are small if not tiny, a little systems analysis and
>> design is probably needed, but it looks like a bit of fun, until the
>> inevitable moment of "why am I here?".
>>
>> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>>> The device I've got is ESP32-WROOM-32. None of the boards I've seen that
>>> use it bother with external memory,
>>> so memory is limited, especially the way it's partitioned.
>>>
>>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <
>>> charles.forsyth@gmail.com> wrote:
>>>
>>>> The ESP32 has got several MMUs. The characteristics are different
>>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>>> memory).
>>>> Some things are accessed using Memory Protection Units instead, which
>>>> control access by Process ID, but don't do mapping. Others including some
>>>> of the SRAMs are accessed through
>>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>>> of PIDs 2 to 7, with the virtual address that
>>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>>> privileged instructions.
>>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>>> translation. The external memory MMU is the most general (most
>>>> conventional).
>>>>
>>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>>>
>>>>> esp32 doesn’t have an mmu, right?
>>>>>
>>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>>>> wrote:
>>>>>
>>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>>
>>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>>> wrote:
>>>>>
>>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>>
>>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>>
>>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but is
>>>>>> there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>>
>>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Shane Morris]

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Everything old is new again?

On Sat, Aug 10, 2019 at 7:11 PM Cyber Fonic <cyberfonic@gmail.com> wrote:

> The emergent problem with IoT is the lack of security.  From my
> understanding of Plan9's architecture. 9p protocol and the "root-less"
> security model suggests to me that a Plan9 swarm of IoT devices could be
> the "killer app" where Plan9 emerges on the strength of the vision of
> decades ago.  Looking at other RT OSes the security models are often bolted
> on.  Plan9 worked well on IBM PC era hardware. An ESP-32 has more resources
> and better networking than the early PCs.  From my tinkering and reverse
> engineering of IoT devices, almost all use 8266 based WiFi and often in
> conjunction with a uController. An ESP-32 is dual processor and with
> sufficient I/O for most simple tasks.  With IoT, in general, you don't need
> a lot of I/O, you simply throw more CPUs into the mix.
>
> On Sat, 10 Aug 2019 at 08:55, Skip Tavakkolian <skip.tavakkolian@gmail.com>
> wrote:
>
>> I'm not sure if the effort would be worth it; but if you add support for
>> esp32, I think it would be better for the os to be something like the one
>> you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9.
>> Staying with FreeRTOS would need removal of GCC specific things from OS and
>> dealing with lots of drivers in C++.
>>
>> The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem more
>> appropriate for an "embedded" Plan 9.
>>
>> (*) for those who have not seen it, it is here:
>> % ls -l /n/sources/contrib/forsyth/avr*
>> --rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
>> /n/sources/contrib/forsyth/avr.9gz
>>
>> On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>>> Since the resources are small if not tiny, a little systems analysis and
>>> design is probably needed, but it looks like a bit of fun, until the
>>> inevitable moment of "why am I here?".
>>>
>>> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <
>>> charles.forsyth@gmail.com> wrote:
>>>
>>>> The device I've got is ESP32-WROOM-32. None of the boards I've seen
>>>> that use it bother with external memory,
>>>> so memory is limited, especially the way it's partitioned.
>>>>
>>>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <
>>>> charles.forsyth@gmail.com> wrote:
>>>>
>>>>> The ESP32 has got several MMUs. The characteristics are different
>>>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>>>> memory).
>>>>> Some things are accessed using Memory Protection Units instead, which
>>>>> control access by Process ID, but don't do mapping. Others including some
>>>>> of the SRAMs are accessed through
>>>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>>>> of PIDs 2 to 7, with the virtual address that
>>>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>>>> privileged instructions.
>>>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>>>> translation. The external memory MMU is the most general (most
>>>>> conventional).
>>>>>
>>>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>>>>
>>>>>> esp32 doesn’t have an mmu, right?
>>>>>>
>>>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>>>
>>>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>>>
>>>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>>>
>>>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but
>>>>>>> is there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>>>
>>>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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At a glance it looked as though the MMUs for the on-chip stuff were more
suitable for Unix Seventh Edition (no later) than "full" Plan 9.
The MMU for the external memory looked fine, but as I said, the device I've
got, and several other boards based on WROOM seem not
to bother with external memory. I didn't look widely, though.

The processor is adequate, I think, but double == float (there's only
single precision).

The existing systems use one processor for applications, and the other
mainly for communications.

I haven't had a lot of spare time, but I did the assembler and am about 3/4
through the loader.
For the most part it's a straightforward RISC.
Might do the disassembler next to help debug the rest, and finally the
compiler.

On Sat, Aug 10, 2019 at 10:11 AM Cyber Fonic <cyberfonic@gmail.com> wrote:

> The emergent problem with IoT is the lack of security.  From my
> understanding of Plan9's architecture. 9p protocol and the "root-less"
> security model suggests to me that a Plan9 swarm of IoT devices could be
> the "killer app" where Plan9 emerges on the strength of the vision of
> decades ago.  Looking at other RT OSes the security models are often bolted
> on.  Plan9 worked well on IBM PC era hardware. An ESP-32 has more resources
> and better networking than the early PCs.  From my tinkering and reverse
> engineering of IoT devices, almost all use 8266 based WiFi and often in
> conjunction with a uController. An ESP-32 is dual processor and with
> sufficient I/O for most simple tasks.  With IoT, in general, you don't need
> a lot of I/O, you simply throw more CPUs into the mix.
>
> On Sat, 10 Aug 2019 at 08:55, Skip Tavakkolian <skip.tavakkolian@gmail.com>
> wrote:
>
>> I'm not sure if the effort would be worth it; but if you add support for
>> esp32, I think it would be better for the os to be something like the one
>> you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9.
>> Staying with FreeRTOS would need removal of GCC specific things from OS and
>> dealing with lots of drivers in C++.
>>
>> The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem more
>> appropriate for an "embedded" Plan 9.
>>
>> (*) for those who have not seen it, it is here:
>> % ls -l /n/sources/contrib/forsyth/avr*
>> --rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
>> /n/sources/contrib/forsyth/avr.9gz
>>
>> On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <charles.forsyth@gmail.com>
>> wrote:
>>
>>> Since the resources are small if not tiny, a little systems analysis and
>>> design is probably needed, but it looks like a bit of fun, until the
>>> inevitable moment of "why am I here?".
>>>
>>> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <
>>> charles.forsyth@gmail.com> wrote:
>>>
>>>> The device I've got is ESP32-WROOM-32. None of the boards I've seen
>>>> that use it bother with external memory,
>>>> so memory is limited, especially the way it's partitioned.
>>>>
>>>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <
>>>> charles.forsyth@gmail.com> wrote:
>>>>
>>>>> The ESP32 has got several MMUs. The characteristics are different
>>>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>>>> memory).
>>>>> Some things are accessed using Memory Protection Units instead, which
>>>>> control access by Process ID, but don't do mapping. Others including some
>>>>> of the SRAMs are accessed through
>>>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>>>> of PIDs 2 to 7, with the virtual address that
>>>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>>>> privileged instructions.
>>>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>>>> translation. The external memory MMU is the most general (most
>>>>> conventional).
>>>>>
>>>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com> wrote:
>>>>>
>>>>>> esp32 doesn’t have an mmu, right?
>>>>>>
>>>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <charles.forsyth@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>>>
>>>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>>>> wrote:
>>>>>>
>>>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>>>
>>>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>>>
>>>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but
>>>>>>> is there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>>>
>>>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Lyndon Nerenberg]

Charles Forsyth writes:

> At a glance it looked as though the MMUs for the on-chip stuff were more
> suitable for Unix Seventh Edition (no later) than "full" Plan 9.

Wouldn't Inferno be a better fit for these sort of devices?

In my experience these things are used primarily as I/O devices,
with most of the CPU cycles going towards reducing/normalizing/marshalling
the data in and out.  Nothing I've ever built out of an ESP*,
Feather, Teensy, etc., would benefit from a full-on Plan9 kernel.

But having a fully-integrated 9P+auth stack would make these
microcontrollers a dream to integrate into a Plan9 environment.

--lyndon

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Charles Forsyth]

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There is another existing variant of ESP32 with flash and RAM, and that one
would provide the external memory MMU.
It seems there could be a range from a small RT-ish kernel, with and
without a user mode, on little ESP32, to a Plan 9 kernel with a few
specialised processes on the bigger one.
An Inferno-like system might also straddle the boundaries.

On Sat, Aug 10, 2019 at 5:18 PM Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> At a glance it looked as though the MMUs for the on-chip stuff were more
> suitable for Unix Seventh Edition (no later) than "full" Plan 9.
> The MMU for the external memory looked fine, but as I said, the device
> I've got, and several other boards based on WROOM seem not
> to bother with external memory. I didn't look widely, though.
>
> The processor is adequate, I think, but double == float (there's only
> single precision).
>
> The existing systems use one processor for applications, and the other
> mainly for communications.
>
> I haven't had a lot of spare time, but I did the assembler and am about
> 3/4 through the loader.
> For the most part it's a straightforward RISC.
> Might do the disassembler next to help debug the rest, and finally the
> compiler.
>
> On Sat, Aug 10, 2019 at 10:11 AM Cyber Fonic <cyberfonic@gmail.com> wrote:
>
>> The emergent problem with IoT is the lack of security.  From my
>> understanding of Plan9's architecture. 9p protocol and the "root-less"
>> security model suggests to me that a Plan9 swarm of IoT devices could be
>> the "killer app" where Plan9 emerges on the strength of the vision of
>> decades ago.  Looking at other RT OSes the security models are often bolted
>> on.  Plan9 worked well on IBM PC era hardware. An ESP-32 has more resources
>> and better networking than the early PCs.  From my tinkering and reverse
>> engineering of IoT devices, almost all use 8266 based WiFi and often in
>> conjunction with a uController. An ESP-32 is dual processor and with
>> sufficient I/O for most simple tasks.  With IoT, in general, you don't need
>> a lot of I/O, you simply throw more CPUs into the mix.
>>
>> On Sat, 10 Aug 2019 at 08:55, Skip Tavakkolian <
>> skip.tavakkolian@gmail.com> wrote:
>>
>>> I'm not sure if the effort would be worth it; but if you add support for
>>> esp32, I think it would be better for the os to be something like the one
>>> you had in kencc for AVR (*) or possibly Russ' libtask, rather than Plan 9.
>>> Staying with FreeRTOS would need removal of GCC specific things from OS and
>>> dealing with lots of drivers in C++.
>>>
>>> The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem
>>> more appropriate for an "embedded" Plan 9.
>>>
>>> (*) for those who have not seen it, it is here:
>>> % ls -l /n/sources/contrib/forsyth/avr*
>>> --rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
>>> /n/sources/contrib/forsyth/avr.9gz
>>>
>>> On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <
>>> charles.forsyth@gmail.com> wrote:
>>>
>>>> Since the resources are small if not tiny, a little systems analysis
>>>> and design is probably needed, but it looks like a bit of fun, until the
>>>> inevitable moment of "why am I here?".
>>>>
>>>> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <
>>>> charles.forsyth@gmail.com> wrote:
>>>>
>>>>> The device I've got is ESP32-WROOM-32. None of the boards I've seen
>>>>> that use it bother with external memory,
>>>>> so memory is limited, especially the way it's partitioned.
>>>>>
>>>>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <
>>>>> charles.forsyth@gmail.com> wrote:
>>>>>
>>>>>> The ESP32 has got several MMUs. The characteristics are different
>>>>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>>>>> memory).
>>>>>> Some things are accessed using Memory Protection Units instead, which
>>>>>> control access by Process ID, but don't do mapping. Others including some
>>>>>> of the SRAMs are accessed through
>>>>>> an MMU that can do virtual to physical mapping. The MMUs for internal
>>>>>> SRAM0 and 2 choose protection for a given physical page as none, one or all
>>>>>> of PIDs 2 to 7, with the virtual address that
>>>>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>>>>> privileged instructions.
>>>>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>>>>> translation. The external memory MMU is the most general (most
>>>>>> conventional).
>>>>>>
>>>>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com>
>>>>>> wrote:
>>>>>>
>>>>>>> esp32 doesn’t have an mmu, right?
>>>>>>>
>>>>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <
>>>>>>> charles.forsyth@gmail.com> wrote:
>>>>>>>
>>>>>>> I was thinking of doing that since I've got an ESP-32 for some reason
>>>>>>>
>>>>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>>>>
>>>>>>>> Made me think that Plan 9 for IoT system of systems could be viable.
>>>>>>>>
>>>>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but
>>>>>>>> is there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>>>>
>>>>>>>>

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Richard Miller]

Charles Forsyth <charles.forsyth@gmail.com:
> I haven't had a lot of spare time, but I did the assembler and am about
> 3/4 through the loader.
> For the most part it's a straightforward RISC.
> Might do the disassembler next to help debug the rest, and finally the
> compiler.

Nowadays I do the disassembler first.  Advantages: (a) useful tool for
debugging the assembler and loader; (b) disassembling binaries produced
by some other toolchain provides a useful check for my understanding of
the instruction encoding.

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Cyber Fonic]

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For IoT deployments, I suppose that one processor core on the ESP32 could
run the WiFi / networking stack and the other act as a CPU-like server and
thus run a small number of servers to expose the interface(s) in a 9P
mountable fashion to more powerful nodes.  A RT-ish kernel might suffice in
most practical use cases - it is IoT after all.  In my vision for Plan9 IoT
I never considered running file-server or terminal server on ESP-32
hardware. There are more capable nodes which would be better suited for
those purposes.  Of course, these observations presume that the 9p protocol
provides sufficient security against any ESP-32 node going rogue for
whatever reason.

It has been said :  "The 'S' in IoT stands for security".  If Plan9 can
address that deficiency of the current state of the art for IoT devices,
then it would be a worthwhile exercise.

On Mon, 19 Aug 2019 at 00:12, Charles Forsyth <charles.forsyth@gmail.com>
wrote:

> There is another existing variant of ESP32 with flash and RAM, and that
> one would provide the external memory MMU.
> It seems there could be a range from a small RT-ish kernel, with and
> without a user mode, on little ESP32, to a Plan 9 kernel with a few
> specialised processes on the bigger one.
> An Inferno-like system might also straddle the boundaries.
>
> On Sat, Aug 10, 2019 at 5:18 PM Charles Forsyth <charles.forsyth@gmail.com>
> wrote:
>
>> At a glance it looked as though the MMUs for the on-chip stuff were more
>> suitable for Unix Seventh Edition (no later) than "full" Plan 9.
>> The MMU for the external memory looked fine, but as I said, the device
>> I've got, and several other boards based on WROOM seem not
>> to bother with external memory. I didn't look widely, though.
>>
>> The processor is adequate, I think, but double == float (there's only
>> single precision).
>>
>> The existing systems use one processor for applications, and the other
>> mainly for communications.
>>
>> I haven't had a lot of spare time, but I did the assembler and am about
>> 3/4 through the loader.
>> For the most part it's a straightforward RISC.
>> Might do the disassembler next to help debug the rest, and finally the
>> compiler.
>>
>> On Sat, Aug 10, 2019 at 10:11 AM Cyber Fonic <cyberfonic@gmail.com>
>> wrote:
>>
>>> The emergent problem with IoT is the lack of security.  From my
>>> understanding of Plan9's architecture. 9p protocol and the "root-less"
>>> security model suggests to me that a Plan9 swarm of IoT devices could be
>>> the "killer app" where Plan9 emerges on the strength of the vision of
>>> decades ago.  Looking at other RT OSes the security models are often bolted
>>> on.  Plan9 worked well on IBM PC era hardware. An ESP-32 has more resources
>>> and better networking than the early PCs.  From my tinkering and reverse
>>> engineering of IoT devices, almost all use 8266 based WiFi and often in
>>> conjunction with a uController. An ESP-32 is dual processor and with
>>> sufficient I/O for most simple tasks.  With IoT, in general, you don't need
>>> a lot of I/O, you simply throw more CPUs into the mix.
>>>
>>> On Sat, 10 Aug 2019 at 08:55, Skip Tavakkolian <
>>> skip.tavakkolian@gmail.com> wrote:
>>>
>>>> I'm not sure if the effort would be worth it; but if you add support
>>>> for esp32, I think it would be better for the os to be something like the
>>>> one you had in kencc for AVR (*) or possibly Russ' libtask, rather than
>>>> Plan 9. Staying with FreeRTOS would need removal of GCC specific things
>>>> from OS and dealing with lots of drivers in C++.
>>>>
>>>> The Cortex-M based mpus (e.g. Teensy 4 with Cortex M7 @ 600MHz) seem
>>>> more appropriate for an "embedded" Plan 9.
>>>>
>>>> (*) for those who have not seen it, it is here:
>>>> % ls -l /n/sources/contrib/forsyth/avr*
>>>> --rw-rw-r-- M 518 bootes sys 251227 Sep  4  2011
>>>> /n/sources/contrib/forsyth/avr.9gz
>>>>
>>>> On Fri, Aug 9, 2019 at 2:36 PM Charles Forsyth <
>>>> charles.forsyth@gmail.com> wrote:
>>>>
>>>>> Since the resources are small if not tiny, a little systems analysis
>>>>> and design is probably needed, but it looks like a bit of fun, until the
>>>>> inevitable moment of "why am I here?".
>>>>>
>>>>> On Fri, Aug 9, 2019 at 4:50 PM Charles Forsyth <
>>>>> charles.forsyth@gmail.com> wrote:
>>>>>
>>>>>> The device I've got is ESP32-WROOM-32. None of the boards I've seen
>>>>>> that use it bother with external memory,
>>>>>> so memory is limited, especially the way it's partitioned.
>>>>>>
>>>>>> On Fri, Aug 9, 2019 at 3:50 PM Charles Forsyth <
>>>>>> charles.forsyth@gmail.com> wrote:
>>>>>>
>>>>>>> The ESP32 has got several MMUs. The characteristics are different
>>>>>>> depending on the part that a given MMU accesses (flash, ROM, SRAM, external
>>>>>>> memory).
>>>>>>> Some things are accessed using Memory Protection Units instead,
>>>>>>> which control access by Process ID, but don't do mapping. Others including
>>>>>>> some of the SRAMs are accessed through
>>>>>>> an MMU that can do virtual to physical mapping. The MMUs for
>>>>>>> internal SRAM0 and 2 choose protection for a given physical page as none,
>>>>>>> one or all of PIDs 2 to 7, with the virtual address that
>>>>>>> maps to it. PIDs 0 and 1 can access everything. PID 0 can execute
>>>>>>> privileged instructions.
>>>>>>> A large chunk of SRAM (SRAM 1) has only Memory Protection and no
>>>>>>> translation. The external memory MMU is the most general (most
>>>>>>> conventional).
>>>>>>>
>>>>>>> On Fri, Aug 9, 2019 at 3:19 PM Bakul Shah <bakul@bitblocks.com>
>>>>>>> wrote:
>>>>>>>
>>>>>>>> esp32 doesn’t have an mmu, right?
>>>>>>>>
>>>>>>>> On Jul 26, 2019, at 03:30, Charles Forsyth <
>>>>>>>> charles.forsyth@gmail.com> wrote:
>>>>>>>>
>>>>>>>> I was thinking of doing that since I've got an ESP-32 for some
>>>>>>>> reason
>>>>>>>>
>>>>>>>> On Fri, Jul 26, 2019 at 7:38 AM Cyber Fonic <cyberfonic@gmail.com>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>>> I was reading the post Why Didn't Plan 9 Succeed
>>>>>>>>> <https://news.ycombinator.com/item?id=20527650> on Hacker News.
>>>>>>>>>
>>>>>>>>> Made me think that Plan 9 for IoT system of systems could be
>>>>>>>>> viable.
>>>>>>>>>
>>>>>>>>> To that end, ESP-32 modules look capable enough to run Plan 9, but
>>>>>>>>> is there a Plan 9 C compiler for Xtensa ISA CPUs?
>>>>>>>>>
>>>>>>>>>

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[9fans] Plan 9 security

[Ethan Gardener]

On Mon, Aug 19, 2019, at 12:53 PM, Cyber Fonic wrote:
>
> It has been said : "The 'S' in IoT stands for security". If Plan9 can address that deficiency of the current state of the art for IoT devices, then it would be a worthwhile exercise.

Plan 9 may have a decent security model, but it's never been audited.  Auditing a codebase, even one as small as Plan 9's, is a lot of work.  Are you willing to make a start on it?

If you want something free and already audited, with more security features, (but perhaps not quite the same convenience,) look into OpenBSD.

--
I love that *Open*BSD is so *security*-focused!

Re: [9fans] Plan 9 security

[Cyber Fonic]

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I don't think OpenBSD will run on an ESP-32.  That is part of the problem
with IoT, the nodes are made on the cheap and thus use the cheapest viable
network capable device.

On Tue, 20 Aug 2019 at 00:54, Ethan Gardener <eekee57@fastmail.fm> wrote:

> On Mon, Aug 19, 2019, at 12:53 PM, Cyber Fonic wrote:
> >
> > It has been said : "The 'S' in IoT stands for security". If Plan9 can
> address that deficiency of the current state of the art for IoT devices,
> then it would be a worthwhile exercise.
>
> Plan 9 may have a decent security model, but it's never been audited.
> Auditing a codebase, even one as small as Plan 9's, is a lot of work.  Are
> you willing to make a start on it?
>
> If you want something free and already audited, with more security
> features, (but perhaps not quite the same convenience,) look into OpenBSD.
>
> --
> I love that *Open*BSD is so *security*-focused!
>
>

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Re: [9fans] Plan 9 security

[Don A. Bailey]

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Fwiw Plan 9’s code vase has indeed been audited. By me. Several exploitable bugs were found including a kernel exploit due to the env driver. I wrote a working PoC for it which is somewhere on the internet, but it’s quite old.

Much of the code hasn’t changed, and, I would suspect, is largely secure.

But you’re talking implementation security versus architectural security. In the case of IoT, Plan 9 does exceptional things to close the gaps that embedded systems supply its users, but it is nowhere near complete.

Notably, a trusted root environment needs to be added - which Plan 9 only slightly addresses. 

Best,
D

> On Aug 20, 2019, at 9:13 AM, Cyber Fonic <cyberfonic@gmail.com> wrote:
> 
> I don't think OpenBSD will run on an ESP-32.  That is part of the problem with IoT, the nodes are made on the cheap and thus use the cheapest viable network capable device.
> 
>> On Tue, 20 Aug 2019 at 00:54, Ethan Gardener <eekee57@fastmail.fm> wrote:
>> On Mon, Aug 19, 2019, at 12:53 PM, Cyber Fonic wrote:
>> > 
>> > It has been said : "The 'S' in IoT stands for security". If Plan9 can address that deficiency of the current state of the art for IoT devices, then it would be a worthwhile exercise.
>> 
>> Plan 9 may have a decent security model, but it's never been audited.  Auditing a codebase, even one as small as Plan 9's, is a lot of work.  Are you willing to make a start on it?
>> 
>> If you want something free and already audited, with more security features, (but perhaps not quite the same convenience,) look into OpenBSD.
>> 
>> -- 
>> I love that *Open*BSD is so *security*-focused!
>> 

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Re: [9fans] Plan 9 security

[Ethan Gardener]

On Tue, Aug 20, 2019, at 2:29 PM, Don A. Bailey wrote:
> 
> Fwiw Plan 9’s code vase has indeed been audited. By me. Several exploitable bugs were found including a kernel exploit due to the env driver. I wrote a working PoC for it which is somewhere on the internet, but it’s quite old.

My apologies!

> Much of the code hasn’t changed, and, I would suspect, is largely secure.

Good to know. :)

I wonder how many relevant parts have changed in 9front?  There are regular kernel changes, some of which were made to handle the heavy shell-script load of running werc sites.  (For a short time, the load on cat-v.org was very heavy.)

> But you’re talking implementation security versus architectural security. In the case of IoT, Plan 9 does exceptional things to close the gaps that embedded systems supply its users, but it is nowhere near complete.

I guess I am, and yes, Plan 9 is sadly incomplete in many areas.  

Re: [9fans] Plan 9 security

[Don Bailey]

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On Fri, Aug 23, 2019 at 12:47 PM Ethan Gardener <eekee57@fastmail.fm> wrote:

> On Tue, Aug 20, 2019, at 2:29 PM, Don A. Bailey wrote:
> >
> > Fwiw Plan 9’s code vase has indeed been audited. By me. Several
> exploitable bugs were found including a kernel exploit due to the env
> driver. I wrote a working PoC for it which is somewhere on the internet,
> but it’s quite old.
>
> My apologies!
>

No apologies necessary, you didn't know.


>
> > Much of the code hasn’t changed, and, I would suspect, is largely secure.
>
> Good to know. :)
>
> I wonder how many relevant parts have changed in 9front?  There are
> regular kernel changes, some of which were made to handle the heavy
> shell-script load of running werc sites.  (For a short time, the load on
> cat-v.org was very heavy.)
>
>
A delta audit would be useful and might be fun. I don't think I have the
time, currently, but I wouldn't mind to get back into it.


> > But you’re talking implementation security versus architectural
> security. In the case of IoT, Plan 9 does exceptional things to close the
> gaps that embedded systems supply its users, but it is nowhere near
> complete.
>
> I guess I am, and yes, Plan 9 is sadly incomplete in many areas.
>

I don't think it's sadly incomplete. Plan 9 is awesome. However, it isn't
really Plan 9's job to address silicon security and hardware trust. Some
integrations could be made into the kernel authentication stack and the
Secure Store et. al., but that is a gap easily closed. The hard part is
choosing cost effective hardware that does the job. The Linux BIOS team
(Ron and Pals) have done a great job of getting closer to The Source, but
that isn't really something an OS should address. That's more of a
firmware/BIOS/CPU thing.

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Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[cinap_lenrek]

nope. charles is your man.

--
cinap

Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[David Boddie]

On Sat, 10 Aug 2019 16:18:16 +0000, Charles Forsyth wrote:

> I haven't had a lot of spare time, but I did the assembler and am about 
> 3/4
> through the loader.
> For the most part it's a straightforward RISC.
> Might do the disassembler next to help debug the rest, and finally the
> compiler.

Did you get any further with this? I'm interested in attempting a port
of Inferno to an ESP32 board I've just picked up.
Learning the instruction set is going to be interesting.

David

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